drivers/gpu/drm/nouveau/include/nvif/cl0080.h

   1 /* SPDX-License-Identifier: MIT */
   2 #ifndef __NVIF_CL0080_H__
   3 #define __NVIF_CL0080_H__
   4
   5 struct nv_device_v0 {
   6         __u8  version;
   7         __u8  priv;
   8         __u8  pad02[6];
   9         __u64 device;   /* device identifier, ~0 for client default */
  10 };
  11
  12 #define NV_DEVICE_V0_INFO                                                  0x00
  13 #define NV_DEVICE_V0_TIME                                                  0x01
  14
  15 struct nv_device_info_v0 {
  16         __u8  version;
  17 #define NV_DEVICE_INFO_V0_IGP                                              0x00
  18 #define NV_DEVICE_INFO_V0_PCI                                              0x01
  19 #define NV_DEVICE_INFO_V0_AGP                                              0x02
  20 #define NV_DEVICE_INFO_V0_PCIE                                             0x03
  21 #define NV_DEVICE_INFO_V0_SOC                                              0x04
  22         __u8  platform;
  23         __u16 chipset;  /* from NV_PMC_BOOT_0 */
  24         __u8  revision; /* from NV_PMC_BOOT_0 */
  25 #define NV_DEVICE_INFO_V0_TNT                                              0x01
  26 #define NV_DEVICE_INFO_V0_CELSIUS                                          0x02
  27 #define NV_DEVICE_INFO_V0_KELVIN                                           0x03
  28 #define NV_DEVICE_INFO_V0_RANKINE                                          0x04
  29 #define NV_DEVICE_INFO_V0_CURIE                                            0x05
  30 #define NV_DEVICE_INFO_V0_TESLA                                            0x06
  31 #define NV_DEVICE_INFO_V0_FERMI                                            0x07
  32 #define NV_DEVICE_INFO_V0_KEPLER                                           0x08
  33 #define NV_DEVICE_INFO_V0_MAXWELL                                          0x09
  34 #define NV_DEVICE_INFO_V0_PASCAL                                           0x0a
  35 #define NV_DEVICE_INFO_V0_VOLTA                                            0x0b
  36 #define NV_DEVICE_INFO_V0_TURING                                           0x0c
  37 #define NV_DEVICE_INFO_V0_AMPERE                                           0x0d
  38         __u8  family;
  39         __u8  pad06[2];
  40         __u64 ram_size;
  41         __u64 ram_user;
  42         char  chip[16];
  43         char  name[64];
  44 };
  45
  46 struct nv_device_info_v1 {
  47         __u8  version;
  48         __u8  count;
  49         __u8  pad02[6];
  50         struct nv_device_info_v1_data {
  51                 __u64 mthd; /* NV_DEVICE_INFO_* (see below). */
  52                 __u64 data;
  53         } data[];
  54 };
  55
  56 struct nv_device_time_v0 {
  57         __u8  version;
  58         __u8  pad01[7];
  59         __u64 time;
  60 };
  61
  62 #define NV_DEVICE_INFO_UNIT                               (0xffffffffULL << 32)
  63 #define NV_DEVICE_INFO(n)                          ((n) | (0x00000000ULL << 32))
  64 #define NV_DEVICE_HOST(n)                          ((n) | (0x00000001ULL << 32))
  65
  66 /* This will be returned in the mthd field for unsupported queries. */
  67 #define NV_DEVICE_INFO_INVALID                                           ~0ULL
  68
  69 /* Returns the number of available runlists. */
  70 #define NV_DEVICE_HOST_RUNLISTS                       NV_DEVICE_HOST(0x00000000)
  71 /* Returns the number of available channels. */
  72 #define NV_DEVICE_HOST_CHANNELS                       NV_DEVICE_HOST(0x00000001)
  73
  74 /* Returns a mask of available engine types on runlist(data). */
  75 #define NV_DEVICE_HOST_RUNLIST_ENGINES                NV_DEVICE_HOST(0x00000100)
  76 #define NV_DEVICE_HOST_RUNLIST_ENGINES_SW                            0x00000001
  77 #define NV_DEVICE_HOST_RUNLIST_ENGINES_GR                            0x00000002
  78 #define NV_DEVICE_HOST_RUNLIST_ENGINES_MPEG                          0x00000004
  79 #define NV_DEVICE_HOST_RUNLIST_ENGINES_ME                            0x00000008
  80 #define NV_DEVICE_HOST_RUNLIST_ENGINES_CIPHER                        0x00000010
  81 #define NV_DEVICE_HOST_RUNLIST_ENGINES_BSP                           0x00000020
  82 #define NV_DEVICE_HOST_RUNLIST_ENGINES_VP                            0x00000040
  83 #define NV_DEVICE_HOST_RUNLIST_ENGINES_CE                            0x00000080
  84 #define NV_DEVICE_HOST_RUNLIST_ENGINES_SEC                           0x00000100
  85 #define NV_DEVICE_HOST_RUNLIST_ENGINES_MSVLD                         0x00000200
  86 #define NV_DEVICE_HOST_RUNLIST_ENGINES_MSPDEC                        0x00000400
  87 #define NV_DEVICE_HOST_RUNLIST_ENGINES_MSPPP                         0x00000800
  88 #define NV_DEVICE_HOST_RUNLIST_ENGINES_MSENC                         0x00001000
  89 #define NV_DEVICE_HOST_RUNLIST_ENGINES_VIC                           0x00002000
  90 #define NV_DEVICE_HOST_RUNLIST_ENGINES_SEC2                          0x00004000
  91 #define NV_DEVICE_HOST_RUNLIST_ENGINES_NVDEC                         0x00008000
  92 #define NV_DEVICE_HOST_RUNLIST_ENGINES_NVENC                         0x00010000
  93 #endif