drivers/gpu/drm/nouveau/dispnv50/headc37d.c

   1 /*
   2  * Copyright 2018 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22 #include "head.h"
  23 #include "atom.h"
  24 #include "core.h"
  25
  26 #include <nvif/pushc37b.h>
  27
  28 static int
  29 headc37d_or(struct nv50_head *head, struct nv50_head_atom *asyh)
  30 {
  31         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
  32         const int i = head->base.index;
  33         u8 depth;
  34         int ret;
  35
  36         /*XXX: This is a dirty hack until OR depth handling is
  37          *     improved later for deep colour etc.
  38          */
  39         switch (asyh->or.depth) {
  40         case 6: depth = 5; break;
  41         case 5: depth = 4; break;
  42         case 2: depth = 1; break;
  43         case 0: depth = 4; break;
  44         default:
  45                 depth = asyh->or.depth;
  46                 WARN_ON(1);
  47                 break;
  48         }
  49
  50         if ((ret = PUSH_WAIT(push, 2)))
  51                 return ret;
  52
  53         PUSH_NVSQ(push, NVC37D, 0x2004 + (i * 0x400), depth << 4 |
  54                                                       asyh->or.nvsync << 3 |
  55                                                       asyh->or.nhsync << 2 |
  56                                                       asyh->or.crc_raster);
  57         return 0;
  58 }
  59
  60 static int
  61 headc37d_procamp(struct nv50_head *head, struct nv50_head_atom *asyh)
  62 {
  63         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
  64         const int i = head->base.index;
  65         int ret;
  66
  67         if ((ret = PUSH_WAIT(push, 2)))
  68                 return ret;
  69
  70         PUSH_NVSQ(push, NVC37D, 0x2000 + (i * 0x400), 0x80000000 |
  71                                                       asyh->procamp.sat.sin << 16 |
  72                                                       asyh->procamp.sat.cos << 4);
  73         return 0;
  74 }
  75
  76 int
  77 headc37d_dither(struct nv50_head *head, struct nv50_head_atom *asyh)
  78 {
  79         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
  80         const int i = head->base.index;
  81         int ret;
  82
  83         if ((ret = PUSH_WAIT(push, 2)))
  84                 return ret;
  85
  86         PUSH_NVSQ(push, NV907D, 0x2018 + (i * 0x400), asyh->dither.mode << 8 |
  87                                                       asyh->dither.bits << 4 |
  88                                                       asyh->dither.enable);
  89         return 0;
  90 }
  91
  92 int
  93 headc37d_curs_clr(struct nv50_head *head)
  94 {
  95         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
  96         const int i = head->base.index;
  97         int ret;
  98
  99         if ((ret = PUSH_WAIT(push, 4)))
 100                 return ret;
 101
 102         PUSH_NVSQ(push, NVC37D, 0x209c + (i * 0x400), 0x000000cf);
 103         PUSH_NVSQ(push, NVC37D, 0x2088 + (i * 0x400), 0x00000000);
 104         return 0;
 105 }
 106
 107 int
 108 headc37d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh)
 109 {
 110         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
 111         const int i = head->base.index;
 112         int ret;
 113
 114         if ((ret = PUSH_WAIT(push, 7)))
 115                 return ret;
 116
 117         PUSH_NVSQ(push, NVC37D, 0x209c + (i * 0x400), 0x80000000 |
 118                                                       asyh->curs.layout << 8 |
 119                                                       asyh->curs.format << 0,
 120                                 0x20a0 + (i * 0x400), 0x000072ff);
 121         PUSH_NVSQ(push, NVC37D, 0x2088 + (i * 0x400), asyh->curs.handle);
 122         PUSH_NVSQ(push, NVC37D, 0x2090 + (i * 0x400), asyh->curs.offset >> 8);
 123         return 0;
 124 }
 125
 126 int
 127 headc37d_curs_format(struct nv50_head *head, struct nv50_wndw_atom *asyw,
 128                      struct nv50_head_atom *asyh)
 129 {
 130         asyh->curs.format = asyw->image.format;
 131         return 0;
 132 }
 133
 134 static int
 135 headc37d_olut_clr(struct nv50_head *head)
 136 {
 137         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
 138         const int i = head->base.index;
 139         int ret;
 140
 141         if ((ret = PUSH_WAIT(push, 2)))
 142                 return ret;
 143
 144         PUSH_NVSQ(push, NVC37D, 0x20ac + (i * 0x400), 0x00000000);
 145         return 0;
 146 }
 147
 148 static int
 149 headc37d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh)
 150 {
 151         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
 152         const int i = head->base.index;
 153         int ret;
 154
 155         if ((ret = PUSH_WAIT(push, 4)))
 156                 return ret;
 157
 158         PUSH_NVSQ(push, NVC37D, 0x20a4 + (i * 0x400), asyh->olut.output_mode << 8 |
 159                                                       asyh->olut.range << 4 |
 160                                                       asyh->olut.size,
 161                                 0x20a8 + (i * 0x400), asyh->olut.offset >> 8,
 162                                 0x20ac + (i * 0x400), asyh->olut.handle);
 163         return 0;
 164 }
 165
 166 static bool
 167 headc37d_olut(struct nv50_head *head, struct nv50_head_atom *asyh, int size)
 168 {
 169         if (size != 256 && size != 1024)
 170                 return false;
 171
 172         asyh->olut.mode = 2;
 173         asyh->olut.size = size == 1024 ? 2 : 0;
 174         asyh->olut.range = 0;
 175         asyh->olut.output_mode = 1;
 176         asyh->olut.load = head907d_olut_load;
 177         return true;
 178 }
 179
 180 static int
 181 headc37d_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
 182 {
 183         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
 184         struct nv50_head_mode *m = &asyh->mode;
 185         const int i = head->base.index;
 186         int ret;
 187
 188         if ((ret = PUSH_WAIT(push, 13)))
 189                 return ret;
 190
 191         PUSH_NVSQ(push, NVC37D, 0x2064 + (i * 0x400), m->v.active  << 16 | m->h.active,
 192                                 0x2068 + (i * 0x400), m->v.synce   << 16 | m->h.synce,
 193                                 0x206c + (i * 0x400), m->v.blanke  << 16 | m->h.blanke,
 194                                 0x2070 + (i * 0x400), m->v.blanks  << 16 | m->h.blanks,
 195                                 0x2074 + (i * 0x400), m->v.blank2e << 16 | m->v.blank2s);
 196         PUSH_NVSQ(push, NVC37D, 0x2008 + (i * 0x400), m->interlace,
 197                                 0x200c + (i * 0x400), m->clock * 1000);
 198         PUSH_NVSQ(push, NVC37D, 0x2028 + (i * 0x400), m->clock * 1000);
 199
 200         /*XXX: HEAD_USAGE_BOUNDS, doesn't belong here. */
 201         PUSH_NVSQ(push, NVC37D, 0x2030 + (i * 0x400), 0x00000124);
 202         return 0;
 203 }
 204
 205 int
 206 headc37d_view(struct nv50_head *head, struct nv50_head_atom *asyh)
 207 {
 208         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
 209         const int i = head->base.index;
 210         int ret;
 211
 212         if ((ret = PUSH_WAIT(push, 4)))
 213                 return ret;
 214
 215         PUSH_NVSQ(push, NVC37D, 0x204c + (i * 0x400), asyh->view.iH << 16 | asyh->view.iW);
 216         PUSH_NVSQ(push, NVC37D, 0x2058 + (i * 0x400), asyh->view.oH << 16 | asyh->view.oW);
 217         return 0;
 218 }
 219
 220 void
 221 headc37d_static_wndw_map(struct nv50_head *head, struct nv50_head_atom *asyh)
 222 {
 223         int i, end;
 224
 225         for (i = head->base.index * 2, end = i + 2; i < end; i++)
 226                 asyh->wndw.owned |= BIT(i);
 227 }
 228
 229 const struct nv50_head_func
 230 headc37d = {
 231         .view = headc37d_view,
 232         .mode = headc37d_mode,
 233         .olut = headc37d_olut,
 234         .olut_size = 1024,
 235         .olut_set = headc37d_olut_set,
 236         .olut_clr = headc37d_olut_clr,
 237         .curs_layout = head917d_curs_layout,
 238         .curs_format = headc37d_curs_format,
 239         .curs_set = headc37d_curs_set,
 240         .curs_clr = headc37d_curs_clr,
 241         .dither = headc37d_dither,
 242         .procamp = headc37d_procamp,
 243         .or = headc37d_or,
 244         .static_wndw_map = headc37d_static_wndw_map,
 245 };