drivers/gpu/drm/nouveau/dispnv50/head907d.c

   1 /*
   2  * Copyright 2018 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22 #include <drm/drm_connector.h>
  23 #include <drm/drm_mode_config.h>
  24 #include <drm/drm_vblank.h>
  25 #include "nouveau_drv.h"
  26 #include "nouveau_bios.h"
  27 #include "nouveau_connector.h"
  28 #include "head.h"
  29 #include "core.h"
  30 #include "crc.h"
  31
  32 #include <nvif/push507c.h>
  33
  34 #include <nvhw/class/cl907d.h>
  35
  36 int
  37 head907d_or(struct nv50_head *head, struct nv50_head_atom *asyh)
  38 {
  39         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
  40         const int i = head->base.index;
  41         int ret;
  42
  43         if ((ret = PUSH_WAIT(push, 3)))
  44                 return ret;
  45
  46         PUSH_NVSQ(push, NV907D, 0x0404 + (i * 0x300), asyh->or.depth  << 6 |
  47                                                       asyh->or.nvsync << 4 |
  48                                                       asyh->or.nhsync << 3 |
  49                                                       asyh->or.crc_raster,
  50                                 0x0408 + (i * 0x300), 0x31ec6000 |
  51                                                       head->base.index << 25 |
  52                                                       asyh->mode.interlace);
  53         return 0;
  54 }
  55
  56 int
  57 head907d_procamp(struct nv50_head *head, struct nv50_head_atom *asyh)
  58 {
  59         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
  60         const int i = head->base.index;
  61         int ret;
  62
  63         if ((ret = PUSH_WAIT(push, 2)))
  64                 return ret;
  65
  66         PUSH_NVSQ(push, NV907D, 0x0498 + (i * 0x300), asyh->procamp.sat.sin << 20 |
  67                                                       asyh->procamp.sat.cos << 8);
  68         return 0;
  69 }
  70
  71 static int
  72 head907d_dither(struct nv50_head *head, struct nv50_head_atom *asyh)
  73 {
  74         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
  75         const int i = head->base.index;
  76         int ret;
  77
  78         if ((ret = PUSH_WAIT(push, 2)))
  79                 return ret;
  80
  81         PUSH_NVSQ(push, NV907D, 0x0490 + (i * 0x300), asyh->dither.mode << 3 |
  82                                                       asyh->dither.bits << 1 |
  83                                                       asyh->dither.enable);
  84         return 0;
  85 }
  86
  87 int
  88 head907d_ovly(struct nv50_head *head, struct nv50_head_atom *asyh)
  89 {
  90         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
  91         const int i = head->base.index;
  92         u32 bounds = 0;
  93         int ret;
  94
  95         if (asyh->ovly.cpp) {
  96                 switch (asyh->ovly.cpp) {
  97                 case 8: bounds |= 0x00000500; break;
  98                 case 4: bounds |= 0x00000300; break;
  99                 case 2: bounds |= 0x00000100; break;
 100                 default:
 101                         WARN_ON(1);
 102                         break;
 103                 }
 104                 bounds |= 0x00000001;
 105         } else {
 106                 bounds |= 0x00000100;
 107         }
 108
 109         if ((ret = PUSH_WAIT(push, 2)))
 110                 return ret;
 111
 112         PUSH_NVSQ(push, NV907D, 0x04d4 + (i * 0x300), bounds);
 113         return 0;
 114 }
 115
 116 static int
 117 head907d_base(struct nv50_head *head, struct nv50_head_atom *asyh)
 118 {
 119         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
 120         const int i = head->base.index;
 121         u32 bounds = 0;
 122         int ret;
 123
 124         if (asyh->base.cpp) {
 125                 switch (asyh->base.cpp) {
 126                 case 8: bounds |= 0x00000500; break;
 127                 case 4: bounds |= 0x00000300; break;
 128                 case 2: bounds |= 0x00000100; break;
 129                 case 1: bounds |= 0x00000000; break;
 130                 default:
 131                         WARN_ON(1);
 132                         break;
 133                 }
 134                 bounds |= 0x00000001;
 135         }
 136
 137         if ((ret = PUSH_WAIT(push, 2)))
 138                 return ret;
 139
 140         PUSH_NVSQ(push, NV907D, 0x04d0 + (i * 0x300), bounds);
 141         return 0;
 142 }
 143
 144 int
 145 head907d_curs_clr(struct nv50_head *head)
 146 {
 147         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
 148         const int i = head->base.index;
 149         int ret;
 150
 151         if ((ret = PUSH_WAIT(push, 4)))
 152                 return ret;
 153
 154         PUSH_NVSQ(push, NV907D, 0x0480 + (i * 0x300), 0x05000000);
 155         PUSH_NVSQ(push, NV907D, 0x048c + (i * 0x300), 0x00000000);
 156         return 0;
 157 }
 158
 159 int
 160 head907d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh)
 161 {
 162         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
 163         const int i = head->base.index;
 164         int ret;
 165
 166         if ((ret = PUSH_WAIT(push, 5)))
 167                 return ret;
 168
 169         PUSH_NVSQ(push, NV907D, 0x0480 + (i * 0x300), 0x80000000 |
 170                                                       asyh->curs.layout << 26 |
 171                                                       asyh->curs.format << 24,
 172                                 0x0484 + (i * 0x300), asyh->curs.offset >> 8);
 173         PUSH_NVSQ(push, NV907D, 0x048c + (i * 0x300), asyh->curs.handle);
 174         return 0;
 175 }
 176
 177 int
 178 head907d_core_clr(struct nv50_head *head)
 179 {
 180         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
 181         const int i = head->base.index;
 182         int ret;
 183
 184         if ((ret = PUSH_WAIT(push, 2)))
 185                 return ret;
 186
 187         PUSH_NVSQ(push, NV907D, 0x0474 + (i * 0x300), 0x00000000);
 188         return 0;
 189 }
 190
 191 int
 192 head907d_core_set(struct nv50_head *head, struct nv50_head_atom *asyh)
 193 {
 194         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
 195         const int i = head->base.index;
 196         int ret;
 197
 198         if ((ret = PUSH_WAIT(push, 9)))
 199                 return ret;
 200
 201         PUSH_NVSQ(push, NV907D, 0x0460 + (i * 0x300), asyh->core.offset >> 8);
 202         PUSH_NVSQ(push, NV907D, 0x0468 + (i * 0x300), asyh->core.h << 16 | asyh->core.w,
 203                                 0x046c + (i * 0x300), asyh->core.layout << 24 |
 204                                                      (asyh->core.pitch >> 8) << 8 |
 205                                                       asyh->core.blocks << 8 |
 206                                                       asyh->core.blockh,
 207                                 0x0470 + (i * 0x300), asyh->core.format << 8,
 208                                 0x0474 + (i * 0x300), asyh->core.handle);
 209         PUSH_NVSQ(push, NV907D, 0x04b0 + (i * 0x300), asyh->core.y << 16 | asyh->core.x);
 210         return 0;
 211 }
 212
 213 int
 214 head907d_olut_clr(struct nv50_head *head)
 215 {
 216         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
 217         const int i = head->base.index;
 218         int ret;
 219
 220         if ((ret = PUSH_WAIT(push, 4)))
 221                 return ret;
 222
 223         PUSH_NVSQ(push, NV907D, 0x0448 + (i * 0x300), 0x00000000);
 224         PUSH_NVSQ(push, NV907D, 0x045c + (i * 0x300), 0x00000000);
 225         return 0;
 226 }
 227
 228 int
 229 head907d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh)
 230 {
 231         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
 232         const int i = head->base.index;
 233         int ret;
 234
 235         if ((ret = PUSH_WAIT(push, 5)))
 236                 return ret;
 237
 238         PUSH_MTHD(push, NV907D, HEAD_SET_OUTPUT_LUT_LO(i),
 239                   NVDEF(NV907D, HEAD_SET_OUTPUT_LUT_LO, ENABLE, ENABLE) |
 240                   NVVAL(NV907D, HEAD_SET_OUTPUT_LUT_LO, MODE, asyh->olut.mode) |
 241                   NVDEF(NV907D, HEAD_SET_OUTPUT_LUT_LO, NEVER_YIELD_TO_BASE, DISABLE),
 242
 243                                 HEAD_SET_OUTPUT_LUT_HI(i),
 244                   NVVAL(NV907D, HEAD_SET_OUTPUT_LUT_HI, ORIGIN, asyh->olut.offset >> 8));
 245
 246         PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_LUT(i), asyh->olut.handle);
 247         return 0;
 248 }
 249
 250 void
 251 head907d_olut_load(struct drm_color_lut *in, int size, void __iomem *mem)
 252 {
 253         for (; size--; in++, mem += 8) {
 254                 writew(drm_color_lut_extract(in->  red, 14) + 0x6000, mem + 0);
 255                 writew(drm_color_lut_extract(in->green, 14) + 0x6000, mem + 2);
 256                 writew(drm_color_lut_extract(in-> blue, 14) + 0x6000, mem + 4);
 257         }
 258
 259         /* INTERPOLATE modes require a "next" entry to interpolate with,
 260          * so we replicate the last entry to deal with this for now.
 261          */
 262         writew(readw(mem - 8), mem + 0);
 263         writew(readw(mem - 6), mem + 2);
 264         writew(readw(mem - 4), mem + 4);
 265 }
 266
 267 bool
 268 head907d_olut(struct nv50_head *head, struct nv50_head_atom *asyh, int size)
 269 {
 270         if (size != 256 && size != 1024)
 271                 return false;
 272
 273         if (size == 1024)
 274                 asyh->olut.mode = NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE;
 275         else
 276                 asyh->olut.mode = NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE;
 277
 278         asyh->olut.load = head907d_olut_load;
 279         return true;
 280 }
 281
 282 int
 283 head907d_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
 284 {
 285         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
 286         struct nv50_head_mode *m = &asyh->mode;
 287         const int i = head->base.index;
 288         int ret;
 289
 290         if ((ret = PUSH_WAIT(push, 14)))
 291                 return ret;
 292
 293         PUSH_MTHD(push, NV907D, HEAD_SET_OVERSCAN_COLOR(i),
 294                   NVVAL(NV907D, HEAD_SET_OVERSCAN_COLOR, RED, 0) |
 295                   NVVAL(NV907D, HEAD_SET_OVERSCAN_COLOR, GRN, 0) |
 296                   NVVAL(NV907D, HEAD_SET_OVERSCAN_COLOR, BLU, 0),
 297
 298                                 HEAD_SET_RASTER_SIZE(i),
 299                   NVVAL(NV907D, HEAD_SET_RASTER_SIZE, WIDTH, m->h.active) |
 300                   NVVAL(NV907D, HEAD_SET_RASTER_SIZE, HEIGHT, m->v.active),
 301
 302                                 HEAD_SET_RASTER_SYNC_END(i),
 303                   NVVAL(NV907D, HEAD_SET_RASTER_SYNC_END, X, m->h.synce) |
 304                   NVVAL(NV907D, HEAD_SET_RASTER_SYNC_END, Y, m->v.synce),
 305
 306                                 HEAD_SET_RASTER_BLANK_END(i),
 307                   NVVAL(NV907D, HEAD_SET_RASTER_BLANK_END, X, m->h.blanke) |
 308                   NVVAL(NV907D, HEAD_SET_RASTER_BLANK_END, Y, m->v.blanke),
 309
 310                                 HEAD_SET_RASTER_BLANK_START(i),
 311                   NVVAL(NV907D, HEAD_SET_RASTER_BLANK_START, X, m->h.blanks) |
 312                   NVVAL(NV907D, HEAD_SET_RASTER_BLANK_START, Y, m->v.blanks),
 313
 314                                 HEAD_SET_RASTER_VERT_BLANK2(i),
 315                   NVVAL(NV907D, HEAD_SET_RASTER_VERT_BLANK2, YSTART, m->v.blank2s) |
 316                   NVVAL(NV907D, HEAD_SET_RASTER_VERT_BLANK2, YEND, m->v.blank2e));
 317
 318         PUSH_MTHD(push, NV907D, HEAD_SET_DEFAULT_BASE_COLOR(i),
 319                   NVVAL(NV907D, HEAD_SET_DEFAULT_BASE_COLOR, RED, 0) |
 320                   NVVAL(NV907D, HEAD_SET_DEFAULT_BASE_COLOR, GREEN, 0) |
 321                   NVVAL(NV907D, HEAD_SET_DEFAULT_BASE_COLOR, BLUE, 0),
 322
 323                                 HEAD_SET_CRC_CONTROL(i),
 324                   NVDEF(NV907D, HEAD_SET_CRC_CONTROL, CONTROLLING_CHANNEL, CORE) |
 325                   NVDEF(NV907D, HEAD_SET_CRC_CONTROL, EXPECT_BUFFER_COLLAPSE, FALSE) |
 326                   NVDEF(NV907D, HEAD_SET_CRC_CONTROL, TIMESTAMP_MODE, FALSE) |
 327                   NVDEF(NV907D, HEAD_SET_CRC_CONTROL, PRIMARY_OUTPUT, NONE) |
 328                   NVDEF(NV907D, HEAD_SET_CRC_CONTROL, SECONDARY_OUTPUT, NONE));
 329
 330         PUSH_MTHD(push, NV907D, HEAD_SET_PIXEL_CLOCK_FREQUENCY(i),
 331                   NVVAL(NV907D, HEAD_SET_PIXEL_CLOCK_FREQUENCY, HERTZ, m->clock * 1000) |
 332                   NVDEF(NV907D, HEAD_SET_PIXEL_CLOCK_FREQUENCY, ADJ1000DIV1001, FALSE),
 333
 334                                 HEAD_SET_PIXEL_CLOCK_CONFIGURATION(i),
 335                   NVDEF(NV907D, HEAD_SET_PIXEL_CLOCK_CONFIGURATION, MODE, CLK_CUSTOM) |
 336                   NVDEF(NV907D, HEAD_SET_PIXEL_CLOCK_CONFIGURATION, NOT_DRIVER, FALSE) |
 337                   NVDEF(NV907D, HEAD_SET_PIXEL_CLOCK_CONFIGURATION, ENABLE_HOPPING, FALSE),
 338
 339                                 HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(i),
 340                   NVVAL(NV907D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX, HERTZ, m->clock * 1000) |
 341                   NVDEF(NV907D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX, ADJ1000DIV1001, FALSE));
 342         return 0;
 343 }
 344
 345 int
 346 head907d_view(struct nv50_head *head, struct nv50_head_atom *asyh)
 347 {
 348         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
 349         const int i = head->base.index;
 350         int ret;
 351
 352         if ((ret = PUSH_WAIT(push, 8)))
 353                 return ret;
 354
 355         PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_OUTPUT_SCALER(i),
 356                   NVDEF(NV907D, HEAD_SET_CONTROL_OUTPUT_SCALER, VERTICAL_TAPS, TAPS_1) |
 357                   NVDEF(NV907D, HEAD_SET_CONTROL_OUTPUT_SCALER, HORIZONTAL_TAPS, TAPS_1) |
 358                   NVVAL(NV907D, HEAD_SET_CONTROL_OUTPUT_SCALER, HRESPONSE_BIAS, 0) |
 359                   NVVAL(NV907D, HEAD_SET_CONTROL_OUTPUT_SCALER, VRESPONSE_BIAS, 0));
 360
 361         PUSH_MTHD(push, NV907D, HEAD_SET_VIEWPORT_SIZE_IN(i),
 362                   NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_IN, WIDTH, asyh->view.iW) |
 363                   NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_IN, HEIGHT, asyh->view.iH));
 364
 365         PUSH_MTHD(push, NV907D, HEAD_SET_VIEWPORT_SIZE_OUT(i),
 366                   NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT, WIDTH, asyh->view.oW) |
 367                   NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT, HEIGHT, asyh->view.oH),
 368
 369                                 HEAD_SET_VIEWPORT_SIZE_OUT_MIN(i),
 370                   NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT_MIN, WIDTH, asyh->view.oW) |
 371                   NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT_MIN, HEIGHT, asyh->view.oH),
 372
 373                                 HEAD_SET_VIEWPORT_SIZE_OUT_MAX(i),
 374                   NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT_MAX, WIDTH, asyh->view.oW) |
 375                   NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT_MAX, HEIGHT, asyh->view.oH));
 376         return 0;
 377 }
 378
 379 const struct nv50_head_func
 380 head907d = {
 381         .view = head907d_view,
 382         .mode = head907d_mode,
 383         .olut = head907d_olut,
 384         .olut_size = 1024,
 385         .olut_set = head907d_olut_set,
 386         .olut_clr = head907d_olut_clr,
 387         .core_calc = head507d_core_calc,
 388         .core_set = head907d_core_set,
 389         .core_clr = head907d_core_clr,
 390         .curs_layout = head507d_curs_layout,
 391         .curs_format = head507d_curs_format,
 392         .curs_set = head907d_curs_set,
 393         .curs_clr = head907d_curs_clr,
 394         .base = head907d_base,
 395         .ovly = head907d_ovly,
 396         .dither = head907d_dither,
 397         .procamp = head907d_procamp,
 398         .or = head907d_or,
 399 };