drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_view()
[linux-2.6-microblaze.git] / drivers / gpu / drm / nouveau / dispnv50 / head907d.c
1 /*
2  * Copyright 2018 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22 #include <drm/drm_connector.h>
23 #include <drm/drm_mode_config.h>
24 #include <drm/drm_vblank.h>
25 #include "nouveau_drv.h"
26 #include "nouveau_bios.h"
27 #include "nouveau_connector.h"
28 #include "head.h"
29 #include "core.h"
30 #include "crc.h"
31
32 #include <nvif/push507c.h>
33
34 #include <nvhw/class/cl907d.h>
35
36 int
37 head907d_or(struct nv50_head *head, struct nv50_head_atom *asyh)
38 {
39         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
40         const int i = head->base.index;
41         int ret;
42
43         if ((ret = PUSH_WAIT(push, 3)))
44                 return ret;
45
46         PUSH_NVSQ(push, NV907D, 0x0404 + (i * 0x300), asyh->or.depth  << 6 |
47                                                       asyh->or.nvsync << 4 |
48                                                       asyh->or.nhsync << 3 |
49                                                       asyh->or.crc_raster,
50                                 0x0408 + (i * 0x300), 0x31ec6000 |
51                                                       head->base.index << 25 |
52                                                       asyh->mode.interlace);
53         return 0;
54 }
55
56 int
57 head907d_procamp(struct nv50_head *head, struct nv50_head_atom *asyh)
58 {
59         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
60         const int i = head->base.index;
61         int ret;
62
63         if ((ret = PUSH_WAIT(push, 2)))
64                 return ret;
65
66         PUSH_NVSQ(push, NV907D, 0x0498 + (i * 0x300), asyh->procamp.sat.sin << 20 |
67                                                       asyh->procamp.sat.cos << 8);
68         return 0;
69 }
70
71 static int
72 head907d_dither(struct nv50_head *head, struct nv50_head_atom *asyh)
73 {
74         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
75         const int i = head->base.index;
76         int ret;
77
78         if ((ret = PUSH_WAIT(push, 2)))
79                 return ret;
80
81         PUSH_NVSQ(push, NV907D, 0x0490 + (i * 0x300), asyh->dither.mode << 3 |
82                                                       asyh->dither.bits << 1 |
83                                                       asyh->dither.enable);
84         return 0;
85 }
86
87 int
88 head907d_ovly(struct nv50_head *head, struct nv50_head_atom *asyh)
89 {
90         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
91         const int i = head->base.index;
92         u32 bounds = 0;
93         int ret;
94
95         if (asyh->ovly.cpp) {
96                 switch (asyh->ovly.cpp) {
97                 case 8: bounds |= 0x00000500; break;
98                 case 4: bounds |= 0x00000300; break;
99                 case 2: bounds |= 0x00000100; break;
100                 default:
101                         WARN_ON(1);
102                         break;
103                 }
104                 bounds |= 0x00000001;
105         } else {
106                 bounds |= 0x00000100;
107         }
108
109         if ((ret = PUSH_WAIT(push, 2)))
110                 return ret;
111
112         PUSH_NVSQ(push, NV907D, 0x04d4 + (i * 0x300), bounds);
113         return 0;
114 }
115
116 static int
117 head907d_base(struct nv50_head *head, struct nv50_head_atom *asyh)
118 {
119         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
120         const int i = head->base.index;
121         u32 bounds = 0;
122         int ret;
123
124         if (asyh->base.cpp) {
125                 switch (asyh->base.cpp) {
126                 case 8: bounds |= 0x00000500; break;
127                 case 4: bounds |= 0x00000300; break;
128                 case 2: bounds |= 0x00000100; break;
129                 case 1: bounds |= 0x00000000; break;
130                 default:
131                         WARN_ON(1);
132                         break;
133                 }
134                 bounds |= 0x00000001;
135         }
136
137         if ((ret = PUSH_WAIT(push, 2)))
138                 return ret;
139
140         PUSH_NVSQ(push, NV907D, 0x04d0 + (i * 0x300), bounds);
141         return 0;
142 }
143
144 int
145 head907d_curs_clr(struct nv50_head *head)
146 {
147         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
148         const int i = head->base.index;
149         int ret;
150
151         if ((ret = PUSH_WAIT(push, 4)))
152                 return ret;
153
154         PUSH_NVSQ(push, NV907D, 0x0480 + (i * 0x300), 0x05000000);
155         PUSH_NVSQ(push, NV907D, 0x048c + (i * 0x300), 0x00000000);
156         return 0;
157 }
158
159 int
160 head907d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh)
161 {
162         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
163         const int i = head->base.index;
164         int ret;
165
166         if ((ret = PUSH_WAIT(push, 5)))
167                 return ret;
168
169         PUSH_NVSQ(push, NV907D, 0x0480 + (i * 0x300), 0x80000000 |
170                                                       asyh->curs.layout << 26 |
171                                                       asyh->curs.format << 24,
172                                 0x0484 + (i * 0x300), asyh->curs.offset >> 8);
173         PUSH_NVSQ(push, NV907D, 0x048c + (i * 0x300), asyh->curs.handle);
174         return 0;
175 }
176
177 int
178 head907d_core_clr(struct nv50_head *head)
179 {
180         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
181         const int i = head->base.index;
182         int ret;
183
184         if ((ret = PUSH_WAIT(push, 2)))
185                 return ret;
186
187         PUSH_NVSQ(push, NV907D, 0x0474 + (i * 0x300), 0x00000000);
188         return 0;
189 }
190
191 int
192 head907d_core_set(struct nv50_head *head, struct nv50_head_atom *asyh)
193 {
194         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
195         const int i = head->base.index;
196         int ret;
197
198         if ((ret = PUSH_WAIT(push, 9)))
199                 return ret;
200
201         PUSH_NVSQ(push, NV907D, 0x0460 + (i * 0x300), asyh->core.offset >> 8);
202         PUSH_NVSQ(push, NV907D, 0x0468 + (i * 0x300), asyh->core.h << 16 | asyh->core.w,
203                                 0x046c + (i * 0x300), asyh->core.layout << 24 |
204                                                      (asyh->core.pitch >> 8) << 8 |
205                                                       asyh->core.blocks << 8 |
206                                                       asyh->core.blockh,
207                                 0x0470 + (i * 0x300), asyh->core.format << 8,
208                                 0x0474 + (i * 0x300), asyh->core.handle);
209         PUSH_NVSQ(push, NV907D, 0x04b0 + (i * 0x300), asyh->core.y << 16 | asyh->core.x);
210         return 0;
211 }
212
213 int
214 head907d_olut_clr(struct nv50_head *head)
215 {
216         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
217         const int i = head->base.index;
218         int ret;
219
220         if ((ret = PUSH_WAIT(push, 4)))
221                 return ret;
222
223         PUSH_NVSQ(push, NV907D, 0x0448 + (i * 0x300), 0x00000000);
224         PUSH_NVSQ(push, NV907D, 0x045c + (i * 0x300), 0x00000000);
225         return 0;
226 }
227
228 int
229 head907d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh)
230 {
231         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
232         const int i = head->base.index;
233         int ret;
234
235         if ((ret = PUSH_WAIT(push, 5)))
236                 return ret;
237
238         PUSH_NVSQ(push, NV907D, 0x0448 + (i * 0x300), 0x80000000 | asyh->olut.mode << 24,
239                                 0x044c + (i * 0x300), asyh->olut.offset >> 8);
240         PUSH_NVSQ(push, NV907D, 0x045c + (i * 0x300), asyh->olut.handle);
241         return 0;
242 }
243
244 void
245 head907d_olut_load(struct drm_color_lut *in, int size, void __iomem *mem)
246 {
247         for (; size--; in++, mem += 8) {
248                 writew(drm_color_lut_extract(in->  red, 14) + 0x6000, mem + 0);
249                 writew(drm_color_lut_extract(in->green, 14) + 0x6000, mem + 2);
250                 writew(drm_color_lut_extract(in-> blue, 14) + 0x6000, mem + 4);
251         }
252
253         /* INTERPOLATE modes require a "next" entry to interpolate with,
254          * so we replicate the last entry to deal with this for now.
255          */
256         writew(readw(mem - 8), mem + 0);
257         writew(readw(mem - 6), mem + 2);
258         writew(readw(mem - 4), mem + 4);
259 }
260
261 bool
262 head907d_olut(struct nv50_head *head, struct nv50_head_atom *asyh, int size)
263 {
264         if (size != 256 && size != 1024)
265                 return false;
266
267         asyh->olut.mode = size == 1024 ? 4 : 7;
268         asyh->olut.load = head907d_olut_load;
269         return true;
270 }
271
272 int
273 head907d_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
274 {
275         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
276         struct nv50_head_mode *m = &asyh->mode;
277         const int i = head->base.index;
278         int ret;
279
280         if ((ret = PUSH_WAIT(push, 14)))
281                 return ret;
282
283         PUSH_NVSQ(push, NV907D, 0x0410 + (i * 0x300), 0x00000000,
284                                 0x0414 + (i * 0x300), m->v.active  << 16 | m->h.active,
285                                 0x0418 + (i * 0x300), m->v.synce   << 16 | m->h.synce,
286                                 0x041c + (i * 0x300), m->v.blanke  << 16 | m->h.blanke,
287                                 0x0420 + (i * 0x300), m->v.blanks  << 16 | m->h.blanks,
288                                 0x0424 + (i * 0x300), m->v.blank2e << 16 | m->v.blank2s);
289         PUSH_NVSQ(push, NV907D, 0x042c + (i * 0x300), 0x00000000,
290                                 0x0430 + (i * 0x300), 0xffffff00);
291         PUSH_NVSQ(push, NV907D, 0x0450 + (i * 0x300), m->clock * 1000,
292                                 0x0454 + (i * 0x300), 0x00200000,
293                                 0x0458 + (i * 0x300), m->clock * 1000);
294         return 0;
295 }
296
297 int
298 head907d_view(struct nv50_head *head, struct nv50_head_atom *asyh)
299 {
300         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
301         const int i = head->base.index;
302         int ret;
303
304         if ((ret = PUSH_WAIT(push, 8)))
305                 return ret;
306
307         PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_OUTPUT_SCALER(i),
308                   NVDEF(NV907D, HEAD_SET_CONTROL_OUTPUT_SCALER, VERTICAL_TAPS, TAPS_1) |
309                   NVDEF(NV907D, HEAD_SET_CONTROL_OUTPUT_SCALER, HORIZONTAL_TAPS, TAPS_1) |
310                   NVVAL(NV907D, HEAD_SET_CONTROL_OUTPUT_SCALER, HRESPONSE_BIAS, 0) |
311                   NVVAL(NV907D, HEAD_SET_CONTROL_OUTPUT_SCALER, VRESPONSE_BIAS, 0));
312
313         PUSH_MTHD(push, NV907D, HEAD_SET_VIEWPORT_SIZE_IN(i),
314                   NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_IN, WIDTH, asyh->view.iW) |
315                   NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_IN, HEIGHT, asyh->view.iH));
316
317         PUSH_MTHD(push, NV907D, HEAD_SET_VIEWPORT_SIZE_OUT(i),
318                   NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT, WIDTH, asyh->view.oW) |
319                   NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT, HEIGHT, asyh->view.oH),
320
321                                 HEAD_SET_VIEWPORT_SIZE_OUT_MIN(i),
322                   NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT_MIN, WIDTH, asyh->view.oW) |
323                   NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT_MIN, HEIGHT, asyh->view.oH),
324
325                                 HEAD_SET_VIEWPORT_SIZE_OUT_MAX(i),
326                   NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT_MAX, WIDTH, asyh->view.oW) |
327                   NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT_MAX, HEIGHT, asyh->view.oH));
328         return 0;
329 }
330
331 const struct nv50_head_func
332 head907d = {
333         .view = head907d_view,
334         .mode = head907d_mode,
335         .olut = head907d_olut,
336         .olut_size = 1024,
337         .olut_set = head907d_olut_set,
338         .olut_clr = head907d_olut_clr,
339         .core_calc = head507d_core_calc,
340         .core_set = head907d_core_set,
341         .core_clr = head907d_core_clr,
342         .curs_layout = head507d_curs_layout,
343         .curs_format = head507d_curs_format,
344         .curs_set = head907d_curs_set,
345         .curs_clr = head907d_curs_clr,
346         .base = head907d_base,
347         .ovly = head907d_ovly,
348         .dither = head907d_dither,
349         .procamp = head907d_procamp,
350         .or = head907d_or,
351 };