drivers/gpu/drm/nouveau/dispnv50/head827d.c

   1 /*
   2  * Copyright 2018 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22 #include "head.h"
  23 #include "core.h"
  24
  25 #include <nvif/push507c.h>
  26
  27 #include <nvhw/class/cl827d.h>
  28
  29 static int
  30 head827d_curs_clr(struct nv50_head *head)
  31 {
  32         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
  33         const int i = head->base.index;
  34         int ret;
  35
  36         if ((ret = PUSH_WAIT(push, 4)))
  37                 return ret;
  38
  39         PUSH_NVSQ(push, NV827D, 0x0880 + (i * 0x400), 0x05000000);
  40         PUSH_NVSQ(push, NV827D, 0x089c + (i * 0x400), 0x00000000);
  41         return 0;
  42 }
  43
  44 static int
  45 head827d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh)
  46 {
  47         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
  48         const int i = head->base.index;
  49         int ret;
  50
  51         if ((ret = PUSH_WAIT(push, 5)))
  52                 return ret;
  53
  54         PUSH_NVSQ(push, NV827D, 0x0880 + (i * 0x400), 0x80000000 |
  55                                                       asyh->curs.layout << 26 |
  56                                                       asyh->curs.format << 24,
  57                                 0x0884 + (i * 0x400), asyh->curs.offset >> 8);
  58         PUSH_NVSQ(push, NV827D, 0x089c + (i * 0x400), asyh->curs.handle);
  59         return 0;
  60 }
  61
  62 static int
  63 head827d_core_set(struct nv50_head *head, struct nv50_head_atom *asyh)
  64 {
  65         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
  66         const int i = head->base.index;
  67         int ret;
  68
  69         if ((ret = PUSH_WAIT(push, 9)))
  70                 return ret;
  71
  72         PUSH_NVSQ(push, NV827D, 0x0860 + (i * 0x400), asyh->core.offset >> 8);
  73         PUSH_NVSQ(push, NV827D, 0x0868 + (i * 0x400), asyh->core.h << 16 | asyh->core.w,
  74                                 0x086c + (i * 0x400), asyh->core.layout << 20 |
  75                                                      (asyh->core.pitch >> 8) << 8 |
  76                                                       asyh->core.blocks << 8 |
  77                                                       asyh->core.blockh,
  78                                 0x0870 + (i * 0x400), asyh->core.format << 8,
  79                                 0x0874 + (i * 0x400), asyh->core.handle);
  80         PUSH_NVSQ(push, NV827D, 0x08c0 + (i * 0x400), asyh->core.y << 16 | asyh->core.x);
  81         return 0;
  82 }
  83
  84 static int
  85 head827d_olut_clr(struct nv50_head *head)
  86 {
  87         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
  88         const int i = head->base.index;
  89         int ret;
  90
  91         if ((ret = PUSH_WAIT(push, 4)))
  92                 return ret;
  93
  94         PUSH_NVSQ(push, NV827D, 0x0840 + (i * 0x400), 0x00000000);
  95         PUSH_NVSQ(push, NV827D, 0x085c + (i * 0x400), 0x00000000);
  96         return 0;
  97 }
  98
  99 static int
 100 head827d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh)
 101 {
 102         struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
 103         const int i = head->base.index;
 104         int ret;
 105
 106         if ((ret = PUSH_WAIT(push, 5)))
 107                 return ret;
 108
 109         PUSH_MTHD(push, NV827D, HEAD_SET_BASE_LUT_LO(i),
 110                   NVDEF(NV827D, HEAD_SET_BASE_LUT_LO, ENABLE, ENABLE) |
 111                   NVVAL(NV827D, HEAD_SET_BASE_LUT_LO, MODE, asyh->olut.mode) |
 112                   NVVAL(NV827D, HEAD_SET_BASE_LUT_LO, ORIGIN, 0),
 113
 114                                 HEAD_SET_BASE_LUT_HI(i),
 115                   NVVAL(NV827D, HEAD_SET_BASE_LUT_HI, ORIGIN, asyh->olut.offset >> 8));
 116
 117         PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_LUT(i), asyh->olut.handle);
 118         return 0;
 119 }
 120
 121 const struct nv50_head_func
 122 head827d = {
 123         .view = head507d_view,
 124         .mode = head507d_mode,
 125         .olut = head507d_olut,
 126         .olut_size = 256,
 127         .olut_set = head827d_olut_set,
 128         .olut_clr = head827d_olut_clr,
 129         .core_calc = head507d_core_calc,
 130         .core_set = head827d_core_set,
 131         .core_clr = head507d_core_clr,
 132         .curs_layout = head507d_curs_layout,
 133         .curs_format = head507d_curs_format,
 134         .curs_set = head827d_curs_set,
 135         .curs_clr = head827d_curs_clr,
 136         .base = head507d_base,
 137         .ovly = head507d_ovly,
 138         .dither = head507d_dither,
 139         .procamp = head507d_procamp,
 140 };