drivers/gpu/drm/nouveau/dispnv50/disp.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "disp.h"
  25 #include "atom.h"
  26 #include "core.h"
  27 #include "head.h"
  28 #include "wndw.h"
  29
  30 #include <linux/dma-mapping.h>
  31 #include <linux/hdmi.h>
  32 #include <linux/component.h>
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_dp_helper.h>
  36 #include <drm/drm_edid.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_plane_helper.h>
  39 #include <drm/drm_probe_helper.h>
  40 #include <drm/drm_scdc_helper.h>
  41 #include <drm/drm_vblank.h>
  42
  43 #include <nvif/class.h>
  44 #include <nvif/cl0002.h>
  45 #include <nvif/cl5070.h>
  46 #include <nvif/cl507d.h>
  47 #include <nvif/event.h>
  48 #include <nvif/timer.h>
  49
  50 #include "nouveau_drv.h"
  51 #include "nouveau_dma.h"
  52 #include "nouveau_gem.h"
  53 #include "nouveau_connector.h"
  54 #include "nouveau_encoder.h"
  55 #include "nouveau_fence.h"
  56 #include "nouveau_fbcon.h"
  57
  58 #include <subdev/bios/dp.h>
  59
  60 /******************************************************************************
  61  * Atomic state
  62  *****************************************************************************/
  63
  64 struct nv50_outp_atom {
  65         struct list_head head;
  66
  67         struct drm_encoder *encoder;
  68         bool flush_disable;
  69
  70         union nv50_outp_atom_mask {
  71                 struct {
  72                         bool ctrl:1;
  73                 };
  74                 u8 mask;
  75         } set, clr;
  76 };
  77
  78 /******************************************************************************
  79  * EVO channel
  80  *****************************************************************************/
  81
  82 static int
  83 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
  84                  const s32 *oclass, u8 head, void *data, u32 size,
  85                  struct nv50_chan *chan)
  86 {
  87         struct nvif_sclass *sclass;
  88         int ret, i, n;
  89
  90         chan->device = device;
  91
  92         ret = n = nvif_object_sclass_get(disp, &sclass);
  93         if (ret < 0)
  94                 return ret;
  95
  96         while (oclass[0]) {
  97                 for (i = 0; i < n; i++) {
  98                         if (sclass[i].oclass == oclass[0]) {
  99                                 ret = nvif_object_init(disp, 0, oclass[0],
 100                                                        data, size, &chan->user);
 101                                 if (ret == 0)
 102                                         nvif_object_map(&chan->user, NULL, 0);
 103                                 nvif_object_sclass_put(&sclass);
 104                                 return ret;
 105                         }
 106                 }
 107                 oclass++;
 108         }
 109
 110         nvif_object_sclass_put(&sclass);
 111         return -ENOSYS;
 112 }
 113
 114 static void
 115 nv50_chan_destroy(struct nv50_chan *chan)
 116 {
 117         nvif_object_fini(&chan->user);
 118 }
 119
 120 /******************************************************************************
 121  * DMA EVO channel
 122  *****************************************************************************/
 123
 124 void
 125 nv50_dmac_destroy(struct nv50_dmac *dmac)
 126 {
 127         nvif_object_fini(&dmac->vram);
 128         nvif_object_fini(&dmac->sync);
 129
 130         nv50_chan_destroy(&dmac->base);
 131
 132         nvif_mem_fini(&dmac->push);
 133 }
 134
 135 int
 136 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
 137                  const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
 138                  struct nv50_dmac *dmac)
 139 {
 140         struct nouveau_cli *cli = (void *)device->object.client;
 141         struct nv50_disp_core_channel_dma_v0 *args = data;
 142         u8 type = NVIF_MEM_COHERENT;
 143         int ret;
 144
 145         mutex_init(&dmac->lock);
 146
 147         /* Pascal added support for 47-bit physical addresses, but some
 148          * parts of EVO still only accept 40-bit PAs.
 149          *
 150          * To avoid issues on systems with large amounts of RAM, and on
 151          * systems where an IOMMU maps pages at a high address, we need
 152          * to allocate push buffers in VRAM instead.
 153          *
 154          * This appears to match NVIDIA's behaviour on Pascal.
 155          */
 156         if (device->info.family == NV_DEVICE_INFO_V0_PASCAL)
 157                 type |= NVIF_MEM_VRAM;
 158
 159         ret = nvif_mem_init_map(&cli->mmu, type, 0x1000, &dmac->push);
 160         if (ret)
 161                 return ret;
 162
 163         dmac->ptr = dmac->push.object.map.ptr;
 164
 165         args->pushbuf = nvif_handle(&dmac->push.object);
 166
 167         ret = nv50_chan_create(device, disp, oclass, head, data, size,
 168                                &dmac->base);
 169         if (ret)
 170                 return ret;
 171
 172         if (!syncbuf)
 173                 return 0;
 174
 175         ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
 176                                &(struct nv_dma_v0) {
 177                                         .target = NV_DMA_V0_TARGET_VRAM,
 178                                         .access = NV_DMA_V0_ACCESS_RDWR,
 179                                         .start = syncbuf + 0x0000,
 180                                         .limit = syncbuf + 0x0fff,
 181                                }, sizeof(struct nv_dma_v0),
 182                                &dmac->sync);
 183         if (ret)
 184                 return ret;
 185
 186         ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
 187                                &(struct nv_dma_v0) {
 188                                         .target = NV_DMA_V0_TARGET_VRAM,
 189                                         .access = NV_DMA_V0_ACCESS_RDWR,
 190                                         .start = 0,
 191                                         .limit = device->info.ram_user - 1,
 192                                }, sizeof(struct nv_dma_v0),
 193                                &dmac->vram);
 194         if (ret)
 195                 return ret;
 196
 197         return ret;
 198 }
 199
 200 /******************************************************************************
 201  * EVO channel helpers
 202  *****************************************************************************/
 203 static void
 204 evo_flush(struct nv50_dmac *dmac)
 205 {
 206         /* Push buffer fetches are not coherent with BAR1, we need to ensure
 207          * writes have been flushed right through to VRAM before writing PUT.
 208          */
 209         if (dmac->push.type & NVIF_MEM_VRAM) {
 210                 struct nvif_device *device = dmac->base.device;
 211                 nvif_wr32(&device->object, 0x070000, 0x00000001);
 212                 nvif_msec(device, 2000,
 213                         if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
 214                                 break;
 215                 );
 216         }
 217 }
 218
 219 u32 *
 220 evo_wait(struct nv50_dmac *evoc, int nr)
 221 {
 222         struct nv50_dmac *dmac = evoc;
 223         struct nvif_device *device = dmac->base.device;
 224         u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
 225
 226         mutex_lock(&dmac->lock);
 227         if (put + nr >= (PAGE_SIZE / 4) - 8) {
 228                 dmac->ptr[put] = 0x20000000;
 229                 evo_flush(dmac);
 230
 231                 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
 232                 if (nvif_msec(device, 2000,
 233                         if (!nvif_rd32(&dmac->base.user, 0x0004))
 234                                 break;
 235                 ) < 0) {
 236                         mutex_unlock(&dmac->lock);
 237                         pr_err("nouveau: evo channel stalled\n");
 238                         return NULL;
 239                 }
 240
 241                 put = 0;
 242         }
 243
 244         return dmac->ptr + put;
 245 }
 246
 247 void
 248 evo_kick(u32 *push, struct nv50_dmac *evoc)
 249 {
 250         struct nv50_dmac *dmac = evoc;
 251
 252         evo_flush(dmac);
 253
 254         nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
 255         mutex_unlock(&dmac->lock);
 256 }
 257
 258 /******************************************************************************
 259  * Output path helpers
 260  *****************************************************************************/
 261 static void
 262 nv50_outp_release(struct nouveau_encoder *nv_encoder)
 263 {
 264         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
 265         struct {
 266                 struct nv50_disp_mthd_v1 base;
 267         } args = {
 268                 .base.version = 1,
 269                 .base.method = NV50_DISP_MTHD_V1_RELEASE,
 270                 .base.hasht  = nv_encoder->dcb->hasht,
 271                 .base.hashm  = nv_encoder->dcb->hashm,
 272         };
 273
 274         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 275         nv_encoder->or = -1;
 276         nv_encoder->link = 0;
 277 }
 278
 279 static int
 280 nv50_outp_acquire(struct nouveau_encoder *nv_encoder, bool hda)
 281 {
 282         struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
 283         struct nv50_disp *disp = nv50_disp(drm->dev);
 284         struct {
 285                 struct nv50_disp_mthd_v1 base;
 286                 struct nv50_disp_acquire_v0 info;
 287         } args = {
 288                 .base.version = 1,
 289                 .base.method = NV50_DISP_MTHD_V1_ACQUIRE,
 290                 .base.hasht  = nv_encoder->dcb->hasht,
 291                 .base.hashm  = nv_encoder->dcb->hashm,
 292                 .info.hda = hda,
 293         };
 294         int ret;
 295
 296         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 297         if (ret) {
 298                 NV_ERROR(drm, "error acquiring output path: %d\n", ret);
 299                 return ret;
 300         }
 301
 302         nv_encoder->or = args.info.or;
 303         nv_encoder->link = args.info.link;
 304         return 0;
 305 }
 306
 307 static int
 308 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
 309                             struct drm_crtc_state *crtc_state,
 310                             struct drm_connector_state *conn_state,
 311                             struct drm_display_mode *native_mode)
 312 {
 313         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
 314         struct drm_display_mode *mode = &crtc_state->mode;
 315         struct drm_connector *connector = conn_state->connector;
 316         struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
 317         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 318
 319         NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
 320         asyc->scaler.full = false;
 321         if (!native_mode)
 322                 return 0;
 323
 324         if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
 325                 switch (connector->connector_type) {
 326                 case DRM_MODE_CONNECTOR_LVDS:
 327                 case DRM_MODE_CONNECTOR_eDP:
 328                         /* Don't force scaler for EDID modes with
 329                          * same size as the native one (e.g. different
 330                          * refresh rate)
 331                          */
 332                         if (mode->hdisplay == native_mode->hdisplay &&
 333                             mode->vdisplay == native_mode->vdisplay &&
 334                             mode->type & DRM_MODE_TYPE_DRIVER)
 335                                 break;
 336                         mode = native_mode;
 337                         asyc->scaler.full = true;
 338                         break;
 339                 default:
 340                         break;
 341                 }
 342         } else {
 343                 mode = native_mode;
 344         }
 345
 346         if (!drm_mode_equal(adjusted_mode, mode)) {
 347                 drm_mode_copy(adjusted_mode, mode);
 348                 crtc_state->mode_changed = true;
 349         }
 350
 351         return 0;
 352 }
 353
 354 static int
 355 nv50_outp_atomic_check(struct drm_encoder *encoder,
 356                        struct drm_crtc_state *crtc_state,
 357                        struct drm_connector_state *conn_state)
 358 {
 359         struct drm_connector *connector = conn_state->connector;
 360         struct nouveau_connector *nv_connector = nouveau_connector(connector);
 361         struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
 362         int ret;
 363
 364         ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 365                                           nv_connector->native_mode);
 366         if (ret)
 367                 return ret;
 368
 369         if (crtc_state->mode_changed || crtc_state->connectors_changed)
 370                 asyh->or.bpc = connector->display_info.bpc;
 371
 372         return 0;
 373 }
 374
 375 /******************************************************************************
 376  * DAC
 377  *****************************************************************************/
 378 static void
 379 nv50_dac_disable(struct drm_encoder *encoder)
 380 {
 381         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 382         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 383         if (nv_encoder->crtc)
 384                 core->func->dac->ctrl(core, nv_encoder->or, 0x00000000, NULL);
 385         nv_encoder->crtc = NULL;
 386         nv50_outp_release(nv_encoder);
 387 }
 388
 389 static void
 390 nv50_dac_enable(struct drm_encoder *encoder)
 391 {
 392         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 393         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 394         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
 395         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 396
 397         nv50_outp_acquire(nv_encoder, false);
 398
 399         core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh);
 400         asyh->or.depth = 0;
 401
 402         nv_encoder->crtc = encoder->crtc;
 403 }
 404
 405 static enum drm_connector_status
 406 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 407 {
 408         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 409         struct nv50_disp *disp = nv50_disp(encoder->dev);
 410         struct {
 411                 struct nv50_disp_mthd_v1 base;
 412                 struct nv50_disp_dac_load_v0 load;
 413         } args = {
 414                 .base.version = 1,
 415                 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
 416                 .base.hasht  = nv_encoder->dcb->hasht,
 417                 .base.hashm  = nv_encoder->dcb->hashm,
 418         };
 419         int ret;
 420
 421         args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
 422         if (args.load.data == 0)
 423                 args.load.data = 340;
 424
 425         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 426         if (ret || !args.load.load)
 427                 return connector_status_disconnected;
 428
 429         return connector_status_connected;
 430 }
 431
 432 static const struct drm_encoder_helper_funcs
 433 nv50_dac_help = {
 434         .atomic_check = nv50_outp_atomic_check,
 435         .enable = nv50_dac_enable,
 436         .disable = nv50_dac_disable,
 437         .detect = nv50_dac_detect
 438 };
 439
 440 static void
 441 nv50_dac_destroy(struct drm_encoder *encoder)
 442 {
 443         drm_encoder_cleanup(encoder);
 444         kfree(encoder);
 445 }
 446
 447 static const struct drm_encoder_funcs
 448 nv50_dac_func = {
 449         .destroy = nv50_dac_destroy,
 450 };
 451
 452 static int
 453 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
 454 {
 455         struct nouveau_drm *drm = nouveau_drm(connector->dev);
 456         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
 457         struct nvkm_i2c_bus *bus;
 458         struct nouveau_encoder *nv_encoder;
 459         struct drm_encoder *encoder;
 460         int type = DRM_MODE_ENCODER_DAC;
 461
 462         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 463         if (!nv_encoder)
 464                 return -ENOMEM;
 465         nv_encoder->dcb = dcbe;
 466
 467         bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
 468         if (bus)
 469                 nv_encoder->i2c = &bus->i2c;
 470
 471         encoder = to_drm_encoder(nv_encoder);
 472         encoder->possible_crtcs = dcbe->heads;
 473         encoder->possible_clones = 0;
 474         drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
 475                          "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
 476         drm_encoder_helper_add(encoder, &nv50_dac_help);
 477
 478         drm_connector_attach_encoder(connector, encoder);
 479         return 0;
 480 }
 481
 482 /*
 483  * audio component binding for ELD notification
 484  */
 485 static void
 486 nv50_audio_component_eld_notify(struct drm_audio_component *acomp, int port,
 487                                 int dev_id)
 488 {
 489         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
 490                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
 491                                                  port, dev_id);
 492 }
 493
 494 static int
 495 nv50_audio_component_get_eld(struct device *kdev, int port, int dev_id,
 496                              bool *enabled, unsigned char *buf, int max_bytes)
 497 {
 498         struct drm_device *drm_dev = dev_get_drvdata(kdev);
 499         struct nouveau_drm *drm = nouveau_drm(drm_dev);
 500         struct drm_encoder *encoder;
 501         struct nouveau_encoder *nv_encoder;
 502         struct nouveau_connector *nv_connector;
 503         struct nouveau_crtc *nv_crtc;
 504         int ret = 0;
 505
 506         *enabled = false;
 507         drm_for_each_encoder(encoder, drm->dev) {
 508                 nv_encoder = nouveau_encoder(encoder);
 509                 nv_connector = nouveau_encoder_connector_get(nv_encoder);
 510                 nv_crtc = nouveau_crtc(encoder->crtc);
 511                 if (!nv_connector || !nv_crtc || nv_encoder->or != port ||
 512                     nv_crtc->index != dev_id)
 513                         continue;
 514                 *enabled = nv_encoder->audio;
 515                 if (*enabled) {
 516                         ret = drm_eld_size(nv_connector->base.eld);
 517                         memcpy(buf, nv_connector->base.eld,
 518                                min(max_bytes, ret));
 519                 }
 520                 break;
 521         }
 522         return ret;
 523 }
 524
 525 static const struct drm_audio_component_ops nv50_audio_component_ops = {
 526         .get_eld = nv50_audio_component_get_eld,
 527 };
 528
 529 static int
 530 nv50_audio_component_bind(struct device *kdev, struct device *hda_kdev,
 531                           void *data)
 532 {
 533         struct drm_device *drm_dev = dev_get_drvdata(kdev);
 534         struct nouveau_drm *drm = nouveau_drm(drm_dev);
 535         struct drm_audio_component *acomp = data;
 536
 537         if (WARN_ON(!device_link_add(hda_kdev, kdev, DL_FLAG_STATELESS)))
 538                 return -ENOMEM;
 539
 540         drm_modeset_lock_all(drm_dev);
 541         acomp->ops = &nv50_audio_component_ops;
 542         acomp->dev = kdev;
 543         drm->audio.component = acomp;
 544         drm_modeset_unlock_all(drm_dev);
 545         return 0;
 546 }
 547
 548 static void
 549 nv50_audio_component_unbind(struct device *kdev, struct device *hda_kdev,
 550                             void *data)
 551 {
 552         struct drm_device *drm_dev = dev_get_drvdata(kdev);
 553         struct nouveau_drm *drm = nouveau_drm(drm_dev);
 554         struct drm_audio_component *acomp = data;
 555
 556         drm_modeset_lock_all(drm_dev);
 557         drm->audio.component = NULL;
 558         acomp->ops = NULL;
 559         acomp->dev = NULL;
 560         drm_modeset_unlock_all(drm_dev);
 561 }
 562
 563 static const struct component_ops nv50_audio_component_bind_ops = {
 564         .bind   = nv50_audio_component_bind,
 565         .unbind = nv50_audio_component_unbind,
 566 };
 567
 568 static void
 569 nv50_audio_component_init(struct nouveau_drm *drm)
 570 {
 571         if (!component_add(drm->dev->dev, &nv50_audio_component_bind_ops))
 572                 drm->audio.component_registered = true;
 573 }
 574
 575 static void
 576 nv50_audio_component_fini(struct nouveau_drm *drm)
 577 {
 578         if (drm->audio.component_registered) {
 579                 component_del(drm->dev->dev, &nv50_audio_component_bind_ops);
 580                 drm->audio.component_registered = false;
 581         }
 582 }
 583
 584 /******************************************************************************
 585  * Audio
 586  *****************************************************************************/
 587 static void
 588 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 589 {
 590         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 591         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 592         struct nv50_disp *disp = nv50_disp(encoder->dev);
 593         struct {
 594                 struct nv50_disp_mthd_v1 base;
 595                 struct nv50_disp_sor_hda_eld_v0 eld;
 596         } args = {
 597                 .base.version = 1,
 598                 .base.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
 599                 .base.hasht   = nv_encoder->dcb->hasht,
 600                 .base.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
 601                                 (0x0100 << nv_crtc->index),
 602         };
 603
 604         if (!nv_encoder->audio)
 605                 return;
 606
 607         nv_encoder->audio = false;
 608         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 609
 610         nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or,
 611                                         nv_crtc->index);
 612 }
 613
 614 static void
 615 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
 616 {
 617         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 618         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 619         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 620         struct nouveau_connector *nv_connector;
 621         struct nv50_disp *disp = nv50_disp(encoder->dev);
 622         struct __packed {
 623                 struct {
 624                         struct nv50_disp_mthd_v1 mthd;
 625                         struct nv50_disp_sor_hda_eld_v0 eld;
 626                 } base;
 627                 u8 data[sizeof(nv_connector->base.eld)];
 628         } args = {
 629                 .base.mthd.version = 1,
 630                 .base.mthd.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
 631                 .base.mthd.hasht   = nv_encoder->dcb->hasht,
 632                 .base.mthd.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
 633                                      (0x0100 << nv_crtc->index),
 634         };
 635
 636         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 637         if (!drm_detect_monitor_audio(nv_connector->edid))
 638                 return;
 639
 640         memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
 641
 642         nvif_mthd(&disp->disp->object, 0, &args,
 643                   sizeof(args.base) + drm_eld_size(args.data));
 644         nv_encoder->audio = true;
 645
 646         nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or,
 647                                         nv_crtc->index);
 648 }
 649
 650 /******************************************************************************
 651  * HDMI
 652  *****************************************************************************/
 653 static void
 654 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 655 {
 656         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 657         struct nv50_disp *disp = nv50_disp(encoder->dev);
 658         struct {
 659                 struct nv50_disp_mthd_v1 base;
 660                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
 661         } args = {
 662                 .base.version = 1,
 663                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
 664                 .base.hasht  = nv_encoder->dcb->hasht,
 665                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
 666                                (0x0100 << nv_crtc->index),
 667         };
 668
 669         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 670 }
 671
 672 static void
 673 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
 674 {
 675         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 676         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 677         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 678         struct nv50_disp *disp = nv50_disp(encoder->dev);
 679         struct {
 680                 struct nv50_disp_mthd_v1 base;
 681                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
 682                 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */
 683         } args = {
 684                 .base.version = 1,
 685                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
 686                 .base.hasht  = nv_encoder->dcb->hasht,
 687                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
 688                                (0x0100 << nv_crtc->index),
 689                 .pwr.state = 1,
 690                 .pwr.rekey = 56, /* binary driver, and tegra, constant */
 691         };
 692         struct nouveau_connector *nv_connector;
 693         struct drm_hdmi_info *hdmi;
 694         u32 max_ac_packet;
 695         union hdmi_infoframe avi_frame;
 696         union hdmi_infoframe vendor_frame;
 697         bool high_tmds_clock_ratio = false, scrambling = false;
 698         u8 config;
 699         int ret;
 700         int size;
 701
 702         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 703         if (!drm_detect_hdmi_monitor(nv_connector->edid))
 704                 return;
 705
 706         hdmi = &nv_connector->base.display_info.hdmi;
 707
 708         ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi,
 709                                                        &nv_connector->base, mode);
 710         if (!ret) {
 711                 /* We have an AVI InfoFrame, populate it to the display */
 712                 args.pwr.avi_infoframe_length
 713                         = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17);
 714         }
 715
 716         ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi,
 717                                                           &nv_connector->base, mode);
 718         if (!ret) {
 719                 /* We have a Vendor InfoFrame, populate it to the display */
 720                 args.pwr.vendor_infoframe_length
 721                         = hdmi_infoframe_pack(&vendor_frame,
 722                                               args.infoframes
 723                                               + args.pwr.avi_infoframe_length,
 724                                               17);
 725         }
 726
 727         max_ac_packet  = mode->htotal - mode->hdisplay;
 728         max_ac_packet -= args.pwr.rekey;
 729         max_ac_packet -= 18; /* constant from tegra */
 730         args.pwr.max_ac_packet = max_ac_packet / 32;
 731
 732         if (hdmi->scdc.scrambling.supported) {
 733                 high_tmds_clock_ratio = mode->clock > 340000;
 734                 scrambling = high_tmds_clock_ratio ||
 735                         hdmi->scdc.scrambling.low_rates;
 736         }
 737
 738         args.pwr.scdc =
 739                 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling |
 740                 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio;
 741
 742         size = sizeof(args.base)
 743                 + sizeof(args.pwr)
 744                 + args.pwr.avi_infoframe_length
 745                 + args.pwr.vendor_infoframe_length;
 746         nvif_mthd(&disp->disp->object, 0, &args, size);
 747
 748         nv50_audio_enable(encoder, mode);
 749
 750         /* If SCDC is supported by the downstream monitor, update
 751          * divider / scrambling settings to what we programmed above.
 752          */
 753         if (!hdmi->scdc.scrambling.supported)
 754                 return;
 755
 756         ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config);
 757         if (ret < 0) {
 758                 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret);
 759                 return;
 760         }
 761         config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE);
 762         config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio;
 763         config |= SCDC_SCRAMBLING_ENABLE * scrambling;
 764         ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config);
 765         if (ret < 0)
 766                 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n",
 767                          config, ret);
 768 }
 769
 770 /******************************************************************************
 771  * MST
 772  *****************************************************************************/
 773 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
 774 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
 775 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
 776
 777 struct nv50_mstm {
 778         struct nouveau_encoder *outp;
 779
 780         struct drm_dp_mst_topology_mgr mgr;
 781
 782         bool modified;
 783         bool disabled;
 784         int links;
 785 };
 786
 787 struct nv50_mstc {
 788         struct nv50_mstm *mstm;
 789         struct drm_dp_mst_port *port;
 790         struct drm_connector connector;
 791
 792         struct drm_display_mode *native;
 793         struct edid *edid;
 794 };
 795
 796 struct nv50_msto {
 797         struct drm_encoder encoder;
 798
 799         struct nv50_head *head;
 800         struct nv50_mstc *mstc;
 801         bool disabled;
 802 };
 803
 804 static struct drm_dp_payload *
 805 nv50_msto_payload(struct nv50_msto *msto)
 806 {
 807         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 808         struct nv50_mstc *mstc = msto->mstc;
 809         struct nv50_mstm *mstm = mstc->mstm;
 810         int vcpi = mstc->port->vcpi.vcpi, i;
 811
 812         WARN_ON(!mutex_is_locked(&mstm->mgr.payload_lock));
 813
 814         NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
 815         for (i = 0; i < mstm->mgr.max_payloads; i++) {
 816                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
 817                 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
 818                           mstm->outp->base.base.name, i, payload->vcpi,
 819                           payload->start_slot, payload->num_slots);
 820         }
 821
 822         for (i = 0; i < mstm->mgr.max_payloads; i++) {
 823                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
 824                 if (payload->vcpi == vcpi)
 825                         return payload;
 826         }
 827
 828         return NULL;
 829 }
 830
 831 static void
 832 nv50_msto_cleanup(struct nv50_msto *msto)
 833 {
 834         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 835         struct nv50_mstc *mstc = msto->mstc;
 836         struct nv50_mstm *mstm = mstc->mstm;
 837
 838         if (!msto->disabled)
 839                 return;
 840
 841         NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
 842
 843         drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
 844
 845         msto->mstc = NULL;
 846         msto->disabled = false;
 847 }
 848
 849 static void
 850 nv50_msto_prepare(struct nv50_msto *msto)
 851 {
 852         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 853         struct nv50_mstc *mstc = msto->mstc;
 854         struct nv50_mstm *mstm = mstc->mstm;
 855         struct {
 856                 struct nv50_disp_mthd_v1 base;
 857                 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi;
 858         } args = {
 859                 .base.version = 1,
 860                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI,
 861                 .base.hasht  = mstm->outp->dcb->hasht,
 862                 .base.hashm  = (0xf0ff & mstm->outp->dcb->hashm) |
 863                                (0x0100 << msto->head->base.index),
 864         };
 865
 866         mutex_lock(&mstm->mgr.payload_lock);
 867
 868         NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
 869         if (mstc->port->vcpi.vcpi > 0) {
 870                 struct drm_dp_payload *payload = nv50_msto_payload(msto);
 871                 if (payload) {
 872                         args.vcpi.start_slot = payload->start_slot;
 873                         args.vcpi.num_slots = payload->num_slots;
 874                         args.vcpi.pbn = mstc->port->vcpi.pbn;
 875                         args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn;
 876                 }
 877         }
 878
 879         NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n",
 880                   msto->encoder.name, msto->head->base.base.name,
 881                   args.vcpi.start_slot, args.vcpi.num_slots,
 882                   args.vcpi.pbn, args.vcpi.aligned_pbn);
 883
 884         nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args));
 885         mutex_unlock(&mstm->mgr.payload_lock);
 886 }
 887
 888 static int
 889 nv50_msto_atomic_check(struct drm_encoder *encoder,
 890                        struct drm_crtc_state *crtc_state,
 891                        struct drm_connector_state *conn_state)
 892 {
 893         struct drm_atomic_state *state = crtc_state->state;
 894         struct drm_connector *connector = conn_state->connector;
 895         struct nv50_mstc *mstc = nv50_mstc(connector);
 896         struct nv50_mstm *mstm = mstc->mstm;
 897         struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
 898         int slots;
 899         int ret;
 900
 901         ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 902                                           mstc->native);
 903         if (ret)
 904                 return ret;
 905
 906         if (!crtc_state->mode_changed && !crtc_state->connectors_changed)
 907                 return 0;
 908
 909         /*
 910          * When restoring duplicated states, we need to make sure that the bw
 911          * remains the same and avoid recalculating it, as the connector's bpc
 912          * may have changed after the state was duplicated
 913          */
 914         if (!state->duplicated) {
 915                 const int clock = crtc_state->adjusted_mode.clock;
 916
 917                 asyh->or.bpc = connector->display_info.bpc;
 918                 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3,
 919                                                     false);
 920         }
 921
 922         slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr, mstc->port,
 923                                               asyh->dp.pbn, 0);
 924         if (slots < 0)
 925                 return slots;
 926
 927         asyh->dp.tu = slots;
 928
 929         return 0;
 930 }
 931
 932 static u8
 933 nv50_dp_bpc_to_depth(unsigned int bpc)
 934 {
 935         switch (bpc) {
 936         case  6: return 0x2;
 937         case  8: return 0x5;
 938         case 10: /* fall-through */
 939         default: return 0x6;
 940         }
 941 }
 942
 943 static void
 944 nv50_msto_enable(struct drm_encoder *encoder)
 945 {
 946         struct nv50_head *head = nv50_head(encoder->crtc);
 947         struct nv50_head_atom *armh = nv50_head_atom(head->base.base.state);
 948         struct nv50_msto *msto = nv50_msto(encoder);
 949         struct nv50_mstc *mstc = NULL;
 950         struct nv50_mstm *mstm = NULL;
 951         struct drm_connector *connector;
 952         struct drm_connector_list_iter conn_iter;
 953         u8 proto;
 954         bool r;
 955
 956         drm_connector_list_iter_begin(encoder->dev, &conn_iter);
 957         drm_for_each_connector_iter(connector, &conn_iter) {
 958                 if (connector->state->best_encoder == &msto->encoder) {
 959                         mstc = nv50_mstc(connector);
 960                         mstm = mstc->mstm;
 961                         break;
 962                 }
 963         }
 964         drm_connector_list_iter_end(&conn_iter);
 965
 966         if (WARN_ON(!mstc))
 967                 return;
 968
 969         r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, armh->dp.pbn,
 970                                      armh->dp.tu);
 971         if (!r)
 972                 DRM_DEBUG_KMS("Failed to allocate VCPI\n");
 973
 974         if (!mstm->links++)
 975                 nv50_outp_acquire(mstm->outp, false /*XXX: MST audio.*/);
 976
 977         if (mstm->outp->link & 1)
 978                 proto = 0x8;
 979         else
 980                 proto = 0x9;
 981
 982         mstm->outp->update(mstm->outp, head->base.index, armh, proto,
 983                            nv50_dp_bpc_to_depth(armh->or.bpc));
 984
 985         msto->mstc = mstc;
 986         mstm->modified = true;
 987 }
 988
 989 static void
 990 nv50_msto_disable(struct drm_encoder *encoder)
 991 {
 992         struct nv50_msto *msto = nv50_msto(encoder);
 993         struct nv50_mstc *mstc = msto->mstc;
 994         struct nv50_mstm *mstm = mstc->mstm;
 995
 996         drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
 997
 998         mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
 999         mstm->modified = true;
1000         if (!--mstm->links)
1001                 mstm->disabled = true;
1002         msto->disabled = true;
1003 }
1004
1005 static const struct drm_encoder_helper_funcs
1006 nv50_msto_help = {
1007         .disable = nv50_msto_disable,
1008         .enable = nv50_msto_enable,
1009         .atomic_check = nv50_msto_atomic_check,
1010 };
1011
1012 static void
1013 nv50_msto_destroy(struct drm_encoder *encoder)
1014 {
1015         struct nv50_msto *msto = nv50_msto(encoder);
1016         drm_encoder_cleanup(&msto->encoder);
1017         kfree(msto);
1018 }
1019
1020 static const struct drm_encoder_funcs
1021 nv50_msto = {
1022         .destroy = nv50_msto_destroy,
1023 };
1024
1025 static struct nv50_msto *
1026 nv50_msto_new(struct drm_device *dev, struct nv50_head *head, int id)
1027 {
1028         struct nv50_msto *msto;
1029         int ret;
1030
1031         msto = kzalloc(sizeof(*msto), GFP_KERNEL);
1032         if (!msto)
1033                 return ERR_PTR(-ENOMEM);
1034
1035         ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
1036                                DRM_MODE_ENCODER_DPMST, "mst-%d", id);
1037         if (ret) {
1038                 kfree(msto);
1039                 return ERR_PTR(ret);
1040         }
1041
1042         drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
1043         msto->encoder.possible_crtcs = drm_crtc_mask(&head->base.base);
1044         msto->head = head;
1045         return msto;
1046 }
1047
1048 static struct drm_encoder *
1049 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
1050                               struct drm_connector_state *connector_state)
1051 {
1052         struct nv50_mstc *mstc = nv50_mstc(connector);
1053         struct drm_crtc *crtc = connector_state->crtc;
1054
1055         if (!(mstc->mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
1056                 return NULL;
1057
1058         return &nv50_head(crtc)->msto->encoder;
1059 }
1060
1061 static enum drm_mode_status
1062 nv50_mstc_mode_valid(struct drm_connector *connector,
1063                      struct drm_display_mode *mode)
1064 {
1065         struct nv50_mstc *mstc = nv50_mstc(connector);
1066         struct nouveau_encoder *outp = mstc->mstm->outp;
1067
1068         /* TODO: calculate the PBN from the dotclock and validate against the
1069          * MSTB's max possible PBN
1070          */
1071
1072         return nv50_dp_mode_valid(connector, outp, mode, NULL);
1073 }
1074
1075 static int
1076 nv50_mstc_get_modes(struct drm_connector *connector)
1077 {
1078         struct nv50_mstc *mstc = nv50_mstc(connector);
1079         int ret = 0;
1080
1081         mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
1082         drm_connector_update_edid_property(&mstc->connector, mstc->edid);
1083         if (mstc->edid)
1084                 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
1085
1086         /*
1087          * XXX: Since we don't use HDR in userspace quite yet, limit the bpc
1088          * to 8 to save bandwidth on the topology. In the future, we'll want
1089          * to properly fix this by dynamically selecting the highest possible
1090          * bpc that would fit in the topology
1091          */
1092         if (connector->display_info.bpc)
1093                 connector->display_info.bpc =
1094                         clamp(connector->display_info.bpc, 6U, 8U);
1095         else
1096                 connector->display_info.bpc = 8;
1097
1098         if (mstc->native)
1099                 drm_mode_destroy(mstc->connector.dev, mstc->native);
1100         mstc->native = nouveau_conn_native_mode(&mstc->connector);
1101         return ret;
1102 }
1103
1104 static int
1105 nv50_mstc_atomic_check(struct drm_connector *connector,
1106                        struct drm_atomic_state *state)
1107 {
1108         struct nv50_mstc *mstc = nv50_mstc(connector);
1109         struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr;
1110         struct drm_connector_state *new_conn_state =
1111                 drm_atomic_get_new_connector_state(state, connector);
1112         struct drm_connector_state *old_conn_state =
1113                 drm_atomic_get_old_connector_state(state, connector);
1114         struct drm_crtc_state *crtc_state;
1115         struct drm_crtc *new_crtc = new_conn_state->crtc;
1116
1117         if (!old_conn_state->crtc)
1118                 return 0;
1119
1120         /* We only want to free VCPI if this state disables the CRTC on this
1121          * connector
1122          */
1123         if (new_crtc) {
1124                 crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc);
1125
1126                 if (!crtc_state ||
1127                     !drm_atomic_crtc_needs_modeset(crtc_state) ||
1128                     crtc_state->enable)
1129                         return 0;
1130         }
1131
1132         return drm_dp_atomic_release_vcpi_slots(state, mgr, mstc->port);
1133 }
1134
1135 static int
1136 nv50_mstc_detect(struct drm_connector *connector,
1137                  struct drm_modeset_acquire_ctx *ctx, bool force)
1138 {
1139         struct nv50_mstc *mstc = nv50_mstc(connector);
1140         int ret;
1141
1142         if (drm_connector_is_unregistered(connector))
1143                 return connector_status_disconnected;
1144
1145         ret = pm_runtime_get_sync(connector->dev->dev);
1146         if (ret < 0 && ret != -EACCES) {
1147                 pm_runtime_put_autosuspend(connector->dev->dev);
1148                 return connector_status_disconnected;
1149         }
1150
1151         ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr,
1152                                      mstc->port);
1153
1154         pm_runtime_mark_last_busy(connector->dev->dev);
1155         pm_runtime_put_autosuspend(connector->dev->dev);
1156         return ret;
1157 }
1158
1159 static const struct drm_connector_helper_funcs
1160 nv50_mstc_help = {
1161         .get_modes = nv50_mstc_get_modes,
1162         .mode_valid = nv50_mstc_mode_valid,
1163         .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
1164         .atomic_check = nv50_mstc_atomic_check,
1165         .detect_ctx = nv50_mstc_detect,
1166 };
1167
1168 static void
1169 nv50_mstc_destroy(struct drm_connector *connector)
1170 {
1171         struct nv50_mstc *mstc = nv50_mstc(connector);
1172
1173         drm_connector_cleanup(&mstc->connector);
1174         drm_dp_mst_put_port_malloc(mstc->port);
1175
1176         kfree(mstc);
1177 }
1178
1179 static const struct drm_connector_funcs
1180 nv50_mstc = {
1181         .reset = nouveau_conn_reset,
1182         .fill_modes = drm_helper_probe_single_connector_modes,
1183         .destroy = nv50_mstc_destroy,
1184         .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
1185         .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
1186         .atomic_set_property = nouveau_conn_atomic_set_property,
1187         .atomic_get_property = nouveau_conn_atomic_get_property,
1188 };
1189
1190 static int
1191 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
1192               const char *path, struct nv50_mstc **pmstc)
1193 {
1194         struct drm_device *dev = mstm->outp->base.base.dev;
1195         struct drm_crtc *crtc;
1196         struct nv50_mstc *mstc;
1197         int ret;
1198
1199         if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
1200                 return -ENOMEM;
1201         mstc->mstm = mstm;
1202         mstc->port = port;
1203
1204         ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
1205                                  DRM_MODE_CONNECTOR_DisplayPort);
1206         if (ret) {
1207                 kfree(*pmstc);
1208                 *pmstc = NULL;
1209                 return ret;
1210         }
1211
1212         drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
1213
1214         mstc->connector.funcs->reset(&mstc->connector);
1215         nouveau_conn_attach_properties(&mstc->connector);
1216
1217         drm_for_each_crtc(crtc, dev) {
1218                 if (!(mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
1219                         continue;
1220
1221                 drm_connector_attach_encoder(&mstc->connector,
1222                                              &nv50_head(crtc)->msto->encoder);
1223         }
1224
1225         drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
1226         drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
1227         drm_connector_set_path_property(&mstc->connector, path);
1228         drm_dp_mst_get_port_malloc(port);
1229         return 0;
1230 }
1231
1232 static void
1233 nv50_mstm_cleanup(struct nv50_mstm *mstm)
1234 {
1235         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1236         struct drm_encoder *encoder;
1237         int ret;
1238
1239         NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
1240         ret = drm_dp_check_act_status(&mstm->mgr);
1241
1242         ret = drm_dp_update_payload_part2(&mstm->mgr);
1243
1244         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1245                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1246                         struct nv50_msto *msto = nv50_msto(encoder);
1247                         struct nv50_mstc *mstc = msto->mstc;
1248                         if (mstc && mstc->mstm == mstm)
1249                                 nv50_msto_cleanup(msto);
1250                 }
1251         }
1252
1253         mstm->modified = false;
1254 }
1255
1256 static void
1257 nv50_mstm_prepare(struct nv50_mstm *mstm)
1258 {
1259         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1260         struct drm_encoder *encoder;
1261         int ret;
1262
1263         NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
1264         ret = drm_dp_update_payload_part1(&mstm->mgr);
1265
1266         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1267                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1268                         struct nv50_msto *msto = nv50_msto(encoder);
1269                         struct nv50_mstc *mstc = msto->mstc;
1270                         if (mstc && mstc->mstm == mstm)
1271                                 nv50_msto_prepare(msto);
1272                 }
1273         }
1274
1275         if (mstm->disabled) {
1276                 if (!mstm->links)
1277                         nv50_outp_release(mstm->outp);
1278                 mstm->disabled = false;
1279         }
1280 }
1281
1282 static struct drm_connector *
1283 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
1284                         struct drm_dp_mst_port *port, const char *path)
1285 {
1286         struct nv50_mstm *mstm = nv50_mstm(mgr);
1287         struct nv50_mstc *mstc;
1288         int ret;
1289
1290         ret = nv50_mstc_new(mstm, port, path, &mstc);
1291         if (ret)
1292                 return NULL;
1293
1294         return &mstc->connector;
1295 }
1296
1297 static const struct drm_dp_mst_topology_cbs
1298 nv50_mstm = {
1299         .add_connector = nv50_mstm_add_connector,
1300 };
1301
1302 void
1303 nv50_mstm_service(struct nv50_mstm *mstm)
1304 {
1305         struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL;
1306         bool handled = true;
1307         int ret;
1308         u8 esi[8] = {};
1309
1310         if (!aux)
1311                 return;
1312
1313         while (handled) {
1314                 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1315                 if (ret != 8) {
1316                         drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1317                         return;
1318                 }
1319
1320                 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
1321                 if (!handled)
1322                         break;
1323
1324                 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3);
1325         }
1326 }
1327
1328 void
1329 nv50_mstm_remove(struct nv50_mstm *mstm)
1330 {
1331         if (mstm)
1332                 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1333 }
1334
1335 static int
1336 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
1337 {
1338         struct nouveau_encoder *outp = mstm->outp;
1339         struct {
1340                 struct nv50_disp_mthd_v1 base;
1341                 struct nv50_disp_sor_dp_mst_link_v0 mst;
1342         } args = {
1343                 .base.version = 1,
1344                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
1345                 .base.hasht = outp->dcb->hasht,
1346                 .base.hashm = outp->dcb->hashm,
1347                 .mst.state = state,
1348         };
1349         struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
1350         struct nvif_object *disp = &drm->display->disp.object;
1351         int ret;
1352
1353         if (dpcd >= 0x12) {
1354                 /* Even if we're enabling MST, start with disabling the
1355                  * branching unit to clear any sink-side MST topology state
1356                  * that wasn't set by us
1357                  */
1358                 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 0);
1359                 if (ret < 0)
1360                         return ret;
1361
1362                 if (state) {
1363                         /* Now, start initializing */
1364                         ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL,
1365                                                  DP_MST_EN);
1366                         if (ret < 0)
1367                                 return ret;
1368                 }
1369         }
1370
1371         return nvif_mthd(disp, 0, &args, sizeof(args));
1372 }
1373
1374 int
1375 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
1376 {
1377         struct drm_dp_aux *aux;
1378         int ret;
1379         bool old_state, new_state;
1380         u8 mstm_ctrl;
1381
1382         if (!mstm)
1383                 return 0;
1384
1385         mutex_lock(&mstm->mgr.lock);
1386
1387         old_state = mstm->mgr.mst_state;
1388         new_state = old_state;
1389         aux = mstm->mgr.aux;
1390
1391         if (old_state) {
1392                 /* Just check that the MST hub is still as we expect it */
1393                 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CTRL, &mstm_ctrl);
1394                 if (ret < 0 || !(mstm_ctrl & DP_MST_EN)) {
1395                         DRM_DEBUG_KMS("Hub gone, disabling MST topology\n");
1396                         new_state = false;
1397                 }
1398         } else if (dpcd[0] >= 0x12) {
1399                 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &dpcd[1]);
1400                 if (ret < 0)
1401                         goto probe_error;
1402
1403                 if (!(dpcd[1] & DP_MST_CAP))
1404                         dpcd[0] = 0x11;
1405                 else
1406                         new_state = allow;
1407         }
1408
1409         if (new_state == old_state) {
1410                 mutex_unlock(&mstm->mgr.lock);
1411                 return new_state;
1412         }
1413
1414         ret = nv50_mstm_enable(mstm, dpcd[0], new_state);
1415         if (ret)
1416                 goto probe_error;
1417
1418         mutex_unlock(&mstm->mgr.lock);
1419
1420         ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, new_state);
1421         if (ret)
1422                 return nv50_mstm_enable(mstm, dpcd[0], 0);
1423
1424         return new_state;
1425
1426 probe_error:
1427         mutex_unlock(&mstm->mgr.lock);
1428         return ret;
1429 }
1430
1431 static void
1432 nv50_mstm_fini(struct nv50_mstm *mstm)
1433 {
1434         if (mstm && mstm->mgr.mst_state)
1435                 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
1436 }
1437
1438 static void
1439 nv50_mstm_init(struct nv50_mstm *mstm, bool runtime)
1440 {
1441         int ret;
1442
1443         if (!mstm || !mstm->mgr.mst_state)
1444                 return;
1445
1446         ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr, !runtime);
1447         if (ret == -1) {
1448                 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1449                 drm_kms_helper_hotplug_event(mstm->mgr.dev);
1450         }
1451 }
1452
1453 static void
1454 nv50_mstm_del(struct nv50_mstm **pmstm)
1455 {
1456         struct nv50_mstm *mstm = *pmstm;
1457         if (mstm) {
1458                 drm_dp_mst_topology_mgr_destroy(&mstm->mgr);
1459                 kfree(*pmstm);
1460                 *pmstm = NULL;
1461         }
1462 }
1463
1464 static int
1465 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
1466               int conn_base_id, struct nv50_mstm **pmstm)
1467 {
1468         const int max_payloads = hweight8(outp->dcb->heads);
1469         struct drm_device *dev = outp->base.base.dev;
1470         struct nv50_mstm *mstm;
1471         int ret;
1472         u8 dpcd;
1473
1474         /* This is a workaround for some monitors not functioning
1475          * correctly in MST mode on initial module load.  I think
1476          * some bad interaction with the VBIOS may be responsible.
1477          *
1478          * A good ol' off and on again seems to work here ;)
1479          */
1480         ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd);
1481         if (ret >= 0 && dpcd >= 0x12)
1482                 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
1483
1484         if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
1485                 return -ENOMEM;
1486         mstm->outp = outp;
1487         mstm->mgr.cbs = &nv50_mstm;
1488
1489         ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
1490                                            max_payloads, conn_base_id);
1491         if (ret)
1492                 return ret;
1493
1494         return 0;
1495 }
1496
1497 /******************************************************************************
1498  * SOR
1499  *****************************************************************************/
1500 static void
1501 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
1502                 struct nv50_head_atom *asyh, u8 proto, u8 depth)
1503 {
1504         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
1505         struct nv50_core *core = disp->core;
1506
1507         if (!asyh) {
1508                 nv_encoder->ctrl &= ~BIT(head);
1509                 if (!(nv_encoder->ctrl & 0x0000000f))
1510                         nv_encoder->ctrl = 0;
1511         } else {
1512                 nv_encoder->ctrl |= proto << 8;
1513                 nv_encoder->ctrl |= BIT(head);
1514                 asyh->or.depth = depth;
1515         }
1516
1517         core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh);
1518 }
1519
1520 static void
1521 nv50_sor_disable(struct drm_encoder *encoder)
1522 {
1523         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1524         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1525
1526         nv_encoder->crtc = NULL;
1527
1528         if (nv_crtc) {
1529                 struct nvkm_i2c_aux *aux = nv_encoder->aux;
1530                 u8 pwr;
1531
1532                 if (aux) {
1533                         int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1);
1534                         if (ret == 0) {
1535                                 pwr &= ~DP_SET_POWER_MASK;
1536                                 pwr |=  DP_SET_POWER_D3;
1537                                 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1);
1538                         }
1539                 }
1540
1541                 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
1542                 nv50_audio_disable(encoder, nv_crtc);
1543                 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
1544                 nv50_outp_release(nv_encoder);
1545         }
1546 }
1547
1548 static void
1549 nv50_sor_enable(struct drm_encoder *encoder)
1550 {
1551         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1552         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1553         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1554         struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1555         struct {
1556                 struct nv50_disp_mthd_v1 base;
1557                 struct nv50_disp_sor_lvds_script_v0 lvds;
1558         } lvds = {
1559                 .base.version = 1,
1560                 .base.method  = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1561                 .base.hasht   = nv_encoder->dcb->hasht,
1562                 .base.hashm   = nv_encoder->dcb->hashm,
1563         };
1564         struct nv50_disp *disp = nv50_disp(encoder->dev);
1565         struct drm_device *dev = encoder->dev;
1566         struct nouveau_drm *drm = nouveau_drm(dev);
1567         struct nouveau_connector *nv_connector;
1568         struct nvbios *bios = &drm->vbios;
1569         bool hda = false;
1570         u8 proto = 0xf;
1571         u8 depth = 0x0;
1572
1573         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1574         nv_encoder->crtc = encoder->crtc;
1575
1576         if ((disp->disp->object.oclass == GT214_DISP ||
1577              disp->disp->object.oclass >= GF110_DISP) &&
1578             drm_detect_monitor_audio(nv_connector->edid))
1579                 hda = true;
1580         nv50_outp_acquire(nv_encoder, hda);
1581
1582         switch (nv_encoder->dcb->type) {
1583         case DCB_OUTPUT_TMDS:
1584                 if (nv_encoder->link & 1) {
1585                         proto = 0x1;
1586                         /* Only enable dual-link if:
1587                          *  - Need to (i.e. rate > 165MHz)
1588                          *  - DCB says we can
1589                          *  - Not an HDMI monitor, since there's no dual-link
1590                          *    on HDMI.
1591                          */
1592                         if (mode->clock >= 165000 &&
1593                             nv_encoder->dcb->duallink_possible &&
1594                             !drm_detect_hdmi_monitor(nv_connector->edid))
1595                                 proto |= 0x4;
1596                 } else {
1597                         proto = 0x2;
1598                 }
1599
1600                 nv50_hdmi_enable(&nv_encoder->base.base, mode);
1601                 break;
1602         case DCB_OUTPUT_LVDS:
1603                 proto = 0x0;
1604
1605                 if (bios->fp_no_ddc) {
1606                         if (bios->fp.dual_link)
1607                                 lvds.lvds.script |= 0x0100;
1608                         if (bios->fp.if_is_24bit)
1609                                 lvds.lvds.script |= 0x0200;
1610                 } else {
1611                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1612                                 if (((u8 *)nv_connector->edid)[121] == 2)
1613                                         lvds.lvds.script |= 0x0100;
1614                         } else
1615                         if (mode->clock >= bios->fp.duallink_transition_clk) {
1616                                 lvds.lvds.script |= 0x0100;
1617                         }
1618
1619                         if (lvds.lvds.script & 0x0100) {
1620                                 if (bios->fp.strapless_is_24bit & 2)
1621                                         lvds.lvds.script |= 0x0200;
1622                         } else {
1623                                 if (bios->fp.strapless_is_24bit & 1)
1624                                         lvds.lvds.script |= 0x0200;
1625                         }
1626
1627                         if (asyh->or.bpc == 8)
1628                                 lvds.lvds.script |= 0x0200;
1629                 }
1630
1631                 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds));
1632                 break;
1633         case DCB_OUTPUT_DP:
1634                 depth = nv50_dp_bpc_to_depth(asyh->or.bpc);
1635
1636                 if (nv_encoder->link & 1)
1637                         proto = 0x8;
1638                 else
1639                         proto = 0x9;
1640
1641                 nv50_audio_enable(encoder, mode);
1642                 break;
1643         default:
1644                 BUG();
1645                 break;
1646         }
1647
1648         nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
1649 }
1650
1651 static const struct drm_encoder_helper_funcs
1652 nv50_sor_help = {
1653         .atomic_check = nv50_outp_atomic_check,
1654         .enable = nv50_sor_enable,
1655         .disable = nv50_sor_disable,
1656 };
1657
1658 static void
1659 nv50_sor_destroy(struct drm_encoder *encoder)
1660 {
1661         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1662         nv50_mstm_del(&nv_encoder->dp.mstm);
1663         drm_encoder_cleanup(encoder);
1664         kfree(encoder);
1665 }
1666
1667 static const struct drm_encoder_funcs
1668 nv50_sor_func = {
1669         .destroy = nv50_sor_destroy,
1670 };
1671
1672 static bool nv50_has_mst(struct nouveau_drm *drm)
1673 {
1674         struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
1675         u32 data;
1676         u8 ver, hdr, cnt, len;
1677
1678         data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len);
1679         return data && ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04);
1680 }
1681
1682 static int
1683 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1684 {
1685         struct nouveau_connector *nv_connector = nouveau_connector(connector);
1686         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1687         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1688         struct nouveau_encoder *nv_encoder;
1689         struct drm_encoder *encoder;
1690         struct nv50_disp *disp = nv50_disp(connector->dev);
1691         int type, ret;
1692
1693         switch (dcbe->type) {
1694         case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1695         case DCB_OUTPUT_TMDS:
1696         case DCB_OUTPUT_DP:
1697         default:
1698                 type = DRM_MODE_ENCODER_TMDS;
1699                 break;
1700         }
1701
1702         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1703         if (!nv_encoder)
1704                 return -ENOMEM;
1705         nv_encoder->dcb = dcbe;
1706         nv_encoder->update = nv50_sor_update;
1707
1708         encoder = to_drm_encoder(nv_encoder);
1709         encoder->possible_crtcs = dcbe->heads;
1710         encoder->possible_clones = 0;
1711         drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
1712                          "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
1713         drm_encoder_helper_add(encoder, &nv50_sor_help);
1714
1715         drm_connector_attach_encoder(connector, encoder);
1716
1717         disp->core->func->sor->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1);
1718
1719         if (dcbe->type == DCB_OUTPUT_DP) {
1720                 struct nvkm_i2c_aux *aux =
1721                         nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
1722
1723                 if (aux) {
1724                         if (disp->disp->object.oclass < GF110_DISP) {
1725                                 /* HW has no support for address-only
1726                                  * transactions, so we're required to
1727                                  * use custom I2C-over-AUX code.
1728                                  */
1729                                 nv_encoder->i2c = &aux->i2c;
1730                         } else {
1731                                 nv_encoder->i2c = &nv_connector->aux.ddc;
1732                         }
1733                         nv_encoder->aux = aux;
1734                 }
1735
1736                 if (nv_connector->type != DCB_CONNECTOR_eDP &&
1737                     nv50_has_mst(drm)) {
1738                         ret = nv50_mstm_new(nv_encoder, &nv_connector->aux,
1739                                             16, nv_connector->base.base.id,
1740                                             &nv_encoder->dp.mstm);
1741                         if (ret)
1742                                 return ret;
1743                 }
1744         } else {
1745                 struct nvkm_i2c_bus *bus =
1746                         nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1747                 if (bus)
1748                         nv_encoder->i2c = &bus->i2c;
1749         }
1750
1751         return 0;
1752 }
1753
1754 /******************************************************************************
1755  * PIOR
1756  *****************************************************************************/
1757 static int
1758 nv50_pior_atomic_check(struct drm_encoder *encoder,
1759                        struct drm_crtc_state *crtc_state,
1760                        struct drm_connector_state *conn_state)
1761 {
1762         int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
1763         if (ret)
1764                 return ret;
1765         crtc_state->adjusted_mode.clock *= 2;
1766         return 0;
1767 }
1768
1769 static void
1770 nv50_pior_disable(struct drm_encoder *encoder)
1771 {
1772         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1773         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1774         if (nv_encoder->crtc)
1775                 core->func->pior->ctrl(core, nv_encoder->or, 0x00000000, NULL);
1776         nv_encoder->crtc = NULL;
1777         nv50_outp_release(nv_encoder);
1778 }
1779
1780 static void
1781 nv50_pior_enable(struct drm_encoder *encoder)
1782 {
1783         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1784         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1785         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1786         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1787         u8 owner = 1 << nv_crtc->index;
1788         u8 proto;
1789
1790         nv50_outp_acquire(nv_encoder, false);
1791
1792         switch (asyh->or.bpc) {
1793         case 10: asyh->or.depth = 0x6; break;
1794         case  8: asyh->or.depth = 0x5; break;
1795         case  6: asyh->or.depth = 0x2; break;
1796         default: asyh->or.depth = 0x0; break;
1797         }
1798
1799         switch (nv_encoder->dcb->type) {
1800         case DCB_OUTPUT_TMDS:
1801         case DCB_OUTPUT_DP:
1802                 proto = 0x0;
1803                 break;
1804         default:
1805                 BUG();
1806                 break;
1807         }
1808
1809         core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) | owner, asyh);
1810         nv_encoder->crtc = encoder->crtc;
1811 }
1812
1813 static const struct drm_encoder_helper_funcs
1814 nv50_pior_help = {
1815         .atomic_check = nv50_pior_atomic_check,
1816         .enable = nv50_pior_enable,
1817         .disable = nv50_pior_disable,
1818 };
1819
1820 static void
1821 nv50_pior_destroy(struct drm_encoder *encoder)
1822 {
1823         drm_encoder_cleanup(encoder);
1824         kfree(encoder);
1825 }
1826
1827 static const struct drm_encoder_funcs
1828 nv50_pior_func = {
1829         .destroy = nv50_pior_destroy,
1830 };
1831
1832 static int
1833 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
1834 {
1835         struct drm_device *dev = connector->dev;
1836         struct nouveau_drm *drm = nouveau_drm(dev);
1837         struct nv50_disp *disp = nv50_disp(dev);
1838         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1839         struct nvkm_i2c_bus *bus = NULL;
1840         struct nvkm_i2c_aux *aux = NULL;
1841         struct i2c_adapter *ddc;
1842         struct nouveau_encoder *nv_encoder;
1843         struct drm_encoder *encoder;
1844         int type;
1845
1846         switch (dcbe->type) {
1847         case DCB_OUTPUT_TMDS:
1848                 bus  = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
1849                 ddc  = bus ? &bus->i2c : NULL;
1850                 type = DRM_MODE_ENCODER_TMDS;
1851                 break;
1852         case DCB_OUTPUT_DP:
1853                 aux  = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
1854                 ddc  = aux ? &aux->i2c : NULL;
1855                 type = DRM_MODE_ENCODER_TMDS;
1856                 break;
1857         default:
1858                 return -ENODEV;
1859         }
1860
1861         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1862         if (!nv_encoder)
1863                 return -ENOMEM;
1864         nv_encoder->dcb = dcbe;
1865         nv_encoder->i2c = ddc;
1866         nv_encoder->aux = aux;
1867
1868         encoder = to_drm_encoder(nv_encoder);
1869         encoder->possible_crtcs = dcbe->heads;
1870         encoder->possible_clones = 0;
1871         drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
1872                          "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
1873         drm_encoder_helper_add(encoder, &nv50_pior_help);
1874
1875         drm_connector_attach_encoder(connector, encoder);
1876
1877         disp->core->func->pior->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1);
1878
1879         return 0;
1880 }
1881
1882 /******************************************************************************
1883  * Atomic
1884  *****************************************************************************/
1885
1886 static void
1887 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock)
1888 {
1889         struct nouveau_drm *drm = nouveau_drm(state->dev);
1890         struct nv50_disp *disp = nv50_disp(drm->dev);
1891         struct nv50_core *core = disp->core;
1892         struct nv50_mstm *mstm;
1893         struct drm_encoder *encoder;
1894
1895         NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]);
1896
1897         drm_for_each_encoder(encoder, drm->dev) {
1898                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1899                         mstm = nouveau_encoder(encoder)->dp.mstm;
1900                         if (mstm && mstm->modified)
1901                                 nv50_mstm_prepare(mstm);
1902                 }
1903         }
1904
1905         core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY);
1906         core->func->update(core, interlock, true);
1907         if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY,
1908                                        disp->core->chan.base.device))
1909                 NV_ERROR(drm, "core notifier timeout\n");
1910
1911         drm_for_each_encoder(encoder, drm->dev) {
1912                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1913                         mstm = nouveau_encoder(encoder)->dp.mstm;
1914                         if (mstm && mstm->modified)
1915                                 nv50_mstm_cleanup(mstm);
1916                 }
1917         }
1918 }
1919
1920 static void
1921 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock)
1922 {
1923         struct drm_plane_state *new_plane_state;
1924         struct drm_plane *plane;
1925         int i;
1926
1927         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1928                 struct nv50_wndw *wndw = nv50_wndw(plane);
1929                 if (interlock[wndw->interlock.type] & wndw->interlock.data) {
1930                         if (wndw->func->update)
1931                                 wndw->func->update(wndw, interlock);
1932                 }
1933         }
1934 }
1935
1936 static void
1937 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
1938 {
1939         struct drm_device *dev = state->dev;
1940         struct drm_crtc_state *new_crtc_state, *old_crtc_state;
1941         struct drm_crtc *crtc;
1942         struct drm_plane_state *new_plane_state;
1943         struct drm_plane *plane;
1944         struct nouveau_drm *drm = nouveau_drm(dev);
1945         struct nv50_disp *disp = nv50_disp(dev);
1946         struct nv50_atom *atom = nv50_atom(state);
1947         struct nv50_core *core = disp->core;
1948         struct nv50_outp_atom *outp, *outt;
1949         u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {};
1950         int i;
1951
1952         NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
1953         drm_atomic_helper_wait_for_fences(dev, state, false);
1954         drm_atomic_helper_wait_for_dependencies(state);
1955         drm_atomic_helper_update_legacy_modeset_state(dev, state);
1956
1957         if (atom->lock_core)
1958                 mutex_lock(&disp->mutex);
1959
1960         /* Disable head(s). */
1961         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1962                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1963                 struct nv50_head *head = nv50_head(crtc);
1964
1965                 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
1966                           asyh->clr.mask, asyh->set.mask);
1967
1968                 if (old_crtc_state->active && !new_crtc_state->active) {
1969                         pm_runtime_put_noidle(dev->dev);
1970                         drm_crtc_vblank_off(crtc);
1971                 }
1972
1973                 if (asyh->clr.mask) {
1974                         nv50_head_flush_clr(head, asyh, atom->flush_disable);
1975                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1976                 }
1977         }
1978
1979         /* Disable plane(s). */
1980         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1981                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1982                 struct nv50_wndw *wndw = nv50_wndw(plane);
1983
1984                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
1985                           asyw->clr.mask, asyw->set.mask);
1986                 if (!asyw->clr.mask)
1987                         continue;
1988
1989                 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw);
1990         }
1991
1992         /* Disable output path(s). */
1993         list_for_each_entry(outp, &atom->outp, head) {
1994                 const struct drm_encoder_helper_funcs *help;
1995                 struct drm_encoder *encoder;
1996
1997                 encoder = outp->encoder;
1998                 help = encoder->helper_private;
1999
2000                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
2001                           outp->clr.mask, outp->set.mask);
2002
2003                 if (outp->clr.mask) {
2004                         help->disable(encoder);
2005                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
2006                         if (outp->flush_disable) {
2007                                 nv50_disp_atomic_commit_wndw(state, interlock);
2008                                 nv50_disp_atomic_commit_core(state, interlock);
2009                                 memset(interlock, 0x00, sizeof(interlock));
2010                         }
2011                 }
2012         }
2013
2014         /* Flush disable. */
2015         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
2016                 if (atom->flush_disable) {
2017                         nv50_disp_atomic_commit_wndw(state, interlock);
2018                         nv50_disp_atomic_commit_core(state, interlock);
2019                         memset(interlock, 0x00, sizeof(interlock));
2020                 }
2021         }
2022
2023         /* Update output path(s). */
2024         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2025                 const struct drm_encoder_helper_funcs *help;
2026                 struct drm_encoder *encoder;
2027
2028                 encoder = outp->encoder;
2029                 help = encoder->helper_private;
2030
2031                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
2032                           outp->set.mask, outp->clr.mask);
2033
2034                 if (outp->set.mask) {
2035                         help->enable(encoder);
2036                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
2037                 }
2038
2039                 list_del(&outp->head);
2040                 kfree(outp);
2041         }
2042
2043         /* Update head(s). */
2044         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
2045                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2046                 struct nv50_head *head = nv50_head(crtc);
2047
2048                 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
2049                           asyh->set.mask, asyh->clr.mask);
2050
2051                 if (asyh->set.mask) {
2052                         nv50_head_flush_set(head, asyh);
2053                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
2054                 }
2055
2056                 if (new_crtc_state->active) {
2057                         if (!old_crtc_state->active) {
2058                                 drm_crtc_vblank_on(crtc);
2059                                 pm_runtime_get_noresume(dev->dev);
2060                         }
2061                         if (new_crtc_state->event)
2062                                 drm_crtc_vblank_get(crtc);
2063                 }
2064         }
2065
2066         /* Update window->head assignment.
2067          *
2068          * This has to happen in an update that's not interlocked with
2069          * any window channels to avoid hitting HW error checks.
2070          *
2071          *TODO: Proper handling of window ownership (Turing apparently
2072          *      supports non-fixed mappings).
2073          */
2074         if (core->assign_windows) {
2075                 core->func->wndw.owner(core);
2076                 nv50_disp_atomic_commit_core(state, interlock);
2077                 core->assign_windows = false;
2078                 interlock[NV50_DISP_INTERLOCK_CORE] = 0;
2079         }
2080
2081         /* Update plane(s). */
2082         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2083                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2084                 struct nv50_wndw *wndw = nv50_wndw(plane);
2085
2086                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
2087                           asyw->set.mask, asyw->clr.mask);
2088                 if ( !asyw->set.mask &&
2089                     (!asyw->clr.mask || atom->flush_disable))
2090                         continue;
2091
2092                 nv50_wndw_flush_set(wndw, interlock, asyw);
2093         }
2094
2095         /* Flush update. */
2096         nv50_disp_atomic_commit_wndw(state, interlock);
2097
2098         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
2099                 if (interlock[NV50_DISP_INTERLOCK_BASE] ||
2100                     interlock[NV50_DISP_INTERLOCK_OVLY] ||
2101                     interlock[NV50_DISP_INTERLOCK_WNDW] ||
2102                     !atom->state.legacy_cursor_update)
2103                         nv50_disp_atomic_commit_core(state, interlock);
2104                 else
2105                         disp->core->func->update(disp->core, interlock, false);
2106         }
2107
2108         if (atom->lock_core)
2109                 mutex_unlock(&disp->mutex);
2110
2111         /* Wait for HW to signal completion. */
2112         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2113                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2114                 struct nv50_wndw *wndw = nv50_wndw(plane);
2115                 int ret = nv50_wndw_wait_armed(wndw, asyw);
2116                 if (ret)
2117                         NV_ERROR(drm, "%s: timeout\n", plane->name);
2118         }
2119
2120         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2121                 if (new_crtc_state->event) {
2122                         unsigned long flags;
2123                         /* Get correct count/ts if racing with vblank irq */
2124                         if (new_crtc_state->active)
2125                                 drm_crtc_accurate_vblank_count(crtc);
2126                         spin_lock_irqsave(&crtc->dev->event_lock, flags);
2127                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
2128                         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
2129
2130                         new_crtc_state->event = NULL;
2131                         if (new_crtc_state->active)
2132                                 drm_crtc_vblank_put(crtc);
2133                 }
2134         }
2135
2136         drm_atomic_helper_commit_hw_done(state);
2137         drm_atomic_helper_cleanup_planes(dev, state);
2138         drm_atomic_helper_commit_cleanup_done(state);
2139         drm_atomic_state_put(state);
2140
2141         /* Drop the RPM ref we got from nv50_disp_atomic_commit() */
2142         pm_runtime_mark_last_busy(dev->dev);
2143         pm_runtime_put_autosuspend(dev->dev);
2144 }
2145
2146 static void
2147 nv50_disp_atomic_commit_work(struct work_struct *work)
2148 {
2149         struct drm_atomic_state *state =
2150                 container_of(work, typeof(*state), commit_work);
2151         nv50_disp_atomic_commit_tail(state);
2152 }
2153
2154 static int
2155 nv50_disp_atomic_commit(struct drm_device *dev,
2156                         struct drm_atomic_state *state, bool nonblock)
2157 {
2158         struct drm_plane_state *new_plane_state;
2159         struct drm_plane *plane;
2160         int ret, i;
2161
2162         ret = pm_runtime_get_sync(dev->dev);
2163         if (ret < 0 && ret != -EACCES)
2164                 return ret;
2165
2166         ret = drm_atomic_helper_setup_commit(state, nonblock);
2167         if (ret)
2168                 goto done;
2169
2170         INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
2171
2172         ret = drm_atomic_helper_prepare_planes(dev, state);
2173         if (ret)
2174                 goto done;
2175
2176         if (!nonblock) {
2177                 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
2178                 if (ret)
2179                         goto err_cleanup;
2180         }
2181
2182         ret = drm_atomic_helper_swap_state(state, true);
2183         if (ret)
2184                 goto err_cleanup;
2185
2186         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2187                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2188                 struct nv50_wndw *wndw = nv50_wndw(plane);
2189
2190                 if (asyw->set.image)
2191                         nv50_wndw_ntfy_enable(wndw, asyw);
2192         }
2193
2194         drm_atomic_state_get(state);
2195
2196         /*
2197          * Grab another RPM ref for the commit tail, which will release the
2198          * ref when it's finished
2199          */
2200         pm_runtime_get_noresume(dev->dev);
2201
2202         if (nonblock)
2203                 queue_work(system_unbound_wq, &state->commit_work);
2204         else
2205                 nv50_disp_atomic_commit_tail(state);
2206
2207 err_cleanup:
2208         if (ret)
2209                 drm_atomic_helper_cleanup_planes(dev, state);
2210 done:
2211         pm_runtime_put_autosuspend(dev->dev);
2212         return ret;
2213 }
2214
2215 static struct nv50_outp_atom *
2216 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
2217 {
2218         struct nv50_outp_atom *outp;
2219
2220         list_for_each_entry(outp, &atom->outp, head) {
2221                 if (outp->encoder == encoder)
2222                         return outp;
2223         }
2224
2225         outp = kzalloc(sizeof(*outp), GFP_KERNEL);
2226         if (!outp)
2227                 return ERR_PTR(-ENOMEM);
2228
2229         list_add(&outp->head, &atom->outp);
2230         outp->encoder = encoder;
2231         return outp;
2232 }
2233
2234 static int
2235 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
2236                                 struct drm_connector_state *old_connector_state)
2237 {
2238         struct drm_encoder *encoder = old_connector_state->best_encoder;
2239         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
2240         struct drm_crtc *crtc;
2241         struct nv50_outp_atom *outp;
2242
2243         if (!(crtc = old_connector_state->crtc))
2244                 return 0;
2245
2246         old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
2247         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2248         if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2249                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2250                 if (IS_ERR(outp))
2251                         return PTR_ERR(outp);
2252
2253                 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
2254                         outp->flush_disable = true;
2255                         atom->flush_disable = true;
2256                 }
2257                 outp->clr.ctrl = true;
2258                 atom->lock_core = true;
2259         }
2260
2261         return 0;
2262 }
2263
2264 static int
2265 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
2266                                 struct drm_connector_state *connector_state)
2267 {
2268         struct drm_encoder *encoder = connector_state->best_encoder;
2269         struct drm_crtc_state *new_crtc_state;
2270         struct drm_crtc *crtc;
2271         struct nv50_outp_atom *outp;
2272
2273         if (!(crtc = connector_state->crtc))
2274                 return 0;
2275
2276         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2277         if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2278                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2279                 if (IS_ERR(outp))
2280                         return PTR_ERR(outp);
2281
2282                 outp->set.ctrl = true;
2283                 atom->lock_core = true;
2284         }
2285
2286         return 0;
2287 }
2288
2289 static int
2290 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
2291 {
2292         struct nv50_atom *atom = nv50_atom(state);
2293         struct drm_connector_state *old_connector_state, *new_connector_state;
2294         struct drm_connector *connector;
2295         struct drm_crtc_state *new_crtc_state;
2296         struct drm_crtc *crtc;
2297         int ret, i;
2298
2299         /* We need to handle colour management on a per-plane basis. */
2300         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2301                 if (new_crtc_state->color_mgmt_changed) {
2302                         ret = drm_atomic_add_affected_planes(state, crtc);
2303                         if (ret)
2304                                 return ret;
2305                 }
2306         }
2307
2308         ret = drm_atomic_helper_check(dev, state);
2309         if (ret)
2310                 return ret;
2311
2312         for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
2313                 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state);
2314                 if (ret)
2315                         return ret;
2316
2317                 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state);
2318                 if (ret)
2319                         return ret;
2320         }
2321
2322         ret = drm_dp_mst_atomic_check(state);
2323         if (ret)
2324                 return ret;
2325
2326         return 0;
2327 }
2328
2329 static void
2330 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
2331 {
2332         struct nv50_atom *atom = nv50_atom(state);
2333         struct nv50_outp_atom *outp, *outt;
2334
2335         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2336                 list_del(&outp->head);
2337                 kfree(outp);
2338         }
2339
2340         drm_atomic_state_default_clear(state);
2341 }
2342
2343 static void
2344 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
2345 {
2346         struct nv50_atom *atom = nv50_atom(state);
2347         drm_atomic_state_default_release(&atom->state);
2348         kfree(atom);
2349 }
2350
2351 static struct drm_atomic_state *
2352 nv50_disp_atomic_state_alloc(struct drm_device *dev)
2353 {
2354         struct nv50_atom *atom;
2355         if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
2356             drm_atomic_state_init(dev, &atom->state) < 0) {
2357                 kfree(atom);
2358                 return NULL;
2359         }
2360         INIT_LIST_HEAD(&atom->outp);
2361         return &atom->state;
2362 }
2363
2364 static const struct drm_mode_config_funcs
2365 nv50_disp_func = {
2366         .fb_create = nouveau_user_framebuffer_create,
2367         .output_poll_changed = nouveau_fbcon_output_poll_changed,
2368         .atomic_check = nv50_disp_atomic_check,
2369         .atomic_commit = nv50_disp_atomic_commit,
2370         .atomic_state_alloc = nv50_disp_atomic_state_alloc,
2371         .atomic_state_clear = nv50_disp_atomic_state_clear,
2372         .atomic_state_free = nv50_disp_atomic_state_free,
2373 };
2374
2375 /******************************************************************************
2376  * Init
2377  *****************************************************************************/
2378
2379 static void
2380 nv50_display_fini(struct drm_device *dev, bool suspend)
2381 {
2382         struct nouveau_encoder *nv_encoder;
2383         struct drm_encoder *encoder;
2384         struct drm_plane *plane;
2385
2386         drm_for_each_plane(plane, dev) {
2387                 struct nv50_wndw *wndw = nv50_wndw(plane);
2388                 if (plane->funcs != &nv50_wndw)
2389                         continue;
2390                 nv50_wndw_fini(wndw);
2391         }
2392
2393         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2394                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2395                         nv_encoder = nouveau_encoder(encoder);
2396                         nv50_mstm_fini(nv_encoder->dp.mstm);
2397                 }
2398         }
2399 }
2400
2401 static int
2402 nv50_display_init(struct drm_device *dev, bool resume, bool runtime)
2403 {
2404         struct nv50_core *core = nv50_disp(dev)->core;
2405         struct drm_encoder *encoder;
2406         struct drm_plane *plane;
2407
2408         if (resume || runtime)
2409                 core->func->init(core);
2410
2411         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2412                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2413                         struct nouveau_encoder *nv_encoder =
2414                                 nouveau_encoder(encoder);
2415                         nv50_mstm_init(nv_encoder->dp.mstm, runtime);
2416                 }
2417         }
2418
2419         drm_for_each_plane(plane, dev) {
2420                 struct nv50_wndw *wndw = nv50_wndw(plane);
2421                 if (plane->funcs != &nv50_wndw)
2422                         continue;
2423                 nv50_wndw_init(wndw);
2424         }
2425
2426         return 0;
2427 }
2428
2429 static void
2430 nv50_display_destroy(struct drm_device *dev)
2431 {
2432         struct nv50_disp *disp = nv50_disp(dev);
2433
2434         nv50_audio_component_fini(nouveau_drm(dev));
2435
2436         nvif_object_unmap(&disp->caps);
2437         nvif_object_fini(&disp->caps);
2438         nv50_core_del(&disp->core);
2439
2440         nouveau_bo_unmap(disp->sync);
2441         if (disp->sync)
2442                 nouveau_bo_unpin(disp->sync);
2443         nouveau_bo_ref(NULL, &disp->sync);
2444
2445         nouveau_display(dev)->priv = NULL;
2446         kfree(disp);
2447 }
2448
2449 int
2450 nv50_display_create(struct drm_device *dev)
2451 {
2452         struct nvif_device *device = &nouveau_drm(dev)->client.device;
2453         struct nouveau_drm *drm = nouveau_drm(dev);
2454         struct dcb_table *dcb = &drm->vbios.dcb;
2455         struct drm_connector *connector, *tmp;
2456         struct nv50_disp *disp;
2457         struct dcb_output *dcbe;
2458         int crtcs, ret, i;
2459         bool has_mst = nv50_has_mst(drm);
2460
2461         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2462         if (!disp)
2463                 return -ENOMEM;
2464
2465         mutex_init(&disp->mutex);
2466
2467         nouveau_display(dev)->priv = disp;
2468         nouveau_display(dev)->dtor = nv50_display_destroy;
2469         nouveau_display(dev)->init = nv50_display_init;
2470         nouveau_display(dev)->fini = nv50_display_fini;
2471         disp->disp = &nouveau_display(dev)->disp;
2472         dev->mode_config.funcs = &nv50_disp_func;
2473         dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true;
2474         dev->mode_config.normalize_zpos = true;
2475
2476         /* small shared memory area we use for notifiers and semaphores */
2477         ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2478                              0, 0x0000, NULL, NULL, &disp->sync);
2479         if (!ret) {
2480                 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
2481                 if (!ret) {
2482                         ret = nouveau_bo_map(disp->sync);
2483                         if (ret)
2484                                 nouveau_bo_unpin(disp->sync);
2485                 }
2486                 if (ret)
2487                         nouveau_bo_ref(NULL, &disp->sync);
2488         }
2489
2490         if (ret)
2491                 goto out;
2492
2493         /* allocate master evo channel */
2494         ret = nv50_core_new(drm, &disp->core);
2495         if (ret)
2496                 goto out;
2497
2498         disp->core->func->init(disp->core);
2499         if (disp->core->func->caps_init) {
2500                 ret = disp->core->func->caps_init(drm, disp);
2501                 if (ret)
2502                         goto out;
2503         }
2504
2505         /* Assign the correct format modifiers */
2506         if (disp->disp->object.oclass >= TU102_DISP)
2507                 nouveau_display(dev)->format_modifiers = wndwc57e_modifiers;
2508         else
2509         if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI)
2510                 nouveau_display(dev)->format_modifiers = disp90xx_modifiers;
2511         else
2512                 nouveau_display(dev)->format_modifiers = disp50xx_modifiers;
2513
2514         /* create crtc objects to represent the hw heads */
2515         if (disp->disp->object.oclass >= GV100_DISP)
2516                 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff;
2517         else
2518         if (disp->disp->object.oclass >= GF110_DISP)
2519                 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf;
2520         else
2521                 crtcs = 0x3;
2522
2523         for (i = 0; i < fls(crtcs); i++) {
2524                 struct nv50_head *head;
2525
2526                 if (!(crtcs & (1 << i)))
2527                         continue;
2528
2529                 head = nv50_head_create(dev, i);
2530                 if (IS_ERR(head)) {
2531                         ret = PTR_ERR(head);
2532                         goto out;
2533                 }
2534
2535                 if (has_mst) {
2536                         head->msto = nv50_msto_new(dev, head, i);
2537                         if (IS_ERR(head->msto)) {
2538                                 ret = PTR_ERR(head->msto);
2539                                 head->msto = NULL;
2540                                 goto out;
2541                         }
2542
2543                         /*
2544                          * FIXME: This is a hack to workaround the following
2545                          * issues:
2546                          *
2547                          * https://gitlab.gnome.org/GNOME/mutter/issues/759
2548                          * https://gitlab.freedesktop.org/xorg/xserver/merge_requests/277
2549                          *
2550                          * Once these issues are closed, this should be
2551                          * removed
2552                          */
2553                         head->msto->encoder.possible_crtcs = crtcs;
2554                 }
2555         }
2556
2557         /* create encoder/connector objects based on VBIOS DCB table */
2558         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2559                 connector = nouveau_connector_create(dev, dcbe);
2560                 if (IS_ERR(connector))
2561                         continue;
2562
2563                 if (dcbe->location == DCB_LOC_ON_CHIP) {
2564                         switch (dcbe->type) {
2565                         case DCB_OUTPUT_TMDS:
2566                         case DCB_OUTPUT_LVDS:
2567                         case DCB_OUTPUT_DP:
2568                                 ret = nv50_sor_create(connector, dcbe);
2569                                 break;
2570                         case DCB_OUTPUT_ANALOG:
2571                                 ret = nv50_dac_create(connector, dcbe);
2572                                 break;
2573                         default:
2574                                 ret = -ENODEV;
2575                                 break;
2576                         }
2577                 } else {
2578                         ret = nv50_pior_create(connector, dcbe);
2579                 }
2580
2581                 if (ret) {
2582                         NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2583                                      dcbe->location, dcbe->type,
2584                                      ffs(dcbe->or) - 1, ret);
2585                         ret = 0;
2586                 }
2587         }
2588
2589         /* cull any connectors we created that don't have an encoder */
2590         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2591                 if (connector->possible_encoders)
2592                         continue;
2593
2594                 NV_WARN(drm, "%s has no encoders, removing\n",
2595                         connector->name);
2596                 connector->funcs->destroy(connector);
2597         }
2598
2599         /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */
2600         dev->vblank_disable_immediate = true;
2601
2602         nv50_audio_component_init(drm);
2603
2604 out:
2605         if (ret)
2606                 nv50_display_destroy(dev);
2607         return ret;
2608 }
2609
2610 /******************************************************************************
2611  * Format modifiers
2612  *****************************************************************************/
2613
2614 /****************************************************************
2615  *            Log2(block height) ----------------------------+  *
2616  *            Page Kind ----------------------------------+  |  *
2617  *            Gob Height/Page Kind Generation ------+     |  |  *
2618  *                          Sector layout -------+  |     |  |  *
2619  *                          Compression ------+  |  |     |  |  */
2620 const u64 disp50xx_modifiers[] = { /*         |  |  |     |  |  */
2621         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 0),
2622         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 1),
2623         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 2),
2624         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 3),
2625         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 4),
2626         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 5),
2627         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 0),
2628         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 1),
2629         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 2),
2630         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 3),
2631         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 4),
2632         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 5),
2633         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 0),
2634         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 1),
2635         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 2),
2636         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 3),
2637         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 4),
2638         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 5),
2639         DRM_FORMAT_MOD_LINEAR,
2640         DRM_FORMAT_MOD_INVALID
2641 };
2642
2643 /****************************************************************
2644  *            Log2(block height) ----------------------------+  *
2645  *            Page Kind ----------------------------------+  |  *
2646  *            Gob Height/Page Kind Generation ------+     |  |  *
2647  *                          Sector layout -------+  |     |  |  *
2648  *                          Compression ------+  |  |     |  |  */
2649 const u64 disp90xx_modifiers[] = { /*         |  |  |     |  |  */
2650         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 0),
2651         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 1),
2652         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 2),
2653         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 3),
2654         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 4),
2655         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 5),
2656         DRM_FORMAT_MOD_LINEAR,
2657         DRM_FORMAT_MOD_INVALID
2658 };