drivers/gpu/drm/nouveau/dispnv50/base507c.c

   1 /*
   2  * Copyright 2018 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22 #include "base.h"
  23
  24 #include <nvif/cl507c.h>
  25 #include <nvif/event.h>
  26 #include <nvif/push507c.h>
  27 #include <nvif/timer.h>
  28
  29 #include <drm/drm_atomic_helper.h>
  30 #include <drm/drm_fourcc.h>
  31 #include <drm/drm_plane_helper.h>
  32
  33 #include "nouveau_bo.h"
  34
  35 void
  36 base507c_update(struct nv50_wndw *wndw, u32 *interlock)
  37 {
  38         u32 *push;
  39         if ((push = evo_wait(&wndw->wndw, 2))) {
  40                 evo_mthd(push, 0x0080, 1);
  41                 evo_data(push, interlock[NV50_DISP_INTERLOCK_CORE]);
  42                 evo_kick(push, &wndw->wndw);
  43         }
  44 }
  45
  46 void
  47 base507c_image_clr(struct nv50_wndw *wndw)
  48 {
  49         u32 *push;
  50         if ((push = evo_wait(&wndw->wndw, 4))) {
  51                 evo_mthd(push, 0x0084, 1);
  52                 evo_data(push, 0x00000000);
  53                 evo_mthd(push, 0x00c0, 1);
  54                 evo_data(push, 0x00000000);
  55                 evo_kick(push, &wndw->wndw);
  56         }
  57 }
  58
  59 static int
  60 base507c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
  61 {
  62         struct nvif_push *push = wndw->wndw.push;
  63         int ret;
  64
  65         if ((ret = PUSH_WAIT(push, 13)))
  66                 return ret;
  67
  68         PUSH_NVSQ(push, NV507C, 0x0084, asyw->image.mode << 8 |
  69                                         asyw->image.interval << 4);
  70         PUSH_NVSQ(push, NV507C, 0x00c0, asyw->image.handle[0]);
  71         if (asyw->image.format == 0xca) {
  72                 PUSH_NVSQ(push, NV507C, 0x0110, 1,
  73                                         0x0114, 0x6400);
  74         } else {
  75                 PUSH_NVSQ(push, NV507C, 0x0110, 0,
  76                                         0x0114, 0);
  77         }
  78         PUSH_NVSQ(push, NV507C, 0x0800, asyw->image.offset[0] >> 8,
  79                                 0x0804, 0x00000000,
  80                                 0x0808, asyw->image.h << 16 | asyw->image.w,
  81                                 0x080c, asyw->image.layout << 20 |
  82                                        (asyw->image.pitch[0] >> 8) << 8 |
  83                                         asyw->image.blocks[0] << 8 |
  84                                         asyw->image.blockh,
  85                                 0x0810, asyw->image.kind << 16 |
  86                                         asyw->image.format << 8);
  87         return 0;
  88 }
  89
  90 int
  91 base507c_xlut_clr(struct nv50_wndw *wndw)
  92 {
  93         struct nvif_push *push = wndw->wndw.push;
  94         int ret;
  95
  96         if ((ret = PUSH_WAIT(push, 2)))
  97                 return ret;
  98
  99         PUSH_NVSQ(push, NV507C, 0x00e0, 0x00000000);
 100         return 0;
 101 }
 102
 103 int
 104 base507c_xlut_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
 105 {
 106         struct nvif_push *push = wndw->wndw.push;
 107         int ret;
 108
 109         if ((ret = PUSH_WAIT(push, 2)))
 110                 return ret;
 111
 112         PUSH_NVSQ(push, NV507C, 0x00e0, 0x40000000);
 113         return 0;
 114 }
 115
 116 int
 117 base507c_ntfy_wait_begun(struct nouveau_bo *bo, u32 offset,
 118                          struct nvif_device *device)
 119 {
 120         s64 time = nvif_msec(device, 2000ULL,
 121                 u32 data = nouveau_bo_rd32(bo, offset / 4);
 122                 if ((data & 0xc0000000) == 0x40000000)
 123                         break;
 124                 usleep_range(1, 2);
 125         );
 126         return time < 0 ? time : 0;
 127 }
 128
 129 int
 130 base507c_ntfy_clr(struct nv50_wndw *wndw)
 131 {
 132         struct nvif_push *push = wndw->wndw.push;
 133         int ret;
 134
 135         if ((ret = PUSH_WAIT(push, 2)))
 136                 return ret;
 137
 138         PUSH_NVSQ(push, NV507C, 0x00a4, 0x00000000);
 139         return 0;
 140 }
 141
 142 int
 143 base507c_ntfy_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
 144 {
 145         struct nvif_push *push = wndw->wndw.push;
 146         int ret;
 147
 148         if ((ret = PUSH_WAIT(push, 3)))
 149                 return ret;
 150
 151         PUSH_NVSQ(push, NV507C, 0x00a0, asyw->ntfy.awaken << 30 |
 152                                         asyw->ntfy.offset,
 153                                 0x00a4, asyw->ntfy.handle);
 154         return 0;
 155 }
 156
 157 void
 158 base507c_ntfy_reset(struct nouveau_bo *bo, u32 offset)
 159 {
 160         nouveau_bo_wr32(bo, offset / 4, 0x00000000);
 161 }
 162
 163 int
 164 base507c_sema_clr(struct nv50_wndw *wndw)
 165 {
 166         struct nvif_push *push = wndw->wndw.push;
 167         int ret;
 168
 169         if ((ret = PUSH_WAIT(push, 2)))
 170                 return ret;
 171
 172         PUSH_NVSQ(push, NV507C, 0x0094, 0x00000000);
 173         return 0;
 174 }
 175
 176 int
 177 base507c_sema_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
 178 {
 179         struct nvif_push *push = wndw->wndw.push;
 180         int ret;
 181
 182         if ((ret = PUSH_WAIT(push, 5)))
 183                 return ret;
 184
 185         PUSH_NVSQ(push, NV507C, 0x0088, asyw->sema.offset,
 186                                 0x008c, asyw->sema.acquire,
 187                                 0x0090, asyw->sema.release,
 188                                 0x0094, asyw->sema.handle);
 189         return 0;
 190 }
 191
 192 void
 193 base507c_release(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
 194                  struct nv50_head_atom *asyh)
 195 {
 196         asyh->base.cpp = 0;
 197 }
 198
 199 int
 200 base507c_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
 201                  struct nv50_head_atom *asyh)
 202 {
 203         const struct drm_framebuffer *fb = asyw->state.fb;
 204         int ret;
 205
 206         ret = drm_atomic_helper_check_plane_state(&asyw->state, &asyh->state,
 207                                                   DRM_PLANE_HELPER_NO_SCALING,
 208                                                   DRM_PLANE_HELPER_NO_SCALING,
 209                                                   false, true);
 210         if (ret)
 211                 return ret;
 212
 213         if (!wndw->func->ilut) {
 214                 if ((asyh->base.cpp != 1) ^ (fb->format->cpp[0] != 1))
 215                         asyh->state.color_mgmt_changed = true;
 216         }
 217
 218         asyh->base.depth = fb->format->depth;
 219         asyh->base.cpp = fb->format->cpp[0];
 220         asyh->base.x = asyw->state.src.x1 >> 16;
 221         asyh->base.y = asyw->state.src.y1 >> 16;
 222         asyh->base.w = asyw->state.fb->width;
 223         asyh->base.h = asyw->state.fb->height;
 224
 225         /* Some newer formats, esp FP16 ones, don't have a
 226          * "depth". There's nothing that really makes sense there
 227          * either, so just set it to the implicit bit count.
 228          */
 229         if (!asyh->base.depth)
 230                 asyh->base.depth = asyh->base.cpp * 8;
 231
 232         return 0;
 233 }
 234
 235 const u32
 236 base507c_format[] = {
 237         DRM_FORMAT_C8,
 238         DRM_FORMAT_RGB565,
 239         DRM_FORMAT_XRGB1555,
 240         DRM_FORMAT_ARGB1555,
 241         DRM_FORMAT_XRGB8888,
 242         DRM_FORMAT_ARGB8888,
 243         DRM_FORMAT_XBGR2101010,
 244         DRM_FORMAT_ABGR2101010,
 245         DRM_FORMAT_XBGR8888,
 246         DRM_FORMAT_ABGR8888,
 247         DRM_FORMAT_XBGR16161616F,
 248         DRM_FORMAT_ABGR16161616F,
 249         0
 250 };
 251
 252 static const struct nv50_wndw_func
 253 base507c = {
 254         .acquire = base507c_acquire,
 255         .release = base507c_release,
 256         .sema_set = base507c_sema_set,
 257         .sema_clr = base507c_sema_clr,
 258         .ntfy_reset = base507c_ntfy_reset,
 259         .ntfy_set = base507c_ntfy_set,
 260         .ntfy_clr = base507c_ntfy_clr,
 261         .ntfy_wait_begun = base507c_ntfy_wait_begun,
 262         .olut_core = 1,
 263         .xlut_set = base507c_xlut_set,
 264         .xlut_clr = base507c_xlut_clr,
 265         .image_set = base507c_image_set,
 266         .image_clr = base507c_image_clr,
 267         .update = base507c_update,
 268 };
 269
 270 int
 271 base507c_new_(const struct nv50_wndw_func *func, const u32 *format,
 272               struct nouveau_drm *drm, int head, s32 oclass, u32 interlock_data,
 273               struct nv50_wndw **pwndw)
 274 {
 275         struct nv50_disp_base_channel_dma_v0 args = {
 276                 .head = head,
 277         };
 278         struct nouveau_display *disp = nouveau_display(drm->dev);
 279         struct nv50_disp *disp50 = nv50_disp(drm->dev);
 280         struct nv50_wndw *wndw;
 281         int ret;
 282
 283         ret = nv50_wndw_new_(func, drm->dev, DRM_PLANE_TYPE_PRIMARY,
 284                              "base", head, format, BIT(head),
 285                              NV50_DISP_INTERLOCK_BASE, interlock_data, &wndw);
 286         if (*pwndw = wndw, ret)
 287                 return ret;
 288
 289         ret = nv50_dmac_create(&drm->client.device, &disp->disp.object,
 290                                &oclass, head, &args, sizeof(args),
 291                                disp50->sync->offset, &wndw->wndw);
 292         if (ret) {
 293                 NV_ERROR(drm, "base%04x allocation failed: %d\n", oclass, ret);
 294                 return ret;
 295         }
 296
 297         ret = nvif_notify_ctor(&wndw->wndw.base.user, "kmsBaseNtfy",
 298                                wndw->notify.func, false,
 299                                NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT,
 300                                &(struct nvif_notify_uevent_req) {},
 301                                sizeof(struct nvif_notify_uevent_req),
 302                                sizeof(struct nvif_notify_uevent_rep),
 303                                &wndw->notify);
 304         if (ret)
 305                 return ret;
 306
 307         wndw->ntfy = NV50_DISP_BASE_NTFY(wndw->id);
 308         wndw->sema = NV50_DISP_BASE_SEM0(wndw->id);
 309         wndw->data = 0x00000000;
 310         return 0;
 311 }
 312
 313 int
 314 base507c_new(struct nouveau_drm *drm, int head, s32 oclass,
 315              struct nv50_wndw **pwndw)
 316 {
 317         return base507c_new_(&base507c, base507c_format, drm, head, oclass,
 318                              0x00000002 << (head * 8), pwndw);
 319 }