1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2018, 2020-2021 The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
8 #include <linux/dma-mapping.h>
9 #include <linux/kthread.h>
10 #include <linux/sched/mm.h>
11 #include <linux/uaccess.h>
12 #include <uapi/linux/sched/types.h>
14 #include <drm/drm_drv.h>
15 #include <drm/drm_file.h>
16 #include <drm/drm_ioctl.h>
17 #include <drm/drm_prime.h>
18 #include <drm/drm_of.h>
19 #include <drm/drm_vblank.h>
21 #include "disp/msm_disp_snapshot.h"
23 #include "msm_debugfs.h"
24 #include "msm_fence.h"
28 #include "adreno/adreno_gpu.h"
32 * - 1.0.0 - initial interface
33 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
34 * - 1.2.0 - adds explicit fence support for submit ioctl
35 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
36 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
38 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get
39 * GEM object's debug name
40 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
41 * - 1.6.0 - Syncobj support
42 * - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count
43 * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx)
44 * - 1.9.0 - Add MSM_SUBMIT_FENCE_SN_IN
46 #define MSM_VERSION_MAJOR 1
47 #define MSM_VERSION_MINOR 9
48 #define MSM_VERSION_PATCHLEVEL 0
50 static const struct drm_mode_config_funcs mode_config_funcs = {
51 .fb_create = msm_framebuffer_create,
52 .output_poll_changed = drm_fb_helper_output_poll_changed,
53 .atomic_check = drm_atomic_helper_check,
54 .atomic_commit = drm_atomic_helper_commit,
57 static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = {
58 .atomic_commit_tail = msm_atomic_commit_tail,
61 #ifdef CONFIG_DRM_FBDEV_EMULATION
62 static bool fbdev = true;
63 MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
64 module_param(fbdev, bool, 0600);
67 static char *vram = "16m";
68 MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
69 module_param(vram, charp, 0);
72 MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
73 module_param(dumpstate, bool, 0600);
75 static bool modeset = true;
76 MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
77 module_param(modeset, bool, 0600);
79 static irqreturn_t msm_irq(int irq, void *arg)
81 struct drm_device *dev = arg;
82 struct msm_drm_private *priv = dev->dev_private;
83 struct msm_kms *kms = priv->kms;
87 return kms->funcs->irq(kms);
90 static void msm_irq_preinstall(struct drm_device *dev)
92 struct msm_drm_private *priv = dev->dev_private;
93 struct msm_kms *kms = priv->kms;
97 kms->funcs->irq_preinstall(kms);
100 static int msm_irq_postinstall(struct drm_device *dev)
102 struct msm_drm_private *priv = dev->dev_private;
103 struct msm_kms *kms = priv->kms;
107 if (kms->funcs->irq_postinstall)
108 return kms->funcs->irq_postinstall(kms);
113 static int msm_irq_install(struct drm_device *dev, unsigned int irq)
117 if (irq == IRQ_NOTCONNECTED)
120 msm_irq_preinstall(dev);
122 ret = request_irq(irq, msm_irq, 0, dev->driver->name, dev);
126 ret = msm_irq_postinstall(dev);
135 static void msm_irq_uninstall(struct drm_device *dev)
137 struct msm_drm_private *priv = dev->dev_private;
138 struct msm_kms *kms = priv->kms;
140 kms->funcs->irq_uninstall(kms);
141 free_irq(kms->irq, dev);
144 struct msm_vblank_work {
145 struct work_struct work;
148 struct msm_drm_private *priv;
151 static void vblank_ctrl_worker(struct work_struct *work)
153 struct msm_vblank_work *vbl_work = container_of(work,
154 struct msm_vblank_work, work);
155 struct msm_drm_private *priv = vbl_work->priv;
156 struct msm_kms *kms = priv->kms;
158 if (vbl_work->enable)
159 kms->funcs->enable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
161 kms->funcs->disable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
166 static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
167 int crtc_id, bool enable)
169 struct msm_vblank_work *vbl_work;
171 vbl_work = kzalloc(sizeof(*vbl_work), GFP_ATOMIC);
175 INIT_WORK(&vbl_work->work, vblank_ctrl_worker);
177 vbl_work->crtc_id = crtc_id;
178 vbl_work->enable = enable;
179 vbl_work->priv = priv;
181 queue_work(priv->wq, &vbl_work->work);
186 static int msm_drm_uninit(struct device *dev)
188 struct platform_device *pdev = to_platform_device(dev);
189 struct msm_drm_private *priv = platform_get_drvdata(pdev);
190 struct drm_device *ddev = priv->dev;
191 struct msm_kms *kms = priv->kms;
195 * Shutdown the hw if we're far enough along where things might be on.
196 * If we run this too early, we'll end up panicking in any variety of
197 * places. Since we don't register the drm device until late in
198 * msm_drm_init, drm_dev->registered is used as an indicator that the
199 * shutdown will be successful.
201 if (ddev->registered) {
202 drm_dev_unregister(ddev);
203 drm_atomic_helper_shutdown(ddev);
206 /* We must cancel and cleanup any pending vblank enable/disable
207 * work before msm_irq_uninstall() to avoid work re-enabling an
208 * irq after uninstall has disabled it.
211 flush_workqueue(priv->wq);
213 /* clean up event worker threads */
214 for (i = 0; i < priv->num_crtcs; i++) {
215 if (priv->event_thread[i].worker)
216 kthread_destroy_worker(priv->event_thread[i].worker);
219 msm_gem_shrinker_cleanup(ddev);
221 drm_kms_helper_poll_fini(ddev);
223 msm_perf_debugfs_cleanup(priv);
224 msm_rd_debugfs_cleanup(priv);
226 #ifdef CONFIG_DRM_FBDEV_EMULATION
227 if (fbdev && priv->fbdev)
228 msm_fbdev_free(ddev);
231 msm_disp_snapshot_destroy(ddev);
233 drm_mode_config_cleanup(ddev);
235 pm_runtime_get_sync(dev);
236 msm_irq_uninstall(ddev);
237 pm_runtime_put_sync(dev);
239 if (kms && kms->funcs)
240 kms->funcs->destroy(kms);
242 if (priv->vram.paddr) {
243 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
244 drm_mm_takedown(&priv->vram.mm);
245 dma_free_attrs(dev, priv->vram.size, NULL,
246 priv->vram.paddr, attrs);
249 component_unbind_all(dev, ddev);
251 ddev->dev_private = NULL;
254 destroy_workqueue(priv->wq);
263 static int get_mdp_ver(struct platform_device *pdev)
265 struct device *dev = &pdev->dev;
267 return (int) (unsigned long) of_device_get_match_data(dev);
270 #include <linux/of_address.h>
272 bool msm_use_mmu(struct drm_device *dev)
274 struct msm_drm_private *priv = dev->dev_private;
276 /* a2xx comes with its own MMU */
277 return priv->is_a2xx || iommu_present(&platform_bus_type);
280 static int msm_init_vram(struct drm_device *dev)
282 struct msm_drm_private *priv = dev->dev_private;
283 struct device_node *node;
284 unsigned long size = 0;
287 /* In the device-tree world, we could have a 'memory-region'
288 * phandle, which gives us a link to our "vram". Allocating
289 * is all nicely abstracted behind the dma api, but we need
290 * to know the entire size to allocate it all in one go. There
292 * 1) device with no IOMMU, in which case we need exclusive
293 * access to a VRAM carveout big enough for all gpu
295 * 2) device with IOMMU, but where the bootloader puts up
296 * a splash screen. In this case, the VRAM carveout
297 * need only be large enough for fbdev fb. But we need
298 * exclusive access to the buffer to avoid the kernel
299 * using those pages for other purposes (which appears
300 * as corruption on screen before we have a chance to
301 * load and do initial modeset)
304 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
307 ret = of_address_to_resource(node, 0, &r);
311 size = r.end - r.start + 1;
312 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
314 /* if we have no IOMMU, then we need to use carveout allocator.
315 * Grab the entire CMA chunk carved out in early startup in
318 } else if (!msm_use_mmu(dev)) {
319 DRM_INFO("using %s VRAM carveout\n", vram);
320 size = memparse(vram, NULL);
324 unsigned long attrs = 0;
327 priv->vram.size = size;
329 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
330 spin_lock_init(&priv->vram.lock);
332 attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
333 attrs |= DMA_ATTR_WRITE_COMBINE;
335 /* note that for no-kernel-mapping, the vaddr returned
336 * is bogus, but non-null if allocation succeeded:
338 p = dma_alloc_attrs(dev->dev, size,
339 &priv->vram.paddr, GFP_KERNEL, attrs);
341 DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n");
342 priv->vram.paddr = 0;
346 DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n",
347 (uint32_t)priv->vram.paddr,
348 (uint32_t)(priv->vram.paddr + size));
354 static int msm_drm_init(struct device *dev, const struct drm_driver *drv)
356 struct platform_device *pdev = to_platform_device(dev);
357 struct msm_drm_private *priv = dev_get_drvdata(dev);
358 struct drm_device *ddev;
362 if (drm_firmware_drivers_only())
365 ddev = drm_dev_alloc(drv, dev);
367 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n");
368 return PTR_ERR(ddev);
370 ddev->dev_private = priv;
373 priv->wq = alloc_ordered_workqueue("msm", 0);
374 priv->hangcheck_period = DRM_MSM_HANGCHECK_DEFAULT_PERIOD;
376 INIT_LIST_HEAD(&priv->objects);
377 mutex_init(&priv->obj_lock);
379 INIT_LIST_HEAD(&priv->inactive_willneed);
380 INIT_LIST_HEAD(&priv->inactive_dontneed);
381 INIT_LIST_HEAD(&priv->inactive_unpinned);
382 mutex_init(&priv->mm_lock);
384 /* Teach lockdep about lock ordering wrt. shrinker: */
385 fs_reclaim_acquire(GFP_KERNEL);
386 might_lock(&priv->mm_lock);
387 fs_reclaim_release(GFP_KERNEL);
389 drm_mode_config_init(ddev);
391 ret = msm_init_vram(ddev);
395 /* Bind all our sub-components: */
396 ret = component_bind_all(dev, ddev);
400 dma_set_max_seg_size(dev, UINT_MAX);
402 msm_gem_shrinker_init(ddev);
404 switch (get_mdp_ver(pdev)) {
406 kms = mdp4_kms_init(ddev);
410 kms = mdp5_kms_init(ddev);
413 kms = dpu_kms_init(ddev);
417 /* valid only for the dummy headless case, where of_node=NULL */
418 WARN_ON(dev->of_node);
424 DRM_DEV_ERROR(dev, "failed to load kms\n");
430 /* Enable normalization of plane zpos */
431 ddev->mode_config.normalize_zpos = true;
435 ret = kms->funcs->hw_init(kms);
437 DRM_DEV_ERROR(dev, "kms hw init failed: %d\n", ret);
442 ddev->mode_config.funcs = &mode_config_funcs;
443 ddev->mode_config.helper_private = &mode_config_helper_funcs;
445 for (i = 0; i < priv->num_crtcs; i++) {
446 /* initialize event thread */
447 priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id;
448 priv->event_thread[i].dev = ddev;
449 priv->event_thread[i].worker = kthread_create_worker(0,
450 "crtc_event:%d", priv->event_thread[i].crtc_id);
451 if (IS_ERR(priv->event_thread[i].worker)) {
452 ret = PTR_ERR(priv->event_thread[i].worker);
453 DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n");
454 ret = PTR_ERR(priv->event_thread[i].worker);
458 sched_set_fifo(priv->event_thread[i].worker->task);
461 ret = drm_vblank_init(ddev, priv->num_crtcs);
463 DRM_DEV_ERROR(dev, "failed to initialize vblank\n");
468 pm_runtime_get_sync(dev);
469 ret = msm_irq_install(ddev, kms->irq);
470 pm_runtime_put_sync(dev);
472 DRM_DEV_ERROR(dev, "failed to install IRQ handler\n");
477 ret = drm_dev_register(ddev, 0);
482 ret = msm_disp_snapshot_init(ddev);
484 DRM_DEV_ERROR(dev, "msm_disp_snapshot_init failed ret = %d\n", ret);
486 drm_mode_config_reset(ddev);
488 #ifdef CONFIG_DRM_FBDEV_EMULATION
490 priv->fbdev = msm_fbdev_init(ddev);
493 ret = msm_debugfs_late_init(ddev);
497 drm_kms_helper_poll_init(ddev);
510 static void load_gpu(struct drm_device *dev)
512 static DEFINE_MUTEX(init_lock);
513 struct msm_drm_private *priv = dev->dev_private;
515 mutex_lock(&init_lock);
518 priv->gpu = adreno_load_gpu(dev);
520 mutex_unlock(&init_lock);
523 static int context_init(struct drm_device *dev, struct drm_file *file)
525 static atomic_t ident = ATOMIC_INIT(0);
526 struct msm_drm_private *priv = dev->dev_private;
527 struct msm_file_private *ctx;
529 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
533 INIT_LIST_HEAD(&ctx->submitqueues);
534 rwlock_init(&ctx->queuelock);
536 kref_init(&ctx->ref);
537 msm_submitqueue_init(dev, ctx);
539 ctx->aspace = msm_gpu_create_private_address_space(priv->gpu, current);
540 file->driver_priv = ctx;
542 ctx->seqno = atomic_inc_return(&ident);
547 static int msm_open(struct drm_device *dev, struct drm_file *file)
549 /* For now, load gpu on open.. to avoid the requirement of having
550 * firmware in the initrd.
554 return context_init(dev, file);
557 static void context_close(struct msm_file_private *ctx)
559 msm_submitqueue_close(ctx);
560 msm_file_private_put(ctx);
563 static void msm_postclose(struct drm_device *dev, struct drm_file *file)
565 struct msm_drm_private *priv = dev->dev_private;
566 struct msm_file_private *ctx = file->driver_priv;
569 * It is not possible to set sysprof param to non-zero if gpu
570 * is not initialized:
573 msm_file_private_set_sysprof(ctx, priv->gpu, 0);
578 int msm_crtc_enable_vblank(struct drm_crtc *crtc)
580 struct drm_device *dev = crtc->dev;
581 unsigned int pipe = crtc->index;
582 struct msm_drm_private *priv = dev->dev_private;
583 struct msm_kms *kms = priv->kms;
586 drm_dbg_vbl(dev, "crtc=%u", pipe);
587 return vblank_ctrl_queue_work(priv, pipe, true);
590 void msm_crtc_disable_vblank(struct drm_crtc *crtc)
592 struct drm_device *dev = crtc->dev;
593 unsigned int pipe = crtc->index;
594 struct msm_drm_private *priv = dev->dev_private;
595 struct msm_kms *kms = priv->kms;
598 drm_dbg_vbl(dev, "crtc=%u", pipe);
599 vblank_ctrl_queue_work(priv, pipe, false);
606 static int msm_ioctl_get_param(struct drm_device *dev, void *data,
607 struct drm_file *file)
609 struct msm_drm_private *priv = dev->dev_private;
610 struct drm_msm_param *args = data;
613 /* for now, we just have 3d pipe.. eventually this would need to
614 * be more clever to dispatch to appropriate gpu module:
616 if (args->pipe != MSM_PIPE_3D0)
624 return gpu->funcs->get_param(gpu, file->driver_priv,
625 args->param, &args->value);
628 static int msm_ioctl_set_param(struct drm_device *dev, void *data,
629 struct drm_file *file)
631 struct msm_drm_private *priv = dev->dev_private;
632 struct drm_msm_param *args = data;
635 if (args->pipe != MSM_PIPE_3D0)
643 return gpu->funcs->set_param(gpu, file->driver_priv,
644 args->param, args->value);
647 static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
648 struct drm_file *file)
650 struct drm_msm_gem_new *args = data;
652 if (args->flags & ~MSM_BO_FLAGS) {
653 DRM_ERROR("invalid flags: %08x\n", args->flags);
657 return msm_gem_new_handle(dev, file, args->size,
658 args->flags, &args->handle, NULL);
661 static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
663 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
666 static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
667 struct drm_file *file)
669 struct drm_msm_gem_cpu_prep *args = data;
670 struct drm_gem_object *obj;
671 ktime_t timeout = to_ktime(args->timeout);
674 if (args->op & ~MSM_PREP_FLAGS) {
675 DRM_ERROR("invalid op: %08x\n", args->op);
679 obj = drm_gem_object_lookup(file, args->handle);
683 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
685 drm_gem_object_put(obj);
690 static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
691 struct drm_file *file)
693 struct drm_msm_gem_cpu_fini *args = data;
694 struct drm_gem_object *obj;
697 obj = drm_gem_object_lookup(file, args->handle);
701 ret = msm_gem_cpu_fini(obj);
703 drm_gem_object_put(obj);
708 static int msm_ioctl_gem_info_iova(struct drm_device *dev,
709 struct drm_file *file, struct drm_gem_object *obj,
712 struct msm_drm_private *priv = dev->dev_private;
713 struct msm_file_private *ctx = file->driver_priv;
719 * Don't pin the memory here - just get an address so that userspace can
722 return msm_gem_get_iova(obj, ctx->aspace, iova);
725 static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
726 struct drm_file *file)
728 struct drm_msm_gem_info *args = data;
729 struct drm_gem_object *obj;
730 struct msm_gem_object *msm_obj;
736 switch (args->info) {
737 case MSM_INFO_GET_OFFSET:
738 case MSM_INFO_GET_IOVA:
739 /* value returned as immediate, not pointer, so len==0: */
743 case MSM_INFO_SET_NAME:
744 case MSM_INFO_GET_NAME:
750 obj = drm_gem_object_lookup(file, args->handle);
754 msm_obj = to_msm_bo(obj);
756 switch (args->info) {
757 case MSM_INFO_GET_OFFSET:
758 args->value = msm_gem_mmap_offset(obj);
760 case MSM_INFO_GET_IOVA:
761 ret = msm_ioctl_gem_info_iova(dev, file, obj, &args->value);
763 case MSM_INFO_SET_NAME:
764 /* length check should leave room for terminating null: */
765 if (args->len >= sizeof(msm_obj->name)) {
769 if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value),
771 msm_obj->name[0] = '\0';
775 msm_obj->name[args->len] = '\0';
776 for (i = 0; i < args->len; i++) {
777 if (!isprint(msm_obj->name[i])) {
778 msm_obj->name[i] = '\0';
783 case MSM_INFO_GET_NAME:
784 if (args->value && (args->len < strlen(msm_obj->name))) {
788 args->len = strlen(msm_obj->name);
790 if (copy_to_user(u64_to_user_ptr(args->value),
791 msm_obj->name, args->len))
797 drm_gem_object_put(obj);
802 static int wait_fence(struct msm_gpu_submitqueue *queue, uint32_t fence_id,
805 struct dma_fence *fence;
808 if (fence_after(fence_id, queue->last_fence)) {
809 DRM_ERROR_RATELIMITED("waiting on invalid fence: %u (of %u)\n",
810 fence_id, queue->last_fence);
815 * Map submitqueue scoped "seqno" (which is actually an idr key)
816 * back to underlying dma-fence
818 * The fence is removed from the fence_idr when the submit is
819 * retired, so if the fence is not found it means there is nothing
822 ret = mutex_lock_interruptible(&queue->lock);
825 fence = idr_find(&queue->fence_idr, fence_id);
827 fence = dma_fence_get_rcu(fence);
828 mutex_unlock(&queue->lock);
833 ret = dma_fence_wait_timeout(fence, true, timeout_to_jiffies(&timeout));
836 } else if (ret != -ERESTARTSYS) {
840 dma_fence_put(fence);
845 static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
846 struct drm_file *file)
848 struct msm_drm_private *priv = dev->dev_private;
849 struct drm_msm_wait_fence *args = data;
850 struct msm_gpu_submitqueue *queue;
854 DRM_ERROR("invalid pad: %08x\n", args->pad);
861 queue = msm_submitqueue_get(file->driver_priv, args->queueid);
865 ret = wait_fence(queue, args->fence, to_ktime(args->timeout));
867 msm_submitqueue_put(queue);
872 static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
873 struct drm_file *file)
875 struct drm_msm_gem_madvise *args = data;
876 struct drm_gem_object *obj;
879 switch (args->madv) {
880 case MSM_MADV_DONTNEED:
881 case MSM_MADV_WILLNEED:
887 obj = drm_gem_object_lookup(file, args->handle);
892 ret = msm_gem_madvise(obj, args->madv);
894 args->retained = ret;
898 drm_gem_object_put(obj);
904 static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
905 struct drm_file *file)
907 struct drm_msm_submitqueue *args = data;
909 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
912 return msm_submitqueue_create(dev, file->driver_priv, args->prio,
913 args->flags, &args->id);
916 static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data,
917 struct drm_file *file)
919 return msm_submitqueue_query(dev, file->driver_priv, data);
922 static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
923 struct drm_file *file)
925 u32 id = *(u32 *) data;
927 return msm_submitqueue_remove(file->driver_priv, id);
930 static const struct drm_ioctl_desc msm_ioctls[] = {
931 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_RENDER_ALLOW),
932 DRM_IOCTL_DEF_DRV(MSM_SET_PARAM, msm_ioctl_set_param, DRM_RENDER_ALLOW),
933 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_RENDER_ALLOW),
934 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_RENDER_ALLOW),
935 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW),
936 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW),
937 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_RENDER_ALLOW),
938 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_RENDER_ALLOW),
939 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_RENDER_ALLOW),
940 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_RENDER_ALLOW),
941 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW),
942 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW),
945 DEFINE_DRM_GEM_FOPS(fops);
947 static const struct drm_driver msm_driver = {
948 .driver_features = DRIVER_GEM |
954 .postclose = msm_postclose,
955 .lastclose = drm_fb_helper_lastclose,
956 .dumb_create = msm_gem_dumb_create,
957 .dumb_map_offset = msm_gem_dumb_map_offset,
958 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
959 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
960 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
961 .gem_prime_mmap = drm_gem_prime_mmap,
962 #ifdef CONFIG_DEBUG_FS
963 .debugfs_init = msm_debugfs_init,
965 .ioctls = msm_ioctls,
966 .num_ioctls = ARRAY_SIZE(msm_ioctls),
969 .desc = "MSM Snapdragon DRM",
971 .major = MSM_VERSION_MAJOR,
972 .minor = MSM_VERSION_MINOR,
973 .patchlevel = MSM_VERSION_PATCHLEVEL,
976 static int __maybe_unused msm_runtime_suspend(struct device *dev)
978 struct msm_drm_private *priv = dev_get_drvdata(dev);
979 struct msm_mdss *mdss = priv->mdss;
983 if (mdss && mdss->funcs)
984 return mdss->funcs->disable(mdss);
989 static int __maybe_unused msm_runtime_resume(struct device *dev)
991 struct msm_drm_private *priv = dev_get_drvdata(dev);
992 struct msm_mdss *mdss = priv->mdss;
996 if (mdss && mdss->funcs)
997 return mdss->funcs->enable(mdss);
1002 static int __maybe_unused msm_pm_suspend(struct device *dev)
1005 if (pm_runtime_suspended(dev))
1008 return msm_runtime_suspend(dev);
1011 static int __maybe_unused msm_pm_resume(struct device *dev)
1013 if (pm_runtime_suspended(dev))
1016 return msm_runtime_resume(dev);
1019 static int __maybe_unused msm_pm_prepare(struct device *dev)
1021 struct msm_drm_private *priv = dev_get_drvdata(dev);
1022 struct drm_device *ddev = priv ? priv->dev : NULL;
1024 if (!priv || !priv->kms)
1027 return drm_mode_config_helper_suspend(ddev);
1030 static void __maybe_unused msm_pm_complete(struct device *dev)
1032 struct msm_drm_private *priv = dev_get_drvdata(dev);
1033 struct drm_device *ddev = priv ? priv->dev : NULL;
1035 if (!priv || !priv->kms)
1038 drm_mode_config_helper_resume(ddev);
1041 static const struct dev_pm_ops msm_pm_ops = {
1042 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
1043 SET_RUNTIME_PM_OPS(msm_runtime_suspend, msm_runtime_resume, NULL)
1044 .prepare = msm_pm_prepare,
1045 .complete = msm_pm_complete,
1049 * Componentized driver support:
1053 * Identify what components need to be added by parsing what remote-endpoints
1054 * our MDP output ports are connected to. In the case of LVDS on MDP4, there
1055 * is no external component that we need to add since LVDS is within MDP4
1058 static int add_components_mdp(struct device *mdp_dev,
1059 struct component_match **matchptr)
1061 struct device_node *np = mdp_dev->of_node;
1062 struct device_node *ep_node;
1063 struct device *master_dev;
1066 * on MDP4 based platforms, the MDP platform device is the component
1067 * master that adds other display interface components to itself.
1069 * on MDP5 based platforms, the MDSS platform device is the component
1070 * master that adds MDP5 and other display interface components to
1073 if (of_device_is_compatible(np, "qcom,mdp4"))
1074 master_dev = mdp_dev;
1076 master_dev = mdp_dev->parent;
1078 for_each_endpoint_of_node(np, ep_node) {
1079 struct device_node *intf;
1080 struct of_endpoint ep;
1083 ret = of_graph_parse_endpoint(ep_node, &ep);
1085 DRM_DEV_ERROR(mdp_dev, "unable to parse port endpoint\n");
1086 of_node_put(ep_node);
1091 * The LCDC/LVDS port on MDP4 is a speacial case where the
1092 * remote-endpoint isn't a component that we need to add
1094 if (of_device_is_compatible(np, "qcom,mdp4") &&
1099 * It's okay if some of the ports don't have a remote endpoint
1100 * specified. It just means that the port isn't connected to
1101 * any external interface.
1103 intf = of_graph_get_remote_port_parent(ep_node);
1107 if (of_device_is_available(intf))
1108 drm_of_component_match_add(master_dev, matchptr,
1109 component_compare_of, intf);
1117 static int find_mdp_node(struct device *dev, void *data)
1119 return of_match_node(dpu_dt_match, dev->of_node) ||
1120 of_match_node(mdp5_dt_match, dev->of_node);
1123 static int add_display_components(struct platform_device *pdev,
1124 struct component_match **matchptr)
1126 struct device *mdp_dev;
1127 struct device *dev = &pdev->dev;
1131 * MDP5/DPU based devices don't have a flat hierarchy. There is a top
1132 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
1133 * Populate the children devices, find the MDP5/DPU node, and then add
1134 * the interfaces to our components list.
1136 switch (get_mdp_ver(pdev)) {
1139 ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
1141 DRM_DEV_ERROR(dev, "failed to populate children devices\n");
1145 mdp_dev = device_find_child(dev, NULL, find_mdp_node);
1147 DRM_DEV_ERROR(dev, "failed to find MDSS MDP node\n");
1148 of_platform_depopulate(dev);
1152 put_device(mdp_dev);
1154 /* add the MDP component itself */
1155 drm_of_component_match_add(dev, matchptr, component_compare_of,
1164 ret = add_components_mdp(mdp_dev, matchptr);
1166 of_platform_depopulate(dev);
1172 * We don't know what's the best binding to link the gpu with the drm device.
1173 * Fow now, we just hunt for all the possible gpus that we support, and add them
1176 static const struct of_device_id msm_gpu_match[] = {
1177 { .compatible = "qcom,adreno" },
1178 { .compatible = "qcom,adreno-3xx" },
1179 { .compatible = "amd,imageon" },
1180 { .compatible = "qcom,kgsl-3d0" },
1184 static int add_gpu_components(struct device *dev,
1185 struct component_match **matchptr)
1187 struct device_node *np;
1189 np = of_find_matching_node(NULL, msm_gpu_match);
1193 if (of_device_is_available(np))
1194 drm_of_component_match_add(dev, matchptr, component_compare_of, np);
1201 static int msm_drm_bind(struct device *dev)
1203 return msm_drm_init(dev, &msm_driver);
1206 static void msm_drm_unbind(struct device *dev)
1208 msm_drm_uninit(dev);
1211 static const struct component_master_ops msm_drm_ops = {
1212 .bind = msm_drm_bind,
1213 .unbind = msm_drm_unbind,
1220 static int msm_pdev_probe(struct platform_device *pdev)
1222 struct component_match *match = NULL;
1223 struct msm_drm_private *priv;
1226 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1230 platform_set_drvdata(pdev, priv);
1232 switch (get_mdp_ver(pdev)) {
1234 ret = mdp5_mdss_init(pdev);
1237 ret = dpu_mdss_init(pdev);
1244 platform_set_drvdata(pdev, NULL);
1248 if (get_mdp_ver(pdev)) {
1249 ret = add_display_components(pdev, &match);
1254 ret = add_gpu_components(&pdev->dev, &match);
1258 /* on all devices that I am aware of, iommu's which can map
1259 * any address the cpu can see are used:
1261 ret = dma_set_mask_and_coherent(&pdev->dev, ~0);
1265 ret = component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
1272 of_platform_depopulate(&pdev->dev);
1274 if (priv->mdss && priv->mdss->funcs)
1275 priv->mdss->funcs->destroy(priv->mdss);
1280 static int msm_pdev_remove(struct platform_device *pdev)
1282 struct msm_drm_private *priv = platform_get_drvdata(pdev);
1283 struct msm_mdss *mdss = priv->mdss;
1285 component_master_del(&pdev->dev, &msm_drm_ops);
1286 of_platform_depopulate(&pdev->dev);
1288 if (mdss && mdss->funcs)
1289 mdss->funcs->destroy(mdss);
1294 static void msm_pdev_shutdown(struct platform_device *pdev)
1296 struct msm_drm_private *priv = platform_get_drvdata(pdev);
1297 struct drm_device *drm = priv ? priv->dev : NULL;
1299 if (!priv || !priv->kms)
1302 drm_atomic_helper_shutdown(drm);
1305 static const struct of_device_id dt_match[] = {
1306 { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 },
1307 { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
1308 { .compatible = "qcom,msm8998-mdss", .data = (void *)KMS_DPU },
1309 { .compatible = "qcom,qcm2290-mdss", .data = (void *)KMS_DPU },
1310 { .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU },
1311 { .compatible = "qcom,sc7180-mdss", .data = (void *)KMS_DPU },
1312 { .compatible = "qcom,sc7280-mdss", .data = (void *)KMS_DPU },
1313 { .compatible = "qcom,sc8180x-mdss", .data = (void *)KMS_DPU },
1314 { .compatible = "qcom,sm8150-mdss", .data = (void *)KMS_DPU },
1315 { .compatible = "qcom,sm8250-mdss", .data = (void *)KMS_DPU },
1318 MODULE_DEVICE_TABLE(of, dt_match);
1320 static struct platform_driver msm_platform_driver = {
1321 .probe = msm_pdev_probe,
1322 .remove = msm_pdev_remove,
1323 .shutdown = msm_pdev_shutdown,
1326 .of_match_table = dt_match,
1331 static int __init msm_drm_register(void)
1340 msm_hdmi_register();
1343 return platform_driver_register(&msm_platform_driver);
1346 static void __exit msm_drm_unregister(void)
1349 platform_driver_unregister(&msm_platform_driver);
1350 msm_dp_unregister();
1351 msm_hdmi_unregister();
1352 adreno_unregister();
1353 msm_dsi_unregister();
1354 msm_mdp_unregister();
1355 msm_dpu_unregister();
1358 module_init(msm_drm_register);
1359 module_exit(msm_drm_unregister);
1361 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1362 MODULE_DESCRIPTION("MSM DRM Driver");
1363 MODULE_LICENSE("GPL");