2 * SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018, The Linux Foundation
7 #include <linux/clk-provider.h>
8 #include <linux/iopoll.h>
14 * DSI PLL 7nm - clock diagram (eg: DSI0): TODO: updated CPHY diagram
16 * dsi0_pll_out_div_clk dsi0_pll_bit_clk
19 * +---------+ | +----------+ | +----+
20 * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk
21 * +---------+ | +----------+ | +----+
23 * | | dsi0_pll_by_2_bit_clk
25 * | | +----+ | |\ dsi0_pclk_mux
26 * | |--| /2 |--o--| \ |
27 * | | +----+ | \ | +---------+
28 * | --------------| |--o--| div_7_4 |-- dsi0_phy_pll_out_dsiclk
29 * |------------------------------| / +---------+
31 * -----------| /4? |--o----------|/
35 * dsi0_pll_post_out_div_clk
38 #define VCO_REF_CLK_RATE 19200000
41 /* Hardware is V4.1 */
42 #define DSI_PHY_7NM_QUIRK_V4_1 BIT(0)
44 struct dsi_pll_config {
52 u32 decimal_div_start;
54 u32 pll_clock_inverters;
59 struct pll_7nm_cached_state {
60 unsigned long vco_rate;
70 struct msm_dsi_phy *phy;
74 /* protects REG_DSI_7nm_PHY_CMN_CLK_CFG0 register */
75 spinlock_t postdiv_lock;
77 struct pll_7nm_cached_state cached_state;
79 struct dsi_pll_7nm *slave;
82 #define to_pll_7nm(x) container_of(x, struct dsi_pll_7nm, clk_hw)
85 * Global list of private DSI PLL struct pointers. We need this for Dual DSI
86 * mode, where the master PLL's clk_ops needs access the slave's private data
88 static struct dsi_pll_7nm *pll_7nm_list[DSI_MAX];
90 static void dsi_pll_setup_config(struct dsi_pll_config *config)
92 config->ssc_freq = 31500;
93 config->ssc_offset = 4800;
94 config->ssc_adj_per = 2;
96 /* TODO: ssc enable */
97 config->enable_ssc = false;
98 config->ssc_center = 0;
101 static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config *config)
103 u64 fref = VCO_REF_CLK_RATE;
106 u64 dec, dec_multiple;
110 pll_freq = pll->vco_current_rate;
114 multiplier = 1 << FRAC_BITS;
115 dec_multiple = div_u64(pll_freq * multiplier, divider);
116 div_u64_rem(dec_multiple, multiplier, &frac);
118 dec = div_u64(dec_multiple, multiplier);
120 if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1))
121 config->pll_clock_inverters = 0x28;
122 else if (pll_freq <= 1000000000ULL)
123 config->pll_clock_inverters = 0xa0;
124 else if (pll_freq <= 2500000000ULL)
125 config->pll_clock_inverters = 0x20;
126 else if (pll_freq <= 3020000000ULL)
127 config->pll_clock_inverters = 0x00;
129 config->pll_clock_inverters = 0x40;
131 config->decimal_div_start = dec;
132 config->frac_div_start = frac;
135 #define SSC_CENTER BIT(0)
136 #define SSC_EN BIT(1)
138 static void dsi_pll_calc_ssc(struct dsi_pll_7nm *pll, struct dsi_pll_config *config)
145 if (!config->enable_ssc) {
146 DBG("SSC not enabled\n");
150 ssc_per = DIV_ROUND_CLOSEST(VCO_REF_CLK_RATE, config->ssc_freq) / 2 - 1;
151 ssc_mod = (ssc_per + 1) % (config->ssc_adj_per + 1);
154 frac = config->frac_div_start;
155 ssc_step_size = config->decimal_div_start;
156 ssc_step_size *= (1 << FRAC_BITS);
157 ssc_step_size += frac;
158 ssc_step_size *= config->ssc_offset;
159 ssc_step_size *= (config->ssc_adj_per + 1);
160 ssc_step_size = div_u64(ssc_step_size, (ssc_per + 1));
161 ssc_step_size = DIV_ROUND_CLOSEST_ULL(ssc_step_size, 1000000);
163 config->ssc_div_per = ssc_per;
164 config->ssc_stepsize = ssc_step_size;
166 pr_debug("SCC: Dec:%d, frac:%llu, frac_bits:%d\n",
167 config->decimal_div_start, frac, FRAC_BITS);
168 pr_debug("SSC: div_per:0x%X, stepsize:0x%X, adjper:0x%X\n",
169 ssc_per, (u32)ssc_step_size, config->ssc_adj_per);
172 static void dsi_pll_ssc_commit(struct dsi_pll_7nm *pll, struct dsi_pll_config *config)
174 void __iomem *base = pll->phy->pll_base;
176 if (config->enable_ssc) {
177 pr_debug("SSC is enabled\n");
179 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1,
180 config->ssc_stepsize & 0xff);
181 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1,
182 config->ssc_stepsize >> 8);
183 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1,
184 config->ssc_div_per & 0xff);
185 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1,
186 config->ssc_div_per >> 8);
187 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1,
188 config->ssc_adj_per & 0xff);
189 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1,
190 config->ssc_adj_per >> 8);
191 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_CONTROL,
192 SSC_EN | (config->ssc_center ? SSC_CENTER : 0));
196 static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
198 void __iomem *base = pll->phy->pll_base;
199 u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00;
201 if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
202 if (pll->vco_current_rate >= 3100000000ULL)
203 analog_controls_five_1 = 0x03;
205 if (pll->vco_current_rate < 1520000000ULL)
207 else if (pll->vco_current_rate < 2990000000ULL)
211 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1,
212 analog_controls_five_1);
213 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1);
214 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE, 0x01);
215 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03);
216 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE, 0x00);
217 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_DSM_DIVIDER, 0x00);
218 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e);
219 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40);
220 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE, 0xba);
221 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE, 0x0c);
222 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_OUTDIV, 0x00);
223 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE, 0x00);
224 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO, 0x08);
225 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x0a);
226 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1, 0xc0);
227 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x84);
228 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x82);
229 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1, 0x4c);
230 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80);
231 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x29);
232 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f);
233 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a);
234 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT,
235 pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1 ? 0x3f : 0x22);
237 if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
238 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
240 dsi_phy_write(pll->slave->phy->pll_base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
244 static void dsi_pll_commit(struct dsi_pll_7nm *pll, struct dsi_pll_config *config)
246 void __iomem *base = pll->phy->pll_base;
248 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12);
249 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1, config->decimal_div_start);
250 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1,
251 config->frac_div_start & 0xff);
252 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1,
253 (config->frac_div_start & 0xff00) >> 8);
254 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1,
255 (config->frac_div_start & 0x30000) >> 16);
256 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1, 0x40);
257 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY, 0x06);
258 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CMODE_1, 0x10); /* TODO: 0x00 for CPHY */
259 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS, config->pll_clock_inverters);
262 static int dsi_pll_7nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
263 unsigned long parent_rate)
265 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
266 struct dsi_pll_config config;
268 DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_7nm->phy->id, rate,
271 pll_7nm->vco_current_rate = rate;
273 dsi_pll_setup_config(&config);
275 dsi_pll_calc_dec_frac(pll_7nm, &config);
277 dsi_pll_calc_ssc(pll_7nm, &config);
279 dsi_pll_commit(pll_7nm, &config);
281 dsi_pll_config_hzindep_reg(pll_7nm);
283 dsi_pll_ssc_commit(pll_7nm, &config);
285 /* flush, ensure all register writes are done*/
291 static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll)
295 u32 const delay_us = 100;
296 u32 const timeout_us = 5000;
298 rc = readl_poll_timeout_atomic(pll->phy->pll_base +
299 REG_DSI_7nm_PHY_PLL_COMMON_STATUS_ONE,
301 ((status & BIT(0)) > 0),
305 pr_err("DSI PLL(%d) lock failed, status=0x%08x\n",
306 pll->phy->id, status);
311 static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll)
313 u32 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
315 dsi_phy_write(pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0);
316 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0, data & ~BIT(5));
320 static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll)
322 u32 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
324 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0, data | BIT(5));
325 dsi_phy_write(pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0xc0);
329 static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll)
333 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
334 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data & ~BIT(5));
337 static void dsi_pll_enable_global_clk(struct dsi_pll_7nm *pll)
341 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x04);
343 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
344 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1,
345 data | BIT(5) | BIT(4));
348 static void dsi_pll_phy_dig_reset(struct dsi_pll_7nm *pll)
351 * Reset the PHY digital domain. This would be needed when
352 * coming out of a CX or analog rail power collapse while
353 * ensuring that the pads maintain LP00 or LP11 state
355 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, BIT(0));
356 wmb(); /* Ensure that the reset is deasserted */
357 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, 0x0);
358 wmb(); /* Ensure that the reset is deasserted */
361 static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw)
363 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
366 dsi_pll_enable_pll_bias(pll_7nm);
368 dsi_pll_enable_pll_bias(pll_7nm->slave);
371 dsi_phy_write(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0x01);
374 * ensure all PLL configurations are written prior to checking
379 /* Check for PLL lock */
380 rc = dsi_pll_7nm_lock_status(pll_7nm);
382 pr_err("PLL(%d) lock failed\n", pll_7nm->phy->id);
386 pll_7nm->phy->pll_on = true;
389 * assert power on reset for PHY digital in case the PLL is
390 * enabled after CX of analog domain power collapse. This needs
391 * to be done before enabling the global clk.
393 dsi_pll_phy_dig_reset(pll_7nm);
395 dsi_pll_phy_dig_reset(pll_7nm->slave);
397 dsi_pll_enable_global_clk(pll_7nm);
399 dsi_pll_enable_global_clk(pll_7nm->slave);
405 static void dsi_pll_disable_sub(struct dsi_pll_7nm *pll)
407 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0);
408 dsi_pll_disable_pll_bias(pll);
411 static void dsi_pll_7nm_vco_unprepare(struct clk_hw *hw)
413 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
416 * To avoid any stray glitches while abruptly powering down the PLL
417 * make sure to gate the clock using the clock enable bit before
418 * powering down the PLL
420 dsi_pll_disable_global_clk(pll_7nm);
421 dsi_phy_write(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0);
422 dsi_pll_disable_sub(pll_7nm);
423 if (pll_7nm->slave) {
424 dsi_pll_disable_global_clk(pll_7nm->slave);
425 dsi_pll_disable_sub(pll_7nm->slave);
427 /* flush, ensure all register writes are done */
429 pll_7nm->phy->pll_on = false;
432 static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw,
433 unsigned long parent_rate)
435 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
436 void __iomem *base = pll_7nm->phy->pll_base;
437 u64 ref_clk = VCO_REF_CLK_RATE;
444 dec = dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1);
447 frac = dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1);
448 frac |= ((dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1) &
450 frac |= ((dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1) &
455 * 1. Assumes prescaler is disabled
457 multiplier = 1 << FRAC_BITS;
458 pll_freq = dec * (ref_clk * 2);
459 tmp64 = (ref_clk * 2 * frac);
460 pll_freq += div_u64(tmp64, multiplier);
464 DBG("DSI PLL%d returning vco rate = %lu, dec = %x, frac = %x",
465 pll_7nm->phy->id, (unsigned long)vco_rate, dec, frac);
467 return (unsigned long)vco_rate;
470 static long dsi_pll_7nm_clk_round_rate(struct clk_hw *hw,
471 unsigned long rate, unsigned long *parent_rate)
473 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
475 if (rate < pll_7nm->phy->cfg->min_pll_rate)
476 return pll_7nm->phy->cfg->min_pll_rate;
477 else if (rate > pll_7nm->phy->cfg->max_pll_rate)
478 return pll_7nm->phy->cfg->max_pll_rate;
483 static const struct clk_ops clk_ops_dsi_pll_7nm_vco = {
484 .round_rate = dsi_pll_7nm_clk_round_rate,
485 .set_rate = dsi_pll_7nm_vco_set_rate,
486 .recalc_rate = dsi_pll_7nm_vco_recalc_rate,
487 .prepare = dsi_pll_7nm_vco_prepare,
488 .unprepare = dsi_pll_7nm_vco_unprepare,
495 static void dsi_7nm_pll_save_state(struct msm_dsi_phy *phy)
497 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
498 struct pll_7nm_cached_state *cached = &pll_7nm->cached_state;
499 void __iomem *phy_base = pll_7nm->phy->base;
500 u32 cmn_clk_cfg0, cmn_clk_cfg1;
502 cached->pll_out_div = dsi_phy_read(pll_7nm->phy->pll_base +
503 REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
504 cached->pll_out_div &= 0x3;
506 cmn_clk_cfg0 = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0);
507 cached->bit_clk_div = cmn_clk_cfg0 & 0xf;
508 cached->pix_clk_div = (cmn_clk_cfg0 & 0xf0) >> 4;
510 cmn_clk_cfg1 = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
511 cached->pll_mux = cmn_clk_cfg1 & 0x3;
513 DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x",
514 pll_7nm->phy->id, cached->pll_out_div, cached->bit_clk_div,
515 cached->pix_clk_div, cached->pll_mux);
518 static int dsi_7nm_pll_restore_state(struct msm_dsi_phy *phy)
520 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
521 struct pll_7nm_cached_state *cached = &pll_7nm->cached_state;
522 void __iomem *phy_base = pll_7nm->phy->base;
526 val = dsi_phy_read(pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
528 val |= cached->pll_out_div;
529 dsi_phy_write(pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE, val);
531 dsi_phy_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0,
532 cached->bit_clk_div | (cached->pix_clk_div << 4));
534 val = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
536 val |= cached->pll_mux;
537 dsi_phy_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val);
539 ret = dsi_pll_7nm_vco_set_rate(phy->vco_hw,
540 pll_7nm->vco_current_rate,
543 DRM_DEV_ERROR(&pll_7nm->phy->pdev->dev,
544 "restore vco rate failed. ret=%d\n", ret);
548 DBG("DSI PLL%d", pll_7nm->phy->id);
553 static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy)
555 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
556 void __iomem *base = phy->base;
557 u32 data = 0x0; /* internal PLL */
559 DBG("DSI PLL%d", pll_7nm->phy->id);
561 switch (phy->usecase) {
562 case MSM_DSI_PHY_STANDALONE:
564 case MSM_DSI_PHY_MASTER:
565 pll_7nm->slave = pll_7nm_list[(pll_7nm->phy->id + 1) % DSI_MAX];
567 case MSM_DSI_PHY_SLAVE:
568 data = 0x1; /* external PLL */
575 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, (data << 2));
581 * The post dividers and mux clocks are created using the standard divider and
582 * mux API. Unlike the 14nm PHY, the slave PLL doesn't need its dividers/mux
583 * state to follow the master PLL's divider/mux state. Therefore, we don't
584 * require special clock ops that also configure the slave PLL registers
586 static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provided_clocks)
588 char clk_name[32], parent[32], vco_name[32];
589 char parent2[32], parent3[32], parent4[32];
590 struct clk_init_data vco_init = {
591 .parent_names = (const char *[]){ "bi_tcxo" },
594 .flags = CLK_IGNORE_UNUSED,
595 .ops = &clk_ops_dsi_pll_7nm_vco,
597 struct device *dev = &pll_7nm->phy->pdev->dev;
601 DBG("DSI%d", pll_7nm->phy->id);
603 snprintf(vco_name, 32, "dsi%dvco_clk", pll_7nm->phy->id);
604 pll_7nm->clk_hw.init = &vco_init;
606 ret = devm_clk_hw_register(dev, &pll_7nm->clk_hw);
610 snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id);
611 snprintf(parent, 32, "dsi%dvco_clk", pll_7nm->phy->id);
613 hw = devm_clk_hw_register_divider(dev, clk_name,
614 parent, CLK_SET_RATE_PARENT,
615 pll_7nm->phy->pll_base +
616 REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE,
617 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
623 snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id);
624 snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id);
626 /* BIT CLK: DIV_CTRL_3_0 */
627 hw = devm_clk_hw_register_divider(dev, clk_name, parent,
630 REG_DSI_7nm_PHY_CMN_CLK_CFG0,
631 0, 4, CLK_DIVIDER_ONE_BASED,
632 &pll_7nm->postdiv_lock);
638 snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_7nm->phy->id);
639 snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id);
641 /* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */
642 hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
643 CLK_SET_RATE_PARENT, 1, 8);
649 provided_clocks[DSI_BYTE_PLL_CLK] = hw;
651 snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->phy->id);
652 snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id);
654 hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
661 snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->phy->id);
662 snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id);
664 hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
671 snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_7nm->phy->id);
672 snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id);
673 snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->phy->id);
674 snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id);
675 snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->phy->id);
677 hw = devm_clk_hw_register_mux(dev, clk_name,
679 parent, parent2, parent3, parent4
680 }), 4, 0, pll_7nm->phy->base +
681 REG_DSI_7nm_PHY_CMN_CLK_CFG1,
688 snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_7nm->phy->id);
689 snprintf(parent, 32, "dsi%d_pclk_mux", pll_7nm->phy->id);
691 /* PIX CLK DIV : DIV_CTRL_7_4*/
692 hw = devm_clk_hw_register_divider(dev, clk_name, parent,
693 0, pll_7nm->phy->base +
694 REG_DSI_7nm_PHY_CMN_CLK_CFG0,
695 4, 4, CLK_DIVIDER_ONE_BASED,
696 &pll_7nm->postdiv_lock);
702 provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
711 static int dsi_pll_7nm_init(struct msm_dsi_phy *phy)
713 struct platform_device *pdev = phy->pdev;
714 struct dsi_pll_7nm *pll_7nm;
717 pll_7nm = devm_kzalloc(&pdev->dev, sizeof(*pll_7nm), GFP_KERNEL);
721 DBG("DSI PLL%d", phy->id);
723 pll_7nm_list[phy->id] = pll_7nm;
725 spin_lock_init(&pll_7nm->postdiv_lock);
729 ret = pll_7nm_register(pll_7nm, phy->provided_clocks->hws);
731 DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
735 phy->vco_hw = &pll_7nm->clk_hw;
737 /* TODO: Remove this when we have proper display handover support */
738 msm_dsi_phy_pll_save_state(phy);
743 static int dsi_phy_hw_v4_0_is_pll_on(struct msm_dsi_phy *phy)
745 void __iomem *base = phy->base;
748 data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL);
749 mb(); /* make sure read happened */
751 return (data & BIT(0));
754 static void dsi_phy_hw_v4_0_config_lpcdrx(struct msm_dsi_phy *phy, bool enable)
756 void __iomem *lane_base = phy->lane_base;
757 int phy_lane_0 = 0; /* TODO: Support all lane swap configs */
760 * LPRX and CDRX need to enabled only for physical data lane
761 * corresponding to the logical data lane 0
764 dsi_phy_write(lane_base +
765 REG_DSI_7nm_PHY_LN_LPRX_CTRL(phy_lane_0), 0x3);
767 dsi_phy_write(lane_base +
768 REG_DSI_7nm_PHY_LN_LPRX_CTRL(phy_lane_0), 0);
771 static void dsi_phy_hw_v4_0_lane_settings(struct msm_dsi_phy *phy)
774 const u8 tx_dctrl_0[] = { 0x00, 0x00, 0x00, 0x04, 0x01 };
775 const u8 tx_dctrl_1[] = { 0x40, 0x40, 0x40, 0x46, 0x41 };
776 const u8 *tx_dctrl = tx_dctrl_0;
777 void __iomem *lane_base = phy->lane_base;
779 if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1)
780 tx_dctrl = tx_dctrl_1;
782 /* Strength ctrl settings */
783 for (i = 0; i < 5; i++) {
785 * Disable LPRX and CDRX for all lanes. And later on, it will
786 * be only enabled for the physical data lane corresponding
787 * to the logical data lane 0
789 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_LPRX_CTRL(i), 0);
790 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_PIN_SWAP(i), 0x0);
793 dsi_phy_hw_v4_0_config_lpcdrx(phy, true);
796 for (i = 0; i < 5; i++) {
797 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_CFG0(i), 0x0);
798 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_CFG1(i), 0x0);
799 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_CFG2(i), i == 4 ? 0x8a : 0xa);
800 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_TX_DCTRL(i), tx_dctrl[i]);
804 static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
805 struct msm_dsi_phy_clk_request *clk_req)
809 u32 const delay_us = 5;
810 u32 const timeout_us = 1000;
811 struct msm_dsi_dphy_timing *timing = &phy->timing;
812 void __iomem *base = phy->base;
813 bool less_than_1500_mhz;
814 u32 vreg_ctrl_0, glbl_str_swi_cal_sel_ctrl, glbl_hstx_str_ctrl_0;
815 u32 glbl_rescode_top_ctrl, glbl_rescode_bot_ctrl;
820 if (msm_dsi_dphy_timing_calc_v4(timing, clk_req)) {
821 DRM_DEV_ERROR(&phy->pdev->dev,
822 "%s: D-PHY timing calculation failed\n", __func__);
826 if (dsi_phy_hw_v4_0_is_pll_on(phy))
827 pr_warn("PLL turned on before configuring PHY\n");
829 /* wait for REFGEN READY */
830 ret = readl_poll_timeout_atomic(base + REG_DSI_7nm_PHY_CMN_PHY_STATUS,
831 status, (status & BIT(0)),
832 delay_us, timeout_us);
834 pr_err("Ref gen not ready. Aborting\n");
838 /* TODO: CPHY enable path (this is for DPHY only) */
840 /* Alter PHY configurations if data rate less than 1.5GHZ*/
841 less_than_1500_mhz = (clk_req->bitclk_rate <= 1500000000);
843 if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
844 vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
845 glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00;
846 glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c;
847 glbl_str_swi_cal_sel_ctrl = 0x00;
848 glbl_hstx_str_ctrl_0 = 0x88;
850 vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59;
851 glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00;
852 glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88;
853 glbl_rescode_top_ctrl = 0x03;
854 glbl_rescode_bot_ctrl = 0x3c;
857 /* de-assert digital and pll power down */
858 data = BIT(6) | BIT(5);
859 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, data);
861 /* Assert PLL core reset */
862 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0x00);
864 /* turn off resync FIFO */
865 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0x00);
867 /* program CMN_CTRL_4 for minor_ver 2 chipsets*/
868 data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0);
869 data = data & (0xf0);
871 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_4, 0x04);
873 /* Configure PHY lane swap (TODO: we need to calculate this) */
874 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CFG0, 0x21);
875 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CFG1, 0x84);
878 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_VREG_CTRL_0, vreg_ctrl_0);
879 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_VREG_CTRL_1, 0x5c);
880 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x00);
881 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL,
882 glbl_str_swi_cal_sel_ctrl);
883 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0,
884 glbl_hstx_str_ctrl_0);
885 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_0, 0x00);
886 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL,
887 glbl_rescode_top_ctrl);
888 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL,
889 glbl_rescode_bot_ctrl);
890 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_LPTX_STR_CTRL, 0x55);
892 /* Remove power down from all blocks */
893 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, 0x7f);
895 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL0, 0x1f);
897 /* Select full-rate mode */
898 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_2, 0x40);
900 ret = dsi_7nm_set_usecase(phy);
902 DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
907 /* DSI PHY timings */
908 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0, 0x00);
909 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1, timing->clk_zero);
910 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2, timing->clk_prepare);
911 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3, timing->clk_trail);
912 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4, timing->hs_exit);
913 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5, timing->hs_zero);
914 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6, timing->hs_prepare);
915 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7, timing->hs_trail);
916 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8, timing->hs_rqst);
917 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9, 0x02);
918 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10, 0x04);
919 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11, 0x00);
920 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_12,
921 timing->shared_timings.clk_pre);
922 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_13,
923 timing->shared_timings.clk_post);
925 /* DSI lane settings */
926 dsi_phy_hw_v4_0_lane_settings(phy);
928 DBG("DSI%d PHY enabled", phy->id);
933 static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy)
935 void __iomem *base = phy->base;
940 if (dsi_phy_hw_v4_0_is_pll_on(phy))
941 pr_warn("Turning OFF PHY while PLL is on\n");
943 dsi_phy_hw_v4_0_config_lpcdrx(phy, false);
944 data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_CTRL_0);
946 /* disable all lanes */
948 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, data);
949 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL0, 0);
951 /* Turn off all PHY blocks */
952 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, 0x00);
953 /* make sure phy is turned off */
956 DBG("DSI%d PHY disabled", phy->id);
959 const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
960 .has_phy_lane = true,
968 .enable = dsi_7nm_phy_enable,
969 .disable = dsi_7nm_phy_disable,
970 .pll_init = dsi_pll_7nm_init,
971 .save_pll_state = dsi_7nm_pll_save_state,
972 .restore_pll_state = dsi_7nm_pll_restore_state,
974 .min_pll_rate = 600000000UL,
975 .max_pll_rate = (5000000000ULL < ULONG_MAX) ? 5000000000ULL : ULONG_MAX,
976 .io_start = { 0xae94400, 0xae96400 },
978 .quirks = DSI_PHY_7NM_QUIRK_V4_1,
981 const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = {
982 .has_phy_lane = true,
990 .enable = dsi_7nm_phy_enable,
991 .disable = dsi_7nm_phy_disable,
992 .pll_init = dsi_pll_7nm_init,
993 .save_pll_state = dsi_7nm_pll_save_state,
994 .restore_pll_state = dsi_7nm_pll_restore_state,
996 .min_pll_rate = 1000000000UL,
997 .max_pll_rate = 3500000000UL,
998 .io_start = { 0xae94400, 0xae96400 },