drm/msm: Generated register update

[linux-2.6-microblaze.git] / drivers / gpu / drm / msm / dsi / dsi_phy_5nm.xml.h

#ifndef DSI_PHY_5NM_XML
#define DSI_PHY_5NM_XML

/* Autogenerated file, DO NOT EDIT manually!

This file was generated by the rules-ng-ng headergen tool in this git repository:
http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git

The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml                   (    981 bytes, from 2021-06-05 21:37:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml   (   1572 bytes, from 2021-02-18 16:45:44)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml              (  20912 bytes, from 2021-02-18 16:45:44)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml        (   2849 bytes, from 2021-02-18 16:45:44)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml              (  37461 bytes, from 2021-02-18 16:45:44)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml               (  15291 bytes, from 2021-06-15 22:36:13)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml        (   3236 bytes, from 2021-06-05 21:37:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml (   4935 bytes, from 2021-05-21 19:18:08)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml      (   7004 bytes, from 2021-05-21 19:18:08)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml      (   3712 bytes, from 2021-05-21 19:18:08)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml      (   5381 bytes, from 2021-05-21 19:18:08)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml      (   4499 bytes, from 2021-05-21 19:18:08)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml       (  10953 bytes, from 2021-05-21 19:18:08)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml       (  10900 bytes, from 2021-05-21 19:18:08)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml              (    602 bytes, from 2021-02-18 16:45:44)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml           (   1686 bytes, from 2021-02-18 16:45:44)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml           (    600 bytes, from 2021-02-18 16:45:44)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml             (  41874 bytes, from 2021-02-18 16:45:44)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml               (  10416 bytes, from 2021-02-18 16:45:44)

Copyright (C) 2013-2021 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)

Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:

The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/


#define REG_DSI_5nm_PHY_CMN_REVISION_ID0                        0x00000000

#define REG_DSI_5nm_PHY_CMN_REVISION_ID1                        0x00000004

#define REG_DSI_5nm_PHY_CMN_REVISION_ID2                        0x00000008

#define REG_DSI_5nm_PHY_CMN_REVISION_ID3                        0x0000000c

#define REG_DSI_5nm_PHY_CMN_CLK_CFG0                            0x00000010

#define REG_DSI_5nm_PHY_CMN_CLK_CFG1                            0x00000014

#define REG_DSI_5nm_PHY_CMN_GLBL_CTRL                           0x00000018

#define REG_DSI_5nm_PHY_CMN_RBUF_CTRL                           0x0000001c

#define REG_DSI_5nm_PHY_CMN_VREG_CTRL_0                         0x00000020

#define REG_DSI_5nm_PHY_CMN_CTRL_0                              0x00000024

#define REG_DSI_5nm_PHY_CMN_CTRL_1                              0x00000028

#define REG_DSI_5nm_PHY_CMN_CTRL_2                              0x0000002c

#define REG_DSI_5nm_PHY_CMN_CTRL_3                              0x00000030

#define REG_DSI_5nm_PHY_CMN_LANE_CFG0                           0x00000034

#define REG_DSI_5nm_PHY_CMN_LANE_CFG1                           0x00000038

#define REG_DSI_5nm_PHY_CMN_PLL_CNTRL                           0x0000003c

#define REG_DSI_5nm_PHY_CMN_DPHY_SOT                            0x00000040

#define REG_DSI_5nm_PHY_CMN_LANE_CTRL0                          0x000000a0

#define REG_DSI_5nm_PHY_CMN_LANE_CTRL1                          0x000000a4

#define REG_DSI_5nm_PHY_CMN_LANE_CTRL2                          0x000000a8

#define REG_DSI_5nm_PHY_CMN_LANE_CTRL3                          0x000000ac

#define REG_DSI_5nm_PHY_CMN_LANE_CTRL4                          0x000000b0

#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_0                       0x000000b4

#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_1                       0x000000b8

#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_2                       0x000000bc

#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_3                       0x000000c0

#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_4                       0x000000c4

#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_5                       0x000000c8

#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_6                       0x000000cc

#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_7                       0x000000d0

#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_8                       0x000000d4

#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_9                       0x000000d8

#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_10                      0x000000dc

#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_11                      0x000000e0

#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_12                      0x000000e4

#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_13                      0x000000e8

#define REG_DSI_5nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0                0x000000ec

#define REG_DSI_5nm_PHY_CMN_GLBL_HSTX_STR_CTRL_1                0x000000f0

#define REG_DSI_5nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL        0x000000f4

#define REG_DSI_5nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL        0x000000f8

#define REG_DSI_5nm_PHY_CMN_GLBL_RESCODE_OFFSET_MID_CTRL        0x000000fc

#define REG_DSI_5nm_PHY_CMN_GLBL_LPTX_STR_CTRL                  0x00000100

#define REG_DSI_5nm_PHY_CMN_GLBL_PEMPH_CTRL_0                   0x00000104

#define REG_DSI_5nm_PHY_CMN_GLBL_PEMPH_CTRL_1                   0x00000108

#define REG_DSI_5nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL           0x0000010c

#define REG_DSI_5nm_PHY_CMN_VREG_CTRL_1                         0x00000110

#define REG_DSI_5nm_PHY_CMN_CTRL_4                              0x00000114

#define REG_DSI_5nm_PHY_CMN_PHY_STATUS                          0x00000140

#define REG_DSI_5nm_PHY_CMN_LANE_STATUS0                        0x00000148

#define REG_DSI_5nm_PHY_CMN_LANE_STATUS1                        0x0000014c

static inline uint32_t REG_DSI_5nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }

static inline uint32_t REG_DSI_5nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }

static inline uint32_t REG_DSI_5nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }

static inline uint32_t REG_DSI_5nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }

static inline uint32_t REG_DSI_5nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x80*i0; }

static inline uint32_t REG_DSI_5nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000010 + 0x80*i0; }

static inline uint32_t REG_DSI_5nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000014 + 0x80*i0; }

static inline uint32_t REG_DSI_5nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }

#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_ONE                 0x00000000

#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_TWO                 0x00000004

#define REG_DSI_5nm_PHY_PLL_INT_LOOP_SETTINGS                   0x00000008

#define REG_DSI_5nm_PHY_PLL_INT_LOOP_SETTINGS_TWO               0x0000000c

#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_THREE               0x00000010

#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_FOUR                0x00000014

#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_FIVE                0x00000018

#define REG_DSI_5nm_PHY_PLL_INT_LOOP_CONTROLS                   0x0000001c

#define REG_DSI_5nm_PHY_PLL_DSM_DIVIDER                         0x00000020

#define REG_DSI_5nm_PHY_PLL_FEEDBACK_DIVIDER                    0x00000024

#define REG_DSI_5nm_PHY_PLL_SYSTEM_MUXES                        0x00000028

#define REG_DSI_5nm_PHY_PLL_FREQ_UPDATE_CONTROL_OVERRIDES       0x0000002c

#define REG_DSI_5nm_PHY_PLL_CMODE                               0x00000030

#define REG_DSI_5nm_PHY_PLL_PSM_CTRL                            0x00000034

#define REG_DSI_5nm_PHY_PLL_RSM_CTRL                            0x00000038

#define REG_DSI_5nm_PHY_PLL_VCO_TUNE_MAP                        0x0000003c

#define REG_DSI_5nm_PHY_PLL_PLL_CNTRL                           0x00000040

#define REG_DSI_5nm_PHY_PLL_CALIBRATION_SETTINGS                0x00000044

#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_TIMER_LOW              0x00000048

#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_TIMER_HIGH             0x0000004c

#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_SETTINGS               0x00000050

#define REG_DSI_5nm_PHY_PLL_BAND_SEL_MIN                        0x00000054

#define REG_DSI_5nm_PHY_PLL_BAND_SEL_MAX                        0x00000058

#define REG_DSI_5nm_PHY_PLL_BAND_SEL_PFILT                      0x0000005c

#define REG_DSI_5nm_PHY_PLL_BAND_SEL_IFILT                      0x00000060

#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_TWO           0x00000064

#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE         0x00000068

#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_FOUR          0x0000006c

#define REG_DSI_5nm_PHY_PLL_BAND_SEL_ICODE_HIGH                 0x00000070

#define REG_DSI_5nm_PHY_PLL_BAND_SEL_ICODE_LOW                  0x00000074

#define REG_DSI_5nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE            0x00000078

#define REG_DSI_5nm_PHY_PLL_FREQ_DETECT_THRESH                  0x0000007c

#define REG_DSI_5nm_PHY_PLL_FREQ_DET_REFCLK_HIGH                0x00000080

#define REG_DSI_5nm_PHY_PLL_FREQ_DET_REFCLK_LOW                 0x00000084

#define REG_DSI_5nm_PHY_PLL_FREQ_DET_PLLCLK_HIGH                0x00000088

#define REG_DSI_5nm_PHY_PLL_FREQ_DET_PLLCLK_LOW                 0x0000008c

#define REG_DSI_5nm_PHY_PLL_PFILT                               0x00000090

#define REG_DSI_5nm_PHY_PLL_IFILT                               0x00000094

#define REG_DSI_5nm_PHY_PLL_PLL_GAIN                            0x00000098

#define REG_DSI_5nm_PHY_PLL_ICODE_LOW                           0x0000009c

#define REG_DSI_5nm_PHY_PLL_ICODE_HIGH                          0x000000a0

#define REG_DSI_5nm_PHY_PLL_LOCKDET                             0x000000a4

#define REG_DSI_5nm_PHY_PLL_OUTDIV                              0x000000a8

#define REG_DSI_5nm_PHY_PLL_FASTLOCK_CONTROL                    0x000000ac

#define REG_DSI_5nm_PHY_PLL_PASS_OUT_OVERRIDE_ONE               0x000000b0

#define REG_DSI_5nm_PHY_PLL_PASS_OUT_OVERRIDE_TWO               0x000000b4

#define REG_DSI_5nm_PHY_PLL_CORE_OVERRIDE                       0x000000b8

#define REG_DSI_5nm_PHY_PLL_CORE_INPUT_OVERRIDE                 0x000000bc

#define REG_DSI_5nm_PHY_PLL_RATE_CHANGE                         0x000000c0

#define REG_DSI_5nm_PHY_PLL_PLL_DIGITAL_TIMERS                  0x000000c4

#define REG_DSI_5nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO              0x000000c8

#define REG_DSI_5nm_PHY_PLL_DECIMAL_DIV_START                   0x000000cc

#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_LOW                  0x000000d0

#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_MID                  0x000000d4

#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_HIGH                 0x000000d8

#define REG_DSI_5nm_PHY_PLL_DEC_FRAC_MUXES                      0x000000dc

#define REG_DSI_5nm_PHY_PLL_DECIMAL_DIV_START_1                 0x000000e0

#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_LOW_1                0x000000e4

#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_MID_1                0x000000e8

#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_HIGH_1               0x000000ec

#define REG_DSI_5nm_PHY_PLL_DECIMAL_DIV_START_2                 0x000000f0

#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_LOW_2                0x000000f4

#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_MID_2                0x000000f8

#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_HIGH_2               0x000000fc

#define REG_DSI_5nm_PHY_PLL_MASH_CONTROL                        0x00000100

#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_LOW                    0x00000104

#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_HIGH                   0x00000108

#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_LOW                     0x0000010c

#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_HIGH                    0x00000110

#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_LOW                      0x00000114

#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_HIGH                     0x00000118

#define REG_DSI_5nm_PHY_PLL_SSC_MUX_CONTROL                     0x0000011c

#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_LOW_1                  0x00000120

#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_HIGH_1                 0x00000124

#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_LOW_1                   0x00000128

#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_HIGH_1                  0x0000012c

#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_LOW_1                    0x00000130

#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_HIGH_1                   0x00000134

#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_LOW_2                  0x00000138

#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_HIGH_2                 0x0000013c

#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_LOW_2                   0x00000140

#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_HIGH_2                  0x00000144

#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_LOW_2                    0x00000148

#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_HIGH_2                   0x0000014c

#define REG_DSI_5nm_PHY_PLL_SSC_CONTROL                         0x00000150

#define REG_DSI_5nm_PHY_PLL_PLL_OUTDIV_RATE                     0x00000154

#define REG_DSI_5nm_PHY_PLL_PLL_LOCKDET_RATE_1                  0x00000158

#define REG_DSI_5nm_PHY_PLL_PLL_LOCKDET_RATE_2                  0x0000015c

#define REG_DSI_5nm_PHY_PLL_PLL_PROP_GAIN_RATE_1                0x00000160

#define REG_DSI_5nm_PHY_PLL_PLL_PROP_GAIN_RATE_2                0x00000164

#define REG_DSI_5nm_PHY_PLL_PLL_BAND_SEL_RATE_1                 0x00000168

#define REG_DSI_5nm_PHY_PLL_PLL_BAND_SEL_RATE_2                 0x0000016c

#define REG_DSI_5nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1           0x00000170

#define REG_DSI_5nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_2           0x00000174

#define REG_DSI_5nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1        0x00000178

#define REG_DSI_5nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_2        0x0000017c

#define REG_DSI_5nm_PHY_PLL_PLL_FASTLOCK_EN_BAND                0x00000180

#define REG_DSI_5nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MID            0x00000184

#define REG_DSI_5nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_HIGH           0x00000188

#define REG_DSI_5nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MUX            0x0000018c

#define REG_DSI_5nm_PHY_PLL_PLL_LOCK_OVERRIDE                   0x00000190

#define REG_DSI_5nm_PHY_PLL_PLL_LOCK_DELAY                      0x00000194

#define REG_DSI_5nm_PHY_PLL_PLL_LOCK_MIN_DELAY                  0x00000198

#define REG_DSI_5nm_PHY_PLL_CLOCK_INVERTERS                     0x0000019c

#define REG_DSI_5nm_PHY_PLL_SPARE_AND_JPC_OVERRIDES             0x000001a0

#define REG_DSI_5nm_PHY_PLL_BIAS_CONTROL_1                      0x000001a4

#define REG_DSI_5nm_PHY_PLL_BIAS_CONTROL_2                      0x000001a8

#define REG_DSI_5nm_PHY_PLL_ALOG_OBSV_BUS_CTRL_1                0x000001ac

#define REG_DSI_5nm_PHY_PLL_COMMON_STATUS_ONE                   0x000001b0

#define REG_DSI_5nm_PHY_PLL_COMMON_STATUS_TWO                   0x000001b4

#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL                        0x000001b8

#define REG_DSI_5nm_PHY_PLL_ICODE_ACCUM_STATUS_LOW              0x000001bc

#define REG_DSI_5nm_PHY_PLL_ICODE_ACCUM_STATUS_HIGH             0x000001c0

#define REG_DSI_5nm_PHY_PLL_FD_OUT_LOW                          0x000001c4

#define REG_DSI_5nm_PHY_PLL_FD_OUT_HIGH                         0x000001c8

#define REG_DSI_5nm_PHY_PLL_ALOG_OBSV_BUS_STATUS_1              0x000001cc

#define REG_DSI_5nm_PHY_PLL_PLL_MISC_CONFIG                     0x000001d0

#define REG_DSI_5nm_PHY_PLL_FLL_CONFIG                          0x000001d4

#define REG_DSI_5nm_PHY_PLL_FLL_FREQ_ACQ_TIME                   0x000001d8

#define REG_DSI_5nm_PHY_PLL_FLL_CODE0                           0x000001dc

#define REG_DSI_5nm_PHY_PLL_FLL_CODE1                           0x000001e0

#define REG_DSI_5nm_PHY_PLL_FLL_GAIN0                           0x000001e4

#define REG_DSI_5nm_PHY_PLL_FLL_GAIN1                           0x000001e8

#define REG_DSI_5nm_PHY_PLL_SW_RESET                            0x000001ec

#define REG_DSI_5nm_PHY_PLL_FAST_PWRUP                          0x000001f0

#define REG_DSI_5nm_PHY_PLL_LOCKTIME0                           0x000001f4

#define REG_DSI_5nm_PHY_PLL_LOCKTIME1                           0x000001f8

#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS_SEL                       0x000001fc

#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS0                          0x00000200

#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS1                          0x00000204

#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS2                          0x00000208

#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS3                          0x0000020c

#define REG_DSI_5nm_PHY_PLL_ANALOG_FLL_CONTROL_OVERRIDES        0x00000210

#define REG_DSI_5nm_PHY_PLL_VCO_CONFIG                          0x00000214

#define REG_DSI_5nm_PHY_PLL_VCO_CAL_CODE1_MODE0_STATUS          0x00000218

#define REG_DSI_5nm_PHY_PLL_VCO_CAL_CODE1_MODE1_STATUS          0x0000021c

#define REG_DSI_5nm_PHY_PLL_RESET_SM_STATUS                     0x00000220

#define REG_DSI_5nm_PHY_PLL_TDC_OFFSET                          0x00000224

#define REG_DSI_5nm_PHY_PLL_PS3_PWRDOWN_CONTROLS                0x00000228

#define REG_DSI_5nm_PHY_PLL_PS4_PWRDOWN_CONTROLS                0x0000022c

#define REG_DSI_5nm_PHY_PLL_PLL_RST_CONTROLS                    0x00000230

#define REG_DSI_5nm_PHY_PLL_GEAR_BAND_SELECT_CONTROLS           0x00000234

#define REG_DSI_5nm_PHY_PLL_PSM_CLK_CONTROLS                    0x00000238

#define REG_DSI_5nm_PHY_PLL_SYSTEM_MUXES_2                      0x0000023c

#define REG_DSI_5nm_PHY_PLL_VCO_CONFIG_1                        0x00000240

#define REG_DSI_5nm_PHY_PLL_VCO_CONFIG_2                        0x00000244

#define REG_DSI_5nm_PHY_PLL_CLOCK_INVERTERS_1                   0x00000248

#define REG_DSI_5nm_PHY_PLL_CLOCK_INVERTERS_2                   0x0000024c

#define REG_DSI_5nm_PHY_PLL_CMODE_1                             0x00000250

#define REG_DSI_5nm_PHY_PLL_CMODE_2                             0x00000254

#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1              0x00000258

#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_FIVE_2              0x0000025c

#define REG_DSI_5nm_PHY_PLL_PERF_OPTIMIZE                       0x00000260


#endif /* DSI_PHY_5NM_XML */