drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
   4  * Copyright (C) 2013 Red Hat
   5  * Author: Rob Clark <robdclark@gmail.com>
   6  */
   7
   8 #include <linux/delay.h>
   9 #include <linux/interconnect.h>
  10 #include <linux/of_irq.h>
  11
  12 #include <drm/drm_debugfs.h>
  13 #include <drm/drm_drv.h>
  14 #include <drm/drm_file.h>
  15 #include <drm/drm_vblank.h>
  16
  17 #include "msm_drv.h"
  18 #include "msm_gem.h"
  19 #include "msm_mmu.h"
  20 #include "mdp5_kms.h"
  21
  22 static int mdp5_hw_init(struct msm_kms *kms)
  23 {
  24         struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
  25         struct device *dev = &mdp5_kms->pdev->dev;
  26         unsigned long flags;
  27
  28         pm_runtime_get_sync(dev);
  29
  30         /* Magic unknown register writes:
  31          *
  32          *    W VBIF:0x004 00000001      (mdss_mdp.c:839)
  33          *    W MDP5:0x2e0 0xe9          (mdss_mdp.c:839)
  34          *    W MDP5:0x2e4 0x55          (mdss_mdp.c:839)
  35          *    W MDP5:0x3ac 0xc0000ccc    (mdss_mdp.c:839)
  36          *    W MDP5:0x3b4 0xc0000ccc    (mdss_mdp.c:839)
  37          *    W MDP5:0x3bc 0xcccccc      (mdss_mdp.c:839)
  38          *    W MDP5:0x4a8 0xcccc0c0     (mdss_mdp.c:839)
  39          *    W MDP5:0x4b0 0xccccc0c0    (mdss_mdp.c:839)
  40          *    W MDP5:0x4b8 0xccccc000    (mdss_mdp.c:839)
  41          *
  42          * Downstream fbdev driver gets these register offsets/values
  43          * from DT.. not really sure what these registers are or if
  44          * different values for different boards/SoC's, etc.  I guess
  45          * they are the golden registers.
  46          *
  47          * Not setting these does not seem to cause any problem.  But
  48          * we may be getting lucky with the bootloader initializing
  49          * them for us.  OTOH, if we can always count on the bootloader
  50          * setting the golden registers, then perhaps we don't need to
  51          * care.
  52          */
  53
  54         spin_lock_irqsave(&mdp5_kms->resource_lock, flags);
  55         mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0);
  56         spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags);
  57
  58         mdp5_ctlm_hw_reset(mdp5_kms->ctlm);
  59
  60         pm_runtime_put_sync(dev);
  61
  62         return 0;
  63 }
  64
  65 /* Global/shared object state funcs */
  66
  67 /*
  68  * This is a helper that returns the private state currently in operation.
  69  * Note that this would return the "old_state" if called in the atomic check
  70  * path, and the "new_state" after the atomic swap has been done.
  71  */
  72 struct mdp5_global_state *
  73 mdp5_get_existing_global_state(struct mdp5_kms *mdp5_kms)
  74 {
  75         return to_mdp5_global_state(mdp5_kms->glob_state.state);
  76 }
  77
  78 /*
  79  * This acquires the modeset lock set aside for global state, creates
  80  * a new duplicated private object state.
  81  */
  82 struct mdp5_global_state *mdp5_get_global_state(struct drm_atomic_state *s)
  83 {
  84         struct msm_drm_private *priv = s->dev->dev_private;
  85         struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
  86         struct drm_private_state *priv_state;
  87         int ret;
  88
  89         ret = drm_modeset_lock(&mdp5_kms->glob_state_lock, s->acquire_ctx);
  90         if (ret)
  91                 return ERR_PTR(ret);
  92
  93         priv_state = drm_atomic_get_private_obj_state(s, &mdp5_kms->glob_state);
  94         if (IS_ERR(priv_state))
  95                 return ERR_CAST(priv_state);
  96
  97         return to_mdp5_global_state(priv_state);
  98 }
  99
 100 static struct drm_private_state *
 101 mdp5_global_duplicate_state(struct drm_private_obj *obj)
 102 {
 103         struct mdp5_global_state *state;
 104
 105         state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
 106         if (!state)
 107                 return NULL;
 108
 109         __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
 110
 111         return &state->base;
 112 }
 113
 114 static void mdp5_global_destroy_state(struct drm_private_obj *obj,
 115                                       struct drm_private_state *state)
 116 {
 117         struct mdp5_global_state *mdp5_state = to_mdp5_global_state(state);
 118
 119         kfree(mdp5_state);
 120 }
 121
 122 static const struct drm_private_state_funcs mdp5_global_state_funcs = {
 123         .atomic_duplicate_state = mdp5_global_duplicate_state,
 124         .atomic_destroy_state = mdp5_global_destroy_state,
 125 };
 126
 127 static int mdp5_global_obj_init(struct mdp5_kms *mdp5_kms)
 128 {
 129         struct mdp5_global_state *state;
 130
 131         drm_modeset_lock_init(&mdp5_kms->glob_state_lock);
 132
 133         state = kzalloc(sizeof(*state), GFP_KERNEL);
 134         if (!state)
 135                 return -ENOMEM;
 136
 137         state->mdp5_kms = mdp5_kms;
 138
 139         drm_atomic_private_obj_init(mdp5_kms->dev, &mdp5_kms->glob_state,
 140                                     &state->base,
 141                                     &mdp5_global_state_funcs);
 142         return 0;
 143 }
 144
 145 static void mdp5_enable_commit(struct msm_kms *kms)
 146 {
 147         struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
 148         pm_runtime_get_sync(&mdp5_kms->pdev->dev);
 149 }
 150
 151 static void mdp5_disable_commit(struct msm_kms *kms)
 152 {
 153         struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
 154         pm_runtime_put_sync(&mdp5_kms->pdev->dev);
 155 }
 156
 157 static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state)
 158 {
 159         struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
 160         struct mdp5_global_state *global_state;
 161
 162         global_state = mdp5_get_existing_global_state(mdp5_kms);
 163
 164         if (mdp5_kms->smp)
 165                 mdp5_smp_prepare_commit(mdp5_kms->smp, &global_state->smp);
 166 }
 167
 168 static void mdp5_flush_commit(struct msm_kms *kms, unsigned crtc_mask)
 169 {
 170         /* TODO */
 171 }
 172
 173 static void mdp5_wait_flush(struct msm_kms *kms, unsigned crtc_mask)
 174 {
 175         struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
 176         struct drm_crtc *crtc;
 177
 178         for_each_crtc_mask(mdp5_kms->dev, crtc, crtc_mask)
 179                 mdp5_crtc_wait_for_commit_done(crtc);
 180 }
 181
 182 static void mdp5_complete_commit(struct msm_kms *kms, unsigned crtc_mask)
 183 {
 184         struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
 185         struct mdp5_global_state *global_state;
 186
 187         global_state = mdp5_get_existing_global_state(mdp5_kms);
 188
 189         if (mdp5_kms->smp)
 190                 mdp5_smp_complete_commit(mdp5_kms->smp, &global_state->smp);
 191 }
 192
 193 static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate,
 194                 struct drm_encoder *encoder)
 195 {
 196         return rate;
 197 }
 198
 199 static int mdp5_set_split_display(struct msm_kms *kms,
 200                 struct drm_encoder *encoder,
 201                 struct drm_encoder *slave_encoder,
 202                 bool is_cmd_mode)
 203 {
 204         if (is_cmd_mode)
 205                 return mdp5_cmd_encoder_set_split_display(encoder,
 206                                                         slave_encoder);
 207         else
 208                 return mdp5_vid_encoder_set_split_display(encoder,
 209                                                           slave_encoder);
 210 }
 211
 212 static void mdp5_set_encoder_mode(struct msm_kms *kms,
 213                                   struct drm_encoder *encoder,
 214                                   bool cmd_mode)
 215 {
 216         mdp5_encoder_set_intf_mode(encoder, cmd_mode);
 217 }
 218
 219 static void mdp5_kms_destroy(struct msm_kms *kms)
 220 {
 221         struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
 222         struct msm_gem_address_space *aspace = kms->aspace;
 223         int i;
 224
 225         for (i = 0; i < mdp5_kms->num_hwmixers; i++)
 226                 mdp5_mixer_destroy(mdp5_kms->hwmixers[i]);
 227
 228         for (i = 0; i < mdp5_kms->num_hwpipes; i++)
 229                 mdp5_pipe_destroy(mdp5_kms->hwpipes[i]);
 230
 231         if (aspace) {
 232                 aspace->mmu->funcs->detach(aspace->mmu);
 233                 msm_gem_address_space_put(aspace);
 234         }
 235
 236         mdp_kms_destroy(&mdp5_kms->base);
 237 }
 238
 239 #ifdef CONFIG_DEBUG_FS
 240 static int smp_show(struct seq_file *m, void *arg)
 241 {
 242         struct drm_info_node *node = (struct drm_info_node *) m->private;
 243         struct drm_device *dev = node->minor->dev;
 244         struct msm_drm_private *priv = dev->dev_private;
 245         struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
 246         struct drm_printer p = drm_seq_file_printer(m);
 247
 248         if (!mdp5_kms->smp) {
 249                 drm_printf(&p, "no SMP pool\n");
 250                 return 0;
 251         }
 252
 253         mdp5_smp_dump(mdp5_kms->smp, &p);
 254
 255         return 0;
 256 }
 257
 258 static struct drm_info_list mdp5_debugfs_list[] = {
 259                 {"smp", smp_show },
 260 };
 261
 262 static int mdp5_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor)
 263 {
 264         drm_debugfs_create_files(mdp5_debugfs_list,
 265                                  ARRAY_SIZE(mdp5_debugfs_list),
 266                                  minor->debugfs_root, minor);
 267
 268         return 0;
 269 }
 270 #endif
 271
 272 static const struct mdp_kms_funcs kms_funcs = {
 273         .base = {
 274                 .hw_init         = mdp5_hw_init,
 275                 .irq_preinstall  = mdp5_irq_preinstall,
 276                 .irq_postinstall = mdp5_irq_postinstall,
 277                 .irq_uninstall   = mdp5_irq_uninstall,
 278                 .irq             = mdp5_irq,
 279                 .enable_vblank   = mdp5_enable_vblank,
 280                 .disable_vblank  = mdp5_disable_vblank,
 281                 .flush_commit    = mdp5_flush_commit,
 282                 .enable_commit   = mdp5_enable_commit,
 283                 .disable_commit  = mdp5_disable_commit,
 284                 .prepare_commit  = mdp5_prepare_commit,
 285                 .wait_flush      = mdp5_wait_flush,
 286                 .complete_commit = mdp5_complete_commit,
 287                 .get_format      = mdp_get_format,
 288                 .round_pixclk    = mdp5_round_pixclk,
 289                 .set_split_display = mdp5_set_split_display,
 290                 .set_encoder_mode = mdp5_set_encoder_mode,
 291                 .destroy         = mdp5_kms_destroy,
 292 #ifdef CONFIG_DEBUG_FS
 293                 .debugfs_init    = mdp5_kms_debugfs_init,
 294 #endif
 295         },
 296         .set_irqmask         = mdp5_set_irqmask,
 297 };
 298
 299 static int mdp5_disable(struct mdp5_kms *mdp5_kms)
 300 {
 301         DBG("");
 302
 303         mdp5_kms->enable_count--;
 304         WARN_ON(mdp5_kms->enable_count < 0);
 305
 306         if (mdp5_kms->tbu_rt_clk)
 307                 clk_disable_unprepare(mdp5_kms->tbu_rt_clk);
 308         if (mdp5_kms->tbu_clk)
 309                 clk_disable_unprepare(mdp5_kms->tbu_clk);
 310         clk_disable_unprepare(mdp5_kms->ahb_clk);
 311         clk_disable_unprepare(mdp5_kms->axi_clk);
 312         clk_disable_unprepare(mdp5_kms->core_clk);
 313         if (mdp5_kms->lut_clk)
 314                 clk_disable_unprepare(mdp5_kms->lut_clk);
 315
 316         return 0;
 317 }
 318
 319 static int mdp5_enable(struct mdp5_kms *mdp5_kms)
 320 {
 321         DBG("");
 322
 323         mdp5_kms->enable_count++;
 324
 325         clk_prepare_enable(mdp5_kms->ahb_clk);
 326         clk_prepare_enable(mdp5_kms->axi_clk);
 327         clk_prepare_enable(mdp5_kms->core_clk);
 328         if (mdp5_kms->lut_clk)
 329                 clk_prepare_enable(mdp5_kms->lut_clk);
 330         if (mdp5_kms->tbu_clk)
 331                 clk_prepare_enable(mdp5_kms->tbu_clk);
 332         if (mdp5_kms->tbu_rt_clk)
 333                 clk_prepare_enable(mdp5_kms->tbu_rt_clk);
 334
 335         return 0;
 336 }
 337
 338 static struct drm_encoder *construct_encoder(struct mdp5_kms *mdp5_kms,
 339                                              struct mdp5_interface *intf,
 340                                              struct mdp5_ctl *ctl)
 341 {
 342         struct drm_device *dev = mdp5_kms->dev;
 343         struct msm_drm_private *priv = dev->dev_private;
 344         struct drm_encoder *encoder;
 345
 346         encoder = mdp5_encoder_init(dev, intf, ctl);
 347         if (IS_ERR(encoder)) {
 348                 DRM_DEV_ERROR(dev->dev, "failed to construct encoder\n");
 349                 return encoder;
 350         }
 351
 352         priv->encoders[priv->num_encoders++] = encoder;
 353
 354         return encoder;
 355 }
 356
 357 static int get_dsi_id_from_intf(const struct mdp5_cfg_hw *hw_cfg, int intf_num)
 358 {
 359         const enum mdp5_intf_type *intfs = hw_cfg->intf.connect;
 360         const int intf_cnt = ARRAY_SIZE(hw_cfg->intf.connect);
 361         int id = 0, i;
 362
 363         for (i = 0; i < intf_cnt; i++) {
 364                 if (intfs[i] == INTF_DSI) {
 365                         if (intf_num == i)
 366                                 return id;
 367
 368                         id++;
 369                 }
 370         }
 371
 372         return -EINVAL;
 373 }
 374
 375 static int modeset_init_intf(struct mdp5_kms *mdp5_kms,
 376                              struct mdp5_interface *intf)
 377 {
 378         struct drm_device *dev = mdp5_kms->dev;
 379         struct msm_drm_private *priv = dev->dev_private;
 380         struct mdp5_ctl_manager *ctlm = mdp5_kms->ctlm;
 381         struct mdp5_ctl *ctl;
 382         struct drm_encoder *encoder;
 383         int ret = 0;
 384
 385         switch (intf->type) {
 386         case INTF_eDP:
 387                 if (!priv->edp)
 388                         break;
 389
 390                 ctl = mdp5_ctlm_request(ctlm, intf->num);
 391                 if (!ctl) {
 392                         ret = -EINVAL;
 393                         break;
 394                 }
 395
 396                 encoder = construct_encoder(mdp5_kms, intf, ctl);
 397                 if (IS_ERR(encoder)) {
 398                         ret = PTR_ERR(encoder);
 399                         break;
 400                 }
 401
 402                 ret = msm_edp_modeset_init(priv->edp, dev, encoder);
 403                 break;
 404         case INTF_HDMI:
 405                 if (!priv->hdmi)
 406                         break;
 407
 408                 ctl = mdp5_ctlm_request(ctlm, intf->num);
 409                 if (!ctl) {
 410                         ret = -EINVAL;
 411                         break;
 412                 }
 413
 414                 encoder = construct_encoder(mdp5_kms, intf, ctl);
 415                 if (IS_ERR(encoder)) {
 416                         ret = PTR_ERR(encoder);
 417                         break;
 418                 }
 419
 420                 ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder);
 421                 break;
 422         case INTF_DSI:
 423         {
 424                 const struct mdp5_cfg_hw *hw_cfg =
 425                                         mdp5_cfg_get_hw_config(mdp5_kms->cfg);
 426                 int dsi_id = get_dsi_id_from_intf(hw_cfg, intf->num);
 427
 428                 if ((dsi_id >= ARRAY_SIZE(priv->dsi)) || (dsi_id < 0)) {
 429                         DRM_DEV_ERROR(dev->dev, "failed to find dsi from intf %d\n",
 430                                 intf->num);
 431                         ret = -EINVAL;
 432                         break;
 433                 }
 434
 435                 if (!priv->dsi[dsi_id])
 436                         break;
 437
 438                 ctl = mdp5_ctlm_request(ctlm, intf->num);
 439                 if (!ctl) {
 440                         ret = -EINVAL;
 441                         break;
 442                 }
 443
 444                 encoder = construct_encoder(mdp5_kms, intf, ctl);
 445                 if (IS_ERR(encoder)) {
 446                         ret = PTR_ERR(encoder);
 447                         break;
 448                 }
 449
 450                 ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder);
 451                 break;
 452         }
 453         default:
 454                 DRM_DEV_ERROR(dev->dev, "unknown intf: %d\n", intf->type);
 455                 ret = -EINVAL;
 456                 break;
 457         }
 458
 459         return ret;
 460 }
 461
 462 static int modeset_init(struct mdp5_kms *mdp5_kms)
 463 {
 464         struct drm_device *dev = mdp5_kms->dev;
 465         struct msm_drm_private *priv = dev->dev_private;
 466         unsigned int num_crtcs;
 467         int i, ret, pi = 0, ci = 0;
 468         struct drm_plane *primary[MAX_BASES] = { NULL };
 469         struct drm_plane *cursor[MAX_BASES] = { NULL };
 470
 471         /*
 472          * Construct encoders and modeset initialize connector devices
 473          * for each external display interface.
 474          */
 475         for (i = 0; i < mdp5_kms->num_intfs; i++) {
 476                 ret = modeset_init_intf(mdp5_kms, mdp5_kms->intfs[i]);
 477                 if (ret)
 478                         goto fail;
 479         }
 480
 481         /*
 482          * We should ideally have less number of encoders (set up by parsing
 483          * the MDP5 interfaces) than the number of layer mixers present in HW,
 484          * but let's be safe here anyway
 485          */
 486         num_crtcs = min(priv->num_encoders, mdp5_kms->num_hwmixers);
 487
 488         /*
 489          * Construct planes equaling the number of hw pipes, and CRTCs for the
 490          * N encoders set up by the driver. The first N planes become primary
 491          * planes for the CRTCs, with the remainder as overlay planes:
 492          */
 493         for (i = 0; i < mdp5_kms->num_hwpipes; i++) {
 494                 struct mdp5_hw_pipe *hwpipe = mdp5_kms->hwpipes[i];
 495                 struct drm_plane *plane;
 496                 enum drm_plane_type type;
 497
 498                 if (i < num_crtcs)
 499                         type = DRM_PLANE_TYPE_PRIMARY;
 500                 else if (hwpipe->caps & MDP_PIPE_CAP_CURSOR)
 501                         type = DRM_PLANE_TYPE_CURSOR;
 502                 else
 503                         type = DRM_PLANE_TYPE_OVERLAY;
 504
 505                 plane = mdp5_plane_init(dev, type);
 506                 if (IS_ERR(plane)) {
 507                         ret = PTR_ERR(plane);
 508                         DRM_DEV_ERROR(dev->dev, "failed to construct plane %d (%d)\n", i, ret);
 509                         goto fail;
 510                 }
 511                 priv->planes[priv->num_planes++] = plane;
 512
 513                 if (type == DRM_PLANE_TYPE_PRIMARY)
 514                         primary[pi++] = plane;
 515                 if (type == DRM_PLANE_TYPE_CURSOR)
 516                         cursor[ci++] = plane;
 517         }
 518
 519         for (i = 0; i < num_crtcs; i++) {
 520                 struct drm_crtc *crtc;
 521
 522                 crtc  = mdp5_crtc_init(dev, primary[i], cursor[i], i);
 523                 if (IS_ERR(crtc)) {
 524                         ret = PTR_ERR(crtc);
 525                         DRM_DEV_ERROR(dev->dev, "failed to construct crtc %d (%d)\n", i, ret);
 526                         goto fail;
 527                 }
 528                 priv->crtcs[priv->num_crtcs++] = crtc;
 529         }
 530
 531         /*
 532          * Now that we know the number of crtcs we've created, set the possible
 533          * crtcs for the encoders
 534          */
 535         for (i = 0; i < priv->num_encoders; i++) {
 536                 struct drm_encoder *encoder = priv->encoders[i];
 537
 538                 encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;
 539         }
 540
 541         return 0;
 542
 543 fail:
 544         return ret;
 545 }
 546
 547 static void read_mdp_hw_revision(struct mdp5_kms *mdp5_kms,
 548                                  u32 *major, u32 *minor)
 549 {
 550         struct device *dev = &mdp5_kms->pdev->dev;
 551         u32 version;
 552
 553         pm_runtime_get_sync(dev);
 554         version = mdp5_read(mdp5_kms, REG_MDP5_HW_VERSION);
 555         pm_runtime_put_sync(dev);
 556
 557         *major = FIELD(version, MDP5_HW_VERSION_MAJOR);
 558         *minor = FIELD(version, MDP5_HW_VERSION_MINOR);
 559
 560         DRM_DEV_INFO(dev, "MDP5 version v%d.%d", *major, *minor);
 561 }
 562
 563 static int get_clk(struct platform_device *pdev, struct clk **clkp,
 564                 const char *name, bool mandatory)
 565 {
 566         struct device *dev = &pdev->dev;
 567         struct clk *clk = msm_clk_get(pdev, name);
 568         if (IS_ERR(clk) && mandatory) {
 569                 DRM_DEV_ERROR(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk));
 570                 return PTR_ERR(clk);
 571         }
 572         if (IS_ERR(clk))
 573                 DBG("skipping %s", name);
 574         else
 575                 *clkp = clk;
 576
 577         return 0;
 578 }
 579
 580 struct msm_kms *mdp5_kms_init(struct drm_device *dev)
 581 {
 582         struct msm_drm_private *priv = dev->dev_private;
 583         struct platform_device *pdev;
 584         struct mdp5_kms *mdp5_kms;
 585         struct mdp5_cfg *config;
 586         struct msm_kms *kms;
 587         struct msm_gem_address_space *aspace;
 588         int irq, i, ret;
 589         struct device *iommu_dev;
 590
 591         /* priv->kms would have been populated by the MDP5 driver */
 592         kms = priv->kms;
 593         if (!kms)
 594                 return NULL;
 595
 596         mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
 597         pdev = mdp5_kms->pdev;
 598
 599         ret = mdp_kms_init(&mdp5_kms->base, &kms_funcs);
 600         if (ret) {
 601                 DRM_DEV_ERROR(&pdev->dev, "failed to init kms\n");
 602                 goto fail;
 603         }
 604
 605         irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
 606         if (irq < 0) {
 607                 ret = irq;
 608                 DRM_DEV_ERROR(&pdev->dev, "failed to get irq: %d\n", ret);
 609                 goto fail;
 610         }
 611
 612         kms->irq = irq;
 613
 614         config = mdp5_cfg_get_config(mdp5_kms->cfg);
 615
 616         /* make sure things are off before attaching iommu (bootloader could
 617          * have left things on, in which case we'll start getting faults if
 618          * we don't disable):
 619          */
 620         pm_runtime_get_sync(&pdev->dev);
 621         for (i = 0; i < MDP5_INTF_NUM_MAX; i++) {
 622                 if (mdp5_cfg_intf_is_virtual(config->hw->intf.connect[i]) ||
 623                     !config->hw->intf.base[i])
 624                         continue;
 625                 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0);
 626
 627                 mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(i), 0x3);
 628         }
 629         mdelay(16);
 630
 631         if (config->platform.iommu) {
 632                 struct msm_mmu *mmu;
 633
 634                 iommu_dev = &pdev->dev;
 635                 if (!dev_iommu_fwspec_get(iommu_dev))
 636                         iommu_dev = iommu_dev->parent;
 637
 638                 mmu = msm_iommu_new(iommu_dev, config->platform.iommu);
 639
 640                 aspace = msm_gem_address_space_create(mmu, "mdp5",
 641                         0x1000, 0x100000000 - 0x1000);
 642
 643                 if (IS_ERR(aspace)) {
 644                         if (!IS_ERR(mmu))
 645                                 mmu->funcs->destroy(mmu);
 646                         ret = PTR_ERR(aspace);
 647                         goto fail;
 648                 }
 649
 650                 kms->aspace = aspace;
 651         } else {
 652                 DRM_DEV_INFO(&pdev->dev,
 653                          "no iommu, fallback to phys contig buffers for scanout\n");
 654                 aspace = NULL;
 655         }
 656
 657         pm_runtime_put_sync(&pdev->dev);
 658
 659         ret = modeset_init(mdp5_kms);
 660         if (ret) {
 661                 DRM_DEV_ERROR(&pdev->dev, "modeset_init failed: %d\n", ret);
 662                 goto fail;
 663         }
 664
 665         dev->mode_config.min_width = 0;
 666         dev->mode_config.min_height = 0;
 667         dev->mode_config.max_width = 0xffff;
 668         dev->mode_config.max_height = 0xffff;
 669
 670         dev->max_vblank_count = 0; /* max_vblank_count is set on each CRTC */
 671         dev->vblank_disable_immediate = true;
 672
 673         return kms;
 674 fail:
 675         if (kms)
 676                 mdp5_kms_destroy(kms);
 677         return ERR_PTR(ret);
 678 }
 679
 680 static void mdp5_destroy(struct platform_device *pdev)
 681 {
 682         struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev);
 683         int i;
 684
 685         if (mdp5_kms->ctlm)
 686                 mdp5_ctlm_destroy(mdp5_kms->ctlm);
 687         if (mdp5_kms->smp)
 688                 mdp5_smp_destroy(mdp5_kms->smp);
 689         if (mdp5_kms->cfg)
 690                 mdp5_cfg_destroy(mdp5_kms->cfg);
 691
 692         for (i = 0; i < mdp5_kms->num_intfs; i++)
 693                 kfree(mdp5_kms->intfs[i]);
 694
 695         if (mdp5_kms->rpm_enabled)
 696                 pm_runtime_disable(&pdev->dev);
 697
 698         drm_atomic_private_obj_fini(&mdp5_kms->glob_state);
 699         drm_modeset_lock_fini(&mdp5_kms->glob_state_lock);
 700 }
 701
 702 static int construct_pipes(struct mdp5_kms *mdp5_kms, int cnt,
 703                 const enum mdp5_pipe *pipes, const uint32_t *offsets,
 704                 uint32_t caps)
 705 {
 706         struct drm_device *dev = mdp5_kms->dev;
 707         int i, ret;
 708
 709         for (i = 0; i < cnt; i++) {
 710                 struct mdp5_hw_pipe *hwpipe;
 711
 712                 hwpipe = mdp5_pipe_init(pipes[i], offsets[i], caps);
 713                 if (IS_ERR(hwpipe)) {
 714                         ret = PTR_ERR(hwpipe);
 715                         DRM_DEV_ERROR(dev->dev, "failed to construct pipe for %s (%d)\n",
 716                                         pipe2name(pipes[i]), ret);
 717                         return ret;
 718                 }
 719                 hwpipe->idx = mdp5_kms->num_hwpipes;
 720                 mdp5_kms->hwpipes[mdp5_kms->num_hwpipes++] = hwpipe;
 721         }
 722
 723         return 0;
 724 }
 725
 726 static int hwpipe_init(struct mdp5_kms *mdp5_kms)
 727 {
 728         static const enum mdp5_pipe rgb_planes[] = {
 729                         SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3,
 730         };
 731         static const enum mdp5_pipe vig_planes[] = {
 732                         SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3,
 733         };
 734         static const enum mdp5_pipe dma_planes[] = {
 735                         SSPP_DMA0, SSPP_DMA1,
 736         };
 737         static const enum mdp5_pipe cursor_planes[] = {
 738                         SSPP_CURSOR0, SSPP_CURSOR1,
 739         };
 740         const struct mdp5_cfg_hw *hw_cfg;
 741         int ret;
 742
 743         hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
 744
 745         /* Construct RGB pipes: */
 746         ret = construct_pipes(mdp5_kms, hw_cfg->pipe_rgb.count, rgb_planes,
 747                         hw_cfg->pipe_rgb.base, hw_cfg->pipe_rgb.caps);
 748         if (ret)
 749                 return ret;
 750
 751         /* Construct video (VIG) pipes: */
 752         ret = construct_pipes(mdp5_kms, hw_cfg->pipe_vig.count, vig_planes,
 753                         hw_cfg->pipe_vig.base, hw_cfg->pipe_vig.caps);
 754         if (ret)
 755                 return ret;
 756
 757         /* Construct DMA pipes: */
 758         ret = construct_pipes(mdp5_kms, hw_cfg->pipe_dma.count, dma_planes,
 759                         hw_cfg->pipe_dma.base, hw_cfg->pipe_dma.caps);
 760         if (ret)
 761                 return ret;
 762
 763         /* Construct cursor pipes: */
 764         ret = construct_pipes(mdp5_kms, hw_cfg->pipe_cursor.count,
 765                         cursor_planes, hw_cfg->pipe_cursor.base,
 766                         hw_cfg->pipe_cursor.caps);
 767         if (ret)
 768                 return ret;
 769
 770         return 0;
 771 }
 772
 773 static int hwmixer_init(struct mdp5_kms *mdp5_kms)
 774 {
 775         struct drm_device *dev = mdp5_kms->dev;
 776         const struct mdp5_cfg_hw *hw_cfg;
 777         int i, ret;
 778
 779         hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
 780
 781         for (i = 0; i < hw_cfg->lm.count; i++) {
 782                 struct mdp5_hw_mixer *mixer;
 783
 784                 mixer = mdp5_mixer_init(&hw_cfg->lm.instances[i]);
 785                 if (IS_ERR(mixer)) {
 786                         ret = PTR_ERR(mixer);
 787                         DRM_DEV_ERROR(dev->dev, "failed to construct LM%d (%d)\n",
 788                                 i, ret);
 789                         return ret;
 790                 }
 791
 792                 mixer->idx = mdp5_kms->num_hwmixers;
 793                 mdp5_kms->hwmixers[mdp5_kms->num_hwmixers++] = mixer;
 794         }
 795
 796         return 0;
 797 }
 798
 799 static int interface_init(struct mdp5_kms *mdp5_kms)
 800 {
 801         struct drm_device *dev = mdp5_kms->dev;
 802         const struct mdp5_cfg_hw *hw_cfg;
 803         const enum mdp5_intf_type *intf_types;
 804         int i;
 805
 806         hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
 807         intf_types = hw_cfg->intf.connect;
 808
 809         for (i = 0; i < ARRAY_SIZE(hw_cfg->intf.connect); i++) {
 810                 struct mdp5_interface *intf;
 811
 812                 if (intf_types[i] == INTF_DISABLED)
 813                         continue;
 814
 815                 intf = kzalloc(sizeof(*intf), GFP_KERNEL);
 816                 if (!intf) {
 817                         DRM_DEV_ERROR(dev->dev, "failed to construct INTF%d\n", i);
 818                         return -ENOMEM;
 819                 }
 820
 821                 intf->num = i;
 822                 intf->type = intf_types[i];
 823                 intf->mode = MDP5_INTF_MODE_NONE;
 824                 intf->idx = mdp5_kms->num_intfs;
 825                 mdp5_kms->intfs[mdp5_kms->num_intfs++] = intf;
 826         }
 827
 828         return 0;
 829 }
 830
 831 static int mdp5_init(struct platform_device *pdev, struct drm_device *dev)
 832 {
 833         struct msm_drm_private *priv = dev->dev_private;
 834         struct mdp5_kms *mdp5_kms;
 835         struct mdp5_cfg *config;
 836         u32 major, minor;
 837         int ret;
 838
 839         mdp5_kms = devm_kzalloc(&pdev->dev, sizeof(*mdp5_kms), GFP_KERNEL);
 840         if (!mdp5_kms) {
 841                 ret = -ENOMEM;
 842                 goto fail;
 843         }
 844
 845         platform_set_drvdata(pdev, mdp5_kms);
 846
 847         spin_lock_init(&mdp5_kms->resource_lock);
 848
 849         mdp5_kms->dev = dev;
 850         mdp5_kms->pdev = pdev;
 851
 852         ret = mdp5_global_obj_init(mdp5_kms);
 853         if (ret)
 854                 goto fail;
 855
 856         mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5");
 857         if (IS_ERR(mdp5_kms->mmio)) {
 858                 ret = PTR_ERR(mdp5_kms->mmio);
 859                 goto fail;
 860         }
 861
 862         /* mandatory clocks: */
 863         ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus", true);
 864         if (ret)
 865                 goto fail;
 866         ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface", true);
 867         if (ret)
 868                 goto fail;
 869         ret = get_clk(pdev, &mdp5_kms->core_clk, "core", true);
 870         if (ret)
 871                 goto fail;
 872         ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync", true);
 873         if (ret)
 874                 goto fail;
 875
 876         /* optional clocks: */
 877         get_clk(pdev, &mdp5_kms->lut_clk, "lut", false);
 878         get_clk(pdev, &mdp5_kms->tbu_clk, "tbu", false);
 879         get_clk(pdev, &mdp5_kms->tbu_rt_clk, "tbu_rt", false);
 880
 881         /* we need to set a default rate before enabling.  Set a safe
 882          * rate first, then figure out hw revision, and then set a
 883          * more optimal rate:
 884          */
 885         clk_set_rate(mdp5_kms->core_clk, 200000000);
 886
 887         pm_runtime_enable(&pdev->dev);
 888         mdp5_kms->rpm_enabled = true;
 889
 890         read_mdp_hw_revision(mdp5_kms, &major, &minor);
 891
 892         mdp5_kms->cfg = mdp5_cfg_init(mdp5_kms, major, minor);
 893         if (IS_ERR(mdp5_kms->cfg)) {
 894                 ret = PTR_ERR(mdp5_kms->cfg);
 895                 mdp5_kms->cfg = NULL;
 896                 goto fail;
 897         }
 898
 899         config = mdp5_cfg_get_config(mdp5_kms->cfg);
 900         mdp5_kms->caps = config->hw->mdp.caps;
 901
 902         /* TODO: compute core clock rate at runtime */
 903         clk_set_rate(mdp5_kms->core_clk, config->hw->max_clk);
 904
 905         /*
 906          * Some chipsets have a Shared Memory Pool (SMP), while others
 907          * have dedicated latency buffering per source pipe instead;
 908          * this section initializes the SMP:
 909          */
 910         if (mdp5_kms->caps & MDP_CAP_SMP) {
 911                 mdp5_kms->smp = mdp5_smp_init(mdp5_kms, &config->hw->smp);
 912                 if (IS_ERR(mdp5_kms->smp)) {
 913                         ret = PTR_ERR(mdp5_kms->smp);
 914                         mdp5_kms->smp = NULL;
 915                         goto fail;
 916                 }
 917         }
 918
 919         mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, mdp5_kms->cfg);
 920         if (IS_ERR(mdp5_kms->ctlm)) {
 921                 ret = PTR_ERR(mdp5_kms->ctlm);
 922                 mdp5_kms->ctlm = NULL;
 923                 goto fail;
 924         }
 925
 926         ret = hwpipe_init(mdp5_kms);
 927         if (ret)
 928                 goto fail;
 929
 930         ret = hwmixer_init(mdp5_kms);
 931         if (ret)
 932                 goto fail;
 933
 934         ret = interface_init(mdp5_kms);
 935         if (ret)
 936                 goto fail;
 937
 938         /* set uninit-ed kms */
 939         priv->kms = &mdp5_kms->base.base;
 940
 941         return 0;
 942 fail:
 943         if (mdp5_kms)
 944                 mdp5_destroy(pdev);
 945         return ret;
 946 }
 947
 948 static int mdp5_bind(struct device *dev, struct device *master, void *data)
 949 {
 950         struct drm_device *ddev = dev_get_drvdata(master);
 951         struct platform_device *pdev = to_platform_device(dev);
 952
 953         DBG("");
 954
 955         return mdp5_init(pdev, ddev);
 956 }
 957
 958 static void mdp5_unbind(struct device *dev, struct device *master,
 959                         void *data)
 960 {
 961         struct platform_device *pdev = to_platform_device(dev);
 962
 963         mdp5_destroy(pdev);
 964 }
 965
 966 static const struct component_ops mdp5_ops = {
 967         .bind   = mdp5_bind,
 968         .unbind = mdp5_unbind,
 969 };
 970
 971 static int mdp5_setup_interconnect(struct platform_device *pdev)
 972 {
 973         struct icc_path *path0 = of_icc_get(&pdev->dev, "mdp0-mem");
 974         struct icc_path *path1 = of_icc_get(&pdev->dev, "mdp1-mem");
 975         struct icc_path *path_rot = of_icc_get(&pdev->dev, "rotator-mem");
 976
 977         if (IS_ERR(path0))
 978                 return PTR_ERR(path0);
 979
 980         if (!path0) {
 981                 /* no interconnect support is not necessarily a fatal
 982                  * condition, the platform may simply not have an
 983                  * interconnect driver yet.  But warn about it in case
 984                  * bootloader didn't setup bus clocks high enough for
 985                  * scanout.
 986                  */
 987                 dev_warn(&pdev->dev, "No interconnect support may cause display underflows!\n");
 988                 return 0;
 989         }
 990
 991         icc_set_bw(path0, 0, MBps_to_icc(6400));
 992
 993         if (!IS_ERR_OR_NULL(path1))
 994                 icc_set_bw(path1, 0, MBps_to_icc(6400));
 995         if (!IS_ERR_OR_NULL(path_rot))
 996                 icc_set_bw(path_rot, 0, MBps_to_icc(6400));
 997
 998         return 0;
 999 }
1000
1001 static int mdp5_dev_probe(struct platform_device *pdev)
1002 {
1003         int ret;
1004
1005         DBG("");
1006
1007         ret = mdp5_setup_interconnect(pdev);
1008         if (ret)
1009                 return ret;
1010
1011         return component_add(&pdev->dev, &mdp5_ops);
1012 }
1013
1014 static int mdp5_dev_remove(struct platform_device *pdev)
1015 {
1016         DBG("");
1017         component_del(&pdev->dev, &mdp5_ops);
1018         return 0;
1019 }
1020
1021 static __maybe_unused int mdp5_runtime_suspend(struct device *dev)
1022 {
1023         struct platform_device *pdev = to_platform_device(dev);
1024         struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev);
1025
1026         DBG("");
1027
1028         return mdp5_disable(mdp5_kms);
1029 }
1030
1031 static __maybe_unused int mdp5_runtime_resume(struct device *dev)
1032 {
1033         struct platform_device *pdev = to_platform_device(dev);
1034         struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev);
1035
1036         DBG("");
1037
1038         return mdp5_enable(mdp5_kms);
1039 }
1040
1041 static const struct dev_pm_ops mdp5_pm_ops = {
1042         SET_RUNTIME_PM_OPS(mdp5_runtime_suspend, mdp5_runtime_resume, NULL)
1043 };
1044
1045 static const struct of_device_id mdp5_dt_match[] = {
1046         { .compatible = "qcom,mdp5", },
1047         /* to support downstream DT files */
1048         { .compatible = "qcom,mdss_mdp", },
1049         {}
1050 };
1051 MODULE_DEVICE_TABLE(of, mdp5_dt_match);
1052
1053 static struct platform_driver mdp5_driver = {
1054         .probe = mdp5_dev_probe,
1055         .remove = mdp5_dev_remove,
1056         .driver = {
1057                 .name = "msm_mdp",
1058                 .of_match_table = mdp5_dt_match,
1059                 .pm = &mdp5_pm_ops,
1060         },
1061 };
1062
1063 void __init msm_mdp_register(void)
1064 {
1065         DBG("");
1066         platform_driver_register(&mdp5_driver);
1067 }
1068
1069 void __exit msm_mdp_unregister(void)
1070 {
1071         DBG("");
1072         platform_driver_unregister(&mdp5_driver);
1073 }