drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
   4  * Copyright (C) 2013 Red Hat
   5  * Author: Rob Clark <robdclark@gmail.com>
   6  */
   7
   8 #define pr_fmt(fmt)     "[drm:%s:%d] " fmt, __func__, __LINE__
   9
  10 #include <linux/debugfs.h>
  11 #include <linux/dma-buf.h>
  12 #include <linux/of_irq.h>
  13 #include <linux/pm_opp.h>
  14
  15 #include <drm/drm_crtc.h>
  16 #include <drm/drm_file.h>
  17
  18 #include "msm_drv.h"
  19 #include "msm_mmu.h"
  20 #include "msm_gem.h"
  21
  22 #include "dpu_kms.h"
  23 #include "dpu_core_irq.h"
  24 #include "dpu_formats.h"
  25 #include "dpu_hw_vbif.h"
  26 #include "dpu_vbif.h"
  27 #include "dpu_encoder.h"
  28 #include "dpu_plane.h"
  29 #include "dpu_crtc.h"
  30
  31 #define CREATE_TRACE_POINTS
  32 #include "dpu_trace.h"
  33
  34 /*
  35  * To enable overall DRM driver logging
  36  * # echo 0x2 > /sys/module/drm/parameters/debug
  37  *
  38  * To enable DRM driver h/w logging
  39  * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask
  40  *
  41  * See dpu_hw_mdss.h for h/w logging mask definitions (search for DPU_DBG_MASK_)
  42  */
  43 #define DPU_DEBUGFS_DIR "msm_dpu"
  44 #define DPU_DEBUGFS_HWMASKNAME "hw_log_mask"
  45
  46 #define MIN_IB_BW       400000000ULL /* Min ib vote 400MB */
  47
  48 static int dpu_kms_hw_init(struct msm_kms *kms);
  49 static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms);
  50
  51 #ifdef CONFIG_DEBUG_FS
  52 static int _dpu_danger_signal_status(struct seq_file *s,
  53                 bool danger_status)
  54 {
  55         struct dpu_kms *kms = (struct dpu_kms *)s->private;
  56         struct dpu_danger_safe_status status;
  57         int i;
  58
  59         if (!kms->hw_mdp) {
  60                 DPU_ERROR("invalid arg(s)\n");
  61                 return 0;
  62         }
  63
  64         memset(&status, 0, sizeof(struct dpu_danger_safe_status));
  65
  66         pm_runtime_get_sync(&kms->pdev->dev);
  67         if (danger_status) {
  68                 seq_puts(s, "\nDanger signal status:\n");
  69                 if (kms->hw_mdp->ops.get_danger_status)
  70                         kms->hw_mdp->ops.get_danger_status(kms->hw_mdp,
  71                                         &status);
  72         } else {
  73                 seq_puts(s, "\nSafe signal status:\n");
  74                 if (kms->hw_mdp->ops.get_danger_status)
  75                         kms->hw_mdp->ops.get_danger_status(kms->hw_mdp,
  76                                         &status);
  77         }
  78         pm_runtime_put_sync(&kms->pdev->dev);
  79
  80         seq_printf(s, "MDP     :  0x%x\n", status.mdp);
  81
  82         for (i = SSPP_VIG0; i < SSPP_MAX; i++)
  83                 seq_printf(s, "SSPP%d   :  0x%x  \t", i - SSPP_VIG0,
  84                                 status.sspp[i]);
  85         seq_puts(s, "\n");
  86
  87         return 0;
  88 }
  89
  90 static int dpu_debugfs_danger_stats_show(struct seq_file *s, void *v)
  91 {
  92         return _dpu_danger_signal_status(s, true);
  93 }
  94 DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_danger_stats);
  95
  96 static int dpu_debugfs_safe_stats_show(struct seq_file *s, void *v)
  97 {
  98         return _dpu_danger_signal_status(s, false);
  99 }
 100 DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_safe_stats);
 101
 102 static void dpu_debugfs_danger_init(struct dpu_kms *dpu_kms,
 103                 struct dentry *parent)
 104 {
 105         struct dentry *entry = debugfs_create_dir("danger", parent);
 106
 107         debugfs_create_file("danger_status", 0600, entry,
 108                         dpu_kms, &dpu_debugfs_danger_stats_fops);
 109         debugfs_create_file("safe_status", 0600, entry,
 110                         dpu_kms, &dpu_debugfs_safe_stats_fops);
 111 }
 112
 113 static int _dpu_debugfs_show_regset32(struct seq_file *s, void *data)
 114 {
 115         struct dpu_debugfs_regset32 *regset = s->private;
 116         struct dpu_kms *dpu_kms = regset->dpu_kms;
 117         void __iomem *base;
 118         uint32_t i, addr;
 119
 120         if (!dpu_kms->mmio)
 121                 return 0;
 122
 123         base = dpu_kms->mmio + regset->offset;
 124
 125         /* insert padding spaces, if needed */
 126         if (regset->offset & 0xF) {
 127                 seq_printf(s, "[%x]", regset->offset & ~0xF);
 128                 for (i = 0; i < (regset->offset & 0xF); i += 4)
 129                         seq_puts(s, "         ");
 130         }
 131
 132         pm_runtime_get_sync(&dpu_kms->pdev->dev);
 133
 134         /* main register output */
 135         for (i = 0; i < regset->blk_len; i += 4) {
 136                 addr = regset->offset + i;
 137                 if ((addr & 0xF) == 0x0)
 138                         seq_printf(s, i ? "\n[%x]" : "[%x]", addr);
 139                 seq_printf(s, " %08x", readl_relaxed(base + i));
 140         }
 141         seq_puts(s, "\n");
 142         pm_runtime_put_sync(&dpu_kms->pdev->dev);
 143
 144         return 0;
 145 }
 146
 147 static int dpu_debugfs_open_regset32(struct inode *inode,
 148                 struct file *file)
 149 {
 150         return single_open(file, _dpu_debugfs_show_regset32, inode->i_private);
 151 }
 152
 153 static const struct file_operations dpu_fops_regset32 = {
 154         .open =         dpu_debugfs_open_regset32,
 155         .read =         seq_read,
 156         .llseek =       seq_lseek,
 157         .release =      single_release,
 158 };
 159
 160 void dpu_debugfs_setup_regset32(struct dpu_debugfs_regset32 *regset,
 161                 uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms)
 162 {
 163         if (regset) {
 164                 regset->offset = offset;
 165                 regset->blk_len = length;
 166                 regset->dpu_kms = dpu_kms;
 167         }
 168 }
 169
 170 void dpu_debugfs_create_regset32(const char *name, umode_t mode,
 171                 void *parent, struct dpu_debugfs_regset32 *regset)
 172 {
 173         if (!name || !regset || !regset->dpu_kms || !regset->blk_len)
 174                 return;
 175
 176         /* make sure offset is a multiple of 4 */
 177         regset->offset = round_down(regset->offset, 4);
 178
 179         debugfs_create_file(name, mode, parent, regset, &dpu_fops_regset32);
 180 }
 181
 182 static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor)
 183 {
 184         struct dpu_kms *dpu_kms = to_dpu_kms(kms);
 185         void *p = dpu_hw_util_get_log_mask_ptr();
 186         struct dentry *entry;
 187         struct drm_device *dev;
 188         struct msm_drm_private *priv;
 189
 190         if (!p)
 191                 return -EINVAL;
 192
 193         dev = dpu_kms->dev;
 194         priv = dev->dev_private;
 195
 196         entry = debugfs_create_dir("debug", minor->debugfs_root);
 197
 198         debugfs_create_x32(DPU_DEBUGFS_HWMASKNAME, 0600, entry, p);
 199
 200         dpu_debugfs_danger_init(dpu_kms, entry);
 201         dpu_debugfs_vbif_init(dpu_kms, entry);
 202         dpu_debugfs_core_irq_init(dpu_kms, entry);
 203
 204         if (priv->dp)
 205                 msm_dp_debugfs_init(priv->dp, minor);
 206
 207         return dpu_core_perf_debugfs_init(dpu_kms, entry);
 208 }
 209 #endif
 210
 211 /* Global/shared object state funcs */
 212
 213 /*
 214  * This is a helper that returns the private state currently in operation.
 215  * Note that this would return the "old_state" if called in the atomic check
 216  * path, and the "new_state" after the atomic swap has been done.
 217  */
 218 struct dpu_global_state *
 219 dpu_kms_get_existing_global_state(struct dpu_kms *dpu_kms)
 220 {
 221         return to_dpu_global_state(dpu_kms->global_state.state);
 222 }
 223
 224 /*
 225  * This acquires the modeset lock set aside for global state, creates
 226  * a new duplicated private object state.
 227  */
 228 struct dpu_global_state *dpu_kms_get_global_state(struct drm_atomic_state *s)
 229 {
 230         struct msm_drm_private *priv = s->dev->dev_private;
 231         struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
 232         struct drm_private_state *priv_state;
 233         int ret;
 234
 235         ret = drm_modeset_lock(&dpu_kms->global_state_lock, s->acquire_ctx);
 236         if (ret)
 237                 return ERR_PTR(ret);
 238
 239         priv_state = drm_atomic_get_private_obj_state(s,
 240                                                 &dpu_kms->global_state);
 241         if (IS_ERR(priv_state))
 242                 return ERR_CAST(priv_state);
 243
 244         return to_dpu_global_state(priv_state);
 245 }
 246
 247 static struct drm_private_state *
 248 dpu_kms_global_duplicate_state(struct drm_private_obj *obj)
 249 {
 250         struct dpu_global_state *state;
 251
 252         state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
 253         if (!state)
 254                 return NULL;
 255
 256         __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
 257
 258         return &state->base;
 259 }
 260
 261 static void dpu_kms_global_destroy_state(struct drm_private_obj *obj,
 262                                       struct drm_private_state *state)
 263 {
 264         struct dpu_global_state *dpu_state = to_dpu_global_state(state);
 265
 266         kfree(dpu_state);
 267 }
 268
 269 static const struct drm_private_state_funcs dpu_kms_global_state_funcs = {
 270         .atomic_duplicate_state = dpu_kms_global_duplicate_state,
 271         .atomic_destroy_state = dpu_kms_global_destroy_state,
 272 };
 273
 274 static int dpu_kms_global_obj_init(struct dpu_kms *dpu_kms)
 275 {
 276         struct dpu_global_state *state;
 277
 278         drm_modeset_lock_init(&dpu_kms->global_state_lock);
 279
 280         state = kzalloc(sizeof(*state), GFP_KERNEL);
 281         if (!state)
 282                 return -ENOMEM;
 283
 284         drm_atomic_private_obj_init(dpu_kms->dev, &dpu_kms->global_state,
 285                                     &state->base,
 286                                     &dpu_kms_global_state_funcs);
 287         return 0;
 288 }
 289
 290 static int dpu_kms_parse_data_bus_icc_path(struct dpu_kms *dpu_kms)
 291 {
 292         struct icc_path *path0;
 293         struct icc_path *path1;
 294         struct drm_device *dev = dpu_kms->dev;
 295
 296         path0 = of_icc_get(dev->dev, "mdp0-mem");
 297         path1 = of_icc_get(dev->dev, "mdp1-mem");
 298
 299         if (IS_ERR_OR_NULL(path0))
 300                 return PTR_ERR_OR_ZERO(path0);
 301
 302         dpu_kms->path[0] = path0;
 303         dpu_kms->num_paths = 1;
 304
 305         if (!IS_ERR_OR_NULL(path1)) {
 306                 dpu_kms->path[1] = path1;
 307                 dpu_kms->num_paths++;
 308         }
 309         return 0;
 310 }
 311
 312 static int dpu_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
 313 {
 314         return dpu_crtc_vblank(crtc, true);
 315 }
 316
 317 static void dpu_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
 318 {
 319         dpu_crtc_vblank(crtc, false);
 320 }
 321
 322 static void dpu_kms_enable_commit(struct msm_kms *kms)
 323 {
 324         struct dpu_kms *dpu_kms = to_dpu_kms(kms);
 325         pm_runtime_get_sync(&dpu_kms->pdev->dev);
 326 }
 327
 328 static void dpu_kms_disable_commit(struct msm_kms *kms)
 329 {
 330         struct dpu_kms *dpu_kms = to_dpu_kms(kms);
 331         pm_runtime_put_sync(&dpu_kms->pdev->dev);
 332 }
 333
 334 static ktime_t dpu_kms_vsync_time(struct msm_kms *kms, struct drm_crtc *crtc)
 335 {
 336         struct drm_encoder *encoder;
 337
 338         drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) {
 339                 ktime_t vsync_time;
 340
 341                 if (dpu_encoder_vsync_time(encoder, &vsync_time) == 0)
 342                         return vsync_time;
 343         }
 344
 345         return ktime_get();
 346 }
 347
 348 static void dpu_kms_prepare_commit(struct msm_kms *kms,
 349                 struct drm_atomic_state *state)
 350 {
 351         struct drm_crtc *crtc;
 352         struct drm_crtc_state *crtc_state;
 353         struct drm_encoder *encoder;
 354         int i;
 355
 356         if (!kms)
 357                 return;
 358
 359         /* Call prepare_commit for all affected encoders */
 360         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
 361                 drm_for_each_encoder_mask(encoder, crtc->dev,
 362                                           crtc_state->encoder_mask) {
 363                         dpu_encoder_prepare_commit(encoder);
 364                 }
 365         }
 366 }
 367
 368 static void dpu_kms_flush_commit(struct msm_kms *kms, unsigned crtc_mask)
 369 {
 370         struct dpu_kms *dpu_kms = to_dpu_kms(kms);
 371         struct drm_crtc *crtc;
 372
 373         for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) {
 374                 if (!crtc->state->active)
 375                         continue;
 376
 377                 trace_dpu_kms_commit(DRMID(crtc));
 378                 dpu_crtc_commit_kickoff(crtc);
 379         }
 380 }
 381
 382 /*
 383  * Override the encoder enable since we need to setup the inline rotator and do
 384  * some crtc magic before enabling any bridge that might be present.
 385  */
 386 void dpu_kms_encoder_enable(struct drm_encoder *encoder)
 387 {
 388         const struct drm_encoder_helper_funcs *funcs = encoder->helper_private;
 389         struct drm_device *dev = encoder->dev;
 390         struct drm_crtc *crtc;
 391
 392         /* Forward this enable call to the commit hook */
 393         if (funcs && funcs->commit)
 394                 funcs->commit(encoder);
 395
 396         drm_for_each_crtc(crtc, dev) {
 397                 if (!(crtc->state->encoder_mask & drm_encoder_mask(encoder)))
 398                         continue;
 399
 400                 trace_dpu_kms_enc_enable(DRMID(crtc));
 401         }
 402 }
 403
 404 static void dpu_kms_complete_commit(struct msm_kms *kms, unsigned crtc_mask)
 405 {
 406         struct dpu_kms *dpu_kms = to_dpu_kms(kms);
 407         struct drm_crtc *crtc;
 408
 409         DPU_ATRACE_BEGIN("kms_complete_commit");
 410
 411         for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask)
 412                 dpu_crtc_complete_commit(crtc);
 413
 414         DPU_ATRACE_END("kms_complete_commit");
 415 }
 416
 417 static void dpu_kms_wait_for_commit_done(struct msm_kms *kms,
 418                 struct drm_crtc *crtc)
 419 {
 420         struct drm_encoder *encoder;
 421         struct drm_device *dev;
 422         int ret;
 423
 424         if (!kms || !crtc || !crtc->state) {
 425                 DPU_ERROR("invalid params\n");
 426                 return;
 427         }
 428
 429         dev = crtc->dev;
 430
 431         if (!crtc->state->enable) {
 432                 DPU_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
 433                 return;
 434         }
 435
 436         if (!crtc->state->active) {
 437                 DPU_DEBUG("[crtc:%d] not active\n", crtc->base.id);
 438                 return;
 439         }
 440
 441         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 442                 if (encoder->crtc != crtc)
 443                         continue;
 444                 /*
 445                  * Wait for post-flush if necessary to delay before
 446                  * plane_cleanup. For example, wait for vsync in case of video
 447                  * mode panels. This may be a no-op for command mode panels.
 448                  */
 449                 trace_dpu_kms_wait_for_commit_done(DRMID(crtc));
 450                 ret = dpu_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE);
 451                 if (ret && ret != -EWOULDBLOCK) {
 452                         DPU_ERROR("wait for commit done returned %d\n", ret);
 453                         break;
 454                 }
 455         }
 456 }
 457
 458 static void dpu_kms_wait_flush(struct msm_kms *kms, unsigned crtc_mask)
 459 {
 460         struct dpu_kms *dpu_kms = to_dpu_kms(kms);
 461         struct drm_crtc *crtc;
 462
 463         for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask)
 464                 dpu_kms_wait_for_commit_done(kms, crtc);
 465 }
 466
 467 static int _dpu_kms_initialize_dsi(struct drm_device *dev,
 468                                     struct msm_drm_private *priv,
 469                                     struct dpu_kms *dpu_kms)
 470 {
 471         struct drm_encoder *encoder = NULL;
 472         int i, rc = 0;
 473
 474         if (!(priv->dsi[0] || priv->dsi[1]))
 475                 return rc;
 476
 477         /*TODO: Support two independent DSI connectors */
 478         encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DSI);
 479         if (IS_ERR(encoder)) {
 480                 DPU_ERROR("encoder init failed for dsi display\n");
 481                 return PTR_ERR(encoder);
 482         }
 483
 484         priv->encoders[priv->num_encoders++] = encoder;
 485
 486         for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) {
 487                 if (!priv->dsi[i])
 488                         continue;
 489
 490                 rc = msm_dsi_modeset_init(priv->dsi[i], dev, encoder);
 491                 if (rc) {
 492                         DPU_ERROR("modeset_init failed for dsi[%d], rc = %d\n",
 493                                 i, rc);
 494                         break;
 495                 }
 496         }
 497
 498         return rc;
 499 }
 500
 501 static int _dpu_kms_initialize_displayport(struct drm_device *dev,
 502                                             struct msm_drm_private *priv,
 503                                             struct dpu_kms *dpu_kms)
 504 {
 505         struct drm_encoder *encoder = NULL;
 506         int rc = 0;
 507
 508         if (!priv->dp)
 509                 return rc;
 510
 511         encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_TMDS);
 512         if (IS_ERR(encoder)) {
 513                 DPU_ERROR("encoder init failed for dsi display\n");
 514                 return PTR_ERR(encoder);
 515         }
 516
 517         rc = msm_dp_modeset_init(priv->dp, dev, encoder);
 518         if (rc) {
 519                 DPU_ERROR("modeset_init failed for DP, rc = %d\n", rc);
 520                 drm_encoder_cleanup(encoder);
 521                 return rc;
 522         }
 523
 524         priv->encoders[priv->num_encoders++] = encoder;
 525         return rc;
 526 }
 527
 528 /**
 529  * _dpu_kms_setup_displays - create encoders, bridges and connectors
 530  *                           for underlying displays
 531  * @dev:        Pointer to drm device structure
 532  * @priv:       Pointer to private drm device data
 533  * @dpu_kms:    Pointer to dpu kms structure
 534  * Returns:     Zero on success
 535  */
 536 static int _dpu_kms_setup_displays(struct drm_device *dev,
 537                                     struct msm_drm_private *priv,
 538                                     struct dpu_kms *dpu_kms)
 539 {
 540         int rc = 0;
 541
 542         rc = _dpu_kms_initialize_dsi(dev, priv, dpu_kms);
 543         if (rc) {
 544                 DPU_ERROR("initialize_dsi failed, rc = %d\n", rc);
 545                 return rc;
 546         }
 547
 548         rc = _dpu_kms_initialize_displayport(dev, priv, dpu_kms);
 549         if (rc) {
 550                 DPU_ERROR("initialize_DP failed, rc = %d\n", rc);
 551                 return rc;
 552         }
 553
 554         return rc;
 555 }
 556
 557 static void _dpu_kms_drm_obj_destroy(struct dpu_kms *dpu_kms)
 558 {
 559         struct msm_drm_private *priv;
 560         int i;
 561
 562         priv = dpu_kms->dev->dev_private;
 563
 564         for (i = 0; i < priv->num_crtcs; i++)
 565                 priv->crtcs[i]->funcs->destroy(priv->crtcs[i]);
 566         priv->num_crtcs = 0;
 567
 568         for (i = 0; i < priv->num_planes; i++)
 569                 priv->planes[i]->funcs->destroy(priv->planes[i]);
 570         priv->num_planes = 0;
 571
 572         for (i = 0; i < priv->num_connectors; i++)
 573                 priv->connectors[i]->funcs->destroy(priv->connectors[i]);
 574         priv->num_connectors = 0;
 575
 576         for (i = 0; i < priv->num_encoders; i++)
 577                 priv->encoders[i]->funcs->destroy(priv->encoders[i]);
 578         priv->num_encoders = 0;
 579 }
 580
 581 static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)
 582 {
 583         struct drm_device *dev;
 584         struct drm_plane *primary_planes[MAX_PLANES], *plane;
 585         struct drm_plane *cursor_planes[MAX_PLANES] = { NULL };
 586         struct drm_crtc *crtc;
 587
 588         struct msm_drm_private *priv;
 589         struct dpu_mdss_cfg *catalog;
 590
 591         int primary_planes_idx = 0, cursor_planes_idx = 0, i, ret;
 592         int max_crtc_count;
 593         dev = dpu_kms->dev;
 594         priv = dev->dev_private;
 595         catalog = dpu_kms->catalog;
 596
 597         /*
 598          * Create encoder and query display drivers to create
 599          * bridges and connectors
 600          */
 601         ret = _dpu_kms_setup_displays(dev, priv, dpu_kms);
 602         if (ret)
 603                 goto fail;
 604
 605         max_crtc_count = min(catalog->mixer_count, priv->num_encoders);
 606
 607         /* Create the planes, keeping track of one primary/cursor per crtc */
 608         for (i = 0; i < catalog->sspp_count; i++) {
 609                 enum drm_plane_type type;
 610
 611                 if ((catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR))
 612                         && cursor_planes_idx < max_crtc_count)
 613                         type = DRM_PLANE_TYPE_CURSOR;
 614                 else if (primary_planes_idx < max_crtc_count)
 615                         type = DRM_PLANE_TYPE_PRIMARY;
 616                 else
 617                         type = DRM_PLANE_TYPE_OVERLAY;
 618
 619                 DPU_DEBUG("Create plane type %d with features %lx (cur %lx)\n",
 620                           type, catalog->sspp[i].features,
 621                           catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR));
 622
 623                 plane = dpu_plane_init(dev, catalog->sspp[i].id, type,
 624                                        (1UL << max_crtc_count) - 1, 0);
 625                 if (IS_ERR(plane)) {
 626                         DPU_ERROR("dpu_plane_init failed\n");
 627                         ret = PTR_ERR(plane);
 628                         goto fail;
 629                 }
 630                 priv->planes[priv->num_planes++] = plane;
 631
 632                 if (type == DRM_PLANE_TYPE_CURSOR)
 633                         cursor_planes[cursor_planes_idx++] = plane;
 634                 else if (type == DRM_PLANE_TYPE_PRIMARY)
 635                         primary_planes[primary_planes_idx++] = plane;
 636         }
 637
 638         max_crtc_count = min(max_crtc_count, primary_planes_idx);
 639
 640         /* Create one CRTC per encoder */
 641         for (i = 0; i < max_crtc_count; i++) {
 642                 crtc = dpu_crtc_init(dev, primary_planes[i], cursor_planes[i]);
 643                 if (IS_ERR(crtc)) {
 644                         ret = PTR_ERR(crtc);
 645                         goto fail;
 646                 }
 647                 priv->crtcs[priv->num_crtcs++] = crtc;
 648         }
 649
 650         /* All CRTCs are compatible with all encoders */
 651         for (i = 0; i < priv->num_encoders; i++)
 652                 priv->encoders[i]->possible_crtcs = (1 << priv->num_crtcs) - 1;
 653
 654         return 0;
 655 fail:
 656         _dpu_kms_drm_obj_destroy(dpu_kms);
 657         return ret;
 658 }
 659
 660 static long dpu_kms_round_pixclk(struct msm_kms *kms, unsigned long rate,
 661                 struct drm_encoder *encoder)
 662 {
 663         return rate;
 664 }
 665
 666 static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms)
 667 {
 668         int i;
 669
 670         if (dpu_kms->hw_intr)
 671                 dpu_hw_intr_destroy(dpu_kms->hw_intr);
 672         dpu_kms->hw_intr = NULL;
 673
 674         /* safe to call these more than once during shutdown */
 675         _dpu_kms_mmu_destroy(dpu_kms);
 676
 677         if (dpu_kms->catalog) {
 678                 for (i = 0; i < dpu_kms->catalog->vbif_count; i++) {
 679                         u32 vbif_idx = dpu_kms->catalog->vbif[i].id;
 680
 681                         if ((vbif_idx < VBIF_MAX) && dpu_kms->hw_vbif[vbif_idx])
 682                                 dpu_hw_vbif_destroy(dpu_kms->hw_vbif[vbif_idx]);
 683                 }
 684         }
 685
 686         if (dpu_kms->rm_init)
 687                 dpu_rm_destroy(&dpu_kms->rm);
 688         dpu_kms->rm_init = false;
 689
 690         if (dpu_kms->catalog)
 691                 dpu_hw_catalog_deinit(dpu_kms->catalog);
 692         dpu_kms->catalog = NULL;
 693
 694         if (dpu_kms->vbif[VBIF_NRT])
 695                 devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->vbif[VBIF_NRT]);
 696         dpu_kms->vbif[VBIF_NRT] = NULL;
 697
 698         if (dpu_kms->vbif[VBIF_RT])
 699                 devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->vbif[VBIF_RT]);
 700         dpu_kms->vbif[VBIF_RT] = NULL;
 701
 702         if (dpu_kms->hw_mdp)
 703                 dpu_hw_mdp_destroy(dpu_kms->hw_mdp);
 704         dpu_kms->hw_mdp = NULL;
 705
 706         if (dpu_kms->mmio)
 707                 devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->mmio);
 708         dpu_kms->mmio = NULL;
 709 }
 710
 711 static void dpu_kms_destroy(struct msm_kms *kms)
 712 {
 713         struct dpu_kms *dpu_kms;
 714
 715         if (!kms) {
 716                 DPU_ERROR("invalid kms\n");
 717                 return;
 718         }
 719
 720         dpu_kms = to_dpu_kms(kms);
 721
 722         _dpu_kms_hw_destroy(dpu_kms);
 723
 724         msm_kms_destroy(&dpu_kms->base);
 725 }
 726
 727 static void _dpu_kms_set_encoder_mode(struct msm_kms *kms,
 728                                  struct drm_encoder *encoder,
 729                                  bool cmd_mode)
 730 {
 731         struct msm_display_info info;
 732         struct msm_drm_private *priv = encoder->dev->dev_private;
 733         int i, rc = 0;
 734
 735         memset(&info, 0, sizeof(info));
 736
 737         info.intf_type = encoder->encoder_type;
 738         info.capabilities = cmd_mode ? MSM_DISPLAY_CAP_CMD_MODE :
 739                         MSM_DISPLAY_CAP_VID_MODE;
 740
 741         switch (info.intf_type) {
 742         case DRM_MODE_ENCODER_DSI:
 743                 /* TODO: No support for DSI swap */
 744                 for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) {
 745                         if (priv->dsi[i]) {
 746                                 info.h_tile_instance[info.num_of_h_tiles] = i;
 747                                 info.num_of_h_tiles++;
 748                         }
 749                 }
 750                 break;
 751         case DRM_MODE_ENCODER_TMDS:
 752                 info.num_of_h_tiles = 1;
 753                 break;
 754         }
 755
 756         rc = dpu_encoder_setup(encoder->dev, encoder, &info);
 757         if (rc)
 758                 DPU_ERROR("failed to setup DPU encoder %d: rc:%d\n",
 759                         encoder->base.id, rc);
 760 }
 761
 762 static irqreturn_t dpu_irq(struct msm_kms *kms)
 763 {
 764         struct dpu_kms *dpu_kms = to_dpu_kms(kms);
 765
 766         return dpu_core_irq(dpu_kms);
 767 }
 768
 769 static void dpu_irq_preinstall(struct msm_kms *kms)
 770 {
 771         struct dpu_kms *dpu_kms = to_dpu_kms(kms);
 772
 773         dpu_core_irq_preinstall(dpu_kms);
 774 }
 775
 776 static int dpu_irq_postinstall(struct msm_kms *kms)
 777 {
 778         struct msm_drm_private *priv;
 779         struct dpu_kms *dpu_kms = to_dpu_kms(kms);
 780
 781         if (!dpu_kms || !dpu_kms->dev)
 782                 return -EINVAL;
 783
 784         priv = dpu_kms->dev->dev_private;
 785         if (!priv)
 786                 return -EINVAL;
 787
 788         msm_dp_irq_postinstall(priv->dp);
 789
 790         return 0;
 791 }
 792
 793 static void dpu_irq_uninstall(struct msm_kms *kms)
 794 {
 795         struct dpu_kms *dpu_kms = to_dpu_kms(kms);
 796
 797         dpu_core_irq_uninstall(dpu_kms);
 798 }
 799
 800 static const struct msm_kms_funcs kms_funcs = {
 801         .hw_init         = dpu_kms_hw_init,
 802         .irq_preinstall  = dpu_irq_preinstall,
 803         .irq_postinstall = dpu_irq_postinstall,
 804         .irq_uninstall   = dpu_irq_uninstall,
 805         .irq             = dpu_irq,
 806         .enable_commit   = dpu_kms_enable_commit,
 807         .disable_commit  = dpu_kms_disable_commit,
 808         .vsync_time      = dpu_kms_vsync_time,
 809         .prepare_commit  = dpu_kms_prepare_commit,
 810         .flush_commit    = dpu_kms_flush_commit,
 811         .wait_flush      = dpu_kms_wait_flush,
 812         .complete_commit = dpu_kms_complete_commit,
 813         .enable_vblank   = dpu_kms_enable_vblank,
 814         .disable_vblank  = dpu_kms_disable_vblank,
 815         .check_modified_format = dpu_format_check_modified_format,
 816         .get_format      = dpu_get_msm_format,
 817         .round_pixclk    = dpu_kms_round_pixclk,
 818         .destroy         = dpu_kms_destroy,
 819         .set_encoder_mode = _dpu_kms_set_encoder_mode,
 820 #ifdef CONFIG_DEBUG_FS
 821         .debugfs_init    = dpu_kms_debugfs_init,
 822 #endif
 823 };
 824
 825 static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms)
 826 {
 827         struct msm_mmu *mmu;
 828
 829         if (!dpu_kms->base.aspace)
 830                 return;
 831
 832         mmu = dpu_kms->base.aspace->mmu;
 833
 834         mmu->funcs->detach(mmu);
 835         msm_gem_address_space_put(dpu_kms->base.aspace);
 836
 837         dpu_kms->base.aspace = NULL;
 838 }
 839
 840 static int _dpu_kms_mmu_init(struct dpu_kms *dpu_kms)
 841 {
 842         struct iommu_domain *domain;
 843         struct msm_gem_address_space *aspace;
 844         struct msm_mmu *mmu;
 845
 846         domain = iommu_domain_alloc(&platform_bus_type);
 847         if (!domain)
 848                 return 0;
 849
 850         mmu = msm_iommu_new(dpu_kms->dev->dev, domain);
 851         aspace = msm_gem_address_space_create(mmu, "dpu1",
 852                 0x1000, 0x100000000 - 0x1000);
 853
 854         if (IS_ERR(aspace)) {
 855                 mmu->funcs->destroy(mmu);
 856                 return PTR_ERR(aspace);
 857         }
 858
 859         dpu_kms->base.aspace = aspace;
 860         return 0;
 861 }
 862
 863 static struct dss_clk *_dpu_kms_get_clk(struct dpu_kms *dpu_kms,
 864                 char *clock_name)
 865 {
 866         struct dss_module_power *mp = &dpu_kms->mp;
 867         int i;
 868
 869         for (i = 0; i < mp->num_clk; i++) {
 870                 if (!strcmp(mp->clk_config[i].clk_name, clock_name))
 871                         return &mp->clk_config[i];
 872         }
 873
 874         return NULL;
 875 }
 876
 877 u64 dpu_kms_get_clk_rate(struct dpu_kms *dpu_kms, char *clock_name)
 878 {
 879         struct dss_clk *clk;
 880
 881         clk = _dpu_kms_get_clk(dpu_kms, clock_name);
 882         if (!clk)
 883                 return -EINVAL;
 884
 885         return clk_get_rate(clk->clk);
 886 }
 887
 888 static int dpu_kms_hw_init(struct msm_kms *kms)
 889 {
 890         struct dpu_kms *dpu_kms;
 891         struct drm_device *dev;
 892         int i, rc = -EINVAL;
 893
 894         if (!kms) {
 895                 DPU_ERROR("invalid kms\n");
 896                 return rc;
 897         }
 898
 899         dpu_kms = to_dpu_kms(kms);
 900         dev = dpu_kms->dev;
 901
 902         rc = dpu_kms_global_obj_init(dpu_kms);
 903         if (rc)
 904                 return rc;
 905
 906         atomic_set(&dpu_kms->bandwidth_ref, 0);
 907
 908         dpu_kms->mmio = msm_ioremap(dpu_kms->pdev, "mdp", "mdp");
 909         if (IS_ERR(dpu_kms->mmio)) {
 910                 rc = PTR_ERR(dpu_kms->mmio);
 911                 DPU_ERROR("mdp register memory map failed: %d\n", rc);
 912                 dpu_kms->mmio = NULL;
 913                 goto error;
 914         }
 915         DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio);
 916
 917         dpu_kms->vbif[VBIF_RT] = msm_ioremap(dpu_kms->pdev, "vbif", "vbif");
 918         if (IS_ERR(dpu_kms->vbif[VBIF_RT])) {
 919                 rc = PTR_ERR(dpu_kms->vbif[VBIF_RT]);
 920                 DPU_ERROR("vbif register memory map failed: %d\n", rc);
 921                 dpu_kms->vbif[VBIF_RT] = NULL;
 922                 goto error;
 923         }
 924         dpu_kms->vbif[VBIF_NRT] = msm_ioremap_quiet(dpu_kms->pdev, "vbif_nrt", "vbif_nrt");
 925         if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) {
 926                 dpu_kms->vbif[VBIF_NRT] = NULL;
 927                 DPU_DEBUG("VBIF NRT is not defined");
 928         }
 929
 930         dpu_kms->reg_dma = msm_ioremap_quiet(dpu_kms->pdev, "regdma", "regdma");
 931         if (IS_ERR(dpu_kms->reg_dma)) {
 932                 dpu_kms->reg_dma = NULL;
 933                 DPU_DEBUG("REG_DMA is not defined");
 934         }
 935
 936         if (of_device_is_compatible(dev->dev->of_node, "qcom,sc7180-mdss"))
 937                 dpu_kms_parse_data_bus_icc_path(dpu_kms);
 938
 939         pm_runtime_get_sync(&dpu_kms->pdev->dev);
 940
 941         dpu_kms->core_rev = readl_relaxed(dpu_kms->mmio + 0x0);
 942
 943         pr_info("dpu hardware revision:0x%x\n", dpu_kms->core_rev);
 944
 945         dpu_kms->catalog = dpu_hw_catalog_init(dpu_kms->core_rev);
 946         if (IS_ERR_OR_NULL(dpu_kms->catalog)) {
 947                 rc = PTR_ERR(dpu_kms->catalog);
 948                 if (!dpu_kms->catalog)
 949                         rc = -EINVAL;
 950                 DPU_ERROR("catalog init failed: %d\n", rc);
 951                 dpu_kms->catalog = NULL;
 952                 goto power_error;
 953         }
 954
 955         /*
 956          * Now we need to read the HW catalog and initialize resources such as
 957          * clocks, regulators, GDSC/MMAGIC, ioremap the register ranges etc
 958          */
 959         rc = _dpu_kms_mmu_init(dpu_kms);
 960         if (rc) {
 961                 DPU_ERROR("dpu_kms_mmu_init failed: %d\n", rc);
 962                 goto power_error;
 963         }
 964
 965         rc = dpu_rm_init(&dpu_kms->rm, dpu_kms->catalog, dpu_kms->mmio);
 966         if (rc) {
 967                 DPU_ERROR("rm init failed: %d\n", rc);
 968                 goto power_error;
 969         }
 970
 971         dpu_kms->rm_init = true;
 972
 973         dpu_kms->hw_mdp = dpu_hw_mdptop_init(MDP_TOP, dpu_kms->mmio,
 974                                              dpu_kms->catalog);
 975         if (IS_ERR(dpu_kms->hw_mdp)) {
 976                 rc = PTR_ERR(dpu_kms->hw_mdp);
 977                 DPU_ERROR("failed to get hw_mdp: %d\n", rc);
 978                 dpu_kms->hw_mdp = NULL;
 979                 goto power_error;
 980         }
 981
 982         for (i = 0; i < dpu_kms->catalog->vbif_count; i++) {
 983                 u32 vbif_idx = dpu_kms->catalog->vbif[i].id;
 984
 985                 dpu_kms->hw_vbif[i] = dpu_hw_vbif_init(vbif_idx,
 986                                 dpu_kms->vbif[vbif_idx], dpu_kms->catalog);
 987                 if (IS_ERR_OR_NULL(dpu_kms->hw_vbif[vbif_idx])) {
 988                         rc = PTR_ERR(dpu_kms->hw_vbif[vbif_idx]);
 989                         if (!dpu_kms->hw_vbif[vbif_idx])
 990                                 rc = -EINVAL;
 991                         DPU_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc);
 992                         dpu_kms->hw_vbif[vbif_idx] = NULL;
 993                         goto power_error;
 994                 }
 995         }
 996
 997         rc = dpu_core_perf_init(&dpu_kms->perf, dev, dpu_kms->catalog,
 998                         _dpu_kms_get_clk(dpu_kms, "core"));
 999         if (rc) {
1000                 DPU_ERROR("failed to init perf %d\n", rc);
1001                 goto perf_err;
1002         }
1003
1004         dpu_kms->hw_intr = dpu_hw_intr_init(dpu_kms->mmio, dpu_kms->catalog);
1005         if (IS_ERR_OR_NULL(dpu_kms->hw_intr)) {
1006                 rc = PTR_ERR(dpu_kms->hw_intr);
1007                 DPU_ERROR("hw_intr init failed: %d\n", rc);
1008                 dpu_kms->hw_intr = NULL;
1009                 goto hw_intr_init_err;
1010         }
1011
1012         dev->mode_config.min_width = 0;
1013         dev->mode_config.min_height = 0;
1014
1015         /*
1016          * max crtc width is equal to the max mixer width * 2 and max height is
1017          * is 4K
1018          */
1019         dev->mode_config.max_width =
1020                         dpu_kms->catalog->caps->max_mixer_width * 2;
1021         dev->mode_config.max_height = 4096;
1022
1023         /*
1024          * Support format modifiers for compression etc.
1025          */
1026         dev->mode_config.allow_fb_modifiers = true;
1027
1028         /*
1029          * _dpu_kms_drm_obj_init should create the DRM related objects
1030          * i.e. CRTCs, planes, encoders, connectors and so forth
1031          */
1032         rc = _dpu_kms_drm_obj_init(dpu_kms);
1033         if (rc) {
1034                 DPU_ERROR("modeset init failed: %d\n", rc);
1035                 goto drm_obj_init_err;
1036         }
1037
1038         dpu_vbif_init_memtypes(dpu_kms);
1039
1040         pm_runtime_put_sync(&dpu_kms->pdev->dev);
1041
1042         return 0;
1043
1044 drm_obj_init_err:
1045         dpu_core_perf_destroy(&dpu_kms->perf);
1046 hw_intr_init_err:
1047 perf_err:
1048 power_error:
1049         pm_runtime_put_sync(&dpu_kms->pdev->dev);
1050 error:
1051         _dpu_kms_hw_destroy(dpu_kms);
1052
1053         return rc;
1054 }
1055
1056 struct msm_kms *dpu_kms_init(struct drm_device *dev)
1057 {
1058         struct msm_drm_private *priv;
1059         struct dpu_kms *dpu_kms;
1060         int irq;
1061
1062         if (!dev) {
1063                 DPU_ERROR("drm device node invalid\n");
1064                 return ERR_PTR(-EINVAL);
1065         }
1066
1067         priv = dev->dev_private;
1068         dpu_kms = to_dpu_kms(priv->kms);
1069
1070         irq = irq_of_parse_and_map(dpu_kms->pdev->dev.of_node, 0);
1071         if (irq < 0) {
1072                 DPU_ERROR("failed to get irq: %d\n", irq);
1073                 return ERR_PTR(irq);
1074         }
1075         dpu_kms->base.irq = irq;
1076
1077         return &dpu_kms->base;
1078 }
1079
1080 static int dpu_bind(struct device *dev, struct device *master, void *data)
1081 {
1082         struct drm_device *ddev = dev_get_drvdata(master);
1083         struct platform_device *pdev = to_platform_device(dev);
1084         struct msm_drm_private *priv = ddev->dev_private;
1085         struct dpu_kms *dpu_kms;
1086         struct dss_module_power *mp;
1087         int ret = 0;
1088
1089         dpu_kms = devm_kzalloc(&pdev->dev, sizeof(*dpu_kms), GFP_KERNEL);
1090         if (!dpu_kms)
1091                 return -ENOMEM;
1092
1093         dpu_kms->opp_table = dev_pm_opp_set_clkname(dev, "core");
1094         if (IS_ERR(dpu_kms->opp_table))
1095                 return PTR_ERR(dpu_kms->opp_table);
1096         /* OPP table is optional */
1097         ret = dev_pm_opp_of_add_table(dev);
1098         if (ret && ret != -ENODEV) {
1099                 dev_err(dev, "invalid OPP table in device tree\n");
1100                 goto put_clkname;
1101         }
1102
1103         mp = &dpu_kms->mp;
1104         ret = msm_dss_parse_clock(pdev, mp);
1105         if (ret) {
1106                 DPU_ERROR("failed to parse clocks, ret=%d\n", ret);
1107                 goto err;
1108         }
1109
1110         platform_set_drvdata(pdev, dpu_kms);
1111
1112         ret = msm_kms_init(&dpu_kms->base, &kms_funcs);
1113         if (ret) {
1114                 DPU_ERROR("failed to init kms, ret=%d\n", ret);
1115                 goto err;
1116         }
1117         dpu_kms->dev = ddev;
1118         dpu_kms->pdev = pdev;
1119
1120         pm_runtime_enable(&pdev->dev);
1121         dpu_kms->rpm_enabled = true;
1122
1123         priv->kms = &dpu_kms->base;
1124         return ret;
1125 err:
1126         dev_pm_opp_of_remove_table(dev);
1127 put_clkname:
1128         dev_pm_opp_put_clkname(dpu_kms->opp_table);
1129         return ret;
1130 }
1131
1132 static void dpu_unbind(struct device *dev, struct device *master, void *data)
1133 {
1134         struct platform_device *pdev = to_platform_device(dev);
1135         struct dpu_kms *dpu_kms = platform_get_drvdata(pdev);
1136         struct dss_module_power *mp = &dpu_kms->mp;
1137
1138         msm_dss_put_clk(mp->clk_config, mp->num_clk);
1139         devm_kfree(&pdev->dev, mp->clk_config);
1140         mp->num_clk = 0;
1141
1142         if (dpu_kms->rpm_enabled)
1143                 pm_runtime_disable(&pdev->dev);
1144
1145         dev_pm_opp_of_remove_table(dev);
1146         dev_pm_opp_put_clkname(dpu_kms->opp_table);
1147 }
1148
1149 static const struct component_ops dpu_ops = {
1150         .bind   = dpu_bind,
1151         .unbind = dpu_unbind,
1152 };
1153
1154 static int dpu_dev_probe(struct platform_device *pdev)
1155 {
1156         return component_add(&pdev->dev, &dpu_ops);
1157 }
1158
1159 static int dpu_dev_remove(struct platform_device *pdev)
1160 {
1161         component_del(&pdev->dev, &dpu_ops);
1162         return 0;
1163 }
1164
1165 static int __maybe_unused dpu_runtime_suspend(struct device *dev)
1166 {
1167         int i, rc = -1;
1168         struct platform_device *pdev = to_platform_device(dev);
1169         struct dpu_kms *dpu_kms = platform_get_drvdata(pdev);
1170         struct dss_module_power *mp = &dpu_kms->mp;
1171
1172         /* Drop the performance state vote */
1173         dev_pm_opp_set_rate(dev, 0);
1174         rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false);
1175         if (rc)
1176                 DPU_ERROR("clock disable failed rc:%d\n", rc);
1177
1178         for (i = 0; i < dpu_kms->num_paths; i++)
1179                 icc_set_bw(dpu_kms->path[i], 0, 0);
1180
1181         return rc;
1182 }
1183
1184 static int __maybe_unused dpu_runtime_resume(struct device *dev)
1185 {
1186         int rc = -1;
1187         struct platform_device *pdev = to_platform_device(dev);
1188         struct dpu_kms *dpu_kms = platform_get_drvdata(pdev);
1189         struct drm_encoder *encoder;
1190         struct drm_device *ddev;
1191         struct dss_module_power *mp = &dpu_kms->mp;
1192         int i;
1193
1194         ddev = dpu_kms->dev;
1195
1196         WARN_ON(!(dpu_kms->num_paths));
1197         /* Min vote of BW is required before turning on AXI clk */
1198         for (i = 0; i < dpu_kms->num_paths; i++)
1199                 icc_set_bw(dpu_kms->path[i], 0, Bps_to_icc(MIN_IB_BW));
1200
1201         rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true);
1202         if (rc) {
1203                 DPU_ERROR("clock enable failed rc:%d\n", rc);
1204                 return rc;
1205         }
1206
1207         dpu_vbif_init_memtypes(dpu_kms);
1208
1209         drm_for_each_encoder(encoder, ddev)
1210                 dpu_encoder_virt_runtime_resume(encoder);
1211
1212         return rc;
1213 }
1214
1215 static const struct dev_pm_ops dpu_pm_ops = {
1216         SET_RUNTIME_PM_OPS(dpu_runtime_suspend, dpu_runtime_resume, NULL)
1217         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1218                                 pm_runtime_force_resume)
1219 };
1220
1221 static const struct of_device_id dpu_dt_match[] = {
1222         { .compatible = "qcom,sdm845-dpu", },
1223         { .compatible = "qcom,sc7180-dpu", },
1224         {}
1225 };
1226 MODULE_DEVICE_TABLE(of, dpu_dt_match);
1227
1228 static struct platform_driver dpu_driver = {
1229         .probe = dpu_dev_probe,
1230         .remove = dpu_dev_remove,
1231         .driver = {
1232                 .name = "msm_dpu",
1233                 .of_match_table = dpu_dt_match,
1234                 .pm = &dpu_pm_ops,
1235         },
1236 };
1237
1238 void __init msm_dpu_register(void)
1239 {
1240         platform_driver_register(&dpu_driver);
1241 }
1242
1243 void __exit msm_dpu_unregister(void)
1244 {
1245         platform_driver_unregister(&dpu_driver);
1246 }