Merge tag 'for-linus-5.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rw/uml
[linux-2.6-microblaze.git] / drivers / gpu / drm / msm / adreno / a6xx_gpu.c
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
3
4
5 #include "msm_gem.h"
6 #include "msm_mmu.h"
7 #include "msm_gpu_trace.h"
8 #include "a6xx_gpu.h"
9 #include "a6xx_gmu.xml.h"
10
11 #include <linux/devfreq.h>
12
13 #define GPU_PAS_ID 13
14
15 static inline bool _a6xx_check_idle(struct msm_gpu *gpu)
16 {
17         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
18         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
19
20         /* Check that the GMU is idle */
21         if (!a6xx_gmu_isidle(&a6xx_gpu->gmu))
22                 return false;
23
24         /* Check tha the CX master is idle */
25         if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) &
26                         ~A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER)
27                 return false;
28
29         return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) &
30                 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT);
31 }
32
33 bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
34 {
35         /* wait for CP to drain ringbuffer: */
36         if (!adreno_idle(gpu, ring))
37                 return false;
38
39         if (spin_until(_a6xx_check_idle(gpu))) {
40                 DRM_ERROR("%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X rptr/wptr %d/%d\n",
41                         gpu->name, __builtin_return_address(0),
42                         gpu_read(gpu, REG_A6XX_RBBM_STATUS),
43                         gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS),
44                         gpu_read(gpu, REG_A6XX_CP_RB_RPTR),
45                         gpu_read(gpu, REG_A6XX_CP_RB_WPTR));
46                 return false;
47         }
48
49         return true;
50 }
51
52 static void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
53 {
54         uint32_t wptr;
55         unsigned long flags;
56
57         spin_lock_irqsave(&ring->lock, flags);
58
59         /* Copy the shadow to the actual register */
60         ring->cur = ring->next;
61
62         /* Make sure to wrap wptr if we need to */
63         wptr = get_wptr(ring);
64
65         spin_unlock_irqrestore(&ring->lock, flags);
66
67         /* Make sure everything is posted before making a decision */
68         mb();
69
70         gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr);
71 }
72
73 static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter,
74                 u64 iova)
75 {
76         OUT_PKT7(ring, CP_REG_TO_MEM, 3);
77         OUT_RING(ring, counter | (1 << 30) | (2 << 18));
78         OUT_RING(ring, lower_32_bits(iova));
79         OUT_RING(ring, upper_32_bits(iova));
80 }
81
82 static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
83         struct msm_file_private *ctx)
84 {
85         unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;
86         struct msm_drm_private *priv = gpu->dev->dev_private;
87         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
88         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
89         struct msm_ringbuffer *ring = submit->ring;
90         unsigned int i;
91
92         get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO,
93                 rbmemptr_stats(ring, index, cpcycles_start));
94
95         /*
96          * For PM4 the GMU register offsets are calculated from the base of the
97          * GPU registers so we need to add 0x1a800 to the register value on A630
98          * to get the right value from PM4.
99          */
100         get_stats_counter(ring, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L + 0x1a800,
101                 rbmemptr_stats(ring, index, alwayson_start));
102
103         /* Invalidate CCU depth and color */
104         OUT_PKT7(ring, CP_EVENT_WRITE, 1);
105         OUT_RING(ring, PC_CCU_INVALIDATE_DEPTH);
106
107         OUT_PKT7(ring, CP_EVENT_WRITE, 1);
108         OUT_RING(ring, PC_CCU_INVALIDATE_COLOR);
109
110         /* Submit the commands */
111         for (i = 0; i < submit->nr_cmds; i++) {
112                 switch (submit->cmd[i].type) {
113                 case MSM_SUBMIT_CMD_IB_TARGET_BUF:
114                         break;
115                 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
116                         if (priv->lastctx == ctx)
117                                 break;
118                         /* fall-thru */
119                 case MSM_SUBMIT_CMD_BUF:
120                         OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3);
121                         OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));
122                         OUT_RING(ring, upper_32_bits(submit->cmd[i].iova));
123                         OUT_RING(ring, submit->cmd[i].size);
124                         break;
125                 }
126         }
127
128         get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO,
129                 rbmemptr_stats(ring, index, cpcycles_end));
130         get_stats_counter(ring, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L + 0x1a800,
131                 rbmemptr_stats(ring, index, alwayson_end));
132
133         /* Write the fence to the scratch register */
134         OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1);
135         OUT_RING(ring, submit->seqno);
136
137         /*
138          * Execute a CACHE_FLUSH_TS event. This will ensure that the
139          * timestamp is written to the memory and then triggers the interrupt
140          */
141         OUT_PKT7(ring, CP_EVENT_WRITE, 4);
142         OUT_RING(ring, CACHE_FLUSH_TS | (1 << 31));
143         OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence)));
144         OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence)));
145         OUT_RING(ring, submit->seqno);
146
147         trace_msm_gpu_submit_flush(submit,
148                 gmu_read64(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L,
149                         REG_A6XX_GMU_ALWAYS_ON_COUNTER_H));
150
151         a6xx_flush(gpu, ring);
152 }
153
154 static const struct {
155         u32 offset;
156         u32 value;
157 } a6xx_hwcg[] = {
158         {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
159         {REG_A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222},
160         {REG_A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222},
161         {REG_A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222},
162         {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220},
163         {REG_A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220},
164         {REG_A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220},
165         {REG_A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220},
166         {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
167         {REG_A6XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},
168         {REG_A6XX_RBBM_CLOCK_DELAY_SP2, 0x00000080},
169         {REG_A6XX_RBBM_CLOCK_DELAY_SP3, 0x00000080},
170         {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
171         {REG_A6XX_RBBM_CLOCK_HYST_SP1, 0x0000f3cf},
172         {REG_A6XX_RBBM_CLOCK_HYST_SP2, 0x0000f3cf},
173         {REG_A6XX_RBBM_CLOCK_HYST_SP3, 0x0000f3cf},
174         {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
175         {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222},
176         {REG_A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222},
177         {REG_A6XX_RBBM_CLOCK_CNTL_TP3, 0x02222222},
178         {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
179         {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
180         {REG_A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222},
181         {REG_A6XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222},
182         {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
183         {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
184         {REG_A6XX_RBBM_CLOCK_CNTL3_TP2, 0x22222222},
185         {REG_A6XX_RBBM_CLOCK_CNTL3_TP3, 0x22222222},
186         {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
187         {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
188         {REG_A6XX_RBBM_CLOCK_CNTL4_TP2, 0x00022222},
189         {REG_A6XX_RBBM_CLOCK_CNTL4_TP3, 0x00022222},
190         {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
191         {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
192         {REG_A6XX_RBBM_CLOCK_HYST_TP2, 0x77777777},
193         {REG_A6XX_RBBM_CLOCK_HYST_TP3, 0x77777777},
194         {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
195         {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
196         {REG_A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777},
197         {REG_A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777},
198         {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
199         {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},
200         {REG_A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777},
201         {REG_A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777},
202         {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
203         {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
204         {REG_A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777},
205         {REG_A6XX_RBBM_CLOCK_HYST4_TP3, 0x00077777},
206         {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
207         {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
208         {REG_A6XX_RBBM_CLOCK_DELAY_TP2, 0x11111111},
209         {REG_A6XX_RBBM_CLOCK_DELAY_TP3, 0x11111111},
210         {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
211         {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
212         {REG_A6XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111},
213         {REG_A6XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111},
214         {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
215         {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
216         {REG_A6XX_RBBM_CLOCK_DELAY3_TP2, 0x11111111},
217         {REG_A6XX_RBBM_CLOCK_DELAY3_TP3, 0x11111111},
218         {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
219         {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
220         {REG_A6XX_RBBM_CLOCK_DELAY4_TP2, 0x00011111},
221         {REG_A6XX_RBBM_CLOCK_DELAY4_TP3, 0x00011111},
222         {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
223         {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
224         {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
225         {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
226         {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
227         {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
228         {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
229         {REG_A6XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},
230         {REG_A6XX_RBBM_CLOCK_CNTL_RB2, 0x22222222},
231         {REG_A6XX_RBBM_CLOCK_CNTL_RB3, 0x22222222},
232         {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},
233         {REG_A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222},
234         {REG_A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222},
235         {REG_A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222},
236         {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
237         {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
238         {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
239         {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
240         {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
241         {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040f00},
242         {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040f00},
243         {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040f00},
244         {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
245         {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
246         {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
247         {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
248         {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
249         {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
250         {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
251         {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
252         {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
253         {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
254         {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
255         {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
256         {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
257         {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
258         {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
259         {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
260         {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
261         {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
262         {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}
263 };
264
265 static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
266 {
267         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
268         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
269         struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
270         unsigned int i;
271         u32 val;
272
273         val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL);
274
275         /* Don't re-program the registers if they are already correct */
276         if ((!state && !val) || (state && (val == 0x8aa8aa02)))
277                 return;
278
279         /* Disable SP clock before programming HWCG registers */
280         gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0);
281
282         for (i = 0; i < ARRAY_SIZE(a6xx_hwcg); i++)
283                 gpu_write(gpu, a6xx_hwcg[i].offset,
284                         state ? a6xx_hwcg[i].value : 0);
285
286         /* Enable SP clock */
287         gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1);
288
289         gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? 0x8aa8aa02 : 0);
290 }
291
292 static int a6xx_cp_init(struct msm_gpu *gpu)
293 {
294         struct msm_ringbuffer *ring = gpu->rb[0];
295
296         OUT_PKT7(ring, CP_ME_INIT, 8);
297
298         OUT_RING(ring, 0x0000002f);
299
300         /* Enable multiple hardware contexts */
301         OUT_RING(ring, 0x00000003);
302
303         /* Enable error detection */
304         OUT_RING(ring, 0x20000000);
305
306         /* Don't enable header dump */
307         OUT_RING(ring, 0x00000000);
308         OUT_RING(ring, 0x00000000);
309
310         /* No workarounds enabled */
311         OUT_RING(ring, 0x00000000);
312
313         /* Pad rest of the cmds with 0's */
314         OUT_RING(ring, 0x00000000);
315         OUT_RING(ring, 0x00000000);
316
317         a6xx_flush(gpu, ring);
318         return a6xx_idle(gpu, ring) ? 0 : -EINVAL;
319 }
320
321 static int a6xx_ucode_init(struct msm_gpu *gpu)
322 {
323         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
324         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
325
326         if (!a6xx_gpu->sqe_bo) {
327                 a6xx_gpu->sqe_bo = adreno_fw_create_bo(gpu,
328                         adreno_gpu->fw[ADRENO_FW_SQE], &a6xx_gpu->sqe_iova);
329
330                 if (IS_ERR(a6xx_gpu->sqe_bo)) {
331                         int ret = PTR_ERR(a6xx_gpu->sqe_bo);
332
333                         a6xx_gpu->sqe_bo = NULL;
334                         DRM_DEV_ERROR(&gpu->pdev->dev,
335                                 "Could not allocate SQE ucode: %d\n", ret);
336
337                         return ret;
338                 }
339
340                 msm_gem_object_set_name(a6xx_gpu->sqe_bo, "sqefw");
341         }
342
343         gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE_LO,
344                 REG_A6XX_CP_SQE_INSTR_BASE_HI, a6xx_gpu->sqe_iova);
345
346         return 0;
347 }
348
349 static int a6xx_zap_shader_init(struct msm_gpu *gpu)
350 {
351         static bool loaded;
352         int ret;
353
354         if (loaded)
355                 return 0;
356
357         ret = adreno_zap_shader_load(gpu, GPU_PAS_ID);
358
359         loaded = !ret;
360         return ret;
361 }
362
363 #define A6XX_INT_MASK (A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR | \
364           A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW | \
365           A6XX_RBBM_INT_0_MASK_CP_HW_ERROR | \
366           A6XX_RBBM_INT_0_MASK_CP_IB2 | \
367           A6XX_RBBM_INT_0_MASK_CP_IB1 | \
368           A6XX_RBBM_INT_0_MASK_CP_RB | \
369           A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \
370           A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW | \
371           A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
372           A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
373           A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR)
374
375 static int a6xx_hw_init(struct msm_gpu *gpu)
376 {
377         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
378         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
379         int ret;
380
381         /* Make sure the GMU keeps the GPU on while we set it up */
382         a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
383
384         gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0);
385
386         /*
387          * Disable the trusted memory range - we don't actually supported secure
388          * memory rendering at this point in time and we don't want to block off
389          * part of the virtual memory space.
390          */
391         gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO,
392                 REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI, 0x00000000);
393         gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000);
394
395         /* Turn on 64 bit addressing for all blocks */
396         gpu_write(gpu, REG_A6XX_CP_ADDR_MODE_CNTL, 0x1);
397         gpu_write(gpu, REG_A6XX_VSC_ADDR_MODE_CNTL, 0x1);
398         gpu_write(gpu, REG_A6XX_GRAS_ADDR_MODE_CNTL, 0x1);
399         gpu_write(gpu, REG_A6XX_RB_ADDR_MODE_CNTL, 0x1);
400         gpu_write(gpu, REG_A6XX_PC_ADDR_MODE_CNTL, 0x1);
401         gpu_write(gpu, REG_A6XX_HLSQ_ADDR_MODE_CNTL, 0x1);
402         gpu_write(gpu, REG_A6XX_VFD_ADDR_MODE_CNTL, 0x1);
403         gpu_write(gpu, REG_A6XX_VPC_ADDR_MODE_CNTL, 0x1);
404         gpu_write(gpu, REG_A6XX_UCHE_ADDR_MODE_CNTL, 0x1);
405         gpu_write(gpu, REG_A6XX_SP_ADDR_MODE_CNTL, 0x1);
406         gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1);
407         gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1);
408
409         /*
410          * enable hardware clockgating
411          * For now enable clock gating only for a630
412          */
413         if (adreno_is_a630(adreno_gpu))
414                 a6xx_set_hwcg(gpu, true);
415
416         /* VBIF/GBIF start*/
417         if (adreno_is_a640(adreno_gpu) || adreno_is_a650(adreno_gpu)) {
418                 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620);
419                 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620);
420                 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620);
421                 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620);
422                 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620);
423                 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3);
424         } else {
425                 gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3);
426         }
427
428         if (adreno_is_a630(adreno_gpu))
429                 gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009);
430
431         /* Make all blocks contribute to the GPU BUSY perf counter */
432         gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff);
433
434         /* Disable L2 bypass in the UCHE */
435         gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_LO, 0xffffffc0);
436         gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_HI, 0x0001ffff);
437         gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_LO, 0xfffff000);
438         gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_HI, 0x0001ffff);
439         gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_LO, 0xfffff000);
440         gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0001ffff);
441
442         if (!adreno_is_a650(adreno_gpu)) {
443                 /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */
444                 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN_LO,
445                         REG_A6XX_UCHE_GMEM_RANGE_MIN_HI, 0x00100000);
446
447                 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX_LO,
448                         REG_A6XX_UCHE_GMEM_RANGE_MAX_HI,
449                         0x00100000 + adreno_gpu->gmem - 1);
450         }
451
452         gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804);
453         gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4);
454
455         if (adreno_is_a640(adreno_gpu) || adreno_is_a650(adreno_gpu))
456                 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
457         else
458                 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0);
459         gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c);
460
461         /* Setting the mem pool size */
462         gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128);
463
464         /* Setting the primFifo thresholds default values */
465         if (adreno_is_a650(adreno_gpu))
466                 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300000);
467         else if (adreno_is_a640(adreno_gpu))
468                 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200000);
469         else
470                 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, (0x300 << 11));
471
472         /* Set the AHB default slave response to "ERROR" */
473         gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1);
474
475         /* Turn on performance counters */
476         gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1);
477
478         /* Select CP0 to always count cycles */
479         gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT);
480
481         if (adreno_is_a630(adreno_gpu)) {
482                 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 2 << 1);
483                 gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, 2 << 1);
484                 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, 2 << 1);
485                 gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, 2 << 21);
486         }
487
488         /* Enable fault detection */
489         gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL,
490                 (1 << 30) | 0x1fffff);
491
492         gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1);
493
494         /* Set weights for bicubic filtering */
495         if (adreno_is_a650(adreno_gpu)) {
496                 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0);
497                 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1,
498                         0x3fe05ff4);
499                 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2,
500                         0x3fa0ebee);
501                 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3,
502                         0x3f5193ed);
503                 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4,
504                         0x3f0243f0);
505         }
506
507         /* Protect registers from the CP */
508         gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, 0x00000003);
509
510         gpu_write(gpu, REG_A6XX_CP_PROTECT(0),
511                 A6XX_PROTECT_RDONLY(0x600, 0x51));
512         gpu_write(gpu, REG_A6XX_CP_PROTECT(1), A6XX_PROTECT_RW(0xae50, 0x2));
513         gpu_write(gpu, REG_A6XX_CP_PROTECT(2), A6XX_PROTECT_RW(0x9624, 0x13));
514         gpu_write(gpu, REG_A6XX_CP_PROTECT(3), A6XX_PROTECT_RW(0x8630, 0x8));
515         gpu_write(gpu, REG_A6XX_CP_PROTECT(4), A6XX_PROTECT_RW(0x9e70, 0x1));
516         gpu_write(gpu, REG_A6XX_CP_PROTECT(5), A6XX_PROTECT_RW(0x9e78, 0x187));
517         gpu_write(gpu, REG_A6XX_CP_PROTECT(6), A6XX_PROTECT_RW(0xf000, 0x810));
518         gpu_write(gpu, REG_A6XX_CP_PROTECT(7),
519                 A6XX_PROTECT_RDONLY(0xfc00, 0x3));
520         gpu_write(gpu, REG_A6XX_CP_PROTECT(8), A6XX_PROTECT_RW(0x50e, 0x0));
521         gpu_write(gpu, REG_A6XX_CP_PROTECT(9), A6XX_PROTECT_RDONLY(0x50f, 0x0));
522         gpu_write(gpu, REG_A6XX_CP_PROTECT(10), A6XX_PROTECT_RW(0x510, 0x0));
523         gpu_write(gpu, REG_A6XX_CP_PROTECT(11),
524                 A6XX_PROTECT_RDONLY(0x0, 0x4f9));
525         gpu_write(gpu, REG_A6XX_CP_PROTECT(12),
526                 A6XX_PROTECT_RDONLY(0x501, 0xa));
527         gpu_write(gpu, REG_A6XX_CP_PROTECT(13),
528                 A6XX_PROTECT_RDONLY(0x511, 0x44));
529         gpu_write(gpu, REG_A6XX_CP_PROTECT(14), A6XX_PROTECT_RW(0xe00, 0xe));
530         gpu_write(gpu, REG_A6XX_CP_PROTECT(15), A6XX_PROTECT_RW(0x8e00, 0x0));
531         gpu_write(gpu, REG_A6XX_CP_PROTECT(16), A6XX_PROTECT_RW(0x8e50, 0xf));
532         gpu_write(gpu, REG_A6XX_CP_PROTECT(17), A6XX_PROTECT_RW(0xbe02, 0x0));
533         gpu_write(gpu, REG_A6XX_CP_PROTECT(18),
534                 A6XX_PROTECT_RW(0xbe20, 0x11f3));
535         gpu_write(gpu, REG_A6XX_CP_PROTECT(19), A6XX_PROTECT_RW(0x800, 0x82));
536         gpu_write(gpu, REG_A6XX_CP_PROTECT(20), A6XX_PROTECT_RW(0x8a0, 0x8));
537         gpu_write(gpu, REG_A6XX_CP_PROTECT(21), A6XX_PROTECT_RW(0x8ab, 0x19));
538         gpu_write(gpu, REG_A6XX_CP_PROTECT(22), A6XX_PROTECT_RW(0x900, 0x4d));
539         gpu_write(gpu, REG_A6XX_CP_PROTECT(23), A6XX_PROTECT_RW(0x98d, 0x76));
540         gpu_write(gpu, REG_A6XX_CP_PROTECT(24),
541                         A6XX_PROTECT_RDONLY(0x980, 0x4));
542         gpu_write(gpu, REG_A6XX_CP_PROTECT(25), A6XX_PROTECT_RW(0xa630, 0x0));
543
544         if (adreno_is_a650(adreno_gpu)) {
545                 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL,
546                         (1 << 6) | (1 << 5) | (1 << 3) | (1 << 2) | (1 << 1));
547         }
548
549         /* Enable interrupts */
550         gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, A6XX_INT_MASK);
551
552         ret = adreno_hw_init(gpu);
553         if (ret)
554                 goto out;
555
556         ret = a6xx_ucode_init(gpu);
557         if (ret)
558                 goto out;
559
560         /* Always come up on rb 0 */
561         a6xx_gpu->cur_ring = gpu->rb[0];
562
563         /* Enable the SQE_to start the CP engine */
564         gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1);
565
566         ret = a6xx_cp_init(gpu);
567         if (ret)
568                 goto out;
569
570         /*
571          * Try to load a zap shader into the secure world. If successful
572          * we can use the CP to switch out of secure mode. If not then we
573          * have no resource but to try to switch ourselves out manually. If we
574          * guessed wrong then access to the RBBM_SECVID_TRUST_CNTL register will
575          * be blocked and a permissions violation will soon follow.
576          */
577         ret = a6xx_zap_shader_init(gpu);
578         if (!ret) {
579                 OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1);
580                 OUT_RING(gpu->rb[0], 0x00000000);
581
582                 a6xx_flush(gpu, gpu->rb[0]);
583                 if (!a6xx_idle(gpu, gpu->rb[0]))
584                         return -EINVAL;
585         } else if (ret == -ENODEV) {
586                 /*
587                  * This device does not use zap shader (but print a warning
588                  * just in case someone got their dt wrong.. hopefully they
589                  * have a debug UART to realize the error of their ways...
590                  * if you mess this up you are about to crash horribly)
591                  */
592                 dev_warn_once(gpu->dev->dev,
593                         "Zap shader not enabled - using SECVID_TRUST_CNTL instead\n");
594                 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0);
595                 ret = 0;
596         } else {
597                 return ret;
598         }
599
600 out:
601         /*
602          * Tell the GMU that we are done touching the GPU and it can start power
603          * management
604          */
605         a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
606
607         if (a6xx_gpu->gmu.legacy) {
608                 /* Take the GMU out of its special boot mode */
609                 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER);
610         }
611
612         return ret;
613 }
614
615 static void a6xx_dump(struct msm_gpu *gpu)
616 {
617         DRM_DEV_INFO(&gpu->pdev->dev, "status:   %08x\n",
618                         gpu_read(gpu, REG_A6XX_RBBM_STATUS));
619         adreno_dump(gpu);
620 }
621
622 #define VBIF_RESET_ACK_TIMEOUT  100
623 #define VBIF_RESET_ACK_MASK     0x00f0
624
625 static void a6xx_recover(struct msm_gpu *gpu)
626 {
627         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
628         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
629         int i;
630
631         adreno_dump_info(gpu);
632
633         for (i = 0; i < 8; i++)
634                 DRM_DEV_INFO(&gpu->pdev->dev, "CP_SCRATCH_REG%d: %u\n", i,
635                         gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i)));
636
637         if (hang_debug)
638                 a6xx_dump(gpu);
639
640         /*
641          * Turn off keep alive that might have been enabled by the hang
642          * interrupt
643          */
644         gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0);
645
646         gpu->funcs->pm_suspend(gpu);
647         gpu->funcs->pm_resume(gpu);
648
649         msm_gpu_hw_init(gpu);
650 }
651
652 static int a6xx_fault_handler(void *arg, unsigned long iova, int flags)
653 {
654         struct msm_gpu *gpu = arg;
655
656         pr_warn_ratelimited("*** gpu fault: iova=%08lx, flags=%d (%u,%u,%u,%u)\n",
657                         iova, flags,
658                         gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)),
659                         gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)),
660                         gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)),
661                         gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)));
662
663         return -EFAULT;
664 }
665
666 static void a6xx_cp_hw_err_irq(struct msm_gpu *gpu)
667 {
668         u32 status = gpu_read(gpu, REG_A6XX_CP_INTERRUPT_STATUS);
669
670         if (status & A6XX_CP_INT_CP_OPCODE_ERROR) {
671                 u32 val;
672
673                 gpu_write(gpu, REG_A6XX_CP_SQE_STAT_ADDR, 1);
674                 val = gpu_read(gpu, REG_A6XX_CP_SQE_STAT_DATA);
675                 dev_err_ratelimited(&gpu->pdev->dev,
676                         "CP | opcode error | possible opcode=0x%8.8X\n",
677                         val);
678         }
679
680         if (status & A6XX_CP_INT_CP_UCODE_ERROR)
681                 dev_err_ratelimited(&gpu->pdev->dev,
682                         "CP ucode error interrupt\n");
683
684         if (status & A6XX_CP_INT_CP_HW_FAULT_ERROR)
685                 dev_err_ratelimited(&gpu->pdev->dev, "CP | HW fault | status=0x%8.8X\n",
686                         gpu_read(gpu, REG_A6XX_CP_HW_FAULT));
687
688         if (status & A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR) {
689                 u32 val = gpu_read(gpu, REG_A6XX_CP_PROTECT_STATUS);
690
691                 dev_err_ratelimited(&gpu->pdev->dev,
692                         "CP | protected mode error | %s | addr=0x%8.8X | status=0x%8.8X\n",
693                         val & (1 << 20) ? "READ" : "WRITE",
694                         (val & 0x3ffff), val);
695         }
696
697         if (status & A6XX_CP_INT_CP_AHB_ERROR)
698                 dev_err_ratelimited(&gpu->pdev->dev, "CP AHB error interrupt\n");
699
700         if (status & A6XX_CP_INT_CP_VSD_PARITY_ERROR)
701                 dev_err_ratelimited(&gpu->pdev->dev, "CP VSD decoder parity error\n");
702
703         if (status & A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR)
704                 dev_err_ratelimited(&gpu->pdev->dev, "CP illegal instruction error\n");
705
706 }
707
708 static void a6xx_fault_detect_irq(struct msm_gpu *gpu)
709 {
710         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
711         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
712         struct drm_device *dev = gpu->dev;
713         struct msm_drm_private *priv = dev->dev_private;
714         struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
715
716         /*
717          * Force the GPU to stay on until after we finish
718          * collecting information
719          */
720         gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1);
721
722         DRM_DEV_ERROR(&gpu->pdev->dev,
723                 "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n",
724                 ring ? ring->id : -1, ring ? ring->seqno : 0,
725                 gpu_read(gpu, REG_A6XX_RBBM_STATUS),
726                 gpu_read(gpu, REG_A6XX_CP_RB_RPTR),
727                 gpu_read(gpu, REG_A6XX_CP_RB_WPTR),
728                 gpu_read64(gpu, REG_A6XX_CP_IB1_BASE, REG_A6XX_CP_IB1_BASE_HI),
729                 gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE),
730                 gpu_read64(gpu, REG_A6XX_CP_IB2_BASE, REG_A6XX_CP_IB2_BASE_HI),
731                 gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE));
732
733         /* Turn off the hangcheck timer to keep it from bothering us */
734         del_timer(&gpu->hangcheck_timer);
735
736         queue_work(priv->wq, &gpu->recover_work);
737 }
738
739 static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
740 {
741         u32 status = gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS);
742
743         gpu_write(gpu, REG_A6XX_RBBM_INT_CLEAR_CMD, status);
744
745         if (status & A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT)
746                 a6xx_fault_detect_irq(gpu);
747
748         if (status & A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR)
749                 dev_err_ratelimited(&gpu->pdev->dev, "CP | AHB bus error\n");
750
751         if (status & A6XX_RBBM_INT_0_MASK_CP_HW_ERROR)
752                 a6xx_cp_hw_err_irq(gpu);
753
754         if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW)
755                 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB ASYNC overflow\n");
756
757         if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW)
758                 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB bus overflow\n");
759
760         if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
761                 dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n");
762
763         if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
764                 msm_gpu_retire(gpu);
765
766         return IRQ_HANDLED;
767 }
768
769 static const u32 a6xx_register_offsets[REG_ADRENO_REGISTER_MAX] = {
770         REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE, REG_A6XX_CP_RB_BASE),
771         REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE_HI, REG_A6XX_CP_RB_BASE_HI),
772         REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR_ADDR,
773                 REG_A6XX_CP_RB_RPTR_ADDR_LO),
774         REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR_ADDR_HI,
775                 REG_A6XX_CP_RB_RPTR_ADDR_HI),
776         REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR, REG_A6XX_CP_RB_RPTR),
777         REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_WPTR, REG_A6XX_CP_RB_WPTR),
778         REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_A6XX_CP_RB_CNTL),
779 };
780
781 static int a6xx_pm_resume(struct msm_gpu *gpu)
782 {
783         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
784         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
785         int ret;
786
787         gpu->needs_hw_init = true;
788
789         ret = a6xx_gmu_resume(a6xx_gpu);
790         if (ret)
791                 return ret;
792
793         msm_gpu_resume_devfreq(gpu);
794
795         return 0;
796 }
797
798 static int a6xx_pm_suspend(struct msm_gpu *gpu)
799 {
800         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
801         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
802
803         devfreq_suspend_device(gpu->devfreq.devfreq);
804
805         return a6xx_gmu_stop(a6xx_gpu);
806 }
807
808 static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
809 {
810         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
811         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
812
813         /* Force the GPU power on so we can read this register */
814         a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
815
816         *value = gpu_read64(gpu, REG_A6XX_RBBM_PERFCTR_CP_0_LO,
817                 REG_A6XX_RBBM_PERFCTR_CP_0_HI);
818
819         a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
820         return 0;
821 }
822
823 static struct msm_ringbuffer *a6xx_active_ring(struct msm_gpu *gpu)
824 {
825         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
826         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
827
828         return a6xx_gpu->cur_ring;
829 }
830
831 static void a6xx_destroy(struct msm_gpu *gpu)
832 {
833         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
834         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
835
836         if (a6xx_gpu->sqe_bo) {
837                 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace);
838                 drm_gem_object_put_unlocked(a6xx_gpu->sqe_bo);
839         }
840
841         a6xx_gmu_remove(a6xx_gpu);
842
843         adreno_gpu_cleanup(adreno_gpu);
844         kfree(a6xx_gpu);
845 }
846
847 static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu)
848 {
849         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
850         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
851         u64 busy_cycles, busy_time;
852
853
854         /* Only read the gpu busy if the hardware is already active */
855         if (pm_runtime_get_if_in_use(a6xx_gpu->gmu.dev) == 0)
856                 return 0;
857
858         busy_cycles = gmu_read64(&a6xx_gpu->gmu,
859                         REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L,
860                         REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H);
861
862         busy_time = (busy_cycles - gpu->devfreq.busy_cycles) * 10;
863         do_div(busy_time, 192);
864
865         gpu->devfreq.busy_cycles = busy_cycles;
866
867         pm_runtime_put(a6xx_gpu->gmu.dev);
868
869         if (WARN_ON(busy_time > ~0LU))
870                 return ~0LU;
871
872         return (unsigned long)busy_time;
873 }
874
875 static const struct adreno_gpu_funcs funcs = {
876         .base = {
877                 .get_param = adreno_get_param,
878                 .hw_init = a6xx_hw_init,
879                 .pm_suspend = a6xx_pm_suspend,
880                 .pm_resume = a6xx_pm_resume,
881                 .recover = a6xx_recover,
882                 .submit = a6xx_submit,
883                 .flush = a6xx_flush,
884                 .active_ring = a6xx_active_ring,
885                 .irq = a6xx_irq,
886                 .destroy = a6xx_destroy,
887 #if defined(CONFIG_DRM_MSM_GPU_STATE)
888                 .show = a6xx_show,
889 #endif
890                 .gpu_busy = a6xx_gpu_busy,
891                 .gpu_get_freq = a6xx_gmu_get_freq,
892                 .gpu_set_freq = a6xx_gmu_set_freq,
893 #if defined(CONFIG_DRM_MSM_GPU_STATE)
894                 .gpu_state_get = a6xx_gpu_state_get,
895                 .gpu_state_put = a6xx_gpu_state_put,
896                 .create_address_space = adreno_iommu_create_address_space,
897 #endif
898         },
899         .get_timestamp = a6xx_get_timestamp,
900 };
901
902 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
903 {
904         struct msm_drm_private *priv = dev->dev_private;
905         struct platform_device *pdev = priv->gpu_pdev;
906         struct device_node *node;
907         struct a6xx_gpu *a6xx_gpu;
908         struct adreno_gpu *adreno_gpu;
909         struct msm_gpu *gpu;
910         int ret;
911
912         a6xx_gpu = kzalloc(sizeof(*a6xx_gpu), GFP_KERNEL);
913         if (!a6xx_gpu)
914                 return ERR_PTR(-ENOMEM);
915
916         adreno_gpu = &a6xx_gpu->base;
917         gpu = &adreno_gpu->base;
918
919         adreno_gpu->registers = NULL;
920         adreno_gpu->reg_offsets = a6xx_register_offsets;
921
922         ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
923         if (ret) {
924                 a6xx_destroy(&(a6xx_gpu->base.base));
925                 return ERR_PTR(ret);
926         }
927
928         /* Check if there is a GMU phandle and set it up */
929         node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0);
930
931         /* FIXME: How do we gracefully handle this? */
932         BUG_ON(!node);
933
934         ret = a6xx_gmu_init(a6xx_gpu, node);
935         if (ret) {
936                 a6xx_destroy(&(a6xx_gpu->base.base));
937                 return ERR_PTR(ret);
938         }
939
940         if (gpu->aspace)
941                 msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu,
942                                 a6xx_fault_handler);
943
944         return gpu;
945 }