drivers/gpu/drm/msm/adreno/a6xx_gmu.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
   3
   4 #include <linux/clk.h>
   5 #include <linux/interconnect.h>
   6 #include <linux/pm_domain.h>
   7 #include <linux/pm_opp.h>
   8 #include <soc/qcom/cmd-db.h>
   9 #include <drm/drm_gem.h>
  10
  11 #include "a6xx_gpu.h"
  12 #include "a6xx_gmu.xml.h"
  13 #include "msm_gem.h"
  14 #include "msm_gpu_trace.h"
  15 #include "msm_mmu.h"
  16
  17 static void a6xx_gmu_fault(struct a6xx_gmu *gmu)
  18 {
  19         struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
  20         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
  21         struct msm_gpu *gpu = &adreno_gpu->base;
  22
  23         /* FIXME: add a banner here */
  24         gmu->hung = true;
  25
  26         /* Turn off the hangcheck timer while we are resetting */
  27         del_timer(&gpu->hangcheck_timer);
  28
  29         /* Queue the GPU handler because we need to treat this as a recovery */
  30         kthread_queue_work(gpu->worker, &gpu->recover_work);
  31 }
  32
  33 static irqreturn_t a6xx_gmu_irq(int irq, void *data)
  34 {
  35         struct a6xx_gmu *gmu = data;
  36         u32 status;
  37
  38         status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS);
  39         gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status);
  40
  41         if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE) {
  42                 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n");
  43
  44                 a6xx_gmu_fault(gmu);
  45         }
  46
  47         if (status &  A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR)
  48                 dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n");
  49
  50         if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR)
  51                 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n",
  52                         gmu_read(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS));
  53
  54         return IRQ_HANDLED;
  55 }
  56
  57 static irqreturn_t a6xx_hfi_irq(int irq, void *data)
  58 {
  59         struct a6xx_gmu *gmu = data;
  60         u32 status;
  61
  62         status = gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO);
  63         gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, status);
  64
  65         if (status & A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) {
  66                 dev_err_ratelimited(gmu->dev, "GMU firmware fault\n");
  67
  68                 a6xx_gmu_fault(gmu);
  69         }
  70
  71         return IRQ_HANDLED;
  72 }
  73
  74 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu)
  75 {
  76         u32 val;
  77
  78         /* This can be called from gpu state code so make sure GMU is valid */
  79         if (!gmu->initialized)
  80                 return false;
  81
  82         val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS);
  83
  84         return !(val &
  85                 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF |
  86                 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF));
  87 }
  88
  89 /* Check to see if the GX rail is still powered */
  90 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu)
  91 {
  92         u32 val;
  93
  94         /* This can be called from gpu state code so make sure GMU is valid */
  95         if (!gmu->initialized)
  96                 return false;
  97
  98         val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS);
  99
 100         return !(val &
 101                 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF |
 102                 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF));
 103 }
 104
 105 void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp)
 106 {
 107         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 108         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
 109         struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
 110         u32 perf_index;
 111         unsigned long gpu_freq;
 112         int ret = 0;
 113
 114         gpu_freq = dev_pm_opp_get_freq(opp);
 115
 116         if (gpu_freq == gmu->freq)
 117                 return;
 118
 119         for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++)
 120                 if (gpu_freq == gmu->gpu_freqs[perf_index])
 121                         break;
 122
 123         gmu->current_perf_index = perf_index;
 124         gmu->freq = gmu->gpu_freqs[perf_index];
 125
 126         trace_msm_gmu_freq_change(gmu->freq, perf_index);
 127
 128         /*
 129          * This can get called from devfreq while the hardware is idle. Don't
 130          * bring up the power if it isn't already active
 131          */
 132         if (pm_runtime_get_if_in_use(gmu->dev) == 0)
 133                 return;
 134
 135         if (!gmu->legacy) {
 136                 a6xx_hfi_set_freq(gmu, perf_index);
 137                 dev_pm_opp_set_opp(&gpu->pdev->dev, opp);
 138                 pm_runtime_put(gmu->dev);
 139                 return;
 140         }
 141
 142         gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0);
 143
 144         gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING,
 145                         ((3 & 0xf) << 28) | perf_index);
 146
 147         /*
 148          * Send an invalid index as a vote for the bus bandwidth and let the
 149          * firmware decide on the right vote
 150          */
 151         gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff);
 152
 153         /* Set and clear the OOB for DCVS to trigger the GMU */
 154         a6xx_gmu_set_oob(gmu, GMU_OOB_DCVS_SET);
 155         a6xx_gmu_clear_oob(gmu, GMU_OOB_DCVS_SET);
 156
 157         ret = gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN);
 158         if (ret)
 159                 dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret);
 160
 161         dev_pm_opp_set_opp(&gpu->pdev->dev, opp);
 162         pm_runtime_put(gmu->dev);
 163 }
 164
 165 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu)
 166 {
 167         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 168         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
 169         struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
 170
 171         return  gmu->freq;
 172 }
 173
 174 static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu)
 175 {
 176         u32 val;
 177         int local = gmu->idle_level;
 178
 179         /* SPTP and IFPC both report as IFPC */
 180         if (gmu->idle_level == GMU_IDLE_STATE_SPTP)
 181                 local = GMU_IDLE_STATE_IFPC;
 182
 183         val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE);
 184
 185         if (val == local) {
 186                 if (gmu->idle_level != GMU_IDLE_STATE_IFPC ||
 187                         !a6xx_gmu_gx_is_on(gmu))
 188                         return true;
 189         }
 190
 191         return false;
 192 }
 193
 194 /* Wait for the GMU to get to its most idle state */
 195 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu)
 196 {
 197         return spin_until(a6xx_gmu_check_idle_level(gmu));
 198 }
 199
 200 static int a6xx_gmu_start(struct a6xx_gmu *gmu)
 201 {
 202         int ret;
 203         u32 val;
 204         u32 mask, reset_val;
 205
 206         val = gmu_read(gmu, REG_A6XX_GMU_CM3_DTCM_START + 0xff8);
 207         if (val <= 0x20010004) {
 208                 mask = 0xffffffff;
 209                 reset_val = 0xbabeface;
 210         } else {
 211                 mask = 0x1ff;
 212                 reset_val = 0x100;
 213         }
 214
 215         gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1);
 216
 217         /* Set the log wptr index
 218          * note: downstream saves the value in poweroff and restores it here
 219          */
 220         gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0);
 221
 222         gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0);
 223
 224         ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, val,
 225                 (val & mask) == reset_val, 100, 10000);
 226
 227         if (ret)
 228                 DRM_DEV_ERROR(gmu->dev, "GMU firmware initialization timed out\n");
 229
 230         return ret;
 231 }
 232
 233 static int a6xx_gmu_hfi_start(struct a6xx_gmu *gmu)
 234 {
 235         u32 val;
 236         int ret;
 237
 238         gmu_write(gmu, REG_A6XX_GMU_HFI_CTRL_INIT, 1);
 239
 240         ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_HFI_CTRL_STATUS, val,
 241                 val & 1, 100, 10000);
 242         if (ret)
 243                 DRM_DEV_ERROR(gmu->dev, "Unable to start the HFI queues\n");
 244
 245         return ret;
 246 }
 247
 248 struct a6xx_gmu_oob_bits {
 249         int set, ack, set_new, ack_new, clear, clear_new;
 250         const char *name;
 251 };
 252
 253 /* These are the interrupt / ack bits for each OOB request that are set
 254  * in a6xx_gmu_set_oob and a6xx_clear_oob
 255  */
 256 static const struct a6xx_gmu_oob_bits a6xx_gmu_oob_bits[] = {
 257         [GMU_OOB_GPU_SET] = {
 258                 .name = "GPU_SET",
 259                 .set = 16,
 260                 .ack = 24,
 261                 .set_new = 30,
 262                 .ack_new = 31,
 263                 .clear = 24,
 264                 .clear_new = 31,
 265         },
 266
 267         [GMU_OOB_PERFCOUNTER_SET] = {
 268                 .name = "PERFCOUNTER",
 269                 .set = 17,
 270                 .ack = 25,
 271                 .set_new = 28,
 272                 .ack_new = 30,
 273                 .clear = 25,
 274                 .clear_new = 29,
 275         },
 276
 277         [GMU_OOB_BOOT_SLUMBER] = {
 278                 .name = "BOOT_SLUMBER",
 279                 .set = 22,
 280                 .ack = 30,
 281                 .clear = 30,
 282         },
 283
 284         [GMU_OOB_DCVS_SET] = {
 285                 .name = "GPU_DCVS",
 286                 .set = 23,
 287                 .ack = 31,
 288                 .clear = 31,
 289         },
 290 };
 291
 292 /* Trigger a OOB (out of band) request to the GMU */
 293 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
 294 {
 295         int ret;
 296         u32 val;
 297         int request, ack;
 298
 299         if (state >= ARRAY_SIZE(a6xx_gmu_oob_bits))
 300                 return -EINVAL;
 301
 302         if (gmu->legacy) {
 303                 request = a6xx_gmu_oob_bits[state].set;
 304                 ack = a6xx_gmu_oob_bits[state].ack;
 305         } else {
 306                 request = a6xx_gmu_oob_bits[state].set_new;
 307                 ack = a6xx_gmu_oob_bits[state].ack_new;
 308                 if (!request || !ack) {
 309                         DRM_DEV_ERROR(gmu->dev,
 310                                       "Invalid non-legacy GMU request %s\n",
 311                                       a6xx_gmu_oob_bits[state].name);
 312                         return -EINVAL;
 313                 }
 314         }
 315
 316         /* Trigger the equested OOB operation */
 317         gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << request);
 318
 319         /* Wait for the acknowledge interrupt */
 320         ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val,
 321                 val & (1 << ack), 100, 10000);
 322
 323         if (ret)
 324                 DRM_DEV_ERROR(gmu->dev,
 325                         "Timeout waiting for GMU OOB set %s: 0x%x\n",
 326                                 a6xx_gmu_oob_bits[state].name,
 327                                 gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO));
 328
 329         /* Clear the acknowledge interrupt */
 330         gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, 1 << ack);
 331
 332         return ret;
 333 }
 334
 335 /* Clear a pending OOB state in the GMU */
 336 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
 337 {
 338         int bit;
 339
 340         if (state >= ARRAY_SIZE(a6xx_gmu_oob_bits))
 341                 return;
 342
 343         if (gmu->legacy)
 344                 bit = a6xx_gmu_oob_bits[state].clear;
 345         else
 346                 bit = a6xx_gmu_oob_bits[state].clear_new;
 347
 348         gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << bit);
 349 }
 350
 351 /* Enable CPU control of SPTP power power collapse */
 352 static int a6xx_sptprac_enable(struct a6xx_gmu *gmu)
 353 {
 354         int ret;
 355         u32 val;
 356
 357         if (!gmu->legacy)
 358                 return 0;
 359
 360         gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000);
 361
 362         ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val,
 363                 (val & 0x38) == 0x28, 1, 100);
 364
 365         if (ret) {
 366                 DRM_DEV_ERROR(gmu->dev, "Unable to power on SPTPRAC: 0x%x\n",
 367                         gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS));
 368         }
 369
 370         return 0;
 371 }
 372
 373 /* Disable CPU control of SPTP power power collapse */
 374 static void a6xx_sptprac_disable(struct a6xx_gmu *gmu)
 375 {
 376         u32 val;
 377         int ret;
 378
 379         if (!gmu->legacy)
 380                 return;
 381
 382         /* Make sure retention is on */
 383         gmu_rmw(gmu, REG_A6XX_GPU_CC_GX_GDSCR, 0, (1 << 11));
 384
 385         gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001);
 386
 387         ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val,
 388                 (val & 0x04), 100, 10000);
 389
 390         if (ret)
 391                 DRM_DEV_ERROR(gmu->dev, "failed to power off SPTPRAC: 0x%x\n",
 392                         gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS));
 393 }
 394
 395 /* Let the GMU know we are starting a boot sequence */
 396 static int a6xx_gmu_gfx_rail_on(struct a6xx_gmu *gmu)
 397 {
 398         u32 vote;
 399
 400         /* Let the GMU know we are getting ready for boot */
 401         gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0);
 402
 403         /* Choose the "default" power level as the highest available */
 404         vote = gmu->gx_arc_votes[gmu->nr_gpu_freqs - 1];
 405
 406         gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff);
 407         gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff);
 408
 409         /* Let the GMU know the boot sequence has started */
 410         return a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER);
 411 }
 412
 413 /* Let the GMU know that we are about to go into slumber */
 414 static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu)
 415 {
 416         int ret;
 417
 418         /* Disable the power counter so the GMU isn't busy */
 419         gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0);
 420
 421         /* Disable SPTP_PC if the CPU is responsible for it */
 422         if (gmu->idle_level < GMU_IDLE_STATE_SPTP)
 423                 a6xx_sptprac_disable(gmu);
 424
 425         if (!gmu->legacy) {
 426                 ret = a6xx_hfi_send_prep_slumber(gmu);
 427                 goto out;
 428         }
 429
 430         /* Tell the GMU to get ready to slumber */
 431         gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 1);
 432
 433         ret = a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER);
 434         a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER);
 435
 436         if (!ret) {
 437                 /* Check to see if the GMU really did slumber */
 438                 if (gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE)
 439                         != 0x0f) {
 440                         DRM_DEV_ERROR(gmu->dev, "The GMU did not go into slumber\n");
 441                         ret = -ETIMEDOUT;
 442                 }
 443         }
 444
 445 out:
 446         /* Put fence into allow mode */
 447         gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
 448         return ret;
 449 }
 450
 451 static int a6xx_rpmh_start(struct a6xx_gmu *gmu)
 452 {
 453         int ret;
 454         u32 val;
 455
 456         gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1 << 1);
 457         /* Wait for the register to finish posting */
 458         wmb();
 459
 460         ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_RSCC_CONTROL_ACK, val,
 461                 val & (1 << 1), 100, 10000);
 462         if (ret) {
 463                 DRM_DEV_ERROR(gmu->dev, "Unable to power on the GPU RSC\n");
 464                 return ret;
 465         }
 466
 467         ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_SEQ_BUSY_DRV0, val,
 468                 !val, 100, 10000);
 469
 470         if (ret) {
 471                 DRM_DEV_ERROR(gmu->dev, "GPU RSC sequence stuck while waking up the GPU\n");
 472                 return ret;
 473         }
 474
 475         gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);
 476
 477         /* Set up CX GMU counter 0 to count busy ticks */
 478         gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000);
 479         gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, 0x20);
 480
 481         /* Enable the power counter */
 482         gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1);
 483         return 0;
 484 }
 485
 486 static void a6xx_rpmh_stop(struct a6xx_gmu *gmu)
 487 {
 488         int ret;
 489         u32 val;
 490
 491         gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1);
 492
 493         ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0,
 494                 val, val & (1 << 16), 100, 10000);
 495         if (ret)
 496                 DRM_DEV_ERROR(gmu->dev, "Unable to power off the GPU RSC\n");
 497
 498         gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);
 499 }
 500
 501 static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value)
 502 {
 503         return msm_writel(value, ptr + (offset << 2));
 504 }
 505
 506 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
 507                 const char *name);
 508
 509 static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
 510 {
 511         struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
 512         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
 513         struct platform_device *pdev = to_platform_device(gmu->dev);
 514         void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc");
 515         void __iomem *seqptr;
 516         uint32_t pdc_address_offset;
 517         bool pdc_in_aop = false;
 518
 519         if (!pdcptr)
 520                 goto err;
 521
 522         if (adreno_is_a650(adreno_gpu) || adreno_is_a660_family(adreno_gpu))
 523                 pdc_in_aop = true;
 524         else if (adreno_is_a618(adreno_gpu) || adreno_is_a640(adreno_gpu) ||
 525                  adreno_is_a680(adreno_gpu))
 526                 pdc_address_offset = 0x30090;
 527         else
 528                 pdc_address_offset = 0x30080;
 529
 530         if (!pdc_in_aop) {
 531                 seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq");
 532                 if (!seqptr)
 533                         goto err;
 534         }
 535
 536         /* Disable SDE clock gating */
 537         gmu_write_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24));
 538
 539         /* Setup RSC PDC handshake for sleep and wakeup */
 540         gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1);
 541         gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0);
 542         gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0);
 543         gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0);
 544         gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0);
 545         gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 0x80000000);
 546         gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0);
 547         gmu_write_rscc(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0);
 548         gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520);
 549         gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510);
 550         gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514);
 551
 552         /* Load RSC sequencer uCode for sleep and wakeup */
 553         if (adreno_is_a650_family(adreno_gpu)) {
 554                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xeaaae5a0);
 555                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xe1a1ebab);
 556                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e0a581);
 557                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xecac82e2);
 558                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020edad);
 559         } else {
 560                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0);
 561                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7);
 562                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1);
 563                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2);
 564                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8);
 565         }
 566
 567         if (pdc_in_aop)
 568                 goto setup_pdc;
 569
 570         /* Load PDC sequencer uCode for power up and power down sequence */
 571         pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1);
 572         pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2);
 573         pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0);
 574         pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284);
 575         pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc);
 576
 577         /* Set TCS commands used by PDC sequence for low power modes */
 578         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK, 7);
 579         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0);
 580         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0);
 581         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108);
 582         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010);
 583         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA, 1);
 584         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108);
 585         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000);
 586         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0);
 587
 588         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108);
 589         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, pdc_address_offset);
 590         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0);
 591
 592         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7);
 593         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0);
 594         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0);
 595         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108);
 596         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010);
 597         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2);
 598
 599         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);
 600         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000);
 601         if (adreno_is_a618(adreno_gpu) || adreno_is_a650_family(adreno_gpu))
 602                 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2);
 603         else
 604                 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);
 605         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108);
 606         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, pdc_address_offset);
 607         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3);
 608
 609         /* Setup GPU PDC */
 610 setup_pdc:
 611         pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0);
 612         pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001);
 613
 614         /* ensure no writes happen before the uCode is fully written */
 615         wmb();
 616
 617 err:
 618         if (!IS_ERR_OR_NULL(pdcptr))
 619                 iounmap(pdcptr);
 620         if (!IS_ERR_OR_NULL(seqptr))
 621                 iounmap(seqptr);
 622 }
 623
 624 /*
 625  * The lowest 16 bits of this value are the number of XO clock cycles for main
 626  * hysteresis which is set at 0x1680 cycles (300 us).  The higher 16 bits are
 627  * for the shorter hysteresis that happens after main - this is 0xa (.5 us)
 628  */
 629
 630 #define GMU_PWR_COL_HYST 0x000a1680
 631
 632 /* Set up the idle state for the GMU */
 633 static void a6xx_gmu_power_config(struct a6xx_gmu *gmu)
 634 {
 635         /* Disable GMU WB/RB buffer */
 636         gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1);
 637         gmu_write(gmu, REG_A6XX_GMU_ICACHE_CONFIG, 0x1);
 638         gmu_write(gmu, REG_A6XX_GMU_DCACHE_CONFIG, 0x1);
 639
 640         gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400);
 641
 642         switch (gmu->idle_level) {
 643         case GMU_IDLE_STATE_IFPC:
 644                 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST,
 645                         GMU_PWR_COL_HYST);
 646                 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0,
 647                         A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE |
 648                         A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE);
 649                 fallthrough;
 650         case GMU_IDLE_STATE_SPTP:
 651                 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST,
 652                         GMU_PWR_COL_HYST);
 653                 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0,
 654                         A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE |
 655                         A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE);
 656         }
 657
 658         /* Enable RPMh GPU client */
 659         gmu_rmw(gmu, REG_A6XX_GMU_RPMH_CTRL, 0,
 660                 A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE |
 661                 A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE |
 662                 A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE |
 663                 A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE |
 664                 A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE |
 665                 A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE);
 666 }
 667
 668 struct block_header {
 669         u32 addr;
 670         u32 size;
 671         u32 type;
 672         u32 value;
 673         u32 data[];
 674 };
 675
 676 /* this should be a general kernel helper */
 677 static int in_range(u32 addr, u32 start, u32 size)
 678 {
 679         return addr >= start && addr < start + size;
 680 }
 681
 682 static bool fw_block_mem(struct a6xx_gmu_bo *bo, const struct block_header *blk)
 683 {
 684         if (!in_range(blk->addr, bo->iova, bo->size))
 685                 return false;
 686
 687         memcpy(bo->virt + blk->addr - bo->iova, blk->data, blk->size);
 688         return true;
 689 }
 690
 691 static int a6xx_gmu_fw_load(struct a6xx_gmu *gmu)
 692 {
 693         struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
 694         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
 695         const struct firmware *fw_image = adreno_gpu->fw[ADRENO_FW_GMU];
 696         const struct block_header *blk;
 697         u32 reg_offset;
 698
 699         u32 itcm_base = 0x00000000;
 700         u32 dtcm_base = 0x00040000;
 701
 702         if (adreno_is_a650_family(adreno_gpu))
 703                 dtcm_base = 0x10004000;
 704
 705         if (gmu->legacy) {
 706                 /* Sanity check the size of the firmware that was loaded */
 707                 if (fw_image->size > 0x8000) {
 708                         DRM_DEV_ERROR(gmu->dev,
 709                                 "GMU firmware is bigger than the available region\n");
 710                         return -EINVAL;
 711                 }
 712
 713                 gmu_write_bulk(gmu, REG_A6XX_GMU_CM3_ITCM_START,
 714                                (u32*) fw_image->data, fw_image->size);
 715                 return 0;
 716         }
 717
 718
 719         for (blk = (const struct block_header *) fw_image->data;
 720              (const u8*) blk < fw_image->data + fw_image->size;
 721              blk = (const struct block_header *) &blk->data[blk->size >> 2]) {
 722                 if (blk->size == 0)
 723                         continue;
 724
 725                 if (in_range(blk->addr, itcm_base, SZ_16K)) {
 726                         reg_offset = (blk->addr - itcm_base) >> 2;
 727                         gmu_write_bulk(gmu,
 728                                 REG_A6XX_GMU_CM3_ITCM_START + reg_offset,
 729                                 blk->data, blk->size);
 730                 } else if (in_range(blk->addr, dtcm_base, SZ_16K)) {
 731                         reg_offset = (blk->addr - dtcm_base) >> 2;
 732                         gmu_write_bulk(gmu,
 733                                 REG_A6XX_GMU_CM3_DTCM_START + reg_offset,
 734                                 blk->data, blk->size);
 735                 } else if (!fw_block_mem(&gmu->icache, blk) &&
 736                            !fw_block_mem(&gmu->dcache, blk) &&
 737                            !fw_block_mem(&gmu->dummy, blk)) {
 738                         DRM_DEV_ERROR(gmu->dev,
 739                                 "failed to match fw block (addr=%.8x size=%d data[0]=%.8x)\n",
 740                                 blk->addr, blk->size, blk->data[0]);
 741                 }
 742         }
 743
 744         return 0;
 745 }
 746
 747 static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
 748 {
 749         static bool rpmh_init;
 750         struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
 751         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
 752         int ret;
 753         u32 chipid;
 754
 755         if (adreno_is_a650_family(adreno_gpu)) {
 756                 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 1);
 757                 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1);
 758         }
 759
 760         if (state == GMU_WARM_BOOT) {
 761                 ret = a6xx_rpmh_start(gmu);
 762                 if (ret)
 763                         return ret;
 764         } else {
 765                 if (WARN(!adreno_gpu->fw[ADRENO_FW_GMU],
 766                         "GMU firmware is not loaded\n"))
 767                         return -ENOENT;
 768
 769                 /* Turn on register retention */
 770                 gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1);
 771
 772                 /* We only need to load the RPMh microcode once */
 773                 if (!rpmh_init) {
 774                         a6xx_gmu_rpmh_init(gmu);
 775                         rpmh_init = true;
 776                 } else {
 777                         ret = a6xx_rpmh_start(gmu);
 778                         if (ret)
 779                                 return ret;
 780                 }
 781
 782                 ret = a6xx_gmu_fw_load(gmu);
 783                 if (ret)
 784                         return ret;
 785         }
 786
 787         gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0);
 788         gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02);
 789
 790         /* Write the iova of the HFI table */
 791         gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_ADDR, gmu->hfi.iova);
 792         gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_INFO, 1);
 793
 794         gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0,
 795                 (1 << 31) | (0xa << 18) | (0xa0));
 796
 797         chipid = adreno_gpu->rev.core << 24;
 798         chipid |= adreno_gpu->rev.major << 16;
 799         chipid |= adreno_gpu->rev.minor << 12;
 800         chipid |= adreno_gpu->rev.patchid << 8;
 801
 802         gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid);
 803
 804         gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG,
 805                   gmu->log.iova | (gmu->log.size / SZ_4K - 1));
 806
 807         /* Set up the lowest idle level on the GMU */
 808         a6xx_gmu_power_config(gmu);
 809
 810         ret = a6xx_gmu_start(gmu);
 811         if (ret)
 812                 return ret;
 813
 814         if (gmu->legacy) {
 815                 ret = a6xx_gmu_gfx_rail_on(gmu);
 816                 if (ret)
 817                         return ret;
 818         }
 819
 820         /* Enable SPTP_PC if the CPU is responsible for it */
 821         if (gmu->idle_level < GMU_IDLE_STATE_SPTP) {
 822                 ret = a6xx_sptprac_enable(gmu);
 823                 if (ret)
 824                         return ret;
 825         }
 826
 827         ret = a6xx_gmu_hfi_start(gmu);
 828         if (ret)
 829                 return ret;
 830
 831         /* FIXME: Do we need this wmb() here? */
 832         wmb();
 833
 834         return 0;
 835 }
 836
 837 #define A6XX_HFI_IRQ_MASK \
 838         (A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT)
 839
 840 #define A6XX_GMU_IRQ_MASK \
 841         (A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE | \
 842          A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR | \
 843          A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR)
 844
 845 static void a6xx_gmu_irq_disable(struct a6xx_gmu *gmu)
 846 {
 847         disable_irq(gmu->gmu_irq);
 848         disable_irq(gmu->hfi_irq);
 849
 850         gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0);
 851         gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0);
 852 }
 853
 854 static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu)
 855 {
 856         u32 val;
 857
 858         /* Make sure there are no outstanding RPMh votes */
 859         gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS0_DRV0_STATUS, val,
 860                 (val & 1), 100, 10000);
 861         gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS1_DRV0_STATUS, val,
 862                 (val & 1), 100, 10000);
 863         gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS2_DRV0_STATUS, val,
 864                 (val & 1), 100, 10000);
 865         gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val,
 866                 (val & 1), 100, 1000);
 867 }
 868
 869 /* Force the GMU off in case it isn't responsive */
 870 static void a6xx_gmu_force_off(struct a6xx_gmu *gmu)
 871 {
 872         /* Flush all the queues */
 873         a6xx_hfi_stop(gmu);
 874
 875         /* Stop the interrupts */
 876         a6xx_gmu_irq_disable(gmu);
 877
 878         /* Force off SPTP in case the GMU is managing it */
 879         a6xx_sptprac_disable(gmu);
 880
 881         /* Make sure there are no outstanding RPMh votes */
 882         a6xx_gmu_rpmh_off(gmu);
 883 }
 884
 885 static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu)
 886 {
 887         struct dev_pm_opp *gpu_opp;
 888         unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index];
 889
 890         gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true);
 891         if (IS_ERR_OR_NULL(gpu_opp))
 892                 return;
 893
 894         gmu->freq = 0; /* so a6xx_gmu_set_freq() doesn't exit early */
 895         a6xx_gmu_set_freq(gpu, gpu_opp);
 896         dev_pm_opp_put(gpu_opp);
 897 }
 898
 899 static void a6xx_gmu_set_initial_bw(struct msm_gpu *gpu, struct a6xx_gmu *gmu)
 900 {
 901         struct dev_pm_opp *gpu_opp;
 902         unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index];
 903
 904         gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true);
 905         if (IS_ERR_OR_NULL(gpu_opp))
 906                 return;
 907
 908         dev_pm_opp_set_opp(&gpu->pdev->dev, gpu_opp);
 909         dev_pm_opp_put(gpu_opp);
 910 }
 911
 912 int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
 913 {
 914         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
 915         struct msm_gpu *gpu = &adreno_gpu->base;
 916         struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
 917         int status, ret;
 918
 919         if (WARN(!gmu->initialized, "The GMU is not set up yet\n"))
 920                 return 0;
 921
 922         gmu->hung = false;
 923
 924         /* Turn on the resources */
 925         pm_runtime_get_sync(gmu->dev);
 926
 927         /*
 928          * "enable" the GX power domain which won't actually do anything but it
 929          * will make sure that the refcounting is correct in case we need to
 930          * bring down the GX after a GMU failure
 931          */
 932         if (!IS_ERR_OR_NULL(gmu->gxpd))
 933                 pm_runtime_get_sync(gmu->gxpd);
 934
 935         /* Use a known rate to bring up the GMU */
 936         clk_set_rate(gmu->core_clk, 200000000);
 937         clk_set_rate(gmu->hub_clk, 150000000);
 938         ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks);
 939         if (ret) {
 940                 pm_runtime_put(gmu->gxpd);
 941                 pm_runtime_put(gmu->dev);
 942                 return ret;
 943         }
 944
 945         /* Set the bus quota to a reasonable value for boot */
 946         a6xx_gmu_set_initial_bw(gpu, gmu);
 947
 948         /* Enable the GMU interrupt */
 949         gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0);
 950         gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~A6XX_GMU_IRQ_MASK);
 951         enable_irq(gmu->gmu_irq);
 952
 953         /* Check to see if we are doing a cold or warm boot */
 954         status = gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) == 1 ?
 955                 GMU_WARM_BOOT : GMU_COLD_BOOT;
 956
 957         /*
 958          * Warm boot path does not work on newer GPUs
 959          * Presumably this is because icache/dcache regions must be restored
 960          */
 961         if (!gmu->legacy)
 962                 status = GMU_COLD_BOOT;
 963
 964         ret = a6xx_gmu_fw_start(gmu, status);
 965         if (ret)
 966                 goto out;
 967
 968         ret = a6xx_hfi_start(gmu, status);
 969         if (ret)
 970                 goto out;
 971
 972         /*
 973          * Turn on the GMU firmware fault interrupt after we know the boot
 974          * sequence is successful
 975          */
 976         gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0);
 977         gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~A6XX_HFI_IRQ_MASK);
 978         enable_irq(gmu->hfi_irq);
 979
 980         /* Set the GPU to the current freq */
 981         a6xx_gmu_set_initial_freq(gpu, gmu);
 982
 983 out:
 984         /* On failure, shut down the GMU to leave it in a good state */
 985         if (ret) {
 986                 disable_irq(gmu->gmu_irq);
 987                 a6xx_rpmh_stop(gmu);
 988                 pm_runtime_put(gmu->gxpd);
 989                 pm_runtime_put(gmu->dev);
 990         }
 991
 992         return ret;
 993 }
 994
 995 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu)
 996 {
 997         u32 reg;
 998
 999         if (!gmu->initialized)
1000                 return true;
1001
1002         reg = gmu_read(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS);
1003
1004         if (reg &  A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB)
1005                 return false;
1006
1007         return true;
1008 }
1009
1010 #define GBIF_CLIENT_HALT_MASK             BIT(0)
1011 #define GBIF_ARB_HALT_MASK                BIT(1)
1012
1013 static void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu)
1014 {
1015         struct msm_gpu *gpu = &adreno_gpu->base;
1016
1017         if (!a6xx_has_gbif(adreno_gpu)) {
1018                 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf);
1019                 spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) &
1020                                                                 0xf) == 0xf);
1021                 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0);
1022
1023                 return;
1024         }
1025
1026         /* Halt new client requests on GBIF */
1027         gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK);
1028         spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &
1029                         (GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK);
1030
1031         /* Halt all AXI requests on GBIF */
1032         gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK);
1033         spin_until((gpu_read(gpu,  REG_A6XX_GBIF_HALT_ACK) &
1034                         (GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK);
1035
1036         /* The GBIF halt needs to be explicitly cleared */
1037         gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0);
1038 }
1039
1040 /* Gracefully try to shut down the GMU and by extension the GPU */
1041 static void a6xx_gmu_shutdown(struct a6xx_gmu *gmu)
1042 {
1043         struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1044         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1045         u32 val;
1046
1047         /*
1048          * The GMU may still be in slumber unless the GPU started so check and
1049          * skip putting it back into slumber if so
1050          */
1051         val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE);
1052
1053         if (val != 0xf) {
1054                 int ret = a6xx_gmu_wait_for_idle(gmu);
1055
1056                 /* If the GMU isn't responding assume it is hung */
1057                 if (ret) {
1058                         a6xx_gmu_force_off(gmu);
1059                         return;
1060                 }
1061
1062                 a6xx_bus_clear_pending_transactions(adreno_gpu);
1063
1064                 /* tell the GMU we want to slumber */
1065                 a6xx_gmu_notify_slumber(gmu);
1066
1067                 ret = gmu_poll_timeout(gmu,
1068                         REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS, val,
1069                         !(val & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB),
1070                         100, 10000);
1071
1072                 /*
1073                  * Let the user know we failed to slumber but don't worry too
1074                  * much because we are powering down anyway
1075                  */
1076
1077                 if (ret)
1078                         DRM_DEV_ERROR(gmu->dev,
1079                                 "Unable to slumber GMU: status = 0%x/0%x\n",
1080                                 gmu_read(gmu,
1081                                         REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS),
1082                                 gmu_read(gmu,
1083                                         REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2));
1084         }
1085
1086         /* Turn off HFI */
1087         a6xx_hfi_stop(gmu);
1088
1089         /* Stop the interrupts and mask the hardware */
1090         a6xx_gmu_irq_disable(gmu);
1091
1092         /* Tell RPMh to power off the GPU */
1093         a6xx_rpmh_stop(gmu);
1094 }
1095
1096
1097 int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu)
1098 {
1099         struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1100         struct msm_gpu *gpu = &a6xx_gpu->base.base;
1101
1102         if (!pm_runtime_active(gmu->dev))
1103                 return 0;
1104
1105         /*
1106          * Force the GMU off if we detected a hang, otherwise try to shut it
1107          * down gracefully
1108          */
1109         if (gmu->hung)
1110                 a6xx_gmu_force_off(gmu);
1111         else
1112                 a6xx_gmu_shutdown(gmu);
1113
1114         /* Remove the bus vote */
1115         dev_pm_opp_set_opp(&gpu->pdev->dev, NULL);
1116
1117         /*
1118          * Make sure the GX domain is off before turning off the GMU (CX)
1119          * domain. Usually the GMU does this but only if the shutdown sequence
1120          * was successful
1121          */
1122         if (!IS_ERR_OR_NULL(gmu->gxpd))
1123                 pm_runtime_put_sync(gmu->gxpd);
1124
1125         clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks);
1126
1127         pm_runtime_put_sync(gmu->dev);
1128
1129         return 0;
1130 }
1131
1132 static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu)
1133 {
1134         msm_gem_kernel_put(gmu->hfi.obj, gmu->aspace);
1135         msm_gem_kernel_put(gmu->debug.obj, gmu->aspace);
1136         msm_gem_kernel_put(gmu->icache.obj, gmu->aspace);
1137         msm_gem_kernel_put(gmu->dcache.obj, gmu->aspace);
1138         msm_gem_kernel_put(gmu->dummy.obj, gmu->aspace);
1139         msm_gem_kernel_put(gmu->log.obj, gmu->aspace);
1140
1141         gmu->aspace->mmu->funcs->detach(gmu->aspace->mmu);
1142         msm_gem_address_space_put(gmu->aspace);
1143 }
1144
1145 static int a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo,
1146                 size_t size, u64 iova)
1147 {
1148         struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1149         struct drm_device *dev = a6xx_gpu->base.base.dev;
1150         uint32_t flags = MSM_BO_WC;
1151         u64 range_start, range_end;
1152         int ret;
1153
1154         size = PAGE_ALIGN(size);
1155         if (!iova) {
1156                 /* no fixed address - use GMU's uncached range */
1157                 range_start = 0x60000000 + PAGE_SIZE; /* skip dummy page */
1158                 range_end = 0x80000000;
1159         } else {
1160                 /* range for fixed address */
1161                 range_start = iova;
1162                 range_end = iova + size;
1163                 /* use IOMMU_PRIV for icache/dcache */
1164                 flags |= MSM_BO_MAP_PRIV;
1165         }
1166
1167         bo->obj = msm_gem_new(dev, size, flags);
1168         if (IS_ERR(bo->obj))
1169                 return PTR_ERR(bo->obj);
1170
1171         ret = msm_gem_get_and_pin_iova_range(bo->obj, gmu->aspace, &bo->iova,
1172                 range_start >> PAGE_SHIFT, range_end >> PAGE_SHIFT);
1173         if (ret) {
1174                 drm_gem_object_put(bo->obj);
1175                 return ret;
1176         }
1177
1178         bo->virt = msm_gem_get_vaddr(bo->obj);
1179         bo->size = size;
1180
1181         return 0;
1182 }
1183
1184 static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu)
1185 {
1186         struct iommu_domain *domain;
1187         struct msm_mmu *mmu;
1188
1189         domain = iommu_domain_alloc(&platform_bus_type);
1190         if (!domain)
1191                 return -ENODEV;
1192
1193         mmu = msm_iommu_new(gmu->dev, domain);
1194         gmu->aspace = msm_gem_address_space_create(mmu, "gmu", 0x0, 0x80000000);
1195         if (IS_ERR(gmu->aspace)) {
1196                 iommu_domain_free(domain);
1197                 return PTR_ERR(gmu->aspace);
1198         }
1199
1200         return 0;
1201 }
1202
1203 /* Return the 'arc-level' for the given frequency */
1204 static unsigned int a6xx_gmu_get_arc_level(struct device *dev,
1205                                            unsigned long freq)
1206 {
1207         struct dev_pm_opp *opp;
1208         unsigned int val;
1209
1210         if (!freq)
1211                 return 0;
1212
1213         opp = dev_pm_opp_find_freq_exact(dev, freq, true);
1214         if (IS_ERR(opp))
1215                 return 0;
1216
1217         val = dev_pm_opp_get_level(opp);
1218
1219         dev_pm_opp_put(opp);
1220
1221         return val;
1222 }
1223
1224 static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes,
1225                 unsigned long *freqs, int freqs_count, const char *id)
1226 {
1227         int i, j;
1228         const u16 *pri, *sec;
1229         size_t pri_count, sec_count;
1230
1231         pri = cmd_db_read_aux_data(id, &pri_count);
1232         if (IS_ERR(pri))
1233                 return PTR_ERR(pri);
1234         /*
1235          * The data comes back as an array of unsigned shorts so adjust the
1236          * count accordingly
1237          */
1238         pri_count >>= 1;
1239         if (!pri_count)
1240                 return -EINVAL;
1241
1242         sec = cmd_db_read_aux_data("mx.lvl", &sec_count);
1243         if (IS_ERR(sec))
1244                 return PTR_ERR(sec);
1245
1246         sec_count >>= 1;
1247         if (!sec_count)
1248                 return -EINVAL;
1249
1250         /* Construct a vote for each frequency */
1251         for (i = 0; i < freqs_count; i++) {
1252                 u8 pindex = 0, sindex = 0;
1253                 unsigned int level = a6xx_gmu_get_arc_level(dev, freqs[i]);
1254
1255                 /* Get the primary index that matches the arc level */
1256                 for (j = 0; j < pri_count; j++) {
1257                         if (pri[j] >= level) {
1258                                 pindex = j;
1259                                 break;
1260                         }
1261                 }
1262
1263                 if (j == pri_count) {
1264                         DRM_DEV_ERROR(dev,
1265                                       "Level %u not found in the RPMh list\n",
1266                                       level);
1267                         DRM_DEV_ERROR(dev, "Available levels:\n");
1268                         for (j = 0; j < pri_count; j++)
1269                                 DRM_DEV_ERROR(dev, "  %u\n", pri[j]);
1270
1271                         return -EINVAL;
1272                 }
1273
1274                 /*
1275                  * Look for a level in in the secondary list that matches. If
1276                  * nothing fits, use the maximum non zero vote
1277                  */
1278
1279                 for (j = 0; j < sec_count; j++) {
1280                         if (sec[j] >= level) {
1281                                 sindex = j;
1282                                 break;
1283                         } else if (sec[j]) {
1284                                 sindex = j;
1285                         }
1286                 }
1287
1288                 /* Construct the vote */
1289                 votes[i] = ((pri[pindex] & 0xffff) << 16) |
1290                         (sindex << 8) | pindex;
1291         }
1292
1293         return 0;
1294 }
1295
1296 /*
1297  * The GMU votes with the RPMh for itself and on behalf of the GPU but we need
1298  * to construct the list of votes on the CPU and send it over. Query the RPMh
1299  * voltage levels and build the votes
1300  */
1301
1302 static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu)
1303 {
1304         struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1305         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1306         struct msm_gpu *gpu = &adreno_gpu->base;
1307         int ret;
1308
1309         /* Build the GX votes */
1310         ret = a6xx_gmu_rpmh_arc_votes_init(&gpu->pdev->dev, gmu->gx_arc_votes,
1311                 gmu->gpu_freqs, gmu->nr_gpu_freqs, "gfx.lvl");
1312
1313         /* Build the CX votes */
1314         ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes,
1315                 gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl");
1316
1317         return ret;
1318 }
1319
1320 static int a6xx_gmu_build_freq_table(struct device *dev, unsigned long *freqs,
1321                 u32 size)
1322 {
1323         int count = dev_pm_opp_get_opp_count(dev);
1324         struct dev_pm_opp *opp;
1325         int i, index = 0;
1326         unsigned long freq = 1;
1327
1328         /*
1329          * The OPP table doesn't contain the "off" frequency level so we need to
1330          * add 1 to the table size to account for it
1331          */
1332
1333         if (WARN(count + 1 > size,
1334                 "The GMU frequency table is being truncated\n"))
1335                 count = size - 1;
1336
1337         /* Set the "off" frequency */
1338         freqs[index++] = 0;
1339
1340         for (i = 0; i < count; i++) {
1341                 opp = dev_pm_opp_find_freq_ceil(dev, &freq);
1342                 if (IS_ERR(opp))
1343                         break;
1344
1345                 dev_pm_opp_put(opp);
1346                 freqs[index++] = freq++;
1347         }
1348
1349         return index;
1350 }
1351
1352 static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu)
1353 {
1354         struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1355         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1356         struct msm_gpu *gpu = &adreno_gpu->base;
1357
1358         int ret = 0;
1359
1360         /*
1361          * The GMU handles its own frequency switching so build a list of
1362          * available frequencies to send during initialization
1363          */
1364         ret = devm_pm_opp_of_add_table(gmu->dev);
1365         if (ret) {
1366                 DRM_DEV_ERROR(gmu->dev, "Unable to set the OPP table for the GMU\n");
1367                 return ret;
1368         }
1369
1370         gmu->nr_gmu_freqs = a6xx_gmu_build_freq_table(gmu->dev,
1371                 gmu->gmu_freqs, ARRAY_SIZE(gmu->gmu_freqs));
1372
1373         /*
1374          * The GMU also handles GPU frequency switching so build a list
1375          * from the GPU OPP table
1376          */
1377         gmu->nr_gpu_freqs = a6xx_gmu_build_freq_table(&gpu->pdev->dev,
1378                 gmu->gpu_freqs, ARRAY_SIZE(gmu->gpu_freqs));
1379
1380         gmu->current_perf_index = gmu->nr_gpu_freqs - 1;
1381
1382         /* Build the list of RPMh votes that we'll send to the GMU */
1383         return a6xx_gmu_rpmh_votes_init(gmu);
1384 }
1385
1386 static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gmu)
1387 {
1388         int ret = devm_clk_bulk_get_all(gmu->dev, &gmu->clocks);
1389
1390         if (ret < 1)
1391                 return ret;
1392
1393         gmu->nr_clocks = ret;
1394
1395         gmu->core_clk = msm_clk_bulk_get_clock(gmu->clocks,
1396                 gmu->nr_clocks, "gmu");
1397
1398         gmu->hub_clk = msm_clk_bulk_get_clock(gmu->clocks,
1399                 gmu->nr_clocks, "hub");
1400
1401         return 0;
1402 }
1403
1404 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
1405                 const char *name)
1406 {
1407         void __iomem *ret;
1408         struct resource *res = platform_get_resource_byname(pdev,
1409                         IORESOURCE_MEM, name);
1410
1411         if (!res) {
1412                 DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name);
1413                 return ERR_PTR(-EINVAL);
1414         }
1415
1416         ret = ioremap(res->start, resource_size(res));
1417         if (!ret) {
1418                 DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name);
1419                 return ERR_PTR(-EINVAL);
1420         }
1421
1422         return ret;
1423 }
1424
1425 static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev,
1426                 const char *name, irq_handler_t handler)
1427 {
1428         int irq, ret;
1429
1430         irq = platform_get_irq_byname(pdev, name);
1431
1432         ret = request_irq(irq, handler, IRQF_TRIGGER_HIGH, name, gmu);
1433         if (ret) {
1434                 DRM_DEV_ERROR(&pdev->dev, "Unable to get interrupt %s %d\n",
1435                               name, ret);
1436                 return ret;
1437         }
1438
1439         disable_irq(irq);
1440
1441         return irq;
1442 }
1443
1444 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu)
1445 {
1446         struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1447         struct platform_device *pdev = to_platform_device(gmu->dev);
1448
1449         if (!gmu->initialized)
1450                 return;
1451
1452         pm_runtime_force_suspend(gmu->dev);
1453
1454         if (!IS_ERR_OR_NULL(gmu->gxpd)) {
1455                 pm_runtime_disable(gmu->gxpd);
1456                 dev_pm_domain_detach(gmu->gxpd, false);
1457         }
1458
1459         iounmap(gmu->mmio);
1460         if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
1461                 iounmap(gmu->rscc);
1462         gmu->mmio = NULL;
1463         gmu->rscc = NULL;
1464
1465         a6xx_gmu_memory_free(gmu);
1466
1467         free_irq(gmu->gmu_irq, gmu);
1468         free_irq(gmu->hfi_irq, gmu);
1469
1470         /* Drop reference taken in of_find_device_by_node */
1471         put_device(gmu->dev);
1472
1473         gmu->initialized = false;
1474 }
1475
1476 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
1477 {
1478         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1479         struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1480         struct platform_device *pdev = of_find_device_by_node(node);
1481         int ret;
1482
1483         if (!pdev)
1484                 return -ENODEV;
1485
1486         gmu->dev = &pdev->dev;
1487
1488         of_dma_configure(gmu->dev, node, true);
1489
1490         /* Fow now, don't do anything fancy until we get our feet under us */
1491         gmu->idle_level = GMU_IDLE_STATE_ACTIVE;
1492
1493         pm_runtime_enable(gmu->dev);
1494
1495         /* Get the list of clocks */
1496         ret = a6xx_gmu_clocks_probe(gmu);
1497         if (ret)
1498                 goto err_put_device;
1499
1500         ret = a6xx_gmu_memory_probe(gmu);
1501         if (ret)
1502                 goto err_put_device;
1503
1504
1505         /* A660 now requires handling "prealloc requests" in GMU firmware
1506          * For now just hardcode allocations based on the known firmware.
1507          * note: there is no indication that these correspond to "dummy" or
1508          * "debug" regions, but this "guess" allows reusing these BOs which
1509          * are otherwise unused by a660.
1510          */
1511         gmu->dummy.size = SZ_4K;
1512         if (adreno_is_a660_family(adreno_gpu)) {
1513                 ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_4K * 7, 0x60400000);
1514                 if (ret)
1515                         goto err_memory;
1516
1517                 gmu->dummy.size = SZ_8K;
1518         }
1519
1520         /* Allocate memory for the GMU dummy page */
1521         ret = a6xx_gmu_memory_alloc(gmu, &gmu->dummy, gmu->dummy.size, 0x60000000);
1522         if (ret)
1523                 goto err_memory;
1524
1525         if (adreno_is_a650_family(adreno_gpu)) {
1526                 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache,
1527                         SZ_16M - SZ_16K, 0x04000);
1528                 if (ret)
1529                         goto err_memory;
1530         } else if (adreno_is_a640(adreno_gpu) || adreno_is_a680(adreno_gpu)) {
1531                 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache,
1532                         SZ_256K - SZ_16K, 0x04000);
1533                 if (ret)
1534                         goto err_memory;
1535
1536                 ret = a6xx_gmu_memory_alloc(gmu, &gmu->dcache,
1537                         SZ_256K - SZ_16K, 0x44000);
1538                 if (ret)
1539                         goto err_memory;
1540         } else {
1541                 /* HFI v1, has sptprac */
1542                 gmu->legacy = true;
1543
1544                 /* Allocate memory for the GMU debug region */
1545                 ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_16K, 0);
1546                 if (ret)
1547                         goto err_memory;
1548         }
1549
1550         /* Allocate memory for for the HFI queues */
1551         ret = a6xx_gmu_memory_alloc(gmu, &gmu->hfi, SZ_16K, 0);
1552         if (ret)
1553                 goto err_memory;
1554
1555         /* Allocate memory for the GMU log region */
1556         ret = a6xx_gmu_memory_alloc(gmu, &gmu->log, SZ_4K, 0);
1557         if (ret)
1558                 goto err_memory;
1559
1560         /* Map the GMU registers */
1561         gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu");
1562         if (IS_ERR(gmu->mmio)) {
1563                 ret = PTR_ERR(gmu->mmio);
1564                 goto err_memory;
1565         }
1566
1567         if (adreno_is_a650_family(adreno_gpu)) {
1568                 gmu->rscc = a6xx_gmu_get_mmio(pdev, "rscc");
1569                 if (IS_ERR(gmu->rscc))
1570                         goto err_mmio;
1571         } else {
1572                 gmu->rscc = gmu->mmio + 0x23000;
1573         }
1574
1575         /* Get the HFI and GMU interrupts */
1576         gmu->hfi_irq = a6xx_gmu_get_irq(gmu, pdev, "hfi", a6xx_hfi_irq);
1577         gmu->gmu_irq = a6xx_gmu_get_irq(gmu, pdev, "gmu", a6xx_gmu_irq);
1578
1579         if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0)
1580                 goto err_mmio;
1581
1582         /*
1583          * Get a link to the GX power domain to reset the GPU in case of GMU
1584          * crash
1585          */
1586         gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx");
1587
1588         /* Get the power levels for the GMU and GPU */
1589         a6xx_gmu_pwrlevels_probe(gmu);
1590
1591         /* Set up the HFI queues */
1592         a6xx_hfi_init(gmu);
1593
1594         gmu->initialized = true;
1595
1596         return 0;
1597
1598 err_mmio:
1599         iounmap(gmu->mmio);
1600         if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
1601                 iounmap(gmu->rscc);
1602         free_irq(gmu->gmu_irq, gmu);
1603         free_irq(gmu->hfi_irq, gmu);
1604
1605         ret = -ENODEV;
1606
1607 err_memory:
1608         a6xx_gmu_memory_free(gmu);
1609 err_put_device:
1610         /* Drop reference taken in of_find_device_by_node */
1611         put_device(gmu->dev);
1612
1613         return ret;
1614 }