drivers/gpu/drm/mediatek/mtk_drm_drv.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015 MediaTek Inc.
   4  * Author: YT SHEN <yt.shen@mediatek.com>
   5  */
   6
   7 #include <linux/component.h>
   8 #include <linux/iommu.h>
   9 #include <linux/module.h>
  10 #include <linux/of_address.h>
  11 #include <linux/of_platform.h>
  12 #include <linux/pm_runtime.h>
  13 #include <linux/dma-mapping.h>
  14
  15 #include <drm/drm_atomic.h>
  16 #include <drm/drm_atomic_helper.h>
  17 #include <drm/drm_drv.h>
  18 #include <drm/drm_fb_helper.h>
  19 #include <drm/drm_fourcc.h>
  20 #include <drm/drm_gem.h>
  21 #include <drm/drm_gem_cma_helper.h>
  22 #include <drm/drm_gem_framebuffer_helper.h>
  23 #include <drm/drm_of.h>
  24 #include <drm/drm_probe_helper.h>
  25 #include <drm/drm_vblank.h>
  26
  27 #include "mtk_drm_crtc.h"
  28 #include "mtk_drm_ddp_comp.h"
  29 #include "mtk_drm_drv.h"
  30 #include "mtk_drm_gem.h"
  31
  32 #define DRIVER_NAME "mediatek"
  33 #define DRIVER_DESC "Mediatek SoC DRM"
  34 #define DRIVER_DATE "20150513"
  35 #define DRIVER_MAJOR 1
  36 #define DRIVER_MINOR 0
  37
  38 static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = {
  39         .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
  40 };
  41
  42 static struct drm_framebuffer *
  43 mtk_drm_mode_fb_create(struct drm_device *dev,
  44                        struct drm_file *file,
  45                        const struct drm_mode_fb_cmd2 *cmd)
  46 {
  47         const struct drm_format_info *info = drm_get_format_info(dev, cmd);
  48
  49         if (info->num_planes != 1)
  50                 return ERR_PTR(-EINVAL);
  51
  52         return drm_gem_fb_create(dev, file, cmd);
  53 }
  54
  55 static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = {
  56         .fb_create = mtk_drm_mode_fb_create,
  57         .atomic_check = drm_atomic_helper_check,
  58         .atomic_commit = drm_atomic_helper_commit,
  59 };
  60
  61 static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
  62         DDP_COMPONENT_OVL0,
  63         DDP_COMPONENT_RDMA0,
  64         DDP_COMPONENT_COLOR0,
  65         DDP_COMPONENT_BLS,
  66         DDP_COMPONENT_DSI0,
  67 };
  68
  69 static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
  70         DDP_COMPONENT_RDMA1,
  71         DDP_COMPONENT_DPI0,
  72 };
  73
  74 static const enum mtk_ddp_comp_id mt7623_mtk_ddp_main[] = {
  75         DDP_COMPONENT_OVL0,
  76         DDP_COMPONENT_RDMA0,
  77         DDP_COMPONENT_COLOR0,
  78         DDP_COMPONENT_BLS,
  79         DDP_COMPONENT_DPI0,
  80 };
  81
  82 static const enum mtk_ddp_comp_id mt7623_mtk_ddp_ext[] = {
  83         DDP_COMPONENT_RDMA1,
  84         DDP_COMPONENT_DSI0,
  85 };
  86
  87 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = {
  88         DDP_COMPONENT_OVL0,
  89         DDP_COMPONENT_COLOR0,
  90         DDP_COMPONENT_AAL0,
  91         DDP_COMPONENT_OD0,
  92         DDP_COMPONENT_RDMA0,
  93         DDP_COMPONENT_DPI0,
  94         DDP_COMPONENT_PWM0,
  95 };
  96
  97 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_ext[] = {
  98         DDP_COMPONENT_OVL1,
  99         DDP_COMPONENT_COLOR1,
 100         DDP_COMPONENT_AAL1,
 101         DDP_COMPONENT_OD1,
 102         DDP_COMPONENT_RDMA1,
 103         DDP_COMPONENT_DPI1,
 104         DDP_COMPONENT_PWM1,
 105 };
 106
 107 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = {
 108         DDP_COMPONENT_RDMA2,
 109         DDP_COMPONENT_DSI3,
 110         DDP_COMPONENT_PWM2,
 111 };
 112
 113 static enum mtk_ddp_comp_id mt8167_mtk_ddp_main[] = {
 114         DDP_COMPONENT_OVL0,
 115         DDP_COMPONENT_COLOR0,
 116         DDP_COMPONENT_CCORR,
 117         DDP_COMPONENT_AAL0,
 118         DDP_COMPONENT_GAMMA,
 119         DDP_COMPONENT_DITHER,
 120         DDP_COMPONENT_RDMA0,
 121         DDP_COMPONENT_DSI0,
 122 };
 123
 124 static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
 125         DDP_COMPONENT_OVL0,
 126         DDP_COMPONENT_COLOR0,
 127         DDP_COMPONENT_AAL0,
 128         DDP_COMPONENT_OD0,
 129         DDP_COMPONENT_RDMA0,
 130         DDP_COMPONENT_UFOE,
 131         DDP_COMPONENT_DSI0,
 132         DDP_COMPONENT_PWM0,
 133 };
 134
 135 static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = {
 136         DDP_COMPONENT_OVL1,
 137         DDP_COMPONENT_COLOR1,
 138         DDP_COMPONENT_GAMMA,
 139         DDP_COMPONENT_RDMA1,
 140         DDP_COMPONENT_DPI0,
 141 };
 142
 143 static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = {
 144         DDP_COMPONENT_OVL0,
 145         DDP_COMPONENT_OVL_2L0,
 146         DDP_COMPONENT_RDMA0,
 147         DDP_COMPONENT_COLOR0,
 148         DDP_COMPONENT_CCORR,
 149         DDP_COMPONENT_AAL0,
 150         DDP_COMPONENT_GAMMA,
 151         DDP_COMPONENT_DITHER,
 152         DDP_COMPONENT_DSI0,
 153 };
 154
 155 static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = {
 156         DDP_COMPONENT_OVL_2L1,
 157         DDP_COMPONENT_RDMA1,
 158         DDP_COMPONENT_DPI0,
 159 };
 160
 161 static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = {
 162         DDP_COMPONENT_OVL0,
 163         DDP_COMPONENT_OVL_2L0,
 164         DDP_COMPONENT_RDMA0,
 165         DDP_COMPONENT_COLOR0,
 166         DDP_COMPONENT_CCORR,
 167         DDP_COMPONENT_AAL0,
 168         DDP_COMPONENT_GAMMA,
 169         DDP_COMPONENT_POSTMASK0,
 170         DDP_COMPONENT_DITHER,
 171         DDP_COMPONENT_DSI0,
 172 };
 173
 174 static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = {
 175         DDP_COMPONENT_OVL_2L2,
 176         DDP_COMPONENT_RDMA4,
 177         DDP_COMPONENT_DPI0,
 178 };
 179
 180 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
 181         .main_path = mt2701_mtk_ddp_main,
 182         .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
 183         .ext_path = mt2701_mtk_ddp_ext,
 184         .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext),
 185         .shadow_register = true,
 186 };
 187
 188 static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
 189         .main_path = mt7623_mtk_ddp_main,
 190         .main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),
 191         .ext_path = mt7623_mtk_ddp_ext,
 192         .ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
 193         .shadow_register = true,
 194 };
 195
 196 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
 197         .main_path = mt2712_mtk_ddp_main,
 198         .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
 199         .ext_path = mt2712_mtk_ddp_ext,
 200         .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
 201         .third_path = mt2712_mtk_ddp_third,
 202         .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
 203 };
 204
 205 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
 206         .main_path = mt8167_mtk_ddp_main,
 207         .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
 208 };
 209
 210 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
 211         .main_path = mt8173_mtk_ddp_main,
 212         .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
 213         .ext_path = mt8173_mtk_ddp_ext,
 214         .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
 215 };
 216
 217 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 218         .main_path = mt8183_mtk_ddp_main,
 219         .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
 220         .ext_path = mt8183_mtk_ddp_ext,
 221         .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
 222 };
 223
 224 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
 225         .main_path = mt8192_mtk_ddp_main,
 226         .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
 227         .ext_path = mt8192_mtk_ddp_ext,
 228         .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
 229 };
 230
 231 static int mtk_drm_kms_init(struct drm_device *drm)
 232 {
 233         struct mtk_drm_private *private = drm->dev_private;
 234         struct platform_device *pdev;
 235         struct device_node *np;
 236         struct device *dma_dev;
 237         int ret;
 238
 239         if (drm_firmware_drivers_only())
 240                 return -ENODEV;
 241
 242         if (!iommu_present(&platform_bus_type))
 243                 return -EPROBE_DEFER;
 244
 245         pdev = of_find_device_by_node(private->mutex_node);
 246         if (!pdev) {
 247                 dev_err(drm->dev, "Waiting for disp-mutex device %pOF\n",
 248                         private->mutex_node);
 249                 of_node_put(private->mutex_node);
 250                 return -EPROBE_DEFER;
 251         }
 252         private->mutex_dev = &pdev->dev;
 253
 254         ret = drmm_mode_config_init(drm);
 255         if (ret)
 256                 goto put_mutex_dev;
 257
 258         drm->mode_config.min_width = 64;
 259         drm->mode_config.min_height = 64;
 260
 261         /*
 262          * set max width and height as default value(4096x4096).
 263          * this value would be used to check framebuffer size limitation
 264          * at drm_mode_addfb().
 265          */
 266         drm->mode_config.max_width = 4096;
 267         drm->mode_config.max_height = 4096;
 268         drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
 269         drm->mode_config.helper_private = &mtk_drm_mode_config_helpers;
 270
 271         ret = component_bind_all(drm->dev, drm);
 272         if (ret)
 273                 goto put_mutex_dev;
 274
 275         /*
 276          * We currently support two fixed data streams, each optional,
 277          * and each statically assigned to a crtc:
 278          * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
 279          */
 280         ret = mtk_drm_crtc_create(drm, private->data->main_path,
 281                                   private->data->main_len);
 282         if (ret < 0)
 283                 goto err_component_unbind;
 284         /* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */
 285         ret = mtk_drm_crtc_create(drm, private->data->ext_path,
 286                                   private->data->ext_len);
 287         if (ret < 0)
 288                 goto err_component_unbind;
 289
 290         ret = mtk_drm_crtc_create(drm, private->data->third_path,
 291                                   private->data->third_len);
 292         if (ret < 0)
 293                 goto err_component_unbind;
 294
 295         /* Use OVL device for all DMA memory allocations */
 296         np = private->comp_node[private->data->main_path[0]] ?:
 297              private->comp_node[private->data->ext_path[0]];
 298         pdev = of_find_device_by_node(np);
 299         if (!pdev) {
 300                 ret = -ENODEV;
 301                 dev_err(drm->dev, "Need at least one OVL device\n");
 302                 goto err_component_unbind;
 303         }
 304
 305         dma_dev = &pdev->dev;
 306         private->dma_dev = dma_dev;
 307
 308         /*
 309          * Configure the DMA segment size to make sure we get contiguous IOVA
 310          * when importing PRIME buffers.
 311          */
 312         ret = dma_set_max_seg_size(dma_dev, UINT_MAX);
 313         if (ret) {
 314                 dev_err(dma_dev, "Failed to set DMA segment size\n");
 315                 goto err_component_unbind;
 316         }
 317
 318         ret = drm_vblank_init(drm, MAX_CRTC);
 319         if (ret < 0)
 320                 goto err_component_unbind;
 321
 322         drm_kms_helper_poll_init(drm);
 323         drm_mode_config_reset(drm);
 324
 325         return 0;
 326
 327 err_component_unbind:
 328         component_unbind_all(drm->dev, drm);
 329 put_mutex_dev:
 330         put_device(private->mutex_dev);
 331         return ret;
 332 }
 333
 334 static void mtk_drm_kms_deinit(struct drm_device *drm)
 335 {
 336         drm_kms_helper_poll_fini(drm);
 337         drm_atomic_helper_shutdown(drm);
 338
 339         component_unbind_all(drm->dev, drm);
 340 }
 341
 342 DEFINE_DRM_GEM_FOPS(mtk_drm_fops);
 343
 344 /*
 345  * We need to override this because the device used to import the memory is
 346  * not dev->dev, as drm_gem_prime_import() expects.
 347  */
 348 static struct drm_gem_object *mtk_drm_gem_prime_import(struct drm_device *dev,
 349                                                        struct dma_buf *dma_buf)
 350 {
 351         struct mtk_drm_private *private = dev->dev_private;
 352
 353         return drm_gem_prime_import_dev(dev, dma_buf, private->dma_dev);
 354 }
 355
 356 static const struct drm_driver mtk_drm_driver = {
 357         .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
 358
 359         .dumb_create = mtk_drm_gem_dumb_create,
 360
 361         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
 362         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
 363         .gem_prime_import = mtk_drm_gem_prime_import,
 364         .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table,
 365         .gem_prime_mmap = drm_gem_prime_mmap,
 366         .fops = &mtk_drm_fops,
 367
 368         .name = DRIVER_NAME,
 369         .desc = DRIVER_DESC,
 370         .date = DRIVER_DATE,
 371         .major = DRIVER_MAJOR,
 372         .minor = DRIVER_MINOR,
 373 };
 374
 375 static int compare_of(struct device *dev, void *data)
 376 {
 377         return dev->of_node == data;
 378 }
 379
 380 static int mtk_drm_bind(struct device *dev)
 381 {
 382         struct mtk_drm_private *private = dev_get_drvdata(dev);
 383         struct drm_device *drm;
 384         int ret;
 385
 386         drm = drm_dev_alloc(&mtk_drm_driver, dev);
 387         if (IS_ERR(drm))
 388                 return PTR_ERR(drm);
 389
 390         drm->dev_private = private;
 391         private->drm = drm;
 392
 393         ret = mtk_drm_kms_init(drm);
 394         if (ret < 0)
 395                 goto err_free;
 396
 397         ret = drm_dev_register(drm, 0);
 398         if (ret < 0)
 399                 goto err_deinit;
 400
 401         drm_fbdev_generic_setup(drm, 32);
 402
 403         return 0;
 404
 405 err_deinit:
 406         mtk_drm_kms_deinit(drm);
 407 err_free:
 408         drm_dev_put(drm);
 409         return ret;
 410 }
 411
 412 static void mtk_drm_unbind(struct device *dev)
 413 {
 414         struct mtk_drm_private *private = dev_get_drvdata(dev);
 415
 416         drm_dev_unregister(private->drm);
 417         mtk_drm_kms_deinit(private->drm);
 418         drm_dev_put(private->drm);
 419         private->num_pipes = 0;
 420         private->drm = NULL;
 421 }
 422
 423 static const struct component_master_ops mtk_drm_ops = {
 424         .bind           = mtk_drm_bind,
 425         .unbind         = mtk_drm_unbind,
 426 };
 427
 428 static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 429         { .compatible = "mediatek,mt8167-disp-aal",
 430           .data = (void *)MTK_DISP_AAL},
 431         { .compatible = "mediatek,mt8173-disp-aal",
 432           .data = (void *)MTK_DISP_AAL},
 433         { .compatible = "mediatek,mt8183-disp-aal",
 434           .data = (void *)MTK_DISP_AAL},
 435         { .compatible = "mediatek,mt8192-disp-aal",
 436           .data = (void *)MTK_DISP_AAL},
 437         { .compatible = "mediatek,mt8167-disp-ccorr",
 438           .data = (void *)MTK_DISP_CCORR },
 439         { .compatible = "mediatek,mt8183-disp-ccorr",
 440           .data = (void *)MTK_DISP_CCORR },
 441         { .compatible = "mediatek,mt8192-disp-ccorr",
 442           .data = (void *)MTK_DISP_CCORR },
 443         { .compatible = "mediatek,mt2701-disp-color",
 444           .data = (void *)MTK_DISP_COLOR },
 445         { .compatible = "mediatek,mt8167-disp-color",
 446           .data = (void *)MTK_DISP_COLOR },
 447         { .compatible = "mediatek,mt8173-disp-color",
 448           .data = (void *)MTK_DISP_COLOR },
 449         { .compatible = "mediatek,mt8167-disp-dither",
 450           .data = (void *)MTK_DISP_DITHER },
 451         { .compatible = "mediatek,mt8183-disp-dither",
 452           .data = (void *)MTK_DISP_DITHER },
 453         { .compatible = "mediatek,mt8167-disp-gamma",
 454           .data = (void *)MTK_DISP_GAMMA, },
 455         { .compatible = "mediatek,mt8173-disp-gamma",
 456           .data = (void *)MTK_DISP_GAMMA, },
 457         { .compatible = "mediatek,mt8183-disp-gamma",
 458           .data = (void *)MTK_DISP_GAMMA, },
 459         { .compatible = "mediatek,mt2701-disp-mutex",
 460           .data = (void *)MTK_DISP_MUTEX },
 461         { .compatible = "mediatek,mt2712-disp-mutex",
 462           .data = (void *)MTK_DISP_MUTEX },
 463         { .compatible = "mediatek,mt8167-disp-mutex",
 464           .data = (void *)MTK_DISP_MUTEX },
 465         { .compatible = "mediatek,mt8173-disp-mutex",
 466           .data = (void *)MTK_DISP_MUTEX },
 467         { .compatible = "mediatek,mt8183-disp-mutex",
 468           .data = (void *)MTK_DISP_MUTEX },
 469         { .compatible = "mediatek,mt8192-disp-mutex",
 470           .data = (void *)MTK_DISP_MUTEX },
 471         { .compatible = "mediatek,mt8173-disp-od",
 472           .data = (void *)MTK_DISP_OD },
 473         { .compatible = "mediatek,mt2701-disp-ovl",
 474           .data = (void *)MTK_DISP_OVL },
 475         { .compatible = "mediatek,mt8167-disp-ovl",
 476           .data = (void *)MTK_DISP_OVL },
 477         { .compatible = "mediatek,mt8173-disp-ovl",
 478           .data = (void *)MTK_DISP_OVL },
 479         { .compatible = "mediatek,mt8183-disp-ovl",
 480           .data = (void *)MTK_DISP_OVL },
 481         { .compatible = "mediatek,mt8192-disp-ovl",
 482           .data = (void *)MTK_DISP_OVL },
 483         { .compatible = "mediatek,mt8183-disp-ovl-2l",
 484           .data = (void *)MTK_DISP_OVL_2L },
 485         { .compatible = "mediatek,mt8192-disp-ovl-2l",
 486           .data = (void *)MTK_DISP_OVL_2L },
 487         { .compatible = "mediatek,mt8192-disp-postmask",
 488           .data = (void *)MTK_DISP_POSTMASK },
 489         { .compatible = "mediatek,mt2701-disp-pwm",
 490           .data = (void *)MTK_DISP_BLS },
 491         { .compatible = "mediatek,mt8167-disp-pwm",
 492           .data = (void *)MTK_DISP_PWM },
 493         { .compatible = "mediatek,mt8173-disp-pwm",
 494           .data = (void *)MTK_DISP_PWM },
 495         { .compatible = "mediatek,mt2701-disp-rdma",
 496           .data = (void *)MTK_DISP_RDMA },
 497         { .compatible = "mediatek,mt8167-disp-rdma",
 498           .data = (void *)MTK_DISP_RDMA },
 499         { .compatible = "mediatek,mt8173-disp-rdma",
 500           .data = (void *)MTK_DISP_RDMA },
 501         { .compatible = "mediatek,mt8183-disp-rdma",
 502           .data = (void *)MTK_DISP_RDMA },
 503         { .compatible = "mediatek,mt8192-disp-rdma",
 504           .data = (void *)MTK_DISP_RDMA },
 505         { .compatible = "mediatek,mt8173-disp-ufoe",
 506           .data = (void *)MTK_DISP_UFOE },
 507         { .compatible = "mediatek,mt8173-disp-wdma",
 508           .data = (void *)MTK_DISP_WDMA },
 509         { .compatible = "mediatek,mt2701-dpi",
 510           .data = (void *)MTK_DPI },
 511         { .compatible = "mediatek,mt8167-dsi",
 512           .data = (void *)MTK_DSI },
 513         { .compatible = "mediatek,mt8173-dpi",
 514           .data = (void *)MTK_DPI },
 515         { .compatible = "mediatek,mt8183-dpi",
 516           .data = (void *)MTK_DPI },
 517         { .compatible = "mediatek,mt2701-dsi",
 518           .data = (void *)MTK_DSI },
 519         { .compatible = "mediatek,mt8173-dsi",
 520           .data = (void *)MTK_DSI },
 521         { .compatible = "mediatek,mt8183-dsi",
 522           .data = (void *)MTK_DSI },
 523         { }
 524 };
 525
 526 static const struct of_device_id mtk_drm_of_ids[] = {
 527         { .compatible = "mediatek,mt2701-mmsys",
 528           .data = &mt2701_mmsys_driver_data},
 529         { .compatible = "mediatek,mt7623-mmsys",
 530           .data = &mt7623_mmsys_driver_data},
 531         { .compatible = "mediatek,mt2712-mmsys",
 532           .data = &mt2712_mmsys_driver_data},
 533         { .compatible = "mediatek,mt8167-mmsys",
 534           .data = &mt8167_mmsys_driver_data},
 535         { .compatible = "mediatek,mt8173-mmsys",
 536           .data = &mt8173_mmsys_driver_data},
 537         { .compatible = "mediatek,mt8183-mmsys",
 538           .data = &mt8183_mmsys_driver_data},
 539         { .compatible = "mediatek,mt8192-mmsys",
 540           .data = &mt8192_mmsys_driver_data},
 541         { }
 542 };
 543 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
 544
 545 static int mtk_drm_probe(struct platform_device *pdev)
 546 {
 547         struct device *dev = &pdev->dev;
 548         struct device_node *phandle = dev->parent->of_node;
 549         const struct of_device_id *of_id;
 550         struct mtk_drm_private *private;
 551         struct device_node *node;
 552         struct component_match *match = NULL;
 553         int ret;
 554         int i;
 555
 556         private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
 557         if (!private)
 558                 return -ENOMEM;
 559
 560         private->mmsys_dev = dev->parent;
 561         if (!private->mmsys_dev) {
 562                 dev_err(dev, "Failed to get MMSYS device\n");
 563                 return -ENODEV;
 564         }
 565
 566         of_id = of_match_node(mtk_drm_of_ids, phandle);
 567         if (!of_id)
 568                 return -ENODEV;
 569
 570         private->data = of_id->data;
 571
 572         /* Iterate over sibling DISP function blocks */
 573         for_each_child_of_node(phandle->parent, node) {
 574                 const struct of_device_id *of_id;
 575                 enum mtk_ddp_comp_type comp_type;
 576                 int comp_id;
 577
 578                 of_id = of_match_node(mtk_ddp_comp_dt_ids, node);
 579                 if (!of_id)
 580                         continue;
 581
 582                 if (!of_device_is_available(node)) {
 583                         dev_dbg(dev, "Skipping disabled component %pOF\n",
 584                                 node);
 585                         continue;
 586                 }
 587
 588                 comp_type = (enum mtk_ddp_comp_type)of_id->data;
 589
 590                 if (comp_type == MTK_DISP_MUTEX) {
 591                         private->mutex_node = of_node_get(node);
 592                         continue;
 593                 }
 594
 595                 comp_id = mtk_ddp_comp_get_id(node, comp_type);
 596                 if (comp_id < 0) {
 597                         dev_warn(dev, "Skipping unknown component %pOF\n",
 598                                  node);
 599                         continue;
 600                 }
 601
 602                 private->comp_node[comp_id] = of_node_get(node);
 603
 604                 /*
 605                  * Currently only the AAL, CCORR, COLOR, GAMMA, OVL, RDMA, DSI, and DPI
 606                  * blocks have separate component platform drivers and initialize their own
 607                  * DDP component structure. The others are initialized here.
 608                  */
 609                 if (comp_type == MTK_DISP_AAL ||
 610                     comp_type == MTK_DISP_CCORR ||
 611                     comp_type == MTK_DISP_COLOR ||
 612                     comp_type == MTK_DISP_GAMMA ||
 613                     comp_type == MTK_DISP_OVL ||
 614                     comp_type == MTK_DISP_OVL_2L ||
 615                     comp_type == MTK_DISP_RDMA ||
 616                     comp_type == MTK_DPI ||
 617                     comp_type == MTK_DSI) {
 618                         dev_info(dev, "Adding component match for %pOF\n",
 619                                  node);
 620                         drm_of_component_match_add(dev, &match, compare_of,
 621                                                    node);
 622                 }
 623
 624                 ret = mtk_ddp_comp_init(node, &private->ddp_comp[comp_id], comp_id);
 625                 if (ret) {
 626                         of_node_put(node);
 627                         goto err_node;
 628                 }
 629         }
 630
 631         if (!private->mutex_node) {
 632                 dev_err(dev, "Failed to find disp-mutex node\n");
 633                 ret = -ENODEV;
 634                 goto err_node;
 635         }
 636
 637         pm_runtime_enable(dev);
 638
 639         platform_set_drvdata(pdev, private);
 640
 641         ret = component_master_add_with_match(dev, &mtk_drm_ops, match);
 642         if (ret)
 643                 goto err_pm;
 644
 645         return 0;
 646
 647 err_pm:
 648         pm_runtime_disable(dev);
 649 err_node:
 650         of_node_put(private->mutex_node);
 651         for (i = 0; i < DDP_COMPONENT_ID_MAX; i++) {
 652                 of_node_put(private->comp_node[i]);
 653                 if (private->ddp_comp[i].larb_dev)
 654                         put_device(private->ddp_comp[i].larb_dev);
 655         }
 656         return ret;
 657 }
 658
 659 static int mtk_drm_remove(struct platform_device *pdev)
 660 {
 661         struct mtk_drm_private *private = platform_get_drvdata(pdev);
 662         int i;
 663
 664         component_master_del(&pdev->dev, &mtk_drm_ops);
 665         pm_runtime_disable(&pdev->dev);
 666         of_node_put(private->mutex_node);
 667         for (i = 0; i < DDP_COMPONENT_ID_MAX; i++)
 668                 of_node_put(private->comp_node[i]);
 669
 670         return 0;
 671 }
 672
 673 #ifdef CONFIG_PM_SLEEP
 674 static int mtk_drm_sys_suspend(struct device *dev)
 675 {
 676         struct mtk_drm_private *private = dev_get_drvdata(dev);
 677         struct drm_device *drm = private->drm;
 678         int ret;
 679
 680         ret = drm_mode_config_helper_suspend(drm);
 681
 682         return ret;
 683 }
 684
 685 static int mtk_drm_sys_resume(struct device *dev)
 686 {
 687         struct mtk_drm_private *private = dev_get_drvdata(dev);
 688         struct drm_device *drm = private->drm;
 689         int ret;
 690
 691         ret = drm_mode_config_helper_resume(drm);
 692
 693         return ret;
 694 }
 695 #endif
 696
 697 static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend,
 698                          mtk_drm_sys_resume);
 699
 700 static struct platform_driver mtk_drm_platform_driver = {
 701         .probe  = mtk_drm_probe,
 702         .remove = mtk_drm_remove,
 703         .driver = {
 704                 .name   = "mediatek-drm",
 705                 .pm     = &mtk_drm_pm_ops,
 706         },
 707 };
 708
 709 static struct platform_driver * const mtk_drm_drivers[] = {
 710         &mtk_disp_aal_driver,
 711         &mtk_disp_ccorr_driver,
 712         &mtk_disp_color_driver,
 713         &mtk_disp_gamma_driver,
 714         &mtk_disp_ovl_driver,
 715         &mtk_disp_rdma_driver,
 716         &mtk_dpi_driver,
 717         &mtk_drm_platform_driver,
 718         &mtk_dsi_driver,
 719 };
 720
 721 static int __init mtk_drm_init(void)
 722 {
 723         return platform_register_drivers(mtk_drm_drivers,
 724                                          ARRAY_SIZE(mtk_drm_drivers));
 725 }
 726
 727 static void __exit mtk_drm_exit(void)
 728 {
 729         platform_unregister_drivers(mtk_drm_drivers,
 730                                     ARRAY_SIZE(mtk_drm_drivers));
 731 }
 732
 733 module_init(mtk_drm_init);
 734 module_exit(mtk_drm_exit);
 735
 736 MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>");
 737 MODULE_DESCRIPTION("Mediatek SoC DRM driver");
 738 MODULE_LICENSE("GPL v2");