drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015 MediaTek Inc.
   4  * Authors:
   5  *      YT Shen <yt.shen@mediatek.com>
   6  *      CK Hu <ck.hu@mediatek.com>
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/of.h>
  11 #include <linux/of_address.h>
  12 #include <linux/of_platform.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/soc/mediatek/mtk-cmdq.h>
  15 #include <drm/drm_print.h>
  16
  17 #include "mtk_disp_drv.h"
  18 #include "mtk_drm_drv.h"
  19 #include "mtk_drm_plane.h"
  20 #include "mtk_drm_ddp_comp.h"
  21 #include "mtk_drm_crtc.h"
  22
  23 #define DISP_OD_EN                              0x0000
  24 #define DISP_OD_INTEN                           0x0008
  25 #define DISP_OD_INTSTA                          0x000c
  26 #define DISP_OD_CFG                             0x0020
  27 #define DISP_OD_SIZE                            0x0030
  28 #define DISP_DITHER_5                           0x0114
  29 #define DISP_DITHER_7                           0x011c
  30 #define DISP_DITHER_15                          0x013c
  31 #define DISP_DITHER_16                          0x0140
  32
  33 #define DISP_REG_UFO_START                      0x0000
  34
  35 #define DISP_AAL_EN                             0x0000
  36 #define DISP_AAL_SIZE                           0x0030
  37
  38 #define DISP_DITHER_EN                          0x0000
  39 #define DITHER_EN                               BIT(0)
  40 #define DISP_DITHER_CFG                         0x0020
  41 #define DITHER_RELAY_MODE                       BIT(0)
  42 #define DITHER_ENGINE_EN                        BIT(1)
  43 #define DISP_DITHER_SIZE                        0x0030
  44
  45 #define LUT_10BIT_MASK                          0x03ff
  46
  47 #define OD_RELAYMODE                            BIT(0)
  48
  49 #define UFO_BYPASS                              BIT(2)
  50
  51 #define AAL_EN                                  BIT(0)
  52
  53 #define DISP_DITHERING                          BIT(2)
  54 #define DITHER_LSB_ERR_SHIFT_R(x)               (((x) & 0x7) << 28)
  55 #define DITHER_OVFLW_BIT_R(x)                   (((x) & 0x7) << 24)
  56 #define DITHER_ADD_LSHIFT_R(x)                  (((x) & 0x7) << 20)
  57 #define DITHER_ADD_RSHIFT_R(x)                  (((x) & 0x7) << 16)
  58 #define DITHER_NEW_BIT_MODE                     BIT(0)
  59 #define DITHER_LSB_ERR_SHIFT_B(x)               (((x) & 0x7) << 28)
  60 #define DITHER_OVFLW_BIT_B(x)                   (((x) & 0x7) << 24)
  61 #define DITHER_ADD_LSHIFT_B(x)                  (((x) & 0x7) << 20)
  62 #define DITHER_ADD_RSHIFT_B(x)                  (((x) & 0x7) << 16)
  63 #define DITHER_LSB_ERR_SHIFT_G(x)               (((x) & 0x7) << 12)
  64 #define DITHER_OVFLW_BIT_G(x)                   (((x) & 0x7) << 8)
  65 #define DITHER_ADD_LSHIFT_G(x)                  (((x) & 0x7) << 4)
  66 #define DITHER_ADD_RSHIFT_G(x)                  (((x) & 0x7) << 0)
  67
  68 struct mtk_ddp_comp_dev {
  69         struct clk *clk;
  70         void __iomem *regs;
  71         struct cmdq_client_reg cmdq_reg;
  72 };
  73
  74 void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,
  75                    struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
  76                    unsigned int offset)
  77 {
  78 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
  79         if (cmdq_pkt)
  80                 cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
  81                                cmdq_reg->offset + offset, value);
  82         else
  83 #endif
  84                 writel(value, regs + offset);
  85 }
  86
  87 void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value,
  88                            struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
  89                            unsigned int offset)
  90 {
  91 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
  92         if (cmdq_pkt)
  93                 cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
  94                                cmdq_reg->offset + offset, value);
  95         else
  96 #endif
  97                 writel_relaxed(value, regs + offset);
  98 }
  99
 100 void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,
 101                         struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
 102                         unsigned int offset, unsigned int mask)
 103 {
 104 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 105         if (cmdq_pkt) {
 106                 cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys,
 107                                     cmdq_reg->offset + offset, value, mask);
 108         } else {
 109 #endif
 110                 u32 tmp = readl(regs + offset);
 111
 112                 tmp = (tmp & ~mask) | (value & mask);
 113                 writel(tmp, regs + offset);
 114 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 115         }
 116 #endif
 117 }
 118
 119 static int mtk_ddp_clk_enable(struct device *dev)
 120 {
 121         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 122
 123         return clk_prepare_enable(priv->clk);
 124 }
 125
 126 static void mtk_ddp_clk_disable(struct device *dev)
 127 {
 128         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 129
 130         clk_disable_unprepare(priv->clk);
 131 }
 132
 133 void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
 134                            unsigned int bpc, unsigned int cfg,
 135                            unsigned int dither_en, struct cmdq_pkt *cmdq_pkt)
 136 {
 137         /* If bpc equal to 0, the dithering function didn't be enabled */
 138         if (bpc == 0)
 139                 return;
 140
 141         if (bpc >= MTK_MIN_BPC) {
 142                 mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_5);
 143                 mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_7);
 144                 mtk_ddp_write(cmdq_pkt,
 145                               DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
 146                               DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
 147                               DITHER_NEW_BIT_MODE,
 148                               cmdq_reg, regs, DISP_DITHER_15);
 149                 mtk_ddp_write(cmdq_pkt,
 150                               DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
 151                               DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
 152                               DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
 153                               DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
 154                               cmdq_reg, regs, DISP_DITHER_16);
 155                 mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs, cfg);
 156         }
 157 }
 158
 159 static void mtk_dither_set(struct device *dev, unsigned int bpc,
 160                     unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
 161 {
 162         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 163
 164         mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, cfg,
 165                               DISP_DITHERING, cmdq_pkt);
 166 }
 167
 168 static void mtk_od_config(struct device *dev, unsigned int w,
 169                           unsigned int h, unsigned int vrefresh,
 170                           unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
 171 {
 172         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 173
 174         mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_OD_SIZE);
 175         mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_OD_CFG);
 176         mtk_dither_set(dev, bpc, DISP_OD_CFG, cmdq_pkt);
 177 }
 178
 179 static void mtk_od_start(struct device *dev)
 180 {
 181         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 182
 183         writel(1, priv->regs + DISP_OD_EN);
 184 }
 185
 186 static void mtk_ufoe_start(struct device *dev)
 187 {
 188         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 189
 190         writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
 191 }
 192
 193 static void mtk_aal_config(struct device *dev, unsigned int w,
 194                            unsigned int h, unsigned int vrefresh,
 195                            unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
 196 {
 197         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 198
 199         mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_AAL_SIZE);
 200 }
 201
 202 static void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state)
 203 {
 204         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 205
 206         mtk_gamma_set_common(priv->regs, state);
 207 }
 208
 209 static void mtk_aal_start(struct device *dev)
 210 {
 211         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 212
 213         writel(AAL_EN, priv->regs + DISP_AAL_EN);
 214 }
 215
 216 static void mtk_aal_stop(struct device *dev)
 217 {
 218         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 219
 220         writel_relaxed(0x0, priv->regs + DISP_AAL_EN);
 221 }
 222
 223 static void mtk_dither_config(struct device *dev, unsigned int w,
 224                               unsigned int h, unsigned int vrefresh,
 225                               unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
 226 {
 227         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 228
 229         mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE);
 230         mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);
 231         mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_DITHER_CFG,
 232                               DITHER_ENGINE_EN, cmdq_pkt);
 233 }
 234
 235 static void mtk_dither_start(struct device *dev)
 236 {
 237         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 238
 239         writel(DITHER_EN, priv->regs + DISP_DITHER_EN);
 240 }
 241
 242 static void mtk_dither_stop(struct device *dev)
 243 {
 244         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 245
 246         writel_relaxed(0x0, priv->regs + DISP_DITHER_EN);
 247 }
 248
 249 static const struct mtk_ddp_comp_funcs ddp_aal = {
 250         .clk_enable = mtk_ddp_clk_enable,
 251         .clk_disable = mtk_ddp_clk_disable,
 252         .gamma_set = mtk_aal_gamma_set,
 253         .config = mtk_aal_config,
 254         .start = mtk_aal_start,
 255         .stop = mtk_aal_stop,
 256 };
 257
 258 static const struct mtk_ddp_comp_funcs ddp_ccorr = {
 259         .clk_enable = mtk_ccorr_clk_enable,
 260         .clk_disable = mtk_ccorr_clk_disable,
 261         .config = mtk_ccorr_config,
 262         .start = mtk_ccorr_start,
 263         .stop = mtk_ccorr_stop,
 264         .ctm_set = mtk_ccorr_ctm_set,
 265 };
 266
 267 static const struct mtk_ddp_comp_funcs ddp_color = {
 268         .clk_enable = mtk_color_clk_enable,
 269         .clk_disable = mtk_color_clk_disable,
 270         .config = mtk_color_config,
 271         .start = mtk_color_start,
 272 };
 273
 274 static const struct mtk_ddp_comp_funcs ddp_dither = {
 275         .clk_enable = mtk_ddp_clk_enable,
 276         .clk_disable = mtk_ddp_clk_disable,
 277         .config = mtk_dither_config,
 278         .start = mtk_dither_start,
 279         .stop = mtk_dither_stop,
 280 };
 281
 282 static const struct mtk_ddp_comp_funcs ddp_dpi = {
 283         .start = mtk_dpi_start,
 284         .stop = mtk_dpi_stop,
 285 };
 286
 287 static const struct mtk_ddp_comp_funcs ddp_dsi = {
 288         .start = mtk_dsi_ddp_start,
 289         .stop = mtk_dsi_ddp_stop,
 290 };
 291
 292 static const struct mtk_ddp_comp_funcs ddp_gamma = {
 293         .clk_enable = mtk_gamma_clk_enable,
 294         .clk_disable = mtk_gamma_clk_disable,
 295         .gamma_set = mtk_gamma_set,
 296         .config = mtk_gamma_config,
 297         .start = mtk_gamma_start,
 298         .stop = mtk_gamma_stop,
 299 };
 300
 301 static const struct mtk_ddp_comp_funcs ddp_od = {
 302         .clk_enable = mtk_ddp_clk_enable,
 303         .clk_disable = mtk_ddp_clk_disable,
 304         .config = mtk_od_config,
 305         .start = mtk_od_start,
 306 };
 307
 308 static const struct mtk_ddp_comp_funcs ddp_ovl = {
 309         .clk_enable = mtk_ovl_clk_enable,
 310         .clk_disable = mtk_ovl_clk_disable,
 311         .config = mtk_ovl_config,
 312         .start = mtk_ovl_start,
 313         .stop = mtk_ovl_stop,
 314         .enable_vblank = mtk_ovl_enable_vblank,
 315         .disable_vblank = mtk_ovl_disable_vblank,
 316         .supported_rotations = mtk_ovl_supported_rotations,
 317         .layer_nr = mtk_ovl_layer_nr,
 318         .layer_check = mtk_ovl_layer_check,
 319         .layer_config = mtk_ovl_layer_config,
 320         .bgclr_in_on = mtk_ovl_bgclr_in_on,
 321         .bgclr_in_off = mtk_ovl_bgclr_in_off,
 322 };
 323
 324 static const struct mtk_ddp_comp_funcs ddp_rdma = {
 325         .clk_enable = mtk_rdma_clk_enable,
 326         .clk_disable = mtk_rdma_clk_disable,
 327         .config = mtk_rdma_config,
 328         .start = mtk_rdma_start,
 329         .stop = mtk_rdma_stop,
 330         .enable_vblank = mtk_rdma_enable_vblank,
 331         .disable_vblank = mtk_rdma_disable_vblank,
 332         .layer_nr = mtk_rdma_layer_nr,
 333         .layer_config = mtk_rdma_layer_config,
 334 };
 335
 336 static const struct mtk_ddp_comp_funcs ddp_ufoe = {
 337         .clk_enable = mtk_ddp_clk_enable,
 338         .clk_disable = mtk_ddp_clk_disable,
 339         .start = mtk_ufoe_start,
 340 };
 341
 342 static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
 343         [MTK_DISP_OVL] = "ovl",
 344         [MTK_DISP_OVL_2L] = "ovl-2l",
 345         [MTK_DISP_RDMA] = "rdma",
 346         [MTK_DISP_WDMA] = "wdma",
 347         [MTK_DISP_COLOR] = "color",
 348         [MTK_DISP_CCORR] = "ccorr",
 349         [MTK_DISP_AAL] = "aal",
 350         [MTK_DISP_GAMMA] = "gamma",
 351         [MTK_DISP_DITHER] = "dither",
 352         [MTK_DISP_UFOE] = "ufoe",
 353         [MTK_DSI] = "dsi",
 354         [MTK_DPI] = "dpi",
 355         [MTK_DISP_PWM] = "pwm",
 356         [MTK_DISP_MUTEX] = "mutex",
 357         [MTK_DISP_OD] = "od",
 358         [MTK_DISP_BLS] = "bls",
 359 };
 360
 361 struct mtk_ddp_comp_match {
 362         enum mtk_ddp_comp_type type;
 363         int alias_id;
 364         const struct mtk_ddp_comp_funcs *funcs;
 365 };
 366
 367 static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
 368         [DDP_COMPONENT_AAL0]    = { MTK_DISP_AAL,       0, &ddp_aal },
 369         [DDP_COMPONENT_AAL1]    = { MTK_DISP_AAL,       1, &ddp_aal },
 370         [DDP_COMPONENT_BLS]     = { MTK_DISP_BLS,       0, NULL },
 371         [DDP_COMPONENT_CCORR]   = { MTK_DISP_CCORR,     0, &ddp_ccorr },
 372         [DDP_COMPONENT_COLOR0]  = { MTK_DISP_COLOR,     0, &ddp_color },
 373         [DDP_COMPONENT_COLOR1]  = { MTK_DISP_COLOR,     1, &ddp_color },
 374         [DDP_COMPONENT_DITHER]  = { MTK_DISP_DITHER,    0, &ddp_dither },
 375         [DDP_COMPONENT_DPI0]    = { MTK_DPI,            0, &ddp_dpi },
 376         [DDP_COMPONENT_DPI1]    = { MTK_DPI,            1, &ddp_dpi },
 377         [DDP_COMPONENT_DSI0]    = { MTK_DSI,            0, &ddp_dsi },
 378         [DDP_COMPONENT_DSI1]    = { MTK_DSI,            1, &ddp_dsi },
 379         [DDP_COMPONENT_DSI2]    = { MTK_DSI,            2, &ddp_dsi },
 380         [DDP_COMPONENT_DSI3]    = { MTK_DSI,            3, &ddp_dsi },
 381         [DDP_COMPONENT_GAMMA]   = { MTK_DISP_GAMMA,     0, &ddp_gamma },
 382         [DDP_COMPONENT_OD0]     = { MTK_DISP_OD,        0, &ddp_od },
 383         [DDP_COMPONENT_OD1]     = { MTK_DISP_OD,        1, &ddp_od },
 384         [DDP_COMPONENT_OVL0]    = { MTK_DISP_OVL,       0, &ddp_ovl },
 385         [DDP_COMPONENT_OVL1]    = { MTK_DISP_OVL,       1, &ddp_ovl },
 386         [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L,    0, &ddp_ovl },
 387         [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L,    1, &ddp_ovl },
 388         [DDP_COMPONENT_PWM0]    = { MTK_DISP_PWM,       0, NULL },
 389         [DDP_COMPONENT_PWM1]    = { MTK_DISP_PWM,       1, NULL },
 390         [DDP_COMPONENT_PWM2]    = { MTK_DISP_PWM,       2, NULL },
 391         [DDP_COMPONENT_RDMA0]   = { MTK_DISP_RDMA,      0, &ddp_rdma },
 392         [DDP_COMPONENT_RDMA1]   = { MTK_DISP_RDMA,      1, &ddp_rdma },
 393         [DDP_COMPONENT_RDMA2]   = { MTK_DISP_RDMA,      2, &ddp_rdma },
 394         [DDP_COMPONENT_UFOE]    = { MTK_DISP_UFOE,      0, &ddp_ufoe },
 395         [DDP_COMPONENT_WDMA0]   = { MTK_DISP_WDMA,      0, NULL },
 396         [DDP_COMPONENT_WDMA1]   = { MTK_DISP_WDMA,      1, NULL },
 397 };
 398
 399 static bool mtk_drm_find_comp_in_ddp(struct device *dev,
 400                                      const enum mtk_ddp_comp_id *path,
 401                                      unsigned int path_len,
 402                                      struct mtk_ddp_comp *ddp_comp)
 403 {
 404         unsigned int i;
 405
 406         if (path == NULL)
 407                 return false;
 408
 409         for (i = 0U; i < path_len; i++)
 410                 if (dev == ddp_comp[path[i]].dev)
 411                         return true;
 412
 413         return false;
 414 }
 415
 416 int mtk_ddp_comp_get_id(struct device_node *node,
 417                         enum mtk_ddp_comp_type comp_type)
 418 {
 419         int id = of_alias_get_id(node, mtk_ddp_comp_stem[comp_type]);
 420         int i;
 421
 422         for (i = 0; i < ARRAY_SIZE(mtk_ddp_matches); i++) {
 423                 if (comp_type == mtk_ddp_matches[i].type &&
 424                     (id < 0 || id == mtk_ddp_matches[i].alias_id))
 425                         return i;
 426         }
 427
 428         return -EINVAL;
 429 }
 430
 431 unsigned int mtk_drm_find_possible_crtc_by_comp(struct drm_device *drm,
 432                                                 struct device *dev)
 433 {
 434         struct mtk_drm_private *private = drm->dev_private;
 435         unsigned int ret = 0;
 436
 437         if (mtk_drm_find_comp_in_ddp(dev, private->data->main_path, private->data->main_len,
 438                                      private->ddp_comp))
 439                 ret = BIT(0);
 440         else if (mtk_drm_find_comp_in_ddp(dev, private->data->ext_path,
 441                                           private->data->ext_len, private->ddp_comp))
 442                 ret = BIT(1);
 443         else if (mtk_drm_find_comp_in_ddp(dev, private->data->third_path,
 444                                           private->data->third_len, private->ddp_comp))
 445                 ret = BIT(2);
 446         else
 447                 DRM_INFO("Failed to find comp in ddp table\n");
 448
 449         return ret;
 450 }
 451
 452 static int mtk_ddp_get_larb_dev(struct device_node *node, struct mtk_ddp_comp *comp,
 453                                 struct device *dev)
 454 {
 455         struct device_node *larb_node;
 456         struct platform_device *larb_pdev;
 457
 458         larb_node = of_parse_phandle(node, "mediatek,larb", 0);
 459         if (!larb_node) {
 460                 dev_err(dev, "Missing mediadek,larb phandle in %pOF node\n", node);
 461                 return -EINVAL;
 462         }
 463
 464         larb_pdev = of_find_device_by_node(larb_node);
 465         if (!larb_pdev) {
 466                 dev_warn(dev, "Waiting for larb device %pOF\n", larb_node);
 467                 of_node_put(larb_node);
 468                 return -EPROBE_DEFER;
 469         }
 470         of_node_put(larb_node);
 471         comp->larb_dev = &larb_pdev->dev;
 472
 473         return 0;
 474 }
 475
 476 int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
 477                       enum mtk_ddp_comp_id comp_id)
 478 {
 479         struct platform_device *comp_pdev;
 480         enum mtk_ddp_comp_type type;
 481         struct mtk_ddp_comp_dev *priv;
 482         int ret;
 483
 484         if (comp_id < 0 || comp_id >= DDP_COMPONENT_ID_MAX)
 485                 return -EINVAL;
 486
 487         type = mtk_ddp_matches[comp_id].type;
 488
 489         comp->id = comp_id;
 490         comp->funcs = mtk_ddp_matches[comp_id].funcs;
 491         comp_pdev = of_find_device_by_node(node);
 492         if (!comp_pdev) {
 493                 DRM_INFO("Waiting for device %s\n", node->full_name);
 494                 return -EPROBE_DEFER;
 495         }
 496         comp->dev = &comp_pdev->dev;
 497
 498         /* Only DMA capable components need the LARB property */
 499         if (type == MTK_DISP_OVL ||
 500             type == MTK_DISP_OVL_2L ||
 501             type == MTK_DISP_RDMA ||
 502             type == MTK_DISP_WDMA) {
 503                 ret = mtk_ddp_get_larb_dev(node, comp, comp->dev);
 504                 if (ret)
 505                         return ret;
 506         }
 507
 508         if (type == MTK_DISP_BLS ||
 509             type == MTK_DISP_CCORR ||
 510             type == MTK_DISP_COLOR ||
 511             type == MTK_DISP_GAMMA ||
 512             type == MTK_DPI ||
 513             type == MTK_DSI ||
 514             type == MTK_DISP_OVL ||
 515             type == MTK_DISP_OVL_2L ||
 516             type == MTK_DISP_PWM ||
 517             type == MTK_DISP_RDMA)
 518                 return 0;
 519
 520         priv = devm_kzalloc(comp->dev, sizeof(*priv), GFP_KERNEL);
 521         if (!priv)
 522                 return -ENOMEM;
 523
 524         priv->regs = of_iomap(node, 0);
 525         priv->clk = of_clk_get(node, 0);
 526         if (IS_ERR(priv->clk))
 527                 return PTR_ERR(priv->clk);
 528
 529 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 530         ret = cmdq_dev_get_client_reg(comp->dev, &priv->cmdq_reg, 0);
 531         if (ret)
 532                 dev_dbg(comp->dev, "get mediatek,gce-client-reg fail!\n");
 533 #endif
 534
 535         platform_set_drvdata(comp_pdev, priv);
 536
 537         return 0;
 538 }