drivers/gpu/drm/mediatek/mtk_drm_crtc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015 MediaTek Inc.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/pm_runtime.h>
   8 #include <linux/soc/mediatek/mtk-cmdq.h>
   9 #include <linux/soc/mediatek/mtk-mmsys.h>
  10 #include <linux/soc/mediatek/mtk-mutex.h>
  11
  12 #include <asm/barrier.h>
  13 #include <soc/mediatek/smi.h>
  14
  15 #include <drm/drm_atomic.h>
  16 #include <drm/drm_atomic_helper.h>
  17 #include <drm/drm_plane_helper.h>
  18 #include <drm/drm_probe_helper.h>
  19 #include <drm/drm_vblank.h>
  20
  21 #include "mtk_drm_drv.h"
  22 #include "mtk_drm_crtc.h"
  23 #include "mtk_drm_ddp_comp.h"
  24 #include "mtk_drm_gem.h"
  25 #include "mtk_drm_plane.h"
  26
  27 /*
  28  * struct mtk_drm_crtc - MediaTek specific crtc structure.
  29  * @base: crtc object.
  30  * @enabled: records whether crtc_enable succeeded
  31  * @planes: array of 4 drm_plane structures, one for each overlay plane
  32  * @pending_planes: whether any plane has pending changes to be applied
  33  * @mmsys_dev: pointer to the mmsys device for configuration registers
  34  * @mutex: handle to one of the ten disp_mutex streams
  35  * @ddp_comp_nr: number of components in ddp_comp
  36  * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc
  37  *
  38  * TODO: Needs update: this header is missing a bunch of member descriptions.
  39  */
  40 struct mtk_drm_crtc {
  41         struct drm_crtc                 base;
  42         bool                            enabled;
  43
  44         bool                            pending_needs_vblank;
  45         struct drm_pending_vblank_event *event;
  46
  47         struct drm_plane                *planes;
  48         unsigned int                    layer_nr;
  49         bool                            pending_planes;
  50         bool                            pending_async_planes;
  51
  52 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
  53         struct cmdq_client              *cmdq_client;
  54         u32                             cmdq_event;
  55 #endif
  56
  57         struct device                   *mmsys_dev;
  58         struct mtk_mutex                *mutex;
  59         unsigned int                    ddp_comp_nr;
  60         struct mtk_ddp_comp             **ddp_comp;
  61
  62         /* lock for display hardware access */
  63         struct mutex                    hw_lock;
  64         bool                            config_updating;
  65 };
  66
  67 struct mtk_crtc_state {
  68         struct drm_crtc_state           base;
  69
  70         bool                            pending_config;
  71         unsigned int                    pending_width;
  72         unsigned int                    pending_height;
  73         unsigned int                    pending_vrefresh;
  74 };
  75
  76 static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c)
  77 {
  78         return container_of(c, struct mtk_drm_crtc, base);
  79 }
  80
  81 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s)
  82 {
  83         return container_of(s, struct mtk_crtc_state, base);
  84 }
  85
  86 static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
  87 {
  88         struct drm_crtc *crtc = &mtk_crtc->base;
  89         unsigned long flags;
  90
  91         spin_lock_irqsave(&crtc->dev->event_lock, flags);
  92         drm_crtc_send_vblank_event(crtc, mtk_crtc->event);
  93         drm_crtc_vblank_put(crtc);
  94         mtk_crtc->event = NULL;
  95         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
  96 }
  97
  98 static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
  99 {
 100         drm_crtc_handle_vblank(&mtk_crtc->base);
 101         if (!mtk_crtc->config_updating && mtk_crtc->pending_needs_vblank) {
 102                 mtk_drm_crtc_finish_page_flip(mtk_crtc);
 103                 mtk_crtc->pending_needs_vblank = false;
 104         }
 105 }
 106
 107 static void mtk_drm_crtc_destroy(struct drm_crtc *crtc)
 108 {
 109         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 110
 111         mtk_mutex_put(mtk_crtc->mutex);
 112
 113         drm_crtc_cleanup(crtc);
 114 }
 115
 116 static void mtk_drm_crtc_reset(struct drm_crtc *crtc)
 117 {
 118         struct mtk_crtc_state *state;
 119
 120         if (crtc->state)
 121                 __drm_atomic_helper_crtc_destroy_state(crtc->state);
 122
 123         kfree(to_mtk_crtc_state(crtc->state));
 124         crtc->state = NULL;
 125
 126         state = kzalloc(sizeof(*state), GFP_KERNEL);
 127         if (state)
 128                 __drm_atomic_helper_crtc_reset(crtc, &state->base);
 129 }
 130
 131 static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc)
 132 {
 133         struct mtk_crtc_state *state;
 134
 135         state = kzalloc(sizeof(*state), GFP_KERNEL);
 136         if (!state)
 137                 return NULL;
 138
 139         __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
 140
 141         WARN_ON(state->base.crtc != crtc);
 142         state->base.crtc = crtc;
 143
 144         return &state->base;
 145 }
 146
 147 static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc,
 148                                        struct drm_crtc_state *state)
 149 {
 150         __drm_atomic_helper_crtc_destroy_state(state);
 151         kfree(to_mtk_crtc_state(state));
 152 }
 153
 154 static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc,
 155                                     const struct drm_display_mode *mode,
 156                                     struct drm_display_mode *adjusted_mode)
 157 {
 158         /* Nothing to do here, but this callback is mandatory. */
 159         return true;
 160 }
 161
 162 static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
 163 {
 164         struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state);
 165
 166         state->pending_width = crtc->mode.hdisplay;
 167         state->pending_height = crtc->mode.vdisplay;
 168         state->pending_vrefresh = drm_mode_vrefresh(&crtc->mode);
 169         wmb();  /* Make sure the above parameters are set before update */
 170         state->pending_config = true;
 171 }
 172
 173 static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc)
 174 {
 175         int ret;
 176         int i;
 177
 178         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 179                 ret = mtk_ddp_comp_clk_enable(mtk_crtc->ddp_comp[i]);
 180                 if (ret) {
 181                         DRM_ERROR("Failed to enable clock %d: %d\n", i, ret);
 182                         goto err;
 183                 }
 184         }
 185
 186         return 0;
 187 err:
 188         while (--i >= 0)
 189                 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]);
 190         return ret;
 191 }
 192
 193 static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc)
 194 {
 195         int i;
 196
 197         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
 198                 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]);
 199 }
 200
 201 static
 202 struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc,
 203                                                 struct drm_plane *plane,
 204                                                 unsigned int *local_layer)
 205 {
 206         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 207         struct mtk_ddp_comp *comp;
 208         int i, count = 0;
 209         unsigned int local_index = plane - mtk_crtc->planes;
 210
 211         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 212                 comp = mtk_crtc->ddp_comp[i];
 213                 if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) {
 214                         *local_layer = local_index - count;
 215                         return comp;
 216                 }
 217                 count += mtk_ddp_comp_layer_nr(comp);
 218         }
 219
 220         WARN(1, "Failed to find component for plane %d\n", plane->index);
 221         return NULL;
 222 }
 223
 224 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 225 static void ddp_cmdq_cb(struct cmdq_cb_data data)
 226 {
 227         cmdq_pkt_destroy(data.data);
 228 }
 229 #endif
 230
 231 static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
 232 {
 233         struct drm_crtc *crtc = &mtk_crtc->base;
 234         struct drm_connector *connector;
 235         struct drm_encoder *encoder;
 236         struct drm_connector_list_iter conn_iter;
 237         unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC;
 238         int ret;
 239         int i;
 240
 241         if (WARN_ON(!crtc->state))
 242                 return -EINVAL;
 243
 244         width = crtc->state->adjusted_mode.hdisplay;
 245         height = crtc->state->adjusted_mode.vdisplay;
 246         vrefresh = drm_mode_vrefresh(&crtc->state->adjusted_mode);
 247
 248         drm_for_each_encoder(encoder, crtc->dev) {
 249                 if (encoder->crtc != crtc)
 250                         continue;
 251
 252                 drm_connector_list_iter_begin(crtc->dev, &conn_iter);
 253                 drm_for_each_connector_iter(connector, &conn_iter) {
 254                         if (connector->encoder != encoder)
 255                                 continue;
 256                         if (connector->display_info.bpc != 0 &&
 257                             bpc > connector->display_info.bpc)
 258                                 bpc = connector->display_info.bpc;
 259                 }
 260                 drm_connector_list_iter_end(&conn_iter);
 261         }
 262
 263         ret = pm_runtime_resume_and_get(crtc->dev->dev);
 264         if (ret < 0) {
 265                 DRM_ERROR("Failed to enable power domain: %d\n", ret);
 266                 return ret;
 267         }
 268
 269         ret = mtk_mutex_prepare(mtk_crtc->mutex);
 270         if (ret < 0) {
 271                 DRM_ERROR("Failed to enable mutex clock: %d\n", ret);
 272                 goto err_pm_runtime_put;
 273         }
 274
 275         ret = mtk_crtc_ddp_clk_enable(mtk_crtc);
 276         if (ret < 0) {
 277                 DRM_ERROR("Failed to enable component clocks: %d\n", ret);
 278                 goto err_mutex_unprepare;
 279         }
 280
 281         for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
 282                 mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev,
 283                                       mtk_crtc->ddp_comp[i]->id,
 284                                       mtk_crtc->ddp_comp[i + 1]->id);
 285                 mtk_mutex_add_comp(mtk_crtc->mutex,
 286                                         mtk_crtc->ddp_comp[i]->id);
 287         }
 288         mtk_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
 289         mtk_mutex_enable(mtk_crtc->mutex);
 290
 291         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 292                 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i];
 293
 294                 if (i == 1)
 295                         mtk_ddp_comp_bgclr_in_on(comp);
 296
 297                 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL);
 298                 mtk_ddp_comp_start(comp);
 299         }
 300
 301         /* Initially configure all planes */
 302         for (i = 0; i < mtk_crtc->layer_nr; i++) {
 303                 struct drm_plane *plane = &mtk_crtc->planes[i];
 304                 struct mtk_plane_state *plane_state;
 305                 struct mtk_ddp_comp *comp;
 306                 unsigned int local_layer;
 307
 308                 plane_state = to_mtk_plane_state(plane->state);
 309                 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer);
 310                 if (comp)
 311                         mtk_ddp_comp_layer_config(comp, local_layer,
 312                                                   plane_state, NULL);
 313         }
 314
 315         return 0;
 316
 317 err_mutex_unprepare:
 318         mtk_mutex_unprepare(mtk_crtc->mutex);
 319 err_pm_runtime_put:
 320         pm_runtime_put(crtc->dev->dev);
 321         return ret;
 322 }
 323
 324 static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc)
 325 {
 326         struct drm_device *drm = mtk_crtc->base.dev;
 327         struct drm_crtc *crtc = &mtk_crtc->base;
 328         int i;
 329
 330         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 331                 mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]);
 332                 if (i == 1)
 333                         mtk_ddp_comp_bgclr_in_off(mtk_crtc->ddp_comp[i]);
 334         }
 335
 336         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
 337                 mtk_mutex_remove_comp(mtk_crtc->mutex,
 338                                            mtk_crtc->ddp_comp[i]->id);
 339         mtk_mutex_disable(mtk_crtc->mutex);
 340         for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
 341                 mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev,
 342                                          mtk_crtc->ddp_comp[i]->id,
 343                                          mtk_crtc->ddp_comp[i + 1]->id);
 344                 mtk_mutex_remove_comp(mtk_crtc->mutex,
 345                                            mtk_crtc->ddp_comp[i]->id);
 346         }
 347         mtk_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
 348         mtk_crtc_ddp_clk_disable(mtk_crtc);
 349         mtk_mutex_unprepare(mtk_crtc->mutex);
 350
 351         pm_runtime_put(drm->dev);
 352
 353         if (crtc->state->event && !crtc->state->active) {
 354                 spin_lock_irq(&crtc->dev->event_lock);
 355                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 356                 crtc->state->event = NULL;
 357                 spin_unlock_irq(&crtc->dev->event_lock);
 358         }
 359 }
 360
 361 static void mtk_crtc_ddp_config(struct drm_crtc *crtc,
 362                                 struct cmdq_pkt *cmdq_handle)
 363 {
 364         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 365         struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
 366         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 367         unsigned int i;
 368         unsigned int local_layer;
 369
 370         /*
 371          * TODO: instead of updating the registers here, we should prepare
 372          * working registers in atomic_commit and let the hardware command
 373          * queue update module registers on vblank.
 374          */
 375         if (state->pending_config) {
 376                 mtk_ddp_comp_config(comp, state->pending_width,
 377                                     state->pending_height,
 378                                     state->pending_vrefresh, 0,
 379                                     cmdq_handle);
 380
 381                 state->pending_config = false;
 382         }
 383
 384         if (mtk_crtc->pending_planes) {
 385                 for (i = 0; i < mtk_crtc->layer_nr; i++) {
 386                         struct drm_plane *plane = &mtk_crtc->planes[i];
 387                         struct mtk_plane_state *plane_state;
 388
 389                         plane_state = to_mtk_plane_state(plane->state);
 390
 391                         if (!plane_state->pending.config)
 392                                 continue;
 393
 394                         comp = mtk_drm_ddp_comp_for_plane(crtc, plane,
 395                                                           &local_layer);
 396
 397                         if (comp)
 398                                 mtk_ddp_comp_layer_config(comp, local_layer,
 399                                                           plane_state,
 400                                                           cmdq_handle);
 401                         plane_state->pending.config = false;
 402                 }
 403                 mtk_crtc->pending_planes = false;
 404         }
 405
 406         if (mtk_crtc->pending_async_planes) {
 407                 for (i = 0; i < mtk_crtc->layer_nr; i++) {
 408                         struct drm_plane *plane = &mtk_crtc->planes[i];
 409                         struct mtk_plane_state *plane_state;
 410
 411                         plane_state = to_mtk_plane_state(plane->state);
 412
 413                         if (!plane_state->pending.async_config)
 414                                 continue;
 415
 416                         comp = mtk_drm_ddp_comp_for_plane(crtc, plane,
 417                                                           &local_layer);
 418
 419                         if (comp)
 420                                 mtk_ddp_comp_layer_config(comp, local_layer,
 421                                                           plane_state,
 422                                                           cmdq_handle);
 423                         plane_state->pending.async_config = false;
 424                 }
 425                 mtk_crtc->pending_async_planes = false;
 426         }
 427 }
 428
 429 static void mtk_drm_crtc_update_config(struct mtk_drm_crtc *mtk_crtc,
 430                                        bool needs_vblank)
 431 {
 432 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 433         struct cmdq_pkt *cmdq_handle;
 434 #endif
 435         struct drm_crtc *crtc = &mtk_crtc->base;
 436         struct mtk_drm_private *priv = crtc->dev->dev_private;
 437         unsigned int pending_planes = 0, pending_async_planes = 0;
 438         int i;
 439
 440         mutex_lock(&mtk_crtc->hw_lock);
 441         mtk_crtc->config_updating = true;
 442         if (needs_vblank)
 443                 mtk_crtc->pending_needs_vblank = true;
 444
 445         for (i = 0; i < mtk_crtc->layer_nr; i++) {
 446                 struct drm_plane *plane = &mtk_crtc->planes[i];
 447                 struct mtk_plane_state *plane_state;
 448
 449                 plane_state = to_mtk_plane_state(plane->state);
 450                 if (plane_state->pending.dirty) {
 451                         plane_state->pending.config = true;
 452                         plane_state->pending.dirty = false;
 453                         pending_planes |= BIT(i);
 454                 } else if (plane_state->pending.async_dirty) {
 455                         plane_state->pending.async_config = true;
 456                         plane_state->pending.async_dirty = false;
 457                         pending_async_planes |= BIT(i);
 458                 }
 459         }
 460         if (pending_planes)
 461                 mtk_crtc->pending_planes = true;
 462         if (pending_async_planes)
 463                 mtk_crtc->pending_async_planes = true;
 464
 465         if (priv->data->shadow_register) {
 466                 mtk_mutex_acquire(mtk_crtc->mutex);
 467                 mtk_crtc_ddp_config(crtc, NULL);
 468                 mtk_mutex_release(mtk_crtc->mutex);
 469         }
 470 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 471         if (mtk_crtc->cmdq_client) {
 472                 mbox_flush(mtk_crtc->cmdq_client->chan, 2000);
 473                 cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE);
 474                 cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
 475                 cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false);
 476                 mtk_crtc_ddp_config(crtc, cmdq_handle);
 477                 cmdq_pkt_finalize(cmdq_handle);
 478                 cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cmdq_handle);
 479         }
 480 #endif
 481         mtk_crtc->config_updating = false;
 482         mutex_unlock(&mtk_crtc->hw_lock);
 483 }
 484
 485 static void mtk_crtc_ddp_irq(void *data)
 486 {
 487         struct drm_crtc *crtc = data;
 488         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 489         struct mtk_drm_private *priv = crtc->dev->dev_private;
 490
 491 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 492         if (!priv->data->shadow_register && !mtk_crtc->cmdq_client)
 493 #else
 494         if (!priv->data->shadow_register)
 495 #endif
 496                 mtk_crtc_ddp_config(crtc, NULL);
 497
 498         mtk_drm_finish_page_flip(mtk_crtc);
 499 }
 500
 501 static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc)
 502 {
 503         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 504         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 505
 506         mtk_ddp_comp_enable_vblank(comp, mtk_crtc_ddp_irq, &mtk_crtc->base);
 507
 508         return 0;
 509 }
 510
 511 static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc)
 512 {
 513         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 514         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 515
 516         mtk_ddp_comp_disable_vblank(comp);
 517 }
 518
 519 int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
 520                              struct mtk_plane_state *state)
 521 {
 522         unsigned int local_layer;
 523         struct mtk_ddp_comp *comp;
 524
 525         comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer);
 526         if (comp)
 527                 return mtk_ddp_comp_layer_check(comp, local_layer, state);
 528         return 0;
 529 }
 530
 531 void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
 532                                struct drm_atomic_state *state)
 533 {
 534         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 535         const struct drm_plane_helper_funcs *plane_helper_funcs =
 536                         plane->helper_private;
 537
 538         if (!mtk_crtc->enabled)
 539                 return;
 540
 541         plane_helper_funcs->atomic_update(plane, state);
 542         mtk_drm_crtc_update_config(mtk_crtc, false);
 543 }
 544
 545 static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc,
 546                                        struct drm_atomic_state *state)
 547 {
 548         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 549         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 550         int ret;
 551
 552         DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
 553
 554         ret = mtk_smi_larb_get(comp->larb_dev);
 555         if (ret) {
 556                 DRM_ERROR("Failed to get larb: %d\n", ret);
 557                 return;
 558         }
 559
 560         ret = mtk_crtc_ddp_hw_init(mtk_crtc);
 561         if (ret) {
 562                 mtk_smi_larb_put(comp->larb_dev);
 563                 return;
 564         }
 565
 566         drm_crtc_vblank_on(crtc);
 567         mtk_crtc->enabled = true;
 568 }
 569
 570 static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc,
 571                                         struct drm_atomic_state *state)
 572 {
 573         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 574         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 575         int i;
 576
 577         DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
 578         if (!mtk_crtc->enabled)
 579                 return;
 580
 581         /* Set all pending plane state to disabled */
 582         for (i = 0; i < mtk_crtc->layer_nr; i++) {
 583                 struct drm_plane *plane = &mtk_crtc->planes[i];
 584                 struct mtk_plane_state *plane_state;
 585
 586                 plane_state = to_mtk_plane_state(plane->state);
 587                 plane_state->pending.enable = false;
 588                 plane_state->pending.config = true;
 589         }
 590         mtk_crtc->pending_planes = true;
 591
 592         mtk_drm_crtc_update_config(mtk_crtc, false);
 593         /* Wait for planes to be disabled */
 594         drm_crtc_wait_one_vblank(crtc);
 595
 596         drm_crtc_vblank_off(crtc);
 597         mtk_crtc_ddp_hw_fini(mtk_crtc);
 598         mtk_smi_larb_put(comp->larb_dev);
 599
 600         mtk_crtc->enabled = false;
 601 }
 602
 603 static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc,
 604                                       struct drm_atomic_state *state)
 605 {
 606         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
 607                                                                           crtc);
 608         struct mtk_crtc_state *mtk_crtc_state = to_mtk_crtc_state(crtc_state);
 609         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 610
 611         if (mtk_crtc->event && mtk_crtc_state->base.event)
 612                 DRM_ERROR("new event while there is still a pending event\n");
 613
 614         if (mtk_crtc_state->base.event) {
 615                 mtk_crtc_state->base.event->pipe = drm_crtc_index(crtc);
 616                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 617                 mtk_crtc->event = mtk_crtc_state->base.event;
 618                 mtk_crtc_state->base.event = NULL;
 619         }
 620 }
 621
 622 static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
 623                                       struct drm_atomic_state *state)
 624 {
 625         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 626         int i;
 627
 628         if (crtc->state->color_mgmt_changed)
 629                 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 630                         mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
 631                         mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
 632                 }
 633         mtk_drm_crtc_update_config(mtk_crtc, !!mtk_crtc->event);
 634 }
 635
 636 static const struct drm_crtc_funcs mtk_crtc_funcs = {
 637         .set_config             = drm_atomic_helper_set_config,
 638         .page_flip              = drm_atomic_helper_page_flip,
 639         .destroy                = mtk_drm_crtc_destroy,
 640         .reset                  = mtk_drm_crtc_reset,
 641         .atomic_duplicate_state = mtk_drm_crtc_duplicate_state,
 642         .atomic_destroy_state   = mtk_drm_crtc_destroy_state,
 643         .enable_vblank          = mtk_drm_crtc_enable_vblank,
 644         .disable_vblank         = mtk_drm_crtc_disable_vblank,
 645 };
 646
 647 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = {
 648         .mode_fixup     = mtk_drm_crtc_mode_fixup,
 649         .mode_set_nofb  = mtk_drm_crtc_mode_set_nofb,
 650         .atomic_begin   = mtk_drm_crtc_atomic_begin,
 651         .atomic_flush   = mtk_drm_crtc_atomic_flush,
 652         .atomic_enable  = mtk_drm_crtc_atomic_enable,
 653         .atomic_disable = mtk_drm_crtc_atomic_disable,
 654 };
 655
 656 static int mtk_drm_crtc_init(struct drm_device *drm,
 657                              struct mtk_drm_crtc *mtk_crtc,
 658                              unsigned int pipe)
 659 {
 660         struct drm_plane *primary = NULL;
 661         struct drm_plane *cursor = NULL;
 662         int i, ret;
 663
 664         for (i = 0; i < mtk_crtc->layer_nr; i++) {
 665                 if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_PRIMARY)
 666                         primary = &mtk_crtc->planes[i];
 667                 else if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_CURSOR)
 668                         cursor = &mtk_crtc->planes[i];
 669         }
 670
 671         ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor,
 672                                         &mtk_crtc_funcs, NULL);
 673         if (ret)
 674                 goto err_cleanup_crtc;
 675
 676         drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs);
 677
 678         return 0;
 679
 680 err_cleanup_crtc:
 681         drm_crtc_cleanup(&mtk_crtc->base);
 682         return ret;
 683 }
 684
 685 static int mtk_drm_crtc_num_comp_planes(struct mtk_drm_crtc *mtk_crtc,
 686                                         int comp_idx)
 687 {
 688         struct mtk_ddp_comp *comp;
 689
 690         if (comp_idx > 1)
 691                 return 0;
 692
 693         comp = mtk_crtc->ddp_comp[comp_idx];
 694         if (!comp->funcs)
 695                 return 0;
 696
 697         if (comp_idx == 1 && !comp->funcs->bgclr_in_on)
 698                 return 0;
 699
 700         return mtk_ddp_comp_layer_nr(comp);
 701 }
 702
 703 static inline
 704 enum drm_plane_type mtk_drm_crtc_plane_type(unsigned int plane_idx,
 705                                             unsigned int num_planes)
 706 {
 707         if (plane_idx == 0)
 708                 return DRM_PLANE_TYPE_PRIMARY;
 709         else if (plane_idx == (num_planes - 1))
 710                 return DRM_PLANE_TYPE_CURSOR;
 711         else
 712                 return DRM_PLANE_TYPE_OVERLAY;
 713
 714 }
 715
 716 static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev,
 717                                          struct mtk_drm_crtc *mtk_crtc,
 718                                          int comp_idx, int pipe)
 719 {
 720         int num_planes = mtk_drm_crtc_num_comp_planes(mtk_crtc, comp_idx);
 721         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[comp_idx];
 722         int i, ret;
 723
 724         for (i = 0; i < num_planes; i++) {
 725                 ret = mtk_plane_init(drm_dev,
 726                                 &mtk_crtc->planes[mtk_crtc->layer_nr],
 727                                 BIT(pipe),
 728                                 mtk_drm_crtc_plane_type(mtk_crtc->layer_nr,
 729                                                         num_planes),
 730                                 mtk_ddp_comp_supported_rotations(comp));
 731                 if (ret)
 732                         return ret;
 733
 734                 mtk_crtc->layer_nr++;
 735         }
 736         return 0;
 737 }
 738
 739 int mtk_drm_crtc_create(struct drm_device *drm_dev,
 740                         const enum mtk_ddp_comp_id *path, unsigned int path_len)
 741 {
 742         struct mtk_drm_private *priv = drm_dev->dev_private;
 743         struct device *dev = drm_dev->dev;
 744         struct mtk_drm_crtc *mtk_crtc;
 745         unsigned int num_comp_planes = 0;
 746         int pipe = priv->num_pipes;
 747         int ret;
 748         int i;
 749         bool has_ctm = false;
 750         uint gamma_lut_size = 0;
 751
 752         if (!path)
 753                 return 0;
 754
 755         for (i = 0; i < path_len; i++) {
 756                 enum mtk_ddp_comp_id comp_id = path[i];
 757                 struct device_node *node;
 758
 759                 node = priv->comp_node[comp_id];
 760                 if (!node) {
 761                         dev_info(dev,
 762                                  "Not creating crtc %d because component %d is disabled or missing\n",
 763                                  pipe, comp_id);
 764                         return 0;
 765                 }
 766         }
 767
 768         mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL);
 769         if (!mtk_crtc)
 770                 return -ENOMEM;
 771
 772         mtk_crtc->mmsys_dev = priv->mmsys_dev;
 773         mtk_crtc->ddp_comp_nr = path_len;
 774         mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr,
 775                                                 sizeof(*mtk_crtc->ddp_comp),
 776                                                 GFP_KERNEL);
 777         if (!mtk_crtc->ddp_comp)
 778                 return -ENOMEM;
 779
 780         mtk_crtc->mutex = mtk_mutex_get(priv->mutex_dev);
 781         if (IS_ERR(mtk_crtc->mutex)) {
 782                 ret = PTR_ERR(mtk_crtc->mutex);
 783                 dev_err(dev, "Failed to get mutex: %d\n", ret);
 784                 return ret;
 785         }
 786
 787         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 788                 enum mtk_ddp_comp_id comp_id = path[i];
 789                 struct mtk_ddp_comp *comp;
 790                 struct device_node *node;
 791
 792                 node = priv->comp_node[comp_id];
 793                 comp = &priv->ddp_comp[comp_id];
 794                 if (!comp) {
 795                         dev_err(dev, "Component %pOF not initialized\n", node);
 796                         ret = -ENODEV;
 797                         return ret;
 798                 }
 799
 800                 mtk_crtc->ddp_comp[i] = comp;
 801
 802                 if (comp->funcs) {
 803                         if (comp->funcs->gamma_set)
 804                                 gamma_lut_size = MTK_LUT_SIZE;
 805
 806                         if (comp->funcs->ctm_set)
 807                                 has_ctm = true;
 808                 }
 809         }
 810
 811         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
 812                 num_comp_planes += mtk_drm_crtc_num_comp_planes(mtk_crtc, i);
 813
 814         mtk_crtc->planes = devm_kcalloc(dev, num_comp_planes,
 815                                         sizeof(struct drm_plane), GFP_KERNEL);
 816
 817         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 818                 ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i,
 819                                                     pipe);
 820                 if (ret)
 821                         return ret;
 822         }
 823
 824         ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe);
 825         if (ret < 0)
 826                 return ret;
 827
 828         if (gamma_lut_size)
 829                 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
 830         drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
 831         priv->num_pipes++;
 832         mutex_init(&mtk_crtc->hw_lock);
 833
 834 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 835         mtk_crtc->cmdq_client =
 836                         cmdq_mbox_create(mtk_crtc->mmsys_dev,
 837                                          drm_crtc_index(&mtk_crtc->base));
 838         if (IS_ERR(mtk_crtc->cmdq_client)) {
 839                 dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n",
 840                         drm_crtc_index(&mtk_crtc->base));
 841                 mtk_crtc->cmdq_client = NULL;
 842         }
 843
 844         if (mtk_crtc->cmdq_client) {
 845                 ret = of_property_read_u32_index(priv->mutex_node,
 846                                                  "mediatek,gce-events",
 847                                                  drm_crtc_index(&mtk_crtc->base),
 848                                                  &mtk_crtc->cmdq_event);
 849                 if (ret) {
 850                         dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n",
 851                                 drm_crtc_index(&mtk_crtc->base));
 852                         cmdq_mbox_destroy(mtk_crtc->cmdq_client);
 853                         mtk_crtc->cmdq_client = NULL;
 854                 }
 855         }
 856 #endif
 857         return 0;
 858 }