1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015 MediaTek Inc.
7 #include <linux/pm_runtime.h>
8 #include <linux/soc/mediatek/mtk-cmdq.h>
9 #include <linux/soc/mediatek/mtk-mmsys.h>
10 #include <linux/soc/mediatek/mtk-mutex.h>
12 #include <asm/barrier.h>
13 #include <soc/mediatek/smi.h>
15 #include <drm/drm_atomic.h>
16 #include <drm/drm_atomic_helper.h>
17 #include <drm/drm_plane_helper.h>
18 #include <drm/drm_probe_helper.h>
19 #include <drm/drm_vblank.h>
21 #include "mtk_drm_drv.h"
22 #include "mtk_drm_crtc.h"
23 #include "mtk_drm_ddp_comp.h"
24 #include "mtk_drm_gem.h"
25 #include "mtk_drm_plane.h"
28 * struct mtk_drm_crtc - MediaTek specific crtc structure.
30 * @enabled: records whether crtc_enable succeeded
31 * @planes: array of 4 drm_plane structures, one for each overlay plane
32 * @pending_planes: whether any plane has pending changes to be applied
33 * @mmsys_dev: pointer to the mmsys device for configuration registers
34 * @mutex: handle to one of the ten disp_mutex streams
35 * @ddp_comp_nr: number of components in ddp_comp
36 * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc
38 * TODO: Needs update: this header is missing a bunch of member descriptions.
44 bool pending_needs_vblank;
45 struct drm_pending_vblank_event *event;
47 struct drm_plane *planes;
48 unsigned int layer_nr;
50 bool pending_async_planes;
52 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
53 struct cmdq_client *cmdq_client;
57 struct device *mmsys_dev;
58 struct mtk_mutex *mutex;
59 unsigned int ddp_comp_nr;
60 struct mtk_ddp_comp **ddp_comp;
62 /* lock for display hardware access */
66 struct mtk_crtc_state {
67 struct drm_crtc_state base;
70 unsigned int pending_width;
71 unsigned int pending_height;
72 unsigned int pending_vrefresh;
75 static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c)
77 return container_of(c, struct mtk_drm_crtc, base);
80 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s)
82 return container_of(s, struct mtk_crtc_state, base);
85 static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
87 struct drm_crtc *crtc = &mtk_crtc->base;
90 spin_lock_irqsave(&crtc->dev->event_lock, flags);
91 drm_crtc_send_vblank_event(crtc, mtk_crtc->event);
92 drm_crtc_vblank_put(crtc);
93 mtk_crtc->event = NULL;
94 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
97 static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
99 drm_crtc_handle_vblank(&mtk_crtc->base);
100 if (mtk_crtc->pending_needs_vblank) {
101 mtk_drm_crtc_finish_page_flip(mtk_crtc);
102 mtk_crtc->pending_needs_vblank = false;
106 static void mtk_drm_crtc_destroy(struct drm_crtc *crtc)
108 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
110 mtk_mutex_put(mtk_crtc->mutex);
112 drm_crtc_cleanup(crtc);
115 static void mtk_drm_crtc_reset(struct drm_crtc *crtc)
117 struct mtk_crtc_state *state;
120 __drm_atomic_helper_crtc_destroy_state(crtc->state);
122 kfree(to_mtk_crtc_state(crtc->state));
125 state = kzalloc(sizeof(*state), GFP_KERNEL);
127 __drm_atomic_helper_crtc_reset(crtc, &state->base);
130 static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc)
132 struct mtk_crtc_state *state;
134 state = kzalloc(sizeof(*state), GFP_KERNEL);
138 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
140 WARN_ON(state->base.crtc != crtc);
141 state->base.crtc = crtc;
146 static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc,
147 struct drm_crtc_state *state)
149 __drm_atomic_helper_crtc_destroy_state(state);
150 kfree(to_mtk_crtc_state(state));
153 static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc,
154 const struct drm_display_mode *mode,
155 struct drm_display_mode *adjusted_mode)
157 /* Nothing to do here, but this callback is mandatory. */
161 static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
163 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state);
165 state->pending_width = crtc->mode.hdisplay;
166 state->pending_height = crtc->mode.vdisplay;
167 state->pending_vrefresh = drm_mode_vrefresh(&crtc->mode);
168 wmb(); /* Make sure the above parameters are set before update */
169 state->pending_config = true;
172 static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc)
177 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
178 ret = mtk_ddp_comp_clk_enable(mtk_crtc->ddp_comp[i]);
180 DRM_ERROR("Failed to enable clock %d: %d\n", i, ret);
188 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]);
192 static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc)
196 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
197 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]);
201 struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc,
202 struct drm_plane *plane,
203 unsigned int *local_layer)
205 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
206 struct mtk_ddp_comp *comp;
208 unsigned int local_index = plane - mtk_crtc->planes;
210 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
211 comp = mtk_crtc->ddp_comp[i];
212 if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) {
213 *local_layer = local_index - count;
216 count += mtk_ddp_comp_layer_nr(comp);
219 WARN(1, "Failed to find component for plane %d\n", plane->index);
223 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
224 static void ddp_cmdq_cb(struct cmdq_cb_data data)
226 cmdq_pkt_destroy(data.data);
230 static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
232 struct drm_crtc *crtc = &mtk_crtc->base;
233 struct drm_connector *connector;
234 struct drm_encoder *encoder;
235 struct drm_connector_list_iter conn_iter;
236 unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC;
240 if (WARN_ON(!crtc->state))
243 width = crtc->state->adjusted_mode.hdisplay;
244 height = crtc->state->adjusted_mode.vdisplay;
245 vrefresh = drm_mode_vrefresh(&crtc->state->adjusted_mode);
247 drm_for_each_encoder(encoder, crtc->dev) {
248 if (encoder->crtc != crtc)
251 drm_connector_list_iter_begin(crtc->dev, &conn_iter);
252 drm_for_each_connector_iter(connector, &conn_iter) {
253 if (connector->encoder != encoder)
255 if (connector->display_info.bpc != 0 &&
256 bpc > connector->display_info.bpc)
257 bpc = connector->display_info.bpc;
259 drm_connector_list_iter_end(&conn_iter);
262 ret = pm_runtime_get_sync(crtc->dev->dev);
264 DRM_ERROR("Failed to enable power domain: %d\n", ret);
268 ret = mtk_mutex_prepare(mtk_crtc->mutex);
270 DRM_ERROR("Failed to enable mutex clock: %d\n", ret);
271 goto err_pm_runtime_put;
274 ret = mtk_crtc_ddp_clk_enable(mtk_crtc);
276 DRM_ERROR("Failed to enable component clocks: %d\n", ret);
277 goto err_mutex_unprepare;
280 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
281 mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev,
282 mtk_crtc->ddp_comp[i]->id,
283 mtk_crtc->ddp_comp[i + 1]->id);
284 mtk_mutex_add_comp(mtk_crtc->mutex,
285 mtk_crtc->ddp_comp[i]->id);
287 mtk_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
288 mtk_mutex_enable(mtk_crtc->mutex);
290 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
291 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i];
294 mtk_ddp_comp_bgclr_in_on(comp);
296 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL);
297 mtk_ddp_comp_start(comp);
300 /* Initially configure all planes */
301 for (i = 0; i < mtk_crtc->layer_nr; i++) {
302 struct drm_plane *plane = &mtk_crtc->planes[i];
303 struct mtk_plane_state *plane_state;
304 struct mtk_ddp_comp *comp;
305 unsigned int local_layer;
307 plane_state = to_mtk_plane_state(plane->state);
308 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer);
310 mtk_ddp_comp_layer_config(comp, local_layer,
317 mtk_mutex_unprepare(mtk_crtc->mutex);
319 pm_runtime_put(crtc->dev->dev);
323 static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc)
325 struct drm_device *drm = mtk_crtc->base.dev;
326 struct drm_crtc *crtc = &mtk_crtc->base;
329 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
330 mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]);
332 mtk_ddp_comp_bgclr_in_off(mtk_crtc->ddp_comp[i]);
335 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
336 mtk_mutex_remove_comp(mtk_crtc->mutex,
337 mtk_crtc->ddp_comp[i]->id);
338 mtk_mutex_disable(mtk_crtc->mutex);
339 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
340 mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev,
341 mtk_crtc->ddp_comp[i]->id,
342 mtk_crtc->ddp_comp[i + 1]->id);
343 mtk_mutex_remove_comp(mtk_crtc->mutex,
344 mtk_crtc->ddp_comp[i]->id);
346 mtk_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
347 mtk_crtc_ddp_clk_disable(mtk_crtc);
348 mtk_mutex_unprepare(mtk_crtc->mutex);
350 pm_runtime_put(drm->dev);
352 if (crtc->state->event && !crtc->state->active) {
353 spin_lock_irq(&crtc->dev->event_lock);
354 drm_crtc_send_vblank_event(crtc, crtc->state->event);
355 crtc->state->event = NULL;
356 spin_unlock_irq(&crtc->dev->event_lock);
360 static void mtk_crtc_ddp_config(struct drm_crtc *crtc,
361 struct cmdq_pkt *cmdq_handle)
363 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
364 struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
365 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
367 unsigned int local_layer;
370 * TODO: instead of updating the registers here, we should prepare
371 * working registers in atomic_commit and let the hardware command
372 * queue update module registers on vblank.
374 if (state->pending_config) {
375 mtk_ddp_comp_config(comp, state->pending_width,
376 state->pending_height,
377 state->pending_vrefresh, 0,
380 state->pending_config = false;
383 if (mtk_crtc->pending_planes) {
384 for (i = 0; i < mtk_crtc->layer_nr; i++) {
385 struct drm_plane *plane = &mtk_crtc->planes[i];
386 struct mtk_plane_state *plane_state;
388 plane_state = to_mtk_plane_state(plane->state);
390 if (!plane_state->pending.config)
393 comp = mtk_drm_ddp_comp_for_plane(crtc, plane,
397 mtk_ddp_comp_layer_config(comp, local_layer,
400 plane_state->pending.config = false;
402 mtk_crtc->pending_planes = false;
405 if (mtk_crtc->pending_async_planes) {
406 for (i = 0; i < mtk_crtc->layer_nr; i++) {
407 struct drm_plane *plane = &mtk_crtc->planes[i];
408 struct mtk_plane_state *plane_state;
410 plane_state = to_mtk_plane_state(plane->state);
412 if (!plane_state->pending.async_config)
415 comp = mtk_drm_ddp_comp_for_plane(crtc, plane,
419 mtk_ddp_comp_layer_config(comp, local_layer,
422 plane_state->pending.async_config = false;
424 mtk_crtc->pending_async_planes = false;
428 static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc)
430 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
431 struct cmdq_pkt *cmdq_handle;
433 struct drm_crtc *crtc = &mtk_crtc->base;
434 struct mtk_drm_private *priv = crtc->dev->dev_private;
435 unsigned int pending_planes = 0, pending_async_planes = 0;
438 mutex_lock(&mtk_crtc->hw_lock);
439 for (i = 0; i < mtk_crtc->layer_nr; i++) {
440 struct drm_plane *plane = &mtk_crtc->planes[i];
441 struct mtk_plane_state *plane_state;
443 plane_state = to_mtk_plane_state(plane->state);
444 if (plane_state->pending.dirty) {
445 plane_state->pending.config = true;
446 plane_state->pending.dirty = false;
447 pending_planes |= BIT(i);
448 } else if (plane_state->pending.async_dirty) {
449 plane_state->pending.async_config = true;
450 plane_state->pending.async_dirty = false;
451 pending_async_planes |= BIT(i);
455 mtk_crtc->pending_planes = true;
456 if (pending_async_planes)
457 mtk_crtc->pending_async_planes = true;
459 if (priv->data->shadow_register) {
460 mtk_mutex_acquire(mtk_crtc->mutex);
461 mtk_crtc_ddp_config(crtc, NULL);
462 mtk_mutex_release(mtk_crtc->mutex);
464 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
465 if (mtk_crtc->cmdq_client) {
466 mbox_flush(mtk_crtc->cmdq_client->chan, 2000);
467 cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE);
468 cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
469 cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false);
470 mtk_crtc_ddp_config(crtc, cmdq_handle);
471 cmdq_pkt_finalize(cmdq_handle);
472 cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cmdq_handle);
475 mutex_unlock(&mtk_crtc->hw_lock);
478 static void mtk_crtc_ddp_irq(void *data)
480 struct drm_crtc *crtc = data;
481 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
482 struct mtk_drm_private *priv = crtc->dev->dev_private;
484 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
485 if (!priv->data->shadow_register && !mtk_crtc->cmdq_client)
487 if (!priv->data->shadow_register)
489 mtk_crtc_ddp_config(crtc, NULL);
491 mtk_drm_finish_page_flip(mtk_crtc);
494 static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc)
496 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
497 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
499 mtk_ddp_comp_enable_vblank(comp, mtk_crtc_ddp_irq, &mtk_crtc->base);
504 static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc)
506 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
507 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
509 mtk_ddp_comp_disable_vblank(comp);
512 int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
513 struct mtk_plane_state *state)
515 unsigned int local_layer;
516 struct mtk_ddp_comp *comp;
518 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer);
520 return mtk_ddp_comp_layer_check(comp, local_layer, state);
524 void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
525 struct drm_atomic_state *state)
527 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
528 const struct drm_plane_helper_funcs *plane_helper_funcs =
529 plane->helper_private;
531 if (!mtk_crtc->enabled)
534 plane_helper_funcs->atomic_update(plane, state);
535 mtk_drm_crtc_hw_config(mtk_crtc);
538 static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc,
539 struct drm_atomic_state *state)
541 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
542 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
545 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
547 ret = mtk_smi_larb_get(comp->larb_dev);
549 DRM_ERROR("Failed to get larb: %d\n", ret);
553 ret = mtk_crtc_ddp_hw_init(mtk_crtc);
555 mtk_smi_larb_put(comp->larb_dev);
559 drm_crtc_vblank_on(crtc);
560 mtk_crtc->enabled = true;
563 static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc,
564 struct drm_atomic_state *state)
566 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
567 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
570 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
571 if (!mtk_crtc->enabled)
574 /* Set all pending plane state to disabled */
575 for (i = 0; i < mtk_crtc->layer_nr; i++) {
576 struct drm_plane *plane = &mtk_crtc->planes[i];
577 struct mtk_plane_state *plane_state;
579 plane_state = to_mtk_plane_state(plane->state);
580 plane_state->pending.enable = false;
581 plane_state->pending.config = true;
583 mtk_crtc->pending_planes = true;
585 mtk_drm_crtc_hw_config(mtk_crtc);
586 /* Wait for planes to be disabled */
587 drm_crtc_wait_one_vblank(crtc);
589 drm_crtc_vblank_off(crtc);
590 mtk_crtc_ddp_hw_fini(mtk_crtc);
591 mtk_smi_larb_put(comp->larb_dev);
593 mtk_crtc->enabled = false;
596 static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc,
597 struct drm_atomic_state *state)
599 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
601 struct mtk_crtc_state *mtk_crtc_state = to_mtk_crtc_state(crtc_state);
602 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
604 if (mtk_crtc->event && mtk_crtc_state->base.event)
605 DRM_ERROR("new event while there is still a pending event\n");
607 if (mtk_crtc_state->base.event) {
608 mtk_crtc_state->base.event->pipe = drm_crtc_index(crtc);
609 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
610 mtk_crtc->event = mtk_crtc_state->base.event;
611 mtk_crtc_state->base.event = NULL;
615 static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
616 struct drm_atomic_state *state)
618 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
622 mtk_crtc->pending_needs_vblank = true;
623 if (crtc->state->color_mgmt_changed)
624 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
625 mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
626 mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
628 mtk_drm_crtc_hw_config(mtk_crtc);
631 static const struct drm_crtc_funcs mtk_crtc_funcs = {
632 .set_config = drm_atomic_helper_set_config,
633 .page_flip = drm_atomic_helper_page_flip,
634 .destroy = mtk_drm_crtc_destroy,
635 .reset = mtk_drm_crtc_reset,
636 .atomic_duplicate_state = mtk_drm_crtc_duplicate_state,
637 .atomic_destroy_state = mtk_drm_crtc_destroy_state,
638 .enable_vblank = mtk_drm_crtc_enable_vblank,
639 .disable_vblank = mtk_drm_crtc_disable_vblank,
642 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = {
643 .mode_fixup = mtk_drm_crtc_mode_fixup,
644 .mode_set_nofb = mtk_drm_crtc_mode_set_nofb,
645 .atomic_begin = mtk_drm_crtc_atomic_begin,
646 .atomic_flush = mtk_drm_crtc_atomic_flush,
647 .atomic_enable = mtk_drm_crtc_atomic_enable,
648 .atomic_disable = mtk_drm_crtc_atomic_disable,
651 static int mtk_drm_crtc_init(struct drm_device *drm,
652 struct mtk_drm_crtc *mtk_crtc,
655 struct drm_plane *primary = NULL;
656 struct drm_plane *cursor = NULL;
659 for (i = 0; i < mtk_crtc->layer_nr; i++) {
660 if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_PRIMARY)
661 primary = &mtk_crtc->planes[i];
662 else if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_CURSOR)
663 cursor = &mtk_crtc->planes[i];
666 ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor,
667 &mtk_crtc_funcs, NULL);
669 goto err_cleanup_crtc;
671 drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs);
676 drm_crtc_cleanup(&mtk_crtc->base);
680 static int mtk_drm_crtc_num_comp_planes(struct mtk_drm_crtc *mtk_crtc,
683 struct mtk_ddp_comp *comp;
688 comp = mtk_crtc->ddp_comp[comp_idx];
692 if (comp_idx == 1 && !comp->funcs->bgclr_in_on)
695 return mtk_ddp_comp_layer_nr(comp);
699 enum drm_plane_type mtk_drm_crtc_plane_type(unsigned int plane_idx,
700 unsigned int num_planes)
703 return DRM_PLANE_TYPE_PRIMARY;
704 else if (plane_idx == (num_planes - 1))
705 return DRM_PLANE_TYPE_CURSOR;
707 return DRM_PLANE_TYPE_OVERLAY;
711 static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev,
712 struct mtk_drm_crtc *mtk_crtc,
713 int comp_idx, int pipe)
715 int num_planes = mtk_drm_crtc_num_comp_planes(mtk_crtc, comp_idx);
716 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[comp_idx];
719 for (i = 0; i < num_planes; i++) {
720 ret = mtk_plane_init(drm_dev,
721 &mtk_crtc->planes[mtk_crtc->layer_nr],
723 mtk_drm_crtc_plane_type(mtk_crtc->layer_nr,
725 mtk_ddp_comp_supported_rotations(comp));
729 mtk_crtc->layer_nr++;
734 int mtk_drm_crtc_create(struct drm_device *drm_dev,
735 const enum mtk_ddp_comp_id *path, unsigned int path_len)
737 struct mtk_drm_private *priv = drm_dev->dev_private;
738 struct device *dev = drm_dev->dev;
739 struct mtk_drm_crtc *mtk_crtc;
740 unsigned int num_comp_planes = 0;
741 int pipe = priv->num_pipes;
744 bool has_ctm = false;
745 uint gamma_lut_size = 0;
750 for (i = 0; i < path_len; i++) {
751 enum mtk_ddp_comp_id comp_id = path[i];
752 struct device_node *node;
754 node = priv->comp_node[comp_id];
757 "Not creating crtc %d because component %d is disabled or missing\n",
763 mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL);
767 mtk_crtc->mmsys_dev = priv->mmsys_dev;
768 mtk_crtc->ddp_comp_nr = path_len;
769 mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr,
770 sizeof(*mtk_crtc->ddp_comp),
772 if (!mtk_crtc->ddp_comp)
775 mtk_crtc->mutex = mtk_mutex_get(priv->mutex_dev);
776 if (IS_ERR(mtk_crtc->mutex)) {
777 ret = PTR_ERR(mtk_crtc->mutex);
778 dev_err(dev, "Failed to get mutex: %d\n", ret);
782 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
783 enum mtk_ddp_comp_id comp_id = path[i];
784 struct mtk_ddp_comp *comp;
785 struct device_node *node;
787 node = priv->comp_node[comp_id];
788 comp = &priv->ddp_comp[comp_id];
790 dev_err(dev, "Component %pOF not initialized\n", node);
795 mtk_crtc->ddp_comp[i] = comp;
798 if (comp->funcs->gamma_set)
799 gamma_lut_size = MTK_LUT_SIZE;
801 if (comp->funcs->ctm_set)
806 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
807 num_comp_planes += mtk_drm_crtc_num_comp_planes(mtk_crtc, i);
809 mtk_crtc->planes = devm_kcalloc(dev, num_comp_planes,
810 sizeof(struct drm_plane), GFP_KERNEL);
812 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
813 ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i,
819 ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe);
824 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
825 drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
827 mutex_init(&mtk_crtc->hw_lock);
829 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
830 mtk_crtc->cmdq_client =
831 cmdq_mbox_create(mtk_crtc->mmsys_dev,
832 drm_crtc_index(&mtk_crtc->base));
833 if (IS_ERR(mtk_crtc->cmdq_client)) {
834 dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n",
835 drm_crtc_index(&mtk_crtc->base));
836 mtk_crtc->cmdq_client = NULL;
839 if (mtk_crtc->cmdq_client) {
840 ret = of_property_read_u32_index(priv->mutex_node,
841 "mediatek,gce-events",
842 drm_crtc_index(&mtk_crtc->base),
843 &mtk_crtc->cmdq_event);
845 dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n",
846 drm_crtc_index(&mtk_crtc->base));
847 cmdq_mbox_destroy(mtk_crtc->cmdq_client);
848 mtk_crtc->cmdq_client = NULL;