1 /* SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2018-2020 Intel Corporation
9 #include <drm/drm_device.h>
11 #include "kmb_plane.h"
14 #define KMB_MAX_WIDTH 1920 /*Max width in pixels */
15 #define KMB_MAX_HEIGHT 1080 /*Max height in pixels */
16 #define KMB_MIN_WIDTH 1920 /*Max width in pixels */
17 #define KMB_MIN_HEIGHT 1080 /*Max height in pixels */
19 #define DRIVER_DATE "20210223"
20 #define DRIVER_MAJOR 1
21 #define DRIVER_MINOR 1
23 #define KMB_LCD_DEFAULT_CLK 200000000
24 #define KMB_SYS_CLK_MHZ 500
26 #define ICAM_MMIO 0x3b100000
27 #define ICAM_LCD_OFFSET 0x1080
28 #define ICAM_MMIO_SIZE 0x2000
37 struct kmb_drm_private {
38 struct drm_device drm;
39 struct kmb_dsi *kmb_dsi;
40 void __iomem *lcd_mmio;
41 struct kmb_clock kmb_clk;
43 struct kmb_plane *plane;
44 struct drm_atomic_state *state;
48 struct layer_status plane_status[KMB_MAX_PLANES];
54 static inline struct kmb_drm_private *to_kmb(const struct drm_device *dev)
56 return container_of(dev, struct kmb_drm_private, drm);
59 static inline struct kmb_drm_private *crtc_to_kmb_priv(const struct drm_crtc *x)
61 return container_of(x, struct kmb_drm_private, crtc);
64 static inline void kmb_write_lcd(struct kmb_drm_private *dev_p,
65 unsigned int reg, u32 value)
67 writel(value, (dev_p->lcd_mmio + reg));
70 static inline u32 kmb_read_lcd(struct kmb_drm_private *dev_p, unsigned int reg)
72 return readl(dev_p->lcd_mmio + reg);
75 static inline void kmb_set_bitmask_lcd(struct kmb_drm_private *dev_p,
76 unsigned int reg, u32 mask)
78 u32 reg_val = kmb_read_lcd(dev_p, reg);
80 kmb_write_lcd(dev_p, reg, (reg_val | mask));
83 static inline void kmb_clr_bitmask_lcd(struct kmb_drm_private *dev_p,
84 unsigned int reg, u32 mask)
86 u32 reg_val = kmb_read_lcd(dev_p, reg);
88 kmb_write_lcd(dev_p, reg, (reg_val & (~mask)));
91 int kmb_setup_crtc(struct drm_device *dev);
92 void kmb_set_scanout(struct kmb_drm_private *lcd);
93 #endif /* __KMB_DRV_H__ */