1 // SPDX-License-Identifier: GPL-2.0+
3 * i.MX IPUv3 DP Overlay Planes
5 * Copyright (C) 2013 Philipp Zabel, Pengutronix
8 #include <drm/drm_atomic.h>
9 #include <drm/drm_atomic_helper.h>
10 #include <drm/drm_fb_cma_helper.h>
11 #include <drm/drm_fourcc.h>
12 #include <drm/drm_gem_atomic_helper.h>
13 #include <drm/drm_gem_cma_helper.h>
14 #include <drm/drm_managed.h>
15 #include <drm/drm_plane_helper.h>
17 #include <video/imx-ipu-v3.h>
20 #include "ipuv3-plane.h"
22 struct ipu_plane_state {
23 struct drm_plane_state base;
27 static inline struct ipu_plane_state *
28 to_ipu_plane_state(struct drm_plane_state *p)
30 return container_of(p, struct ipu_plane_state, base);
33 static unsigned int ipu_src_rect_width(const struct drm_plane_state *state)
35 return ALIGN(drm_rect_width(&state->src) >> 16, 8);
38 static inline struct ipu_plane *to_ipu_plane(struct drm_plane *p)
40 return container_of(p, struct ipu_plane, base);
43 static const uint32_t ipu_plane_all_formats[] = {
76 DRM_FORMAT_RGBX8888_A8,
77 DRM_FORMAT_BGRX8888_A8,
80 static const uint32_t ipu_plane_rgb_formats[] = {
100 DRM_FORMAT_BGR888_A8,
101 DRM_FORMAT_RGBX8888_A8,
102 DRM_FORMAT_BGRX8888_A8,
105 static const uint64_t ipu_format_modifiers[] = {
106 DRM_FORMAT_MOD_LINEAR,
107 DRM_FORMAT_MOD_INVALID
110 static const uint64_t pre_format_modifiers[] = {
111 DRM_FORMAT_MOD_LINEAR,
112 DRM_FORMAT_MOD_VIVANTE_TILED,
113 DRM_FORMAT_MOD_VIVANTE_SUPER_TILED,
114 DRM_FORMAT_MOD_INVALID
117 int ipu_plane_irq(struct ipu_plane *ipu_plane)
119 return ipu_idmac_channel_irq(ipu_plane->ipu, ipu_plane->ipu_ch,
123 static inline unsigned long
124 drm_plane_state_to_eba(struct drm_plane_state *state, int plane)
126 struct drm_framebuffer *fb = state->fb;
127 struct drm_gem_cma_object *cma_obj;
128 int x = state->src.x1 >> 16;
129 int y = state->src.y1 >> 16;
131 cma_obj = drm_fb_cma_get_gem_obj(fb, plane);
134 return cma_obj->paddr + fb->offsets[plane] + fb->pitches[plane] * y +
135 fb->format->cpp[plane] * x;
138 static inline unsigned long
139 drm_plane_state_to_ubo(struct drm_plane_state *state)
141 struct drm_framebuffer *fb = state->fb;
142 struct drm_gem_cma_object *cma_obj;
143 unsigned long eba = drm_plane_state_to_eba(state, 0);
144 int x = state->src.x1 >> 16;
145 int y = state->src.y1 >> 16;
147 cma_obj = drm_fb_cma_get_gem_obj(fb, 1);
150 x /= fb->format->hsub;
151 y /= fb->format->vsub;
153 return cma_obj->paddr + fb->offsets[1] + fb->pitches[1] * y +
154 fb->format->cpp[1] * x - eba;
157 static inline unsigned long
158 drm_plane_state_to_vbo(struct drm_plane_state *state)
160 struct drm_framebuffer *fb = state->fb;
161 struct drm_gem_cma_object *cma_obj;
162 unsigned long eba = drm_plane_state_to_eba(state, 0);
163 int x = state->src.x1 >> 16;
164 int y = state->src.y1 >> 16;
166 cma_obj = drm_fb_cma_get_gem_obj(fb, 2);
169 x /= fb->format->hsub;
170 y /= fb->format->vsub;
172 return cma_obj->paddr + fb->offsets[2] + fb->pitches[2] * y +
173 fb->format->cpp[2] * x - eba;
176 static void ipu_plane_put_resources(struct drm_device *dev, void *ptr)
178 struct ipu_plane *ipu_plane = ptr;
180 if (!IS_ERR_OR_NULL(ipu_plane->dp))
181 ipu_dp_put(ipu_plane->dp);
182 if (!IS_ERR_OR_NULL(ipu_plane->dmfc))
183 ipu_dmfc_put(ipu_plane->dmfc);
184 if (!IS_ERR_OR_NULL(ipu_plane->ipu_ch))
185 ipu_idmac_put(ipu_plane->ipu_ch);
186 if (!IS_ERR_OR_NULL(ipu_plane->alpha_ch))
187 ipu_idmac_put(ipu_plane->alpha_ch);
190 static int ipu_plane_get_resources(struct drm_device *dev,
191 struct ipu_plane *ipu_plane)
196 ipu_plane->ipu_ch = ipu_idmac_get(ipu_plane->ipu, ipu_plane->dma);
197 if (IS_ERR(ipu_plane->ipu_ch)) {
198 ret = PTR_ERR(ipu_plane->ipu_ch);
199 DRM_ERROR("failed to get idmac channel: %d\n", ret);
203 ret = drmm_add_action_or_reset(dev, ipu_plane_put_resources, ipu_plane);
207 alpha_ch = ipu_channel_alpha_channel(ipu_plane->dma);
209 ipu_plane->alpha_ch = ipu_idmac_get(ipu_plane->ipu, alpha_ch);
210 if (IS_ERR(ipu_plane->alpha_ch)) {
211 ret = PTR_ERR(ipu_plane->alpha_ch);
212 DRM_ERROR("failed to get alpha idmac channel %d: %d\n",
218 ipu_plane->dmfc = ipu_dmfc_get(ipu_plane->ipu, ipu_plane->dma);
219 if (IS_ERR(ipu_plane->dmfc)) {
220 ret = PTR_ERR(ipu_plane->dmfc);
221 DRM_ERROR("failed to get dmfc: ret %d\n", ret);
225 if (ipu_plane->dp_flow >= 0) {
226 ipu_plane->dp = ipu_dp_get(ipu_plane->ipu, ipu_plane->dp_flow);
227 if (IS_ERR(ipu_plane->dp)) {
228 ret = PTR_ERR(ipu_plane->dp);
229 DRM_ERROR("failed to get dp flow: %d\n", ret);
237 static bool ipu_plane_separate_alpha(struct ipu_plane *ipu_plane)
239 switch (ipu_plane->base.state->fb->format->format) {
240 case DRM_FORMAT_RGB565_A8:
241 case DRM_FORMAT_BGR565_A8:
242 case DRM_FORMAT_RGB888_A8:
243 case DRM_FORMAT_BGR888_A8:
244 case DRM_FORMAT_RGBX8888_A8:
245 case DRM_FORMAT_BGRX8888_A8:
252 static void ipu_plane_enable(struct ipu_plane *ipu_plane)
255 ipu_dp_enable(ipu_plane->ipu);
256 ipu_dmfc_enable_channel(ipu_plane->dmfc);
257 ipu_idmac_enable_channel(ipu_plane->ipu_ch);
258 if (ipu_plane_separate_alpha(ipu_plane))
259 ipu_idmac_enable_channel(ipu_plane->alpha_ch);
261 ipu_dp_enable_channel(ipu_plane->dp);
264 void ipu_plane_disable(struct ipu_plane *ipu_plane, bool disable_dp_channel)
268 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
270 ret = ipu_idmac_wait_busy(ipu_plane->ipu_ch, 50);
271 if (ret == -ETIMEDOUT) {
272 DRM_ERROR("[PLANE:%d] IDMAC timeout\n",
273 ipu_plane->base.base.id);
276 if (ipu_plane->dp && disable_dp_channel)
277 ipu_dp_disable_channel(ipu_plane->dp, false);
278 ipu_idmac_disable_channel(ipu_plane->ipu_ch);
279 if (ipu_plane->alpha_ch)
280 ipu_idmac_disable_channel(ipu_plane->alpha_ch);
281 ipu_dmfc_disable_channel(ipu_plane->dmfc);
283 ipu_dp_disable(ipu_plane->ipu);
284 if (ipu_prg_present(ipu_plane->ipu))
285 ipu_prg_channel_disable(ipu_plane->ipu_ch);
288 void ipu_plane_disable_deferred(struct drm_plane *plane)
290 struct ipu_plane *ipu_plane = to_ipu_plane(plane);
292 if (ipu_plane->disabling) {
293 ipu_plane->disabling = false;
294 ipu_plane_disable(ipu_plane, false);
298 static void ipu_plane_state_reset(struct drm_plane *plane)
300 unsigned int zpos = (plane->type == DRM_PLANE_TYPE_PRIMARY) ? 0 : 1;
301 struct ipu_plane_state *ipu_state;
304 ipu_state = to_ipu_plane_state(plane->state);
305 __drm_atomic_helper_plane_destroy_state(plane->state);
310 ipu_state = kzalloc(sizeof(*ipu_state), GFP_KERNEL);
313 __drm_atomic_helper_plane_reset(plane, &ipu_state->base);
314 ipu_state->base.zpos = zpos;
315 ipu_state->base.normalized_zpos = zpos;
316 ipu_state->base.color_encoding = DRM_COLOR_YCBCR_BT601;
317 ipu_state->base.color_range = DRM_COLOR_YCBCR_LIMITED_RANGE;
321 static struct drm_plane_state *
322 ipu_plane_duplicate_state(struct drm_plane *plane)
324 struct ipu_plane_state *state;
326 if (WARN_ON(!plane->state))
329 state = kmalloc(sizeof(*state), GFP_KERNEL);
331 __drm_atomic_helper_plane_duplicate_state(plane, &state->base);
336 static void ipu_plane_destroy_state(struct drm_plane *plane,
337 struct drm_plane_state *state)
339 struct ipu_plane_state *ipu_state = to_ipu_plane_state(state);
341 __drm_atomic_helper_plane_destroy_state(state);
345 static bool ipu_plane_format_mod_supported(struct drm_plane *plane,
346 uint32_t format, uint64_t modifier)
348 struct ipu_soc *ipu = to_ipu_plane(plane)->ipu;
350 /* linear is supported for all planes and formats */
351 if (modifier == DRM_FORMAT_MOD_LINEAR)
355 * Without a PRG the possible modifiers list only includes the linear
356 * modifier, so we always take the early return from this function and
357 * only end up here if the PRG is present.
359 return ipu_prg_format_supported(ipu, format, modifier);
362 static const struct drm_plane_funcs ipu_plane_funcs = {
363 .update_plane = drm_atomic_helper_update_plane,
364 .disable_plane = drm_atomic_helper_disable_plane,
365 .reset = ipu_plane_state_reset,
366 .atomic_duplicate_state = ipu_plane_duplicate_state,
367 .atomic_destroy_state = ipu_plane_destroy_state,
368 .format_mod_supported = ipu_plane_format_mod_supported,
371 static int ipu_plane_atomic_check(struct drm_plane *plane,
372 struct drm_atomic_state *state)
374 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
376 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
378 struct drm_crtc_state *crtc_state;
379 struct device *dev = plane->dev->dev;
380 struct drm_framebuffer *fb = new_state->fb;
381 struct drm_framebuffer *old_fb = old_state->fb;
382 unsigned long eba, ubo, vbo, old_ubo, old_vbo, alpha_eba;
383 bool can_position = (plane->type == DRM_PLANE_TYPE_OVERLAY);
390 if (WARN_ON(!new_state->crtc))
394 drm_atomic_get_existing_crtc_state(state,
396 if (WARN_ON(!crtc_state))
399 ret = drm_atomic_helper_check_plane_state(new_state, crtc_state,
400 DRM_PLANE_HELPER_NO_SCALING,
401 DRM_PLANE_HELPER_NO_SCALING,
406 /* nothing to check when disabling or disabled */
407 if (!crtc_state->enable)
410 switch (plane->type) {
411 case DRM_PLANE_TYPE_PRIMARY:
412 /* full plane minimum width is 13 pixels */
413 if (drm_rect_width(&new_state->dst) < 13)
416 case DRM_PLANE_TYPE_OVERLAY:
419 dev_warn(dev, "Unsupported plane type %d\n", plane->type);
423 if (drm_rect_height(&new_state->dst) < 2)
427 * We support resizing active plane or changing its format by
428 * forcing CRTC mode change in plane's ->atomic_check callback
429 * and disabling all affected active planes in CRTC's ->atomic_disable
430 * callback. The planes will be reenabled in plane's ->atomic_update
434 (drm_rect_width(&new_state->dst) != drm_rect_width(&old_state->dst) ||
435 drm_rect_height(&new_state->dst) != drm_rect_height(&old_state->dst) ||
436 fb->format != old_fb->format))
437 crtc_state->mode_changed = true;
439 eba = drm_plane_state_to_eba(new_state, 0);
444 if (fb->pitches[0] < 1 || fb->pitches[0] > 16384)
447 if (old_fb && fb->pitches[0] != old_fb->pitches[0])
448 crtc_state->mode_changed = true;
450 if (ALIGN(fb->width, 8) * fb->format->cpp[0] >
451 fb->pitches[0] + fb->offsets[0]) {
452 dev_warn(dev, "pitch is not big enough for 8 pixels alignment");
456 switch (fb->format->format) {
457 case DRM_FORMAT_YUV420:
458 case DRM_FORMAT_YVU420:
459 case DRM_FORMAT_YUV422:
460 case DRM_FORMAT_YVU422:
461 case DRM_FORMAT_YUV444:
462 case DRM_FORMAT_YVU444:
464 * Multiplanar formats have to meet the following restrictions:
465 * - The (up to) three plane addresses are EBA, EBA+UBO, EBA+VBO
466 * - EBA, UBO and VBO are a multiple of 8
467 * - UBO and VBO are unsigned and not larger than 0xfffff8
468 * - Only EBA may be changed while scanout is active
469 * - The strides of U and V planes must be identical.
471 vbo = drm_plane_state_to_vbo(new_state);
473 if (vbo & 0x7 || vbo > 0xfffff8)
476 if (old_fb && (fb->format == old_fb->format)) {
477 old_vbo = drm_plane_state_to_vbo(old_state);
479 crtc_state->mode_changed = true;
482 if (fb->pitches[1] != fb->pitches[2])
486 case DRM_FORMAT_NV12:
487 case DRM_FORMAT_NV16:
488 ubo = drm_plane_state_to_ubo(new_state);
490 if (ubo & 0x7 || ubo > 0xfffff8)
493 if (old_fb && (fb->format == old_fb->format)) {
494 old_ubo = drm_plane_state_to_ubo(old_state);
496 crtc_state->mode_changed = true;
499 if (fb->pitches[1] < 1 || fb->pitches[1] > 16384)
502 if (old_fb && old_fb->pitches[1] != fb->pitches[1])
503 crtc_state->mode_changed = true;
506 * The x/y offsets must be even in case of horizontal/vertical
507 * chroma subsampling.
509 if (((new_state->src.x1 >> 16) & (fb->format->hsub - 1)) ||
510 ((new_state->src.y1 >> 16) & (fb->format->vsub - 1)))
513 case DRM_FORMAT_RGB565_A8:
514 case DRM_FORMAT_BGR565_A8:
515 case DRM_FORMAT_RGB888_A8:
516 case DRM_FORMAT_BGR888_A8:
517 case DRM_FORMAT_RGBX8888_A8:
518 case DRM_FORMAT_BGRX8888_A8:
519 alpha_eba = drm_plane_state_to_eba(new_state, 1);
523 if (fb->pitches[1] < 1 || fb->pitches[1] > 16384)
526 if (old_fb && old_fb->pitches[1] != fb->pitches[1])
527 crtc_state->mode_changed = true;
534 static void ipu_plane_atomic_disable(struct drm_plane *plane,
535 struct drm_atomic_state *state)
537 struct ipu_plane *ipu_plane = to_ipu_plane(plane);
540 ipu_dp_disable_channel(ipu_plane->dp, true);
541 ipu_plane->disabling = true;
544 static int ipu_chan_assign_axi_id(int ipu_chan)
547 case IPUV3_CHANNEL_MEM_BG_SYNC:
549 case IPUV3_CHANNEL_MEM_FG_SYNC:
551 case IPUV3_CHANNEL_MEM_DC_SYNC:
558 static void ipu_calculate_bursts(u32 width, u32 cpp, u32 stride,
559 u8 *burstsize, u8 *num_bursts)
561 const unsigned int width_bytes = width * cpp;
562 unsigned int npb, bursts;
564 /* Maximum number of pixels per burst without overshooting stride */
565 for (npb = 64 / cpp; npb > 0; --npb) {
566 if (round_up(width_bytes, npb * cpp) <= stride)
571 /* Maximum number of consecutive bursts without overshooting stride */
572 for (bursts = 8; bursts > 1; bursts /= 2) {
573 if (round_up(width_bytes, npb * cpp * bursts) <= stride)
576 *num_bursts = bursts;
579 static void ipu_plane_atomic_update(struct drm_plane *plane,
580 struct drm_atomic_state *state)
582 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
584 struct ipu_plane *ipu_plane = to_ipu_plane(plane);
585 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
587 struct ipu_plane_state *ipu_state = to_ipu_plane_state(new_state);
588 struct drm_crtc_state *crtc_state = new_state->crtc->state;
589 struct drm_framebuffer *fb = new_state->fb;
590 struct drm_rect *dst = &new_state->dst;
591 unsigned long eba, ubo, vbo;
592 unsigned long alpha_eba = 0;
593 enum ipu_color_space ics;
594 unsigned int axi_id = 0;
595 const struct drm_format_info *info;
596 u8 burstsize, num_bursts;
600 if (ipu_plane->dp_flow == IPU_DP_FLOW_SYNC_FG)
601 ipu_dp_set_window_pos(ipu_plane->dp, dst->x1, dst->y1);
603 switch (ipu_plane->dp_flow) {
604 case IPU_DP_FLOW_SYNC_BG:
605 if (new_state->normalized_zpos == 1) {
606 ipu_dp_set_global_alpha(ipu_plane->dp,
607 !fb->format->has_alpha, 0xff,
610 ipu_dp_set_global_alpha(ipu_plane->dp, true, 0, true);
613 case IPU_DP_FLOW_SYNC_FG:
614 if (new_state->normalized_zpos == 1) {
615 ipu_dp_set_global_alpha(ipu_plane->dp,
616 !fb->format->has_alpha, 0xff,
622 eba = drm_plane_state_to_eba(new_state, 0);
625 * Configure PRG channel and attached PRE, this changes the EBA to an
626 * internal SRAM location.
628 if (ipu_state->use_pre) {
629 axi_id = ipu_chan_assign_axi_id(ipu_plane->dma);
630 ipu_prg_channel_configure(ipu_plane->ipu_ch, axi_id,
631 ipu_src_rect_width(new_state),
632 drm_rect_height(&new_state->src) >> 16,
633 fb->pitches[0], fb->format->format,
637 if (!old_state->fb ||
638 old_state->fb->format->format != fb->format->format ||
639 old_state->color_encoding != new_state->color_encoding ||
640 old_state->color_range != new_state->color_range) {
641 ics = ipu_drm_fourcc_to_colorspace(fb->format->format);
642 switch (ipu_plane->dp_flow) {
643 case IPU_DP_FLOW_SYNC_BG:
644 ipu_dp_setup_channel(ipu_plane->dp, new_state->color_encoding,
645 new_state->color_range, ics,
646 IPUV3_COLORSPACE_RGB);
648 case IPU_DP_FLOW_SYNC_FG:
649 ipu_dp_setup_channel(ipu_plane->dp, new_state->color_encoding,
650 new_state->color_range, ics,
651 IPUV3_COLORSPACE_UNKNOWN);
656 if (old_state->fb && !drm_atomic_crtc_needs_modeset(crtc_state)) {
657 /* nothing to do if PRE is used */
658 if (ipu_state->use_pre)
660 active = ipu_idmac_get_current_buffer(ipu_plane->ipu_ch);
661 ipu_cpmem_set_buffer(ipu_plane->ipu_ch, !active, eba);
662 ipu_idmac_select_buffer(ipu_plane->ipu_ch, !active);
663 if (ipu_plane_separate_alpha(ipu_plane)) {
664 active = ipu_idmac_get_current_buffer(ipu_plane->alpha_ch);
665 ipu_cpmem_set_buffer(ipu_plane->alpha_ch, !active,
667 ipu_idmac_select_buffer(ipu_plane->alpha_ch, !active);
672 ics = ipu_drm_fourcc_to_colorspace(fb->format->format);
673 switch (ipu_plane->dp_flow) {
674 case IPU_DP_FLOW_SYNC_BG:
675 ipu_dp_setup_channel(ipu_plane->dp, DRM_COLOR_YCBCR_BT601,
676 DRM_COLOR_YCBCR_LIMITED_RANGE, ics,
677 IPUV3_COLORSPACE_RGB);
679 case IPU_DP_FLOW_SYNC_FG:
680 ipu_dp_setup_channel(ipu_plane->dp, DRM_COLOR_YCBCR_BT601,
681 DRM_COLOR_YCBCR_LIMITED_RANGE, ics,
682 IPUV3_COLORSPACE_UNKNOWN);
686 ipu_dmfc_config_wait4eot(ipu_plane->dmfc, drm_rect_width(dst));
688 width = ipu_src_rect_width(new_state);
689 height = drm_rect_height(&new_state->src) >> 16;
690 info = drm_format_info(fb->format->format);
691 ipu_calculate_bursts(width, info->cpp[0], fb->pitches[0],
692 &burstsize, &num_bursts);
694 ipu_cpmem_zero(ipu_plane->ipu_ch);
695 ipu_cpmem_set_resolution(ipu_plane->ipu_ch, width, height);
696 ipu_cpmem_set_fmt(ipu_plane->ipu_ch, fb->format->format);
697 ipu_cpmem_set_burstsize(ipu_plane->ipu_ch, burstsize);
698 ipu_cpmem_set_high_priority(ipu_plane->ipu_ch);
699 ipu_idmac_enable_watermark(ipu_plane->ipu_ch, true);
700 ipu_idmac_set_double_buffer(ipu_plane->ipu_ch, 1);
701 ipu_cpmem_set_stride(ipu_plane->ipu_ch, fb->pitches[0]);
702 ipu_cpmem_set_axi_id(ipu_plane->ipu_ch, axi_id);
704 switch (fb->format->format) {
705 case DRM_FORMAT_YUV420:
706 case DRM_FORMAT_YVU420:
707 case DRM_FORMAT_YUV422:
708 case DRM_FORMAT_YVU422:
709 case DRM_FORMAT_YUV444:
710 case DRM_FORMAT_YVU444:
711 ubo = drm_plane_state_to_ubo(new_state);
712 vbo = drm_plane_state_to_vbo(new_state);
713 if (fb->format->format == DRM_FORMAT_YVU420 ||
714 fb->format->format == DRM_FORMAT_YVU422 ||
715 fb->format->format == DRM_FORMAT_YVU444)
718 ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch,
719 fb->pitches[1], ubo, vbo);
721 dev_dbg(ipu_plane->base.dev->dev,
722 "phy = %lu %lu %lu, x = %d, y = %d", eba, ubo, vbo,
723 new_state->src.x1 >> 16, new_state->src.y1 >> 16);
725 case DRM_FORMAT_NV12:
726 case DRM_FORMAT_NV16:
727 ubo = drm_plane_state_to_ubo(new_state);
729 ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch,
730 fb->pitches[1], ubo, ubo);
732 dev_dbg(ipu_plane->base.dev->dev,
733 "phy = %lu %lu, x = %d, y = %d", eba, ubo,
734 new_state->src.x1 >> 16, new_state->src.y1 >> 16);
736 case DRM_FORMAT_RGB565_A8:
737 case DRM_FORMAT_BGR565_A8:
738 case DRM_FORMAT_RGB888_A8:
739 case DRM_FORMAT_BGR888_A8:
740 case DRM_FORMAT_RGBX8888_A8:
741 case DRM_FORMAT_BGRX8888_A8:
742 alpha_eba = drm_plane_state_to_eba(new_state, 1);
745 dev_dbg(ipu_plane->base.dev->dev, "phys = %lu %lu, x = %d, y = %d",
746 eba, alpha_eba, new_state->src.x1 >> 16,
747 new_state->src.y1 >> 16);
749 ipu_cpmem_set_burstsize(ipu_plane->ipu_ch, 16);
751 ipu_cpmem_zero(ipu_plane->alpha_ch);
752 ipu_cpmem_set_resolution(ipu_plane->alpha_ch,
753 ipu_src_rect_width(new_state),
754 drm_rect_height(&new_state->src) >> 16);
755 ipu_cpmem_set_format_passthrough(ipu_plane->alpha_ch, 8);
756 ipu_cpmem_set_high_priority(ipu_plane->alpha_ch);
757 ipu_idmac_set_double_buffer(ipu_plane->alpha_ch, 1);
758 ipu_cpmem_set_stride(ipu_plane->alpha_ch, fb->pitches[1]);
759 ipu_cpmem_set_burstsize(ipu_plane->alpha_ch, 16);
760 ipu_cpmem_set_buffer(ipu_plane->alpha_ch, 0, alpha_eba);
761 ipu_cpmem_set_buffer(ipu_plane->alpha_ch, 1, alpha_eba);
764 dev_dbg(ipu_plane->base.dev->dev, "phys = %lu, x = %d, y = %d",
765 eba, new_state->src.x1 >> 16, new_state->src.y1 >> 16);
768 ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 0, eba);
769 ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 1, eba);
770 ipu_idmac_lock_enable(ipu_plane->ipu_ch, num_bursts);
771 ipu_plane_enable(ipu_plane);
774 static const struct drm_plane_helper_funcs ipu_plane_helper_funcs = {
775 .prepare_fb = drm_gem_plane_helper_prepare_fb,
776 .atomic_check = ipu_plane_atomic_check,
777 .atomic_disable = ipu_plane_atomic_disable,
778 .atomic_update = ipu_plane_atomic_update,
781 bool ipu_plane_atomic_update_pending(struct drm_plane *plane)
783 struct ipu_plane *ipu_plane = to_ipu_plane(plane);
784 struct drm_plane_state *state = plane->state;
785 struct ipu_plane_state *ipu_state = to_ipu_plane_state(state);
787 /* disabled crtcs must not block the update */
791 if (ipu_state->use_pre)
792 return ipu_prg_channel_configure_pending(ipu_plane->ipu_ch);
795 * Pretend no update is pending in the non-PRE/PRG case. For this to
796 * happen, an atomic update would have to be deferred until after the
797 * start of the next frame and simultaneously interrupt latency would
798 * have to be high enough to let the atomic update finish and issue an
799 * event before the previous end of frame interrupt handler can be
804 int ipu_planes_assign_pre(struct drm_device *dev,
805 struct drm_atomic_state *state)
807 struct drm_crtc_state *old_crtc_state, *crtc_state;
808 struct drm_plane_state *plane_state;
809 struct ipu_plane_state *ipu_state;
810 struct ipu_plane *ipu_plane;
811 struct drm_plane *plane;
812 struct drm_crtc *crtc;
813 int available_pres = ipu_prg_max_active_channels();
816 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
817 ret = drm_atomic_add_affected_planes(state, crtc);
823 * We are going over the planes in 2 passes: first we assign PREs to
824 * planes with a tiling modifier, which need the PREs to resolve into
825 * linear. Any failure to assign a PRE there is fatal. In the second
826 * pass we try to assign PREs to linear FBs, to improve memory access
827 * patterns for them. Failure at this point is non-fatal, as we can
828 * scan out linear FBs without a PRE.
830 for_each_new_plane_in_state(state, plane, plane_state, i) {
831 ipu_state = to_ipu_plane_state(plane_state);
832 ipu_plane = to_ipu_plane(plane);
834 if (!plane_state->fb) {
835 ipu_state->use_pre = false;
839 if (!(plane_state->fb->flags & DRM_MODE_FB_MODIFIERS) ||
840 plane_state->fb->modifier == DRM_FORMAT_MOD_LINEAR)
843 if (!ipu_prg_present(ipu_plane->ipu) || !available_pres)
846 if (!ipu_prg_format_supported(ipu_plane->ipu,
847 plane_state->fb->format->format,
848 plane_state->fb->modifier))
851 ipu_state->use_pre = true;
855 for_each_new_plane_in_state(state, plane, plane_state, i) {
856 ipu_state = to_ipu_plane_state(plane_state);
857 ipu_plane = to_ipu_plane(plane);
859 if (!plane_state->fb) {
860 ipu_state->use_pre = false;
864 if ((plane_state->fb->flags & DRM_MODE_FB_MODIFIERS) &&
865 plane_state->fb->modifier != DRM_FORMAT_MOD_LINEAR)
868 /* make sure that modifier is initialized */
869 plane_state->fb->modifier = DRM_FORMAT_MOD_LINEAR;
871 if (ipu_prg_present(ipu_plane->ipu) && available_pres &&
872 ipu_prg_format_supported(ipu_plane->ipu,
873 plane_state->fb->format->format,
874 plane_state->fb->modifier)) {
875 ipu_state->use_pre = true;
878 ipu_state->use_pre = false;
885 struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu,
886 int dma, int dp, unsigned int possible_crtcs,
887 enum drm_plane_type type)
889 struct ipu_plane *ipu_plane;
890 const uint64_t *modifiers = ipu_format_modifiers;
891 unsigned int zpos = (type == DRM_PLANE_TYPE_PRIMARY) ? 0 : 1;
892 unsigned int format_count;
893 const uint32_t *formats;
896 DRM_DEBUG_KMS("channel %d, dp flow %d, possible_crtcs=0x%x\n",
897 dma, dp, possible_crtcs);
899 if (dp == IPU_DP_FLOW_SYNC_BG || dp == IPU_DP_FLOW_SYNC_FG) {
900 formats = ipu_plane_all_formats;
901 format_count = ARRAY_SIZE(ipu_plane_all_formats);
903 formats = ipu_plane_rgb_formats;
904 format_count = ARRAY_SIZE(ipu_plane_rgb_formats);
907 if (ipu_prg_present(ipu))
908 modifiers = pre_format_modifiers;
910 ipu_plane = drmm_universal_plane_alloc(dev, struct ipu_plane, base,
911 possible_crtcs, &ipu_plane_funcs,
912 formats, format_count, modifiers,
914 if (IS_ERR(ipu_plane)) {
915 DRM_ERROR("failed to allocate and initialize %s plane\n",
916 zpos ? "overlay" : "primary");
920 ipu_plane->ipu = ipu;
921 ipu_plane->dma = dma;
922 ipu_plane->dp_flow = dp;
924 drm_plane_helper_add(&ipu_plane->base, &ipu_plane_helper_funcs);
926 if (dp == IPU_DP_FLOW_SYNC_BG || dp == IPU_DP_FLOW_SYNC_FG)
927 ret = drm_plane_create_zpos_property(&ipu_plane->base, zpos, 0,
930 ret = drm_plane_create_zpos_immutable_property(&ipu_plane->base,
935 ret = drm_plane_create_color_properties(&ipu_plane->base,
936 BIT(DRM_COLOR_YCBCR_BT601) |
937 BIT(DRM_COLOR_YCBCR_BT709),
938 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE),
939 DRM_COLOR_YCBCR_BT601,
940 DRM_COLOR_YCBCR_LIMITED_RANGE);
944 ret = ipu_plane_get_resources(dev, ipu_plane);
946 DRM_ERROR("failed to get %s plane resources: %pe\n",
947 zpos ? "overlay" : "primary", &ret);