drivers/gpu/drm/imx/imx-ldb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * i.MX drm driver - LVDS display bridge
   4  *
   5  * Copyright (C) 2012 Sascha Hauer, Pengutronix
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/component.h>
  10 #include <linux/mfd/syscon.h>
  11 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  12 #include <linux/module.h>
  13 #include <linux/of_device.h>
  14 #include <linux/of_graph.h>
  15 #include <linux/regmap.h>
  16 #include <linux/videodev2.h>
  17
  18 #include <video/of_display_timing.h>
  19 #include <video/of_videomode.h>
  20
  21 #include <drm/drm_atomic.h>
  22 #include <drm/drm_atomic_helper.h>
  23 #include <drm/drm_bridge.h>
  24 #include <drm/drm_fb_helper.h>
  25 #include <drm/drm_managed.h>
  26 #include <drm/drm_of.h>
  27 #include <drm/drm_panel.h>
  28 #include <drm/drm_print.h>
  29 #include <drm/drm_probe_helper.h>
  30 #include <drm/drm_simple_kms_helper.h>
  31
  32 #include "imx-drm.h"
  33
  34 #define DRIVER_NAME "imx-ldb"
  35
  36 #define LDB_CH0_MODE_EN_TO_DI0          (1 << 0)
  37 #define LDB_CH0_MODE_EN_TO_DI1          (3 << 0)
  38 #define LDB_CH0_MODE_EN_MASK            (3 << 0)
  39 #define LDB_CH1_MODE_EN_TO_DI0          (1 << 2)
  40 #define LDB_CH1_MODE_EN_TO_DI1          (3 << 2)
  41 #define LDB_CH1_MODE_EN_MASK            (3 << 2)
  42 #define LDB_SPLIT_MODE_EN               (1 << 4)
  43 #define LDB_DATA_WIDTH_CH0_24           (1 << 5)
  44 #define LDB_BIT_MAP_CH0_JEIDA           (1 << 6)
  45 #define LDB_DATA_WIDTH_CH1_24           (1 << 7)
  46 #define LDB_BIT_MAP_CH1_JEIDA           (1 << 8)
  47 #define LDB_DI0_VS_POL_ACT_LOW          (1 << 9)
  48 #define LDB_DI1_VS_POL_ACT_LOW          (1 << 10)
  49 #define LDB_BGREF_RMODE_INT             (1 << 15)
  50
  51 struct imx_ldb_channel;
  52
  53 struct imx_ldb_encoder {
  54         struct drm_connector connector;
  55         struct drm_encoder encoder;
  56         struct imx_ldb_channel *channel;
  57 };
  58
  59 struct imx_ldb;
  60
  61 struct imx_ldb_channel {
  62         struct imx_ldb *ldb;
  63
  64         /* Defines what is connected to the ldb, only one at a time */
  65         struct drm_panel *panel;
  66         struct drm_bridge *bridge;
  67
  68         struct device_node *child;
  69         struct i2c_adapter *ddc;
  70         int chno;
  71         void *edid;
  72         struct drm_display_mode mode;
  73         int mode_valid;
  74         u32 bus_format;
  75         u32 bus_flags;
  76 };
  77
  78 static inline struct imx_ldb_channel *con_to_imx_ldb_ch(struct drm_connector *c)
  79 {
  80         return container_of(c, struct imx_ldb_encoder, connector)->channel;
  81 }
  82
  83 static inline struct imx_ldb_channel *enc_to_imx_ldb_ch(struct drm_encoder *e)
  84 {
  85         return container_of(e, struct imx_ldb_encoder, encoder)->channel;
  86 }
  87
  88 struct bus_mux {
  89         int reg;
  90         int shift;
  91         int mask;
  92 };
  93
  94 struct imx_ldb {
  95         struct regmap *regmap;
  96         struct device *dev;
  97         struct imx_ldb_channel channel[2];
  98         struct clk *clk[2]; /* our own clock */
  99         struct clk *clk_sel[4]; /* parent of display clock */
 100         struct clk *clk_parent[4]; /* original parent of clk_sel */
 101         struct clk *clk_pll[2]; /* upstream clock we can adjust */
 102         u32 ldb_ctrl;
 103         const struct bus_mux *lvds_mux;
 104 };
 105
 106 static void imx_ldb_ch_set_bus_format(struct imx_ldb_channel *imx_ldb_ch,
 107                                       u32 bus_format)
 108 {
 109         struct imx_ldb *ldb = imx_ldb_ch->ldb;
 110         int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
 111
 112         switch (bus_format) {
 113         case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
 114                 break;
 115         case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
 116                 if (imx_ldb_ch->chno == 0 || dual)
 117                         ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24;
 118                 if (imx_ldb_ch->chno == 1 || dual)
 119                         ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24;
 120                 break;
 121         case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
 122                 if (imx_ldb_ch->chno == 0 || dual)
 123                         ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 |
 124                                          LDB_BIT_MAP_CH0_JEIDA;
 125                 if (imx_ldb_ch->chno == 1 || dual)
 126                         ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 |
 127                                          LDB_BIT_MAP_CH1_JEIDA;
 128                 break;
 129         }
 130 }
 131
 132 static int imx_ldb_connector_get_modes(struct drm_connector *connector)
 133 {
 134         struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
 135         int num_modes;
 136
 137         num_modes = drm_panel_get_modes(imx_ldb_ch->panel, connector);
 138         if (num_modes > 0)
 139                 return num_modes;
 140
 141         if (!imx_ldb_ch->edid && imx_ldb_ch->ddc)
 142                 imx_ldb_ch->edid = drm_get_edid(connector, imx_ldb_ch->ddc);
 143
 144         if (imx_ldb_ch->edid) {
 145                 drm_connector_update_edid_property(connector,
 146                                                         imx_ldb_ch->edid);
 147                 num_modes = drm_add_edid_modes(connector, imx_ldb_ch->edid);
 148         }
 149
 150         if (imx_ldb_ch->mode_valid) {
 151                 struct drm_display_mode *mode;
 152
 153                 mode = drm_mode_create(connector->dev);
 154                 if (!mode)
 155                         return -EINVAL;
 156                 drm_mode_copy(mode, &imx_ldb_ch->mode);
 157                 mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
 158                 drm_mode_probed_add(connector, mode);
 159                 num_modes++;
 160         }
 161
 162         return num_modes;
 163 }
 164
 165 static void imx_ldb_set_clock(struct imx_ldb *ldb, int mux, int chno,
 166                 unsigned long serial_clk, unsigned long di_clk)
 167 {
 168         int ret;
 169
 170         dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
 171                         clk_get_rate(ldb->clk_pll[chno]), serial_clk);
 172         clk_set_rate(ldb->clk_pll[chno], serial_clk);
 173
 174         dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
 175                         clk_get_rate(ldb->clk_pll[chno]));
 176
 177         dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
 178                         clk_get_rate(ldb->clk[chno]),
 179                         (long int)di_clk);
 180         clk_set_rate(ldb->clk[chno], di_clk);
 181
 182         dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
 183                         clk_get_rate(ldb->clk[chno]));
 184
 185         /* set display clock mux to LDB input clock */
 186         ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]);
 187         if (ret)
 188                 dev_err(ldb->dev,
 189                         "unable to set di%d parent clock to ldb_di%d\n", mux,
 190                         chno);
 191 }
 192
 193 static void imx_ldb_encoder_enable(struct drm_encoder *encoder)
 194 {
 195         struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
 196         struct imx_ldb *ldb = imx_ldb_ch->ldb;
 197         int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
 198         int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder);
 199
 200         if (mux < 0 || mux >= ARRAY_SIZE(ldb->clk_sel)) {
 201                 dev_warn(ldb->dev, "%s: invalid mux %d\n", __func__, mux);
 202                 return;
 203         }
 204
 205         drm_panel_prepare(imx_ldb_ch->panel);
 206
 207         if (dual) {
 208                 clk_set_parent(ldb->clk_sel[mux], ldb->clk[0]);
 209                 clk_set_parent(ldb->clk_sel[mux], ldb->clk[1]);
 210
 211                 clk_prepare_enable(ldb->clk[0]);
 212                 clk_prepare_enable(ldb->clk[1]);
 213         } else {
 214                 clk_set_parent(ldb->clk_sel[mux], ldb->clk[imx_ldb_ch->chno]);
 215         }
 216
 217         if (imx_ldb_ch == &ldb->channel[0] || dual) {
 218                 ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
 219                 if (mux == 0 || ldb->lvds_mux)
 220                         ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0;
 221                 else if (mux == 1)
 222                         ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI1;
 223         }
 224         if (imx_ldb_ch == &ldb->channel[1] || dual) {
 225                 ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
 226                 if (mux == 1 || ldb->lvds_mux)
 227                         ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI1;
 228                 else if (mux == 0)
 229                         ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0;
 230         }
 231
 232         if (ldb->lvds_mux) {
 233                 const struct bus_mux *lvds_mux = NULL;
 234
 235                 if (imx_ldb_ch == &ldb->channel[0])
 236                         lvds_mux = &ldb->lvds_mux[0];
 237                 else if (imx_ldb_ch == &ldb->channel[1])
 238                         lvds_mux = &ldb->lvds_mux[1];
 239
 240                 regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask,
 241                                    mux << lvds_mux->shift);
 242         }
 243
 244         regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
 245
 246         drm_panel_enable(imx_ldb_ch->panel);
 247 }
 248
 249 static void
 250 imx_ldb_encoder_atomic_mode_set(struct drm_encoder *encoder,
 251                                 struct drm_crtc_state *crtc_state,
 252                                 struct drm_connector_state *connector_state)
 253 {
 254         struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
 255         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
 256         struct imx_ldb *ldb = imx_ldb_ch->ldb;
 257         int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
 258         unsigned long serial_clk;
 259         unsigned long di_clk = mode->clock * 1000;
 260         int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder);
 261         u32 bus_format = imx_ldb_ch->bus_format;
 262
 263         if (mux < 0 || mux >= ARRAY_SIZE(ldb->clk_sel)) {
 264                 dev_warn(ldb->dev, "%s: invalid mux %d\n", __func__, mux);
 265                 return;
 266         }
 267
 268         if (mode->clock > 170000) {
 269                 dev_warn(ldb->dev,
 270                          "%s: mode exceeds 170 MHz pixel clock\n", __func__);
 271         }
 272         if (mode->clock > 85000 && !dual) {
 273                 dev_warn(ldb->dev,
 274                          "%s: mode exceeds 85 MHz pixel clock\n", __func__);
 275         }
 276
 277         if (!IS_ALIGNED(mode->hdisplay, 8)) {
 278                 dev_warn(ldb->dev,
 279                          "%s: hdisplay does not align to 8 byte\n", __func__);
 280         }
 281
 282         if (dual) {
 283                 serial_clk = 3500UL * mode->clock;
 284                 imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk);
 285                 imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk);
 286         } else {
 287                 serial_clk = 7000UL * mode->clock;
 288                 imx_ldb_set_clock(ldb, mux, imx_ldb_ch->chno, serial_clk,
 289                                   di_clk);
 290         }
 291
 292         /* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */
 293         if (imx_ldb_ch == &ldb->channel[0] || dual) {
 294                 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 295                         ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW;
 296                 else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 297                         ldb->ldb_ctrl &= ~LDB_DI0_VS_POL_ACT_LOW;
 298         }
 299         if (imx_ldb_ch == &ldb->channel[1] || dual) {
 300                 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 301                         ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW;
 302                 else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 303                         ldb->ldb_ctrl &= ~LDB_DI1_VS_POL_ACT_LOW;
 304         }
 305
 306         if (!bus_format) {
 307                 struct drm_connector *connector = connector_state->connector;
 308                 struct drm_display_info *di = &connector->display_info;
 309
 310                 if (di->num_bus_formats)
 311                         bus_format = di->bus_formats[0];
 312         }
 313         imx_ldb_ch_set_bus_format(imx_ldb_ch, bus_format);
 314 }
 315
 316 static void imx_ldb_encoder_disable(struct drm_encoder *encoder)
 317 {
 318         struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
 319         struct imx_ldb *ldb = imx_ldb_ch->ldb;
 320         int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
 321         int mux, ret;
 322
 323         drm_panel_disable(imx_ldb_ch->panel);
 324
 325         if (imx_ldb_ch == &ldb->channel[0] || dual)
 326                 ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
 327         if (imx_ldb_ch == &ldb->channel[1] || dual)
 328                 ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
 329
 330         regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
 331
 332         if (dual) {
 333                 clk_disable_unprepare(ldb->clk[0]);
 334                 clk_disable_unprepare(ldb->clk[1]);
 335         }
 336
 337         if (ldb->lvds_mux) {
 338                 const struct bus_mux *lvds_mux = NULL;
 339
 340                 if (imx_ldb_ch == &ldb->channel[0])
 341                         lvds_mux = &ldb->lvds_mux[0];
 342                 else if (imx_ldb_ch == &ldb->channel[1])
 343                         lvds_mux = &ldb->lvds_mux[1];
 344
 345                 regmap_read(ldb->regmap, lvds_mux->reg, &mux);
 346                 mux &= lvds_mux->mask;
 347                 mux >>= lvds_mux->shift;
 348         } else {
 349                 mux = (imx_ldb_ch == &ldb->channel[0]) ? 0 : 1;
 350         }
 351
 352         /* set display clock mux back to original input clock */
 353         ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]);
 354         if (ret)
 355                 dev_err(ldb->dev,
 356                         "unable to set di%d parent clock to original parent\n",
 357                         mux);
 358
 359         drm_panel_unprepare(imx_ldb_ch->panel);
 360 }
 361
 362 static int imx_ldb_encoder_atomic_check(struct drm_encoder *encoder,
 363                                         struct drm_crtc_state *crtc_state,
 364                                         struct drm_connector_state *conn_state)
 365 {
 366         struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
 367         struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
 368         struct drm_display_info *di = &conn_state->connector->display_info;
 369         u32 bus_format = imx_ldb_ch->bus_format;
 370
 371         /* Bus format description in DT overrides connector display info. */
 372         if (!bus_format && di->num_bus_formats) {
 373                 bus_format = di->bus_formats[0];
 374                 imx_crtc_state->bus_flags = di->bus_flags;
 375         } else {
 376                 bus_format = imx_ldb_ch->bus_format;
 377                 imx_crtc_state->bus_flags = imx_ldb_ch->bus_flags;
 378         }
 379         switch (bus_format) {
 380         case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
 381                 imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB666_1X18;
 382                 break;
 383         case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
 384         case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
 385                 imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
 386                 break;
 387         default:
 388                 return -EINVAL;
 389         }
 390
 391         imx_crtc_state->di_hsync_pin = 2;
 392         imx_crtc_state->di_vsync_pin = 3;
 393
 394         return 0;
 395 }
 396
 397
 398 static const struct drm_connector_funcs imx_ldb_connector_funcs = {
 399         .fill_modes = drm_helper_probe_single_connector_modes,
 400         .destroy = imx_drm_connector_destroy,
 401         .reset = drm_atomic_helper_connector_reset,
 402         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 403         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 404 };
 405
 406 static const struct drm_connector_helper_funcs imx_ldb_connector_helper_funcs = {
 407         .get_modes = imx_ldb_connector_get_modes,
 408 };
 409
 410 static const struct drm_encoder_helper_funcs imx_ldb_encoder_helper_funcs = {
 411         .atomic_mode_set = imx_ldb_encoder_atomic_mode_set,
 412         .enable = imx_ldb_encoder_enable,
 413         .disable = imx_ldb_encoder_disable,
 414         .atomic_check = imx_ldb_encoder_atomic_check,
 415 };
 416
 417 static int imx_ldb_get_clk(struct imx_ldb *ldb, int chno)
 418 {
 419         char clkname[16];
 420
 421         snprintf(clkname, sizeof(clkname), "di%d", chno);
 422         ldb->clk[chno] = devm_clk_get(ldb->dev, clkname);
 423         if (IS_ERR(ldb->clk[chno]))
 424                 return PTR_ERR(ldb->clk[chno]);
 425
 426         snprintf(clkname, sizeof(clkname), "di%d_pll", chno);
 427         ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname);
 428
 429         return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]);
 430 }
 431
 432 static int imx_ldb_register(struct drm_device *drm,
 433         struct imx_ldb_channel *imx_ldb_ch)
 434 {
 435         struct imx_ldb *ldb = imx_ldb_ch->ldb;
 436         struct imx_ldb_encoder *ldb_encoder;
 437         struct drm_connector *connector;
 438         struct drm_encoder *encoder;
 439         int ret;
 440
 441         ldb_encoder = drmm_simple_encoder_alloc(drm, struct imx_ldb_encoder,
 442                                                 encoder, DRM_MODE_ENCODER_LVDS);
 443         if (IS_ERR(ldb_encoder))
 444                 return PTR_ERR(ldb_encoder);
 445
 446         ldb_encoder->channel = imx_ldb_ch;
 447         connector = &ldb_encoder->connector;
 448         encoder = &ldb_encoder->encoder;
 449
 450         ret = imx_drm_encoder_parse_of(drm, encoder, imx_ldb_ch->child);
 451         if (ret)
 452                 return ret;
 453
 454         ret = imx_ldb_get_clk(ldb, imx_ldb_ch->chno);
 455         if (ret)
 456                 return ret;
 457
 458         if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
 459                 ret = imx_ldb_get_clk(ldb, 1);
 460                 if (ret)
 461                         return ret;
 462         }
 463
 464         drm_encoder_helper_add(encoder, &imx_ldb_encoder_helper_funcs);
 465
 466         if (imx_ldb_ch->bridge) {
 467                 ret = drm_bridge_attach(encoder, imx_ldb_ch->bridge, NULL, 0);
 468                 if (ret)
 469                         return ret;
 470         } else {
 471                 /*
 472                  * We want to add the connector whenever there is no bridge
 473                  * that brings its own, not only when there is a panel. For
 474                  * historical reasons, the ldb driver can also work without
 475                  * a panel.
 476                  */
 477                 drm_connector_helper_add(connector,
 478                                          &imx_ldb_connector_helper_funcs);
 479                 drm_connector_init_with_ddc(drm, connector,
 480                                             &imx_ldb_connector_funcs,
 481                                             DRM_MODE_CONNECTOR_LVDS,
 482                                             imx_ldb_ch->ddc);
 483                 drm_connector_attach_encoder(connector, encoder);
 484         }
 485
 486         return 0;
 487 }
 488
 489 struct imx_ldb_bit_mapping {
 490         u32 bus_format;
 491         u32 datawidth;
 492         const char * const mapping;
 493 };
 494
 495 static const struct imx_ldb_bit_mapping imx_ldb_bit_mappings[] = {
 496         { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,  18, "spwg" },
 497         { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,  24, "spwg" },
 498         { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, "jeida" },
 499 };
 500
 501 static u32 of_get_bus_format(struct device *dev, struct device_node *np)
 502 {
 503         const char *bm;
 504         u32 datawidth = 0;
 505         int ret, i;
 506
 507         ret = of_property_read_string(np, "fsl,data-mapping", &bm);
 508         if (ret < 0)
 509                 return ret;
 510
 511         of_property_read_u32(np, "fsl,data-width", &datawidth);
 512
 513         for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++) {
 514                 if (!strcasecmp(bm, imx_ldb_bit_mappings[i].mapping) &&
 515                     datawidth == imx_ldb_bit_mappings[i].datawidth)
 516                         return imx_ldb_bit_mappings[i].bus_format;
 517         }
 518
 519         dev_err(dev, "invalid data mapping: %d-bit \"%s\"\n", datawidth, bm);
 520
 521         return -ENOENT;
 522 }
 523
 524 static struct bus_mux imx6q_lvds_mux[2] = {
 525         {
 526                 .reg = IOMUXC_GPR3,
 527                 .shift = 6,
 528                 .mask = IMX6Q_GPR3_LVDS0_MUX_CTL_MASK,
 529         }, {
 530                 .reg = IOMUXC_GPR3,
 531                 .shift = 8,
 532                 .mask = IMX6Q_GPR3_LVDS1_MUX_CTL_MASK,
 533         }
 534 };
 535
 536 /*
 537  * For a device declaring compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb",
 538  * of_match_device will walk through this list and take the first entry
 539  * matching any of its compatible values. Therefore, the more generic
 540  * entries (in this case fsl,imx53-ldb) need to be ordered last.
 541  */
 542 static const struct of_device_id imx_ldb_dt_ids[] = {
 543         { .compatible = "fsl,imx6q-ldb", .data = imx6q_lvds_mux, },
 544         { .compatible = "fsl,imx53-ldb", .data = NULL, },
 545         { }
 546 };
 547 MODULE_DEVICE_TABLE(of, imx_ldb_dt_ids);
 548
 549 static int imx_ldb_panel_ddc(struct device *dev,
 550                 struct imx_ldb_channel *channel, struct device_node *child)
 551 {
 552         struct device_node *ddc_node;
 553         const u8 *edidp;
 554         int ret;
 555
 556         ddc_node = of_parse_phandle(child, "ddc-i2c-bus", 0);
 557         if (ddc_node) {
 558                 channel->ddc = of_find_i2c_adapter_by_node(ddc_node);
 559                 of_node_put(ddc_node);
 560                 if (!channel->ddc) {
 561                         dev_warn(dev, "failed to get ddc i2c adapter\n");
 562                         return -EPROBE_DEFER;
 563                 }
 564         }
 565
 566         if (!channel->ddc) {
 567                 int edid_len;
 568
 569                 /* if no DDC available, fallback to hardcoded EDID */
 570                 dev_dbg(dev, "no ddc available\n");
 571
 572                 edidp = of_get_property(child, "edid", &edid_len);
 573                 if (edidp) {
 574                         channel->edid = kmemdup(edidp, edid_len, GFP_KERNEL);
 575                         if (!channel->edid)
 576                                 return -ENOMEM;
 577                 } else if (!channel->panel) {
 578                         /* fallback to display-timings node */
 579                         ret = of_get_drm_display_mode(child,
 580                                                       &channel->mode,
 581                                                       &channel->bus_flags,
 582                                                       OF_USE_NATIVE_MODE);
 583                         if (!ret)
 584                                 channel->mode_valid = 1;
 585                 }
 586         }
 587         return 0;
 588 }
 589
 590 static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
 591 {
 592         struct drm_device *drm = data;
 593         struct imx_ldb *imx_ldb = dev_get_drvdata(dev);
 594         int ret;
 595         int i;
 596
 597         for (i = 0; i < 2; i++) {
 598                 struct imx_ldb_channel *channel = &imx_ldb->channel[i];
 599
 600                 if (!channel->ldb)
 601                         continue;
 602
 603                 ret = imx_ldb_register(drm, channel);
 604                 if (ret)
 605                         return ret;
 606         }
 607
 608         return 0;
 609 }
 610
 611 static const struct component_ops imx_ldb_ops = {
 612         .bind   = imx_ldb_bind,
 613 };
 614
 615 static int imx_ldb_probe(struct platform_device *pdev)
 616 {
 617         struct device *dev = &pdev->dev;
 618         struct device_node *np = dev->of_node;
 619         const struct of_device_id *of_id = of_match_device(imx_ldb_dt_ids, dev);
 620         struct device_node *child;
 621         struct imx_ldb *imx_ldb;
 622         int dual;
 623         int ret;
 624         int i;
 625
 626         imx_ldb = devm_kzalloc(dev, sizeof(*imx_ldb), GFP_KERNEL);
 627         if (!imx_ldb)
 628                 return -ENOMEM;
 629
 630         imx_ldb->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
 631         if (IS_ERR(imx_ldb->regmap)) {
 632                 dev_err(dev, "failed to get parent regmap\n");
 633                 return PTR_ERR(imx_ldb->regmap);
 634         }
 635
 636         /* disable LDB by resetting the control register to POR default */
 637         regmap_write(imx_ldb->regmap, IOMUXC_GPR2, 0);
 638
 639         imx_ldb->dev = dev;
 640
 641         if (of_id)
 642                 imx_ldb->lvds_mux = of_id->data;
 643
 644         dual = of_property_read_bool(np, "fsl,dual-channel");
 645         if (dual)
 646                 imx_ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN;
 647
 648         /*
 649          * There are three different possible clock mux configurations:
 650          * i.MX53:  ipu1_di0_sel, ipu1_di1_sel
 651          * i.MX6q:  ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, ipu2_di1_sel
 652          * i.MX6dl: ipu1_di0_sel, ipu1_di1_sel, lcdif_sel
 653          * Map them all to di0_sel...di3_sel.
 654          */
 655         for (i = 0; i < 4; i++) {
 656                 char clkname[16];
 657
 658                 sprintf(clkname, "di%d_sel", i);
 659                 imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname);
 660                 if (IS_ERR(imx_ldb->clk_sel[i])) {
 661                         ret = PTR_ERR(imx_ldb->clk_sel[i]);
 662                         imx_ldb->clk_sel[i] = NULL;
 663                         break;
 664                 }
 665
 666                 imx_ldb->clk_parent[i] = clk_get_parent(imx_ldb->clk_sel[i]);
 667         }
 668         if (i == 0)
 669                 return ret;
 670
 671         for_each_child_of_node(np, child) {
 672                 struct imx_ldb_channel *channel;
 673                 int bus_format;
 674
 675                 ret = of_property_read_u32(child, "reg", &i);
 676                 if (ret || i < 0 || i > 1) {
 677                         ret = -EINVAL;
 678                         goto free_child;
 679                 }
 680
 681                 if (!of_device_is_available(child))
 682                         continue;
 683
 684                 if (dual && i > 0) {
 685                         dev_warn(dev, "dual-channel mode, ignoring second output\n");
 686                         continue;
 687                 }
 688
 689                 channel = &imx_ldb->channel[i];
 690                 channel->ldb = imx_ldb;
 691                 channel->chno = i;
 692
 693                 /*
 694                  * The output port is port@4 with an external 4-port mux or
 695                  * port@2 with the internal 2-port mux.
 696                  */
 697                 ret = drm_of_find_panel_or_bridge(child,
 698                                                   imx_ldb->lvds_mux ? 4 : 2, 0,
 699                                                   &channel->panel, &channel->bridge);
 700                 if (ret && ret != -ENODEV)
 701                         goto free_child;
 702
 703                 /* panel ddc only if there is no bridge */
 704                 if (!channel->bridge) {
 705                         ret = imx_ldb_panel_ddc(dev, channel, child);
 706                         if (ret)
 707                                 goto free_child;
 708                 }
 709
 710                 bus_format = of_get_bus_format(dev, child);
 711                 if (bus_format == -EINVAL) {
 712                         /*
 713                          * If no bus format was specified in the device tree,
 714                          * we can still get it from the connected panel later.
 715                          */
 716                         if (channel->panel && channel->panel->funcs &&
 717                             channel->panel->funcs->get_modes)
 718                                 bus_format = 0;
 719                 }
 720                 if (bus_format < 0) {
 721                         dev_err(dev, "could not determine data mapping: %d\n",
 722                                 bus_format);
 723                         ret = bus_format;
 724                         goto free_child;
 725                 }
 726                 channel->bus_format = bus_format;
 727                 channel->child = child;
 728         }
 729
 730         platform_set_drvdata(pdev, imx_ldb);
 731
 732         return component_add(&pdev->dev, &imx_ldb_ops);
 733
 734 free_child:
 735         of_node_put(child);
 736         return ret;
 737 }
 738
 739 static int imx_ldb_remove(struct platform_device *pdev)
 740 {
 741         struct imx_ldb *imx_ldb = platform_get_drvdata(pdev);
 742         int i;
 743
 744         for (i = 0; i < 2; i++) {
 745                 struct imx_ldb_channel *channel = &imx_ldb->channel[i];
 746
 747                 kfree(channel->edid);
 748                 i2c_put_adapter(channel->ddc);
 749         }
 750
 751         component_del(&pdev->dev, &imx_ldb_ops);
 752         return 0;
 753 }
 754
 755 static struct platform_driver imx_ldb_driver = {
 756         .probe          = imx_ldb_probe,
 757         .remove         = imx_ldb_remove,
 758         .driver         = {
 759                 .of_match_table = imx_ldb_dt_ids,
 760                 .name   = DRIVER_NAME,
 761         },
 762 };
 763
 764 module_platform_driver(imx_ldb_driver);
 765
 766 MODULE_DESCRIPTION("i.MX LVDS driver");
 767 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
 768 MODULE_LICENSE("GPL");
 769 MODULE_ALIAS("platform:" DRIVER_NAME);