drivers/gpu/drm/i915/intel_uncore.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <linux/pm_runtime.h>
  25
  26 #include "gt/intel_lrc_reg.h" /* for shadow reg list */
  27
  28 #include "i915_drv.h"
  29 #include "i915_iosf_mbi.h"
  30 #include "i915_trace.h"
  31 #include "i915_vgpu.h"
  32 #include "intel_pm.h"
  33
  34 #define FORCEWAKE_ACK_TIMEOUT_MS 50
  35 #define GT_FIFO_TIMEOUT_MS       10
  36
  37 #define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__))
  38
  39 static void
  40 fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
  41 {
  42         uncore->fw_get_funcs->force_wake_get(uncore, fw_domains);
  43 }
  44
  45 void
  46 intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug)
  47 {
  48         spin_lock_init(&mmio_debug->lock);
  49         mmio_debug->unclaimed_mmio_check = 1;
  50 }
  51
  52 static void mmio_debug_suspend(struct intel_uncore_mmio_debug *mmio_debug)
  53 {
  54         lockdep_assert_held(&mmio_debug->lock);
  55
  56         /* Save and disable mmio debugging for the user bypass */
  57         if (!mmio_debug->suspend_count++) {
  58                 mmio_debug->saved_mmio_check = mmio_debug->unclaimed_mmio_check;
  59                 mmio_debug->unclaimed_mmio_check = 0;
  60         }
  61 }
  62
  63 static void mmio_debug_resume(struct intel_uncore_mmio_debug *mmio_debug)
  64 {
  65         lockdep_assert_held(&mmio_debug->lock);
  66
  67         if (!--mmio_debug->suspend_count)
  68                 mmio_debug->unclaimed_mmio_check = mmio_debug->saved_mmio_check;
  69 }
  70
  71 static const char * const forcewake_domain_names[] = {
  72         "render",
  73         "gt",
  74         "media",
  75         "vdbox0",
  76         "vdbox1",
  77         "vdbox2",
  78         "vdbox3",
  79         "vdbox4",
  80         "vdbox5",
  81         "vdbox6",
  82         "vdbox7",
  83         "vebox0",
  84         "vebox1",
  85         "vebox2",
  86         "vebox3",
  87 };
  88
  89 const char *
  90 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
  91 {
  92         BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
  93
  94         if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
  95                 return forcewake_domain_names[id];
  96
  97         WARN_ON(id);
  98
  99         return "unknown";
 100 }
 101
 102 #define fw_ack(d) readl((d)->reg_ack)
 103 #define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set)
 104 #define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set)
 105
 106 static inline void
 107 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
 108 {
 109         /*
 110          * We don't really know if the powerwell for the forcewake domain we are
 111          * trying to reset here does exist at this point (engines could be fused
 112          * off in ICL+), so no waiting for acks
 113          */
 114         /* WaRsClearFWBitsAtReset:bdw,skl */
 115         fw_clear(d, 0xffff);
 116 }
 117
 118 static inline void
 119 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
 120 {
 121         GEM_BUG_ON(d->uncore->fw_domains_timer & d->mask);
 122         d->uncore->fw_domains_timer |= d->mask;
 123         d->wake_count++;
 124         hrtimer_start_range_ns(&d->timer,
 125                                NSEC_PER_MSEC,
 126                                NSEC_PER_MSEC,
 127                                HRTIMER_MODE_REL);
 128 }
 129
 130 static inline int
 131 __wait_for_ack(const struct intel_uncore_forcewake_domain *d,
 132                const u32 ack,
 133                const u32 value)
 134 {
 135         return wait_for_atomic((fw_ack(d) & ack) == value,
 136                                FORCEWAKE_ACK_TIMEOUT_MS);
 137 }
 138
 139 static inline int
 140 wait_ack_clear(const struct intel_uncore_forcewake_domain *d,
 141                const u32 ack)
 142 {
 143         return __wait_for_ack(d, ack, 0);
 144 }
 145
 146 static inline int
 147 wait_ack_set(const struct intel_uncore_forcewake_domain *d,
 148              const u32 ack)
 149 {
 150         return __wait_for_ack(d, ack, ack);
 151 }
 152
 153 static inline void
 154 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
 155 {
 156         if (wait_ack_clear(d, FORCEWAKE_KERNEL)) {
 157                 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
 158                           intel_uncore_forcewake_domain_to_str(d->id));
 159                 add_taint_for_CI(d->uncore->i915, TAINT_WARN); /* CI now unreliable */
 160         }
 161 }
 162
 163 enum ack_type {
 164         ACK_CLEAR = 0,
 165         ACK_SET
 166 };
 167
 168 static int
 169 fw_domain_wait_ack_with_fallback(const struct intel_uncore_forcewake_domain *d,
 170                                  const enum ack_type type)
 171 {
 172         const u32 ack_bit = FORCEWAKE_KERNEL;
 173         const u32 value = type == ACK_SET ? ack_bit : 0;
 174         unsigned int pass;
 175         bool ack_detected;
 176
 177         /*
 178          * There is a possibility of driver's wake request colliding
 179          * with hardware's own wake requests and that can cause
 180          * hardware to not deliver the driver's ack message.
 181          *
 182          * Use a fallback bit toggle to kick the gpu state machine
 183          * in the hope that the original ack will be delivered along with
 184          * the fallback ack.
 185          *
 186          * This workaround is described in HSDES #1604254524 and it's known as:
 187          * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl
 188          * although the name is a bit misleading.
 189          */
 190
 191         pass = 1;
 192         do {
 193                 wait_ack_clear(d, FORCEWAKE_KERNEL_FALLBACK);
 194
 195                 fw_set(d, FORCEWAKE_KERNEL_FALLBACK);
 196                 /* Give gt some time to relax before the polling frenzy */
 197                 udelay(10 * pass);
 198                 wait_ack_set(d, FORCEWAKE_KERNEL_FALLBACK);
 199
 200                 ack_detected = (fw_ack(d) & ack_bit) == value;
 201
 202                 fw_clear(d, FORCEWAKE_KERNEL_FALLBACK);
 203         } while (!ack_detected && pass++ < 10);
 204
 205         DRM_DEBUG_DRIVER("%s had to use fallback to %s ack, 0x%x (passes %u)\n",
 206                          intel_uncore_forcewake_domain_to_str(d->id),
 207                          type == ACK_SET ? "set" : "clear",
 208                          fw_ack(d),
 209                          pass);
 210
 211         return ack_detected ? 0 : -ETIMEDOUT;
 212 }
 213
 214 static inline void
 215 fw_domain_wait_ack_clear_fallback(const struct intel_uncore_forcewake_domain *d)
 216 {
 217         if (likely(!wait_ack_clear(d, FORCEWAKE_KERNEL)))
 218                 return;
 219
 220         if (fw_domain_wait_ack_with_fallback(d, ACK_CLEAR))
 221                 fw_domain_wait_ack_clear(d);
 222 }
 223
 224 static inline void
 225 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
 226 {
 227         fw_set(d, FORCEWAKE_KERNEL);
 228 }
 229
 230 static inline void
 231 fw_domain_wait_ack_set(const struct intel_uncore_forcewake_domain *d)
 232 {
 233         if (wait_ack_set(d, FORCEWAKE_KERNEL)) {
 234                 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
 235                           intel_uncore_forcewake_domain_to_str(d->id));
 236                 add_taint_for_CI(d->uncore->i915, TAINT_WARN); /* CI now unreliable */
 237         }
 238 }
 239
 240 static inline void
 241 fw_domain_wait_ack_set_fallback(const struct intel_uncore_forcewake_domain *d)
 242 {
 243         if (likely(!wait_ack_set(d, FORCEWAKE_KERNEL)))
 244                 return;
 245
 246         if (fw_domain_wait_ack_with_fallback(d, ACK_SET))
 247                 fw_domain_wait_ack_set(d);
 248 }
 249
 250 static inline void
 251 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
 252 {
 253         fw_clear(d, FORCEWAKE_KERNEL);
 254 }
 255
 256 static void
 257 fw_domains_get_normal(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
 258 {
 259         struct intel_uncore_forcewake_domain *d;
 260         unsigned int tmp;
 261
 262         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
 263
 264         for_each_fw_domain_masked(d, fw_domains, uncore, tmp) {
 265                 fw_domain_wait_ack_clear(d);
 266                 fw_domain_get(d);
 267         }
 268
 269         for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
 270                 fw_domain_wait_ack_set(d);
 271
 272         uncore->fw_domains_active |= fw_domains;
 273 }
 274
 275 static void
 276 fw_domains_get_with_fallback(struct intel_uncore *uncore,
 277                              enum forcewake_domains fw_domains)
 278 {
 279         struct intel_uncore_forcewake_domain *d;
 280         unsigned int tmp;
 281
 282         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
 283
 284         for_each_fw_domain_masked(d, fw_domains, uncore, tmp) {
 285                 fw_domain_wait_ack_clear_fallback(d);
 286                 fw_domain_get(d);
 287         }
 288
 289         for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
 290                 fw_domain_wait_ack_set_fallback(d);
 291
 292         uncore->fw_domains_active |= fw_domains;
 293 }
 294
 295 static void
 296 fw_domains_put(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
 297 {
 298         struct intel_uncore_forcewake_domain *d;
 299         unsigned int tmp;
 300
 301         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
 302
 303         for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
 304                 fw_domain_put(d);
 305
 306         uncore->fw_domains_active &= ~fw_domains;
 307 }
 308
 309 static void
 310 fw_domains_reset(struct intel_uncore *uncore,
 311                  enum forcewake_domains fw_domains)
 312 {
 313         struct intel_uncore_forcewake_domain *d;
 314         unsigned int tmp;
 315
 316         if (!fw_domains)
 317                 return;
 318
 319         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
 320
 321         for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
 322                 fw_domain_reset(d);
 323 }
 324
 325 static inline u32 gt_thread_status(struct intel_uncore *uncore)
 326 {
 327         u32 val;
 328
 329         val = __raw_uncore_read32(uncore, GEN6_GT_THREAD_STATUS_REG);
 330         val &= GEN6_GT_THREAD_STATUS_CORE_MASK;
 331
 332         return val;
 333 }
 334
 335 static void __gen6_gt_wait_for_thread_c0(struct intel_uncore *uncore)
 336 {
 337         /*
 338          * w/a for a sporadic read returning 0 by waiting for the GT
 339          * thread to wake up.
 340          */
 341         drm_WARN_ONCE(&uncore->i915->drm,
 342                       wait_for_atomic_us(gt_thread_status(uncore) == 0, 5000),
 343                       "GT thread status wait timed out\n");
 344 }
 345
 346 static void fw_domains_get_with_thread_status(struct intel_uncore *uncore,
 347                                               enum forcewake_domains fw_domains)
 348 {
 349         fw_domains_get_normal(uncore, fw_domains);
 350
 351         /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
 352         __gen6_gt_wait_for_thread_c0(uncore);
 353 }
 354
 355 static inline u32 fifo_free_entries(struct intel_uncore *uncore)
 356 {
 357         u32 count = __raw_uncore_read32(uncore, GTFIFOCTL);
 358
 359         return count & GT_FIFO_FREE_ENTRIES_MASK;
 360 }
 361
 362 static void __gen6_gt_wait_for_fifo(struct intel_uncore *uncore)
 363 {
 364         u32 n;
 365
 366         /* On VLV, FIFO will be shared by both SW and HW.
 367          * So, we need to read the FREE_ENTRIES everytime */
 368         if (IS_VALLEYVIEW(uncore->i915))
 369                 n = fifo_free_entries(uncore);
 370         else
 371                 n = uncore->fifo_count;
 372
 373         if (n <= GT_FIFO_NUM_RESERVED_ENTRIES) {
 374                 if (wait_for_atomic((n = fifo_free_entries(uncore)) >
 375                                     GT_FIFO_NUM_RESERVED_ENTRIES,
 376                                     GT_FIFO_TIMEOUT_MS)) {
 377                         drm_dbg(&uncore->i915->drm,
 378                                 "GT_FIFO timeout, entries: %u\n", n);
 379                         return;
 380                 }
 381         }
 382
 383         uncore->fifo_count = n - 1;
 384 }
 385
 386 static enum hrtimer_restart
 387 intel_uncore_fw_release_timer(struct hrtimer *timer)
 388 {
 389         struct intel_uncore_forcewake_domain *domain =
 390                container_of(timer, struct intel_uncore_forcewake_domain, timer);
 391         struct intel_uncore *uncore = domain->uncore;
 392         unsigned long irqflags;
 393
 394         assert_rpm_device_not_suspended(uncore->rpm);
 395
 396         if (xchg(&domain->active, false))
 397                 return HRTIMER_RESTART;
 398
 399         spin_lock_irqsave(&uncore->lock, irqflags);
 400
 401         uncore->fw_domains_timer &= ~domain->mask;
 402
 403         GEM_BUG_ON(!domain->wake_count);
 404         if (--domain->wake_count == 0)
 405                 fw_domains_put(uncore, domain->mask);
 406
 407         spin_unlock_irqrestore(&uncore->lock, irqflags);
 408
 409         return HRTIMER_NORESTART;
 410 }
 411
 412 /* Note callers must have acquired the PUNIT->PMIC bus, before calling this. */
 413 static unsigned int
 414 intel_uncore_forcewake_reset(struct intel_uncore *uncore)
 415 {
 416         unsigned long irqflags;
 417         struct intel_uncore_forcewake_domain *domain;
 418         int retry_count = 100;
 419         enum forcewake_domains fw, active_domains;
 420
 421         iosf_mbi_assert_punit_acquired();
 422
 423         /* Hold uncore.lock across reset to prevent any register access
 424          * with forcewake not set correctly. Wait until all pending
 425          * timers are run before holding.
 426          */
 427         while (1) {
 428                 unsigned int tmp;
 429
 430                 active_domains = 0;
 431
 432                 for_each_fw_domain(domain, uncore, tmp) {
 433                         smp_store_mb(domain->active, false);
 434                         if (hrtimer_cancel(&domain->timer) == 0)
 435                                 continue;
 436
 437                         intel_uncore_fw_release_timer(&domain->timer);
 438                 }
 439
 440                 spin_lock_irqsave(&uncore->lock, irqflags);
 441
 442                 for_each_fw_domain(domain, uncore, tmp) {
 443                         if (hrtimer_active(&domain->timer))
 444                                 active_domains |= domain->mask;
 445                 }
 446
 447                 if (active_domains == 0)
 448                         break;
 449
 450                 if (--retry_count == 0) {
 451                         drm_err(&uncore->i915->drm, "Timed out waiting for forcewake timers to finish\n");
 452                         break;
 453                 }
 454
 455                 spin_unlock_irqrestore(&uncore->lock, irqflags);
 456                 cond_resched();
 457         }
 458
 459         drm_WARN_ON(&uncore->i915->drm, active_domains);
 460
 461         fw = uncore->fw_domains_active;
 462         if (fw)
 463                 fw_domains_put(uncore, fw);
 464
 465         fw_domains_reset(uncore, uncore->fw_domains);
 466         assert_forcewakes_inactive(uncore);
 467
 468         spin_unlock_irqrestore(&uncore->lock, irqflags);
 469
 470         return fw; /* track the lost user forcewake domains */
 471 }
 472
 473 static bool
 474 fpga_check_for_unclaimed_mmio(struct intel_uncore *uncore)
 475 {
 476         u32 dbg;
 477
 478         dbg = __raw_uncore_read32(uncore, FPGA_DBG);
 479         if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
 480                 return false;
 481
 482         /*
 483          * Bugs in PCI programming (or failing hardware) can occasionally cause
 484          * us to lose access to the MMIO BAR.  When this happens, register
 485          * reads will come back with 0xFFFFFFFF for every register and things
 486          * go bad very quickly.  Let's try to detect that special case and at
 487          * least try to print a more informative message about what has
 488          * happened.
 489          *
 490          * During normal operation the FPGA_DBG register has several unused
 491          * bits that will always read back as 0's so we can use them as canaries
 492          * to recognize when MMIO accesses are just busted.
 493          */
 494         if (unlikely(dbg == ~0))
 495                 drm_err(&uncore->i915->drm,
 496                         "Lost access to MMIO BAR; all registers now read back as 0xFFFFFFFF!\n");
 497
 498         __raw_uncore_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 499
 500         return true;
 501 }
 502
 503 static bool
 504 vlv_check_for_unclaimed_mmio(struct intel_uncore *uncore)
 505 {
 506         u32 cer;
 507
 508         cer = __raw_uncore_read32(uncore, CLAIM_ER);
 509         if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
 510                 return false;
 511
 512         __raw_uncore_write32(uncore, CLAIM_ER, CLAIM_ER_CLR);
 513
 514         return true;
 515 }
 516
 517 static bool
 518 gen6_check_for_fifo_debug(struct intel_uncore *uncore)
 519 {
 520         u32 fifodbg;
 521
 522         fifodbg = __raw_uncore_read32(uncore, GTFIFODBG);
 523
 524         if (unlikely(fifodbg)) {
 525                 drm_dbg(&uncore->i915->drm, "GTFIFODBG = 0x08%x\n", fifodbg);
 526                 __raw_uncore_write32(uncore, GTFIFODBG, fifodbg);
 527         }
 528
 529         return fifodbg;
 530 }
 531
 532 static bool
 533 check_for_unclaimed_mmio(struct intel_uncore *uncore)
 534 {
 535         bool ret = false;
 536
 537         lockdep_assert_held(&uncore->debug->lock);
 538
 539         if (uncore->debug->suspend_count)
 540                 return false;
 541
 542         if (intel_uncore_has_fpga_dbg_unclaimed(uncore))
 543                 ret |= fpga_check_for_unclaimed_mmio(uncore);
 544
 545         if (intel_uncore_has_dbg_unclaimed(uncore))
 546                 ret |= vlv_check_for_unclaimed_mmio(uncore);
 547
 548         if (intel_uncore_has_fifo(uncore))
 549                 ret |= gen6_check_for_fifo_debug(uncore);
 550
 551         return ret;
 552 }
 553
 554 static void forcewake_early_sanitize(struct intel_uncore *uncore,
 555                                      unsigned int restore_forcewake)
 556 {
 557         GEM_BUG_ON(!intel_uncore_has_forcewake(uncore));
 558
 559         /* WaDisableShadowRegForCpd:chv */
 560         if (IS_CHERRYVIEW(uncore->i915)) {
 561                 __raw_uncore_write32(uncore, GTFIFOCTL,
 562                                      __raw_uncore_read32(uncore, GTFIFOCTL) |
 563                                      GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
 564                                      GT_FIFO_CTL_RC6_POLICY_STALL);
 565         }
 566
 567         iosf_mbi_punit_acquire();
 568         intel_uncore_forcewake_reset(uncore);
 569         if (restore_forcewake) {
 570                 spin_lock_irq(&uncore->lock);
 571                 fw_domains_get(uncore, restore_forcewake);
 572
 573                 if (intel_uncore_has_fifo(uncore))
 574                         uncore->fifo_count = fifo_free_entries(uncore);
 575                 spin_unlock_irq(&uncore->lock);
 576         }
 577         iosf_mbi_punit_release();
 578 }
 579
 580 void intel_uncore_suspend(struct intel_uncore *uncore)
 581 {
 582         if (!intel_uncore_has_forcewake(uncore))
 583                 return;
 584
 585         iosf_mbi_punit_acquire();
 586         iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
 587                 &uncore->pmic_bus_access_nb);
 588         uncore->fw_domains_saved = intel_uncore_forcewake_reset(uncore);
 589         iosf_mbi_punit_release();
 590 }
 591
 592 void intel_uncore_resume_early(struct intel_uncore *uncore)
 593 {
 594         unsigned int restore_forcewake;
 595
 596         if (intel_uncore_unclaimed_mmio(uncore))
 597                 drm_dbg(&uncore->i915->drm, "unclaimed mmio detected on resume, clearing\n");
 598
 599         if (!intel_uncore_has_forcewake(uncore))
 600                 return;
 601
 602         restore_forcewake = fetch_and_zero(&uncore->fw_domains_saved);
 603         forcewake_early_sanitize(uncore, restore_forcewake);
 604
 605         iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
 606 }
 607
 608 void intel_uncore_runtime_resume(struct intel_uncore *uncore)
 609 {
 610         if (!intel_uncore_has_forcewake(uncore))
 611                 return;
 612
 613         iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
 614 }
 615
 616 static void __intel_uncore_forcewake_get(struct intel_uncore *uncore,
 617                                          enum forcewake_domains fw_domains)
 618 {
 619         struct intel_uncore_forcewake_domain *domain;
 620         unsigned int tmp;
 621
 622         fw_domains &= uncore->fw_domains;
 623
 624         for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
 625                 if (domain->wake_count++) {
 626                         fw_domains &= ~domain->mask;
 627                         domain->active = true;
 628                 }
 629         }
 630
 631         if (fw_domains)
 632                 fw_domains_get(uncore, fw_domains);
 633 }
 634
 635 /**
 636  * intel_uncore_forcewake_get - grab forcewake domain references
 637  * @uncore: the intel_uncore structure
 638  * @fw_domains: forcewake domains to get reference on
 639  *
 640  * This function can be used get GT's forcewake domain references.
 641  * Normal register access will handle the forcewake domains automatically.
 642  * However if some sequence requires the GT to not power down a particular
 643  * forcewake domains this function should be called at the beginning of the
 644  * sequence. And subsequently the reference should be dropped by symmetric
 645  * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
 646  * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
 647  */
 648 void intel_uncore_forcewake_get(struct intel_uncore *uncore,
 649                                 enum forcewake_domains fw_domains)
 650 {
 651         unsigned long irqflags;
 652
 653         if (!uncore->fw_get_funcs)
 654                 return;
 655
 656         assert_rpm_wakelock_held(uncore->rpm);
 657
 658         spin_lock_irqsave(&uncore->lock, irqflags);
 659         __intel_uncore_forcewake_get(uncore, fw_domains);
 660         spin_unlock_irqrestore(&uncore->lock, irqflags);
 661 }
 662
 663 /**
 664  * intel_uncore_forcewake_user_get - claim forcewake on behalf of userspace
 665  * @uncore: the intel_uncore structure
 666  *
 667  * This function is a wrapper around intel_uncore_forcewake_get() to acquire
 668  * the GT powerwell and in the process disable our debugging for the
 669  * duration of userspace's bypass.
 670  */
 671 void intel_uncore_forcewake_user_get(struct intel_uncore *uncore)
 672 {
 673         spin_lock_irq(&uncore->lock);
 674         if (!uncore->user_forcewake_count++) {
 675                 intel_uncore_forcewake_get__locked(uncore, FORCEWAKE_ALL);
 676                 spin_lock(&uncore->debug->lock);
 677                 mmio_debug_suspend(uncore->debug);
 678                 spin_unlock(&uncore->debug->lock);
 679         }
 680         spin_unlock_irq(&uncore->lock);
 681 }
 682
 683 /**
 684  * intel_uncore_forcewake_user_put - release forcewake on behalf of userspace
 685  * @uncore: the intel_uncore structure
 686  *
 687  * This function complements intel_uncore_forcewake_user_get() and releases
 688  * the GT powerwell taken on behalf of the userspace bypass.
 689  */
 690 void intel_uncore_forcewake_user_put(struct intel_uncore *uncore)
 691 {
 692         spin_lock_irq(&uncore->lock);
 693         if (!--uncore->user_forcewake_count) {
 694                 spin_lock(&uncore->debug->lock);
 695                 mmio_debug_resume(uncore->debug);
 696
 697                 if (check_for_unclaimed_mmio(uncore))
 698                         drm_info(&uncore->i915->drm,
 699                                  "Invalid mmio detected during user access\n");
 700                 spin_unlock(&uncore->debug->lock);
 701
 702                 intel_uncore_forcewake_put__locked(uncore, FORCEWAKE_ALL);
 703         }
 704         spin_unlock_irq(&uncore->lock);
 705 }
 706
 707 /**
 708  * intel_uncore_forcewake_get__locked - grab forcewake domain references
 709  * @uncore: the intel_uncore structure
 710  * @fw_domains: forcewake domains to get reference on
 711  *
 712  * See intel_uncore_forcewake_get(). This variant places the onus
 713  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 714  */
 715 void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore,
 716                                         enum forcewake_domains fw_domains)
 717 {
 718         lockdep_assert_held(&uncore->lock);
 719
 720         if (!uncore->fw_get_funcs)
 721                 return;
 722
 723         __intel_uncore_forcewake_get(uncore, fw_domains);
 724 }
 725
 726 static void __intel_uncore_forcewake_put(struct intel_uncore *uncore,
 727                                          enum forcewake_domains fw_domains)
 728 {
 729         struct intel_uncore_forcewake_domain *domain;
 730         unsigned int tmp;
 731
 732         fw_domains &= uncore->fw_domains;
 733
 734         for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
 735                 GEM_BUG_ON(!domain->wake_count);
 736
 737                 if (--domain->wake_count) {
 738                         domain->active = true;
 739                         continue;
 740                 }
 741
 742                 fw_domains_put(uncore, domain->mask);
 743         }
 744 }
 745
 746 /**
 747  * intel_uncore_forcewake_put - release a forcewake domain reference
 748  * @uncore: the intel_uncore structure
 749  * @fw_domains: forcewake domains to put references
 750  *
 751  * This function drops the device-level forcewakes for specified
 752  * domains obtained by intel_uncore_forcewake_get().
 753  */
 754 void intel_uncore_forcewake_put(struct intel_uncore *uncore,
 755                                 enum forcewake_domains fw_domains)
 756 {
 757         unsigned long irqflags;
 758
 759         if (!uncore->fw_get_funcs)
 760                 return;
 761
 762         spin_lock_irqsave(&uncore->lock, irqflags);
 763         __intel_uncore_forcewake_put(uncore, fw_domains);
 764         spin_unlock_irqrestore(&uncore->lock, irqflags);
 765 }
 766
 767 /**
 768  * intel_uncore_forcewake_flush - flush the delayed release
 769  * @uncore: the intel_uncore structure
 770  * @fw_domains: forcewake domains to flush
 771  */
 772 void intel_uncore_forcewake_flush(struct intel_uncore *uncore,
 773                                   enum forcewake_domains fw_domains)
 774 {
 775         struct intel_uncore_forcewake_domain *domain;
 776         unsigned int tmp;
 777
 778         if (!uncore->fw_get_funcs)
 779                 return;
 780
 781         fw_domains &= uncore->fw_domains;
 782         for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
 783                 WRITE_ONCE(domain->active, false);
 784                 if (hrtimer_cancel(&domain->timer))
 785                         intel_uncore_fw_release_timer(&domain->timer);
 786         }
 787 }
 788
 789 /**
 790  * intel_uncore_forcewake_put__locked - grab forcewake domain references
 791  * @uncore: the intel_uncore structure
 792  * @fw_domains: forcewake domains to get reference on
 793  *
 794  * See intel_uncore_forcewake_put(). This variant places the onus
 795  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 796  */
 797 void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
 798                                         enum forcewake_domains fw_domains)
 799 {
 800         lockdep_assert_held(&uncore->lock);
 801
 802         if (!uncore->fw_get_funcs)
 803                 return;
 804
 805         __intel_uncore_forcewake_put(uncore, fw_domains);
 806 }
 807
 808 void assert_forcewakes_inactive(struct intel_uncore *uncore)
 809 {
 810         if (!uncore->fw_get_funcs)
 811                 return;
 812
 813         drm_WARN(&uncore->i915->drm, uncore->fw_domains_active,
 814                  "Expected all fw_domains to be inactive, but %08x are still on\n",
 815                  uncore->fw_domains_active);
 816 }
 817
 818 void assert_forcewakes_active(struct intel_uncore *uncore,
 819                               enum forcewake_domains fw_domains)
 820 {
 821         struct intel_uncore_forcewake_domain *domain;
 822         unsigned int tmp;
 823
 824         if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
 825                 return;
 826
 827         if (!uncore->fw_get_funcs)
 828                 return;
 829
 830         spin_lock_irq(&uncore->lock);
 831
 832         assert_rpm_wakelock_held(uncore->rpm);
 833
 834         fw_domains &= uncore->fw_domains;
 835         drm_WARN(&uncore->i915->drm, fw_domains & ~uncore->fw_domains_active,
 836                  "Expected %08x fw_domains to be active, but %08x are off\n",
 837                  fw_domains, fw_domains & ~uncore->fw_domains_active);
 838
 839         /*
 840          * Check that the caller has an explicit wakeref and we don't mistake
 841          * it for the auto wakeref.
 842          */
 843         for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
 844                 unsigned int actual = READ_ONCE(domain->wake_count);
 845                 unsigned int expect = 1;
 846
 847                 if (uncore->fw_domains_timer & domain->mask)
 848                         expect++; /* pending automatic release */
 849
 850                 if (drm_WARN(&uncore->i915->drm, actual < expect,
 851                              "Expected domain %d to be held awake by caller, count=%d\n",
 852                              domain->id, actual))
 853                         break;
 854         }
 855
 856         spin_unlock_irq(&uncore->lock);
 857 }
 858
 859 /* We give fast paths for the really cool registers */
 860 #define NEEDS_FORCE_WAKE(reg) ({ \
 861         u32 __reg = (reg); \
 862         __reg < 0x40000 || __reg >= GEN11_BSD_RING_BASE; \
 863 })
 864
 865 static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry)
 866 {
 867         if (offset < entry->start)
 868                 return -1;
 869         else if (offset > entry->end)
 870                 return 1;
 871         else
 872                 return 0;
 873 }
 874
 875 /* Copied and "macroized" from lib/bsearch.c */
 876 #define BSEARCH(key, base, num, cmp) ({                                 \
 877         unsigned int start__ = 0, end__ = (num);                        \
 878         typeof(base) result__ = NULL;                                   \
 879         while (start__ < end__) {                                       \
 880                 unsigned int mid__ = start__ + (end__ - start__) / 2;   \
 881                 int ret__ = (cmp)((key), (base) + mid__);               \
 882                 if (ret__ < 0) {                                        \
 883                         end__ = mid__;                                  \
 884                 } else if (ret__ > 0) {                                 \
 885                         start__ = mid__ + 1;                            \
 886                 } else {                                                \
 887                         result__ = (base) + mid__;                      \
 888                         break;                                          \
 889                 }                                                       \
 890         }                                                               \
 891         result__;                                                       \
 892 })
 893
 894 static enum forcewake_domains
 895 find_fw_domain(struct intel_uncore *uncore, u32 offset)
 896 {
 897         const struct intel_forcewake_range *entry;
 898
 899         entry = BSEARCH(offset,
 900                         uncore->fw_domains_table,
 901                         uncore->fw_domains_table_entries,
 902                         fw_range_cmp);
 903
 904         if (!entry)
 905                 return 0;
 906
 907         /*
 908          * The list of FW domains depends on the SKU in gen11+ so we
 909          * can't determine it statically. We use FORCEWAKE_ALL and
 910          * translate it here to the list of available domains.
 911          */
 912         if (entry->domains == FORCEWAKE_ALL)
 913                 return uncore->fw_domains;
 914
 915         drm_WARN(&uncore->i915->drm, entry->domains & ~uncore->fw_domains,
 916                  "Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n",
 917                  entry->domains & ~uncore->fw_domains, offset);
 918
 919         return entry->domains;
 920 }
 921
 922 #define GEN_FW_RANGE(s, e, d) \
 923         { .start = (s), .end = (e), .domains = (d) }
 924
 925 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 926 static const struct intel_forcewake_range __vlv_fw_ranges[] = {
 927         GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
 928         GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER),
 929         GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER),
 930         GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
 931         GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA),
 932         GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER),
 933         GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
 934 };
 935
 936 #define __fwtable_reg_read_fw_domains(uncore, offset) \
 937 ({ \
 938         enum forcewake_domains __fwd = 0; \
 939         if (NEEDS_FORCE_WAKE((offset))) \
 940                 __fwd = find_fw_domain(uncore, offset); \
 941         __fwd; \
 942 })
 943
 944 /* *Must* be sorted by offset! See intel_shadow_table_check(). */
 945 static const struct i915_range gen8_shadowed_regs[] = {
 946         { .start =  0x2030, .end =  0x2030 },
 947         { .start =  0xA008, .end =  0xA00C },
 948         { .start = 0x12030, .end = 0x12030 },
 949         { .start = 0x1a030, .end = 0x1a030 },
 950         { .start = 0x22030, .end = 0x22030 },
 951         /* TODO: Other registers are not yet used */
 952 };
 953
 954 static const struct i915_range gen11_shadowed_regs[] = {
 955         { .start =   0x2030, .end =   0x2030 },
 956         { .start =   0x2550, .end =   0x2550 },
 957         { .start =   0xA008, .end =   0xA00C },
 958         { .start =  0x22030, .end =  0x22030 },
 959         { .start =  0x22230, .end =  0x22230 },
 960         { .start =  0x22510, .end =  0x22550 },
 961         { .start = 0x1C0030, .end = 0x1C0030 },
 962         { .start = 0x1C0230, .end = 0x1C0230 },
 963         { .start = 0x1C0510, .end = 0x1C0550 },
 964         { .start = 0x1C4030, .end = 0x1C4030 },
 965         { .start = 0x1C4230, .end = 0x1C4230 },
 966         { .start = 0x1C4510, .end = 0x1C4550 },
 967         { .start = 0x1C8030, .end = 0x1C8030 },
 968         { .start = 0x1C8230, .end = 0x1C8230 },
 969         { .start = 0x1C8510, .end = 0x1C8550 },
 970         { .start = 0x1D0030, .end = 0x1D0030 },
 971         { .start = 0x1D0230, .end = 0x1D0230 },
 972         { .start = 0x1D0510, .end = 0x1D0550 },
 973         { .start = 0x1D4030, .end = 0x1D4030 },
 974         { .start = 0x1D4230, .end = 0x1D4230 },
 975         { .start = 0x1D4510, .end = 0x1D4550 },
 976         { .start = 0x1D8030, .end = 0x1D8030 },
 977         { .start = 0x1D8230, .end = 0x1D8230 },
 978         { .start = 0x1D8510, .end = 0x1D8550 },
 979 };
 980
 981 static const struct i915_range gen12_shadowed_regs[] = {
 982         { .start =   0x2030, .end =   0x2030 },
 983         { .start =   0x2510, .end =   0x2550 },
 984         { .start =   0xA008, .end =   0xA00C },
 985         { .start =   0xA188, .end =   0xA188 },
 986         { .start =   0xA278, .end =   0xA278 },
 987         { .start =   0xA540, .end =   0xA56C },
 988         { .start =   0xC4C8, .end =   0xC4C8 },
 989         { .start =   0xC4D4, .end =   0xC4D4 },
 990         { .start =   0xC600, .end =   0xC600 },
 991         { .start =  0x22030, .end =  0x22030 },
 992         { .start =  0x22510, .end =  0x22550 },
 993         { .start = 0x1C0030, .end = 0x1C0030 },
 994         { .start = 0x1C0510, .end = 0x1C0550 },
 995         { .start = 0x1C4030, .end = 0x1C4030 },
 996         { .start = 0x1C4510, .end = 0x1C4550 },
 997         { .start = 0x1C8030, .end = 0x1C8030 },
 998         { .start = 0x1C8510, .end = 0x1C8550 },
 999         { .start = 0x1D0030, .end = 0x1D0030 },
1000         { .start = 0x1D0510, .end = 0x1D0550 },
1001         { .start = 0x1D4030, .end = 0x1D4030 },
1002         { .start = 0x1D4510, .end = 0x1D4550 },
1003         { .start = 0x1D8030, .end = 0x1D8030 },
1004         { .start = 0x1D8510, .end = 0x1D8550 },
1005
1006         /*
1007          * The rest of these ranges are specific to Xe_HP and beyond, but
1008          * are reserved/unused ranges on earlier gen12 platforms, so they can
1009          * be safely added to the gen12 table.
1010          */
1011         { .start = 0x1E0030, .end = 0x1E0030 },
1012         { .start = 0x1E0510, .end = 0x1E0550 },
1013         { .start = 0x1E4030, .end = 0x1E4030 },
1014         { .start = 0x1E4510, .end = 0x1E4550 },
1015         { .start = 0x1E8030, .end = 0x1E8030 },
1016         { .start = 0x1E8510, .end = 0x1E8550 },
1017         { .start = 0x1F0030, .end = 0x1F0030 },
1018         { .start = 0x1F0510, .end = 0x1F0550 },
1019         { .start = 0x1F4030, .end = 0x1F4030 },
1020         { .start = 0x1F4510, .end = 0x1F4550 },
1021         { .start = 0x1F8030, .end = 0x1F8030 },
1022         { .start = 0x1F8510, .end = 0x1F8550 },
1023 };
1024
1025 static const struct i915_range dg2_shadowed_regs[] = {
1026         { .start =   0x2030, .end =   0x2030 },
1027         { .start =   0x2510, .end =   0x2550 },
1028         { .start =   0xA008, .end =   0xA00C },
1029         { .start =   0xA188, .end =   0xA188 },
1030         { .start =   0xA278, .end =   0xA278 },
1031         { .start =   0xA540, .end =   0xA56C },
1032         { .start =   0xC4C8, .end =   0xC4C8 },
1033         { .start =   0xC4E0, .end =   0xC4E0 },
1034         { .start =   0xC600, .end =   0xC600 },
1035         { .start =   0xC658, .end =   0xC658 },
1036         { .start =  0x22030, .end =  0x22030 },
1037         { .start =  0x22510, .end =  0x22550 },
1038         { .start = 0x1C0030, .end = 0x1C0030 },
1039         { .start = 0x1C0510, .end = 0x1C0550 },
1040         { .start = 0x1C4030, .end = 0x1C4030 },
1041         { .start = 0x1C4510, .end = 0x1C4550 },
1042         { .start = 0x1C8030, .end = 0x1C8030 },
1043         { .start = 0x1C8510, .end = 0x1C8550 },
1044         { .start = 0x1D0030, .end = 0x1D0030 },
1045         { .start = 0x1D0510, .end = 0x1D0550 },
1046         { .start = 0x1D4030, .end = 0x1D4030 },
1047         { .start = 0x1D4510, .end = 0x1D4550 },
1048         { .start = 0x1D8030, .end = 0x1D8030 },
1049         { .start = 0x1D8510, .end = 0x1D8550 },
1050         { .start = 0x1E0030, .end = 0x1E0030 },
1051         { .start = 0x1E0510, .end = 0x1E0550 },
1052         { .start = 0x1E4030, .end = 0x1E4030 },
1053         { .start = 0x1E4510, .end = 0x1E4550 },
1054         { .start = 0x1E8030, .end = 0x1E8030 },
1055         { .start = 0x1E8510, .end = 0x1E8550 },
1056         { .start = 0x1F0030, .end = 0x1F0030 },
1057         { .start = 0x1F0510, .end = 0x1F0550 },
1058         { .start = 0x1F4030, .end = 0x1F4030 },
1059         { .start = 0x1F4510, .end = 0x1F4550 },
1060         { .start = 0x1F8030, .end = 0x1F8030 },
1061         { .start = 0x1F8510, .end = 0x1F8550 },
1062 };
1063
1064 static int mmio_range_cmp(u32 key, const struct i915_range *range)
1065 {
1066         if (key < range->start)
1067                 return -1;
1068         else if (key > range->end)
1069                 return 1;
1070         else
1071                 return 0;
1072 }
1073
1074 static bool is_shadowed(struct intel_uncore *uncore, u32 offset)
1075 {
1076         if (drm_WARN_ON(&uncore->i915->drm, !uncore->shadowed_reg_table))
1077                 return false;
1078
1079         return BSEARCH(offset,
1080                        uncore->shadowed_reg_table,
1081                        uncore->shadowed_reg_table_entries,
1082                        mmio_range_cmp);
1083 }
1084
1085 static enum forcewake_domains
1086 gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg)
1087 {
1088         return FORCEWAKE_RENDER;
1089 }
1090
1091 static const struct intel_forcewake_range __gen6_fw_ranges[] = {
1092         GEN_FW_RANGE(0x0, 0x3ffff, FORCEWAKE_RENDER),
1093 };
1094
1095 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
1096 static const struct intel_forcewake_range __chv_fw_ranges[] = {
1097         GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
1098         GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1099         GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1100         GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1101         GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1102         GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1103         GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA),
1104         GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1105         GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1106         GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
1107         GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER),
1108         GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1109         GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
1110         GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA),
1111         GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA),
1112         GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA),
1113 };
1114
1115 #define __fwtable_reg_write_fw_domains(uncore, offset) \
1116 ({ \
1117         enum forcewake_domains __fwd = 0; \
1118         const u32 __offset = (offset); \
1119         if (NEEDS_FORCE_WAKE((__offset)) && !is_shadowed(uncore, __offset)) \
1120                 __fwd = find_fw_domain(uncore, __offset); \
1121         __fwd; \
1122 })
1123
1124 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
1125 static const struct intel_forcewake_range __gen9_fw_ranges[] = {
1126         GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_GT),
1127         GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
1128         GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1129         GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT),
1130         GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
1131         GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT),
1132         GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1133         GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_GT),
1134         GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA),
1135         GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
1136         GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT),
1137         GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1138         GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_GT),
1139         GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA),
1140         GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_GT),
1141         GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
1142         GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_GT),
1143         GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1144         GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_GT),
1145         GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1146         GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_GT),
1147         GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
1148         GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_GT),
1149         GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
1150         GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_GT),
1151         GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
1152         GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_GT),
1153         GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA),
1154         GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_GT),
1155         GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
1156         GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_GT),
1157         GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
1158 };
1159
1160 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
1161 static const struct intel_forcewake_range __gen11_fw_ranges[] = {
1162         GEN_FW_RANGE(0x0, 0x1fff, 0), /* uncore range */
1163         GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1164         GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT),
1165         GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
1166         GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT),
1167         GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1168         GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT),
1169         GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
1170         GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT),
1171         GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1172         GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_GT),
1173         GEN_FW_RANGE(0x8800, 0x8bff, 0),
1174         GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
1175         GEN_FW_RANGE(0x8d00, 0x94cf, FORCEWAKE_GT),
1176         GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
1177         GEN_FW_RANGE(0x9560, 0x95ff, 0),
1178         GEN_FW_RANGE(0x9600, 0xafff, FORCEWAKE_GT),
1179         GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1180         GEN_FW_RANGE(0xb480, 0xdeff, FORCEWAKE_GT),
1181         GEN_FW_RANGE(0xdf00, 0xe8ff, FORCEWAKE_RENDER),
1182         GEN_FW_RANGE(0xe900, 0x16dff, FORCEWAKE_GT),
1183         GEN_FW_RANGE(0x16e00, 0x19fff, FORCEWAKE_RENDER),
1184         GEN_FW_RANGE(0x1a000, 0x23fff, FORCEWAKE_GT),
1185         GEN_FW_RANGE(0x24000, 0x2407f, 0),
1186         GEN_FW_RANGE(0x24080, 0x2417f, FORCEWAKE_GT),
1187         GEN_FW_RANGE(0x24180, 0x242ff, FORCEWAKE_RENDER),
1188         GEN_FW_RANGE(0x24300, 0x243ff, FORCEWAKE_GT),
1189         GEN_FW_RANGE(0x24400, 0x24fff, FORCEWAKE_RENDER),
1190         GEN_FW_RANGE(0x25000, 0x3ffff, FORCEWAKE_GT),
1191         GEN_FW_RANGE(0x40000, 0x1bffff, 0),
1192         GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0),
1193         GEN_FW_RANGE(0x1c4000, 0x1c7fff, 0),
1194         GEN_FW_RANGE(0x1c8000, 0x1cffff, FORCEWAKE_MEDIA_VEBOX0),
1195         GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2),
1196         GEN_FW_RANGE(0x1d4000, 0x1dbfff, 0)
1197 };
1198
1199 /*
1200  * *Must* be sorted by offset ranges! See intel_fw_table_check().
1201  *
1202  * Note that the spec lists several reserved/unused ranges that don't
1203  * actually contain any registers.  In the table below we'll combine those
1204  * reserved ranges with either the preceding or following range to keep the
1205  * table small and lookups fast.
1206  */
1207 static const struct intel_forcewake_range __gen12_fw_ranges[] = {
1208         GEN_FW_RANGE(0x0, 0x1fff, 0), /*
1209                 0x0   -  0xaff: reserved
1210                 0xb00 - 0x1fff: always on */
1211         GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1212         GEN_FW_RANGE(0x2700, 0x27ff, FORCEWAKE_GT),
1213         GEN_FW_RANGE(0x2800, 0x2aff, FORCEWAKE_RENDER),
1214         GEN_FW_RANGE(0x2b00, 0x2fff, FORCEWAKE_GT),
1215         GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
1216         GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), /*
1217                 0x4000 - 0x48ff: gt
1218                 0x4900 - 0x51ff: reserved */
1219         GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), /*
1220                 0x5200 - 0x53ff: render
1221                 0x5400 - 0x54ff: reserved
1222                 0x5500 - 0x7fff: render */
1223         GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT),
1224         GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
1225         GEN_FW_RANGE(0x8160, 0x81ff, 0), /*
1226                 0x8160 - 0x817f: reserved
1227                 0x8180 - 0x81ff: always on */
1228         GEN_FW_RANGE(0x8200, 0x82ff, FORCEWAKE_GT),
1229         GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1230         GEN_FW_RANGE(0x8500, 0x94cf, FORCEWAKE_GT), /*
1231                 0x8500 - 0x87ff: gt
1232                 0x8800 - 0x8fff: reserved
1233                 0x9000 - 0x947f: gt
1234                 0x9480 - 0x94cf: reserved */
1235         GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
1236         GEN_FW_RANGE(0x9560, 0x97ff, 0), /*
1237                 0x9560 - 0x95ff: always on
1238                 0x9600 - 0x97ff: reserved */
1239         GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_GT),
1240         GEN_FW_RANGE(0xb000, 0xb3ff, FORCEWAKE_RENDER),
1241         GEN_FW_RANGE(0xb400, 0xcfff, FORCEWAKE_GT), /*
1242                 0xb400 - 0xbf7f: gt
1243                 0xb480 - 0xbfff: reserved
1244                 0xc000 - 0xcfff: gt */
1245         GEN_FW_RANGE(0xd000, 0xd7ff, 0),
1246         GEN_FW_RANGE(0xd800, 0xd8ff, FORCEWAKE_RENDER),
1247         GEN_FW_RANGE(0xd900, 0xdbff, FORCEWAKE_GT),
1248         GEN_FW_RANGE(0xdc00, 0xefff, FORCEWAKE_RENDER), /*
1249                 0xdc00 - 0xddff: render
1250                 0xde00 - 0xde7f: reserved
1251                 0xde80 - 0xe8ff: render
1252                 0xe900 - 0xefff: reserved */
1253         GEN_FW_RANGE(0xf000, 0x147ff, FORCEWAKE_GT), /*
1254                  0xf000 - 0xffff: gt
1255                 0x10000 - 0x147ff: reserved */
1256         GEN_FW_RANGE(0x14800, 0x1ffff, FORCEWAKE_RENDER), /*
1257                 0x14800 - 0x14fff: render
1258                 0x15000 - 0x16dff: reserved
1259                 0x16e00 - 0x1bfff: render
1260                 0x1c000 - 0x1ffff: reserved */
1261         GEN_FW_RANGE(0x20000, 0x20fff, FORCEWAKE_MEDIA_VDBOX0),
1262         GEN_FW_RANGE(0x21000, 0x21fff, FORCEWAKE_MEDIA_VDBOX2),
1263         GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT),
1264         GEN_FW_RANGE(0x24000, 0x2417f, 0), /*
1265                 0x24000 - 0x2407f: always on
1266                 0x24080 - 0x2417f: reserved */
1267         GEN_FW_RANGE(0x24180, 0x249ff, FORCEWAKE_GT), /*
1268                 0x24180 - 0x241ff: gt
1269                 0x24200 - 0x249ff: reserved */
1270         GEN_FW_RANGE(0x24a00, 0x251ff, FORCEWAKE_RENDER), /*
1271                 0x24a00 - 0x24a7f: render
1272                 0x24a80 - 0x251ff: reserved */
1273         GEN_FW_RANGE(0x25200, 0x255ff, FORCEWAKE_GT), /*
1274                 0x25200 - 0x252ff: gt
1275                 0x25300 - 0x255ff: reserved */
1276         GEN_FW_RANGE(0x25600, 0x2567f, FORCEWAKE_MEDIA_VDBOX0),
1277         GEN_FW_RANGE(0x25680, 0x259ff, FORCEWAKE_MEDIA_VDBOX2), /*
1278                 0x25680 - 0x256ff: VD2
1279                 0x25700 - 0x259ff: reserved */
1280         GEN_FW_RANGE(0x25a00, 0x25a7f, FORCEWAKE_MEDIA_VDBOX0),
1281         GEN_FW_RANGE(0x25a80, 0x2ffff, FORCEWAKE_MEDIA_VDBOX2), /*
1282                 0x25a80 - 0x25aff: VD2
1283                 0x25b00 - 0x2ffff: reserved */
1284         GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT),
1285         GEN_FW_RANGE(0x40000, 0x1bffff, 0),
1286         GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /*
1287                 0x1c0000 - 0x1c2bff: VD0
1288                 0x1c2c00 - 0x1c2cff: reserved
1289                 0x1c2d00 - 0x1c2dff: VD0
1290                 0x1c2e00 - 0x1c3eff: reserved
1291                 0x1c3f00 - 0x1c3fff: VD0 */
1292         GEN_FW_RANGE(0x1c4000, 0x1c7fff, 0),
1293         GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /*
1294                 0x1c8000 - 0x1ca0ff: VE0
1295                 0x1ca100 - 0x1cbeff: reserved
1296                 0x1cbf00 - 0x1cbfff: VE0 */
1297         GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX0), /*
1298                 0x1cc000 - 0x1ccfff: VD0
1299                 0x1cd000 - 0x1cffff: reserved */
1300         GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), /*
1301                 0x1d0000 - 0x1d2bff: VD2
1302                 0x1d2c00 - 0x1d2cff: reserved
1303                 0x1d2d00 - 0x1d2dff: VD2
1304                 0x1d2e00 - 0x1d3eff: reserved
1305                 0x1d3f00 - 0x1d3fff: VD2 */
1306 };
1307
1308 /*
1309  * Graphics IP version 12.55 brings a slight change to the 0xd800 range,
1310  * switching it from the GT domain to the render domain.
1311  *
1312  * *Must* be sorted by offset ranges! See intel_fw_table_check().
1313  */
1314 #define XEHP_FWRANGES(FW_RANGE_D800)                                    \
1315         GEN_FW_RANGE(0x0, 0x1fff, 0), /*                                        \
1316                   0x0 -  0xaff: reserved                                        \
1317                 0xb00 - 0x1fff: always on */                                    \
1318         GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),                         \
1319         GEN_FW_RANGE(0x2700, 0x4aff, FORCEWAKE_GT),                             \
1320         GEN_FW_RANGE(0x4b00, 0x51ff, 0), /*                                     \
1321                 0x4b00 - 0x4fff: reserved                                       \
1322                 0x5000 - 0x51ff: always on */                                   \
1323         GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),                         \
1324         GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT),                             \
1325         GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),                         \
1326         GEN_FW_RANGE(0x8160, 0x81ff, 0), /*                                     \
1327                 0x8160 - 0x817f: reserved                                       \
1328                 0x8180 - 0x81ff: always on */                                   \
1329         GEN_FW_RANGE(0x8200, 0x82ff, FORCEWAKE_GT),                             \
1330         GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),                         \
1331         GEN_FW_RANGE(0x8500, 0x8cff, FORCEWAKE_GT), /*                          \
1332                 0x8500 - 0x87ff: gt                                             \
1333                 0x8800 - 0x8c7f: reserved                                       \
1334                 0x8c80 - 0x8cff: gt (DG2 only) */                               \
1335         GEN_FW_RANGE(0x8d00, 0x8fff, FORCEWAKE_RENDER), /*                      \
1336                 0x8d00 - 0x8dff: render (DG2 only)                              \
1337                 0x8e00 - 0x8fff: reserved */                                    \
1338         GEN_FW_RANGE(0x9000, 0x94cf, FORCEWAKE_GT), /*                          \
1339                 0x9000 - 0x947f: gt                                             \
1340                 0x9480 - 0x94cf: reserved */                                    \
1341         GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),                         \
1342         GEN_FW_RANGE(0x9560, 0x967f, 0), /*                                     \
1343                 0x9560 - 0x95ff: always on                                      \
1344                 0x9600 - 0x967f: reserved */                                    \
1345         GEN_FW_RANGE(0x9680, 0x97ff, FORCEWAKE_RENDER), /*                      \
1346                 0x9680 - 0x96ff: render (DG2 only)                              \
1347                 0x9700 - 0x97ff: reserved */                                    \
1348         GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /*                          \
1349                 0x9800 - 0xb4ff: gt                                             \
1350                 0xb500 - 0xbfff: reserved                                       \
1351                 0xc000 - 0xcfff: gt */                                          \
1352         GEN_FW_RANGE(0xd000, 0xd7ff, 0),                                        \
1353         GEN_FW_RANGE(0xd800, 0xd87f, FW_RANGE_D800),                    \
1354         GEN_FW_RANGE(0xd880, 0xdbff, FORCEWAKE_GT),                             \
1355         GEN_FW_RANGE(0xdc00, 0xdcff, FORCEWAKE_RENDER),                         \
1356         GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /*                          \
1357                 0xdd00 - 0xddff: gt                                             \
1358                 0xde00 - 0xde7f: reserved */                                    \
1359         GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /*                      \
1360                 0xde80 - 0xdfff: render                                         \
1361                 0xe000 - 0xe0ff: reserved                                       \
1362                 0xe100 - 0xe8ff: render */                                      \
1363         GEN_FW_RANGE(0xe900, 0xffff, FORCEWAKE_GT), /*                          \
1364                 0xe900 - 0xe9ff: gt                                             \
1365                 0xea00 - 0xefff: reserved                                       \
1366                 0xf000 - 0xffff: gt */                                          \
1367         GEN_FW_RANGE(0x10000, 0x12fff, 0), /*                                   \
1368                 0x10000 - 0x11fff: reserved                                     \
1369                 0x12000 - 0x127ff: always on                                    \
1370                 0x12800 - 0x12fff: reserved */                                  \
1371         GEN_FW_RANGE(0x13000, 0x131ff, FORCEWAKE_MEDIA_VDBOX0), /* DG2 only */  \
1372         GEN_FW_RANGE(0x13200, 0x13fff, FORCEWAKE_MEDIA_VDBOX2), /*              \
1373                 0x13200 - 0x133ff: VD2 (DG2 only)                               \
1374                 0x13400 - 0x13fff: reserved */                                  \
1375         GEN_FW_RANGE(0x14000, 0x141ff, FORCEWAKE_MEDIA_VDBOX0), /* XEHPSDV only */      \
1376         GEN_FW_RANGE(0x14200, 0x143ff, FORCEWAKE_MEDIA_VDBOX2), /* XEHPSDV only */      \
1377         GEN_FW_RANGE(0x14400, 0x145ff, FORCEWAKE_MEDIA_VDBOX4), /* XEHPSDV only */      \
1378         GEN_FW_RANGE(0x14600, 0x147ff, FORCEWAKE_MEDIA_VDBOX6), /* XEHPSDV only */      \
1379         GEN_FW_RANGE(0x14800, 0x14fff, FORCEWAKE_RENDER),                       \
1380         GEN_FW_RANGE(0x15000, 0x16dff, FORCEWAKE_GT), /*                        \
1381                 0x15000 - 0x15fff: gt (DG2 only)                                \
1382                 0x16000 - 0x16dff: reserved */                                  \
1383         GEN_FW_RANGE(0x16e00, 0x1ffff, FORCEWAKE_RENDER),                       \
1384         GEN_FW_RANGE(0x20000, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /*              \
1385                 0x20000 - 0x20fff: VD0 (XEHPSDV only)                           \
1386                 0x21000 - 0x21fff: reserved */                                  \
1387         GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT),                           \
1388         GEN_FW_RANGE(0x24000, 0x2417f, 0), /*                                   \
1389                 0x24000 - 0x2407f: always on                                    \
1390                 0x24080 - 0x2417f: reserved */                                  \
1391         GEN_FW_RANGE(0x24180, 0x249ff, FORCEWAKE_GT), /*                        \
1392                 0x24180 - 0x241ff: gt                                           \
1393                 0x24200 - 0x249ff: reserved */                                  \
1394         GEN_FW_RANGE(0x24a00, 0x251ff, FORCEWAKE_RENDER), /*                    \
1395                 0x24a00 - 0x24a7f: render                                       \
1396                 0x24a80 - 0x251ff: reserved */                                  \
1397         GEN_FW_RANGE(0x25200, 0x25fff, FORCEWAKE_GT), /*                        \
1398                 0x25200 - 0x252ff: gt                                           \
1399                 0x25300 - 0x25fff: reserved */                                  \
1400         GEN_FW_RANGE(0x26000, 0x2ffff, FORCEWAKE_RENDER), /*                    \
1401                 0x26000 - 0x27fff: render                                       \
1402                 0x28000 - 0x29fff: reserved                                     \
1403                 0x2a000 - 0x2ffff: undocumented */                              \
1404         GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT),                           \
1405         GEN_FW_RANGE(0x40000, 0x1bffff, 0),                                     \
1406         GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /*            \
1407                 0x1c0000 - 0x1c2bff: VD0                                        \
1408                 0x1c2c00 - 0x1c2cff: reserved                                   \
1409                 0x1c2d00 - 0x1c2dff: VD0                                        \
1410                 0x1c2e00 - 0x1c3eff: VD0 (DG2 only)                             \
1411                 0x1c3f00 - 0x1c3fff: VD0 */                                     \
1412         GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1), /*            \
1413                 0x1c4000 - 0x1c6bff: VD1                                        \
1414                 0x1c6c00 - 0x1c6cff: reserved                                   \
1415                 0x1c6d00 - 0x1c6dff: VD1                                        \
1416                 0x1c6e00 - 0x1c7fff: reserved */                                \
1417         GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /*            \
1418                 0x1c8000 - 0x1ca0ff: VE0                                        \
1419                 0x1ca100 - 0x1cbfff: reserved */                                \
1420         GEN_FW_RANGE(0x1cc000, 0x1ccfff, FORCEWAKE_MEDIA_VDBOX0),               \
1421         GEN_FW_RANGE(0x1cd000, 0x1cdfff, FORCEWAKE_MEDIA_VDBOX2),               \
1422         GEN_FW_RANGE(0x1ce000, 0x1cefff, FORCEWAKE_MEDIA_VDBOX4),               \
1423         GEN_FW_RANGE(0x1cf000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX6),               \
1424         GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), /*            \
1425                 0x1d0000 - 0x1d2bff: VD2                                        \
1426                 0x1d2c00 - 0x1d2cff: reserved                                   \
1427                 0x1d2d00 - 0x1d2dff: VD2                                        \
1428                 0x1d2e00 - 0x1d3dff: VD2 (DG2 only)                             \
1429                 0x1d3e00 - 0x1d3eff: reserved                                   \
1430                 0x1d3f00 - 0x1d3fff: VD2 */                                     \
1431         GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3), /*            \
1432                 0x1d4000 - 0x1d6bff: VD3                                        \
1433                 0x1d6c00 - 0x1d6cff: reserved                                   \
1434                 0x1d6d00 - 0x1d6dff: VD3                                        \
1435                 0x1d6e00 - 0x1d7fff: reserved */                                \
1436         GEN_FW_RANGE(0x1d8000, 0x1dffff, FORCEWAKE_MEDIA_VEBOX1), /*            \
1437                 0x1d8000 - 0x1da0ff: VE1                                        \
1438                 0x1da100 - 0x1dffff: reserved */                                \
1439         GEN_FW_RANGE(0x1e0000, 0x1e3fff, FORCEWAKE_MEDIA_VDBOX4), /*            \
1440                 0x1e0000 - 0x1e2bff: VD4                                        \
1441                 0x1e2c00 - 0x1e2cff: reserved                                   \
1442                 0x1e2d00 - 0x1e2dff: VD4                                        \
1443                 0x1e2e00 - 0x1e3eff: reserved                                   \
1444                 0x1e3f00 - 0x1e3fff: VD4 */                                     \
1445         GEN_FW_RANGE(0x1e4000, 0x1e7fff, FORCEWAKE_MEDIA_VDBOX5), /*            \
1446                 0x1e4000 - 0x1e6bff: VD5                                        \
1447                 0x1e6c00 - 0x1e6cff: reserved                                   \
1448                 0x1e6d00 - 0x1e6dff: VD5                                        \
1449                 0x1e6e00 - 0x1e7fff: reserved */                                \
1450         GEN_FW_RANGE(0x1e8000, 0x1effff, FORCEWAKE_MEDIA_VEBOX2), /*            \
1451                 0x1e8000 - 0x1ea0ff: VE2                                        \
1452                 0x1ea100 - 0x1effff: reserved */                                \
1453         GEN_FW_RANGE(0x1f0000, 0x1f3fff, FORCEWAKE_MEDIA_VDBOX6), /*            \
1454                 0x1f0000 - 0x1f2bff: VD6                                        \
1455                 0x1f2c00 - 0x1f2cff: reserved                                   \
1456                 0x1f2d00 - 0x1f2dff: VD6                                        \
1457                 0x1f2e00 - 0x1f3eff: reserved                                   \
1458                 0x1f3f00 - 0x1f3fff: VD6 */                                     \
1459         GEN_FW_RANGE(0x1f4000, 0x1f7fff, FORCEWAKE_MEDIA_VDBOX7), /*            \
1460                 0x1f4000 - 0x1f6bff: VD7                                        \
1461                 0x1f6c00 - 0x1f6cff: reserved                                   \
1462                 0x1f6d00 - 0x1f6dff: VD7                                        \
1463                 0x1f6e00 - 0x1f7fff: reserved */                                \
1464         GEN_FW_RANGE(0x1f8000, 0x1fa0ff, FORCEWAKE_MEDIA_VEBOX3),
1465
1466 static const struct intel_forcewake_range __xehp_fw_ranges[] = {
1467         XEHP_FWRANGES(FORCEWAKE_GT)
1468 };
1469
1470 static const struct intel_forcewake_range __dg2_fw_ranges[] = {
1471         XEHP_FWRANGES(FORCEWAKE_RENDER)
1472 };
1473
1474 static void
1475 ilk_dummy_write(struct intel_uncore *uncore)
1476 {
1477         /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
1478          * the chip from rc6 before touching it for real. MI_MODE is masked,
1479          * hence harmless to write 0 into. */
1480         __raw_uncore_write32(uncore, MI_MODE, 0);
1481 }
1482
1483 static void
1484 __unclaimed_reg_debug(struct intel_uncore *uncore,
1485                       const i915_reg_t reg,
1486                       const bool read,
1487                       const bool before)
1488 {
1489         if (drm_WARN(&uncore->i915->drm,
1490                      check_for_unclaimed_mmio(uncore) && !before,
1491                      "Unclaimed %s register 0x%x\n",
1492                      read ? "read from" : "write to",
1493                      i915_mmio_reg_offset(reg)))
1494                 /* Only report the first N failures */
1495                 uncore->i915->params.mmio_debug--;
1496 }
1497
1498 static inline void
1499 unclaimed_reg_debug(struct intel_uncore *uncore,
1500                     const i915_reg_t reg,
1501                     const bool read,
1502                     const bool before)
1503 {
1504         if (likely(!uncore->i915->params.mmio_debug))
1505                 return;
1506
1507         /* interrupts are disabled and re-enabled around uncore->lock usage */
1508         lockdep_assert_held(&uncore->lock);
1509
1510         if (before)
1511                 spin_lock(&uncore->debug->lock);
1512
1513         __unclaimed_reg_debug(uncore, reg, read, before);
1514
1515         if (!before)
1516                 spin_unlock(&uncore->debug->lock);
1517 }
1518
1519 #define __vgpu_read(x) \
1520 static u##x \
1521 vgpu_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1522         u##x val = __raw_uncore_read##x(uncore, reg); \
1523         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
1524         return val; \
1525 }
1526 __vgpu_read(8)
1527 __vgpu_read(16)
1528 __vgpu_read(32)
1529 __vgpu_read(64)
1530
1531 #define GEN2_READ_HEADER(x) \
1532         u##x val = 0; \
1533         assert_rpm_wakelock_held(uncore->rpm);
1534
1535 #define GEN2_READ_FOOTER \
1536         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
1537         return val
1538
1539 #define __gen2_read(x) \
1540 static u##x \
1541 gen2_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1542         GEN2_READ_HEADER(x); \
1543         val = __raw_uncore_read##x(uncore, reg); \
1544         GEN2_READ_FOOTER; \
1545 }
1546
1547 #define __gen5_read(x) \
1548 static u##x \
1549 gen5_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1550         GEN2_READ_HEADER(x); \
1551         ilk_dummy_write(uncore); \
1552         val = __raw_uncore_read##x(uncore, reg); \
1553         GEN2_READ_FOOTER; \
1554 }
1555
1556 __gen5_read(8)
1557 __gen5_read(16)
1558 __gen5_read(32)
1559 __gen5_read(64)
1560 __gen2_read(8)
1561 __gen2_read(16)
1562 __gen2_read(32)
1563 __gen2_read(64)
1564
1565 #undef __gen5_read
1566 #undef __gen2_read
1567
1568 #undef GEN2_READ_FOOTER
1569 #undef GEN2_READ_HEADER
1570
1571 #define GEN6_READ_HEADER(x) \
1572         u32 offset = i915_mmio_reg_offset(reg); \
1573         unsigned long irqflags; \
1574         u##x val = 0; \
1575         assert_rpm_wakelock_held(uncore->rpm); \
1576         spin_lock_irqsave(&uncore->lock, irqflags); \
1577         unclaimed_reg_debug(uncore, reg, true, true)
1578
1579 #define GEN6_READ_FOOTER \
1580         unclaimed_reg_debug(uncore, reg, true, false); \
1581         spin_unlock_irqrestore(&uncore->lock, irqflags); \
1582         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
1583         return val
1584
1585 static noinline void ___force_wake_auto(struct intel_uncore *uncore,
1586                                         enum forcewake_domains fw_domains)
1587 {
1588         struct intel_uncore_forcewake_domain *domain;
1589         unsigned int tmp;
1590
1591         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
1592
1593         for_each_fw_domain_masked(domain, fw_domains, uncore, tmp)
1594                 fw_domain_arm_timer(domain);
1595
1596         fw_domains_get(uncore, fw_domains);
1597 }
1598
1599 static inline void __force_wake_auto(struct intel_uncore *uncore,
1600                                      enum forcewake_domains fw_domains)
1601 {
1602         GEM_BUG_ON(!fw_domains);
1603
1604         /* Turn on all requested but inactive supported forcewake domains. */
1605         fw_domains &= uncore->fw_domains;
1606         fw_domains &= ~uncore->fw_domains_active;
1607
1608         if (fw_domains)
1609                 ___force_wake_auto(uncore, fw_domains);
1610 }
1611
1612 #define __gen_fwtable_read(x) \
1613 static u##x \
1614 fwtable_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) \
1615 { \
1616         enum forcewake_domains fw_engine; \
1617         GEN6_READ_HEADER(x); \
1618         fw_engine = __fwtable_reg_read_fw_domains(uncore, offset); \
1619         if (fw_engine) \
1620                 __force_wake_auto(uncore, fw_engine); \
1621         val = __raw_uncore_read##x(uncore, reg); \
1622         GEN6_READ_FOOTER; \
1623 }
1624
1625 static enum forcewake_domains
1626 fwtable_reg_read_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) {
1627         return __fwtable_reg_read_fw_domains(uncore, i915_mmio_reg_offset(reg));
1628 }
1629
1630 __gen_fwtable_read(8)
1631 __gen_fwtable_read(16)
1632 __gen_fwtable_read(32)
1633 __gen_fwtable_read(64)
1634
1635 #undef __gen_fwtable_read
1636 #undef GEN6_READ_FOOTER
1637 #undef GEN6_READ_HEADER
1638
1639 #define GEN2_WRITE_HEADER \
1640         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1641         assert_rpm_wakelock_held(uncore->rpm); \
1642
1643 #define GEN2_WRITE_FOOTER
1644
1645 #define __gen2_write(x) \
1646 static void \
1647 gen2_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1648         GEN2_WRITE_HEADER; \
1649         __raw_uncore_write##x(uncore, reg, val); \
1650         GEN2_WRITE_FOOTER; \
1651 }
1652
1653 #define __gen5_write(x) \
1654 static void \
1655 gen5_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1656         GEN2_WRITE_HEADER; \
1657         ilk_dummy_write(uncore); \
1658         __raw_uncore_write##x(uncore, reg, val); \
1659         GEN2_WRITE_FOOTER; \
1660 }
1661
1662 __gen5_write(8)
1663 __gen5_write(16)
1664 __gen5_write(32)
1665 __gen2_write(8)
1666 __gen2_write(16)
1667 __gen2_write(32)
1668
1669 #undef __gen5_write
1670 #undef __gen2_write
1671
1672 #undef GEN2_WRITE_FOOTER
1673 #undef GEN2_WRITE_HEADER
1674
1675 #define GEN6_WRITE_HEADER \
1676         u32 offset = i915_mmio_reg_offset(reg); \
1677         unsigned long irqflags; \
1678         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1679         assert_rpm_wakelock_held(uncore->rpm); \
1680         spin_lock_irqsave(&uncore->lock, irqflags); \
1681         unclaimed_reg_debug(uncore, reg, false, true)
1682
1683 #define GEN6_WRITE_FOOTER \
1684         unclaimed_reg_debug(uncore, reg, false, false); \
1685         spin_unlock_irqrestore(&uncore->lock, irqflags)
1686
1687 #define __gen6_write(x) \
1688 static void \
1689 gen6_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1690         GEN6_WRITE_HEADER; \
1691         if (NEEDS_FORCE_WAKE(offset)) \
1692                 __gen6_gt_wait_for_fifo(uncore); \
1693         __raw_uncore_write##x(uncore, reg, val); \
1694         GEN6_WRITE_FOOTER; \
1695 }
1696 __gen6_write(8)
1697 __gen6_write(16)
1698 __gen6_write(32)
1699
1700 #define __gen_fwtable_write(x) \
1701 static void \
1702 fwtable_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1703         enum forcewake_domains fw_engine; \
1704         GEN6_WRITE_HEADER; \
1705         fw_engine = __fwtable_reg_write_fw_domains(uncore, offset); \
1706         if (fw_engine) \
1707                 __force_wake_auto(uncore, fw_engine); \
1708         __raw_uncore_write##x(uncore, reg, val); \
1709         GEN6_WRITE_FOOTER; \
1710 }
1711
1712 static enum forcewake_domains
1713 fwtable_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg)
1714 {
1715         return __fwtable_reg_write_fw_domains(uncore, i915_mmio_reg_offset(reg));
1716 }
1717
1718 __gen_fwtable_write(8)
1719 __gen_fwtable_write(16)
1720 __gen_fwtable_write(32)
1721
1722 #undef __gen_fwtable_write
1723 #undef GEN6_WRITE_FOOTER
1724 #undef GEN6_WRITE_HEADER
1725
1726 #define __vgpu_write(x) \
1727 static void \
1728 vgpu_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1729         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1730         __raw_uncore_write##x(uncore, reg, val); \
1731 }
1732 __vgpu_write(8)
1733 __vgpu_write(16)
1734 __vgpu_write(32)
1735
1736 #define ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, x) \
1737 do { \
1738         (uncore)->funcs.mmio_writeb = x##_write8; \
1739         (uncore)->funcs.mmio_writew = x##_write16; \
1740         (uncore)->funcs.mmio_writel = x##_write32; \
1741 } while (0)
1742
1743 #define ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x) \
1744 do { \
1745         (uncore)->funcs.mmio_readb = x##_read8; \
1746         (uncore)->funcs.mmio_readw = x##_read16; \
1747         (uncore)->funcs.mmio_readl = x##_read32; \
1748         (uncore)->funcs.mmio_readq = x##_read64; \
1749 } while (0)
1750
1751 #define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \
1752 do { \
1753         ASSIGN_RAW_WRITE_MMIO_VFUNCS((uncore), x); \
1754         (uncore)->funcs.write_fw_domains = x##_reg_write_fw_domains; \
1755 } while (0)
1756
1757 #define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \
1758 do { \
1759         ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x); \
1760         (uncore)->funcs.read_fw_domains = x##_reg_read_fw_domains; \
1761 } while (0)
1762
1763 static int __fw_domain_init(struct intel_uncore *uncore,
1764                             enum forcewake_domain_id domain_id,
1765                             i915_reg_t reg_set,
1766                             i915_reg_t reg_ack)
1767 {
1768         struct intel_uncore_forcewake_domain *d;
1769
1770         GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT);
1771         GEM_BUG_ON(uncore->fw_domain[domain_id]);
1772
1773         if (i915_inject_probe_failure(uncore->i915))
1774                 return -ENOMEM;
1775
1776         d = kzalloc(sizeof(*d), GFP_KERNEL);
1777         if (!d)
1778                 return -ENOMEM;
1779
1780         drm_WARN_ON(&uncore->i915->drm, !i915_mmio_reg_valid(reg_set));
1781         drm_WARN_ON(&uncore->i915->drm, !i915_mmio_reg_valid(reg_ack));
1782
1783         d->uncore = uncore;
1784         d->wake_count = 0;
1785         d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set);
1786         d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack);
1787
1788         d->id = domain_id;
1789
1790         BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER));
1791         BUILD_BUG_ON(FORCEWAKE_GT != (1 << FW_DOMAIN_ID_GT));
1792         BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA));
1793         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX0));
1794         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX1));
1795         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX2));
1796         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX3));
1797         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX4 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX4));
1798         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX5 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX5));
1799         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX6 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX6));
1800         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX7 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX7));
1801         BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX0));
1802         BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX1));
1803         BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX2));
1804         BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX3));
1805
1806         d->mask = BIT(domain_id);
1807
1808         hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1809         d->timer.function = intel_uncore_fw_release_timer;
1810
1811         uncore->fw_domains |= BIT(domain_id);
1812
1813         fw_domain_reset(d);
1814
1815         uncore->fw_domain[domain_id] = d;
1816
1817         return 0;
1818 }
1819
1820 static void fw_domain_fini(struct intel_uncore *uncore,
1821                            enum forcewake_domain_id domain_id)
1822 {
1823         struct intel_uncore_forcewake_domain *d;
1824
1825         GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT);
1826
1827         d = fetch_and_zero(&uncore->fw_domain[domain_id]);
1828         if (!d)
1829                 return;
1830
1831         uncore->fw_domains &= ~BIT(domain_id);
1832         drm_WARN_ON(&uncore->i915->drm, d->wake_count);
1833         drm_WARN_ON(&uncore->i915->drm, hrtimer_cancel(&d->timer));
1834         kfree(d);
1835 }
1836
1837 static void intel_uncore_fw_domains_fini(struct intel_uncore *uncore)
1838 {
1839         struct intel_uncore_forcewake_domain *d;
1840         int tmp;
1841
1842         for_each_fw_domain(d, uncore, tmp)
1843                 fw_domain_fini(uncore, d->id);
1844 }
1845
1846 static const struct intel_uncore_fw_get uncore_get_fallback = {
1847         .force_wake_get = fw_domains_get_with_fallback
1848 };
1849
1850 static const struct intel_uncore_fw_get uncore_get_normal = {
1851         .force_wake_get = fw_domains_get_normal,
1852 };
1853
1854 static const struct intel_uncore_fw_get uncore_get_thread_status = {
1855         .force_wake_get = fw_domains_get_with_thread_status
1856 };
1857
1858 static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
1859 {
1860         struct drm_i915_private *i915 = uncore->i915;
1861         int ret = 0;
1862
1863         GEM_BUG_ON(!intel_uncore_has_forcewake(uncore));
1864
1865 #define fw_domain_init(uncore__, id__, set__, ack__) \
1866         (ret ?: (ret = __fw_domain_init((uncore__), (id__), (set__), (ack__))))
1867
1868         if (GRAPHICS_VER(i915) >= 11) {
1869                 /* we'll prune the domains of missing engines later */
1870                 intel_engine_mask_t emask = INTEL_INFO(i915)->platform_engine_mask;
1871                 int i;
1872
1873                 uncore->fw_get_funcs = &uncore_get_fallback;
1874                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1875                                FORCEWAKE_RENDER_GEN9,
1876                                FORCEWAKE_ACK_RENDER_GEN9);
1877                 fw_domain_init(uncore, FW_DOMAIN_ID_GT,
1878                                FORCEWAKE_GT_GEN9,
1879                                FORCEWAKE_ACK_GT_GEN9);
1880
1881                 for (i = 0; i < I915_MAX_VCS; i++) {
1882                         if (!__HAS_ENGINE(emask, _VCS(i)))
1883                                 continue;
1884
1885                         fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VDBOX0 + i,
1886                                        FORCEWAKE_MEDIA_VDBOX_GEN11(i),
1887                                        FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(i));
1888                 }
1889                 for (i = 0; i < I915_MAX_VECS; i++) {
1890                         if (!__HAS_ENGINE(emask, _VECS(i)))
1891                                 continue;
1892
1893                         fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VEBOX0 + i,
1894                                        FORCEWAKE_MEDIA_VEBOX_GEN11(i),
1895                                        FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i));
1896                 }
1897         } else if (IS_GRAPHICS_VER(i915, 9, 10)) {
1898                 uncore->fw_get_funcs = &uncore_get_fallback;
1899                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1900                                FORCEWAKE_RENDER_GEN9,
1901                                FORCEWAKE_ACK_RENDER_GEN9);
1902                 fw_domain_init(uncore, FW_DOMAIN_ID_GT,
1903                                FORCEWAKE_GT_GEN9,
1904                                FORCEWAKE_ACK_GT_GEN9);
1905                 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA,
1906                                FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1907         } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
1908                 uncore->fw_get_funcs = &uncore_get_normal;
1909                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1910                                FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1911                 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA,
1912                                FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1913         } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
1914                 uncore->fw_get_funcs = &uncore_get_thread_status;
1915                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1916                                FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1917         } else if (IS_IVYBRIDGE(i915)) {
1918                 u32 ecobus;
1919
1920                 /* IVB configs may use multi-threaded forcewake */
1921
1922                 /* A small trick here - if the bios hasn't configured
1923                  * MT forcewake, and if the device is in RC6, then
1924                  * force_wake_mt_get will not wake the device and the
1925                  * ECOBUS read will return zero. Which will be
1926                  * (correctly) interpreted by the test below as MT
1927                  * forcewake being disabled.
1928                  */
1929                 uncore->fw_get_funcs = &uncore_get_thread_status;
1930
1931                 /* We need to init first for ECOBUS access and then
1932                  * determine later if we want to reinit, in case of MT access is
1933                  * not working. In this stage we don't know which flavour this
1934                  * ivb is, so it is better to reset also the gen6 fw registers
1935                  * before the ecobus check.
1936                  */
1937
1938                 __raw_uncore_write32(uncore, FORCEWAKE, 0);
1939                 __raw_posting_read(uncore, ECOBUS);
1940
1941                 ret = __fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1942                                        FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1943                 if (ret)
1944                         goto out;
1945
1946                 spin_lock_irq(&uncore->lock);
1947                 fw_domains_get_with_thread_status(uncore, FORCEWAKE_RENDER);
1948                 ecobus = __raw_uncore_read32(uncore, ECOBUS);
1949                 fw_domains_put(uncore, FORCEWAKE_RENDER);
1950                 spin_unlock_irq(&uncore->lock);
1951
1952                 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1953                         drm_info(&i915->drm, "No MT forcewake available on Ivybridge, this can result in issues\n");
1954                         drm_info(&i915->drm, "when using vblank-synced partial screen updates.\n");
1955                         fw_domain_fini(uncore, FW_DOMAIN_ID_RENDER);
1956                         fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1957                                        FORCEWAKE, FORCEWAKE_ACK);
1958                 }
1959         } else if (GRAPHICS_VER(i915) == 6) {
1960                 uncore->fw_get_funcs = &uncore_get_thread_status;
1961                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1962                                FORCEWAKE, FORCEWAKE_ACK);
1963         }
1964
1965 #undef fw_domain_init
1966
1967         /* All future platforms are expected to require complex power gating */
1968         drm_WARN_ON(&i915->drm, !ret && uncore->fw_domains == 0);
1969
1970 out:
1971         if (ret)
1972                 intel_uncore_fw_domains_fini(uncore);
1973
1974         return ret;
1975 }
1976
1977 #define ASSIGN_FW_DOMAINS_TABLE(uncore, d) \
1978 { \
1979         (uncore)->fw_domains_table = \
1980                         (struct intel_forcewake_range *)(d); \
1981         (uncore)->fw_domains_table_entries = ARRAY_SIZE((d)); \
1982 }
1983
1984 #define ASSIGN_SHADOW_TABLE(uncore, d) \
1985 { \
1986         (uncore)->shadowed_reg_table = d; \
1987         (uncore)->shadowed_reg_table_entries = ARRAY_SIZE((d)); \
1988 }
1989
1990 static int i915_pmic_bus_access_notifier(struct notifier_block *nb,
1991                                          unsigned long action, void *data)
1992 {
1993         struct intel_uncore *uncore = container_of(nb,
1994                         struct intel_uncore, pmic_bus_access_nb);
1995
1996         switch (action) {
1997         case MBI_PMIC_BUS_ACCESS_BEGIN:
1998                 /*
1999                  * forcewake all now to make sure that we don't need to do a
2000                  * forcewake later which on systems where this notifier gets
2001                  * called requires the punit to access to the shared pmic i2c
2002                  * bus, which will be busy after this notification, leading to:
2003                  * "render: timed out waiting for forcewake ack request."
2004                  * errors.
2005                  *
2006                  * The notifier is unregistered during intel_runtime_suspend(),
2007                  * so it's ok to access the HW here without holding a RPM
2008                  * wake reference -> disable wakeref asserts for the time of
2009                  * the access.
2010                  */
2011                 disable_rpm_wakeref_asserts(uncore->rpm);
2012                 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
2013                 enable_rpm_wakeref_asserts(uncore->rpm);
2014                 break;
2015         case MBI_PMIC_BUS_ACCESS_END:
2016                 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
2017                 break;
2018         }
2019
2020         return NOTIFY_OK;
2021 }
2022
2023 int intel_uncore_setup_mmio(struct intel_uncore *uncore)
2024 {
2025         struct drm_i915_private *i915 = uncore->i915;
2026         struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
2027         int mmio_bar;
2028         int mmio_size;
2029
2030         mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0;
2031         /*
2032          * Before gen4, the registers and the GTT are behind different BARs.
2033          * However, from gen4 onwards, the registers and the GTT are shared
2034          * in the same BAR, so we want to restrict this ioremap from
2035          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
2036          * the register BAR remains the same size for all the earlier
2037          * generations up to Ironlake.
2038          * For dgfx chips register range is expanded to 4MB.
2039          */
2040         if (GRAPHICS_VER(i915) < 5)
2041                 mmio_size = 512 * 1024;
2042         else if (IS_DGFX(i915))
2043                 mmio_size = 4 * 1024 * 1024;
2044         else
2045                 mmio_size = 2 * 1024 * 1024;
2046
2047         uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size);
2048         if (uncore->regs == NULL) {
2049                 drm_err(&i915->drm, "failed to map registers\n");
2050                 return -EIO;
2051         }
2052
2053         return 0;
2054 }
2055
2056 void intel_uncore_cleanup_mmio(struct intel_uncore *uncore)
2057 {
2058         struct pci_dev *pdev = to_pci_dev(uncore->i915->drm.dev);
2059
2060         pci_iounmap(pdev, uncore->regs);
2061 }
2062
2063 void intel_uncore_init_early(struct intel_uncore *uncore,
2064                              struct intel_gt *gt)
2065 {
2066         spin_lock_init(&uncore->lock);
2067         uncore->i915 = gt->i915;
2068         uncore->gt = gt;
2069         uncore->rpm = &gt->i915->runtime_pm;
2070         uncore->debug = &gt->i915->mmio_debug;
2071 }
2072
2073 static void uncore_raw_init(struct intel_uncore *uncore)
2074 {
2075         GEM_BUG_ON(intel_uncore_has_forcewake(uncore));
2076
2077         if (intel_vgpu_active(uncore->i915)) {
2078                 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, vgpu);
2079                 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, vgpu);
2080         } else if (GRAPHICS_VER(uncore->i915) == 5) {
2081                 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen5);
2082                 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen5);
2083         } else {
2084                 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen2);
2085                 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen2);
2086         }
2087 }
2088
2089 static int uncore_forcewake_init(struct intel_uncore *uncore)
2090 {
2091         struct drm_i915_private *i915 = uncore->i915;
2092         int ret;
2093
2094         GEM_BUG_ON(!intel_uncore_has_forcewake(uncore));
2095
2096         ret = intel_uncore_fw_domains_init(uncore);
2097         if (ret)
2098                 return ret;
2099         forcewake_early_sanitize(uncore, 0);
2100
2101         ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
2102
2103         if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
2104                 ASSIGN_FW_DOMAINS_TABLE(uncore, __dg2_fw_ranges);
2105                 ASSIGN_SHADOW_TABLE(uncore, dg2_shadowed_regs);
2106                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
2107         } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
2108                 ASSIGN_FW_DOMAINS_TABLE(uncore, __xehp_fw_ranges);
2109                 ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);
2110                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
2111         } else if (GRAPHICS_VER(i915) >= 12) {
2112                 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges);
2113                 ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);
2114                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
2115         } else if (GRAPHICS_VER(i915) == 11) {
2116                 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen11_fw_ranges);
2117                 ASSIGN_SHADOW_TABLE(uncore, gen11_shadowed_regs);
2118                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
2119         } else if (IS_GRAPHICS_VER(i915, 9, 10)) {
2120                 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen9_fw_ranges);
2121                 ASSIGN_SHADOW_TABLE(uncore, gen8_shadowed_regs);
2122                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
2123         } else if (IS_CHERRYVIEW(i915)) {
2124                 ASSIGN_FW_DOMAINS_TABLE(uncore, __chv_fw_ranges);
2125                 ASSIGN_SHADOW_TABLE(uncore, gen8_shadowed_regs);
2126                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
2127         } else if (GRAPHICS_VER(i915) == 8) {
2128                 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen6_fw_ranges);
2129                 ASSIGN_SHADOW_TABLE(uncore, gen8_shadowed_regs);
2130                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
2131         } else if (IS_VALLEYVIEW(i915)) {
2132                 ASSIGN_FW_DOMAINS_TABLE(uncore, __vlv_fw_ranges);
2133                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6);
2134         } else if (IS_GRAPHICS_VER(i915, 6, 7)) {
2135                 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen6_fw_ranges);
2136                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6);
2137         }
2138
2139         uncore->pmic_bus_access_nb.notifier_call = i915_pmic_bus_access_notifier;
2140         iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
2141
2142         return 0;
2143 }
2144
2145 int intel_uncore_init_mmio(struct intel_uncore *uncore)
2146 {
2147         struct drm_i915_private *i915 = uncore->i915;
2148         int ret;
2149
2150         /*
2151          * The boot firmware initializes local memory and assesses its health.
2152          * If memory training fails, the punit will have been instructed to
2153          * keep the GT powered down; we won't be able to communicate with it
2154          * and we should not continue with driver initialization.
2155          */
2156         if (IS_DGFX(i915) &&
2157             !(__raw_uncore_read32(uncore, GU_CNTL) & LMEM_INIT)) {
2158                 drm_err(&i915->drm, "LMEM not initialized by firmware\n");
2159                 return -ENODEV;
2160         }
2161
2162         if (GRAPHICS_VER(i915) > 5 && !intel_vgpu_active(i915))
2163                 uncore->flags |= UNCORE_HAS_FORCEWAKE;
2164
2165         if (!intel_uncore_has_forcewake(uncore)) {
2166                 uncore_raw_init(uncore);
2167         } else {
2168                 ret = uncore_forcewake_init(uncore);
2169                 if (ret)
2170                         return ret;
2171         }
2172
2173         /* make sure fw funcs are set if and only if we have fw*/
2174         GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->fw_get_funcs);
2175         GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.read_fw_domains);
2176         GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.write_fw_domains);
2177
2178         if (HAS_FPGA_DBG_UNCLAIMED(i915))
2179                 uncore->flags |= UNCORE_HAS_FPGA_DBG_UNCLAIMED;
2180
2181         if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
2182                 uncore->flags |= UNCORE_HAS_DBG_UNCLAIMED;
2183
2184         if (IS_GRAPHICS_VER(i915, 6, 7))
2185                 uncore->flags |= UNCORE_HAS_FIFO;
2186
2187         /* clear out unclaimed reg detection bit */
2188         if (intel_uncore_unclaimed_mmio(uncore))
2189                 drm_dbg(&i915->drm, "unclaimed mmio detected on uncore init, clearing\n");
2190
2191         return 0;
2192 }
2193
2194 /*
2195  * We might have detected that some engines are fused off after we initialized
2196  * the forcewake domains. Prune them, to make sure they only reference existing
2197  * engines.
2198  */
2199 void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
2200                                           struct intel_gt *gt)
2201 {
2202         enum forcewake_domains fw_domains = uncore->fw_domains;
2203         enum forcewake_domain_id domain_id;
2204         int i;
2205
2206         if (!intel_uncore_has_forcewake(uncore) || GRAPHICS_VER(uncore->i915) < 11)
2207                 return;
2208
2209         for (i = 0; i < I915_MAX_VCS; i++) {
2210                 domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i;
2211
2212                 if (HAS_ENGINE(gt, _VCS(i)))
2213                         continue;
2214
2215                 /*
2216                  * Starting with XeHP, the power well for an even-numbered
2217                  * VDBOX is also used for shared units within the
2218                  * media slice such as SFC.  So even if the engine
2219                  * itself is fused off, we still need to initialize
2220                  * the forcewake domain if any of the other engines
2221                  * in the same media slice are present.
2222                  */
2223                 if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 50) && i % 2 == 0) {
2224                         if ((i + 1 < I915_MAX_VCS) && HAS_ENGINE(gt, _VCS(i + 1)))
2225                                 continue;
2226
2227                         if (HAS_ENGINE(gt, _VECS(i / 2)))
2228                                 continue;
2229                 }
2230
2231                 if (fw_domains & BIT(domain_id))
2232                         fw_domain_fini(uncore, domain_id);
2233         }
2234
2235         for (i = 0; i < I915_MAX_VECS; i++) {
2236                 domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i;
2237
2238                 if (HAS_ENGINE(gt, _VECS(i)))
2239                         continue;
2240
2241                 if (fw_domains & BIT(domain_id))
2242                         fw_domain_fini(uncore, domain_id);
2243         }
2244 }
2245
2246 void intel_uncore_fini_mmio(struct intel_uncore *uncore)
2247 {
2248         if (intel_uncore_has_forcewake(uncore)) {
2249                 iosf_mbi_punit_acquire();
2250                 iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
2251                         &uncore->pmic_bus_access_nb);
2252                 intel_uncore_forcewake_reset(uncore);
2253                 intel_uncore_fw_domains_fini(uncore);
2254                 iosf_mbi_punit_release();
2255         }
2256 }
2257
2258 static const struct reg_whitelist {
2259         i915_reg_t offset_ldw;
2260         i915_reg_t offset_udw;
2261         u8 min_graphics_ver;
2262         u8 max_graphics_ver;
2263         u8 size;
2264 } reg_read_whitelist[] = { {
2265         .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
2266         .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
2267         .min_graphics_ver = 4,
2268         .max_graphics_ver = 12,
2269         .size = 8
2270 } };
2271
2272 int i915_reg_read_ioctl(struct drm_device *dev,
2273                         void *data, struct drm_file *file)
2274 {
2275         struct drm_i915_private *i915 = to_i915(dev);
2276         struct intel_uncore *uncore = &i915->uncore;
2277         struct drm_i915_reg_read *reg = data;
2278         struct reg_whitelist const *entry;
2279         intel_wakeref_t wakeref;
2280         unsigned int flags;
2281         int remain;
2282         int ret = 0;
2283
2284         entry = reg_read_whitelist;
2285         remain = ARRAY_SIZE(reg_read_whitelist);
2286         while (remain) {
2287                 u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);
2288
2289                 GEM_BUG_ON(!is_power_of_2(entry->size));
2290                 GEM_BUG_ON(entry->size > 8);
2291                 GEM_BUG_ON(entry_offset & (entry->size - 1));
2292
2293                 if (IS_GRAPHICS_VER(i915, entry->min_graphics_ver, entry->max_graphics_ver) &&
2294                     entry_offset == (reg->offset & -entry->size))
2295                         break;
2296                 entry++;
2297                 remain--;
2298         }
2299
2300         if (!remain)
2301                 return -EINVAL;
2302
2303         flags = reg->offset & (entry->size - 1);
2304
2305         with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
2306                 if (entry->size == 8 && flags == I915_REG_READ_8B_WA)
2307                         reg->val = intel_uncore_read64_2x32(uncore,
2308                                                             entry->offset_ldw,
2309                                                             entry->offset_udw);
2310                 else if (entry->size == 8 && flags == 0)
2311                         reg->val = intel_uncore_read64(uncore,
2312                                                        entry->offset_ldw);
2313                 else if (entry->size == 4 && flags == 0)
2314                         reg->val = intel_uncore_read(uncore, entry->offset_ldw);
2315                 else if (entry->size == 2 && flags == 0)
2316                         reg->val = intel_uncore_read16(uncore,
2317                                                        entry->offset_ldw);
2318                 else if (entry->size == 1 && flags == 0)
2319                         reg->val = intel_uncore_read8(uncore,
2320                                                       entry->offset_ldw);
2321                 else
2322                         ret = -EINVAL;
2323         }
2324
2325         return ret;
2326 }
2327
2328 /**
2329  * __intel_wait_for_register_fw - wait until register matches expected state
2330  * @uncore: the struct intel_uncore
2331  * @reg: the register to read
2332  * @mask: mask to apply to register value
2333  * @value: expected value
2334  * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait
2335  * @slow_timeout_ms: slow timeout in millisecond
2336  * @out_value: optional placeholder to hold registry value
2337  *
2338  * This routine waits until the target register @reg contains the expected
2339  * @value after applying the @mask, i.e. it waits until ::
2340  *
2341  *     (intel_uncore_read_fw(uncore, reg) & mask) == value
2342  *
2343  * Otherwise, the wait will timeout after @slow_timeout_ms milliseconds.
2344  * For atomic context @slow_timeout_ms must be zero and @fast_timeout_us
2345  * must be not larger than 20,0000 microseconds.
2346  *
2347  * Note that this routine assumes the caller holds forcewake asserted, it is
2348  * not suitable for very long waits. See intel_wait_for_register() if you
2349  * wish to wait without holding forcewake for the duration (i.e. you expect
2350  * the wait to be slow).
2351  *
2352  * Return: 0 if the register matches the desired condition, or -ETIMEDOUT.
2353  */
2354 int __intel_wait_for_register_fw(struct intel_uncore *uncore,
2355                                  i915_reg_t reg,
2356                                  u32 mask,
2357                                  u32 value,
2358                                  unsigned int fast_timeout_us,
2359                                  unsigned int slow_timeout_ms,
2360                                  u32 *out_value)
2361 {
2362         u32 reg_value = 0;
2363 #define done (((reg_value = intel_uncore_read_fw(uncore, reg)) & mask) == value)
2364         int ret;
2365
2366         /* Catch any overuse of this function */
2367         might_sleep_if(slow_timeout_ms);
2368         GEM_BUG_ON(fast_timeout_us > 20000);
2369         GEM_BUG_ON(!fast_timeout_us && !slow_timeout_ms);
2370
2371         ret = -ETIMEDOUT;
2372         if (fast_timeout_us && fast_timeout_us <= 20000)
2373                 ret = _wait_for_atomic(done, fast_timeout_us, 0);
2374         if (ret && slow_timeout_ms)
2375                 ret = wait_for(done, slow_timeout_ms);
2376
2377         if (out_value)
2378                 *out_value = reg_value;
2379
2380         return ret;
2381 #undef done
2382 }
2383
2384 /**
2385  * __intel_wait_for_register - wait until register matches expected state
2386  * @uncore: the struct intel_uncore
2387  * @reg: the register to read
2388  * @mask: mask to apply to register value
2389  * @value: expected value
2390  * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait
2391  * @slow_timeout_ms: slow timeout in millisecond
2392  * @out_value: optional placeholder to hold registry value
2393  *
2394  * This routine waits until the target register @reg contains the expected
2395  * @value after applying the @mask, i.e. it waits until ::
2396  *
2397  *     (intel_uncore_read(uncore, reg) & mask) == value
2398  *
2399  * Otherwise, the wait will timeout after @timeout_ms milliseconds.
2400  *
2401  * Return: 0 if the register matches the desired condition, or -ETIMEDOUT.
2402  */
2403 int __intel_wait_for_register(struct intel_uncore *uncore,
2404                               i915_reg_t reg,
2405                               u32 mask,
2406                               u32 value,
2407                               unsigned int fast_timeout_us,
2408                               unsigned int slow_timeout_ms,
2409                               u32 *out_value)
2410 {
2411         unsigned fw =
2412                 intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ);
2413         u32 reg_value;
2414         int ret;
2415
2416         might_sleep_if(slow_timeout_ms);
2417
2418         spin_lock_irq(&uncore->lock);
2419         intel_uncore_forcewake_get__locked(uncore, fw);
2420
2421         ret = __intel_wait_for_register_fw(uncore,
2422                                            reg, mask, value,
2423                                            fast_timeout_us, 0, &reg_value);
2424
2425         intel_uncore_forcewake_put__locked(uncore, fw);
2426         spin_unlock_irq(&uncore->lock);
2427
2428         if (ret && slow_timeout_ms)
2429                 ret = __wait_for(reg_value = intel_uncore_read_notrace(uncore,
2430                                                                        reg),
2431                                  (reg_value & mask) == value,
2432                                  slow_timeout_ms * 1000, 10, 1000);
2433
2434         /* just trace the final value */
2435         trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
2436
2437         if (out_value)
2438                 *out_value = reg_value;
2439
2440         return ret;
2441 }
2442
2443 bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore)
2444 {
2445         bool ret;
2446
2447         spin_lock_irq(&uncore->debug->lock);
2448         ret = check_for_unclaimed_mmio(uncore);
2449         spin_unlock_irq(&uncore->debug->lock);
2450
2451         return ret;
2452 }
2453
2454 bool
2455 intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore)
2456 {
2457         bool ret = false;
2458
2459         spin_lock_irq(&uncore->debug->lock);
2460
2461         if (unlikely(uncore->debug->unclaimed_mmio_check <= 0))
2462                 goto out;
2463
2464         if (unlikely(check_for_unclaimed_mmio(uncore))) {
2465                 if (!uncore->i915->params.mmio_debug) {
2466                         drm_dbg(&uncore->i915->drm,
2467                                 "Unclaimed register detected, "
2468                                 "enabling oneshot unclaimed register reporting. "
2469                                 "Please use i915.mmio_debug=N for more information.\n");
2470                         uncore->i915->params.mmio_debug++;
2471                 }
2472                 uncore->debug->unclaimed_mmio_check--;
2473                 ret = true;
2474         }
2475
2476 out:
2477         spin_unlock_irq(&uncore->debug->lock);
2478
2479         return ret;
2480 }
2481
2482 /**
2483  * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
2484  *                                  a register
2485  * @uncore: pointer to struct intel_uncore
2486  * @reg: register in question
2487  * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE
2488  *
2489  * Returns a set of forcewake domains required to be taken with for example
2490  * intel_uncore_forcewake_get for the specified register to be accessible in the
2491  * specified mode (read, write or read/write) with raw mmio accessors.
2492  *
2493  * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the
2494  * callers to do FIFO management on their own or risk losing writes.
2495  */
2496 enum forcewake_domains
2497 intel_uncore_forcewake_for_reg(struct intel_uncore *uncore,
2498                                i915_reg_t reg, unsigned int op)
2499 {
2500         enum forcewake_domains fw_domains = 0;
2501
2502         drm_WARN_ON(&uncore->i915->drm, !op);
2503
2504         if (!intel_uncore_has_forcewake(uncore))
2505                 return 0;
2506
2507         if (op & FW_REG_READ)
2508                 fw_domains = uncore->funcs.read_fw_domains(uncore, reg);
2509
2510         if (op & FW_REG_WRITE)
2511                 fw_domains |= uncore->funcs.write_fw_domains(uncore, reg);
2512
2513         drm_WARN_ON(&uncore->i915->drm, fw_domains & ~uncore->fw_domains);
2514
2515         return fw_domains;
2516 }
2517
2518 u32 intel_uncore_read_with_mcr_steering_fw(struct intel_uncore *uncore,
2519                                            i915_reg_t reg,
2520                                            int slice, int subslice)
2521 {
2522         u32 mcr_mask, mcr_ss, mcr, old_mcr, val;
2523
2524         lockdep_assert_held(&uncore->lock);
2525
2526         if (GRAPHICS_VER(uncore->i915) >= 11) {
2527                 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
2528                 mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
2529         } else {
2530                 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
2531                 mcr_ss = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
2532         }
2533
2534         old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
2535
2536         mcr &= ~mcr_mask;
2537         mcr |= mcr_ss;
2538         intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
2539
2540         val = intel_uncore_read_fw(uncore, reg);
2541
2542         mcr &= ~mcr_mask;
2543         mcr |= old_mcr & mcr_mask;
2544
2545         intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
2546
2547         return val;
2548 }
2549
2550 u32 intel_uncore_read_with_mcr_steering(struct intel_uncore *uncore,
2551                                         i915_reg_t reg, int slice, int subslice)
2552 {
2553         enum forcewake_domains fw_domains;
2554         u32 val;
2555
2556         fw_domains = intel_uncore_forcewake_for_reg(uncore, reg,
2557                                                     FW_REG_READ);
2558         fw_domains |= intel_uncore_forcewake_for_reg(uncore,
2559                                                      GEN8_MCR_SELECTOR,
2560                                                      FW_REG_READ | FW_REG_WRITE);
2561
2562         spin_lock_irq(&uncore->lock);
2563         intel_uncore_forcewake_get__locked(uncore, fw_domains);
2564
2565         val = intel_uncore_read_with_mcr_steering_fw(uncore, reg, slice, subslice);
2566
2567         intel_uncore_forcewake_put__locked(uncore, fw_domains);
2568         spin_unlock_irq(&uncore->lock);
2569
2570         return val;
2571 }
2572
2573 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2574 #include "selftests/mock_uncore.c"
2575 #include "selftests/intel_uncore.c"
2576 #endif