drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <linux/log2.h>
  31
  32 #include <drm/drmP.h>
  33 #include <drm/i915_drm.h>
  34
  35 #include "i915_drv.h"
  36 #include "i915_gem_render_state.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39 #include "intel_workarounds.h"
  40
  41 /* Rough estimate of the typical request size, performing a flush,
  42  * set-context and then emitting the batch.
  43  */
  44 #define LEGACY_REQUEST_SIZE 200
  45
  46 static unsigned int __intel_ring_space(unsigned int head,
  47                                        unsigned int tail,
  48                                        unsigned int size)
  49 {
  50         /*
  51          * "If the Ring Buffer Head Pointer and the Tail Pointer are on the
  52          * same cacheline, the Head Pointer must not be greater than the Tail
  53          * Pointer."
  54          */
  55         GEM_BUG_ON(!is_power_of_2(size));
  56         return (head - tail - CACHELINE_BYTES) & (size - 1);
  57 }
  58
  59 unsigned int intel_ring_update_space(struct intel_ring *ring)
  60 {
  61         unsigned int space;
  62
  63         space = __intel_ring_space(ring->head, ring->emit, ring->size);
  64
  65         ring->space = space;
  66         return space;
  67 }
  68
  69 static int
  70 gen2_render_ring_flush(struct i915_request *rq, u32 mode)
  71 {
  72         u32 cmd, *cs;
  73
  74         cmd = MI_FLUSH;
  75
  76         if (mode & EMIT_INVALIDATE)
  77                 cmd |= MI_READ_FLUSH;
  78
  79         cs = intel_ring_begin(rq, 2);
  80         if (IS_ERR(cs))
  81                 return PTR_ERR(cs);
  82
  83         *cs++ = cmd;
  84         *cs++ = MI_NOOP;
  85         intel_ring_advance(rq, cs);
  86
  87         return 0;
  88 }
  89
  90 static int
  91 gen4_render_ring_flush(struct i915_request *rq, u32 mode)
  92 {
  93         u32 cmd, *cs;
  94
  95         /*
  96          * read/write caches:
  97          *
  98          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  99          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 100          * also flushed at 2d versus 3d pipeline switches.
 101          *
 102          * read-only caches:
 103          *
 104          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 105          * MI_READ_FLUSH is set, and is always flushed on 965.
 106          *
 107          * I915_GEM_DOMAIN_COMMAND may not exist?
 108          *
 109          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 110          * invalidated when MI_EXE_FLUSH is set.
 111          *
 112          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 113          * invalidated with every MI_FLUSH.
 114          *
 115          * TLBs:
 116          *
 117          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 118          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 119          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 120          * are flushed at any MI_FLUSH.
 121          */
 122
 123         cmd = MI_FLUSH;
 124         if (mode & EMIT_INVALIDATE) {
 125                 cmd |= MI_EXE_FLUSH;
 126                 if (IS_G4X(rq->i915) || IS_GEN5(rq->i915))
 127                         cmd |= MI_INVALIDATE_ISP;
 128         }
 129
 130         cs = intel_ring_begin(rq, 2);
 131         if (IS_ERR(cs))
 132                 return PTR_ERR(cs);
 133
 134         *cs++ = cmd;
 135         *cs++ = MI_NOOP;
 136         intel_ring_advance(rq, cs);
 137
 138         return 0;
 139 }
 140
 141 /*
 142  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 143  * implementing two workarounds on gen6.  From section 1.4.7.1
 144  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 145  *
 146  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 147  * produced by non-pipelined state commands), software needs to first
 148  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 149  * 0.
 150  *
 151  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 152  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 153  *
 154  * And the workaround for these two requires this workaround first:
 155  *
 156  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 157  * BEFORE the pipe-control with a post-sync op and no write-cache
 158  * flushes.
 159  *
 160  * And this last workaround is tricky because of the requirements on
 161  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 162  * volume 2 part 1:
 163  *
 164  *     "1 of the following must also be set:
 165  *      - Render Target Cache Flush Enable ([12] of DW1)
 166  *      - Depth Cache Flush Enable ([0] of DW1)
 167  *      - Stall at Pixel Scoreboard ([1] of DW1)
 168  *      - Depth Stall ([13] of DW1)
 169  *      - Post-Sync Operation ([13] of DW1)
 170  *      - Notify Enable ([8] of DW1)"
 171  *
 172  * The cache flushes require the workaround flush that triggered this
 173  * one, so we can't use it.  Depth stall would trigger the same.
 174  * Post-sync nonzero is what triggered this second workaround, so we
 175  * can't use that one either.  Notify enable is IRQs, which aren't
 176  * really our business.  That leaves only stall at scoreboard.
 177  */
 178 static int
 179 intel_emit_post_sync_nonzero_flush(struct i915_request *rq)
 180 {
 181         u32 scratch_addr =
 182                 i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES;
 183         u32 *cs;
 184
 185         cs = intel_ring_begin(rq, 6);
 186         if (IS_ERR(cs))
 187                 return PTR_ERR(cs);
 188
 189         *cs++ = GFX_OP_PIPE_CONTROL(5);
 190         *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD;
 191         *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;
 192         *cs++ = 0; /* low dword */
 193         *cs++ = 0; /* high dword */
 194         *cs++ = MI_NOOP;
 195         intel_ring_advance(rq, cs);
 196
 197         cs = intel_ring_begin(rq, 6);
 198         if (IS_ERR(cs))
 199                 return PTR_ERR(cs);
 200
 201         *cs++ = GFX_OP_PIPE_CONTROL(5);
 202         *cs++ = PIPE_CONTROL_QW_WRITE;
 203         *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;
 204         *cs++ = 0;
 205         *cs++ = 0;
 206         *cs++ = MI_NOOP;
 207         intel_ring_advance(rq, cs);
 208
 209         return 0;
 210 }
 211
 212 static int
 213 gen6_render_ring_flush(struct i915_request *rq, u32 mode)
 214 {
 215         u32 scratch_addr =
 216                 i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES;
 217         u32 *cs, flags = 0;
 218         int ret;
 219
 220         /* Force SNB workarounds for PIPE_CONTROL flushes */
 221         ret = intel_emit_post_sync_nonzero_flush(rq);
 222         if (ret)
 223                 return ret;
 224
 225         /* Just flush everything.  Experiments have shown that reducing the
 226          * number of bits based on the write domains has little performance
 227          * impact.
 228          */
 229         if (mode & EMIT_FLUSH) {
 230                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 231                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 232                 /*
 233                  * Ensure that any following seqno writes only happen
 234                  * when the render cache is indeed flushed.
 235                  */
 236                 flags |= PIPE_CONTROL_CS_STALL;
 237         }
 238         if (mode & EMIT_INVALIDATE) {
 239                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 240                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 241                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 242                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 243                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 244                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 245                 /*
 246                  * TLB invalidate requires a post-sync write.
 247                  */
 248                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 249         }
 250
 251         cs = intel_ring_begin(rq, 4);
 252         if (IS_ERR(cs))
 253                 return PTR_ERR(cs);
 254
 255         *cs++ = GFX_OP_PIPE_CONTROL(4);
 256         *cs++ = flags;
 257         *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;
 258         *cs++ = 0;
 259         intel_ring_advance(rq, cs);
 260
 261         return 0;
 262 }
 263
 264 static int
 265 gen7_render_ring_cs_stall_wa(struct i915_request *rq)
 266 {
 267         u32 *cs;
 268
 269         cs = intel_ring_begin(rq, 4);
 270         if (IS_ERR(cs))
 271                 return PTR_ERR(cs);
 272
 273         *cs++ = GFX_OP_PIPE_CONTROL(4);
 274         *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD;
 275         *cs++ = 0;
 276         *cs++ = 0;
 277         intel_ring_advance(rq, cs);
 278
 279         return 0;
 280 }
 281
 282 static int
 283 gen7_render_ring_flush(struct i915_request *rq, u32 mode)
 284 {
 285         u32 scratch_addr =
 286                 i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES;
 287         u32 *cs, flags = 0;
 288
 289         /*
 290          * Ensure that any following seqno writes only happen when the render
 291          * cache is indeed flushed.
 292          *
 293          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 294          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 295          * don't try to be clever and just set it unconditionally.
 296          */
 297         flags |= PIPE_CONTROL_CS_STALL;
 298
 299         /* Just flush everything.  Experiments have shown that reducing the
 300          * number of bits based on the write domains has little performance
 301          * impact.
 302          */
 303         if (mode & EMIT_FLUSH) {
 304                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 305                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 306                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 307                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 308         }
 309         if (mode & EMIT_INVALIDATE) {
 310                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 311                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 312                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 313                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 314                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 315                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 316                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 317                 /*
 318                  * TLB invalidate requires a post-sync write.
 319                  */
 320                 flags |= PIPE_CONTROL_QW_WRITE;
 321                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 322
 323                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 324
 325                 /* Workaround: we must issue a pipe_control with CS-stall bit
 326                  * set before a pipe_control command that has the state cache
 327                  * invalidate bit set. */
 328                 gen7_render_ring_cs_stall_wa(rq);
 329         }
 330
 331         cs = intel_ring_begin(rq, 4);
 332         if (IS_ERR(cs))
 333                 return PTR_ERR(cs);
 334
 335         *cs++ = GFX_OP_PIPE_CONTROL(4);
 336         *cs++ = flags;
 337         *cs++ = scratch_addr;
 338         *cs++ = 0;
 339         intel_ring_advance(rq, cs);
 340
 341         return 0;
 342 }
 343
 344 static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
 345 {
 346         struct drm_i915_private *dev_priv = engine->i915;
 347         struct page *page = virt_to_page(engine->status_page.page_addr);
 348         phys_addr_t phys = PFN_PHYS(page_to_pfn(page));
 349         u32 addr;
 350
 351         addr = lower_32_bits(phys);
 352         if (INTEL_GEN(dev_priv) >= 4)
 353                 addr |= (phys >> 28) & 0xf0;
 354
 355         I915_WRITE(HWS_PGA, addr);
 356 }
 357
 358 static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
 359 {
 360         struct drm_i915_private *dev_priv = engine->i915;
 361         i915_reg_t mmio;
 362
 363         /* The ring status page addresses are no longer next to the rest of
 364          * the ring registers as of gen7.
 365          */
 366         if (IS_GEN7(dev_priv)) {
 367                 switch (engine->id) {
 368                 /*
 369                  * No more rings exist on Gen7. Default case is only to shut up
 370                  * gcc switch check warning.
 371                  */
 372                 default:
 373                         GEM_BUG_ON(engine->id);
 374                 case RCS:
 375                         mmio = RENDER_HWS_PGA_GEN7;
 376                         break;
 377                 case BCS:
 378                         mmio = BLT_HWS_PGA_GEN7;
 379                         break;
 380                 case VCS:
 381                         mmio = BSD_HWS_PGA_GEN7;
 382                         break;
 383                 case VECS:
 384                         mmio = VEBOX_HWS_PGA_GEN7;
 385                         break;
 386                 }
 387         } else if (IS_GEN6(dev_priv)) {
 388                 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
 389         } else {
 390                 mmio = RING_HWS_PGA(engine->mmio_base);
 391         }
 392
 393         if (INTEL_GEN(dev_priv) >= 6) {
 394                 u32 mask = ~0u;
 395
 396                 /*
 397                  * Keep the render interrupt unmasked as this papers over
 398                  * lost interrupts following a reset.
 399                  */
 400                 if (engine->id == RCS)
 401                         mask &= ~BIT(0);
 402
 403                 I915_WRITE(RING_HWSTAM(engine->mmio_base), mask);
 404         }
 405
 406         I915_WRITE(mmio, engine->status_page.ggtt_offset);
 407         POSTING_READ(mmio);
 408
 409         /* Flush the TLB for this page */
 410         if (IS_GEN(dev_priv, 6, 7)) {
 411                 i915_reg_t reg = RING_INSTPM(engine->mmio_base);
 412
 413                 /* ring should be idle before issuing a sync flush*/
 414                 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
 415
 416                 I915_WRITE(reg,
 417                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 418                                               INSTPM_SYNC_FLUSH));
 419                 if (intel_wait_for_register(dev_priv,
 420                                             reg, INSTPM_SYNC_FLUSH, 0,
 421                                             1000))
 422                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 423                                   engine->name);
 424         }
 425 }
 426
 427 static bool stop_ring(struct intel_engine_cs *engine)
 428 {
 429         struct drm_i915_private *dev_priv = engine->i915;
 430
 431         if (INTEL_GEN(dev_priv) > 2) {
 432                 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
 433                 if (intel_wait_for_register(dev_priv,
 434                                             RING_MI_MODE(engine->mmio_base),
 435                                             MODE_IDLE,
 436                                             MODE_IDLE,
 437                                             1000)) {
 438                         DRM_ERROR("%s : timed out trying to stop ring\n",
 439                                   engine->name);
 440                         /* Sometimes we observe that the idle flag is not
 441                          * set even though the ring is empty. So double
 442                          * check before giving up.
 443                          */
 444                         if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
 445                                 return false;
 446                 }
 447         }
 448
 449         I915_WRITE_HEAD(engine, I915_READ_TAIL(engine));
 450
 451         I915_WRITE_HEAD(engine, 0);
 452         I915_WRITE_TAIL(engine, 0);
 453
 454         /* The ring must be empty before it is disabled */
 455         I915_WRITE_CTL(engine, 0);
 456
 457         return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
 458 }
 459
 460 static int init_ring_common(struct intel_engine_cs *engine)
 461 {
 462         struct drm_i915_private *dev_priv = engine->i915;
 463         struct intel_ring *ring = engine->buffer;
 464         int ret = 0;
 465
 466         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 467
 468         if (!stop_ring(engine)) {
 469                 /* G45 ring initialization often fails to reset head to zero */
 470                 DRM_DEBUG_DRIVER("%s head not reset to zero "
 471                                 "ctl %08x head %08x tail %08x start %08x\n",
 472                                 engine->name,
 473                                 I915_READ_CTL(engine),
 474                                 I915_READ_HEAD(engine),
 475                                 I915_READ_TAIL(engine),
 476                                 I915_READ_START(engine));
 477
 478                 if (!stop_ring(engine)) {
 479                         DRM_ERROR("failed to set %s head to zero "
 480                                   "ctl %08x head %08x tail %08x start %08x\n",
 481                                   engine->name,
 482                                   I915_READ_CTL(engine),
 483                                   I915_READ_HEAD(engine),
 484                                   I915_READ_TAIL(engine),
 485                                   I915_READ_START(engine));
 486                         ret = -EIO;
 487                         goto out;
 488                 }
 489         }
 490
 491         if (HWS_NEEDS_PHYSICAL(dev_priv))
 492                 ring_setup_phys_status_page(engine);
 493         else
 494                 intel_ring_setup_status_page(engine);
 495
 496         intel_engine_reset_breadcrumbs(engine);
 497
 498         /* Enforce ordering by reading HEAD register back */
 499         I915_READ_HEAD(engine);
 500
 501         /* Initialize the ring. This must happen _after_ we've cleared the ring
 502          * registers with the above sequence (the readback of the HEAD registers
 503          * also enforces ordering), otherwise the hw might lose the new ring
 504          * register values. */
 505         I915_WRITE_START(engine, i915_ggtt_offset(ring->vma));
 506
 507         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 508         if (I915_READ_HEAD(engine))
 509                 DRM_DEBUG_DRIVER("%s initialization failed [head=%08x], fudging\n",
 510                                  engine->name, I915_READ_HEAD(engine));
 511
 512         /* Check that the ring offsets point within the ring! */
 513         GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head));
 514         GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail));
 515
 516         intel_ring_update_space(ring);
 517         I915_WRITE_HEAD(engine, ring->head);
 518         I915_WRITE_TAIL(engine, ring->tail);
 519         (void)I915_READ_TAIL(engine);
 520
 521         I915_WRITE_CTL(engine, RING_CTL_SIZE(ring->size) | RING_VALID);
 522
 523         /* If the head is still not zero, the ring is dead */
 524         if (intel_wait_for_register(dev_priv, RING_CTL(engine->mmio_base),
 525                                     RING_VALID, RING_VALID,
 526                                     50)) {
 527                 DRM_ERROR("%s initialization failed "
 528                           "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n",
 529                           engine->name,
 530                           I915_READ_CTL(engine),
 531                           I915_READ_CTL(engine) & RING_VALID,
 532                           I915_READ_HEAD(engine), ring->head,
 533                           I915_READ_TAIL(engine), ring->tail,
 534                           I915_READ_START(engine),
 535                           i915_ggtt_offset(ring->vma));
 536                 ret = -EIO;
 537                 goto out;
 538         }
 539
 540         if (INTEL_GEN(dev_priv) > 2)
 541                 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
 542
 543         /* Papering over lost _interrupts_ immediately following the restart */
 544         intel_engine_wakeup(engine);
 545 out:
 546         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 547
 548         return ret;
 549 }
 550
 551 static struct i915_request *reset_prepare(struct intel_engine_cs *engine)
 552 {
 553         intel_engine_stop_cs(engine);
 554
 555         if (engine->irq_seqno_barrier)
 556                 engine->irq_seqno_barrier(engine);
 557
 558         return i915_gem_find_active_request(engine);
 559 }
 560
 561 static void skip_request(struct i915_request *rq)
 562 {
 563         void *vaddr = rq->ring->vaddr;
 564         u32 head;
 565
 566         head = rq->infix;
 567         if (rq->postfix < head) {
 568                 memset32(vaddr + head, MI_NOOP,
 569                          (rq->ring->size - head) / sizeof(u32));
 570                 head = 0;
 571         }
 572         memset32(vaddr + head, MI_NOOP, (rq->postfix - head) / sizeof(u32));
 573 }
 574
 575 static void reset_ring(struct intel_engine_cs *engine, struct i915_request *rq)
 576 {
 577         GEM_TRACE("%s seqno=%x\n", engine->name, rq ? rq->global_seqno : 0);
 578
 579         /*
 580          * Try to restore the logical GPU state to match the continuation
 581          * of the request queue. If we skip the context/PD restore, then
 582          * the next request may try to execute assuming that its context
 583          * is valid and loaded on the GPU and so may try to access invalid
 584          * memory, prompting repeated GPU hangs.
 585          *
 586          * If the request was guilty, we still restore the logical state
 587          * in case the next request requires it (e.g. the aliasing ppgtt),
 588          * but skip over the hung batch.
 589          *
 590          * If the request was innocent, we try to replay the request with
 591          * the restored context.
 592          */
 593         if (rq) {
 594                 /* If the rq hung, jump to its breadcrumb and skip the batch */
 595                 rq->ring->head = intel_ring_wrap(rq->ring, rq->head);
 596                 if (rq->fence.error == -EIO)
 597                         skip_request(rq);
 598         }
 599 }
 600
 601 static void reset_finish(struct intel_engine_cs *engine)
 602 {
 603 }
 604
 605 static int intel_rcs_ctx_init(struct i915_request *rq)
 606 {
 607         int ret;
 608
 609         ret = intel_ctx_workarounds_emit(rq);
 610         if (ret != 0)
 611                 return ret;
 612
 613         ret = i915_gem_render_state_emit(rq);
 614         if (ret)
 615                 return ret;
 616
 617         return 0;
 618 }
 619
 620 static int init_render_ring(struct intel_engine_cs *engine)
 621 {
 622         struct drm_i915_private *dev_priv = engine->i915;
 623         int ret = init_ring_common(engine);
 624         if (ret)
 625                 return ret;
 626
 627         intel_whitelist_workarounds_apply(engine);
 628
 629         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
 630         if (IS_GEN(dev_priv, 4, 6))
 631                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 632
 633         /* We need to disable the AsyncFlip performance optimisations in order
 634          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 635          * programmed to '1' on all products.
 636          *
 637          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
 638          */
 639         if (IS_GEN(dev_priv, 6, 7))
 640                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 641
 642         /* Required for the hardware to program scanline values for waiting */
 643         /* WaEnableFlushTlbInvalidationMode:snb */
 644         if (IS_GEN6(dev_priv))
 645                 I915_WRITE(GFX_MODE,
 646                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
 647
 648         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
 649         if (IS_GEN7(dev_priv))
 650                 I915_WRITE(GFX_MODE_GEN7,
 651                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
 652                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 653
 654         if (IS_GEN6(dev_priv)) {
 655                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 656                  * "If this bit is set, STCunit will have LRA as replacement
 657                  *  policy. [...] This bit must be reset.  LRA replacement
 658                  *  policy is not supported."
 659                  */
 660                 I915_WRITE(CACHE_MODE_0,
 661                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 662         }
 663
 664         if (IS_GEN(dev_priv, 6, 7))
 665                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 666
 667         if (INTEL_GEN(dev_priv) >= 6)
 668                 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
 669
 670         return 0;
 671 }
 672
 673 static u32 *gen6_signal(struct i915_request *rq, u32 *cs)
 674 {
 675         struct drm_i915_private *dev_priv = rq->i915;
 676         struct intel_engine_cs *engine;
 677         enum intel_engine_id id;
 678         int num_rings = 0;
 679
 680         for_each_engine(engine, dev_priv, id) {
 681                 i915_reg_t mbox_reg;
 682
 683                 if (!(BIT(engine->hw_id) & GEN6_SEMAPHORES_MASK))
 684                         continue;
 685
 686                 mbox_reg = rq->engine->semaphore.mbox.signal[engine->hw_id];
 687                 if (i915_mmio_reg_valid(mbox_reg)) {
 688                         *cs++ = MI_LOAD_REGISTER_IMM(1);
 689                         *cs++ = i915_mmio_reg_offset(mbox_reg);
 690                         *cs++ = rq->global_seqno;
 691                         num_rings++;
 692                 }
 693         }
 694         if (num_rings & 1)
 695                 *cs++ = MI_NOOP;
 696
 697         return cs;
 698 }
 699
 700 static void cancel_requests(struct intel_engine_cs *engine)
 701 {
 702         struct i915_request *request;
 703         unsigned long flags;
 704
 705         spin_lock_irqsave(&engine->timeline.lock, flags);
 706
 707         /* Mark all submitted requests as skipped. */
 708         list_for_each_entry(request, &engine->timeline.requests, link) {
 709                 GEM_BUG_ON(!request->global_seqno);
 710                 if (!i915_request_completed(request))
 711                         dma_fence_set_error(&request->fence, -EIO);
 712         }
 713         /* Remaining _unready_ requests will be nop'ed when submitted */
 714
 715         spin_unlock_irqrestore(&engine->timeline.lock, flags);
 716 }
 717
 718 static void i9xx_submit_request(struct i915_request *request)
 719 {
 720         struct drm_i915_private *dev_priv = request->i915;
 721
 722         i915_request_submit(request);
 723
 724         I915_WRITE_TAIL(request->engine,
 725                         intel_ring_set_tail(request->ring, request->tail));
 726 }
 727
 728 static void i9xx_emit_breadcrumb(struct i915_request *rq, u32 *cs)
 729 {
 730         *cs++ = MI_STORE_DWORD_INDEX;
 731         *cs++ = I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT;
 732         *cs++ = rq->global_seqno;
 733         *cs++ = MI_USER_INTERRUPT;
 734
 735         rq->tail = intel_ring_offset(rq, cs);
 736         assert_ring_tail_valid(rq->ring, rq->tail);
 737 }
 738
 739 static const int i9xx_emit_breadcrumb_sz = 4;
 740
 741 static void gen6_sema_emit_breadcrumb(struct i915_request *rq, u32 *cs)
 742 {
 743         return i9xx_emit_breadcrumb(rq, rq->engine->semaphore.signal(rq, cs));
 744 }
 745
 746 static int
 747 gen6_ring_sync_to(struct i915_request *rq, struct i915_request *signal)
 748 {
 749         u32 dw1 = MI_SEMAPHORE_MBOX |
 750                   MI_SEMAPHORE_COMPARE |
 751                   MI_SEMAPHORE_REGISTER;
 752         u32 wait_mbox = signal->engine->semaphore.mbox.wait[rq->engine->hw_id];
 753         u32 *cs;
 754
 755         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
 756
 757         cs = intel_ring_begin(rq, 4);
 758         if (IS_ERR(cs))
 759                 return PTR_ERR(cs);
 760
 761         *cs++ = dw1 | wait_mbox;
 762         /* Throughout all of the GEM code, seqno passed implies our current
 763          * seqno is >= the last seqno executed. However for hardware the
 764          * comparison is strictly greater than.
 765          */
 766         *cs++ = signal->global_seqno - 1;
 767         *cs++ = 0;
 768         *cs++ = MI_NOOP;
 769         intel_ring_advance(rq, cs);
 770
 771         return 0;
 772 }
 773
 774 static void
 775 gen5_seqno_barrier(struct intel_engine_cs *engine)
 776 {
 777         /* MI_STORE are internally buffered by the GPU and not flushed
 778          * either by MI_FLUSH or SyncFlush or any other combination of
 779          * MI commands.
 780          *
 781          * "Only the submission of the store operation is guaranteed.
 782          * The write result will be complete (coherent) some time later
 783          * (this is practically a finite period but there is no guaranteed
 784          * latency)."
 785          *
 786          * Empirically, we observe that we need a delay of at least 75us to
 787          * be sure that the seqno write is visible by the CPU.
 788          */
 789         usleep_range(125, 250);
 790 }
 791
 792 static void
 793 gen6_seqno_barrier(struct intel_engine_cs *engine)
 794 {
 795         struct drm_i915_private *dev_priv = engine->i915;
 796
 797         /* Workaround to force correct ordering between irq and seqno writes on
 798          * ivb (and maybe also on snb) by reading from a CS register (like
 799          * ACTHD) before reading the status page.
 800          *
 801          * Note that this effectively stalls the read by the time it takes to
 802          * do a memory transaction, which more or less ensures that the write
 803          * from the GPU has sufficient time to invalidate the CPU cacheline.
 804          * Alternatively we could delay the interrupt from the CS ring to give
 805          * the write time to land, but that would incur a delay after every
 806          * batch i.e. much more frequent than a delay when waiting for the
 807          * interrupt (with the same net latency).
 808          *
 809          * Also note that to prevent whole machine hangs on gen7, we have to
 810          * take the spinlock to guard against concurrent cacheline access.
 811          */
 812         spin_lock_irq(&dev_priv->uncore.lock);
 813         POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
 814         spin_unlock_irq(&dev_priv->uncore.lock);
 815 }
 816
 817 static void
 818 gen5_irq_enable(struct intel_engine_cs *engine)
 819 {
 820         gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask);
 821 }
 822
 823 static void
 824 gen5_irq_disable(struct intel_engine_cs *engine)
 825 {
 826         gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask);
 827 }
 828
 829 static void
 830 i9xx_irq_enable(struct intel_engine_cs *engine)
 831 {
 832         struct drm_i915_private *dev_priv = engine->i915;
 833
 834         dev_priv->irq_mask &= ~engine->irq_enable_mask;
 835         I915_WRITE(IMR, dev_priv->irq_mask);
 836         POSTING_READ_FW(RING_IMR(engine->mmio_base));
 837 }
 838
 839 static void
 840 i9xx_irq_disable(struct intel_engine_cs *engine)
 841 {
 842         struct drm_i915_private *dev_priv = engine->i915;
 843
 844         dev_priv->irq_mask |= engine->irq_enable_mask;
 845         I915_WRITE(IMR, dev_priv->irq_mask);
 846 }
 847
 848 static void
 849 i8xx_irq_enable(struct intel_engine_cs *engine)
 850 {
 851         struct drm_i915_private *dev_priv = engine->i915;
 852
 853         dev_priv->irq_mask &= ~engine->irq_enable_mask;
 854         I915_WRITE16(IMR, dev_priv->irq_mask);
 855         POSTING_READ16(RING_IMR(engine->mmio_base));
 856 }
 857
 858 static void
 859 i8xx_irq_disable(struct intel_engine_cs *engine)
 860 {
 861         struct drm_i915_private *dev_priv = engine->i915;
 862
 863         dev_priv->irq_mask |= engine->irq_enable_mask;
 864         I915_WRITE16(IMR, dev_priv->irq_mask);
 865 }
 866
 867 static int
 868 bsd_ring_flush(struct i915_request *rq, u32 mode)
 869 {
 870         u32 *cs;
 871
 872         cs = intel_ring_begin(rq, 2);
 873         if (IS_ERR(cs))
 874                 return PTR_ERR(cs);
 875
 876         *cs++ = MI_FLUSH;
 877         *cs++ = MI_NOOP;
 878         intel_ring_advance(rq, cs);
 879         return 0;
 880 }
 881
 882 static void
 883 gen6_irq_enable(struct intel_engine_cs *engine)
 884 {
 885         struct drm_i915_private *dev_priv = engine->i915;
 886
 887         I915_WRITE_IMR(engine,
 888                        ~(engine->irq_enable_mask |
 889                          engine->irq_keep_mask));
 890         gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
 891 }
 892
 893 static void
 894 gen6_irq_disable(struct intel_engine_cs *engine)
 895 {
 896         struct drm_i915_private *dev_priv = engine->i915;
 897
 898         I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
 899         gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
 900 }
 901
 902 static void
 903 hsw_vebox_irq_enable(struct intel_engine_cs *engine)
 904 {
 905         struct drm_i915_private *dev_priv = engine->i915;
 906
 907         I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
 908         gen6_unmask_pm_irq(dev_priv, engine->irq_enable_mask);
 909 }
 910
 911 static void
 912 hsw_vebox_irq_disable(struct intel_engine_cs *engine)
 913 {
 914         struct drm_i915_private *dev_priv = engine->i915;
 915
 916         I915_WRITE_IMR(engine, ~0);
 917         gen6_mask_pm_irq(dev_priv, engine->irq_enable_mask);
 918 }
 919
 920 static int
 921 i965_emit_bb_start(struct i915_request *rq,
 922                    u64 offset, u32 length,
 923                    unsigned int dispatch_flags)
 924 {
 925         u32 *cs;
 926
 927         cs = intel_ring_begin(rq, 2);
 928         if (IS_ERR(cs))
 929                 return PTR_ERR(cs);
 930
 931         *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | (dispatch_flags &
 932                 I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965);
 933         *cs++ = offset;
 934         intel_ring_advance(rq, cs);
 935
 936         return 0;
 937 }
 938
 939 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
 940 #define I830_BATCH_LIMIT (256*1024)
 941 #define I830_TLB_ENTRIES (2)
 942 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
 943 static int
 944 i830_emit_bb_start(struct i915_request *rq,
 945                    u64 offset, u32 len,
 946                    unsigned int dispatch_flags)
 947 {
 948         u32 *cs, cs_offset = i915_ggtt_offset(rq->engine->scratch);
 949
 950         cs = intel_ring_begin(rq, 6);
 951         if (IS_ERR(cs))
 952                 return PTR_ERR(cs);
 953
 954         /* Evict the invalid PTE TLBs */
 955         *cs++ = COLOR_BLT_CMD | BLT_WRITE_RGBA;
 956         *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096;
 957         *cs++ = I830_TLB_ENTRIES << 16 | 4; /* load each page */
 958         *cs++ = cs_offset;
 959         *cs++ = 0xdeadbeef;
 960         *cs++ = MI_NOOP;
 961         intel_ring_advance(rq, cs);
 962
 963         if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
 964                 if (len > I830_BATCH_LIMIT)
 965                         return -ENOSPC;
 966
 967                 cs = intel_ring_begin(rq, 6 + 2);
 968                 if (IS_ERR(cs))
 969                         return PTR_ERR(cs);
 970
 971                 /* Blit the batch (which has now all relocs applied) to the
 972                  * stable batch scratch bo area (so that the CS never
 973                  * stumbles over its tlb invalidation bug) ...
 974                  */
 975                 *cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA;
 976                 *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096;
 977                 *cs++ = DIV_ROUND_UP(len, 4096) << 16 | 4096;
 978                 *cs++ = cs_offset;
 979                 *cs++ = 4096;
 980                 *cs++ = offset;
 981
 982                 *cs++ = MI_FLUSH;
 983                 *cs++ = MI_NOOP;
 984                 intel_ring_advance(rq, cs);
 985
 986                 /* ... and execute it. */
 987                 offset = cs_offset;
 988         }
 989
 990         cs = intel_ring_begin(rq, 2);
 991         if (IS_ERR(cs))
 992                 return PTR_ERR(cs);
 993
 994         *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
 995         *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 :
 996                 MI_BATCH_NON_SECURE);
 997         intel_ring_advance(rq, cs);
 998
 999         return 0;
1000 }
1001
1002 static int
1003 i915_emit_bb_start(struct i915_request *rq,
1004                    u64 offset, u32 len,
1005                    unsigned int dispatch_flags)
1006 {
1007         u32 *cs;
1008
1009         cs = intel_ring_begin(rq, 2);
1010         if (IS_ERR(cs))
1011                 return PTR_ERR(cs);
1012
1013         *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
1014         *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 :
1015                 MI_BATCH_NON_SECURE);
1016         intel_ring_advance(rq, cs);
1017
1018         return 0;
1019 }
1020
1021 int intel_ring_pin(struct intel_ring *ring)
1022 {
1023         struct i915_vma *vma = ring->vma;
1024         enum i915_map_type map =
1025                 HAS_LLC(vma->vm->i915) ? I915_MAP_WB : I915_MAP_WC;
1026         unsigned int flags;
1027         void *addr;
1028         int ret;
1029
1030         GEM_BUG_ON(ring->vaddr);
1031
1032         flags = PIN_GLOBAL;
1033
1034         /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
1035         flags |= PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma);
1036
1037         if (vma->obj->stolen)
1038                 flags |= PIN_MAPPABLE;
1039         else
1040                 flags |= PIN_HIGH;
1041
1042         if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
1043                 if (flags & PIN_MAPPABLE || map == I915_MAP_WC)
1044                         ret = i915_gem_object_set_to_gtt_domain(vma->obj, true);
1045                 else
1046                         ret = i915_gem_object_set_to_cpu_domain(vma->obj, true);
1047                 if (unlikely(ret))
1048                         return ret;
1049         }
1050
1051         ret = i915_vma_pin(vma, 0, 0, flags);
1052         if (unlikely(ret))
1053                 return ret;
1054
1055         if (i915_vma_is_map_and_fenceable(vma))
1056                 addr = (void __force *)i915_vma_pin_iomap(vma);
1057         else
1058                 addr = i915_gem_object_pin_map(vma->obj, map);
1059         if (IS_ERR(addr))
1060                 goto err;
1061
1062         vma->obj->pin_global++;
1063
1064         ring->vaddr = addr;
1065         return 0;
1066
1067 err:
1068         i915_vma_unpin(vma);
1069         return PTR_ERR(addr);
1070 }
1071
1072 void intel_ring_reset(struct intel_ring *ring, u32 tail)
1073 {
1074         GEM_BUG_ON(!intel_ring_offset_valid(ring, tail));
1075
1076         ring->tail = tail;
1077         ring->head = tail;
1078         ring->emit = tail;
1079         intel_ring_update_space(ring);
1080 }
1081
1082 void intel_ring_unpin(struct intel_ring *ring)
1083 {
1084         GEM_BUG_ON(!ring->vma);
1085         GEM_BUG_ON(!ring->vaddr);
1086
1087         /* Discard any unused bytes beyond that submitted to hw. */
1088         intel_ring_reset(ring, ring->tail);
1089
1090         if (i915_vma_is_map_and_fenceable(ring->vma))
1091                 i915_vma_unpin_iomap(ring->vma);
1092         else
1093                 i915_gem_object_unpin_map(ring->vma->obj);
1094         ring->vaddr = NULL;
1095
1096         ring->vma->obj->pin_global--;
1097         i915_vma_unpin(ring->vma);
1098 }
1099
1100 static struct i915_vma *
1101 intel_ring_create_vma(struct drm_i915_private *dev_priv, int size)
1102 {
1103         struct i915_address_space *vm = &dev_priv->ggtt.vm;
1104         struct drm_i915_gem_object *obj;
1105         struct i915_vma *vma;
1106
1107         obj = i915_gem_object_create_stolen(dev_priv, size);
1108         if (!obj)
1109                 obj = i915_gem_object_create_internal(dev_priv, size);
1110         if (IS_ERR(obj))
1111                 return ERR_CAST(obj);
1112
1113         /*
1114          * Mark ring buffers as read-only from GPU side (so no stray overwrites)
1115          * if supported by the platform's GGTT.
1116          */
1117         if (vm->has_read_only)
1118                 i915_gem_object_set_readonly(obj);
1119
1120         vma = i915_vma_instance(obj, vm, NULL);
1121         if (IS_ERR(vma))
1122                 goto err;
1123
1124         return vma;
1125
1126 err:
1127         i915_gem_object_put(obj);
1128         return vma;
1129 }
1130
1131 struct intel_ring *
1132 intel_engine_create_ring(struct intel_engine_cs *engine,
1133                          struct i915_timeline *timeline,
1134                          int size)
1135 {
1136         struct intel_ring *ring;
1137         struct i915_vma *vma;
1138
1139         GEM_BUG_ON(!is_power_of_2(size));
1140         GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES);
1141         GEM_BUG_ON(timeline == &engine->timeline);
1142         lockdep_assert_held(&engine->i915->drm.struct_mutex);
1143
1144         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
1145         if (!ring)
1146                 return ERR_PTR(-ENOMEM);
1147
1148         INIT_LIST_HEAD(&ring->request_list);
1149         ring->timeline = i915_timeline_get(timeline);
1150
1151         ring->size = size;
1152         /* Workaround an erratum on the i830 which causes a hang if
1153          * the TAIL pointer points to within the last 2 cachelines
1154          * of the buffer.
1155          */
1156         ring->effective_size = size;
1157         if (IS_I830(engine->i915) || IS_I845G(engine->i915))
1158                 ring->effective_size -= 2 * CACHELINE_BYTES;
1159
1160         intel_ring_update_space(ring);
1161
1162         vma = intel_ring_create_vma(engine->i915, size);
1163         if (IS_ERR(vma)) {
1164                 kfree(ring);
1165                 return ERR_CAST(vma);
1166         }
1167         ring->vma = vma;
1168
1169         return ring;
1170 }
1171
1172 void
1173 intel_ring_free(struct intel_ring *ring)
1174 {
1175         struct drm_i915_gem_object *obj = ring->vma->obj;
1176
1177         i915_vma_close(ring->vma);
1178         __i915_gem_object_release_unless_active(obj);
1179
1180         i915_timeline_put(ring->timeline);
1181         kfree(ring);
1182 }
1183
1184 static void intel_ring_context_destroy(struct intel_context *ce)
1185 {
1186         GEM_BUG_ON(ce->pin_count);
1187
1188         if (!ce->state)
1189                 return;
1190
1191         GEM_BUG_ON(i915_gem_object_is_active(ce->state->obj));
1192         i915_gem_object_put(ce->state->obj);
1193 }
1194
1195 static int __context_pin_ppgtt(struct i915_gem_context *ctx)
1196 {
1197         struct i915_hw_ppgtt *ppgtt;
1198         int err = 0;
1199
1200         ppgtt = ctx->ppgtt ?: ctx->i915->mm.aliasing_ppgtt;
1201         if (ppgtt)
1202                 err = gen6_ppgtt_pin(ppgtt);
1203
1204         return err;
1205 }
1206
1207 static void __context_unpin_ppgtt(struct i915_gem_context *ctx)
1208 {
1209         struct i915_hw_ppgtt *ppgtt;
1210
1211         ppgtt = ctx->ppgtt ?: ctx->i915->mm.aliasing_ppgtt;
1212         if (ppgtt)
1213                 gen6_ppgtt_unpin(ppgtt);
1214 }
1215
1216 static int __context_pin(struct intel_context *ce)
1217 {
1218         struct i915_vma *vma;
1219         int err;
1220
1221         vma = ce->state;
1222         if (!vma)
1223                 return 0;
1224
1225         /*
1226          * Clear this page out of any CPU caches for coherent swap-in/out.
1227          * We only want to do this on the first bind so that we do not stall
1228          * on an active context (which by nature is already on the GPU).
1229          */
1230         if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
1231                 err = i915_gem_object_set_to_gtt_domain(vma->obj, true);
1232                 if (err)
1233                         return err;
1234         }
1235
1236         err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
1237         if (err)
1238                 return err;
1239
1240         /*
1241          * And mark is as a globally pinned object to let the shrinker know
1242          * it cannot reclaim the object until we release it.
1243          */
1244         vma->obj->pin_global++;
1245
1246         return 0;
1247 }
1248
1249 static void __context_unpin(struct intel_context *ce)
1250 {
1251         struct i915_vma *vma;
1252
1253         vma = ce->state;
1254         if (!vma)
1255                 return;
1256
1257         vma->obj->pin_global--;
1258         i915_vma_unpin(vma);
1259 }
1260
1261 static void intel_ring_context_unpin(struct intel_context *ce)
1262 {
1263         __context_unpin_ppgtt(ce->gem_context);
1264         __context_unpin(ce);
1265
1266         i915_gem_context_put(ce->gem_context);
1267 }
1268
1269 static struct i915_vma *
1270 alloc_context_vma(struct intel_engine_cs *engine)
1271 {
1272         struct drm_i915_private *i915 = engine->i915;
1273         struct drm_i915_gem_object *obj;
1274         struct i915_vma *vma;
1275         int err;
1276
1277         obj = i915_gem_object_create(i915, engine->context_size);
1278         if (IS_ERR(obj))
1279                 return ERR_CAST(obj);
1280
1281         if (engine->default_state) {
1282                 void *defaults, *vaddr;
1283
1284                 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
1285                 if (IS_ERR(vaddr)) {
1286                         err = PTR_ERR(vaddr);
1287                         goto err_obj;
1288                 }
1289
1290                 defaults = i915_gem_object_pin_map(engine->default_state,
1291                                                    I915_MAP_WB);
1292                 if (IS_ERR(defaults)) {
1293                         err = PTR_ERR(defaults);
1294                         goto err_map;
1295                 }
1296
1297                 memcpy(vaddr, defaults, engine->context_size);
1298
1299                 i915_gem_object_unpin_map(engine->default_state);
1300                 i915_gem_object_unpin_map(obj);
1301         }
1302
1303         /*
1304          * Try to make the context utilize L3 as well as LLC.
1305          *
1306          * On VLV we don't have L3 controls in the PTEs so we
1307          * shouldn't touch the cache level, especially as that
1308          * would make the object snooped which might have a
1309          * negative performance impact.
1310          *
1311          * Snooping is required on non-llc platforms in execlist
1312          * mode, but since all GGTT accesses use PAT entry 0 we
1313          * get snooping anyway regardless of cache_level.
1314          *
1315          * This is only applicable for Ivy Bridge devices since
1316          * later platforms don't have L3 control bits in the PTE.
1317          */
1318         if (IS_IVYBRIDGE(i915)) {
1319                 /* Ignore any error, regard it as a simple optimisation */
1320                 i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
1321         }
1322
1323         vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
1324         if (IS_ERR(vma)) {
1325                 err = PTR_ERR(vma);
1326                 goto err_obj;
1327         }
1328
1329         return vma;
1330
1331 err_map:
1332         i915_gem_object_unpin_map(obj);
1333 err_obj:
1334         i915_gem_object_put(obj);
1335         return ERR_PTR(err);
1336 }
1337
1338 static struct intel_context *
1339 __ring_context_pin(struct intel_engine_cs *engine,
1340                    struct i915_gem_context *ctx,
1341                    struct intel_context *ce)
1342 {
1343         int err;
1344
1345         if (!ce->state && engine->context_size) {
1346                 struct i915_vma *vma;
1347
1348                 vma = alloc_context_vma(engine);
1349                 if (IS_ERR(vma)) {
1350                         err = PTR_ERR(vma);
1351                         goto err;
1352                 }
1353
1354                 ce->state = vma;
1355         }
1356
1357         err = __context_pin(ce);
1358         if (err)
1359                 goto err;
1360
1361         err = __context_pin_ppgtt(ce->gem_context);
1362         if (err)
1363                 goto err_unpin;
1364
1365         i915_gem_context_get(ctx);
1366
1367         /* One ringbuffer to rule them all */
1368         GEM_BUG_ON(!engine->buffer);
1369         ce->ring = engine->buffer;
1370
1371         return ce;
1372
1373 err_unpin:
1374         __context_unpin(ce);
1375 err:
1376         ce->pin_count = 0;
1377         return ERR_PTR(err);
1378 }
1379
1380 static const struct intel_context_ops ring_context_ops = {
1381         .unpin = intel_ring_context_unpin,
1382         .destroy = intel_ring_context_destroy,
1383 };
1384
1385 static struct intel_context *
1386 intel_ring_context_pin(struct intel_engine_cs *engine,
1387                        struct i915_gem_context *ctx)
1388 {
1389         struct intel_context *ce = to_intel_context(ctx, engine);
1390
1391         lockdep_assert_held(&ctx->i915->drm.struct_mutex);
1392
1393         if (likely(ce->pin_count++))
1394                 return ce;
1395         GEM_BUG_ON(!ce->pin_count); /* no overflow please! */
1396
1397         ce->ops = &ring_context_ops;
1398
1399         return __ring_context_pin(engine, ctx, ce);
1400 }
1401
1402 static int intel_init_ring_buffer(struct intel_engine_cs *engine)
1403 {
1404         struct i915_timeline *timeline;
1405         struct intel_ring *ring;
1406         unsigned int size;
1407         int err;
1408
1409         intel_engine_setup_common(engine);
1410
1411         timeline = i915_timeline_create(engine->i915, engine->name);
1412         if (IS_ERR(timeline)) {
1413                 err = PTR_ERR(timeline);
1414                 goto err;
1415         }
1416
1417         ring = intel_engine_create_ring(engine, timeline, 32 * PAGE_SIZE);
1418         i915_timeline_put(timeline);
1419         if (IS_ERR(ring)) {
1420                 err = PTR_ERR(ring);
1421                 goto err;
1422         }
1423
1424         err = intel_ring_pin(ring);
1425         if (err)
1426                 goto err_ring;
1427
1428         GEM_BUG_ON(engine->buffer);
1429         engine->buffer = ring;
1430
1431         size = PAGE_SIZE;
1432         if (HAS_BROKEN_CS_TLB(engine->i915))
1433                 size = I830_WA_SIZE;
1434         err = intel_engine_create_scratch(engine, size);
1435         if (err)
1436                 goto err_unpin;
1437
1438         err = intel_engine_init_common(engine);
1439         if (err)
1440                 goto err_scratch;
1441
1442         return 0;
1443
1444 err_scratch:
1445         intel_engine_cleanup_scratch(engine);
1446 err_unpin:
1447         intel_ring_unpin(ring);
1448 err_ring:
1449         intel_ring_free(ring);
1450 err:
1451         intel_engine_cleanup_common(engine);
1452         return err;
1453 }
1454
1455 void intel_engine_cleanup(struct intel_engine_cs *engine)
1456 {
1457         struct drm_i915_private *dev_priv = engine->i915;
1458
1459         WARN_ON(INTEL_GEN(dev_priv) > 2 &&
1460                 (I915_READ_MODE(engine) & MODE_IDLE) == 0);
1461
1462         intel_ring_unpin(engine->buffer);
1463         intel_ring_free(engine->buffer);
1464
1465         if (engine->cleanup)
1466                 engine->cleanup(engine);
1467
1468         intel_engine_cleanup_common(engine);
1469
1470         dev_priv->engine[engine->id] = NULL;
1471         kfree(engine);
1472 }
1473
1474 void intel_legacy_submission_resume(struct drm_i915_private *dev_priv)
1475 {
1476         struct intel_engine_cs *engine;
1477         enum intel_engine_id id;
1478
1479         /* Restart from the beginning of the rings for convenience */
1480         for_each_engine(engine, dev_priv, id)
1481                 intel_ring_reset(engine->buffer, 0);
1482 }
1483
1484 static int load_pd_dir(struct i915_request *rq,
1485                        const struct i915_hw_ppgtt *ppgtt)
1486 {
1487         const struct intel_engine_cs * const engine = rq->engine;
1488         u32 *cs;
1489
1490         cs = intel_ring_begin(rq, 6);
1491         if (IS_ERR(cs))
1492                 return PTR_ERR(cs);
1493
1494         *cs++ = MI_LOAD_REGISTER_IMM(1);
1495         *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine));
1496         *cs++ = PP_DIR_DCLV_2G;
1497
1498         *cs++ = MI_LOAD_REGISTER_IMM(1);
1499         *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine));
1500         *cs++ = ppgtt->pd.base.ggtt_offset << 10;
1501
1502         intel_ring_advance(rq, cs);
1503
1504         return 0;
1505 }
1506
1507 static int flush_pd_dir(struct i915_request *rq)
1508 {
1509         const struct intel_engine_cs * const engine = rq->engine;
1510         u32 *cs;
1511
1512         cs = intel_ring_begin(rq, 4);
1513         if (IS_ERR(cs))
1514                 return PTR_ERR(cs);
1515
1516         /* Stall until the page table load is complete */
1517         *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
1518         *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine));
1519         *cs++ = i915_ggtt_offset(engine->scratch);
1520         *cs++ = MI_NOOP;
1521
1522         intel_ring_advance(rq, cs);
1523         return 0;
1524 }
1525
1526 static inline int mi_set_context(struct i915_request *rq, u32 flags)
1527 {
1528         struct drm_i915_private *i915 = rq->i915;
1529         struct intel_engine_cs *engine = rq->engine;
1530         enum intel_engine_id id;
1531         const int num_rings =
1532                 /* Use an extended w/a on gen7 if signalling from other rings */
1533                 (HAS_LEGACY_SEMAPHORES(i915) && IS_GEN7(i915)) ?
1534                 INTEL_INFO(i915)->num_rings - 1 :
1535                 0;
1536         bool force_restore = false;
1537         int len;
1538         u32 *cs;
1539
1540         flags |= MI_MM_SPACE_GTT;
1541         if (IS_HASWELL(i915))
1542                 /* These flags are for resource streamer on HSW+ */
1543                 flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN;
1544         else
1545                 flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN;
1546
1547         len = 4;
1548         if (IS_GEN7(i915))
1549                 len += 2 + (num_rings ? 4*num_rings + 6 : 0);
1550         if (flags & MI_FORCE_RESTORE) {
1551                 GEM_BUG_ON(flags & MI_RESTORE_INHIBIT);
1552                 flags &= ~MI_FORCE_RESTORE;
1553                 force_restore = true;
1554                 len += 2;
1555         }
1556
1557         cs = intel_ring_begin(rq, len);
1558         if (IS_ERR(cs))
1559                 return PTR_ERR(cs);
1560
1561         /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
1562         if (IS_GEN7(i915)) {
1563                 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1564                 if (num_rings) {
1565                         struct intel_engine_cs *signaller;
1566
1567                         *cs++ = MI_LOAD_REGISTER_IMM(num_rings);
1568                         for_each_engine(signaller, i915, id) {
1569                                 if (signaller == engine)
1570                                         continue;
1571
1572                                 *cs++ = i915_mmio_reg_offset(
1573                                            RING_PSMI_CTL(signaller->mmio_base));
1574                                 *cs++ = _MASKED_BIT_ENABLE(
1575                                                 GEN6_PSMI_SLEEP_MSG_DISABLE);
1576                         }
1577                 }
1578         }
1579
1580         if (force_restore) {
1581                 /*
1582                  * The HW doesn't handle being told to restore the current
1583                  * context very well. Quite often it likes goes to go off and
1584                  * sulk, especially when it is meant to be reloading PP_DIR.
1585                  * A very simple fix to force the reload is to simply switch
1586                  * away from the current context and back again.
1587                  *
1588                  * Note that the kernel_context will contain random state
1589                  * following the INHIBIT_RESTORE. We accept this since we
1590                  * never use the kernel_context state; it is merely a
1591                  * placeholder we use to flush other contexts.
1592                  */
1593                 *cs++ = MI_SET_CONTEXT;
1594                 *cs++ = i915_ggtt_offset(to_intel_context(i915->kernel_context,
1595                                                           engine)->state) |
1596                         MI_MM_SPACE_GTT |
1597                         MI_RESTORE_INHIBIT;
1598         }
1599
1600         *cs++ = MI_NOOP;
1601         *cs++ = MI_SET_CONTEXT;
1602         *cs++ = i915_ggtt_offset(rq->hw_context->state) | flags;
1603         /*
1604          * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
1605          * WaMiSetContext_Hang:snb,ivb,vlv
1606          */
1607         *cs++ = MI_NOOP;
1608
1609         if (IS_GEN7(i915)) {
1610                 if (num_rings) {
1611                         struct intel_engine_cs *signaller;
1612                         i915_reg_t last_reg = {}; /* keep gcc quiet */
1613
1614                         *cs++ = MI_LOAD_REGISTER_IMM(num_rings);
1615                         for_each_engine(signaller, i915, id) {
1616                                 if (signaller == engine)
1617                                         continue;
1618
1619                                 last_reg = RING_PSMI_CTL(signaller->mmio_base);
1620                                 *cs++ = i915_mmio_reg_offset(last_reg);
1621                                 *cs++ = _MASKED_BIT_DISABLE(
1622                                                 GEN6_PSMI_SLEEP_MSG_DISABLE);
1623                         }
1624
1625                         /* Insert a delay before the next switch! */
1626                         *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
1627                         *cs++ = i915_mmio_reg_offset(last_reg);
1628                         *cs++ = i915_ggtt_offset(engine->scratch);
1629                         *cs++ = MI_NOOP;
1630                 }
1631                 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1632         }
1633
1634         intel_ring_advance(rq, cs);
1635
1636         return 0;
1637 }
1638
1639 static int remap_l3(struct i915_request *rq, int slice)
1640 {
1641         u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice];
1642         int i;
1643
1644         if (!remap_info)
1645                 return 0;
1646
1647         cs = intel_ring_begin(rq, GEN7_L3LOG_SIZE/4 * 2 + 2);
1648         if (IS_ERR(cs))
1649                 return PTR_ERR(cs);
1650
1651         /*
1652          * Note: We do not worry about the concurrent register cacheline hang
1653          * here because no other code should access these registers other than
1654          * at initialization time.
1655          */
1656         *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4);
1657         for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) {
1658                 *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i));
1659                 *cs++ = remap_info[i];
1660         }
1661         *cs++ = MI_NOOP;
1662         intel_ring_advance(rq, cs);
1663
1664         return 0;
1665 }
1666
1667 static int switch_context(struct i915_request *rq)
1668 {
1669         struct intel_engine_cs *engine = rq->engine;
1670         struct i915_gem_context *ctx = rq->gem_context;
1671         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
1672         unsigned int unwind_mm = 0;
1673         u32 hw_flags = 0;
1674         int ret, i;
1675
1676         lockdep_assert_held(&rq->i915->drm.struct_mutex);
1677         GEM_BUG_ON(HAS_EXECLISTS(rq->i915));
1678
1679         if (ppgtt) {
1680                 ret = load_pd_dir(rq, ppgtt);
1681                 if (ret)
1682                         goto err;
1683
1684                 if (intel_engine_flag(engine) & ppgtt->pd_dirty_rings) {
1685                         unwind_mm = intel_engine_flag(engine);
1686                         ppgtt->pd_dirty_rings &= ~unwind_mm;
1687                         hw_flags = MI_FORCE_RESTORE;
1688                 }
1689         }
1690
1691         if (rq->hw_context->state) {
1692                 GEM_BUG_ON(engine->id != RCS);
1693
1694                 /*
1695                  * The kernel context(s) is treated as pure scratch and is not
1696                  * expected to retain any state (as we sacrifice it during
1697                  * suspend and on resume it may be corrupted). This is ok,
1698                  * as nothing actually executes using the kernel context; it
1699                  * is purely used for flushing user contexts.
1700                  */
1701                 if (i915_gem_context_is_kernel(ctx))
1702                         hw_flags = MI_RESTORE_INHIBIT;
1703
1704                 ret = mi_set_context(rq, hw_flags);
1705                 if (ret)
1706                         goto err_mm;
1707         }
1708
1709         if (ppgtt) {
1710                 ret = engine->emit_flush(rq, EMIT_INVALIDATE);
1711                 if (ret)
1712                         goto err_mm;
1713
1714                 ret = flush_pd_dir(rq);
1715                 if (ret)
1716                         goto err_mm;
1717
1718                 /*
1719                  * Not only do we need a full barrier (post-sync write) after
1720                  * invalidating the TLBs, but we need to wait a little bit
1721                  * longer. Whether this is merely delaying us, or the
1722                  * subsequent flush is a key part of serialising with the
1723                  * post-sync op, this extra pass appears vital before a
1724                  * mm switch!
1725                  */
1726                 ret = engine->emit_flush(rq, EMIT_INVALIDATE);
1727                 if (ret)
1728                         goto err_mm;
1729
1730                 ret = engine->emit_flush(rq, EMIT_FLUSH);
1731                 if (ret)
1732                         goto err_mm;
1733         }
1734
1735         if (ctx->remap_slice) {
1736                 for (i = 0; i < MAX_L3_SLICES; i++) {
1737                         if (!(ctx->remap_slice & BIT(i)))
1738                                 continue;
1739
1740                         ret = remap_l3(rq, i);
1741                         if (ret)
1742                                 goto err_mm;
1743                 }
1744
1745                 ctx->remap_slice = 0;
1746         }
1747
1748         return 0;
1749
1750 err_mm:
1751         if (unwind_mm)
1752                 ppgtt->pd_dirty_rings |= unwind_mm;
1753 err:
1754         return ret;
1755 }
1756
1757 static int ring_request_alloc(struct i915_request *request)
1758 {
1759         int ret;
1760
1761         GEM_BUG_ON(!request->hw_context->pin_count);
1762
1763         /* Flush enough space to reduce the likelihood of waiting after
1764          * we start building the request - in which case we will just
1765          * have to repeat work.
1766          */
1767         request->reserved_space += LEGACY_REQUEST_SIZE;
1768
1769         ret = intel_ring_wait_for_space(request->ring, request->reserved_space);
1770         if (ret)
1771                 return ret;
1772
1773         ret = switch_context(request);
1774         if (ret)
1775                 return ret;
1776
1777         request->reserved_space -= LEGACY_REQUEST_SIZE;
1778         return 0;
1779 }
1780
1781 static noinline int wait_for_space(struct intel_ring *ring, unsigned int bytes)
1782 {
1783         struct i915_request *target;
1784         long timeout;
1785
1786         lockdep_assert_held(&ring->vma->vm->i915->drm.struct_mutex);
1787
1788         if (intel_ring_update_space(ring) >= bytes)
1789                 return 0;
1790
1791         GEM_BUG_ON(list_empty(&ring->request_list));
1792         list_for_each_entry(target, &ring->request_list, ring_link) {
1793                 /* Would completion of this request free enough space? */
1794                 if (bytes <= __intel_ring_space(target->postfix,
1795                                                 ring->emit, ring->size))
1796                         break;
1797         }
1798
1799         if (WARN_ON(&target->ring_link == &ring->request_list))
1800                 return -ENOSPC;
1801
1802         timeout = i915_request_wait(target,
1803                                     I915_WAIT_INTERRUPTIBLE | I915_WAIT_LOCKED,
1804                                     MAX_SCHEDULE_TIMEOUT);
1805         if (timeout < 0)
1806                 return timeout;
1807
1808         i915_request_retire_upto(target);
1809
1810         intel_ring_update_space(ring);
1811         GEM_BUG_ON(ring->space < bytes);
1812         return 0;
1813 }
1814
1815 int intel_ring_wait_for_space(struct intel_ring *ring, unsigned int bytes)
1816 {
1817         GEM_BUG_ON(bytes > ring->effective_size);
1818         if (unlikely(bytes > ring->effective_size - ring->emit))
1819                 bytes += ring->size - ring->emit;
1820
1821         if (unlikely(bytes > ring->space)) {
1822                 int ret = wait_for_space(ring, bytes);
1823                 if (unlikely(ret))
1824                         return ret;
1825         }
1826
1827         GEM_BUG_ON(ring->space < bytes);
1828         return 0;
1829 }
1830
1831 u32 *intel_ring_begin(struct i915_request *rq, unsigned int num_dwords)
1832 {
1833         struct intel_ring *ring = rq->ring;
1834         const unsigned int remain_usable = ring->effective_size - ring->emit;
1835         const unsigned int bytes = num_dwords * sizeof(u32);
1836         unsigned int need_wrap = 0;
1837         unsigned int total_bytes;
1838         u32 *cs;
1839
1840         /* Packets must be qword aligned. */
1841         GEM_BUG_ON(num_dwords & 1);
1842
1843         total_bytes = bytes + rq->reserved_space;
1844         GEM_BUG_ON(total_bytes > ring->effective_size);
1845
1846         if (unlikely(total_bytes > remain_usable)) {
1847                 const int remain_actual = ring->size - ring->emit;
1848
1849                 if (bytes > remain_usable) {
1850                         /*
1851                          * Not enough space for the basic request. So need to
1852                          * flush out the remainder and then wait for
1853                          * base + reserved.
1854                          */
1855                         total_bytes += remain_actual;
1856                         need_wrap = remain_actual | 1;
1857                 } else  {
1858                         /*
1859                          * The base request will fit but the reserved space
1860                          * falls off the end. So we don't need an immediate
1861                          * wrap and only need to effectively wait for the
1862                          * reserved size from the start of ringbuffer.
1863                          */
1864                         total_bytes = rq->reserved_space + remain_actual;
1865                 }
1866         }
1867
1868         if (unlikely(total_bytes > ring->space)) {
1869                 int ret;
1870
1871                 /*
1872                  * Space is reserved in the ringbuffer for finalising the
1873                  * request, as that cannot be allowed to fail. During request
1874                  * finalisation, reserved_space is set to 0 to stop the
1875                  * overallocation and the assumption is that then we never need
1876                  * to wait (which has the risk of failing with EINTR).
1877                  *
1878                  * See also i915_request_alloc() and i915_request_add().
1879                  */
1880                 GEM_BUG_ON(!rq->reserved_space);
1881
1882                 ret = wait_for_space(ring, total_bytes);
1883                 if (unlikely(ret))
1884                         return ERR_PTR(ret);
1885         }
1886
1887         if (unlikely(need_wrap)) {
1888                 need_wrap &= ~1;
1889                 GEM_BUG_ON(need_wrap > ring->space);
1890                 GEM_BUG_ON(ring->emit + need_wrap > ring->size);
1891                 GEM_BUG_ON(!IS_ALIGNED(need_wrap, sizeof(u64)));
1892
1893                 /* Fill the tail with MI_NOOP */
1894                 memset64(ring->vaddr + ring->emit, 0, need_wrap / sizeof(u64));
1895                 ring->space -= need_wrap;
1896                 ring->emit = 0;
1897         }
1898
1899         GEM_BUG_ON(ring->emit > ring->size - bytes);
1900         GEM_BUG_ON(ring->space < bytes);
1901         cs = ring->vaddr + ring->emit;
1902         GEM_DEBUG_EXEC(memset32(cs, POISON_INUSE, bytes / sizeof(*cs)));
1903         ring->emit += bytes;
1904         ring->space -= bytes;
1905
1906         return cs;
1907 }
1908
1909 /* Align the ring tail to a cacheline boundary */
1910 int intel_ring_cacheline_align(struct i915_request *rq)
1911 {
1912         int num_dwords;
1913         void *cs;
1914
1915         num_dwords = (rq->ring->emit & (CACHELINE_BYTES - 1)) / sizeof(u32);
1916         if (num_dwords == 0)
1917                 return 0;
1918
1919         num_dwords = CACHELINE_DWORDS - num_dwords;
1920         GEM_BUG_ON(num_dwords & 1);
1921
1922         cs = intel_ring_begin(rq, num_dwords);
1923         if (IS_ERR(cs))
1924                 return PTR_ERR(cs);
1925
1926         memset64(cs, (u64)MI_NOOP << 32 | MI_NOOP, num_dwords / 2);
1927         intel_ring_advance(rq, cs);
1928
1929         GEM_BUG_ON(rq->ring->emit & (CACHELINE_BYTES - 1));
1930         return 0;
1931 }
1932
1933 static void gen6_bsd_submit_request(struct i915_request *request)
1934 {
1935         struct drm_i915_private *dev_priv = request->i915;
1936
1937         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1938
1939        /* Every tail move must follow the sequence below */
1940
1941         /* Disable notification that the ring is IDLE. The GT
1942          * will then assume that it is busy and bring it out of rc6.
1943          */
1944         I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,
1945                       _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1946
1947         /* Clear the context id. Here be magic! */
1948         I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0);
1949
1950         /* Wait for the ring not to be idle, i.e. for it to wake up. */
1951         if (__intel_wait_for_register_fw(dev_priv,
1952                                          GEN6_BSD_SLEEP_PSMI_CONTROL,
1953                                          GEN6_BSD_SLEEP_INDICATOR,
1954                                          0,
1955                                          1000, 0, NULL))
1956                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1957
1958         /* Now that the ring is fully powered up, update the tail */
1959         i9xx_submit_request(request);
1960
1961         /* Let the ring send IDLE messages to the GT again,
1962          * and so let it sleep to conserve power when idle.
1963          */
1964         I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,
1965                       _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1966
1967         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1968 }
1969
1970 static int mi_flush_dw(struct i915_request *rq, u32 flags)
1971 {
1972         u32 cmd, *cs;
1973
1974         cs = intel_ring_begin(rq, 4);
1975         if (IS_ERR(cs))
1976                 return PTR_ERR(cs);
1977
1978         cmd = MI_FLUSH_DW;
1979
1980         /*
1981          * We always require a command barrier so that subsequent
1982          * commands, such as breadcrumb interrupts, are strictly ordered
1983          * wrt the contents of the write cache being flushed to memory
1984          * (and thus being coherent from the CPU).
1985          */
1986         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1987
1988         /*
1989          * Bspec vol 1c.3 - blitter engine command streamer:
1990          * "If ENABLED, all TLBs will be invalidated once the flush
1991          * operation is complete. This bit is only valid when the
1992          * Post-Sync Operation field is a value of 1h or 3h."
1993          */
1994         cmd |= flags;
1995
1996         *cs++ = cmd;
1997         *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
1998         *cs++ = 0;
1999         *cs++ = MI_NOOP;
2000
2001         intel_ring_advance(rq, cs);
2002
2003         return 0;
2004 }
2005
2006 static int gen6_flush_dw(struct i915_request *rq, u32 mode, u32 invflags)
2007 {
2008         return mi_flush_dw(rq, mode & EMIT_INVALIDATE ? invflags : 0);
2009 }
2010
2011 static int gen6_bsd_ring_flush(struct i915_request *rq, u32 mode)
2012 {
2013         return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB | MI_INVALIDATE_BSD);
2014 }
2015
2016 static int
2017 hsw_emit_bb_start(struct i915_request *rq,
2018                   u64 offset, u32 len,
2019                   unsigned int dispatch_flags)
2020 {
2021         u32 *cs;
2022
2023         cs = intel_ring_begin(rq, 2);
2024         if (IS_ERR(cs))
2025                 return PTR_ERR(cs);
2026
2027         *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ?
2028                 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW);
2029         /* bit0-7 is the length on GEN6+ */
2030         *cs++ = offset;
2031         intel_ring_advance(rq, cs);
2032
2033         return 0;
2034 }
2035
2036 static int
2037 gen6_emit_bb_start(struct i915_request *rq,
2038                    u64 offset, u32 len,
2039                    unsigned int dispatch_flags)
2040 {
2041         u32 *cs;
2042
2043         cs = intel_ring_begin(rq, 2);
2044         if (IS_ERR(cs))
2045                 return PTR_ERR(cs);
2046
2047         *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ?
2048                 0 : MI_BATCH_NON_SECURE_I965);
2049         /* bit0-7 is the length on GEN6+ */
2050         *cs++ = offset;
2051         intel_ring_advance(rq, cs);
2052
2053         return 0;
2054 }
2055
2056 /* Blitter support (SandyBridge+) */
2057
2058 static int gen6_ring_flush(struct i915_request *rq, u32 mode)
2059 {
2060         return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB);
2061 }
2062
2063 static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv,
2064                                        struct intel_engine_cs *engine)
2065 {
2066         int i;
2067
2068         if (!HAS_LEGACY_SEMAPHORES(dev_priv))
2069                 return;
2070
2071         GEM_BUG_ON(INTEL_GEN(dev_priv) < 6);
2072         engine->semaphore.sync_to = gen6_ring_sync_to;
2073         engine->semaphore.signal = gen6_signal;
2074
2075         /*
2076          * The current semaphore is only applied on pre-gen8
2077          * platform.  And there is no VCS2 ring on the pre-gen8
2078          * platform. So the semaphore between RCS and VCS2 is
2079          * initialized as INVALID.
2080          */
2081         for (i = 0; i < GEN6_NUM_SEMAPHORES; i++) {
2082                 static const struct {
2083                         u32 wait_mbox;
2084                         i915_reg_t mbox_reg;
2085                 } sem_data[GEN6_NUM_SEMAPHORES][GEN6_NUM_SEMAPHORES] = {
2086                         [RCS_HW] = {
2087                                 [VCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_RV,  .mbox_reg = GEN6_VRSYNC },
2088                                 [BCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_RB,  .mbox_reg = GEN6_BRSYNC },
2089                                 [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC },
2090                         },
2091                         [VCS_HW] = {
2092                                 [RCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VR,  .mbox_reg = GEN6_RVSYNC },
2093                                 [BCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VB,  .mbox_reg = GEN6_BVSYNC },
2094                                 [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC },
2095                         },
2096                         [BCS_HW] = {
2097                                 [RCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_BR,  .mbox_reg = GEN6_RBSYNC },
2098                                 [VCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_BV,  .mbox_reg = GEN6_VBSYNC },
2099                                 [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC },
2100                         },
2101                         [VECS_HW] = {
2102                                 [RCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC },
2103                                 [VCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC },
2104                                 [BCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC },
2105                         },
2106                 };
2107                 u32 wait_mbox;
2108                 i915_reg_t mbox_reg;
2109
2110                 if (i == engine->hw_id) {
2111                         wait_mbox = MI_SEMAPHORE_SYNC_INVALID;
2112                         mbox_reg = GEN6_NOSYNC;
2113                 } else {
2114                         wait_mbox = sem_data[engine->hw_id][i].wait_mbox;
2115                         mbox_reg = sem_data[engine->hw_id][i].mbox_reg;
2116                 }
2117
2118                 engine->semaphore.mbox.wait[i] = wait_mbox;
2119                 engine->semaphore.mbox.signal[i] = mbox_reg;
2120         }
2121 }
2122
2123 static void intel_ring_init_irq(struct drm_i915_private *dev_priv,
2124                                 struct intel_engine_cs *engine)
2125 {
2126         if (INTEL_GEN(dev_priv) >= 6) {
2127                 engine->irq_enable = gen6_irq_enable;
2128                 engine->irq_disable = gen6_irq_disable;
2129                 engine->irq_seqno_barrier = gen6_seqno_barrier;
2130         } else if (INTEL_GEN(dev_priv) >= 5) {
2131                 engine->irq_enable = gen5_irq_enable;
2132                 engine->irq_disable = gen5_irq_disable;
2133                 engine->irq_seqno_barrier = gen5_seqno_barrier;
2134         } else if (INTEL_GEN(dev_priv) >= 3) {
2135                 engine->irq_enable = i9xx_irq_enable;
2136                 engine->irq_disable = i9xx_irq_disable;
2137         } else {
2138                 engine->irq_enable = i8xx_irq_enable;
2139                 engine->irq_disable = i8xx_irq_disable;
2140         }
2141 }
2142
2143 static void i9xx_set_default_submission(struct intel_engine_cs *engine)
2144 {
2145         engine->submit_request = i9xx_submit_request;
2146         engine->cancel_requests = cancel_requests;
2147
2148         engine->park = NULL;
2149         engine->unpark = NULL;
2150 }
2151
2152 static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine)
2153 {
2154         i9xx_set_default_submission(engine);
2155         engine->submit_request = gen6_bsd_submit_request;
2156 }
2157
2158 static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
2159                                       struct intel_engine_cs *engine)
2160 {
2161         /* gen8+ are only supported with execlists */
2162         GEM_BUG_ON(INTEL_GEN(dev_priv) >= 8);
2163
2164         intel_ring_init_irq(dev_priv, engine);
2165         intel_ring_init_semaphores(dev_priv, engine);
2166
2167         engine->init_hw = init_ring_common;
2168         engine->reset.prepare = reset_prepare;
2169         engine->reset.reset = reset_ring;
2170         engine->reset.finish = reset_finish;
2171
2172         engine->context_pin = intel_ring_context_pin;
2173         engine->request_alloc = ring_request_alloc;
2174
2175         engine->emit_breadcrumb = i9xx_emit_breadcrumb;
2176         engine->emit_breadcrumb_sz = i9xx_emit_breadcrumb_sz;
2177         if (HAS_LEGACY_SEMAPHORES(dev_priv)) {
2178                 int num_rings;
2179
2180                 engine->emit_breadcrumb = gen6_sema_emit_breadcrumb;
2181
2182                 num_rings = INTEL_INFO(dev_priv)->num_rings - 1;
2183                 engine->emit_breadcrumb_sz += num_rings * 3;
2184                 if (num_rings & 1)
2185                         engine->emit_breadcrumb_sz++;
2186         }
2187
2188         engine->set_default_submission = i9xx_set_default_submission;
2189
2190         if (INTEL_GEN(dev_priv) >= 6)
2191                 engine->emit_bb_start = gen6_emit_bb_start;
2192         else if (INTEL_GEN(dev_priv) >= 4)
2193                 engine->emit_bb_start = i965_emit_bb_start;
2194         else if (IS_I830(dev_priv) || IS_I845G(dev_priv))
2195                 engine->emit_bb_start = i830_emit_bb_start;
2196         else
2197                 engine->emit_bb_start = i915_emit_bb_start;
2198 }
2199
2200 int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
2201 {
2202         struct drm_i915_private *dev_priv = engine->i915;
2203         int ret;
2204
2205         intel_ring_default_vfuncs(dev_priv, engine);
2206
2207         if (HAS_L3_DPF(dev_priv))
2208                 engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2209
2210         engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2211
2212         if (INTEL_GEN(dev_priv) >= 6) {
2213                 engine->init_context = intel_rcs_ctx_init;
2214                 engine->emit_flush = gen7_render_ring_flush;
2215                 if (IS_GEN6(dev_priv))
2216                         engine->emit_flush = gen6_render_ring_flush;
2217         } else if (IS_GEN5(dev_priv)) {
2218                 engine->emit_flush = gen4_render_ring_flush;
2219         } else {
2220                 if (INTEL_GEN(dev_priv) < 4)
2221                         engine->emit_flush = gen2_render_ring_flush;
2222                 else
2223                         engine->emit_flush = gen4_render_ring_flush;
2224                 engine->irq_enable_mask = I915_USER_INTERRUPT;
2225         }
2226
2227         if (IS_HASWELL(dev_priv))
2228                 engine->emit_bb_start = hsw_emit_bb_start;
2229
2230         engine->init_hw = init_render_ring;
2231
2232         ret = intel_init_ring_buffer(engine);
2233         if (ret)
2234                 return ret;
2235
2236         return 0;
2237 }
2238
2239 int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine)
2240 {
2241         struct drm_i915_private *dev_priv = engine->i915;
2242
2243         intel_ring_default_vfuncs(dev_priv, engine);
2244
2245         if (INTEL_GEN(dev_priv) >= 6) {
2246                 /* gen6 bsd needs a special wa for tail updates */
2247                 if (IS_GEN6(dev_priv))
2248                         engine->set_default_submission = gen6_bsd_set_default_submission;
2249                 engine->emit_flush = gen6_bsd_ring_flush;
2250                 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2251         } else {
2252                 engine->emit_flush = bsd_ring_flush;
2253                 if (IS_GEN5(dev_priv))
2254                         engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2255                 else
2256                         engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2257         }
2258
2259         return intel_init_ring_buffer(engine);
2260 }
2261
2262 int intel_init_blt_ring_buffer(struct intel_engine_cs *engine)
2263 {
2264         struct drm_i915_private *dev_priv = engine->i915;
2265
2266         intel_ring_default_vfuncs(dev_priv, engine);
2267
2268         engine->emit_flush = gen6_ring_flush;
2269         engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2270
2271         return intel_init_ring_buffer(engine);
2272 }
2273
2274 int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine)
2275 {
2276         struct drm_i915_private *dev_priv = engine->i915;
2277
2278         intel_ring_default_vfuncs(dev_priv, engine);
2279
2280         engine->emit_flush = gen6_ring_flush;
2281         engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2282         engine->irq_enable = hsw_vebox_irq_enable;
2283         engine->irq_disable = hsw_vebox_irq_disable;
2284
2285         return intel_init_ring_buffer(engine);
2286 }