drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/module.h>
  29 #include <linux/pm_runtime.h>
  30
  31 #include <drm/drm_atomic_helper.h>
  32 #include <drm/drm_fourcc.h>
  33 #include <drm/drm_plane_helper.h>
  34
  35 #include "display/intel_atomic.h"
  36 #include "display/intel_atomic_plane.h"
  37 #include "display/intel_bw.h"
  38 #include "display/intel_de.h"
  39 #include "display/intel_display_types.h"
  40 #include "display/intel_fbc.h"
  41 #include "display/intel_sprite.h"
  42 #include "display/skl_universal_plane.h"
  43
  44 #include "gt/intel_llc.h"
  45
  46 #include "i915_drv.h"
  47 #include "i915_fixed.h"
  48 #include "i915_irq.h"
  49 #include "i915_trace.h"
  50 #include "intel_pm.h"
  51 #include "intel_sideband.h"
  52 #include "../../../platform/x86/intel_ips.h"
  53
  54 /* Stores plane specific WM parameters */
  55 struct skl_wm_params {
  56         bool x_tiled, y_tiled;
  57         bool rc_surface;
  58         bool is_planar;
  59         u32 width;
  60         u8 cpp;
  61         u32 plane_pixel_rate;
  62         u32 y_min_scanlines;
  63         u32 plane_bytes_per_line;
  64         uint_fixed_16_16_t plane_blocks_per_line;
  65         uint_fixed_16_16_t y_tile_minimum;
  66         u32 linetime_us;
  67         u32 dbuf_block_size;
  68 };
  69
  70 /* used in computing the new watermarks state */
  71 struct intel_wm_config {
  72         unsigned int num_pipes_active;
  73         bool sprites_enabled;
  74         bool sprites_scaled;
  75 };
  76
  77 static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
  78 {
  79         if (HAS_LLC(dev_priv)) {
  80                 /*
  81                  * WaCompressedResourceDisplayNewHashMode:skl,kbl
  82                  * Display WA #0390: skl,kbl
  83                  *
  84                  * Must match Sampler, Pixel Back End, and Media. See
  85                  * WaCompressedResourceSamplerPbeMediaNewHashMode.
  86                  */
  87                 intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1,
  88                            intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) |
  89                            SKL_DE_COMPRESSED_HASH_MODE);
  90         }
  91
  92         /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
  93         intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1,
  94                    intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
  95
  96         /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
  97         intel_uncore_write(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
  98                    intel_uncore_read(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
  99
 100         /*
 101          * WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl
 102          * Display WA #0859: skl,bxt,kbl,glk,cfl
 103          */
 104         intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
 105                    DISP_FBC_MEMORY_WAKE);
 106 }
 107
 108 static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
 109 {
 110         gen9_init_clock_gating(dev_priv);
 111
 112         /* WaDisableSDEUnitClockGating:bxt */
 113         intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |
 114                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
 115
 116         /*
 117          * FIXME:
 118          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
 119          */
 120         intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |
 121                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
 122
 123         /*
 124          * Wa: Backlight PWM may stop in the asserted state, causing backlight
 125          * to stay fully on.
 126          */
 127         intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_0, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_0) |
 128                    PWM1_GATING_DIS | PWM2_GATING_DIS);
 129
 130         /*
 131          * Lower the display internal timeout.
 132          * This is needed to avoid any hard hangs when DSI port PLL
 133          * is off and a MMIO access is attempted by any privilege
 134          * application, using batch buffers or any other means.
 135          */
 136         intel_uncore_write(&dev_priv->uncore, RM_TIMEOUT, MMIO_TIMEOUT_US(950));
 137
 138         /*
 139          * WaFbcTurnOffFbcWatermark:bxt
 140          * Display WA #0562: bxt
 141          */
 142         intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
 143                    DISP_FBC_WM_DIS);
 144
 145         /*
 146          * WaFbcHighMemBwCorruptionAvoidance:bxt
 147          * Display WA #0883: bxt
 148          */
 149         intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
 150                    ILK_DPFC_DISABLE_DUMMY0);
 151 }
 152
 153 static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
 154 {
 155         gen9_init_clock_gating(dev_priv);
 156
 157         /*
 158          * WaDisablePWMClockGating:glk
 159          * Backlight PWM may stop in the asserted state, causing backlight
 160          * to stay fully on.
 161          */
 162         intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_0, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_0) |
 163                    PWM1_GATING_DIS | PWM2_GATING_DIS);
 164 }
 165
 166 static void pnv_get_mem_freq(struct drm_i915_private *dev_priv)
 167 {
 168         u32 tmp;
 169
 170         tmp = intel_uncore_read(&dev_priv->uncore, CLKCFG);
 171
 172         switch (tmp & CLKCFG_FSB_MASK) {
 173         case CLKCFG_FSB_533:
 174                 dev_priv->fsb_freq = 533; /* 133*4 */
 175                 break;
 176         case CLKCFG_FSB_800:
 177                 dev_priv->fsb_freq = 800; /* 200*4 */
 178                 break;
 179         case CLKCFG_FSB_667:
 180                 dev_priv->fsb_freq =  667; /* 167*4 */
 181                 break;
 182         case CLKCFG_FSB_400:
 183                 dev_priv->fsb_freq = 400; /* 100*4 */
 184                 break;
 185         }
 186
 187         switch (tmp & CLKCFG_MEM_MASK) {
 188         case CLKCFG_MEM_533:
 189                 dev_priv->mem_freq = 533;
 190                 break;
 191         case CLKCFG_MEM_667:
 192                 dev_priv->mem_freq = 667;
 193                 break;
 194         case CLKCFG_MEM_800:
 195                 dev_priv->mem_freq = 800;
 196                 break;
 197         }
 198
 199         /* detect pineview DDR3 setting */
 200         tmp = intel_uncore_read(&dev_priv->uncore, CSHRDDR3CTL);
 201         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 202 }
 203
 204 static void ilk_get_mem_freq(struct drm_i915_private *dev_priv)
 205 {
 206         u16 ddrpll, csipll;
 207
 208         ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1);
 209         csipll = intel_uncore_read16(&dev_priv->uncore, CSIPLL0);
 210
 211         switch (ddrpll & 0xff) {
 212         case 0xc:
 213                 dev_priv->mem_freq = 800;
 214                 break;
 215         case 0x10:
 216                 dev_priv->mem_freq = 1066;
 217                 break;
 218         case 0x14:
 219                 dev_priv->mem_freq = 1333;
 220                 break;
 221         case 0x18:
 222                 dev_priv->mem_freq = 1600;
 223                 break;
 224         default:
 225                 drm_dbg(&dev_priv->drm, "unknown memory frequency 0x%02x\n",
 226                         ddrpll & 0xff);
 227                 dev_priv->mem_freq = 0;
 228                 break;
 229         }
 230
 231         switch (csipll & 0x3ff) {
 232         case 0x00c:
 233                 dev_priv->fsb_freq = 3200;
 234                 break;
 235         case 0x00e:
 236                 dev_priv->fsb_freq = 3733;
 237                 break;
 238         case 0x010:
 239                 dev_priv->fsb_freq = 4266;
 240                 break;
 241         case 0x012:
 242                 dev_priv->fsb_freq = 4800;
 243                 break;
 244         case 0x014:
 245                 dev_priv->fsb_freq = 5333;
 246                 break;
 247         case 0x016:
 248                 dev_priv->fsb_freq = 5866;
 249                 break;
 250         case 0x018:
 251                 dev_priv->fsb_freq = 6400;
 252                 break;
 253         default:
 254                 drm_dbg(&dev_priv->drm, "unknown fsb frequency 0x%04x\n",
 255                         csipll & 0x3ff);
 256                 dev_priv->fsb_freq = 0;
 257                 break;
 258         }
 259 }
 260
 261 static const struct cxsr_latency cxsr_latency_table[] = {
 262         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 263         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 264         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 265         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 266         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 267
 268         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 269         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 270         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 271         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 272         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 273
 274         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 275         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 276         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 277         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 278         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 279
 280         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 281         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 282         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 283         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 284         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 285
 286         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 287         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 288         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 289         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 290         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 291
 292         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 293         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 294         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 295         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 296         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 297 };
 298
 299 static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
 300                                                          bool is_ddr3,
 301                                                          int fsb,
 302                                                          int mem)
 303 {
 304         const struct cxsr_latency *latency;
 305         int i;
 306
 307         if (fsb == 0 || mem == 0)
 308                 return NULL;
 309
 310         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 311                 latency = &cxsr_latency_table[i];
 312                 if (is_desktop == latency->is_desktop &&
 313                     is_ddr3 == latency->is_ddr3 &&
 314                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 315                         return latency;
 316         }
 317
 318         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 319
 320         return NULL;
 321 }
 322
 323 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 324 {
 325         u32 val;
 326
 327         vlv_punit_get(dev_priv);
 328
 329         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 330         if (enable)
 331                 val &= ~FORCE_DDR_HIGH_FREQ;
 332         else
 333                 val |= FORCE_DDR_HIGH_FREQ;
 334         val &= ~FORCE_DDR_LOW_FREQ;
 335         val |= FORCE_DDR_FREQ_REQ_ACK;
 336         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 337
 338         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 339                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 340                 drm_err(&dev_priv->drm,
 341                         "timed out waiting for Punit DDR DVFS request\n");
 342
 343         vlv_punit_put(dev_priv);
 344 }
 345
 346 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 347 {
 348         u32 val;
 349
 350         vlv_punit_get(dev_priv);
 351
 352         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
 353         if (enable)
 354                 val |= DSP_MAXFIFO_PM5_ENABLE;
 355         else
 356                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 357         vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
 358
 359         vlv_punit_put(dev_priv);
 360 }
 361
 362 #define FW_WM(value, plane) \
 363         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 364
 365 static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 366 {
 367         bool was_enabled;
 368         u32 val;
 369
 370         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 371                 was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
 372                 intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 373                 intel_uncore_posting_read(&dev_priv->uncore, FW_BLC_SELF_VLV);
 374         } else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) {
 375                 was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN;
 376                 intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 377                 intel_uncore_posting_read(&dev_priv->uncore, FW_BLC_SELF);
 378         } else if (IS_PINEVIEW(dev_priv)) {
 379                 val = intel_uncore_read(&dev_priv->uncore, DSPFW3);
 380                 was_enabled = val & PINEVIEW_SELF_REFRESH_EN;
 381                 if (enable)
 382                         val |= PINEVIEW_SELF_REFRESH_EN;
 383                 else
 384                         val &= ~PINEVIEW_SELF_REFRESH_EN;
 385                 intel_uncore_write(&dev_priv->uncore, DSPFW3, val);
 386                 intel_uncore_posting_read(&dev_priv->uncore, DSPFW3);
 387         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
 388                 was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN;
 389                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 390                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 391                 intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, val);
 392                 intel_uncore_posting_read(&dev_priv->uncore, FW_BLC_SELF);
 393         } else if (IS_I915GM(dev_priv)) {
 394                 /*
 395                  * FIXME can't find a bit like this for 915G, and
 396                  * and yet it does have the related watermark in
 397                  * FW_BLC_SELF. What's going on?
 398                  */
 399                 was_enabled = intel_uncore_read(&dev_priv->uncore, INSTPM) & INSTPM_SELF_EN;
 400                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 401                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 402                 intel_uncore_write(&dev_priv->uncore, INSTPM, val);
 403                 intel_uncore_posting_read(&dev_priv->uncore, INSTPM);
 404         } else {
 405                 return false;
 406         }
 407
 408         trace_intel_memory_cxsr(dev_priv, was_enabled, enable);
 409
 410         drm_dbg_kms(&dev_priv->drm, "memory self-refresh is %s (was %s)\n",
 411                     enableddisabled(enable),
 412                     enableddisabled(was_enabled));
 413
 414         return was_enabled;
 415 }
 416
 417 /**
 418  * intel_set_memory_cxsr - Configure CxSR state
 419  * @dev_priv: i915 device
 420  * @enable: Allow vs. disallow CxSR
 421  *
 422  * Allow or disallow the system to enter a special CxSR
 423  * (C-state self refresh) state. What typically happens in CxSR mode
 424  * is that several display FIFOs may get combined into a single larger
 425  * FIFO for a particular plane (so called max FIFO mode) to allow the
 426  * system to defer memory fetches longer, and the memory will enter
 427  * self refresh.
 428  *
 429  * Note that enabling CxSR does not guarantee that the system enter
 430  * this special mode, nor does it guarantee that the system stays
 431  * in that mode once entered. So this just allows/disallows the system
 432  * to autonomously utilize the CxSR mode. Other factors such as core
 433  * C-states will affect when/if the system actually enters/exits the
 434  * CxSR mode.
 435  *
 436  * Note that on VLV/CHV this actually only controls the max FIFO mode,
 437  * and the system is free to enter/exit memory self refresh at any time
 438  * even when the use of CxSR has been disallowed.
 439  *
 440  * While the system is actually in the CxSR/max FIFO mode, some plane
 441  * control registers will not get latched on vblank. Thus in order to
 442  * guarantee the system will respond to changes in the plane registers
 443  * we must always disallow CxSR prior to making changes to those registers.
 444  * Unfortunately the system will re-evaluate the CxSR conditions at
 445  * frame start which happens after vblank start (which is when the plane
 446  * registers would get latched), so we can't proceed with the plane update
 447  * during the same frame where we disallowed CxSR.
 448  *
 449  * Certain platforms also have a deeper HPLL SR mode. Fortunately the
 450  * HPLL SR mode depends on CxSR itself, so we don't have to hand hold
 451  * the hardware w.r.t. HPLL SR when writing to plane registers.
 452  * Disallowing just CxSR is sufficient.
 453  */
 454 bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 455 {
 456         bool ret;
 457
 458         mutex_lock(&dev_priv->wm.wm_mutex);
 459         ret = _intel_set_memory_cxsr(dev_priv, enable);
 460         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 461                 dev_priv->wm.vlv.cxsr = enable;
 462         else if (IS_G4X(dev_priv))
 463                 dev_priv->wm.g4x.cxsr = enable;
 464         mutex_unlock(&dev_priv->wm.wm_mutex);
 465
 466         return ret;
 467 }
 468
 469 /*
 470  * Latency for FIFO fetches is dependent on several factors:
 471  *   - memory configuration (speed, channels)
 472  *   - chipset
 473  *   - current MCH state
 474  * It can be fairly high in some situations, so here we assume a fairly
 475  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 476  * set this value too high, the FIFO will fetch frequently to stay full)
 477  * and power consumption (set it too low to save power and we might see
 478  * FIFO underruns and display "flicker").
 479  *
 480  * A value of 5us seems to be a good balance; safe for very low end
 481  * platforms but not overly aggressive on lower latency configs.
 482  */
 483 static const int pessimal_latency_ns = 5000;
 484
 485 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 486         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 487
 488 static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
 489 {
 490         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 491         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 492         struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
 493         enum pipe pipe = crtc->pipe;
 494         int sprite0_start, sprite1_start;
 495         u32 dsparb, dsparb2, dsparb3;
 496
 497         switch (pipe) {
 498         case PIPE_A:
 499                 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
 500                 dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
 501                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 502                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 503                 break;
 504         case PIPE_B:
 505                 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
 506                 dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
 507                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 508                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 509                 break;
 510         case PIPE_C:
 511                 dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
 512                 dsparb3 = intel_uncore_read(&dev_priv->uncore, DSPARB3);
 513                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 514                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 515                 break;
 516         default:
 517                 MISSING_CASE(pipe);
 518                 return;
 519         }
 520
 521         fifo_state->plane[PLANE_PRIMARY] = sprite0_start;
 522         fifo_state->plane[PLANE_SPRITE0] = sprite1_start - sprite0_start;
 523         fifo_state->plane[PLANE_SPRITE1] = 511 - sprite1_start;
 524         fifo_state->plane[PLANE_CURSOR] = 63;
 525 }
 526
 527 static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
 528                               enum i9xx_plane_id i9xx_plane)
 529 {
 530         u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
 531         int size;
 532
 533         size = dsparb & 0x7f;
 534         if (i9xx_plane == PLANE_B)
 535                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 536
 537         drm_dbg_kms(&dev_priv->drm, "FIFO size - (0x%08x) %c: %d\n",
 538                     dsparb, plane_name(i9xx_plane), size);
 539
 540         return size;
 541 }
 542
 543 static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
 544                               enum i9xx_plane_id i9xx_plane)
 545 {
 546         u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
 547         int size;
 548
 549         size = dsparb & 0x1ff;
 550         if (i9xx_plane == PLANE_B)
 551                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 552         size >>= 1; /* Convert to cachelines */
 553
 554         drm_dbg_kms(&dev_priv->drm, "FIFO size - (0x%08x) %c: %d\n",
 555                     dsparb, plane_name(i9xx_plane), size);
 556
 557         return size;
 558 }
 559
 560 static int i845_get_fifo_size(struct drm_i915_private *dev_priv,
 561                               enum i9xx_plane_id i9xx_plane)
 562 {
 563         u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
 564         int size;
 565
 566         size = dsparb & 0x7f;
 567         size >>= 2; /* Convert to cachelines */
 568
 569         drm_dbg_kms(&dev_priv->drm, "FIFO size - (0x%08x) %c: %d\n",
 570                     dsparb, plane_name(i9xx_plane), size);
 571
 572         return size;
 573 }
 574
 575 /* Pineview has different values for various configs */
 576 static const struct intel_watermark_params pnv_display_wm = {
 577         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 578         .max_wm = PINEVIEW_MAX_WM,
 579         .default_wm = PINEVIEW_DFT_WM,
 580         .guard_size = PINEVIEW_GUARD_WM,
 581         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 582 };
 583
 584 static const struct intel_watermark_params pnv_display_hplloff_wm = {
 585         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 586         .max_wm = PINEVIEW_MAX_WM,
 587         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 588         .guard_size = PINEVIEW_GUARD_WM,
 589         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 590 };
 591
 592 static const struct intel_watermark_params pnv_cursor_wm = {
 593         .fifo_size = PINEVIEW_CURSOR_FIFO,
 594         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 595         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 596         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 597         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 598 };
 599
 600 static const struct intel_watermark_params pnv_cursor_hplloff_wm = {
 601         .fifo_size = PINEVIEW_CURSOR_FIFO,
 602         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 603         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 604         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 605         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 606 };
 607
 608 static const struct intel_watermark_params i965_cursor_wm_info = {
 609         .fifo_size = I965_CURSOR_FIFO,
 610         .max_wm = I965_CURSOR_MAX_WM,
 611         .default_wm = I965_CURSOR_DFT_WM,
 612         .guard_size = 2,
 613         .cacheline_size = I915_FIFO_LINE_SIZE,
 614 };
 615
 616 static const struct intel_watermark_params i945_wm_info = {
 617         .fifo_size = I945_FIFO_SIZE,
 618         .max_wm = I915_MAX_WM,
 619         .default_wm = 1,
 620         .guard_size = 2,
 621         .cacheline_size = I915_FIFO_LINE_SIZE,
 622 };
 623
 624 static const struct intel_watermark_params i915_wm_info = {
 625         .fifo_size = I915_FIFO_SIZE,
 626         .max_wm = I915_MAX_WM,
 627         .default_wm = 1,
 628         .guard_size = 2,
 629         .cacheline_size = I915_FIFO_LINE_SIZE,
 630 };
 631
 632 static const struct intel_watermark_params i830_a_wm_info = {
 633         .fifo_size = I855GM_FIFO_SIZE,
 634         .max_wm = I915_MAX_WM,
 635         .default_wm = 1,
 636         .guard_size = 2,
 637         .cacheline_size = I830_FIFO_LINE_SIZE,
 638 };
 639
 640 static const struct intel_watermark_params i830_bc_wm_info = {
 641         .fifo_size = I855GM_FIFO_SIZE,
 642         .max_wm = I915_MAX_WM/2,
 643         .default_wm = 1,
 644         .guard_size = 2,
 645         .cacheline_size = I830_FIFO_LINE_SIZE,
 646 };
 647
 648 static const struct intel_watermark_params i845_wm_info = {
 649         .fifo_size = I830_FIFO_SIZE,
 650         .max_wm = I915_MAX_WM,
 651         .default_wm = 1,
 652         .guard_size = 2,
 653         .cacheline_size = I830_FIFO_LINE_SIZE,
 654 };
 655
 656 /**
 657  * intel_wm_method1 - Method 1 / "small buffer" watermark formula
 658  * @pixel_rate: Pipe pixel rate in kHz
 659  * @cpp: Plane bytes per pixel
 660  * @latency: Memory wakeup latency in 0.1us units
 661  *
 662  * Compute the watermark using the method 1 or "small buffer"
 663  * formula. The caller may additonally add extra cachelines
 664  * to account for TLB misses and clock crossings.
 665  *
 666  * This method is concerned with the short term drain rate
 667  * of the FIFO, ie. it does not account for blanking periods
 668  * which would effectively reduce the average drain rate across
 669  * a longer period. The name "small" refers to the fact the
 670  * FIFO is relatively small compared to the amount of data
 671  * fetched.
 672  *
 673  * The FIFO level vs. time graph might look something like:
 674  *
 675  *   |\   |\
 676  *   | \  | \
 677  * __---__---__ (- plane active, _ blanking)
 678  * -> time
 679  *
 680  * or perhaps like this:
 681  *
 682  *   |\|\  |\|\
 683  * __----__----__ (- plane active, _ blanking)
 684  * -> time
 685  *
 686  * Returns:
 687  * The watermark in bytes
 688  */
 689 static unsigned int intel_wm_method1(unsigned int pixel_rate,
 690                                      unsigned int cpp,
 691                                      unsigned int latency)
 692 {
 693         u64 ret;
 694
 695         ret = mul_u32_u32(pixel_rate, cpp * latency);
 696         ret = DIV_ROUND_UP_ULL(ret, 10000);
 697
 698         return ret;
 699 }
 700
 701 /**
 702  * intel_wm_method2 - Method 2 / "large buffer" watermark formula
 703  * @pixel_rate: Pipe pixel rate in kHz
 704  * @htotal: Pipe horizontal total
 705  * @width: Plane width in pixels
 706  * @cpp: Plane bytes per pixel
 707  * @latency: Memory wakeup latency in 0.1us units
 708  *
 709  * Compute the watermark using the method 2 or "large buffer"
 710  * formula. The caller may additonally add extra cachelines
 711  * to account for TLB misses and clock crossings.
 712  *
 713  * This method is concerned with the long term drain rate
 714  * of the FIFO, ie. it does account for blanking periods
 715  * which effectively reduce the average drain rate across
 716  * a longer period. The name "large" refers to the fact the
 717  * FIFO is relatively large compared to the amount of data
 718  * fetched.
 719  *
 720  * The FIFO level vs. time graph might look something like:
 721  *
 722  *    |\___       |\___
 723  *    |    \___   |    \___
 724  *    |        \  |        \
 725  * __ --__--__--__--__--__--__ (- plane active, _ blanking)
 726  * -> time
 727  *
 728  * Returns:
 729  * The watermark in bytes
 730  */
 731 static unsigned int intel_wm_method2(unsigned int pixel_rate,
 732                                      unsigned int htotal,
 733                                      unsigned int width,
 734                                      unsigned int cpp,
 735                                      unsigned int latency)
 736 {
 737         unsigned int ret;
 738
 739         /*
 740          * FIXME remove once all users are computing
 741          * watermarks in the correct place.
 742          */
 743         if (WARN_ON_ONCE(htotal == 0))
 744                 htotal = 1;
 745
 746         ret = (latency * pixel_rate) / (htotal * 10000);
 747         ret = (ret + 1) * width * cpp;
 748
 749         return ret;
 750 }
 751
 752 /**
 753  * intel_calculate_wm - calculate watermark level
 754  * @pixel_rate: pixel clock
 755  * @wm: chip FIFO params
 756  * @fifo_size: size of the FIFO buffer
 757  * @cpp: bytes per pixel
 758  * @latency_ns: memory latency for the platform
 759  *
 760  * Calculate the watermark level (the level at which the display plane will
 761  * start fetching from memory again).  Each chip has a different display
 762  * FIFO size and allocation, so the caller needs to figure that out and pass
 763  * in the correct intel_watermark_params structure.
 764  *
 765  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 766  * on the pixel size.  When it reaches the watermark level, it'll start
 767  * fetching FIFO line sized based chunks from memory until the FIFO fills
 768  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 769  * will occur, and a display engine hang could result.
 770  */
 771 static unsigned int intel_calculate_wm(int pixel_rate,
 772                                        const struct intel_watermark_params *wm,
 773                                        int fifo_size, int cpp,
 774                                        unsigned int latency_ns)
 775 {
 776         int entries, wm_size;
 777
 778         /*
 779          * Note: we need to make sure we don't overflow for various clock &
 780          * latency values.
 781          * clocks go from a few thousand to several hundred thousand.
 782          * latency is usually a few thousand
 783          */
 784         entries = intel_wm_method1(pixel_rate, cpp,
 785                                    latency_ns / 100);
 786         entries = DIV_ROUND_UP(entries, wm->cacheline_size) +
 787                 wm->guard_size;
 788         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries);
 789
 790         wm_size = fifo_size - entries;
 791         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
 792
 793         /* Don't promote wm_size to unsigned... */
 794         if (wm_size > wm->max_wm)
 795                 wm_size = wm->max_wm;
 796         if (wm_size <= 0)
 797                 wm_size = wm->default_wm;
 798
 799         /*
 800          * Bspec seems to indicate that the value shouldn't be lower than
 801          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 802          * Lets go for 8 which is the burst size since certain platforms
 803          * already use a hardcoded 8 (which is what the spec says should be
 804          * done).
 805          */
 806         if (wm_size <= 8)
 807                 wm_size = 8;
 808
 809         return wm_size;
 810 }
 811
 812 static bool is_disabling(int old, int new, int threshold)
 813 {
 814         return old >= threshold && new < threshold;
 815 }
 816
 817 static bool is_enabling(int old, int new, int threshold)
 818 {
 819         return old < threshold && new >= threshold;
 820 }
 821
 822 static int intel_wm_num_levels(struct drm_i915_private *dev_priv)
 823 {
 824         return dev_priv->wm.max_level + 1;
 825 }
 826
 827 static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
 828                                    const struct intel_plane_state *plane_state)
 829 {
 830         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 831
 832         /* FIXME check the 'enable' instead */
 833         if (!crtc_state->hw.active)
 834                 return false;
 835
 836         /*
 837          * Treat cursor with fb as always visible since cursor updates
 838          * can happen faster than the vrefresh rate, and the current
 839          * watermark code doesn't handle that correctly. Cursor updates
 840          * which set/clear the fb or change the cursor size are going
 841          * to get throttled by intel_legacy_cursor_update() to work
 842          * around this problem with the watermark code.
 843          */
 844         if (plane->id == PLANE_CURSOR)
 845                 return plane_state->hw.fb != NULL;
 846         else
 847                 return plane_state->uapi.visible;
 848 }
 849
 850 static bool intel_crtc_active(struct intel_crtc *crtc)
 851 {
 852         /* Be paranoid as we can arrive here with only partial
 853          * state retrieved from the hardware during setup.
 854          *
 855          * We can ditch the adjusted_mode.crtc_clock check as soon
 856          * as Haswell has gained clock readout/fastboot support.
 857          *
 858          * We can ditch the crtc->primary->state->fb check as soon as we can
 859          * properly reconstruct framebuffers.
 860          *
 861          * FIXME: The intel_crtc->active here should be switched to
 862          * crtc->state->active once we have proper CRTC states wired up
 863          * for atomic.
 864          */
 865         return crtc->active && crtc->base.primary->state->fb &&
 866                 crtc->config->hw.adjusted_mode.crtc_clock;
 867 }
 868
 869 static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
 870 {
 871         struct intel_crtc *crtc, *enabled = NULL;
 872
 873         for_each_intel_crtc(&dev_priv->drm, crtc) {
 874                 if (intel_crtc_active(crtc)) {
 875                         if (enabled)
 876                                 return NULL;
 877                         enabled = crtc;
 878                 }
 879         }
 880
 881         return enabled;
 882 }
 883
 884 static void pnv_update_wm(struct intel_crtc *unused_crtc)
 885 {
 886         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
 887         struct intel_crtc *crtc;
 888         const struct cxsr_latency *latency;
 889         u32 reg;
 890         unsigned int wm;
 891
 892         latency = intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
 893                                          dev_priv->is_ddr3,
 894                                          dev_priv->fsb_freq,
 895                                          dev_priv->mem_freq);
 896         if (!latency) {
 897                 drm_dbg_kms(&dev_priv->drm,
 898                             "Unknown FSB/MEM found, disable CxSR\n");
 899                 intel_set_memory_cxsr(dev_priv, false);
 900                 return;
 901         }
 902
 903         crtc = single_enabled_crtc(dev_priv);
 904         if (crtc) {
 905                 const struct drm_display_mode *pipe_mode =
 906                         &crtc->config->hw.pipe_mode;
 907                 const struct drm_framebuffer *fb =
 908                         crtc->base.primary->state->fb;
 909                 int cpp = fb->format->cpp[0];
 910                 int clock = pipe_mode->crtc_clock;
 911
 912                 /* Display SR */
 913                 wm = intel_calculate_wm(clock, &pnv_display_wm,
 914                                         pnv_display_wm.fifo_size,
 915                                         cpp, latency->display_sr);
 916                 reg = intel_uncore_read(&dev_priv->uncore, DSPFW1);
 917                 reg &= ~DSPFW_SR_MASK;
 918                 reg |= FW_WM(wm, SR);
 919                 intel_uncore_write(&dev_priv->uncore, DSPFW1, reg);
 920                 drm_dbg_kms(&dev_priv->drm, "DSPFW1 register is %x\n", reg);
 921
 922                 /* cursor SR */
 923                 wm = intel_calculate_wm(clock, &pnv_cursor_wm,
 924                                         pnv_display_wm.fifo_size,
 925                                         4, latency->cursor_sr);
 926                 reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
 927                 reg &= ~DSPFW_CURSOR_SR_MASK;
 928                 reg |= FW_WM(wm, CURSOR_SR);
 929                 intel_uncore_write(&dev_priv->uncore, DSPFW3, reg);
 930
 931                 /* Display HPLL off SR */
 932                 wm = intel_calculate_wm(clock, &pnv_display_hplloff_wm,
 933                                         pnv_display_hplloff_wm.fifo_size,
 934                                         cpp, latency->display_hpll_disable);
 935                 reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
 936                 reg &= ~DSPFW_HPLL_SR_MASK;
 937                 reg |= FW_WM(wm, HPLL_SR);
 938                 intel_uncore_write(&dev_priv->uncore, DSPFW3, reg);
 939
 940                 /* cursor HPLL off SR */
 941                 wm = intel_calculate_wm(clock, &pnv_cursor_hplloff_wm,
 942                                         pnv_display_hplloff_wm.fifo_size,
 943                                         4, latency->cursor_hpll_disable);
 944                 reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
 945                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 946                 reg |= FW_WM(wm, HPLL_CURSOR);
 947                 intel_uncore_write(&dev_priv->uncore, DSPFW3, reg);
 948                 drm_dbg_kms(&dev_priv->drm, "DSPFW3 register is %x\n", reg);
 949
 950                 intel_set_memory_cxsr(dev_priv, true);
 951         } else {
 952                 intel_set_memory_cxsr(dev_priv, false);
 953         }
 954 }
 955
 956 /*
 957  * Documentation says:
 958  * "If the line size is small, the TLB fetches can get in the way of the
 959  *  data fetches, causing some lag in the pixel data return which is not
 960  *  accounted for in the above formulas. The following adjustment only
 961  *  needs to be applied if eight whole lines fit in the buffer at once.
 962  *  The WM is adjusted upwards by the difference between the FIFO size
 963  *  and the size of 8 whole lines. This adjustment is always performed
 964  *  in the actual pixel depth regardless of whether FBC is enabled or not."
 965  */
 966 static unsigned int g4x_tlb_miss_wa(int fifo_size, int width, int cpp)
 967 {
 968         int tlb_miss = fifo_size * 64 - width * cpp * 8;
 969
 970         return max(0, tlb_miss);
 971 }
 972
 973 static void g4x_write_wm_values(struct drm_i915_private *dev_priv,
 974                                 const struct g4x_wm_values *wm)
 975 {
 976         enum pipe pipe;
 977
 978         for_each_pipe(dev_priv, pipe)
 979                 trace_g4x_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
 980
 981         intel_uncore_write(&dev_priv->uncore, DSPFW1,
 982                    FW_WM(wm->sr.plane, SR) |
 983                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
 984                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
 985                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
 986         intel_uncore_write(&dev_priv->uncore, DSPFW2,
 987                    (wm->fbc_en ? DSPFW_FBC_SR_EN : 0) |
 988                    FW_WM(wm->sr.fbc, FBC_SR) |
 989                    FW_WM(wm->hpll.fbc, FBC_HPLL_SR) |
 990                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) |
 991                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
 992                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
 993         intel_uncore_write(&dev_priv->uncore, DSPFW3,
 994                    (wm->hpll_en ? DSPFW_HPLL_SR_EN : 0) |
 995                    FW_WM(wm->sr.cursor, CURSOR_SR) |
 996                    FW_WM(wm->hpll.cursor, HPLL_CURSOR) |
 997                    FW_WM(wm->hpll.plane, HPLL_SR));
 998
 999         intel_uncore_posting_read(&dev_priv->uncore, DSPFW1);
1000 }
1001
1002 #define FW_WM_VLV(value, plane) \
1003         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
1004
1005 static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
1006                                 const struct vlv_wm_values *wm)
1007 {
1008         enum pipe pipe;
1009
1010         for_each_pipe(dev_priv, pipe) {
1011                 trace_vlv_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
1012
1013                 intel_uncore_write(&dev_priv->uncore, VLV_DDL(pipe),
1014                            (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) |
1015                            (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) |
1016                            (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) |
1017                            (wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT));
1018         }
1019
1020         /*
1021          * Zero the (unused) WM1 watermarks, and also clear all the
1022          * high order bits so that there are no out of bounds values
1023          * present in the registers during the reprogramming.
1024          */
1025         intel_uncore_write(&dev_priv->uncore, DSPHOWM, 0);
1026         intel_uncore_write(&dev_priv->uncore, DSPHOWM1, 0);
1027         intel_uncore_write(&dev_priv->uncore, DSPFW4, 0);
1028         intel_uncore_write(&dev_priv->uncore, DSPFW5, 0);
1029         intel_uncore_write(&dev_priv->uncore, DSPFW6, 0);
1030
1031         intel_uncore_write(&dev_priv->uncore, DSPFW1,
1032                    FW_WM(wm->sr.plane, SR) |
1033                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
1034                    FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
1035                    FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
1036         intel_uncore_write(&dev_priv->uncore, DSPFW2,
1037                    FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
1038                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
1039                    FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
1040         intel_uncore_write(&dev_priv->uncore, DSPFW3,
1041                    FW_WM(wm->sr.cursor, CURSOR_SR));
1042
1043         if (IS_CHERRYVIEW(dev_priv)) {
1044                 intel_uncore_write(&dev_priv->uncore, DSPFW7_CHV,
1045                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
1046                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
1047                 intel_uncore_write(&dev_priv->uncore, DSPFW8_CHV,
1048                            FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |
1049                            FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE));
1050                 intel_uncore_write(&dev_priv->uncore, DSPFW9_CHV,
1051                            FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |
1052                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC));
1053                 intel_uncore_write(&dev_priv->uncore, DSPHOWM,
1054                            FW_WM(wm->sr.plane >> 9, SR_HI) |
1055                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) |
1056                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) |
1057                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) |
1058                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
1059                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
1060                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
1061                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
1062                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
1063                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
1064         } else {
1065                 intel_uncore_write(&dev_priv->uncore, DSPFW7,
1066                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
1067                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
1068                 intel_uncore_write(&dev_priv->uncore, DSPHOWM,
1069                            FW_WM(wm->sr.plane >> 9, SR_HI) |
1070                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
1071                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
1072                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
1073                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
1074                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
1075                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
1076         }
1077
1078         intel_uncore_posting_read(&dev_priv->uncore, DSPFW1);
1079 }
1080
1081 #undef FW_WM_VLV
1082
1083 static void g4x_setup_wm_latency(struct drm_i915_private *dev_priv)
1084 {
1085         /* all latencies in usec */
1086         dev_priv->wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5;
1087         dev_priv->wm.pri_latency[G4X_WM_LEVEL_SR] = 12;
1088         dev_priv->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35;
1089
1090         dev_priv->wm.max_level = G4X_WM_LEVEL_HPLL;
1091 }
1092
1093 static int g4x_plane_fifo_size(enum plane_id plane_id, int level)
1094 {
1095         /*
1096          * DSPCNTR[13] supposedly controls whether the
1097          * primary plane can use the FIFO space otherwise
1098          * reserved for the sprite plane. It's not 100% clear
1099          * what the actual FIFO size is, but it looks like we
1100          * can happily set both primary and sprite watermarks
1101          * up to 127 cachelines. So that would seem to mean
1102          * that either DSPCNTR[13] doesn't do anything, or that
1103          * the total FIFO is >= 256 cachelines in size. Either
1104          * way, we don't seem to have to worry about this
1105          * repartitioning as the maximum watermark value the
1106          * register can hold for each plane is lower than the
1107          * minimum FIFO size.
1108          */
1109         switch (plane_id) {
1110         case PLANE_CURSOR:
1111                 return 63;
1112         case PLANE_PRIMARY:
1113                 return level == G4X_WM_LEVEL_NORMAL ? 127 : 511;
1114         case PLANE_SPRITE0:
1115                 return level == G4X_WM_LEVEL_NORMAL ? 127 : 0;
1116         default:
1117                 MISSING_CASE(plane_id);
1118                 return 0;
1119         }
1120 }
1121
1122 static int g4x_fbc_fifo_size(int level)
1123 {
1124         switch (level) {
1125         case G4X_WM_LEVEL_SR:
1126                 return 7;
1127         case G4X_WM_LEVEL_HPLL:
1128                 return 15;
1129         default:
1130                 MISSING_CASE(level);
1131                 return 0;
1132         }
1133 }
1134
1135 static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
1136                           const struct intel_plane_state *plane_state,
1137                           int level)
1138 {
1139         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1140         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1141         const struct drm_display_mode *pipe_mode =
1142                 &crtc_state->hw.pipe_mode;
1143         unsigned int latency = dev_priv->wm.pri_latency[level] * 10;
1144         unsigned int clock, htotal, cpp, width, wm;
1145
1146         if (latency == 0)
1147                 return USHRT_MAX;
1148
1149         if (!intel_wm_plane_visible(crtc_state, plane_state))
1150                 return 0;
1151
1152         cpp = plane_state->hw.fb->format->cpp[0];
1153
1154         /*
1155          * Not 100% sure which way ELK should go here as the
1156          * spec only says CL/CTG should assume 32bpp and BW
1157          * doesn't need to. But as these things followed the
1158          * mobile vs. desktop lines on gen3 as well, let's
1159          * assume ELK doesn't need this.
1160          *
1161          * The spec also fails to list such a restriction for
1162          * the HPLL watermark, which seems a little strange.
1163          * Let's use 32bpp for the HPLL watermark as well.
1164          */
1165         if (IS_GM45(dev_priv) && plane->id == PLANE_PRIMARY &&
1166             level != G4X_WM_LEVEL_NORMAL)
1167                 cpp = max(cpp, 4u);
1168
1169         clock = pipe_mode->crtc_clock;
1170         htotal = pipe_mode->crtc_htotal;
1171
1172         width = drm_rect_width(&plane_state->uapi.dst);
1173
1174         if (plane->id == PLANE_CURSOR) {
1175                 wm = intel_wm_method2(clock, htotal, width, cpp, latency);
1176         } else if (plane->id == PLANE_PRIMARY &&
1177                    level == G4X_WM_LEVEL_NORMAL) {
1178                 wm = intel_wm_method1(clock, cpp, latency);
1179         } else {
1180                 unsigned int small, large;
1181
1182                 small = intel_wm_method1(clock, cpp, latency);
1183                 large = intel_wm_method2(clock, htotal, width, cpp, latency);
1184
1185                 wm = min(small, large);
1186         }
1187
1188         wm += g4x_tlb_miss_wa(g4x_plane_fifo_size(plane->id, level),
1189                               width, cpp);
1190
1191         wm = DIV_ROUND_UP(wm, 64) + 2;
1192
1193         return min_t(unsigned int, wm, USHRT_MAX);
1194 }
1195
1196 static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
1197                                  int level, enum plane_id plane_id, u16 value)
1198 {
1199         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1200         bool dirty = false;
1201
1202         for (; level < intel_wm_num_levels(dev_priv); level++) {
1203                 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1204
1205                 dirty |= raw->plane[plane_id] != value;
1206                 raw->plane[plane_id] = value;
1207         }
1208
1209         return dirty;
1210 }
1211
1212 static bool g4x_raw_fbc_wm_set(struct intel_crtc_state *crtc_state,
1213                                int level, u16 value)
1214 {
1215         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1216         bool dirty = false;
1217
1218         /* NORMAL level doesn't have an FBC watermark */
1219         level = max(level, G4X_WM_LEVEL_SR);
1220
1221         for (; level < intel_wm_num_levels(dev_priv); level++) {
1222                 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1223
1224                 dirty |= raw->fbc != value;
1225                 raw->fbc = value;
1226         }
1227
1228         return dirty;
1229 }
1230
1231 static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
1232                               const struct intel_plane_state *plane_state,
1233                               u32 pri_val);
1234
1235 static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
1236                                      const struct intel_plane_state *plane_state)
1237 {
1238         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1239         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1240         int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
1241         enum plane_id plane_id = plane->id;
1242         bool dirty = false;
1243         int level;
1244
1245         if (!intel_wm_plane_visible(crtc_state, plane_state)) {
1246                 dirty |= g4x_raw_plane_wm_set(crtc_state, 0, plane_id, 0);
1247                 if (plane_id == PLANE_PRIMARY)
1248                         dirty |= g4x_raw_fbc_wm_set(crtc_state, 0, 0);
1249                 goto out;
1250         }
1251
1252         for (level = 0; level < num_levels; level++) {
1253                 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1254                 int wm, max_wm;
1255
1256                 wm = g4x_compute_wm(crtc_state, plane_state, level);
1257                 max_wm = g4x_plane_fifo_size(plane_id, level);
1258
1259                 if (wm > max_wm)
1260                         break;
1261
1262                 dirty |= raw->plane[plane_id] != wm;
1263                 raw->plane[plane_id] = wm;
1264
1265                 if (plane_id != PLANE_PRIMARY ||
1266                     level == G4X_WM_LEVEL_NORMAL)
1267                         continue;
1268
1269                 wm = ilk_compute_fbc_wm(crtc_state, plane_state,
1270                                         raw->plane[plane_id]);
1271                 max_wm = g4x_fbc_fifo_size(level);
1272
1273                 /*
1274                  * FBC wm is not mandatory as we
1275                  * can always just disable its use.
1276                  */
1277                 if (wm > max_wm)
1278                         wm = USHRT_MAX;
1279
1280                 dirty |= raw->fbc != wm;
1281                 raw->fbc = wm;
1282         }
1283
1284         /* mark watermarks as invalid */
1285         dirty |= g4x_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
1286
1287         if (plane_id == PLANE_PRIMARY)
1288                 dirty |= g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX);
1289
1290  out:
1291         if (dirty) {
1292                 drm_dbg_kms(&dev_priv->drm,
1293                             "%s watermarks: normal=%d, SR=%d, HPLL=%d\n",
1294                             plane->base.name,
1295                             crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id],
1296                             crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id],
1297                             crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]);
1298
1299                 if (plane_id == PLANE_PRIMARY)
1300                         drm_dbg_kms(&dev_priv->drm,
1301                                     "FBC watermarks: SR=%d, HPLL=%d\n",
1302                                     crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc,
1303                                     crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc);
1304         }
1305
1306         return dirty;
1307 }
1308
1309 static bool g4x_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
1310                                       enum plane_id plane_id, int level)
1311 {
1312         const struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1313
1314         return raw->plane[plane_id] <= g4x_plane_fifo_size(plane_id, level);
1315 }
1316
1317 static bool g4x_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state,
1318                                      int level)
1319 {
1320         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1321
1322         if (level > dev_priv->wm.max_level)
1323                 return false;
1324
1325         return g4x_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&
1326                 g4x_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) &&
1327                 g4x_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level);
1328 }
1329
1330 /* mark all levels starting from 'level' as invalid */
1331 static void g4x_invalidate_wms(struct intel_crtc *crtc,
1332                                struct g4x_wm_state *wm_state, int level)
1333 {
1334         if (level <= G4X_WM_LEVEL_NORMAL) {
1335                 enum plane_id plane_id;
1336
1337                 for_each_plane_id_on_crtc(crtc, plane_id)
1338                         wm_state->wm.plane[plane_id] = USHRT_MAX;
1339         }
1340
1341         if (level <= G4X_WM_LEVEL_SR) {
1342                 wm_state->cxsr = false;
1343                 wm_state->sr.cursor = USHRT_MAX;
1344                 wm_state->sr.plane = USHRT_MAX;
1345                 wm_state->sr.fbc = USHRT_MAX;
1346         }
1347
1348         if (level <= G4X_WM_LEVEL_HPLL) {
1349                 wm_state->hpll_en = false;
1350                 wm_state->hpll.cursor = USHRT_MAX;
1351                 wm_state->hpll.plane = USHRT_MAX;
1352                 wm_state->hpll.fbc = USHRT_MAX;
1353         }
1354 }
1355
1356 static bool g4x_compute_fbc_en(const struct g4x_wm_state *wm_state,
1357                                int level)
1358 {
1359         if (level < G4X_WM_LEVEL_SR)
1360                 return false;
1361
1362         if (level >= G4X_WM_LEVEL_SR &&
1363             wm_state->sr.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_SR))
1364                 return false;
1365
1366         if (level >= G4X_WM_LEVEL_HPLL &&
1367             wm_state->hpll.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_HPLL))
1368                 return false;
1369
1370         return true;
1371 }
1372
1373 static int g4x_compute_pipe_wm(struct intel_atomic_state *state,
1374                                struct intel_crtc *crtc)
1375 {
1376         struct intel_crtc_state *crtc_state =
1377                 intel_atomic_get_new_crtc_state(state, crtc);
1378         struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
1379         int num_active_planes = hweight8(crtc_state->active_planes &
1380                                          ~BIT(PLANE_CURSOR));
1381         const struct g4x_pipe_wm *raw;
1382         const struct intel_plane_state *old_plane_state;
1383         const struct intel_plane_state *new_plane_state;
1384         struct intel_plane *plane;
1385         enum plane_id plane_id;
1386         int i, level;
1387         unsigned int dirty = 0;
1388
1389         for_each_oldnew_intel_plane_in_state(state, plane,
1390                                              old_plane_state,
1391                                              new_plane_state, i) {
1392                 if (new_plane_state->hw.crtc != &crtc->base &&
1393                     old_plane_state->hw.crtc != &crtc->base)
1394                         continue;
1395
1396                 if (g4x_raw_plane_wm_compute(crtc_state, new_plane_state))
1397                         dirty |= BIT(plane->id);
1398         }
1399
1400         if (!dirty)
1401                 return 0;
1402
1403         level = G4X_WM_LEVEL_NORMAL;
1404         if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1405                 goto out;
1406
1407         raw = &crtc_state->wm.g4x.raw[level];
1408         for_each_plane_id_on_crtc(crtc, plane_id)
1409                 wm_state->wm.plane[plane_id] = raw->plane[plane_id];
1410
1411         level = G4X_WM_LEVEL_SR;
1412         if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1413                 goto out;
1414
1415         raw = &crtc_state->wm.g4x.raw[level];
1416         wm_state->sr.plane = raw->plane[PLANE_PRIMARY];
1417         wm_state->sr.cursor = raw->plane[PLANE_CURSOR];
1418         wm_state->sr.fbc = raw->fbc;
1419
1420         wm_state->cxsr = num_active_planes == BIT(PLANE_PRIMARY);
1421
1422         level = G4X_WM_LEVEL_HPLL;
1423         if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1424                 goto out;
1425
1426         raw = &crtc_state->wm.g4x.raw[level];
1427         wm_state->hpll.plane = raw->plane[PLANE_PRIMARY];
1428         wm_state->hpll.cursor = raw->plane[PLANE_CURSOR];
1429         wm_state->hpll.fbc = raw->fbc;
1430
1431         wm_state->hpll_en = wm_state->cxsr;
1432
1433         level++;
1434
1435  out:
1436         if (level == G4X_WM_LEVEL_NORMAL)
1437                 return -EINVAL;
1438
1439         /* invalidate the higher levels */
1440         g4x_invalidate_wms(crtc, wm_state, level);
1441
1442         /*
1443          * Determine if the FBC watermark(s) can be used. IF
1444          * this isn't the case we prefer to disable the FBC
1445          * watermark(s) rather than disable the SR/HPLL
1446          * level(s) entirely. 'level-1' is the highest valid
1447          * level here.
1448          */
1449         wm_state->fbc_en = g4x_compute_fbc_en(wm_state, level - 1);
1450
1451         return 0;
1452 }
1453
1454 static int g4x_compute_intermediate_wm(struct intel_atomic_state *state,
1455                                        struct intel_crtc *crtc)
1456 {
1457         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1458         struct intel_crtc_state *new_crtc_state =
1459                 intel_atomic_get_new_crtc_state(state, crtc);
1460         const struct intel_crtc_state *old_crtc_state =
1461                 intel_atomic_get_old_crtc_state(state, crtc);
1462         struct g4x_wm_state *intermediate = &new_crtc_state->wm.g4x.intermediate;
1463         const struct g4x_wm_state *optimal = &new_crtc_state->wm.g4x.optimal;
1464         const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal;
1465         enum plane_id plane_id;
1466
1467         if (!new_crtc_state->hw.active ||
1468             drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi)) {
1469                 *intermediate = *optimal;
1470
1471                 intermediate->cxsr = false;
1472                 intermediate->hpll_en = false;
1473                 goto out;
1474         }
1475
1476         intermediate->cxsr = optimal->cxsr && active->cxsr &&
1477                 !new_crtc_state->disable_cxsr;
1478         intermediate->hpll_en = optimal->hpll_en && active->hpll_en &&
1479                 !new_crtc_state->disable_cxsr;
1480         intermediate->fbc_en = optimal->fbc_en && active->fbc_en;
1481
1482         for_each_plane_id_on_crtc(crtc, plane_id) {
1483                 intermediate->wm.plane[plane_id] =
1484                         max(optimal->wm.plane[plane_id],
1485                             active->wm.plane[plane_id]);
1486
1487                 drm_WARN_ON(&dev_priv->drm, intermediate->wm.plane[plane_id] >
1488                             g4x_plane_fifo_size(plane_id, G4X_WM_LEVEL_NORMAL));
1489         }
1490
1491         intermediate->sr.plane = max(optimal->sr.plane,
1492                                      active->sr.plane);
1493         intermediate->sr.cursor = max(optimal->sr.cursor,
1494                                       active->sr.cursor);
1495         intermediate->sr.fbc = max(optimal->sr.fbc,
1496                                    active->sr.fbc);
1497
1498         intermediate->hpll.plane = max(optimal->hpll.plane,
1499                                        active->hpll.plane);
1500         intermediate->hpll.cursor = max(optimal->hpll.cursor,
1501                                         active->hpll.cursor);
1502         intermediate->hpll.fbc = max(optimal->hpll.fbc,
1503                                      active->hpll.fbc);
1504
1505         drm_WARN_ON(&dev_priv->drm,
1506                     (intermediate->sr.plane >
1507                      g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_SR) ||
1508                      intermediate->sr.cursor >
1509                      g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_SR)) &&
1510                     intermediate->cxsr);
1511         drm_WARN_ON(&dev_priv->drm,
1512                     (intermediate->sr.plane >
1513                      g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_HPLL) ||
1514                      intermediate->sr.cursor >
1515                      g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_HPLL)) &&
1516                     intermediate->hpll_en);
1517
1518         drm_WARN_ON(&dev_priv->drm,
1519                     intermediate->sr.fbc > g4x_fbc_fifo_size(1) &&
1520                     intermediate->fbc_en && intermediate->cxsr);
1521         drm_WARN_ON(&dev_priv->drm,
1522                     intermediate->hpll.fbc > g4x_fbc_fifo_size(2) &&
1523                     intermediate->fbc_en && intermediate->hpll_en);
1524
1525 out:
1526         /*
1527          * If our intermediate WM are identical to the final WM, then we can
1528          * omit the post-vblank programming; only update if it's different.
1529          */
1530         if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)
1531                 new_crtc_state->wm.need_postvbl_update = true;
1532
1533         return 0;
1534 }
1535
1536 static void g4x_merge_wm(struct drm_i915_private *dev_priv,
1537                          struct g4x_wm_values *wm)
1538 {
1539         struct intel_crtc *crtc;
1540         int num_active_pipes = 0;
1541
1542         wm->cxsr = true;
1543         wm->hpll_en = true;
1544         wm->fbc_en = true;
1545
1546         for_each_intel_crtc(&dev_priv->drm, crtc) {
1547                 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
1548
1549                 if (!crtc->active)
1550                         continue;
1551
1552                 if (!wm_state->cxsr)
1553                         wm->cxsr = false;
1554                 if (!wm_state->hpll_en)
1555                         wm->hpll_en = false;
1556                 if (!wm_state->fbc_en)
1557                         wm->fbc_en = false;
1558
1559                 num_active_pipes++;
1560         }
1561
1562         if (num_active_pipes != 1) {
1563                 wm->cxsr = false;
1564                 wm->hpll_en = false;
1565                 wm->fbc_en = false;
1566         }
1567
1568         for_each_intel_crtc(&dev_priv->drm, crtc) {
1569                 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
1570                 enum pipe pipe = crtc->pipe;
1571
1572                 wm->pipe[pipe] = wm_state->wm;
1573                 if (crtc->active && wm->cxsr)
1574                         wm->sr = wm_state->sr;
1575                 if (crtc->active && wm->hpll_en)
1576                         wm->hpll = wm_state->hpll;
1577         }
1578 }
1579
1580 static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
1581 {
1582         struct g4x_wm_values *old_wm = &dev_priv->wm.g4x;
1583         struct g4x_wm_values new_wm = {};
1584
1585         g4x_merge_wm(dev_priv, &new_wm);
1586
1587         if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0)
1588                 return;
1589
1590         if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
1591                 _intel_set_memory_cxsr(dev_priv, false);
1592
1593         g4x_write_wm_values(dev_priv, &new_wm);
1594
1595         if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
1596                 _intel_set_memory_cxsr(dev_priv, true);
1597
1598         *old_wm = new_wm;
1599 }
1600
1601 static void g4x_initial_watermarks(struct intel_atomic_state *state,
1602                                    struct intel_crtc *crtc)
1603 {
1604         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1605         const struct intel_crtc_state *crtc_state =
1606                 intel_atomic_get_new_crtc_state(state, crtc);
1607
1608         mutex_lock(&dev_priv->wm.wm_mutex);
1609         crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
1610         g4x_program_watermarks(dev_priv);
1611         mutex_unlock(&dev_priv->wm.wm_mutex);
1612 }
1613
1614 static void g4x_optimize_watermarks(struct intel_atomic_state *state,
1615                                     struct intel_crtc *crtc)
1616 {
1617         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1618         const struct intel_crtc_state *crtc_state =
1619                 intel_atomic_get_new_crtc_state(state, crtc);
1620
1621         if (!crtc_state->wm.need_postvbl_update)
1622                 return;
1623
1624         mutex_lock(&dev_priv->wm.wm_mutex);
1625         crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
1626         g4x_program_watermarks(dev_priv);
1627         mutex_unlock(&dev_priv->wm.wm_mutex);
1628 }
1629
1630 /* latency must be in 0.1us units. */
1631 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
1632                                    unsigned int htotal,
1633                                    unsigned int width,
1634                                    unsigned int cpp,
1635                                    unsigned int latency)
1636 {
1637         unsigned int ret;
1638
1639         ret = intel_wm_method2(pixel_rate, htotal,
1640                                width, cpp, latency);
1641         ret = DIV_ROUND_UP(ret, 64);
1642
1643         return ret;
1644 }
1645
1646 static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
1647 {
1648         /* all latencies in usec */
1649         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
1650
1651         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
1652
1653         if (IS_CHERRYVIEW(dev_priv)) {
1654                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
1655                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
1656
1657                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
1658         }
1659 }
1660
1661 static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
1662                                 const struct intel_plane_state *plane_state,
1663                                 int level)
1664 {
1665         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1666         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1667         const struct drm_display_mode *pipe_mode =
1668                 &crtc_state->hw.pipe_mode;
1669         unsigned int clock, htotal, cpp, width, wm;
1670
1671         if (dev_priv->wm.pri_latency[level] == 0)
1672                 return USHRT_MAX;
1673
1674         if (!intel_wm_plane_visible(crtc_state, plane_state))
1675                 return 0;
1676
1677         cpp = plane_state->hw.fb->format->cpp[0];
1678         clock = pipe_mode->crtc_clock;
1679         htotal = pipe_mode->crtc_htotal;
1680         width = crtc_state->pipe_src_w;
1681
1682         if (plane->id == PLANE_CURSOR) {
1683                 /*
1684                  * FIXME the formula gives values that are
1685                  * too big for the cursor FIFO, and hence we
1686                  * would never be able to use cursors. For
1687                  * now just hardcode the watermark.
1688                  */
1689                 wm = 63;
1690         } else {
1691                 wm = vlv_wm_method2(clock, htotal, width, cpp,
1692                                     dev_priv->wm.pri_latency[level] * 10);
1693         }
1694
1695         return min_t(unsigned int, wm, USHRT_MAX);
1696 }
1697
1698 static bool vlv_need_sprite0_fifo_workaround(unsigned int active_planes)
1699 {
1700         return (active_planes & (BIT(PLANE_SPRITE0) |
1701                                  BIT(PLANE_SPRITE1))) == BIT(PLANE_SPRITE1);
1702 }
1703
1704 static int vlv_compute_fifo(struct intel_crtc_state *crtc_state)
1705 {
1706         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1707         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1708         const struct g4x_pipe_wm *raw =
1709                 &crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2];
1710         struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
1711         unsigned int active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);
1712         int num_active_planes = hweight8(active_planes);
1713         const int fifo_size = 511;
1714         int fifo_extra, fifo_left = fifo_size;
1715         int sprite0_fifo_extra = 0;
1716         unsigned int total_rate;
1717         enum plane_id plane_id;
1718
1719         /*
1720          * When enabling sprite0 after sprite1 has already been enabled
1721          * we tend to get an underrun unless sprite0 already has some
1722          * FIFO space allcoated. Hence we always allocate at least one
1723          * cacheline for sprite0 whenever sprite1 is enabled.
1724          *
1725          * All other plane enable sequences appear immune to this problem.
1726          */
1727         if (vlv_need_sprite0_fifo_workaround(active_planes))
1728                 sprite0_fifo_extra = 1;
1729
1730         total_rate = raw->plane[PLANE_PRIMARY] +
1731                 raw->plane[PLANE_SPRITE0] +
1732                 raw->plane[PLANE_SPRITE1] +
1733                 sprite0_fifo_extra;
1734
1735         if (total_rate > fifo_size)
1736                 return -EINVAL;
1737
1738         if (total_rate == 0)
1739                 total_rate = 1;
1740
1741         for_each_plane_id_on_crtc(crtc, plane_id) {
1742                 unsigned int rate;
1743
1744                 if ((active_planes & BIT(plane_id)) == 0) {
1745                         fifo_state->plane[plane_id] = 0;
1746                         continue;
1747                 }
1748
1749                 rate = raw->plane[plane_id];
1750                 fifo_state->plane[plane_id] = fifo_size * rate / total_rate;
1751                 fifo_left -= fifo_state->plane[plane_id];
1752         }
1753
1754         fifo_state->plane[PLANE_SPRITE0] += sprite0_fifo_extra;
1755         fifo_left -= sprite0_fifo_extra;
1756
1757         fifo_state->plane[PLANE_CURSOR] = 63;
1758
1759         fifo_extra = DIV_ROUND_UP(fifo_left, num_active_planes ?: 1);
1760
1761         /* spread the remainder evenly */
1762         for_each_plane_id_on_crtc(crtc, plane_id) {
1763                 int plane_extra;
1764
1765                 if (fifo_left == 0)
1766                         break;
1767
1768                 if ((active_planes & BIT(plane_id)) == 0)
1769                         continue;
1770
1771                 plane_extra = min(fifo_extra, fifo_left);
1772                 fifo_state->plane[plane_id] += plane_extra;
1773                 fifo_left -= plane_extra;
1774         }
1775
1776         drm_WARN_ON(&dev_priv->drm, active_planes != 0 && fifo_left != 0);
1777
1778         /* give it all to the first plane if none are active */
1779         if (active_planes == 0) {
1780                 drm_WARN_ON(&dev_priv->drm, fifo_left != fifo_size);
1781                 fifo_state->plane[PLANE_PRIMARY] = fifo_left;
1782         }
1783
1784         return 0;
1785 }
1786
1787 /* mark all levels starting from 'level' as invalid */
1788 static void vlv_invalidate_wms(struct intel_crtc *crtc,
1789                                struct vlv_wm_state *wm_state, int level)
1790 {
1791         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1792
1793         for (; level < intel_wm_num_levels(dev_priv); level++) {
1794                 enum plane_id plane_id;
1795
1796                 for_each_plane_id_on_crtc(crtc, plane_id)
1797                         wm_state->wm[level].plane[plane_id] = USHRT_MAX;
1798
1799                 wm_state->sr[level].cursor = USHRT_MAX;
1800                 wm_state->sr[level].plane = USHRT_MAX;
1801         }
1802 }
1803
1804 static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size)
1805 {
1806         if (wm > fifo_size)
1807                 return USHRT_MAX;
1808         else
1809                 return fifo_size - wm;
1810 }
1811
1812 /*
1813  * Starting from 'level' set all higher
1814  * levels to 'value' in the "raw" watermarks.
1815  */
1816 static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
1817                                  int level, enum plane_id plane_id, u16 value)
1818 {
1819         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1820         int num_levels = intel_wm_num_levels(dev_priv);
1821         bool dirty = false;
1822
1823         for (; level < num_levels; level++) {
1824                 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1825
1826                 dirty |= raw->plane[plane_id] != value;
1827                 raw->plane[plane_id] = value;
1828         }
1829
1830         return dirty;
1831 }
1832
1833 static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
1834                                      const struct intel_plane_state *plane_state)
1835 {
1836         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1837         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1838         enum plane_id plane_id = plane->id;
1839         int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
1840         int level;
1841         bool dirty = false;
1842
1843         if (!intel_wm_plane_visible(crtc_state, plane_state)) {
1844                 dirty |= vlv_raw_plane_wm_set(crtc_state, 0, plane_id, 0);
1845                 goto out;
1846         }
1847
1848         for (level = 0; level < num_levels; level++) {
1849                 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1850                 int wm = vlv_compute_wm_level(crtc_state, plane_state, level);
1851                 int max_wm = plane_id == PLANE_CURSOR ? 63 : 511;
1852
1853                 if (wm > max_wm)
1854                         break;
1855
1856                 dirty |= raw->plane[plane_id] != wm;
1857                 raw->plane[plane_id] = wm;
1858         }
1859
1860         /* mark all higher levels as invalid */
1861         dirty |= vlv_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
1862
1863 out:
1864         if (dirty)
1865                 drm_dbg_kms(&dev_priv->drm,
1866                             "%s watermarks: PM2=%d, PM5=%d, DDR DVFS=%d\n",
1867                             plane->base.name,
1868                             crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id],
1869                             crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id],
1870                             crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]);
1871
1872         return dirty;
1873 }
1874
1875 static bool vlv_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
1876                                       enum plane_id plane_id, int level)
1877 {
1878         const struct g4x_pipe_wm *raw =
1879                 &crtc_state->wm.vlv.raw[level];
1880         const struct vlv_fifo_state *fifo_state =
1881                 &crtc_state->wm.vlv.fifo_state;
1882
1883         return raw->plane[plane_id] <= fifo_state->plane[plane_id];
1884 }
1885
1886 static bool vlv_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state, int level)
1887 {
1888         return vlv_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&
1889                 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) &&
1890                 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE1, level) &&
1891                 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level);
1892 }
1893
1894 static int vlv_compute_pipe_wm(struct intel_atomic_state *state,
1895                                struct intel_crtc *crtc)
1896 {
1897         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1898         struct intel_crtc_state *crtc_state =
1899                 intel_atomic_get_new_crtc_state(state, crtc);
1900         struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
1901         const struct vlv_fifo_state *fifo_state =
1902                 &crtc_state->wm.vlv.fifo_state;
1903         int num_active_planes = hweight8(crtc_state->active_planes &
1904                                          ~BIT(PLANE_CURSOR));
1905         bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->uapi);
1906         const struct intel_plane_state *old_plane_state;
1907         const struct intel_plane_state *new_plane_state;
1908         struct intel_plane *plane;
1909         enum plane_id plane_id;
1910         int level, ret, i;
1911         unsigned int dirty = 0;
1912
1913         for_each_oldnew_intel_plane_in_state(state, plane,
1914                                              old_plane_state,
1915                                              new_plane_state, i) {
1916                 if (new_plane_state->hw.crtc != &crtc->base &&
1917                     old_plane_state->hw.crtc != &crtc->base)
1918                         continue;
1919
1920                 if (vlv_raw_plane_wm_compute(crtc_state, new_plane_state))
1921                         dirty |= BIT(plane->id);
1922         }
1923
1924         /*
1925          * DSPARB registers may have been reset due to the
1926          * power well being turned off. Make sure we restore
1927          * them to a consistent state even if no primary/sprite
1928          * planes are initially active.
1929          */
1930         if (needs_modeset)
1931                 crtc_state->fifo_changed = true;
1932
1933         if (!dirty)
1934                 return 0;
1935
1936         /* cursor changes don't warrant a FIFO recompute */
1937         if (dirty & ~BIT(PLANE_CURSOR)) {
1938                 const struct intel_crtc_state *old_crtc_state =
1939                         intel_atomic_get_old_crtc_state(state, crtc);
1940                 const struct vlv_fifo_state *old_fifo_state =
1941                         &old_crtc_state->wm.vlv.fifo_state;
1942
1943                 ret = vlv_compute_fifo(crtc_state);
1944                 if (ret)
1945                         return ret;
1946
1947                 if (needs_modeset ||
1948                     memcmp(old_fifo_state, fifo_state,
1949                            sizeof(*fifo_state)) != 0)
1950                         crtc_state->fifo_changed = true;
1951         }
1952
1953         /* initially allow all levels */
1954         wm_state->num_levels = intel_wm_num_levels(dev_priv);
1955         /*
1956          * Note that enabling cxsr with no primary/sprite planes
1957          * enabled can wedge the pipe. Hence we only allow cxsr
1958          * with exactly one enabled primary/sprite plane.
1959          */
1960         wm_state->cxsr = crtc->pipe != PIPE_C && num_active_planes == 1;
1961
1962         for (level = 0; level < wm_state->num_levels; level++) {
1963                 const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1964                 const int sr_fifo_size = INTEL_NUM_PIPES(dev_priv) * 512 - 1;
1965
1966                 if (!vlv_raw_crtc_wm_is_valid(crtc_state, level))
1967                         break;
1968
1969                 for_each_plane_id_on_crtc(crtc, plane_id) {
1970                         wm_state->wm[level].plane[plane_id] =
1971                                 vlv_invert_wm_value(raw->plane[plane_id],
1972                                                     fifo_state->plane[plane_id]);
1973                 }
1974
1975                 wm_state->sr[level].plane =
1976                         vlv_invert_wm_value(max3(raw->plane[PLANE_PRIMARY],
1977                                                  raw->plane[PLANE_SPRITE0],
1978                                                  raw->plane[PLANE_SPRITE1]),
1979                                             sr_fifo_size);
1980
1981                 wm_state->sr[level].cursor =
1982                         vlv_invert_wm_value(raw->plane[PLANE_CURSOR],
1983                                             63);
1984         }
1985
1986         if (level == 0)
1987                 return -EINVAL;
1988
1989         /* limit to only levels we can actually handle */
1990         wm_state->num_levels = level;
1991
1992         /* invalidate the higher levels */
1993         vlv_invalidate_wms(crtc, wm_state, level);
1994
1995         return 0;
1996 }
1997
1998 #define VLV_FIFO(plane, value) \
1999         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
2000
2001 static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
2002                                    struct intel_crtc *crtc)
2003 {
2004         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2005         struct intel_uncore *uncore = &dev_priv->uncore;
2006         const struct intel_crtc_state *crtc_state =
2007                 intel_atomic_get_new_crtc_state(state, crtc);
2008         const struct vlv_fifo_state *fifo_state =
2009                 &crtc_state->wm.vlv.fifo_state;
2010         int sprite0_start, sprite1_start, fifo_size;
2011         u32 dsparb, dsparb2, dsparb3;
2012
2013         if (!crtc_state->fifo_changed)
2014                 return;
2015
2016         sprite0_start = fifo_state->plane[PLANE_PRIMARY];
2017         sprite1_start = fifo_state->plane[PLANE_SPRITE0] + sprite0_start;
2018         fifo_size = fifo_state->plane[PLANE_SPRITE1] + sprite1_start;
2019
2020         drm_WARN_ON(&dev_priv->drm, fifo_state->plane[PLANE_CURSOR] != 63);
2021         drm_WARN_ON(&dev_priv->drm, fifo_size != 511);
2022
2023         trace_vlv_fifo_size(crtc, sprite0_start, sprite1_start, fifo_size);
2024
2025         /*
2026          * uncore.lock serves a double purpose here. It allows us to
2027          * use the less expensive I915_{READ,WRITE}_FW() functions, and
2028          * it protects the DSPARB registers from getting clobbered by
2029          * parallel updates from multiple pipes.
2030          *
2031          * intel_pipe_update_start() has already disabled interrupts
2032          * for us, so a plain spin_lock() is sufficient here.
2033          */
2034         spin_lock(&uncore->lock);
2035
2036         switch (crtc->pipe) {
2037         case PIPE_A:
2038                 dsparb = intel_uncore_read_fw(uncore, DSPARB);
2039                 dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
2040
2041                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
2042                             VLV_FIFO(SPRITEB, 0xff));
2043                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
2044                            VLV_FIFO(SPRITEB, sprite1_start));
2045
2046                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
2047                              VLV_FIFO(SPRITEB_HI, 0x1));
2048                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
2049                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
2050
2051                 intel_uncore_write_fw(uncore, DSPARB, dsparb);
2052                 intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
2053                 break;
2054         case PIPE_B:
2055                 dsparb = intel_uncore_read_fw(uncore, DSPARB);
2056                 dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
2057
2058                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
2059                             VLV_FIFO(SPRITED, 0xff));
2060                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
2061                            VLV_FIFO(SPRITED, sprite1_start));
2062
2063                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
2064                              VLV_FIFO(SPRITED_HI, 0xff));
2065                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
2066                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
2067
2068                 intel_uncore_write_fw(uncore, DSPARB, dsparb);
2069                 intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
2070                 break;
2071         case PIPE_C:
2072                 dsparb3 = intel_uncore_read_fw(uncore, DSPARB3);
2073                 dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
2074
2075                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
2076                              VLV_FIFO(SPRITEF, 0xff));
2077                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
2078                             VLV_FIFO(SPRITEF, sprite1_start));
2079
2080                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
2081                              VLV_FIFO(SPRITEF_HI, 0xff));
2082                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
2083                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
2084
2085                 intel_uncore_write_fw(uncore, DSPARB3, dsparb3);
2086                 intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
2087                 break;
2088         default:
2089                 break;
2090         }
2091
2092         intel_uncore_posting_read_fw(uncore, DSPARB);
2093
2094         spin_unlock(&uncore->lock);
2095 }
2096
2097 #undef VLV_FIFO
2098
2099 static int vlv_compute_intermediate_wm(struct intel_atomic_state *state,
2100                                        struct intel_crtc *crtc)
2101 {
2102         struct intel_crtc_state *new_crtc_state =
2103                 intel_atomic_get_new_crtc_state(state, crtc);
2104         const struct intel_crtc_state *old_crtc_state =
2105                 intel_atomic_get_old_crtc_state(state, crtc);
2106         struct vlv_wm_state *intermediate = &new_crtc_state->wm.vlv.intermediate;
2107         const struct vlv_wm_state *optimal = &new_crtc_state->wm.vlv.optimal;
2108         const struct vlv_wm_state *active = &old_crtc_state->wm.vlv.optimal;
2109         int level;
2110
2111         if (!new_crtc_state->hw.active ||
2112             drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi)) {
2113                 *intermediate = *optimal;
2114
2115                 intermediate->cxsr = false;
2116                 goto out;
2117         }
2118
2119         intermediate->num_levels = min(optimal->num_levels, active->num_levels);
2120         intermediate->cxsr = optimal->cxsr && active->cxsr &&
2121                 !new_crtc_state->disable_cxsr;
2122
2123         for (level = 0; level < intermediate->num_levels; level++) {
2124                 enum plane_id plane_id;
2125
2126                 for_each_plane_id_on_crtc(crtc, plane_id) {
2127                         intermediate->wm[level].plane[plane_id] =
2128                                 min(optimal->wm[level].plane[plane_id],
2129                                     active->wm[level].plane[plane_id]);
2130                 }
2131
2132                 intermediate->sr[level].plane = min(optimal->sr[level].plane,
2133                                                     active->sr[level].plane);
2134                 intermediate->sr[level].cursor = min(optimal->sr[level].cursor,
2135                                                      active->sr[level].cursor);
2136         }
2137
2138         vlv_invalidate_wms(crtc, intermediate, level);
2139
2140 out:
2141         /*
2142          * If our intermediate WM are identical to the final WM, then we can
2143          * omit the post-vblank programming; only update if it's different.
2144          */
2145         if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)
2146                 new_crtc_state->wm.need_postvbl_update = true;
2147
2148         return 0;
2149 }
2150
2151 static void vlv_merge_wm(struct drm_i915_private *dev_priv,
2152                          struct vlv_wm_values *wm)
2153 {
2154         struct intel_crtc *crtc;
2155         int num_active_pipes = 0;
2156
2157         wm->level = dev_priv->wm.max_level;
2158         wm->cxsr = true;
2159
2160         for_each_intel_crtc(&dev_priv->drm, crtc) {
2161                 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
2162
2163                 if (!crtc->active)
2164                         continue;
2165
2166                 if (!wm_state->cxsr)
2167                         wm->cxsr = false;
2168
2169                 num_active_pipes++;
2170                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
2171         }
2172
2173         if (num_active_pipes != 1)
2174                 wm->cxsr = false;
2175
2176         if (num_active_pipes > 1)
2177                 wm->level = VLV_WM_LEVEL_PM2;
2178
2179         for_each_intel_crtc(&dev_priv->drm, crtc) {
2180                 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
2181                 enum pipe pipe = crtc->pipe;
2182
2183                 wm->pipe[pipe] = wm_state->wm[wm->level];
2184                 if (crtc->active && wm->cxsr)
2185                         wm->sr = wm_state->sr[wm->level];
2186
2187                 wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2;
2188                 wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2;
2189                 wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2;
2190                 wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2;
2191         }
2192 }
2193
2194 static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
2195 {
2196         struct vlv_wm_values *old_wm = &dev_priv->wm.vlv;
2197         struct vlv_wm_values new_wm = {};
2198
2199         vlv_merge_wm(dev_priv, &new_wm);
2200
2201         if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0)
2202                 return;
2203
2204         if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
2205                 chv_set_memory_dvfs(dev_priv, false);
2206
2207         if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
2208                 chv_set_memory_pm5(dev_priv, false);
2209
2210         if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
2211                 _intel_set_memory_cxsr(dev_priv, false);
2212
2213         vlv_write_wm_values(dev_priv, &new_wm);
2214
2215         if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
2216                 _intel_set_memory_cxsr(dev_priv, true);
2217
2218         if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
2219                 chv_set_memory_pm5(dev_priv, true);
2220
2221         if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
2222                 chv_set_memory_dvfs(dev_priv, true);
2223
2224         *old_wm = new_wm;
2225 }
2226
2227 static void vlv_initial_watermarks(struct intel_atomic_state *state,
2228                                    struct intel_crtc *crtc)
2229 {
2230         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2231         const struct intel_crtc_state *crtc_state =
2232                 intel_atomic_get_new_crtc_state(state, crtc);
2233
2234         mutex_lock(&dev_priv->wm.wm_mutex);
2235         crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
2236         vlv_program_watermarks(dev_priv);
2237         mutex_unlock(&dev_priv->wm.wm_mutex);
2238 }
2239
2240 static void vlv_optimize_watermarks(struct intel_atomic_state *state,
2241                                     struct intel_crtc *crtc)
2242 {
2243         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2244         const struct intel_crtc_state *crtc_state =
2245                 intel_atomic_get_new_crtc_state(state, crtc);
2246
2247         if (!crtc_state->wm.need_postvbl_update)
2248                 return;
2249
2250         mutex_lock(&dev_priv->wm.wm_mutex);
2251         crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
2252         vlv_program_watermarks(dev_priv);
2253         mutex_unlock(&dev_priv->wm.wm_mutex);
2254 }
2255
2256 static void i965_update_wm(struct intel_crtc *unused_crtc)
2257 {
2258         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2259         struct intel_crtc *crtc;
2260         int srwm = 1;
2261         int cursor_sr = 16;
2262         bool cxsr_enabled;
2263
2264         /* Calc sr entries for one plane configs */
2265         crtc = single_enabled_crtc(dev_priv);
2266         if (crtc) {
2267                 /* self-refresh has much higher latency */
2268                 static const int sr_latency_ns = 12000;
2269                 const struct drm_display_mode *pipe_mode =
2270                         &crtc->config->hw.pipe_mode;
2271                 const struct drm_framebuffer *fb =
2272                         crtc->base.primary->state->fb;
2273                 int clock = pipe_mode->crtc_clock;
2274                 int htotal = pipe_mode->crtc_htotal;
2275                 int hdisplay = crtc->config->pipe_src_w;
2276                 int cpp = fb->format->cpp[0];
2277                 int entries;
2278
2279                 entries = intel_wm_method2(clock, htotal,
2280                                            hdisplay, cpp, sr_latency_ns / 100);
2281                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
2282                 srwm = I965_FIFO_SIZE - entries;
2283                 if (srwm < 0)
2284                         srwm = 1;
2285                 srwm &= 0x1ff;
2286                 drm_dbg_kms(&dev_priv->drm,
2287                             "self-refresh entries: %d, wm: %d\n",
2288                             entries, srwm);
2289
2290                 entries = intel_wm_method2(clock, htotal,
2291                                            crtc->base.cursor->state->crtc_w, 4,
2292                                            sr_latency_ns / 100);
2293                 entries = DIV_ROUND_UP(entries,
2294                                        i965_cursor_wm_info.cacheline_size) +
2295                         i965_cursor_wm_info.guard_size;
2296
2297                 cursor_sr = i965_cursor_wm_info.fifo_size - entries;
2298                 if (cursor_sr > i965_cursor_wm_info.max_wm)
2299                         cursor_sr = i965_cursor_wm_info.max_wm;
2300
2301                 drm_dbg_kms(&dev_priv->drm,
2302                             "self-refresh watermark: display plane %d "
2303                             "cursor %d\n", srwm, cursor_sr);
2304
2305                 cxsr_enabled = true;
2306         } else {
2307                 cxsr_enabled = false;
2308                 /* Turn off self refresh if both pipes are enabled */
2309                 intel_set_memory_cxsr(dev_priv, false);
2310         }
2311
2312         drm_dbg_kms(&dev_priv->drm,
2313                     "Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2314                     srwm);
2315
2316         /* 965 has limitations... */
2317         intel_uncore_write(&dev_priv->uncore, DSPFW1, FW_WM(srwm, SR) |
2318                    FW_WM(8, CURSORB) |
2319                    FW_WM(8, PLANEB) |
2320                    FW_WM(8, PLANEA));
2321         intel_uncore_write(&dev_priv->uncore, DSPFW2, FW_WM(8, CURSORA) |
2322                    FW_WM(8, PLANEC_OLD));
2323         /* update cursor SR watermark */
2324         intel_uncore_write(&dev_priv->uncore, DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
2325
2326         if (cxsr_enabled)
2327                 intel_set_memory_cxsr(dev_priv, true);
2328 }
2329
2330 #undef FW_WM
2331
2332 static void i9xx_update_wm(struct intel_crtc *unused_crtc)
2333 {
2334         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2335         const struct intel_watermark_params *wm_info;
2336         u32 fwater_lo;
2337         u32 fwater_hi;
2338         int cwm, srwm = 1;
2339         int fifo_size;
2340         int planea_wm, planeb_wm;
2341         struct intel_crtc *crtc, *enabled = NULL;
2342
2343         if (IS_I945GM(dev_priv))
2344                 wm_info = &i945_wm_info;
2345         else if (DISPLAY_VER(dev_priv) != 2)
2346                 wm_info = &i915_wm_info;
2347         else
2348                 wm_info = &i830_a_wm_info;
2349
2350         fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_A);
2351         crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
2352         if (intel_crtc_active(crtc)) {
2353                 const struct drm_display_mode *pipe_mode =
2354                         &crtc->config->hw.pipe_mode;
2355                 const struct drm_framebuffer *fb =
2356                         crtc->base.primary->state->fb;
2357                 int cpp;
2358
2359                 if (DISPLAY_VER(dev_priv) == 2)
2360                         cpp = 4;
2361                 else
2362                         cpp = fb->format->cpp[0];
2363
2364                 planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
2365                                                wm_info, fifo_size, cpp,
2366                                                pessimal_latency_ns);
2367                 enabled = crtc;
2368         } else {
2369                 planea_wm = fifo_size - wm_info->guard_size;
2370                 if (planea_wm > (long)wm_info->max_wm)
2371                         planea_wm = wm_info->max_wm;
2372         }
2373
2374         if (DISPLAY_VER(dev_priv) == 2)
2375                 wm_info = &i830_bc_wm_info;
2376
2377         fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);
2378         crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
2379         if (intel_crtc_active(crtc)) {
2380                 const struct drm_display_mode *pipe_mode =
2381                         &crtc->config->hw.pipe_mode;
2382                 const struct drm_framebuffer *fb =
2383                         crtc->base.primary->state->fb;
2384                 int cpp;
2385
2386                 if (DISPLAY_VER(dev_priv) == 2)
2387                         cpp = 4;
2388                 else
2389                         cpp = fb->format->cpp[0];
2390
2391                 planeb_wm = intel_calculate_wm(pipe_mode->crtc_clock,
2392                                                wm_info, fifo_size, cpp,
2393                                                pessimal_latency_ns);
2394                 if (enabled == NULL)
2395                         enabled = crtc;
2396                 else
2397                         enabled = NULL;
2398         } else {
2399                 planeb_wm = fifo_size - wm_info->guard_size;
2400                 if (planeb_wm > (long)wm_info->max_wm)
2401                         planeb_wm = wm_info->max_wm;
2402         }
2403
2404         drm_dbg_kms(&dev_priv->drm,
2405                     "FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2406
2407         if (IS_I915GM(dev_priv) && enabled) {
2408                 struct drm_i915_gem_object *obj;
2409
2410                 obj = intel_fb_obj(enabled->base.primary->state->fb);
2411
2412                 /* self-refresh seems busted with untiled */
2413                 if (!i915_gem_object_is_tiled(obj))
2414                         enabled = NULL;
2415         }
2416
2417         /*
2418          * Overlay gets an aggressive default since video jitter is bad.
2419          */
2420         cwm = 2;
2421
2422         /* Play safe and disable self-refresh before adjusting watermarks. */
2423         intel_set_memory_cxsr(dev_priv, false);
2424
2425         /* Calc sr entries for one plane configs */
2426         if (HAS_FW_BLC(dev_priv) && enabled) {
2427                 /* self-refresh has much higher latency */
2428                 static const int sr_latency_ns = 6000;
2429                 const struct drm_display_mode *pipe_mode =
2430                         &enabled->config->hw.pipe_mode;
2431                 const struct drm_framebuffer *fb =
2432                         enabled->base.primary->state->fb;
2433                 int clock = pipe_mode->crtc_clock;
2434                 int htotal = pipe_mode->crtc_htotal;
2435                 int hdisplay = enabled->config->pipe_src_w;
2436                 int cpp;
2437                 int entries;
2438
2439                 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
2440                         cpp = 4;
2441                 else
2442                         cpp = fb->format->cpp[0];
2443
2444                 entries = intel_wm_method2(clock, htotal, hdisplay, cpp,
2445                                            sr_latency_ns / 100);
2446                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
2447                 drm_dbg_kms(&dev_priv->drm,
2448                             "self-refresh entries: %d\n", entries);
2449                 srwm = wm_info->fifo_size - entries;
2450                 if (srwm < 0)
2451                         srwm = 1;
2452
2453                 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
2454                         intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF,
2455                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
2456                 else
2457                         intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, srwm & 0x3f);
2458         }
2459
2460         drm_dbg_kms(&dev_priv->drm,
2461                     "Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2462                      planea_wm, planeb_wm, cwm, srwm);
2463
2464         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2465         fwater_hi = (cwm & 0x1f);
2466
2467         /* Set request length to 8 cachelines per fetch */
2468         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2469         fwater_hi = fwater_hi | (1 << 8);
2470
2471         intel_uncore_write(&dev_priv->uncore, FW_BLC, fwater_lo);
2472         intel_uncore_write(&dev_priv->uncore, FW_BLC2, fwater_hi);
2473
2474         if (enabled)
2475                 intel_set_memory_cxsr(dev_priv, true);
2476 }
2477
2478 static void i845_update_wm(struct intel_crtc *unused_crtc)
2479 {
2480         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2481         struct intel_crtc *crtc;
2482         const struct drm_display_mode *pipe_mode;
2483         u32 fwater_lo;
2484         int planea_wm;
2485
2486         crtc = single_enabled_crtc(dev_priv);
2487         if (crtc == NULL)
2488                 return;
2489
2490         pipe_mode = &crtc->config->hw.pipe_mode;
2491         planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
2492                                        &i845_wm_info,
2493                                        dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
2494                                        4, pessimal_latency_ns);
2495         fwater_lo = intel_uncore_read(&dev_priv->uncore, FW_BLC) & ~0xfff;
2496         fwater_lo |= (3<<8) | planea_wm;
2497
2498         drm_dbg_kms(&dev_priv->drm,
2499                     "Setting FIFO watermarks - A: %d\n", planea_wm);
2500
2501         intel_uncore_write(&dev_priv->uncore, FW_BLC, fwater_lo);
2502 }
2503
2504 /* latency must be in 0.1us units. */
2505 static unsigned int ilk_wm_method1(unsigned int pixel_rate,
2506                                    unsigned int cpp,
2507                                    unsigned int latency)
2508 {
2509         unsigned int ret;
2510
2511         ret = intel_wm_method1(pixel_rate, cpp, latency);
2512         ret = DIV_ROUND_UP(ret, 64) + 2;
2513
2514         return ret;
2515 }
2516
2517 /* latency must be in 0.1us units. */
2518 static unsigned int ilk_wm_method2(unsigned int pixel_rate,
2519                                    unsigned int htotal,
2520                                    unsigned int width,
2521                                    unsigned int cpp,
2522                                    unsigned int latency)
2523 {
2524         unsigned int ret;
2525
2526         ret = intel_wm_method2(pixel_rate, htotal,
2527                                width, cpp, latency);
2528         ret = DIV_ROUND_UP(ret, 64) + 2;
2529
2530         return ret;
2531 }
2532
2533 static u32 ilk_wm_fbc(u32 pri_val, u32 horiz_pixels, u8 cpp)
2534 {
2535         /*
2536          * Neither of these should be possible since this function shouldn't be
2537          * called if the CRTC is off or the plane is invisible.  But let's be
2538          * extra paranoid to avoid a potential divide-by-zero if we screw up
2539          * elsewhere in the driver.
2540          */
2541         if (WARN_ON(!cpp))
2542                 return 0;
2543         if (WARN_ON(!horiz_pixels))
2544                 return 0;
2545
2546         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
2547 }
2548
2549 struct ilk_wm_maximums {
2550         u16 pri;
2551         u16 spr;
2552         u16 cur;
2553         u16 fbc;
2554 };
2555
2556 /*
2557  * For both WM_PIPE and WM_LP.
2558  * mem_value must be in 0.1us units.
2559  */
2560 static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,
2561                               const struct intel_plane_state *plane_state,
2562                               u32 mem_value, bool is_lp)
2563 {
2564         u32 method1, method2;
2565         int cpp;
2566
2567         if (mem_value == 0)
2568                 return U32_MAX;
2569
2570         if (!intel_wm_plane_visible(crtc_state, plane_state))
2571                 return 0;
2572
2573         cpp = plane_state->hw.fb->format->cpp[0];
2574
2575         method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
2576
2577         if (!is_lp)
2578                 return method1;
2579
2580         method2 = ilk_wm_method2(crtc_state->pixel_rate,
2581                                  crtc_state->hw.pipe_mode.crtc_htotal,
2582                                  drm_rect_width(&plane_state->uapi.dst),
2583                                  cpp, mem_value);
2584
2585         return min(method1, method2);
2586 }
2587
2588 /*
2589  * For both WM_PIPE and WM_LP.
2590  * mem_value must be in 0.1us units.
2591  */
2592 static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state,
2593                               const struct intel_plane_state *plane_state,
2594                               u32 mem_value)
2595 {
2596         u32 method1, method2;
2597         int cpp;
2598
2599         if (mem_value == 0)
2600                 return U32_MAX;
2601
2602         if (!intel_wm_plane_visible(crtc_state, plane_state))
2603                 return 0;
2604
2605         cpp = plane_state->hw.fb->format->cpp[0];
2606
2607         method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
2608         method2 = ilk_wm_method2(crtc_state->pixel_rate,
2609                                  crtc_state->hw.pipe_mode.crtc_htotal,
2610                                  drm_rect_width(&plane_state->uapi.dst),
2611                                  cpp, mem_value);
2612         return min(method1, method2);
2613 }
2614
2615 /*
2616  * For both WM_PIPE and WM_LP.
2617  * mem_value must be in 0.1us units.
2618  */
2619 static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,
2620                               const struct intel_plane_state *plane_state,
2621                               u32 mem_value)
2622 {
2623         int cpp;
2624
2625         if (mem_value == 0)
2626                 return U32_MAX;
2627
2628         if (!intel_wm_plane_visible(crtc_state, plane_state))
2629                 return 0;
2630
2631         cpp = plane_state->hw.fb->format->cpp[0];
2632
2633         return ilk_wm_method2(crtc_state->pixel_rate,
2634                               crtc_state->hw.pipe_mode.crtc_htotal,
2635                               drm_rect_width(&plane_state->uapi.dst),
2636                               cpp, mem_value);
2637 }
2638
2639 /* Only for WM_LP. */
2640 static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
2641                               const struct intel_plane_state *plane_state,
2642                               u32 pri_val)
2643 {
2644         int cpp;
2645
2646         if (!intel_wm_plane_visible(crtc_state, plane_state))
2647                 return 0;
2648
2649         cpp = plane_state->hw.fb->format->cpp[0];
2650
2651         return ilk_wm_fbc(pri_val, drm_rect_width(&plane_state->uapi.dst),
2652                           cpp);
2653 }
2654
2655 static unsigned int
2656 ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
2657 {
2658         if (DISPLAY_VER(dev_priv) >= 8)
2659                 return 3072;
2660         else if (DISPLAY_VER(dev_priv) >= 7)
2661                 return 768;
2662         else
2663                 return 512;
2664 }
2665
2666 static unsigned int
2667 ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
2668                      int level, bool is_sprite)
2669 {
2670         if (DISPLAY_VER(dev_priv) >= 8)
2671                 /* BDW primary/sprite plane watermarks */
2672                 return level == 0 ? 255 : 2047;
2673         else if (DISPLAY_VER(dev_priv) >= 7)
2674                 /* IVB/HSW primary/sprite plane watermarks */
2675                 return level == 0 ? 127 : 1023;
2676         else if (!is_sprite)
2677                 /* ILK/SNB primary plane watermarks */
2678                 return level == 0 ? 127 : 511;
2679         else
2680                 /* ILK/SNB sprite plane watermarks */
2681                 return level == 0 ? 63 : 255;
2682 }
2683
2684 static unsigned int
2685 ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
2686 {
2687         if (DISPLAY_VER(dev_priv) >= 7)
2688                 return level == 0 ? 63 : 255;
2689         else
2690                 return level == 0 ? 31 : 63;
2691 }
2692
2693 static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
2694 {
2695         if (DISPLAY_VER(dev_priv) >= 8)
2696                 return 31;
2697         else
2698                 return 15;
2699 }
2700
2701 /* Calculate the maximum primary/sprite plane watermark */
2702 static unsigned int ilk_plane_wm_max(const struct drm_i915_private *dev_priv,
2703                                      int level,
2704                                      const struct intel_wm_config *config,
2705                                      enum intel_ddb_partitioning ddb_partitioning,
2706                                      bool is_sprite)
2707 {
2708         unsigned int fifo_size = ilk_display_fifo_size(dev_priv);
2709
2710         /* if sprites aren't enabled, sprites get nothing */
2711         if (is_sprite && !config->sprites_enabled)
2712                 return 0;
2713
2714         /* HSW allows LP1+ watermarks even with multiple pipes */
2715         if (level == 0 || config->num_pipes_active > 1) {
2716                 fifo_size /= INTEL_NUM_PIPES(dev_priv);
2717
2718                 /*
2719                  * For some reason the non self refresh
2720                  * FIFO size is only half of the self
2721                  * refresh FIFO size on ILK/SNB.
2722                  */
2723                 if (DISPLAY_VER(dev_priv) <= 6)
2724                         fifo_size /= 2;
2725         }
2726
2727         if (config->sprites_enabled) {
2728                 /* level 0 is always calculated with 1:1 split */
2729                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2730                         if (is_sprite)
2731                                 fifo_size *= 5;
2732                         fifo_size /= 6;
2733                 } else {
2734                         fifo_size /= 2;
2735                 }
2736         }
2737
2738         /* clamp to max that the registers can hold */
2739         return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite));
2740 }
2741
2742 /* Calculate the maximum cursor plane watermark */
2743 static unsigned int ilk_cursor_wm_max(const struct drm_i915_private *dev_priv,
2744                                       int level,
2745                                       const struct intel_wm_config *config)
2746 {
2747         /* HSW LP1+ watermarks w/ multiple pipes */
2748         if (level > 0 && config->num_pipes_active > 1)
2749                 return 64;
2750
2751         /* otherwise just report max that registers can hold */
2752         return ilk_cursor_wm_reg_max(dev_priv, level);
2753 }
2754
2755 static void ilk_compute_wm_maximums(const struct drm_i915_private *dev_priv,
2756                                     int level,
2757                                     const struct intel_wm_config *config,
2758                                     enum intel_ddb_partitioning ddb_partitioning,
2759                                     struct ilk_wm_maximums *max)
2760 {
2761         max->pri = ilk_plane_wm_max(dev_priv, level, config, ddb_partitioning, false);
2762         max->spr = ilk_plane_wm_max(dev_priv, level, config, ddb_partitioning, true);
2763         max->cur = ilk_cursor_wm_max(dev_priv, level, config);
2764         max->fbc = ilk_fbc_wm_reg_max(dev_priv);
2765 }
2766
2767 static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv,
2768                                         int level,
2769                                         struct ilk_wm_maximums *max)
2770 {
2771         max->pri = ilk_plane_wm_reg_max(dev_priv, level, false);
2772         max->spr = ilk_plane_wm_reg_max(dev_priv, level, true);
2773         max->cur = ilk_cursor_wm_reg_max(dev_priv, level);
2774         max->fbc = ilk_fbc_wm_reg_max(dev_priv);
2775 }
2776
2777 static bool ilk_validate_wm_level(int level,
2778                                   const struct ilk_wm_maximums *max,
2779                                   struct intel_wm_level *result)
2780 {
2781         bool ret;
2782
2783         /* already determined to be invalid? */
2784         if (!result->enable)
2785                 return false;
2786
2787         result->enable = result->pri_val <= max->pri &&
2788                          result->spr_val <= max->spr &&
2789                          result->cur_val <= max->cur;
2790
2791         ret = result->enable;
2792
2793         /*
2794          * HACK until we can pre-compute everything,
2795          * and thus fail gracefully if LP0 watermarks
2796          * are exceeded...
2797          */
2798         if (level == 0 && !result->enable) {
2799                 if (result->pri_val > max->pri)
2800                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2801                                       level, result->pri_val, max->pri);
2802                 if (result->spr_val > max->spr)
2803                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2804                                       level, result->spr_val, max->spr);
2805                 if (result->cur_val > max->cur)
2806                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2807                                       level, result->cur_val, max->cur);
2808
2809                 result->pri_val = min_t(u32, result->pri_val, max->pri);
2810                 result->spr_val = min_t(u32, result->spr_val, max->spr);
2811                 result->cur_val = min_t(u32, result->cur_val, max->cur);
2812                 result->enable = true;
2813         }
2814
2815         return ret;
2816 }
2817
2818 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2819                                  const struct intel_crtc *crtc,
2820                                  int level,
2821                                  struct intel_crtc_state *crtc_state,
2822                                  const struct intel_plane_state *pristate,
2823                                  const struct intel_plane_state *sprstate,
2824                                  const struct intel_plane_state *curstate,
2825                                  struct intel_wm_level *result)
2826 {
2827         u16 pri_latency = dev_priv->wm.pri_latency[level];
2828         u16 spr_latency = dev_priv->wm.spr_latency[level];
2829         u16 cur_latency = dev_priv->wm.cur_latency[level];
2830
2831         /* WM1+ latency values stored in 0.5us units */
2832         if (level > 0) {
2833                 pri_latency *= 5;
2834                 spr_latency *= 5;
2835                 cur_latency *= 5;
2836         }
2837
2838         if (pristate) {
2839                 result->pri_val = ilk_compute_pri_wm(crtc_state, pristate,
2840                                                      pri_latency, level);
2841                 result->fbc_val = ilk_compute_fbc_wm(crtc_state, pristate, result->pri_val);
2842         }
2843
2844         if (sprstate)
2845                 result->spr_val = ilk_compute_spr_wm(crtc_state, sprstate, spr_latency);
2846
2847         if (curstate)
2848                 result->cur_val = ilk_compute_cur_wm(crtc_state, curstate, cur_latency);
2849
2850         result->enable = true;
2851 }
2852
2853 static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
2854                                   u16 wm[8])
2855 {
2856         struct intel_uncore *uncore = &dev_priv->uncore;
2857
2858         if (DISPLAY_VER(dev_priv) >= 9) {
2859                 u32 val;
2860                 int ret, i;
2861                 int level, max_level = ilk_wm_max_level(dev_priv);
2862
2863                 /* read the first set of memory latencies[0:3] */
2864                 val = 0; /* data0 to be programmed to 0 for first set */
2865                 ret = sandybridge_pcode_read(dev_priv,
2866                                              GEN9_PCODE_READ_MEM_LATENCY,
2867                                              &val, NULL);
2868
2869                 if (ret) {
2870                         drm_err(&dev_priv->drm,
2871                                 "SKL Mailbox read error = %d\n", ret);
2872                         return;
2873                 }
2874
2875                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2876                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2877                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2878                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2879                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2880                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2881                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2882
2883                 /* read the second set of memory latencies[4:7] */
2884                 val = 1; /* data0 to be programmed to 1 for second set */
2885                 ret = sandybridge_pcode_read(dev_priv,
2886                                              GEN9_PCODE_READ_MEM_LATENCY,
2887                                              &val, NULL);
2888                 if (ret) {
2889                         drm_err(&dev_priv->drm,
2890                                 "SKL Mailbox read error = %d\n", ret);
2891                         return;
2892                 }
2893
2894                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2895                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2896                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2897                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2898                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2899                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2900                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2901
2902                 /*
2903                  * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2904                  * need to be disabled. We make sure to sanitize the values out
2905                  * of the punit to satisfy this requirement.
2906                  */
2907                 for (level = 1; level <= max_level; level++) {
2908                         if (wm[level] == 0) {
2909                                 for (i = level + 1; i <= max_level; i++)
2910                                         wm[i] = 0;
2911
2912                                 max_level = level - 1;
2913
2914                                 break;
2915                         }
2916                 }
2917
2918                 /*
2919                  * WaWmMemoryReadLatency
2920                  *
2921                  * punit doesn't take into account the read latency so we need
2922                  * to add proper adjustement to each valid level we retrieve
2923                  * from the punit when level 0 response data is 0us.
2924                  */
2925                 if (wm[0] == 0) {
2926                         u8 adjust = DISPLAY_VER(dev_priv) >= 12 ? 3 : 2;
2927
2928                         for (level = 0; level <= max_level; level++)
2929                                 wm[level] += adjust;
2930                 }
2931
2932                 /*
2933                  * WA Level-0 adjustment for 16GB DIMMs: SKL+
2934                  * If we could not get dimm info enable this WA to prevent from
2935                  * any underrun. If not able to get Dimm info assume 16GB dimm
2936                  * to avoid any underrun.
2937                  */
2938                 if (dev_priv->dram_info.wm_lv_0_adjust_needed)
2939                         wm[0] += 1;
2940         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2941                 u64 sskpd = intel_uncore_read64(uncore, MCH_SSKPD);
2942
2943                 wm[0] = (sskpd >> 56) & 0xFF;
2944                 if (wm[0] == 0)
2945                         wm[0] = sskpd & 0xF;
2946                 wm[1] = (sskpd >> 4) & 0xFF;
2947                 wm[2] = (sskpd >> 12) & 0xFF;
2948                 wm[3] = (sskpd >> 20) & 0x1FF;
2949                 wm[4] = (sskpd >> 32) & 0x1FF;
2950         } else if (DISPLAY_VER(dev_priv) >= 6) {
2951                 u32 sskpd = intel_uncore_read(uncore, MCH_SSKPD);
2952
2953                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2954                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2955                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2956                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2957         } else if (DISPLAY_VER(dev_priv) >= 5) {
2958                 u32 mltr = intel_uncore_read(uncore, MLTR_ILK);
2959
2960                 /* ILK primary LP0 latency is 700 ns */
2961                 wm[0] = 7;
2962                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2963                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2964         } else {
2965                 MISSING_CASE(INTEL_DEVID(dev_priv));
2966         }
2967 }
2968
2969 static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2970                                        u16 wm[5])
2971 {
2972         /* ILK sprite LP0 latency is 1300 ns */
2973         if (DISPLAY_VER(dev_priv) == 5)
2974                 wm[0] = 13;
2975 }
2976
2977 static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2978                                        u16 wm[5])
2979 {
2980         /* ILK cursor LP0 latency is 1300 ns */
2981         if (DISPLAY_VER(dev_priv) == 5)
2982                 wm[0] = 13;
2983 }
2984
2985 int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
2986 {
2987         /* how many WM levels are we expecting */
2988         if (HAS_HW_SAGV_WM(dev_priv))
2989                 return 5;
2990         else if (DISPLAY_VER(dev_priv) >= 9)
2991                 return 7;
2992         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2993                 return 4;
2994         else if (DISPLAY_VER(dev_priv) >= 6)
2995                 return 3;
2996         else
2997                 return 2;
2998 }
2999
3000 static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
3001                                    const char *name,
3002                                    const u16 wm[])
3003 {
3004         int level, max_level = ilk_wm_max_level(dev_priv);
3005
3006         for (level = 0; level <= max_level; level++) {
3007                 unsigned int latency = wm[level];
3008
3009                 if (latency == 0) {
3010                         drm_dbg_kms(&dev_priv->drm,
3011                                     "%s WM%d latency not provided\n",
3012                                     name, level);
3013                         continue;
3014                 }
3015
3016                 /*
3017                  * - latencies are in us on gen9.
3018                  * - before then, WM1+ latency values are in 0.5us units
3019                  */
3020                 if (DISPLAY_VER(dev_priv) >= 9)
3021                         latency *= 10;
3022                 else if (level > 0)
3023                         latency *= 5;
3024
3025                 drm_dbg_kms(&dev_priv->drm,
3026                             "%s WM%d latency %u (%u.%u usec)\n", name, level,
3027                             wm[level], latency / 10, latency % 10);
3028         }
3029 }
3030
3031 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
3032                                     u16 wm[5], u16 min)
3033 {
3034         int level, max_level = ilk_wm_max_level(dev_priv);
3035
3036         if (wm[0] >= min)
3037                 return false;
3038
3039         wm[0] = max(wm[0], min);
3040         for (level = 1; level <= max_level; level++)
3041                 wm[level] = max_t(u16, wm[level], DIV_ROUND_UP(min, 5));
3042
3043         return true;
3044 }
3045
3046 static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
3047 {
3048         bool changed;
3049
3050         /*
3051          * The BIOS provided WM memory latency values are often
3052          * inadequate for high resolution displays. Adjust them.
3053          */
3054         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
3055                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
3056                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
3057
3058         if (!changed)
3059                 return;
3060
3061         drm_dbg_kms(&dev_priv->drm,
3062                     "WM latency values increased to avoid potential underruns\n");
3063         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
3064         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
3065         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
3066 }
3067
3068 static void snb_wm_lp3_irq_quirk(struct drm_i915_private *dev_priv)
3069 {
3070         /*
3071          * On some SNB machines (Thinkpad X220 Tablet at least)
3072          * LP3 usage can cause vblank interrupts to be lost.
3073          * The DEIIR bit will go high but it looks like the CPU
3074          * never gets interrupted.
3075          *
3076          * It's not clear whether other interrupt source could
3077          * be affected or if this is somehow limited to vblank
3078          * interrupts only. To play it safe we disable LP3
3079          * watermarks entirely.
3080          */
3081         if (dev_priv->wm.pri_latency[3] == 0 &&
3082             dev_priv->wm.spr_latency[3] == 0 &&
3083             dev_priv->wm.cur_latency[3] == 0)
3084                 return;
3085
3086         dev_priv->wm.pri_latency[3] = 0;
3087         dev_priv->wm.spr_latency[3] = 0;
3088         dev_priv->wm.cur_latency[3] = 0;
3089
3090         drm_dbg_kms(&dev_priv->drm,
3091                     "LP3 watermarks disabled due to potential for lost interrupts\n");
3092         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
3093         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
3094         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
3095 }
3096
3097 static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
3098 {
3099         intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
3100
3101         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
3102                sizeof(dev_priv->wm.pri_latency));
3103         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
3104                sizeof(dev_priv->wm.pri_latency));
3105
3106         intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
3107         intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
3108
3109         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
3110         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
3111         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
3112
3113         if (DISPLAY_VER(dev_priv) == 6) {
3114                 snb_wm_latency_quirk(dev_priv);
3115                 snb_wm_lp3_irq_quirk(dev_priv);
3116         }
3117 }
3118
3119 static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
3120 {
3121         intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency);
3122         intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
3123 }
3124
3125 static bool ilk_validate_pipe_wm(const struct drm_i915_private *dev_priv,
3126                                  struct intel_pipe_wm *pipe_wm)
3127 {
3128         /* LP0 watermark maximums depend on this pipe alone */
3129         const struct intel_wm_config config = {
3130                 .num_pipes_active = 1,
3131                 .sprites_enabled = pipe_wm->sprites_enabled,
3132                 .sprites_scaled = pipe_wm->sprites_scaled,
3133         };
3134         struct ilk_wm_maximums max;
3135
3136         /* LP0 watermarks always use 1/2 DDB partitioning */
3137         ilk_compute_wm_maximums(dev_priv, 0, &config, INTEL_DDB_PART_1_2, &max);
3138
3139         /* At least LP0 must be valid */
3140         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
3141                 drm_dbg_kms(&dev_priv->drm, "LP0 watermark invalid\n");
3142                 return false;
3143         }
3144
3145         return true;
3146 }
3147
3148 /* Compute new watermarks for the pipe */
3149 static int ilk_compute_pipe_wm(struct intel_atomic_state *state,
3150                                struct intel_crtc *crtc)
3151 {
3152         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3153         struct intel_crtc_state *crtc_state =
3154                 intel_atomic_get_new_crtc_state(state, crtc);
3155         struct intel_pipe_wm *pipe_wm;
3156         struct intel_plane *plane;
3157         const struct intel_plane_state *plane_state;
3158         const struct intel_plane_state *pristate = NULL;
3159         const struct intel_plane_state *sprstate = NULL;
3160         const struct intel_plane_state *curstate = NULL;
3161         int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
3162         struct ilk_wm_maximums max;
3163
3164         pipe_wm = &crtc_state->wm.ilk.optimal;
3165
3166         intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
3167                 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
3168                         pristate = plane_state;
3169                 else if (plane->base.type == DRM_PLANE_TYPE_OVERLAY)
3170                         sprstate = plane_state;
3171                 else if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
3172                         curstate = plane_state;
3173         }
3174
3175         pipe_wm->pipe_enabled = crtc_state->hw.active;
3176         if (sprstate) {
3177                 pipe_wm->sprites_enabled = sprstate->uapi.visible;
3178                 pipe_wm->sprites_scaled = sprstate->uapi.visible &&
3179                         (drm_rect_width(&sprstate->uapi.dst) != drm_rect_width(&sprstate->uapi.src) >> 16 ||
3180                          drm_rect_height(&sprstate->uapi.dst) != drm_rect_height(&sprstate->uapi.src) >> 16);
3181         }
3182
3183         usable_level = max_level;
3184
3185         /* ILK/SNB: LP2+ watermarks only w/o sprites */
3186         if (DISPLAY_VER(dev_priv) <= 6 && pipe_wm->sprites_enabled)
3187                 usable_level = 1;
3188
3189         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
3190         if (pipe_wm->sprites_scaled)
3191                 usable_level = 0;
3192
3193         memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
3194         ilk_compute_wm_level(dev_priv, crtc, 0, crtc_state,
3195                              pristate, sprstate, curstate, &pipe_wm->wm[0]);
3196
3197         if (!ilk_validate_pipe_wm(dev_priv, pipe_wm))
3198                 return -EINVAL;
3199
3200         ilk_compute_wm_reg_maximums(dev_priv, 1, &max);
3201
3202         for (level = 1; level <= usable_level; level++) {
3203                 struct intel_wm_level *wm = &pipe_wm->wm[level];
3204
3205                 ilk_compute_wm_level(dev_priv, crtc, level, crtc_state,
3206                                      pristate, sprstate, curstate, wm);
3207
3208                 /*
3209                  * Disable any watermark level that exceeds the
3210                  * register maximums since such watermarks are
3211                  * always invalid.
3212                  */
3213                 if (!ilk_validate_wm_level(level, &max, wm)) {
3214                         memset(wm, 0, sizeof(*wm));
3215                         break;
3216                 }
3217         }
3218
3219         return 0;
3220 }
3221
3222 /*
3223  * Build a set of 'intermediate' watermark values that satisfy both the old
3224  * state and the new state.  These can be programmed to the hardware
3225  * immediately.
3226  */
3227 static int ilk_compute_intermediate_wm(struct intel_atomic_state *state,
3228                                        struct intel_crtc *crtc)
3229 {
3230         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3231         struct intel_crtc_state *new_crtc_state =
3232                 intel_atomic_get_new_crtc_state(state, crtc);
3233         const struct intel_crtc_state *old_crtc_state =
3234                 intel_atomic_get_old_crtc_state(state, crtc);
3235         struct intel_pipe_wm *a = &new_crtc_state->wm.ilk.intermediate;
3236         const struct intel_pipe_wm *b = &old_crtc_state->wm.ilk.optimal;
3237         int level, max_level = ilk_wm_max_level(dev_priv);
3238
3239         /*
3240          * Start with the final, target watermarks, then combine with the
3241          * currently active watermarks to get values that are safe both before
3242          * and after the vblank.
3243          */
3244         *a = new_crtc_state->wm.ilk.optimal;
3245         if (!new_crtc_state->hw.active ||
3246             drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi) ||
3247             state->skip_intermediate_wm)
3248                 return 0;
3249
3250         a->pipe_enabled |= b->pipe_enabled;
3251         a->sprites_enabled |= b->sprites_enabled;
3252         a->sprites_scaled |= b->sprites_scaled;
3253
3254         for (level = 0; level <= max_level; level++) {
3255                 struct intel_wm_level *a_wm = &a->wm[level];
3256                 const struct intel_wm_level *b_wm = &b->wm[level];
3257
3258                 a_wm->enable &= b_wm->enable;
3259                 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
3260                 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
3261                 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
3262                 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
3263         }
3264
3265         /*
3266          * We need to make sure that these merged watermark values are
3267          * actually a valid configuration themselves.  If they're not,
3268          * there's no safe way to transition from the old state to
3269          * the new state, so we need to fail the atomic transaction.
3270          */
3271         if (!ilk_validate_pipe_wm(dev_priv, a))
3272                 return -EINVAL;
3273
3274         /*
3275          * If our intermediate WM are identical to the final WM, then we can
3276          * omit the post-vblank programming; only update if it's different.
3277          */
3278         if (memcmp(a, &new_crtc_state->wm.ilk.optimal, sizeof(*a)) != 0)
3279                 new_crtc_state->wm.need_postvbl_update = true;
3280
3281         return 0;
3282 }
3283
3284 /*
3285  * Merge the watermarks from all active pipes for a specific level.
3286  */
3287 static void ilk_merge_wm_level(struct drm_i915_private *dev_priv,
3288                                int level,
3289                                struct intel_wm_level *ret_wm)
3290 {
3291         const struct intel_crtc *crtc;
3292
3293         ret_wm->enable = true;
3294
3295         for_each_intel_crtc(&dev_priv->drm, crtc) {
3296                 const struct intel_pipe_wm *active = &crtc->wm.active.ilk;
3297                 const struct intel_wm_level *wm = &active->wm[level];
3298
3299                 if (!active->pipe_enabled)
3300                         continue;
3301
3302                 /*
3303                  * The watermark values may have been used in the past,
3304                  * so we must maintain them in the registers for some
3305                  * time even if the level is now disabled.
3306                  */
3307                 if (!wm->enable)
3308                         ret_wm->enable = false;
3309
3310                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
3311                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
3312                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
3313                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
3314         }
3315 }
3316
3317 /*
3318  * Merge all low power watermarks for all active pipes.
3319  */
3320 static void ilk_wm_merge(struct drm_i915_private *dev_priv,
3321                          const struct intel_wm_config *config,
3322                          const struct ilk_wm_maximums *max,
3323                          struct intel_pipe_wm *merged)
3324 {
3325         int level, max_level = ilk_wm_max_level(dev_priv);
3326         int last_enabled_level = max_level;
3327
3328         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
3329         if ((DISPLAY_VER(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
3330             config->num_pipes_active > 1)
3331                 last_enabled_level = 0;
3332
3333         /* ILK: FBC WM must be disabled always */
3334         merged->fbc_wm_enabled = DISPLAY_VER(dev_priv) >= 6;
3335
3336         /* merge each WM1+ level */
3337         for (level = 1; level <= max_level; level++) {
3338                 struct intel_wm_level *wm = &merged->wm[level];
3339
3340                 ilk_merge_wm_level(dev_priv, level, wm);
3341
3342                 if (level > last_enabled_level)
3343                         wm->enable = false;
3344                 else if (!ilk_validate_wm_level(level, max, wm))
3345                         /* make sure all following levels get disabled */
3346                         last_enabled_level = level - 1;
3347
3348                 /*
3349                  * The spec says it is preferred to disable
3350                  * FBC WMs instead of disabling a WM level.
3351                  */
3352                 if (wm->fbc_val > max->fbc) {
3353                         if (wm->enable)
3354                                 merged->fbc_wm_enabled = false;
3355                         wm->fbc_val = 0;
3356                 }
3357         }
3358
3359         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
3360         /*
3361          * FIXME this is racy. FBC might get enabled later.
3362          * What we should check here is whether FBC can be
3363          * enabled sometime later.
3364          */
3365         if (DISPLAY_VER(dev_priv) == 5 && !merged->fbc_wm_enabled &&
3366             intel_fbc_is_active(dev_priv)) {
3367                 for (level = 2; level <= max_level; level++) {
3368                         struct intel_wm_level *wm = &merged->wm[level];
3369
3370                         wm->enable = false;
3371                 }
3372         }
3373 }
3374
3375 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
3376 {
3377         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
3378         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
3379 }
3380
3381 /* The value we need to program into the WM_LPx latency field */
3382 static unsigned int ilk_wm_lp_latency(struct drm_i915_private *dev_priv,
3383                                       int level)
3384 {
3385         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3386                 return 2 * level;
3387         else
3388                 return dev_priv->wm.pri_latency[level];
3389 }
3390
3391 static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
3392                                    const struct intel_pipe_wm *merged,
3393                                    enum intel_ddb_partitioning partitioning,
3394                                    struct ilk_wm_values *results)
3395 {
3396         struct intel_crtc *crtc;
3397         int level, wm_lp;
3398
3399         results->enable_fbc_wm = merged->fbc_wm_enabled;
3400         results->partitioning = partitioning;
3401
3402         /* LP1+ register values */
3403         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
3404                 const struct intel_wm_level *r;
3405
3406                 level = ilk_wm_lp_to_level(wm_lp, merged);
3407
3408                 r = &merged->wm[level];
3409
3410                 /*
3411                  * Maintain the watermark values even if the level is
3412                  * disabled. Doing otherwise could cause underruns.
3413                  */
3414                 results->wm_lp[wm_lp - 1] =
3415                         (ilk_wm_lp_latency(dev_priv, level) << WM1_LP_LATENCY_SHIFT) |
3416                         (r->pri_val << WM1_LP_SR_SHIFT) |
3417                         r->cur_val;
3418
3419                 if (r->enable)
3420                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
3421
3422                 if (DISPLAY_VER(dev_priv) >= 8)
3423                         results->wm_lp[wm_lp - 1] |=
3424                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
3425                 else
3426                         results->wm_lp[wm_lp - 1] |=
3427                                 r->fbc_val << WM1_LP_FBC_SHIFT;
3428
3429                 /*
3430                  * Always set WM1S_LP_EN when spr_val != 0, even if the
3431                  * level is disabled. Doing otherwise could cause underruns.
3432                  */
3433                 if (DISPLAY_VER(dev_priv) <= 6 && r->spr_val) {
3434                         drm_WARN_ON(&dev_priv->drm, wm_lp != 1);
3435                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
3436                 } else
3437                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
3438         }
3439
3440         /* LP0 register values */
3441         for_each_intel_crtc(&dev_priv->drm, crtc) {
3442                 enum pipe pipe = crtc->pipe;
3443                 const struct intel_pipe_wm *pipe_wm = &crtc->wm.active.ilk;
3444                 const struct intel_wm_level *r = &pipe_wm->wm[0];
3445
3446                 if (drm_WARN_ON(&dev_priv->drm, !r->enable))
3447                         continue;
3448
3449                 results->wm_pipe[pipe] =
3450                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
3451                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
3452                         r->cur_val;
3453         }
3454 }
3455
3456 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
3457  * case both are at the same level. Prefer r1 in case they're the same. */
3458 static struct intel_pipe_wm *
3459 ilk_find_best_result(struct drm_i915_private *dev_priv,
3460                      struct intel_pipe_wm *r1,
3461                      struct intel_pipe_wm *r2)
3462 {
3463         int level, max_level = ilk_wm_max_level(dev_priv);
3464         int level1 = 0, level2 = 0;
3465
3466         for (level = 1; level <= max_level; level++) {
3467                 if (r1->wm[level].enable)
3468                         level1 = level;
3469                 if (r2->wm[level].enable)
3470                         level2 = level;
3471         }
3472
3473         if (level1 == level2) {
3474                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
3475                         return r2;
3476                 else
3477                         return r1;
3478         } else if (level1 > level2) {
3479                 return r1;
3480         } else {
3481                 return r2;
3482         }
3483 }
3484
3485 /* dirty bits used to track which watermarks need changes */
3486 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
3487 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
3488 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
3489 #define WM_DIRTY_FBC (1 << 24)
3490 #define WM_DIRTY_DDB (1 << 25)
3491
3492 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
3493                                          const struct ilk_wm_values *old,
3494                                          const struct ilk_wm_values *new)
3495 {
3496         unsigned int dirty = 0;
3497         enum pipe pipe;
3498         int wm_lp;
3499
3500         for_each_pipe(dev_priv, pipe) {
3501                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
3502                         dirty |= WM_DIRTY_PIPE(pipe);
3503                         /* Must disable LP1+ watermarks too */
3504                         dirty |= WM_DIRTY_LP_ALL;
3505                 }
3506         }
3507
3508         if (old->enable_fbc_wm != new->enable_fbc_wm) {
3509                 dirty |= WM_DIRTY_FBC;
3510                 /* Must disable LP1+ watermarks too */
3511                 dirty |= WM_DIRTY_LP_ALL;
3512         }
3513
3514         if (old->partitioning != new->partitioning) {
3515                 dirty |= WM_DIRTY_DDB;
3516                 /* Must disable LP1+ watermarks too */
3517                 dirty |= WM_DIRTY_LP_ALL;
3518         }
3519
3520         /* LP1+ watermarks already deemed dirty, no need to continue */
3521         if (dirty & WM_DIRTY_LP_ALL)
3522                 return dirty;
3523
3524         /* Find the lowest numbered LP1+ watermark in need of an update... */
3525         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
3526                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
3527                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
3528                         break;
3529         }
3530
3531         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
3532         for (; wm_lp <= 3; wm_lp++)
3533                 dirty |= WM_DIRTY_LP(wm_lp);
3534
3535         return dirty;
3536 }
3537
3538 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
3539                                unsigned int dirty)
3540 {
3541         struct ilk_wm_values *previous = &dev_priv->wm.hw;
3542         bool changed = false;
3543
3544         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
3545                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
3546                 intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, previous->wm_lp[2]);
3547                 changed = true;
3548         }
3549         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
3550                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
3551                 intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, previous->wm_lp[1]);
3552                 changed = true;
3553         }
3554         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
3555                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
3556                 intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, previous->wm_lp[0]);
3557                 changed = true;
3558         }
3559
3560         /*
3561          * Don't touch WM1S_LP_EN here.
3562          * Doing so could cause underruns.
3563          */
3564
3565         return changed;
3566 }
3567
3568 /*
3569  * The spec says we shouldn't write when we don't need, because every write
3570  * causes WMs to be re-evaluated, expending some power.
3571  */
3572 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
3573                                 struct ilk_wm_values *results)
3574 {
3575         struct ilk_wm_values *previous = &dev_priv->wm.hw;
3576         unsigned int dirty;
3577         u32 val;
3578
3579         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
3580         if (!dirty)
3581                 return;
3582
3583         _ilk_disable_lp_wm(dev_priv, dirty);
3584
3585         if (dirty & WM_DIRTY_PIPE(PIPE_A))
3586                 intel_uncore_write(&dev_priv->uncore, WM0_PIPE_ILK(PIPE_A), results->wm_pipe[0]);
3587         if (dirty & WM_DIRTY_PIPE(PIPE_B))
3588                 intel_uncore_write(&dev_priv->uncore, WM0_PIPE_ILK(PIPE_B), results->wm_pipe[1]);
3589         if (dirty & WM_DIRTY_PIPE(PIPE_C))
3590                 intel_uncore_write(&dev_priv->uncore, WM0_PIPE_ILK(PIPE_C), results->wm_pipe[2]);
3591
3592         if (dirty & WM_DIRTY_DDB) {
3593                 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3594                         val = intel_uncore_read(&dev_priv->uncore, WM_MISC);
3595                         if (results->partitioning == INTEL_DDB_PART_1_2)
3596                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
3597                         else
3598                                 val |= WM_MISC_DATA_PARTITION_5_6;
3599                         intel_uncore_write(&dev_priv->uncore, WM_MISC, val);
3600                 } else {
3601                         val = intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL2);
3602                         if (results->partitioning == INTEL_DDB_PART_1_2)
3603                                 val &= ~DISP_DATA_PARTITION_5_6;
3604                         else
3605                                 val |= DISP_DATA_PARTITION_5_6;
3606                         intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL2, val);
3607                 }
3608         }
3609
3610         if (dirty & WM_DIRTY_FBC) {
3611                 val = intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL);
3612                 if (results->enable_fbc_wm)
3613                         val &= ~DISP_FBC_WM_DIS;
3614                 else
3615                         val |= DISP_FBC_WM_DIS;
3616                 intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, val);
3617         }
3618
3619         if (dirty & WM_DIRTY_LP(1) &&
3620             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
3621                 intel_uncore_write(&dev_priv->uncore, WM1S_LP_ILK, results->wm_lp_spr[0]);
3622
3623         if (DISPLAY_VER(dev_priv) >= 7) {
3624                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
3625                         intel_uncore_write(&dev_priv->uncore, WM2S_LP_IVB, results->wm_lp_spr[1]);
3626                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
3627                         intel_uncore_write(&dev_priv->uncore, WM3S_LP_IVB, results->wm_lp_spr[2]);
3628         }
3629
3630         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
3631                 intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, results->wm_lp[0]);
3632         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
3633                 intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, results->wm_lp[1]);
3634         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
3635                 intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, results->wm_lp[2]);
3636
3637         dev_priv->wm.hw = *results;
3638 }
3639
3640 bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv)
3641 {
3642         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
3643 }
3644
3645 u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv)
3646 {
3647         u8 enabled_slices = 0;
3648         enum dbuf_slice slice;
3649
3650         for_each_dbuf_slice(dev_priv, slice) {
3651                 if (intel_uncore_read(&dev_priv->uncore,
3652                                       DBUF_CTL_S(slice)) & DBUF_POWER_STATE)
3653                         enabled_slices |= BIT(slice);
3654         }
3655
3656         return enabled_slices;
3657 }
3658
3659 /*
3660  * FIXME: We still don't have the proper code detect if we need to apply the WA,
3661  * so assume we'll always need it in order to avoid underruns.
3662  */
3663 static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
3664 {
3665         return DISPLAY_VER(dev_priv) == 9;
3666 }
3667
3668 static bool
3669 intel_has_sagv(struct drm_i915_private *dev_priv)
3670 {
3671         return DISPLAY_VER(dev_priv) >= 9 && !IS_LP(dev_priv) &&
3672                 dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
3673 }
3674
3675 static void
3676 skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
3677 {
3678         if (DISPLAY_VER(dev_priv) >= 12) {
3679                 u32 val = 0;
3680                 int ret;
3681
3682                 ret = sandybridge_pcode_read(dev_priv,
3683                                              GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
3684                                              &val, NULL);
3685                 if (!ret) {
3686                         dev_priv->sagv_block_time_us = val;
3687                         return;
3688                 }
3689
3690                 drm_dbg(&dev_priv->drm, "Couldn't read SAGV block time!\n");
3691         } else if (DISPLAY_VER(dev_priv) == 11) {
3692                 dev_priv->sagv_block_time_us = 10;
3693                 return;
3694         } else if (DISPLAY_VER(dev_priv) == 10) {
3695                 dev_priv->sagv_block_time_us = 20;
3696                 return;
3697         } else if (DISPLAY_VER(dev_priv) == 9) {
3698                 dev_priv->sagv_block_time_us = 30;
3699                 return;
3700         } else {
3701                 MISSING_CASE(DISPLAY_VER(dev_priv));
3702         }
3703
3704         /* Default to an unusable block time */
3705         dev_priv->sagv_block_time_us = -1;
3706 }
3707
3708 /*
3709  * SAGV dynamically adjusts the system agent voltage and clock frequencies
3710  * depending on power and performance requirements. The display engine access
3711  * to system memory is blocked during the adjustment time. Because of the
3712  * blocking time, having this enabled can cause full system hangs and/or pipe
3713  * underruns if we don't meet all of the following requirements:
3714  *
3715  *  - <= 1 pipe enabled
3716  *  - All planes can enable watermarks for latencies >= SAGV engine block time
3717  *  - We're not using an interlaced display configuration
3718  */
3719 static int
3720 intel_enable_sagv(struct drm_i915_private *dev_priv)
3721 {
3722         int ret;
3723
3724         if (!intel_has_sagv(dev_priv))
3725                 return 0;
3726
3727         if (dev_priv->sagv_status == I915_SAGV_ENABLED)
3728                 return 0;
3729
3730         drm_dbg_kms(&dev_priv->drm, "Enabling SAGV\n");
3731         ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
3732                                       GEN9_SAGV_ENABLE);
3733
3734         /* We don't need to wait for SAGV when enabling */
3735
3736         /*
3737          * Some skl systems, pre-release machines in particular,
3738          * don't actually have SAGV.
3739          */
3740         if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
3741                 drm_dbg(&dev_priv->drm, "No SAGV found on system, ignoring\n");
3742                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
3743                 return 0;
3744         } else if (ret < 0) {
3745                 drm_err(&dev_priv->drm, "Failed to enable SAGV\n");
3746                 return ret;
3747         }
3748
3749         dev_priv->sagv_status = I915_SAGV_ENABLED;
3750         return 0;
3751 }
3752
3753 static int
3754 intel_disable_sagv(struct drm_i915_private *dev_priv)
3755 {
3756         int ret;
3757
3758         if (!intel_has_sagv(dev_priv))
3759                 return 0;
3760
3761         if (dev_priv->sagv_status == I915_SAGV_DISABLED)
3762                 return 0;
3763
3764         drm_dbg_kms(&dev_priv->drm, "Disabling SAGV\n");
3765         /* bspec says to keep retrying for at least 1 ms */
3766         ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,
3767                                 GEN9_SAGV_DISABLE,
3768                                 GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED,
3769                                 1);
3770         /*
3771          * Some skl systems, pre-release machines in particular,
3772          * don't actually have SAGV.
3773          */
3774         if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
3775                 drm_dbg(&dev_priv->drm, "No SAGV found on system, ignoring\n");
3776                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
3777                 return 0;
3778         } else if (ret < 0) {
3779                 drm_err(&dev_priv->drm, "Failed to disable SAGV (%d)\n", ret);
3780                 return ret;
3781         }
3782
3783         dev_priv->sagv_status = I915_SAGV_DISABLED;
3784         return 0;
3785 }
3786
3787 void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
3788 {
3789         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3790         const struct intel_bw_state *new_bw_state;
3791         const struct intel_bw_state *old_bw_state;
3792         u32 new_mask = 0;
3793
3794         /*
3795          * Just return if we can't control SAGV or don't have it.
3796          * This is different from situation when we have SAGV but just can't
3797          * afford it due to DBuf limitation - in case if SAGV is completely
3798          * disabled in a BIOS, we are not even allowed to send a PCode request,
3799          * as it will throw an error. So have to check it here.
3800          */
3801         if (!intel_has_sagv(dev_priv))
3802                 return;
3803
3804         new_bw_state = intel_atomic_get_new_bw_state(state);
3805         if (!new_bw_state)
3806                 return;
3807
3808         if (DISPLAY_VER(dev_priv) < 11 && !intel_can_enable_sagv(dev_priv, new_bw_state)) {
3809                 intel_disable_sagv(dev_priv);
3810                 return;
3811         }
3812
3813         old_bw_state = intel_atomic_get_old_bw_state(state);
3814         /*
3815          * Nothing to mask
3816          */
3817         if (new_bw_state->qgv_points_mask == old_bw_state->qgv_points_mask)
3818                 return;
3819
3820         new_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;
3821
3822         /*
3823          * If new mask is zero - means there is nothing to mask,
3824          * we can only unmask, which should be done in unmask.
3825          */
3826         if (!new_mask)
3827                 return;
3828
3829         /*
3830          * Restrict required qgv points before updating the configuration.
3831          * According to BSpec we can't mask and unmask qgv points at the same
3832          * time. Also masking should be done before updating the configuration
3833          * and unmasking afterwards.
3834          */
3835         icl_pcode_restrict_qgv_points(dev_priv, new_mask);
3836 }
3837
3838 void intel_sagv_post_plane_update(struct intel_atomic_state *state)
3839 {
3840         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3841         const struct intel_bw_state *new_bw_state;
3842         const struct intel_bw_state *old_bw_state;
3843         u32 new_mask = 0;
3844
3845         /*
3846          * Just return if we can't control SAGV or don't have it.
3847          * This is different from situation when we have SAGV but just can't
3848          * afford it due to DBuf limitation - in case if SAGV is completely
3849          * disabled in a BIOS, we are not even allowed to send a PCode request,
3850          * as it will throw an error. So have to check it here.
3851          */
3852         if (!intel_has_sagv(dev_priv))
3853                 return;
3854
3855         new_bw_state = intel_atomic_get_new_bw_state(state);
3856         if (!new_bw_state)
3857                 return;
3858
3859         if (DISPLAY_VER(dev_priv) < 11 && intel_can_enable_sagv(dev_priv, new_bw_state)) {
3860                 intel_enable_sagv(dev_priv);
3861                 return;
3862         }
3863
3864         old_bw_state = intel_atomic_get_old_bw_state(state);
3865         /*
3866          * Nothing to unmask
3867          */
3868         if (new_bw_state->qgv_points_mask == old_bw_state->qgv_points_mask)
3869                 return;
3870
3871         new_mask = new_bw_state->qgv_points_mask;
3872
3873         /*
3874          * Allow required qgv points after updating the configuration.
3875          * According to BSpec we can't mask and unmask qgv points at the same
3876          * time. Also masking should be done before updating the configuration
3877          * and unmasking afterwards.
3878          */
3879         icl_pcode_restrict_qgv_points(dev_priv, new_mask);
3880 }
3881
3882 static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
3883 {
3884         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3885         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3886         enum plane_id plane_id;
3887         int max_level = INT_MAX;
3888
3889         if (!intel_has_sagv(dev_priv))
3890                 return false;
3891
3892         if (!crtc_state->hw.active)
3893                 return true;
3894
3895         if (crtc_state->hw.pipe_mode.flags & DRM_MODE_FLAG_INTERLACE)
3896                 return false;
3897
3898         for_each_plane_id_on_crtc(crtc, plane_id) {
3899                 const struct skl_plane_wm *wm =
3900                         &crtc_state->wm.skl.optimal.planes[plane_id];
3901                 int level;
3902
3903                 /* Skip this plane if it's not enabled */
3904                 if (!wm->wm[0].enable)
3905                         continue;
3906
3907                 /* Find the highest enabled wm level for this plane */
3908                 for (level = ilk_wm_max_level(dev_priv);
3909                      !wm->wm[level].enable; --level)
3910                      { }
3911
3912                 /* Highest common enabled wm level for all planes */
3913                 max_level = min(level, max_level);
3914         }
3915
3916         /* No enabled planes? */
3917         if (max_level == INT_MAX)
3918                 return true;
3919
3920         for_each_plane_id_on_crtc(crtc, plane_id) {
3921                 const struct skl_plane_wm *wm =
3922                         &crtc_state->wm.skl.optimal.planes[plane_id];
3923
3924                 /*
3925                  * All enabled planes must have enabled a common wm level that
3926                  * can tolerate memory latencies higher than sagv_block_time_us
3927                  */
3928                 if (wm->wm[0].enable && !wm->wm[max_level].can_sagv)
3929                         return false;
3930         }
3931
3932         return true;
3933 }
3934
3935 static bool tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
3936 {
3937         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3938         enum plane_id plane_id;
3939
3940         if (!crtc_state->hw.active)
3941                 return true;
3942
3943         for_each_plane_id_on_crtc(crtc, plane_id) {
3944                 const struct skl_plane_wm *wm =
3945                         &crtc_state->wm.skl.optimal.planes[plane_id];
3946
3947                 if (wm->wm[0].enable && !wm->sagv.wm0.enable)
3948                         return false;
3949         }
3950
3951         return true;
3952 }
3953
3954 static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
3955 {
3956         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3957         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3958
3959         if (DISPLAY_VER(dev_priv) >= 12)
3960                 return tgl_crtc_can_enable_sagv(crtc_state);
3961         else
3962                 return skl_crtc_can_enable_sagv(crtc_state);
3963 }
3964
3965 bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
3966                            const struct intel_bw_state *bw_state)
3967 {
3968         if (DISPLAY_VER(dev_priv) < 11 &&
3969             bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
3970                 return false;
3971
3972         return bw_state->pipe_sagv_reject == 0;
3973 }
3974
3975 static int intel_compute_sagv_mask(struct intel_atomic_state *state)
3976 {
3977         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3978         int ret;
3979         struct intel_crtc *crtc;
3980         struct intel_crtc_state *new_crtc_state;
3981         struct intel_bw_state *new_bw_state = NULL;
3982         const struct intel_bw_state *old_bw_state = NULL;
3983         int i;
3984
3985         for_each_new_intel_crtc_in_state(state, crtc,
3986                                          new_crtc_state, i) {
3987                 new_bw_state = intel_atomic_get_bw_state(state);
3988                 if (IS_ERR(new_bw_state))
3989                         return PTR_ERR(new_bw_state);
3990
3991                 old_bw_state = intel_atomic_get_old_bw_state(state);
3992
3993                 if (intel_crtc_can_enable_sagv(new_crtc_state))
3994                         new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
3995                 else
3996                         new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
3997         }
3998
3999         if (!new_bw_state)
4000                 return 0;
4001
4002         new_bw_state->active_pipes =
4003                 intel_calc_active_pipes(state, old_bw_state->active_pipes);
4004
4005         if (new_bw_state->active_pipes != old_bw_state->active_pipes) {
4006                 ret = intel_atomic_lock_global_state(&new_bw_state->base);
4007                 if (ret)
4008                         return ret;
4009         }
4010
4011         for_each_new_intel_crtc_in_state(state, crtc,
4012                                          new_crtc_state, i) {
4013                 struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
4014
4015                 /*
4016                  * We store use_sagv_wm in the crtc state rather than relying on
4017                  * that bw state since we have no convenient way to get at the
4018                  * latter from the plane commit hooks (especially in the legacy
4019                  * cursor case)
4020                  */
4021                 pipe_wm->use_sagv_wm = !HAS_HW_SAGV_WM(dev_priv) &&
4022                         DISPLAY_VER(dev_priv) >= 12 &&
4023                         intel_can_enable_sagv(dev_priv, new_bw_state);
4024         }
4025
4026         if (intel_can_enable_sagv(dev_priv, new_bw_state) !=
4027             intel_can_enable_sagv(dev_priv, old_bw_state)) {
4028                 ret = intel_atomic_serialize_global_state(&new_bw_state->base);
4029                 if (ret)
4030                         return ret;
4031         } else if (new_bw_state->pipe_sagv_reject != old_bw_state->pipe_sagv_reject) {
4032                 ret = intel_atomic_lock_global_state(&new_bw_state->base);
4033                 if (ret)
4034                         return ret;
4035         }
4036
4037         return 0;
4038 }
4039
4040 static int intel_dbuf_slice_size(struct drm_i915_private *dev_priv)
4041 {
4042         return INTEL_INFO(dev_priv)->dbuf.size /
4043                 hweight8(INTEL_INFO(dev_priv)->dbuf.slice_mask);
4044 }
4045
4046 static void
4047 skl_ddb_entry_for_slices(struct drm_i915_private *dev_priv, u8 slice_mask,
4048                          struct skl_ddb_entry *ddb)
4049 {
4050         int slice_size = intel_dbuf_slice_size(dev_priv);
4051
4052         if (!slice_mask) {
4053                 ddb->start = 0;
4054                 ddb->end = 0;
4055                 return;
4056         }
4057
4058         ddb->start = (ffs(slice_mask) - 1) * slice_size;
4059         ddb->end = fls(slice_mask) * slice_size;
4060
4061         WARN_ON(ddb->start >= ddb->end);
4062         WARN_ON(ddb->end > INTEL_INFO(dev_priv)->dbuf.size);
4063 }
4064
4065 static unsigned int mbus_ddb_offset(struct drm_i915_private *i915, u8 slice_mask)
4066 {
4067         struct skl_ddb_entry ddb;
4068
4069         if (slice_mask & (BIT(DBUF_S1) | BIT(DBUF_S2)))
4070                 slice_mask = BIT(DBUF_S1);
4071         else if (slice_mask & (BIT(DBUF_S3) | BIT(DBUF_S4)))
4072                 slice_mask = BIT(DBUF_S3);
4073
4074         skl_ddb_entry_for_slices(i915, slice_mask, &ddb);
4075
4076         return ddb.start;
4077 }
4078
4079 u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv,
4080                             const struct skl_ddb_entry *entry)
4081 {
4082         int slice_size = intel_dbuf_slice_size(dev_priv);
4083         enum dbuf_slice start_slice, end_slice;
4084         u8 slice_mask = 0;
4085
4086         if (!skl_ddb_entry_size(entry))
4087                 return 0;
4088
4089         start_slice = entry->start / slice_size;
4090         end_slice = (entry->end - 1) / slice_size;
4091
4092         /*
4093          * Per plane DDB entry can in a really worst case be on multiple slices
4094          * but single entry is anyway contigious.
4095          */
4096         while (start_slice <= end_slice) {
4097                 slice_mask |= BIT(start_slice);
4098                 start_slice++;
4099         }
4100
4101         return slice_mask;
4102 }
4103
4104 static unsigned int intel_crtc_ddb_weight(const struct intel_crtc_state *crtc_state)
4105 {
4106         const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
4107         int hdisplay, vdisplay;
4108
4109         if (!crtc_state->hw.active)
4110                 return 0;
4111
4112         /*
4113          * Watermark/ddb requirement highly depends upon width of the
4114          * framebuffer, So instead of allocating DDB equally among pipes
4115          * distribute DDB based on resolution/width of the display.
4116          */
4117         drm_mode_get_hv_timing(pipe_mode, &hdisplay, &vdisplay);
4118
4119         return hdisplay;
4120 }
4121
4122 static void intel_crtc_dbuf_weights(const struct intel_dbuf_state *dbuf_state,
4123                                     enum pipe for_pipe,
4124                                     unsigned int *weight_start,
4125                                     unsigned int *weight_end,
4126                                     unsigned int *weight_total)
4127 {
4128         struct drm_i915_private *dev_priv =
4129                 to_i915(dbuf_state->base.state->base.dev);
4130         enum pipe pipe;
4131
4132         *weight_start = 0;
4133         *weight_end = 0;
4134         *weight_total = 0;
4135
4136         for_each_pipe(dev_priv, pipe) {
4137                 int weight = dbuf_state->weight[pipe];
4138
4139                 /*
4140                  * Do not account pipes using other slice sets
4141                  * luckily as of current BSpec slice sets do not partially
4142                  * intersect(pipes share either same one slice or same slice set
4143                  * i.e no partial intersection), so it is enough to check for
4144                  * equality for now.
4145                  */
4146                 if (dbuf_state->slices[pipe] != dbuf_state->slices[for_pipe])
4147                         continue;
4148
4149                 *weight_total += weight;
4150                 if (pipe < for_pipe) {
4151                         *weight_start += weight;
4152                         *weight_end += weight;
4153                 } else if (pipe == for_pipe) {
4154                         *weight_end += weight;
4155                 }
4156         }
4157 }
4158
4159 static int
4160 skl_crtc_allocate_ddb(struct intel_atomic_state *state, struct intel_crtc *crtc)
4161 {
4162         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4163         unsigned int weight_total, weight_start, weight_end;
4164         const struct intel_dbuf_state *old_dbuf_state =
4165                 intel_atomic_get_old_dbuf_state(state);
4166         struct intel_dbuf_state *new_dbuf_state =
4167                 intel_atomic_get_new_dbuf_state(state);
4168         struct intel_crtc_state *crtc_state;
4169         struct skl_ddb_entry ddb_slices;
4170         enum pipe pipe = crtc->pipe;
4171         unsigned int mbus_offset = 0;
4172         u32 ddb_range_size;
4173         u32 dbuf_slice_mask;
4174         u32 start, end;
4175         int ret;
4176
4177         if (new_dbuf_state->weight[pipe] == 0) {
4178                 new_dbuf_state->ddb[pipe].start = 0;
4179                 new_dbuf_state->ddb[pipe].end = 0;
4180                 goto out;
4181         }
4182
4183         dbuf_slice_mask = new_dbuf_state->slices[pipe];
4184
4185         skl_ddb_entry_for_slices(dev_priv, dbuf_slice_mask, &ddb_slices);
4186         mbus_offset = mbus_ddb_offset(dev_priv, dbuf_slice_mask);
4187         ddb_range_size = skl_ddb_entry_size(&ddb_slices);
4188
4189         intel_crtc_dbuf_weights(new_dbuf_state, pipe,
4190                                 &weight_start, &weight_end, &weight_total);
4191
4192         start = ddb_range_size * weight_start / weight_total;
4193         end = ddb_range_size * weight_end / weight_total;
4194
4195         new_dbuf_state->ddb[pipe].start = ddb_slices.start - mbus_offset + start;
4196         new_dbuf_state->ddb[pipe].end = ddb_slices.start - mbus_offset + end;
4197 out:
4198         if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe] &&
4199             skl_ddb_entry_equal(&old_dbuf_state->ddb[pipe],
4200                                 &new_dbuf_state->ddb[pipe]))
4201                 return 0;
4202
4203         ret = intel_atomic_lock_global_state(&new_dbuf_state->base);
4204         if (ret)
4205                 return ret;
4206
4207         crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
4208         if (IS_ERR(crtc_state))
4209                 return PTR_ERR(crtc_state);
4210
4211         /*
4212          * Used for checking overlaps, so we need absolute
4213          * offsets instead of MBUS relative offsets.
4214          */
4215         crtc_state->wm.skl.ddb.start = mbus_offset + new_dbuf_state->ddb[pipe].start;
4216         crtc_state->wm.skl.ddb.end = mbus_offset + new_dbuf_state->ddb[pipe].end;
4217
4218         drm_dbg_kms(&dev_priv->drm,
4219                     "[CRTC:%d:%s] dbuf slices 0x%x -> 0x%x, ddb (%d - %d) -> (%d - %d), active pipes 0x%x -> 0x%x\n",
4220                     crtc->base.base.id, crtc->base.name,
4221                     old_dbuf_state->slices[pipe], new_dbuf_state->slices[pipe],
4222                     old_dbuf_state->ddb[pipe].start, old_dbuf_state->ddb[pipe].end,
4223                     new_dbuf_state->ddb[pipe].start, new_dbuf_state->ddb[pipe].end,
4224                     old_dbuf_state->active_pipes, new_dbuf_state->active_pipes);
4225
4226         return 0;
4227 }
4228
4229 static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
4230                                  int width, const struct drm_format_info *format,
4231                                  u64 modifier, unsigned int rotation,
4232                                  u32 plane_pixel_rate, struct skl_wm_params *wp,
4233                                  int color_plane);
4234 static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
4235                                  int level,
4236                                  unsigned int latency,
4237                                  const struct skl_wm_params *wp,
4238                                  const struct skl_wm_level *result_prev,
4239                                  struct skl_wm_level *result /* out */);
4240
4241 static unsigned int
4242 skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
4243                       int num_active)
4244 {
4245         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4246         int level, max_level = ilk_wm_max_level(dev_priv);
4247         struct skl_wm_level wm = {};
4248         int ret, min_ddb_alloc = 0;
4249         struct skl_wm_params wp;
4250
4251         ret = skl_compute_wm_params(crtc_state, 256,
4252                                     drm_format_info(DRM_FORMAT_ARGB8888),
4253                                     DRM_FORMAT_MOD_LINEAR,
4254                                     DRM_MODE_ROTATE_0,
4255                                     crtc_state->pixel_rate, &wp, 0);
4256         drm_WARN_ON(&dev_priv->drm, ret);
4257
4258         for (level = 0; level <= max_level; level++) {
4259                 unsigned int latency = dev_priv->wm.skl_latency[level];
4260
4261                 skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
4262                 if (wm.min_ddb_alloc == U16_MAX)
4263                         break;
4264
4265                 min_ddb_alloc = wm.min_ddb_alloc;
4266         }
4267
4268         return max(num_active == 1 ? 32 : 8, min_ddb_alloc);
4269 }
4270
4271 static void skl_ddb_entry_init_from_hw(struct drm_i915_private *dev_priv,
4272                                        struct skl_ddb_entry *entry, u32 reg)
4273 {
4274         entry->start = reg & DDB_ENTRY_MASK;
4275         entry->end = (reg >> DDB_ENTRY_END_SHIFT) & DDB_ENTRY_MASK;
4276
4277         if (entry->end)
4278                 entry->end += 1;
4279 }
4280
4281 static void
4282 skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
4283                            const enum pipe pipe,
4284                            const enum plane_id plane_id,
4285                            struct skl_ddb_entry *ddb_y,
4286                            struct skl_ddb_entry *ddb_uv)
4287 {
4288         u32 val, val2;
4289         u32 fourcc = 0;
4290
4291         /* Cursor doesn't support NV12/planar, so no extra calculation needed */
4292         if (plane_id == PLANE_CURSOR) {
4293                 val = intel_uncore_read(&dev_priv->uncore, CUR_BUF_CFG(pipe));
4294                 skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
4295                 return;
4296         }
4297
4298         val = intel_uncore_read(&dev_priv->uncore, PLANE_CTL(pipe, plane_id));
4299
4300         /* No DDB allocated for disabled planes */
4301         if (val & PLANE_CTL_ENABLE)
4302                 fourcc = skl_format_to_fourcc(val & PLANE_CTL_FORMAT_MASK,
4303                                               val & PLANE_CTL_ORDER_RGBX,
4304                                               val & PLANE_CTL_ALPHA_MASK);
4305
4306         if (DISPLAY_VER(dev_priv) >= 11) {
4307                 val = intel_uncore_read(&dev_priv->uncore, PLANE_BUF_CFG(pipe, plane_id));
4308                 skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
4309         } else {
4310                 val = intel_uncore_read(&dev_priv->uncore, PLANE_BUF_CFG(pipe, plane_id));
4311                 val2 = intel_uncore_read(&dev_priv->uncore, PLANE_NV12_BUF_CFG(pipe, plane_id));
4312
4313                 if (fourcc &&
4314                     drm_format_info_is_yuv_semiplanar(drm_format_info(fourcc)))
4315                         swap(val, val2);
4316
4317                 skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
4318                 skl_ddb_entry_init_from_hw(dev_priv, ddb_uv, val2);
4319         }
4320 }
4321
4322 void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
4323                                struct skl_ddb_entry *ddb_y,
4324                                struct skl_ddb_entry *ddb_uv)
4325 {
4326         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4327         enum intel_display_power_domain power_domain;
4328         enum pipe pipe = crtc->pipe;
4329         intel_wakeref_t wakeref;
4330         enum plane_id plane_id;
4331
4332         power_domain = POWER_DOMAIN_PIPE(pipe);
4333         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
4334         if (!wakeref)
4335                 return;
4336
4337         for_each_plane_id_on_crtc(crtc, plane_id)
4338                 skl_ddb_get_hw_plane_state(dev_priv, pipe,
4339                                            plane_id,
4340                                            &ddb_y[plane_id],
4341                                            &ddb_uv[plane_id]);
4342
4343         intel_display_power_put(dev_priv, power_domain, wakeref);
4344 }
4345
4346 /*
4347  * Determines the downscale amount of a plane for the purposes of watermark calculations.
4348  * The bspec defines downscale amount as:
4349  *
4350  * """
4351  * Horizontal down scale amount = maximum[1, Horizontal source size /
4352  *                                           Horizontal destination size]
4353  * Vertical down scale amount = maximum[1, Vertical source size /
4354  *                                         Vertical destination size]
4355  * Total down scale amount = Horizontal down scale amount *
4356  *                           Vertical down scale amount
4357  * """
4358  *
4359  * Return value is provided in 16.16 fixed point form to retain fractional part.
4360  * Caller should take care of dividing & rounding off the value.
4361  */
4362 static uint_fixed_16_16_t
4363 skl_plane_downscale_amount(const struct intel_crtc_state *crtc_state,
4364                            const struct intel_plane_state *plane_state)
4365 {
4366         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4367         u32 src_w, src_h, dst_w, dst_h;
4368         uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
4369         uint_fixed_16_16_t downscale_h, downscale_w;
4370
4371         if (drm_WARN_ON(&dev_priv->drm,
4372                         !intel_wm_plane_visible(crtc_state, plane_state)))
4373                 return u32_to_fixed16(0);
4374
4375         /*
4376          * Src coordinates are already rotated by 270 degrees for
4377          * the 90/270 degree plane rotation cases (to match the
4378          * GTT mapping), hence no need to account for rotation here.
4379          *
4380          * n.b., src is 16.16 fixed point, dst is whole integer.
4381          */
4382         src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
4383         src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
4384         dst_w = drm_rect_width(&plane_state->uapi.dst);
4385         dst_h = drm_rect_height(&plane_state->uapi.dst);
4386
4387         fp_w_ratio = div_fixed16(src_w, dst_w);
4388         fp_h_ratio = div_fixed16(src_h, dst_h);
4389         downscale_w = max_fixed16(fp_w_ratio, u32_to_fixed16(1));
4390         downscale_h = max_fixed16(fp_h_ratio, u32_to_fixed16(1));
4391
4392         return mul_fixed16(downscale_w, downscale_h);
4393 }
4394
4395 struct dbuf_slice_conf_entry {
4396         u8 active_pipes;
4397         u8 dbuf_mask[I915_MAX_PIPES];
4398         bool join_mbus;
4399 };
4400
4401 /*
4402  * Table taken from Bspec 12716
4403  * Pipes do have some preferred DBuf slice affinity,
4404  * plus there are some hardcoded requirements on how
4405  * those should be distributed for multipipe scenarios.
4406  * For more DBuf slices algorithm can get even more messy
4407  * and less readable, so decided to use a table almost
4408  * as is from BSpec itself - that way it is at least easier
4409  * to compare, change and check.
4410  */
4411 static const struct dbuf_slice_conf_entry icl_allowed_dbufs[] =
4412 /* Autogenerated with igt/tools/intel_dbuf_map tool: */
4413 {
4414         {
4415                 .active_pipes = BIT(PIPE_A),
4416                 .dbuf_mask = {
4417                         [PIPE_A] = BIT(DBUF_S1),
4418                 },
4419         },
4420         {
4421                 .active_pipes = BIT(PIPE_B),
4422                 .dbuf_mask = {
4423                         [PIPE_B] = BIT(DBUF_S1),
4424                 },
4425         },
4426         {
4427                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
4428                 .dbuf_mask = {
4429                         [PIPE_A] = BIT(DBUF_S1),
4430                         [PIPE_B] = BIT(DBUF_S2),
4431                 },
4432         },
4433         {
4434                 .active_pipes = BIT(PIPE_C),
4435                 .dbuf_mask = {
4436                         [PIPE_C] = BIT(DBUF_S2),
4437                 },
4438         },
4439         {
4440                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
4441                 .dbuf_mask = {
4442                         [PIPE_A] = BIT(DBUF_S1),
4443                         [PIPE_C] = BIT(DBUF_S2),
4444                 },
4445         },
4446         {
4447                 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
4448                 .dbuf_mask = {
4449                         [PIPE_B] = BIT(DBUF_S1),
4450                         [PIPE_C] = BIT(DBUF_S2),
4451                 },
4452         },
4453         {
4454                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
4455                 .dbuf_mask = {
4456                         [PIPE_A] = BIT(DBUF_S1),
4457                         [PIPE_B] = BIT(DBUF_S1),
4458                         [PIPE_C] = BIT(DBUF_S2),
4459                 },
4460         },
4461         {}
4462 };
4463
4464 /*
4465  * Table taken from Bspec 49255
4466  * Pipes do have some preferred DBuf slice affinity,
4467  * plus there are some hardcoded requirements on how
4468  * those should be distributed for multipipe scenarios.
4469  * For more DBuf slices algorithm can get even more messy
4470  * and less readable, so decided to use a table almost
4471  * as is from BSpec itself - that way it is at least easier
4472  * to compare, change and check.
4473  */
4474 static const struct dbuf_slice_conf_entry tgl_allowed_dbufs[] =
4475 /* Autogenerated with igt/tools/intel_dbuf_map tool: */
4476 {
4477         {
4478                 .active_pipes = BIT(PIPE_A),
4479                 .dbuf_mask = {
4480                         [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
4481                 },
4482         },
4483         {
4484                 .active_pipes = BIT(PIPE_B),
4485                 .dbuf_mask = {
4486                         [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),
4487                 },
4488         },
4489         {
4490                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
4491                 .dbuf_mask = {
4492                         [PIPE_A] = BIT(DBUF_S2),
4493                         [PIPE_B] = BIT(DBUF_S1),
4494                 },
4495         },
4496         {
4497                 .active_pipes = BIT(PIPE_C),
4498                 .dbuf_mask = {
4499                         [PIPE_C] = BIT(DBUF_S2) | BIT(DBUF_S1),
4500                 },
4501         },
4502         {
4503                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
4504                 .dbuf_mask = {
4505                         [PIPE_A] = BIT(DBUF_S1),
4506                         [PIPE_C] = BIT(DBUF_S2),
4507                 },
4508         },
4509         {
4510                 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
4511                 .dbuf_mask = {
4512                         [PIPE_B] = BIT(DBUF_S1),
4513                         [PIPE_C] = BIT(DBUF_S2),
4514                 },
4515         },
4516         {
4517                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
4518                 .dbuf_mask = {
4519                         [PIPE_A] = BIT(DBUF_S1),
4520                         [PIPE_B] = BIT(DBUF_S1),
4521                         [PIPE_C] = BIT(DBUF_S2),
4522                 },
4523         },
4524         {
4525                 .active_pipes = BIT(PIPE_D),
4526                 .dbuf_mask = {
4527                         [PIPE_D] = BIT(DBUF_S2) | BIT(DBUF_S1),
4528                 },
4529         },
4530         {
4531                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_D),
4532                 .dbuf_mask = {
4533                         [PIPE_A] = BIT(DBUF_S1),
4534                         [PIPE_D] = BIT(DBUF_S2),
4535                 },
4536         },
4537         {
4538                 .active_pipes = BIT(PIPE_B) | BIT(PIPE_D),
4539                 .dbuf_mask = {
4540                         [PIPE_B] = BIT(DBUF_S1),
4541                         [PIPE_D] = BIT(DBUF_S2),
4542                 },
4543         },
4544         {
4545                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),
4546                 .dbuf_mask = {
4547                         [PIPE_A] = BIT(DBUF_S1),
4548                         [PIPE_B] = BIT(DBUF_S1),
4549                         [PIPE_D] = BIT(DBUF_S2),
4550                 },
4551         },
4552         {
4553                 .active_pipes = BIT(PIPE_C) | BIT(PIPE_D),
4554                 .dbuf_mask = {
4555                         [PIPE_C] = BIT(DBUF_S1),
4556                         [PIPE_D] = BIT(DBUF_S2),
4557                 },
4558         },
4559         {
4560                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),
4561                 .dbuf_mask = {
4562                         [PIPE_A] = BIT(DBUF_S1),
4563                         [PIPE_C] = BIT(DBUF_S2),
4564                         [PIPE_D] = BIT(DBUF_S2),
4565                 },
4566         },
4567         {
4568                 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
4569                 .dbuf_mask = {
4570                         [PIPE_B] = BIT(DBUF_S1),
4571                         [PIPE_C] = BIT(DBUF_S2),
4572                         [PIPE_D] = BIT(DBUF_S2),
4573                 },
4574         },
4575         {
4576                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
4577                 .dbuf_mask = {
4578                         [PIPE_A] = BIT(DBUF_S1),
4579                         [PIPE_B] = BIT(DBUF_S1),
4580                         [PIPE_C] = BIT(DBUF_S2),
4581                         [PIPE_D] = BIT(DBUF_S2),
4582                 },
4583         },
4584         {}
4585 };
4586
4587 static const struct dbuf_slice_conf_entry dg2_allowed_dbufs[] = {
4588         {
4589                 .active_pipes = BIT(PIPE_A),
4590                 .dbuf_mask = {
4591                         [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
4592                 },
4593         },
4594         {
4595                 .active_pipes = BIT(PIPE_B),
4596                 .dbuf_mask = {
4597                         [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),
4598                 },
4599         },
4600         {
4601                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
4602                 .dbuf_mask = {
4603                         [PIPE_A] = BIT(DBUF_S1),
4604                         [PIPE_B] = BIT(DBUF_S2),
4605                 },
4606         },
4607         {
4608                 .active_pipes = BIT(PIPE_C),
4609                 .dbuf_mask = {
4610                         [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
4611                 },
4612         },
4613         {
4614                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
4615                 .dbuf_mask = {
4616                         [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
4617                         [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
4618                 },
4619         },
4620         {
4621                 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
4622                 .dbuf_mask = {
4623                         [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),
4624                         [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
4625                 },
4626         },
4627         {
4628                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
4629                 .dbuf_mask = {
4630                         [PIPE_A] = BIT(DBUF_S1),
4631                         [PIPE_B] = BIT(DBUF_S2),
4632                         [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
4633                 },
4634         },
4635         {
4636                 .active_pipes = BIT(PIPE_D),
4637                 .dbuf_mask = {
4638                         [PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4),
4639                 },
4640         },
4641         {
4642                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_D),
4643                 .dbuf_mask = {
4644                         [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
4645                         [PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4),
4646                 },
4647         },
4648         {
4649                 .active_pipes = BIT(PIPE_B) | BIT(PIPE_D),
4650                 .dbuf_mask = {
4651                         [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),
4652                         [PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4),
4653                 },
4654         },
4655         {
4656                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),
4657                 .dbuf_mask = {
4658                         [PIPE_A] = BIT(DBUF_S1),
4659                         [PIPE_B] = BIT(DBUF_S2),
4660                         [PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4),
4661                 },
4662         },
4663         {
4664                 .active_pipes = BIT(PIPE_C) | BIT(PIPE_D),
4665                 .dbuf_mask = {
4666                         [PIPE_C] = BIT(DBUF_S3),
4667                         [PIPE_D] = BIT(DBUF_S4),
4668                 },
4669         },
4670         {
4671                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),
4672                 .dbuf_mask = {
4673                         [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
4674                         [PIPE_C] = BIT(DBUF_S3),
4675                         [PIPE_D] = BIT(DBUF_S4),
4676                 },
4677         },
4678         {
4679                 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
4680                 .dbuf_mask = {
4681                         [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),
4682                         [PIPE_C] = BIT(DBUF_S3),
4683                         [PIPE_D] = BIT(DBUF_S4),
4684                 },
4685         },
4686         {
4687                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
4688                 .dbuf_mask = {
4689                         [PIPE_A] = BIT(DBUF_S1),
4690                         [PIPE_B] = BIT(DBUF_S2),
4691                         [PIPE_C] = BIT(DBUF_S3),
4692                         [PIPE_D] = BIT(DBUF_S4),
4693                 },
4694         },
4695         {}
4696 };
4697
4698 static const struct dbuf_slice_conf_entry adlp_allowed_dbufs[] = {
4699         {
4700                 .active_pipes = BIT(PIPE_A),
4701                 .dbuf_mask = {
4702                         [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4),
4703                 },
4704                 .join_mbus = true,
4705         },
4706         {
4707                 .active_pipes = BIT(PIPE_B),
4708                 .dbuf_mask = {
4709                         [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4),
4710                 },
4711                 .join_mbus = true,
4712         },
4713         {
4714                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
4715                 .dbuf_mask = {
4716                         [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
4717                         [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
4718                 },
4719         },
4720         {
4721                 .active_pipes = BIT(PIPE_C),
4722                 .dbuf_mask = {
4723                         [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
4724                 },
4725         },
4726         {
4727                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
4728                 .dbuf_mask = {
4729                         [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
4730                         [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
4731                 },
4732         },
4733         {
4734                 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
4735                 .dbuf_mask = {
4736                         [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
4737                         [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
4738                 },
4739         },
4740         {
4741                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
4742                 .dbuf_mask = {
4743                         [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
4744                         [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
4745                         [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
4746                 },
4747         },
4748         {
4749                 .active_pipes = BIT(PIPE_D),
4750                 .dbuf_mask = {
4751                         [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
4752                 },
4753         },
4754         {
4755                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_D),
4756                 .dbuf_mask = {
4757                         [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
4758                         [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
4759                 },
4760         },
4761         {
4762                 .active_pipes = BIT(PIPE_B) | BIT(PIPE_D),
4763                 .dbuf_mask = {
4764                         [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
4765                         [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
4766                 },
4767         },
4768         {
4769                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),
4770                 .dbuf_mask = {
4771                         [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
4772                         [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
4773                         [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
4774                 },
4775         },
4776         {
4777                 .active_pipes = BIT(PIPE_C) | BIT(PIPE_D),
4778                 .dbuf_mask = {
4779                         [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
4780                         [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
4781                 },
4782         },
4783         {
4784                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),
4785                 .dbuf_mask = {
4786                         [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
4787                         [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
4788                         [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
4789                 },
4790         },
4791         {
4792                 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
4793                 .dbuf_mask = {
4794                         [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
4795                         [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
4796                         [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
4797                 },
4798         },
4799         {
4800                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
4801                 .dbuf_mask = {
4802                         [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
4803                         [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
4804                         [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
4805                         [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
4806                 },
4807         },
4808         {}
4809
4810 };
4811
4812 static bool check_mbus_joined(u8 active_pipes,
4813                               const struct dbuf_slice_conf_entry *dbuf_slices)
4814 {
4815         int i;
4816
4817         for (i = 0; i < dbuf_slices[i].active_pipes; i++) {
4818                 if (dbuf_slices[i].active_pipes == active_pipes)
4819                         return dbuf_slices[i].join_mbus;
4820         }
4821         return false;
4822 }
4823
4824 static bool adlp_check_mbus_joined(u8 active_pipes)
4825 {
4826         return check_mbus_joined(active_pipes, adlp_allowed_dbufs);
4827 }
4828
4829 static u8 compute_dbuf_slices(enum pipe pipe, u8 active_pipes,
4830                               const struct dbuf_slice_conf_entry *dbuf_slices)
4831 {
4832         int i;
4833
4834         for (i = 0; i < dbuf_slices[i].active_pipes; i++) {
4835                 if (dbuf_slices[i].active_pipes == active_pipes)
4836                         return dbuf_slices[i].dbuf_mask[pipe];
4837         }
4838         return 0;
4839 }
4840
4841 /*
4842  * This function finds an entry with same enabled pipe configuration and
4843  * returns correspondent DBuf slice mask as stated in BSpec for particular
4844  * platform.
4845  */
4846 static u8 icl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes)
4847 {
4848         /*
4849          * FIXME: For ICL this is still a bit unclear as prev BSpec revision
4850          * required calculating "pipe ratio" in order to determine
4851          * if one or two slices can be used for single pipe configurations
4852          * as additional constraint to the existing table.
4853          * However based on recent info, it should be not "pipe ratio"
4854          * but rather ratio between pixel_rate and cdclk with additional
4855          * constants, so for now we are using only table until this is
4856          * clarified. Also this is the reason why crtc_state param is
4857          * still here - we will need it once those additional constraints
4858          * pop up.
4859          */
4860         return compute_dbuf_slices(pipe, active_pipes, icl_allowed_dbufs);
4861 }
4862
4863 static u8 tgl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes)
4864 {
4865         return compute_dbuf_slices(pipe, active_pipes, tgl_allowed_dbufs);
4866 }
4867
4868 static u32 adlp_compute_dbuf_slices(enum pipe pipe, u32 active_pipes)
4869 {
4870         return compute_dbuf_slices(pipe, active_pipes, adlp_allowed_dbufs);
4871 }
4872
4873 static u32 dg2_compute_dbuf_slices(enum pipe pipe, u32 active_pipes)
4874 {
4875         return compute_dbuf_slices(pipe, active_pipes, dg2_allowed_dbufs);
4876 }
4877
4878 static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes)
4879 {
4880         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4881         enum pipe pipe = crtc->pipe;
4882
4883         if (IS_DG2(dev_priv))
4884                 return dg2_compute_dbuf_slices(pipe, active_pipes);
4885         else if (IS_ALDERLAKE_P(dev_priv))
4886                 return adlp_compute_dbuf_slices(pipe, active_pipes);
4887         else if (DISPLAY_VER(dev_priv) == 12)
4888                 return tgl_compute_dbuf_slices(pipe, active_pipes);
4889         else if (DISPLAY_VER(dev_priv) == 11)
4890                 return icl_compute_dbuf_slices(pipe, active_pipes);
4891         /*
4892          * For anything else just return one slice yet.
4893          * Should be extended for other platforms.
4894          */
4895         return active_pipes & BIT(pipe) ? BIT(DBUF_S1) : 0;
4896 }
4897
4898 static u64
4899 skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
4900                              const struct intel_plane_state *plane_state,
4901                              int color_plane)
4902 {
4903         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
4904         const struct drm_framebuffer *fb = plane_state->hw.fb;
4905         u32 data_rate;
4906         u32 width = 0, height = 0;
4907         uint_fixed_16_16_t down_scale_amount;
4908         u64 rate;
4909
4910         if (!plane_state->uapi.visible)
4911                 return 0;
4912
4913         if (plane->id == PLANE_CURSOR)
4914                 return 0;
4915
4916         if (color_plane == 1 &&
4917             !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
4918                 return 0;
4919
4920         /*
4921          * Src coordinates are already rotated by 270 degrees for
4922          * the 90/270 degree plane rotation cases (to match the
4923          * GTT mapping), hence no need to account for rotation here.
4924          */
4925         width = drm_rect_width(&plane_state->uapi.src) >> 16;
4926         height = drm_rect_height(&plane_state->uapi.src) >> 16;
4927
4928         /* UV plane does 1/2 pixel sub-sampling */
4929         if (color_plane == 1) {
4930                 width /= 2;
4931                 height /= 2;
4932         }
4933
4934         data_rate = width * height;
4935
4936         down_scale_amount = skl_plane_downscale_amount(crtc_state, plane_state);
4937
4938         rate = mul_round_up_u32_fixed16(data_rate, down_scale_amount);
4939
4940         rate *= fb->format->cpp[color_plane];
4941         return rate;
4942 }
4943
4944 static u64
4945 skl_get_total_relative_data_rate(struct intel_atomic_state *state,
4946                                  struct intel_crtc *crtc)
4947 {
4948         struct intel_crtc_state *crtc_state =
4949                 intel_atomic_get_new_crtc_state(state, crtc);
4950         const struct intel_plane_state *plane_state;
4951         struct intel_plane *plane;
4952         u64 total_data_rate = 0;
4953         enum plane_id plane_id;
4954         int i;
4955
4956         /* Calculate and cache data rate for each plane */
4957         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4958                 if (plane->pipe != crtc->pipe)
4959                         continue;
4960
4961                 plane_id = plane->id;
4962
4963                 /* packed/y */
4964                 crtc_state->plane_data_rate[plane_id] =
4965                         skl_plane_relative_data_rate(crtc_state, plane_state, 0);
4966
4967                 /* uv-plane */
4968                 crtc_state->uv_plane_data_rate[plane_id] =
4969                         skl_plane_relative_data_rate(crtc_state, plane_state, 1);
4970         }
4971
4972         for_each_plane_id_on_crtc(crtc, plane_id) {
4973                 total_data_rate += crtc_state->plane_data_rate[plane_id];
4974                 total_data_rate += crtc_state->uv_plane_data_rate[plane_id];
4975         }
4976
4977         return total_data_rate;
4978 }
4979
4980 static u64
4981 icl_get_total_relative_data_rate(struct intel_atomic_state *state,
4982                                  struct intel_crtc *crtc)
4983 {
4984         struct intel_crtc_state *crtc_state =
4985                 intel_atomic_get_new_crtc_state(state, crtc);
4986         const struct intel_plane_state *plane_state;
4987         struct intel_plane *plane;
4988         u64 total_data_rate = 0;
4989         enum plane_id plane_id;
4990         int i;
4991
4992         /* Calculate and cache data rate for each plane */
4993         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4994                 if (plane->pipe != crtc->pipe)
4995                         continue;
4996
4997                 plane_id = plane->id;
4998
4999                 if (!plane_state->planar_linked_plane) {
5000                         crtc_state->plane_data_rate[plane_id] =
5001                                 skl_plane_relative_data_rate(crtc_state, plane_state, 0);
5002                 } else {
5003                         enum plane_id y_plane_id;
5004
5005                         /*
5006                          * The slave plane might not iterate in
5007                          * intel_atomic_crtc_state_for_each_plane_state(),
5008                          * and needs the master plane state which may be
5009                          * NULL if we try get_new_plane_state(), so we
5010                          * always calculate from the master.
5011                          */
5012                         if (plane_state->planar_slave)
5013                                 continue;
5014
5015                         /* Y plane rate is calculated on the slave */
5016                         y_plane_id = plane_state->planar_linked_plane->id;
5017                         crtc_state->plane_data_rate[y_plane_id] =
5018                                 skl_plane_relative_data_rate(crtc_state, plane_state, 0);
5019
5020                         crtc_state->plane_data_rate[plane_id] =
5021                                 skl_plane_relative_data_rate(crtc_state, plane_state, 1);
5022                 }
5023         }
5024
5025         for_each_plane_id_on_crtc(crtc, plane_id)
5026                 total_data_rate += crtc_state->plane_data_rate[plane_id];
5027
5028         return total_data_rate;
5029 }
5030
5031 const struct skl_wm_level *
5032 skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm,
5033                    enum plane_id plane_id,
5034                    int level)
5035 {
5036         const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
5037
5038         if (level == 0 && pipe_wm->use_sagv_wm)
5039                 return &wm->sagv.wm0;
5040
5041         return &wm->wm[level];
5042 }
5043
5044 const struct skl_wm_level *
5045 skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm,
5046                    enum plane_id plane_id)
5047 {
5048         const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
5049
5050         if (pipe_wm->use_sagv_wm)
5051                 return &wm->sagv.trans_wm;
5052
5053         return &wm->trans_wm;
5054 }
5055
5056 /*
5057  * We only disable the watermarks for each plane if
5058  * they exceed the ddb allocation of said plane. This
5059  * is done so that we don't end up touching cursor
5060  * watermarks needlessly when some other plane reduces
5061  * our max possible watermark level.
5062  *
5063  * Bspec has this to say about the PLANE_WM enable bit:
5064  * "All the watermarks at this level for all enabled
5065  *  planes must be enabled before the level will be used."
5066  * So this is actually safe to do.
5067  */
5068 static void
5069 skl_check_wm_level(struct skl_wm_level *wm, u64 total)
5070 {
5071         if (wm->min_ddb_alloc > total)
5072                 memset(wm, 0, sizeof(*wm));
5073 }
5074
5075 static void
5076 skl_check_nv12_wm_level(struct skl_wm_level *wm, struct skl_wm_level *uv_wm,
5077                         u64 total, u64 uv_total)
5078 {
5079         if (wm->min_ddb_alloc > total ||
5080             uv_wm->min_ddb_alloc > uv_total) {
5081                 memset(wm, 0, sizeof(*wm));
5082                 memset(uv_wm, 0, sizeof(*uv_wm));
5083         }
5084 }
5085
5086 static int
5087 skl_allocate_plane_ddb(struct intel_atomic_state *state,
5088                        struct intel_crtc *crtc)
5089 {
5090         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5091         struct intel_crtc_state *crtc_state =
5092                 intel_atomic_get_new_crtc_state(state, crtc);
5093         const struct intel_dbuf_state *dbuf_state =
5094                 intel_atomic_get_new_dbuf_state(state);
5095         const struct skl_ddb_entry *alloc = &dbuf_state->ddb[crtc->pipe];
5096         int num_active = hweight8(dbuf_state->active_pipes);
5097         u16 alloc_size, start = 0;
5098         u16 total[I915_MAX_PLANES] = {};
5099         u16 uv_total[I915_MAX_PLANES] = {};
5100         u64 total_data_rate;
5101         enum plane_id plane_id;
5102         u32 blocks;
5103         int level;
5104
5105         /* Clear the partitioning for disabled planes. */
5106         memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y));
5107         memset(crtc_state->wm.skl.plane_ddb_uv, 0, sizeof(crtc_state->wm.skl.plane_ddb_uv));
5108
5109         if (!crtc_state->hw.active)
5110                 return 0;
5111
5112         if (DISPLAY_VER(dev_priv) >= 11)
5113                 total_data_rate =
5114                         icl_get_total_relative_data_rate(state, crtc);
5115         else
5116                 total_data_rate =
5117                         skl_get_total_relative_data_rate(state, crtc);
5118
5119         alloc_size = skl_ddb_entry_size(alloc);
5120         if (alloc_size == 0)
5121                 return 0;
5122
5123         /* Allocate fixed number of blocks for cursor. */
5124         total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
5125         alloc_size -= total[PLANE_CURSOR];
5126         crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
5127                 alloc->end - total[PLANE_CURSOR];
5128         crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
5129
5130         if (total_data_rate == 0)
5131                 return 0;
5132
5133         /*
5134          * Find the highest watermark level for which we can satisfy the block
5135          * requirement of active planes.
5136          */
5137         for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
5138                 blocks = 0;
5139                 for_each_plane_id_on_crtc(crtc, plane_id) {
5140                         const struct skl_plane_wm *wm =
5141                                 &crtc_state->wm.skl.optimal.planes[plane_id];
5142
5143                         if (plane_id == PLANE_CURSOR) {
5144                                 if (wm->wm[level].min_ddb_alloc > total[PLANE_CURSOR]) {
5145                                         drm_WARN_ON(&dev_priv->drm,
5146                                                     wm->wm[level].min_ddb_alloc != U16_MAX);
5147                                         blocks = U32_MAX;
5148                                         break;
5149                                 }
5150                                 continue;
5151                         }
5152
5153                         blocks += wm->wm[level].min_ddb_alloc;
5154                         blocks += wm->uv_wm[level].min_ddb_alloc;
5155                 }
5156
5157                 if (blocks <= alloc_size) {
5158                         alloc_size -= blocks;
5159                         break;
5160                 }
5161         }
5162
5163         if (level < 0) {
5164                 drm_dbg_kms(&dev_priv->drm,
5165                             "Requested display configuration exceeds system DDB limitations");
5166                 drm_dbg_kms(&dev_priv->drm, "minimum required %d/%d\n",
5167                             blocks, alloc_size);
5168                 return -EINVAL;
5169         }
5170
5171         /*
5172          * Grant each plane the blocks it requires at the highest achievable
5173          * watermark level, plus an extra share of the leftover blocks
5174          * proportional to its relative data rate.
5175          */
5176         for_each_plane_id_on_crtc(crtc, plane_id) {
5177                 const struct skl_plane_wm *wm =
5178                         &crtc_state->wm.skl.optimal.planes[plane_id];
5179                 u64 rate;
5180                 u16 extra;
5181
5182                 if (plane_id == PLANE_CURSOR)
5183                         continue;
5184
5185                 /*
5186                  * We've accounted for all active planes; remaining planes are
5187                  * all disabled.
5188                  */
5189                 if (total_data_rate == 0)
5190                         break;
5191
5192                 rate = crtc_state->plane_data_rate[plane_id];
5193                 extra = min_t(u16, alloc_size,
5194                               DIV64_U64_ROUND_UP(alloc_size * rate,
5195                                                  total_data_rate));
5196                 total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
5197                 alloc_size -= extra;
5198                 total_data_rate -= rate;
5199
5200                 if (total_data_rate == 0)
5201                         break;
5202
5203                 rate = crtc_state->uv_plane_data_rate[plane_id];
5204                 extra = min_t(u16, alloc_size,
5205                               DIV64_U64_ROUND_UP(alloc_size * rate,
5206                                                  total_data_rate));
5207                 uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
5208                 alloc_size -= extra;
5209                 total_data_rate -= rate;
5210         }
5211         drm_WARN_ON(&dev_priv->drm, alloc_size != 0 || total_data_rate != 0);
5212
5213         /* Set the actual DDB start/end points for each plane */
5214         start = alloc->start;
5215         for_each_plane_id_on_crtc(crtc, plane_id) {
5216                 struct skl_ddb_entry *plane_alloc =
5217                         &crtc_state->wm.skl.plane_ddb_y[plane_id];
5218                 struct skl_ddb_entry *uv_plane_alloc =
5219                         &crtc_state->wm.skl.plane_ddb_uv[plane_id];
5220
5221                 if (plane_id == PLANE_CURSOR)
5222                         continue;
5223
5224                 /* Gen11+ uses a separate plane for UV watermarks */
5225                 drm_WARN_ON(&dev_priv->drm,
5226                             DISPLAY_VER(dev_priv) >= 11 && uv_total[plane_id]);
5227
5228                 /* Leave disabled planes at (0,0) */
5229                 if (total[plane_id]) {
5230                         plane_alloc->start = start;
5231                         start += total[plane_id];
5232                         plane_alloc->end = start;
5233                 }
5234
5235                 if (uv_total[plane_id]) {
5236                         uv_plane_alloc->start = start;
5237                         start += uv_total[plane_id];
5238                         uv_plane_alloc->end = start;
5239                 }
5240         }
5241
5242         /*
5243          * When we calculated watermark values we didn't know how high
5244          * of a level we'd actually be able to hit, so we just marked
5245          * all levels as "enabled."  Go back now and disable the ones
5246          * that aren't actually possible.
5247          */
5248         for (level++; level <= ilk_wm_max_level(dev_priv); level++) {
5249                 for_each_plane_id_on_crtc(crtc, plane_id) {
5250                         struct skl_plane_wm *wm =
5251                                 &crtc_state->wm.skl.optimal.planes[plane_id];
5252
5253                         skl_check_nv12_wm_level(&wm->wm[level], &wm->uv_wm[level],
5254                                                 total[plane_id], uv_total[plane_id]);
5255
5256                         /*
5257                          * Wa_1408961008:icl, ehl
5258                          * Underruns with WM1+ disabled
5259                          */
5260                         if (DISPLAY_VER(dev_priv) == 11 &&
5261                             level == 1 && wm->wm[0].enable) {
5262                                 wm->wm[level].blocks = wm->wm[0].blocks;
5263                                 wm->wm[level].lines = wm->wm[0].lines;
5264                                 wm->wm[level].ignore_lines = wm->wm[0].ignore_lines;
5265                         }
5266                 }
5267         }
5268
5269         /*
5270          * Go back and disable the transition and SAGV watermarks
5271          * if it turns out we don't have enough DDB blocks for them.
5272          */
5273         for_each_plane_id_on_crtc(crtc, plane_id) {
5274                 struct skl_plane_wm *wm =
5275                         &crtc_state->wm.skl.optimal.planes[plane_id];
5276
5277                 skl_check_wm_level(&wm->trans_wm, total[plane_id]);
5278                 skl_check_wm_level(&wm->sagv.wm0, total[plane_id]);
5279                 skl_check_wm_level(&wm->sagv.trans_wm, total[plane_id]);
5280         }
5281
5282         return 0;
5283 }
5284
5285 /*
5286  * The max latency should be 257 (max the punit can code is 255 and we add 2us
5287  * for the read latency) and cpp should always be <= 8, so that
5288  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
5289  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
5290 */
5291 static uint_fixed_16_16_t
5292 skl_wm_method1(const struct drm_i915_private *dev_priv, u32 pixel_rate,
5293                u8 cpp, u32 latency, u32 dbuf_block_size)
5294 {
5295         u32 wm_intermediate_val;
5296         uint_fixed_16_16_t ret;
5297
5298         if (latency == 0)
5299                 return FP_16_16_MAX;
5300
5301         wm_intermediate_val = latency * pixel_rate * cpp;
5302         ret = div_fixed16(wm_intermediate_val, 1000 * dbuf_block_size);
5303
5304         if (DISPLAY_VER(dev_priv) >= 10)
5305                 ret = add_fixed16_u32(ret, 1);
5306
5307         return ret;
5308 }
5309
5310 static uint_fixed_16_16_t
5311 skl_wm_method2(u32 pixel_rate, u32 pipe_htotal, u32 latency,
5312                uint_fixed_16_16_t plane_blocks_per_line)
5313 {
5314         u32 wm_intermediate_val;
5315         uint_fixed_16_16_t ret;
5316
5317         if (latency == 0)
5318                 return FP_16_16_MAX;
5319
5320         wm_intermediate_val = latency * pixel_rate;
5321         wm_intermediate_val = DIV_ROUND_UP(wm_intermediate_val,
5322                                            pipe_htotal * 1000);
5323         ret = mul_u32_fixed16(wm_intermediate_val, plane_blocks_per_line);
5324         return ret;
5325 }
5326
5327 static uint_fixed_16_16_t
5328 intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
5329 {
5330         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
5331         u32 pixel_rate;
5332         u32 crtc_htotal;
5333         uint_fixed_16_16_t linetime_us;
5334
5335         if (!crtc_state->hw.active)
5336                 return u32_to_fixed16(0);
5337
5338         pixel_rate = crtc_state->pixel_rate;
5339
5340         if (drm_WARN_ON(&dev_priv->drm, pixel_rate == 0))
5341                 return u32_to_fixed16(0);
5342
5343         crtc_htotal = crtc_state->hw.pipe_mode.crtc_htotal;
5344         linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate);
5345
5346         return linetime_us;
5347 }
5348
5349 static int
5350 skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
5351                       int width, const struct drm_format_info *format,
5352                       u64 modifier, unsigned int rotation,
5353                       u32 plane_pixel_rate, struct skl_wm_params *wp,
5354                       int color_plane)
5355 {
5356         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5357         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5358         u32 interm_pbpl;
5359
5360         /* only planar format has two planes */
5361         if (color_plane == 1 &&
5362             !intel_format_info_is_yuv_semiplanar(format, modifier)) {
5363                 drm_dbg_kms(&dev_priv->drm,
5364                             "Non planar format have single plane\n");
5365                 return -EINVAL;
5366         }
5367
5368         wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
5369                       modifier == I915_FORMAT_MOD_Yf_TILED ||
5370                       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
5371                       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
5372         wp->x_tiled = modifier == I915_FORMAT_MOD_X_TILED;
5373         wp->rc_surface = modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
5374                          modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
5375         wp->is_planar = intel_format_info_is_yuv_semiplanar(format, modifier);
5376
5377         wp->width = width;
5378         if (color_plane == 1 && wp->is_planar)
5379                 wp->width /= 2;
5380
5381         wp->cpp = format->cpp[color_plane];
5382         wp->plane_pixel_rate = plane_pixel_rate;
5383
5384         if (DISPLAY_VER(dev_priv) >= 11 &&
5385             modifier == I915_FORMAT_MOD_Yf_TILED  && wp->cpp == 1)
5386                 wp->dbuf_block_size = 256;
5387         else
5388                 wp->dbuf_block_size = 512;
5389
5390         if (drm_rotation_90_or_270(rotation)) {
5391                 switch (wp->cpp) {
5392                 case 1:
5393                         wp->y_min_scanlines = 16;
5394                         break;
5395                 case 2:
5396                         wp->y_min_scanlines = 8;
5397                         break;
5398                 case 4:
5399                         wp->y_min_scanlines = 4;
5400                         break;
5401                 default:
5402                         MISSING_CASE(wp->cpp);
5403                         return -EINVAL;
5404                 }
5405         } else {
5406                 wp->y_min_scanlines = 4;
5407         }
5408
5409         if (skl_needs_memory_bw_wa(dev_priv))
5410                 wp->y_min_scanlines *= 2;
5411
5412         wp->plane_bytes_per_line = wp->width * wp->cpp;
5413         if (wp->y_tiled) {
5414                 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line *
5415                                            wp->y_min_scanlines,
5416                                            wp->dbuf_block_size);
5417
5418                 if (DISPLAY_VER(dev_priv) >= 10)
5419                         interm_pbpl++;
5420
5421                 wp->plane_blocks_per_line = div_fixed16(interm_pbpl,
5422                                                         wp->y_min_scanlines);
5423         } else {
5424                 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
5425                                            wp->dbuf_block_size);
5426
5427                 if (!wp->x_tiled || DISPLAY_VER(dev_priv) >= 10)
5428                         interm_pbpl++;
5429
5430                 wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
5431         }
5432
5433         wp->y_tile_minimum = mul_u32_fixed16(wp->y_min_scanlines,
5434                                              wp->plane_blocks_per_line);
5435
5436         wp->linetime_us = fixed16_to_u32_round_up(
5437                                         intel_get_linetime_us(crtc_state));
5438
5439         return 0;
5440 }
5441
5442 static int
5443 skl_compute_plane_wm_params(const struct intel_crtc_state *crtc_state,
5444                             const struct intel_plane_state *plane_state,
5445                             struct skl_wm_params *wp, int color_plane)
5446 {
5447         const struct drm_framebuffer *fb = plane_state->hw.fb;
5448         int width;
5449
5450         /*
5451          * Src coordinates are already rotated by 270 degrees for
5452          * the 90/270 degree plane rotation cases (to match the
5453          * GTT mapping), hence no need to account for rotation here.
5454          */
5455         width = drm_rect_width(&plane_state->uapi.src) >> 16;
5456
5457         return skl_compute_wm_params(crtc_state, width,
5458                                      fb->format, fb->modifier,
5459                                      plane_state->hw.rotation,
5460                                      intel_plane_pixel_rate(crtc_state, plane_state),
5461                                      wp, color_plane);
5462 }
5463
5464 static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level)
5465 {
5466         if (DISPLAY_VER(dev_priv) >= 10)
5467                 return true;
5468
5469         /* The number of lines are ignored for the level 0 watermark. */
5470         return level > 0;
5471 }
5472
5473 static int skl_wm_max_lines(struct drm_i915_private *dev_priv)
5474 {
5475         if (DISPLAY_VER(dev_priv) >= 13)
5476                 return 255;
5477         else
5478                 return 31;
5479 }
5480
5481 static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
5482                                  int level,
5483                                  unsigned int latency,
5484                                  const struct skl_wm_params *wp,
5485                                  const struct skl_wm_level *result_prev,
5486                                  struct skl_wm_level *result /* out */)
5487 {
5488         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
5489         uint_fixed_16_16_t method1, method2;
5490         uint_fixed_16_16_t selected_result;
5491         u32 blocks, lines, min_ddb_alloc = 0;
5492
5493         if (latency == 0) {
5494                 /* reject it */
5495                 result->min_ddb_alloc = U16_MAX;
5496                 return;
5497         }
5498
5499         /*
5500          * WaIncreaseLatencyIPCEnabled: kbl,cfl
5501          * Display WA #1141: kbl,cfl
5502          */
5503         if ((IS_KABYLAKE(dev_priv) ||
5504              IS_COFFEELAKE(dev_priv) ||
5505              IS_COMETLAKE(dev_priv)) &&
5506             dev_priv->ipc_enabled)
5507                 latency += 4;
5508
5509         if (skl_needs_memory_bw_wa(dev_priv) && wp->x_tiled)
5510                 latency += 15;
5511
5512         method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
5513                                  wp->cpp, latency, wp->dbuf_block_size);
5514         method2 = skl_wm_method2(wp->plane_pixel_rate,
5515                                  crtc_state->hw.pipe_mode.crtc_htotal,
5516                                  latency,
5517                                  wp->plane_blocks_per_line);
5518
5519         if (wp->y_tiled) {
5520                 selected_result = max_fixed16(method2, wp->y_tile_minimum);
5521         } else {
5522                 if ((wp->cpp * crtc_state->hw.pipe_mode.crtc_htotal /
5523                      wp->dbuf_block_size < 1) &&
5524                      (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
5525                         selected_result = method2;
5526                 } else if (latency >= wp->linetime_us) {
5527                         if (DISPLAY_VER(dev_priv) == 9)
5528                                 selected_result = min_fixed16(method1, method2);
5529                         else
5530                                 selected_result = method2;
5531                 } else {
5532                         selected_result = method1;
5533                 }
5534         }
5535
5536         blocks = fixed16_to_u32_round_up(selected_result) + 1;
5537         lines = div_round_up_fixed16(selected_result,
5538                                      wp->plane_blocks_per_line);
5539
5540         if (DISPLAY_VER(dev_priv) == 9) {
5541                 /* Display WA #1125: skl,bxt,kbl */
5542                 if (level == 0 && wp->rc_surface)
5543                         blocks += fixed16_to_u32_round_up(wp->y_tile_minimum);
5544
5545                 /* Display WA #1126: skl,bxt,kbl */
5546                 if (level >= 1 && level <= 7) {
5547                         if (wp->y_tiled) {
5548                                 blocks += fixed16_to_u32_round_up(wp->y_tile_minimum);
5549                                 lines += wp->y_min_scanlines;
5550                         } else {
5551                                 blocks++;
5552                         }
5553
5554                         /*
5555                          * Make sure result blocks for higher latency levels are
5556                          * atleast as high as level below the current level.
5557                          * Assumption in DDB algorithm optimization for special
5558                          * cases. Also covers Display WA #1125 for RC.
5559                          */
5560                         if (result_prev->blocks > blocks)
5561                                 blocks = result_prev->blocks;
5562                 }
5563         }
5564
5565         if (DISPLAY_VER(dev_priv) >= 11) {
5566                 if (wp->y_tiled) {
5567                         int extra_lines;
5568
5569                         if (lines % wp->y_min_scanlines == 0)
5570                                 extra_lines = wp->y_min_scanlines;
5571                         else
5572                                 extra_lines = wp->y_min_scanlines * 2 -
5573                                         lines % wp->y_min_scanlines;
5574
5575                         min_ddb_alloc = mul_round_up_u32_fixed16(lines + extra_lines,
5576                                                                  wp->plane_blocks_per_line);
5577                 } else {
5578                         min_ddb_alloc = blocks + DIV_ROUND_UP(blocks, 10);
5579                 }
5580         }
5581
5582         if (!skl_wm_has_lines(dev_priv, level))
5583                 lines = 0;
5584
5585         if (lines > skl_wm_max_lines(dev_priv)) {
5586                 /* reject it */
5587                 result->min_ddb_alloc = U16_MAX;
5588                 return;
5589         }
5590
5591         /*
5592          * If lines is valid, assume we can use this watermark level
5593          * for now.  We'll come back and disable it after we calculate the
5594          * DDB allocation if it turns out we don't actually have enough
5595          * blocks to satisfy it.
5596          */
5597         result->blocks = blocks;
5598         result->lines = lines;
5599         /* Bspec says: value >= plane ddb allocation -> invalid, hence the +1 here */
5600         result->min_ddb_alloc = max(min_ddb_alloc, blocks) + 1;
5601         result->enable = true;
5602
5603         if (DISPLAY_VER(dev_priv) < 12)
5604                 result->can_sagv = latency >= dev_priv->sagv_block_time_us;
5605 }
5606
5607 static void
5608 skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
5609                       const struct skl_wm_params *wm_params,
5610                       struct skl_wm_level *levels)
5611 {
5612         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
5613         int level, max_level = ilk_wm_max_level(dev_priv);
5614         struct skl_wm_level *result_prev = &levels[0];
5615
5616         for (level = 0; level <= max_level; level++) {
5617                 struct skl_wm_level *result = &levels[level];
5618                 unsigned int latency = dev_priv->wm.skl_latency[level];
5619
5620                 skl_compute_plane_wm(crtc_state, level, latency,
5621                                      wm_params, result_prev, result);
5622
5623                 result_prev = result;
5624         }
5625 }
5626
5627 static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
5628                                 const struct skl_wm_params *wm_params,
5629                                 struct skl_plane_wm *plane_wm)
5630 {
5631         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
5632         struct skl_wm_level *sagv_wm = &plane_wm->sagv.wm0;
5633         struct skl_wm_level *levels = plane_wm->wm;
5634         unsigned int latency = dev_priv->wm.skl_latency[0] + dev_priv->sagv_block_time_us;
5635
5636         skl_compute_plane_wm(crtc_state, 0, latency,
5637                              wm_params, &levels[0],
5638                              sagv_wm);
5639 }
5640
5641 static void skl_compute_transition_wm(struct drm_i915_private *dev_priv,
5642                                       struct skl_wm_level *trans_wm,
5643                                       const struct skl_wm_level *wm0,
5644                                       const struct skl_wm_params *wp)
5645 {
5646         u16 trans_min, trans_amount, trans_y_tile_min;
5647         u16 wm0_blocks, trans_offset, blocks;
5648
5649         /* Transition WM don't make any sense if ipc is disabled */
5650         if (!dev_priv->ipc_enabled)
5651                 return;
5652
5653         /*
5654          * WaDisableTWM:skl,kbl,cfl,bxt
5655          * Transition WM are not recommended by HW team for GEN9
5656          */
5657         if (DISPLAY_VER(dev_priv) == 9)
5658                 return;
5659
5660         if (DISPLAY_VER(dev_priv) >= 11)
5661                 trans_min = 4;
5662         else
5663                 trans_min = 14;
5664
5665         /* Display WA #1140: glk,cnl */
5666         if (DISPLAY_VER(dev_priv) == 10)
5667                 trans_amount = 0;
5668         else
5669                 trans_amount = 10; /* This is configurable amount */
5670
5671         trans_offset = trans_min + trans_amount;
5672
5673         /*
5674          * The spec asks for Selected Result Blocks for wm0 (the real value),
5675          * not Result Blocks (the integer value). Pay attention to the capital
5676          * letters. The value wm_l0->blocks is actually Result Blocks, but
5677          * since Result Blocks is the ceiling of Selected Result Blocks plus 1,
5678          * and since we later will have to get the ceiling of the sum in the
5679          * transition watermarks calculation, we can just pretend Selected
5680          * Result Blocks is Result Blocks minus 1 and it should work for the
5681          * current platforms.
5682          */
5683         wm0_blocks = wm0->blocks - 1;
5684
5685         if (wp->y_tiled) {
5686                 trans_y_tile_min =
5687                         (u16)mul_round_up_u32_fixed16(2, wp->y_tile_minimum);
5688                 blocks = max(wm0_blocks, trans_y_tile_min) + trans_offset;
5689         } else {
5690                 blocks = wm0_blocks + trans_offset;
5691         }
5692         blocks++;
5693
5694         /*
5695          * Just assume we can enable the transition watermark.  After
5696          * computing the DDB we'll come back and disable it if that
5697          * assumption turns out to be false.
5698          */
5699         trans_wm->blocks = blocks;
5700         trans_wm->min_ddb_alloc = max_t(u16, wm0->min_ddb_alloc, blocks + 1);
5701         trans_wm->enable = true;
5702 }
5703
5704 static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
5705                                      const struct intel_plane_state *plane_state,
5706                                      enum plane_id plane_id, int color_plane)
5707 {
5708         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5709         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5710         struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
5711         struct skl_wm_params wm_params;
5712         int ret;
5713
5714         ret = skl_compute_plane_wm_params(crtc_state, plane_state,
5715                                           &wm_params, color_plane);
5716         if (ret)
5717                 return ret;
5718
5719         skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
5720
5721         skl_compute_transition_wm(dev_priv, &wm->trans_wm,
5722                                   &wm->wm[0], &wm_params);
5723
5724         if (DISPLAY_VER(dev_priv) >= 12) {
5725                 tgl_compute_sagv_wm(crtc_state, &wm_params, wm);
5726
5727                 skl_compute_transition_wm(dev_priv, &wm->sagv.trans_wm,
5728                                           &wm->sagv.wm0, &wm_params);
5729         }
5730
5731         return 0;
5732 }
5733
5734 static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
5735                                  const struct intel_plane_state *plane_state,
5736                                  enum plane_id plane_id)
5737 {
5738         struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
5739         struct skl_wm_params wm_params;
5740         int ret;
5741
5742         wm->is_planar = true;
5743
5744         /* uv plane watermarks must also be validated for NV12/Planar */
5745         ret = skl_compute_plane_wm_params(crtc_state, plane_state,
5746                                           &wm_params, 1);
5747         if (ret)
5748                 return ret;
5749
5750         skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
5751
5752         return 0;
5753 }
5754
5755 static int skl_build_plane_wm(struct intel_crtc_state *crtc_state,
5756                               const struct intel_plane_state *plane_state)
5757 {
5758         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
5759         enum plane_id plane_id = plane->id;
5760         struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
5761         const struct drm_framebuffer *fb = plane_state->hw.fb;
5762         int ret;
5763
5764         memset(wm, 0, sizeof(*wm));
5765
5766         if (!intel_wm_plane_visible(crtc_state, plane_state))
5767                 return 0;
5768
5769         ret = skl_build_plane_wm_single(crtc_state, plane_state,
5770                                         plane_id, 0);
5771         if (ret)
5772                 return ret;
5773
5774         if (fb->format->is_yuv && fb->format->num_planes > 1) {
5775                 ret = skl_build_plane_wm_uv(crtc_state, plane_state,
5776                                             plane_id);
5777                 if (ret)
5778                         return ret;
5779         }
5780
5781         return 0;
5782 }
5783
5784 static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
5785                               const struct intel_plane_state *plane_state)
5786 {
5787         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
5788         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
5789         enum plane_id plane_id = plane->id;
5790         struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
5791         int ret;
5792
5793         /* Watermarks calculated in master */
5794         if (plane_state->planar_slave)
5795                 return 0;
5796
5797         memset(wm, 0, sizeof(*wm));
5798
5799         if (plane_state->planar_linked_plane) {
5800                 const struct drm_framebuffer *fb = plane_state->hw.fb;
5801                 enum plane_id y_plane_id = plane_state->planar_linked_plane->id;
5802
5803                 drm_WARN_ON(&dev_priv->drm,
5804                             !intel_wm_plane_visible(crtc_state, plane_state));
5805                 drm_WARN_ON(&dev_priv->drm, !fb->format->is_yuv ||
5806                             fb->format->num_planes == 1);
5807
5808                 ret = skl_build_plane_wm_single(crtc_state, plane_state,
5809                                                 y_plane_id, 0);
5810                 if (ret)
5811                         return ret;
5812
5813                 ret = skl_build_plane_wm_single(crtc_state, plane_state,
5814                                                 plane_id, 1);
5815                 if (ret)
5816                         return ret;
5817         } else if (intel_wm_plane_visible(crtc_state, plane_state)) {
5818                 ret = skl_build_plane_wm_single(crtc_state, plane_state,
5819                                                 plane_id, 0);
5820                 if (ret)
5821                         return ret;
5822         }
5823
5824         return 0;
5825 }
5826
5827 static int skl_build_pipe_wm(struct intel_atomic_state *state,
5828                              struct intel_crtc *crtc)
5829 {
5830         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5831         struct intel_crtc_state *crtc_state =
5832                 intel_atomic_get_new_crtc_state(state, crtc);
5833         const struct intel_plane_state *plane_state;
5834         struct intel_plane *plane;
5835         int ret, i;
5836
5837         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
5838                 /*
5839                  * FIXME should perhaps check {old,new}_plane_crtc->hw.crtc
5840                  * instead but we don't populate that correctly for NV12 Y
5841                  * planes so for now hack this.
5842                  */
5843                 if (plane->pipe != crtc->pipe)
5844                         continue;
5845
5846                 if (DISPLAY_VER(dev_priv) >= 11)
5847                         ret = icl_build_plane_wm(crtc_state, plane_state);
5848                 else
5849                         ret = skl_build_plane_wm(crtc_state, plane_state);
5850                 if (ret)
5851                         return ret;
5852         }
5853
5854         crtc_state->wm.skl.optimal = crtc_state->wm.skl.raw;
5855
5856         return 0;
5857 }
5858
5859 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
5860                                 i915_reg_t reg,
5861                                 const struct skl_ddb_entry *entry)
5862 {
5863         if (entry->end)
5864                 intel_de_write_fw(dev_priv, reg,
5865                                   (entry->end - 1) << 16 | entry->start);
5866         else
5867                 intel_de_write_fw(dev_priv, reg, 0);
5868 }
5869
5870 static void skl_write_wm_level(struct drm_i915_private *dev_priv,
5871                                i915_reg_t reg,
5872                                const struct skl_wm_level *level)
5873 {
5874         u32 val = 0;
5875
5876         if (level->enable)
5877                 val |= PLANE_WM_EN;
5878         if (level->ignore_lines)
5879                 val |= PLANE_WM_IGNORE_LINES;
5880         val |= level->blocks;
5881         val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines);
5882
5883         intel_de_write_fw(dev_priv, reg, val);
5884 }
5885
5886 void skl_write_plane_wm(struct intel_plane *plane,
5887                         const struct intel_crtc_state *crtc_state)
5888 {
5889         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
5890         int level, max_level = ilk_wm_max_level(dev_priv);
5891         enum plane_id plane_id = plane->id;
5892         enum pipe pipe = plane->pipe;
5893         const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
5894         const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
5895         const struct skl_ddb_entry *ddb_y =
5896                 &crtc_state->wm.skl.plane_ddb_y[plane_id];
5897         const struct skl_ddb_entry *ddb_uv =
5898                 &crtc_state->wm.skl.plane_ddb_uv[plane_id];
5899
5900         for (level = 0; level <= max_level; level++)
5901                 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
5902                                    skl_plane_wm_level(pipe_wm, plane_id, level));
5903
5904         skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
5905                            skl_plane_trans_wm(pipe_wm, plane_id));
5906
5907         if (HAS_HW_SAGV_WM(dev_priv)) {
5908                 skl_write_wm_level(dev_priv, PLANE_WM_SAGV(pipe, plane_id),
5909                                    &wm->sagv.wm0);
5910                 skl_write_wm_level(dev_priv, PLANE_WM_SAGV_TRANS(pipe, plane_id),
5911                                    &wm->sagv.trans_wm);
5912         }
5913
5914         if (DISPLAY_VER(dev_priv) >= 11) {
5915                 skl_ddb_entry_write(dev_priv,
5916                                     PLANE_BUF_CFG(pipe, plane_id), ddb_y);
5917                 return;
5918         }
5919
5920         if (wm->is_planar)
5921                 swap(ddb_y, ddb_uv);
5922
5923         skl_ddb_entry_write(dev_priv,
5924                             PLANE_BUF_CFG(pipe, plane_id), ddb_y);
5925         skl_ddb_entry_write(dev_priv,
5926                             PLANE_NV12_BUF_CFG(pipe, plane_id), ddb_uv);
5927 }
5928
5929 void skl_write_cursor_wm(struct intel_plane *plane,
5930                          const struct intel_crtc_state *crtc_state)
5931 {
5932         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
5933         int level, max_level = ilk_wm_max_level(dev_priv);
5934         enum plane_id plane_id = plane->id;
5935         enum pipe pipe = plane->pipe;
5936         const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
5937         const struct skl_ddb_entry *ddb =
5938                 &crtc_state->wm.skl.plane_ddb_y[plane_id];
5939
5940         for (level = 0; level <= max_level; level++)
5941                 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
5942                                    skl_plane_wm_level(pipe_wm, plane_id, level));
5943
5944         skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe),
5945                            skl_plane_trans_wm(pipe_wm, plane_id));
5946
5947         if (HAS_HW_SAGV_WM(dev_priv)) {
5948                 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
5949
5950                 skl_write_wm_level(dev_priv, CUR_WM_SAGV(pipe),
5951                                    &wm->sagv.wm0);
5952                 skl_write_wm_level(dev_priv, CUR_WM_SAGV_TRANS(pipe),
5953                                    &wm->sagv.trans_wm);
5954         }
5955
5956         skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), ddb);
5957 }
5958
5959 bool skl_wm_level_equals(const struct skl_wm_level *l1,
5960                          const struct skl_wm_level *l2)
5961 {
5962         return l1->enable == l2->enable &&
5963                 l1->ignore_lines == l2->ignore_lines &&
5964                 l1->lines == l2->lines &&
5965                 l1->blocks == l2->blocks;
5966 }
5967
5968 static bool skl_plane_wm_equals(struct drm_i915_private *dev_priv,
5969                                 const struct skl_plane_wm *wm1,
5970                                 const struct skl_plane_wm *wm2)
5971 {
5972         int level, max_level = ilk_wm_max_level(dev_priv);
5973
5974         for (level = 0; level <= max_level; level++) {
5975                 /*
5976                  * We don't check uv_wm as the hardware doesn't actually
5977                  * use it. It only gets used for calculating the required
5978                  * ddb allocation.
5979                  */
5980                 if (!skl_wm_level_equals(&wm1->wm[level], &wm2->wm[level]))
5981                         return false;
5982         }
5983
5984         return skl_wm_level_equals(&wm1->trans_wm, &wm2->trans_wm) &&
5985                 skl_wm_level_equals(&wm1->sagv.wm0, &wm2->sagv.wm0) &&
5986                 skl_wm_level_equals(&wm1->sagv.trans_wm, &wm2->sagv.trans_wm);
5987 }
5988
5989 static bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
5990                                     const struct skl_ddb_entry *b)
5991 {
5992         return a->start < b->end && b->start < a->end;
5993 }
5994
5995 static void skl_ddb_entry_union(struct skl_ddb_entry *a,
5996                                 const struct skl_ddb_entry *b)
5997 {
5998         if (a->end && b->end) {
5999                 a->start = min(a->start, b->start);
6000                 a->end = max(a->end, b->end);
6001         } else if (b->end) {
6002                 a->start = b->start;
6003                 a->end = b->end;
6004         }
6005 }
6006
6007 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
6008                                  const struct skl_ddb_entry *entries,
6009                                  int num_entries, int ignore_idx)
6010 {
6011         int i;
6012
6013         for (i = 0; i < num_entries; i++) {
6014                 if (i != ignore_idx &&
6015                     skl_ddb_entries_overlap(ddb, &entries[i]))
6016                         return true;
6017         }
6018
6019         return false;
6020 }
6021
6022 static int
6023 skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
6024                             struct intel_crtc_state *new_crtc_state)
6025 {
6026         struct intel_atomic_state *state = to_intel_atomic_state(new_crtc_state->uapi.state);
6027         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6028         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6029         struct intel_plane *plane;
6030
6031         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
6032                 struct intel_plane_state *plane_state;
6033                 enum plane_id plane_id = plane->id;
6034
6035                 if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id],
6036                                         &new_crtc_state->wm.skl.plane_ddb_y[plane_id]) &&
6037                     skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_uv[plane_id],
6038                                         &new_crtc_state->wm.skl.plane_ddb_uv[plane_id]))
6039                         continue;
6040
6041                 plane_state = intel_atomic_get_plane_state(state, plane);
6042                 if (IS_ERR(plane_state))
6043                         return PTR_ERR(plane_state);
6044
6045                 new_crtc_state->update_planes |= BIT(plane_id);
6046         }
6047
6048         return 0;
6049 }
6050
6051 static u8 intel_dbuf_enabled_slices(const struct intel_dbuf_state *dbuf_state)
6052 {
6053         struct drm_i915_private *dev_priv = to_i915(dbuf_state->base.state->base.dev);
6054         u8 enabled_slices;
6055         enum pipe pipe;
6056
6057         /*
6058          * FIXME: For now we always enable slice S1 as per
6059          * the Bspec display initialization sequence.
6060          */
6061         enabled_slices = BIT(DBUF_S1);
6062
6063         for_each_pipe(dev_priv, pipe)
6064                 enabled_slices |= dbuf_state->slices[pipe];
6065
6066         return enabled_slices;
6067 }
6068
6069 static int
6070 skl_compute_ddb(struct intel_atomic_state *state)
6071 {
6072         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6073         const struct intel_dbuf_state *old_dbuf_state;
6074         struct intel_dbuf_state *new_dbuf_state = NULL;
6075         const struct intel_crtc_state *old_crtc_state;
6076         struct intel_crtc_state *new_crtc_state;
6077         struct intel_crtc *crtc;
6078         int ret, i;
6079
6080         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6081                 new_dbuf_state = intel_atomic_get_dbuf_state(state);
6082                 if (IS_ERR(new_dbuf_state))
6083                         return PTR_ERR(new_dbuf_state);
6084
6085                 old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
6086                 break;
6087         }
6088
6089         if (!new_dbuf_state)
6090                 return 0;
6091
6092         new_dbuf_state->active_pipes =
6093                 intel_calc_active_pipes(state, old_dbuf_state->active_pipes);
6094
6095         if (old_dbuf_state->active_pipes != new_dbuf_state->active_pipes) {
6096                 ret = intel_atomic_lock_global_state(&new_dbuf_state->base);
6097                 if (ret)
6098                         return ret;
6099         }
6100
6101         for_each_intel_crtc(&dev_priv->drm, crtc) {
6102                 enum pipe pipe = crtc->pipe;
6103
6104                 new_dbuf_state->slices[pipe] =
6105                         skl_compute_dbuf_slices(crtc, new_dbuf_state->active_pipes);
6106
6107                 if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe])
6108                         continue;
6109
6110                 ret = intel_atomic_lock_global_state(&new_dbuf_state->base);
6111                 if (ret)
6112                         return ret;
6113         }
6114
6115         new_dbuf_state->enabled_slices = intel_dbuf_enabled_slices(new_dbuf_state);
6116
6117         if (IS_ALDERLAKE_P(dev_priv))
6118                 new_dbuf_state->joined_mbus = adlp_check_mbus_joined(new_dbuf_state->active_pipes);
6119
6120         if (old_dbuf_state->enabled_slices != new_dbuf_state->enabled_slices ||
6121             old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) {
6122                 ret = intel_atomic_serialize_global_state(&new_dbuf_state->base);
6123                 if (ret)
6124                         return ret;
6125
6126                 if (old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) {
6127                         /* TODO: Implement vblank synchronized MBUS joining changes */
6128                         ret = intel_modeset_all_pipes(state);
6129                         if (ret)
6130                                 return ret;
6131                 }
6132
6133                 drm_dbg_kms(&dev_priv->drm,
6134                             "Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x), mbus joined? %s->%s\n",
6135                             old_dbuf_state->enabled_slices,
6136                             new_dbuf_state->enabled_slices,
6137                             INTEL_INFO(dev_priv)->dbuf.slice_mask,
6138                             yesno(old_dbuf_state->joined_mbus),
6139                             yesno(new_dbuf_state->joined_mbus));
6140         }
6141
6142         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6143                 enum pipe pipe = crtc->pipe;
6144
6145                 new_dbuf_state->weight[pipe] = intel_crtc_ddb_weight(new_crtc_state);
6146
6147                 if (old_dbuf_state->weight[pipe] == new_dbuf_state->weight[pipe])
6148                         continue;
6149
6150                 ret = intel_atomic_lock_global_state(&new_dbuf_state->base);
6151                 if (ret)
6152                         return ret;
6153         }
6154
6155         for_each_intel_crtc(&dev_priv->drm, crtc) {
6156                 ret = skl_crtc_allocate_ddb(state, crtc);
6157                 if (ret)
6158                         return ret;
6159         }
6160
6161         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6162                                             new_crtc_state, i) {
6163                 ret = skl_allocate_plane_ddb(state, crtc);
6164                 if (ret)
6165                         return ret;
6166
6167                 ret = skl_ddb_add_affected_planes(old_crtc_state,
6168                                                   new_crtc_state);
6169                 if (ret)
6170                         return ret;
6171         }
6172
6173         return 0;
6174 }
6175
6176 static char enast(bool enable)
6177 {
6178         return enable ? '*' : ' ';
6179 }
6180
6181 static void
6182 skl_print_wm_changes(struct intel_atomic_state *state)
6183 {
6184         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6185         const struct intel_crtc_state *old_crtc_state;
6186         const struct intel_crtc_state *new_crtc_state;
6187         struct intel_plane *plane;
6188         struct intel_crtc *crtc;
6189         int i;
6190
6191         if (!drm_debug_enabled(DRM_UT_KMS))
6192                 return;
6193
6194         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6195                                             new_crtc_state, i) {
6196                 const struct skl_pipe_wm *old_pipe_wm, *new_pipe_wm;
6197
6198                 old_pipe_wm = &old_crtc_state->wm.skl.optimal;
6199                 new_pipe_wm = &new_crtc_state->wm.skl.optimal;
6200
6201                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
6202                         enum plane_id plane_id = plane->id;
6203                         const struct skl_ddb_entry *old, *new;
6204
6205                         old = &old_crtc_state->wm.skl.plane_ddb_y[plane_id];
6206                         new = &new_crtc_state->wm.skl.plane_ddb_y[plane_id];
6207
6208                         if (skl_ddb_entry_equal(old, new))
6209                                 continue;
6210
6211                         drm_dbg_kms(&dev_priv->drm,
6212                                     "[PLANE:%d:%s] ddb (%4d - %4d) -> (%4d - %4d), size %4d -> %4d\n",
6213                                     plane->base.base.id, plane->base.name,
6214                                     old->start, old->end, new->start, new->end,
6215                                     skl_ddb_entry_size(old), skl_ddb_entry_size(new));
6216                 }
6217
6218                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
6219                         enum plane_id plane_id = plane->id;
6220                         const struct skl_plane_wm *old_wm, *new_wm;
6221
6222                         old_wm = &old_pipe_wm->planes[plane_id];
6223                         new_wm = &new_pipe_wm->planes[plane_id];
6224
6225                         if (skl_plane_wm_equals(dev_priv, old_wm, new_wm))
6226                                 continue;
6227
6228                         drm_dbg_kms(&dev_priv->drm,
6229                                     "[PLANE:%d:%s]   level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm"
6230                                     " -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm\n",
6231                                     plane->base.base.id, plane->base.name,
6232                                     enast(old_wm->wm[0].enable), enast(old_wm->wm[1].enable),
6233                                     enast(old_wm->wm[2].enable), enast(old_wm->wm[3].enable),
6234                                     enast(old_wm->wm[4].enable), enast(old_wm->wm[5].enable),
6235                                     enast(old_wm->wm[6].enable), enast(old_wm->wm[7].enable),
6236                                     enast(old_wm->trans_wm.enable),
6237                                     enast(old_wm->sagv.wm0.enable),
6238                                     enast(old_wm->sagv.trans_wm.enable),
6239                                     enast(new_wm->wm[0].enable), enast(new_wm->wm[1].enable),
6240                                     enast(new_wm->wm[2].enable), enast(new_wm->wm[3].enable),
6241                                     enast(new_wm->wm[4].enable), enast(new_wm->wm[5].enable),
6242                                     enast(new_wm->wm[6].enable), enast(new_wm->wm[7].enable),
6243                                     enast(new_wm->trans_wm.enable),
6244                                     enast(new_wm->sagv.wm0.enable),
6245                                     enast(new_wm->sagv.trans_wm.enable));
6246
6247                         drm_dbg_kms(&dev_priv->drm,
6248                                     "[PLANE:%d:%s]   lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d"
6249                                       " -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d\n",
6250                                     plane->base.base.id, plane->base.name,
6251                                     enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].lines,
6252                                     enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].lines,
6253                                     enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].lines,
6254                                     enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].lines,
6255                                     enast(old_wm->wm[4].ignore_lines), old_wm->wm[4].lines,
6256                                     enast(old_wm->wm[5].ignore_lines), old_wm->wm[5].lines,
6257                                     enast(old_wm->wm[6].ignore_lines), old_wm->wm[6].lines,
6258                                     enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].lines,
6259                                     enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.lines,
6260                                     enast(old_wm->sagv.wm0.ignore_lines), old_wm->sagv.wm0.lines,
6261                                     enast(old_wm->sagv.trans_wm.ignore_lines), old_wm->sagv.trans_wm.lines,
6262                                     enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].lines,
6263                                     enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].lines,
6264                                     enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].lines,
6265                                     enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].lines,
6266                                     enast(new_wm->wm[4].ignore_lines), new_wm->wm[4].lines,
6267                                     enast(new_wm->wm[5].ignore_lines), new_wm->wm[5].lines,
6268                                     enast(new_wm->wm[6].ignore_lines), new_wm->wm[6].lines,
6269                                     enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].lines,
6270                                     enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.lines,
6271                                     enast(new_wm->sagv.wm0.ignore_lines), new_wm->sagv.wm0.lines,
6272                                     enast(new_wm->sagv.trans_wm.ignore_lines), new_wm->sagv.trans_wm.lines);
6273
6274                         drm_dbg_kms(&dev_priv->drm,
6275                                     "[PLANE:%d:%s]  blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
6276                                     " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n",
6277                                     plane->base.base.id, plane->base.name,
6278                                     old_wm->wm[0].blocks, old_wm->wm[1].blocks,
6279                                     old_wm->wm[2].blocks, old_wm->wm[3].blocks,
6280                                     old_wm->wm[4].blocks, old_wm->wm[5].blocks,
6281                                     old_wm->wm[6].blocks, old_wm->wm[7].blocks,
6282                                     old_wm->trans_wm.blocks,
6283                                     old_wm->sagv.wm0.blocks,
6284                                     old_wm->sagv.trans_wm.blocks,
6285                                     new_wm->wm[0].blocks, new_wm->wm[1].blocks,
6286                                     new_wm->wm[2].blocks, new_wm->wm[3].blocks,
6287                                     new_wm->wm[4].blocks, new_wm->wm[5].blocks,
6288                                     new_wm->wm[6].blocks, new_wm->wm[7].blocks,
6289                                     new_wm->trans_wm.blocks,
6290                                     new_wm->sagv.wm0.blocks,
6291                                     new_wm->sagv.trans_wm.blocks);
6292
6293                         drm_dbg_kms(&dev_priv->drm,
6294                                     "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
6295                                     " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n",
6296                                     plane->base.base.id, plane->base.name,
6297                                     old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
6298                                     old_wm->wm[2].min_ddb_alloc, old_wm->wm[3].min_ddb_alloc,
6299                                     old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc,
6300                                     old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc,
6301                                     old_wm->trans_wm.min_ddb_alloc,
6302                                     old_wm->sagv.wm0.min_ddb_alloc,
6303                                     old_wm->sagv.trans_wm.min_ddb_alloc,
6304                                     new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc,
6305                                     new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc,
6306                                     new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
6307                                     new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
6308                                     new_wm->trans_wm.min_ddb_alloc,
6309                                     new_wm->sagv.wm0.min_ddb_alloc,
6310                                     new_wm->sagv.trans_wm.min_ddb_alloc);
6311                 }
6312         }
6313 }
6314
6315 static bool skl_plane_selected_wm_equals(struct intel_plane *plane,
6316                                          const struct skl_pipe_wm *old_pipe_wm,
6317                                          const struct skl_pipe_wm *new_pipe_wm)
6318 {
6319         struct drm_i915_private *i915 = to_i915(plane->base.dev);
6320         int level, max_level = ilk_wm_max_level(i915);
6321
6322         for (level = 0; level <= max_level; level++) {
6323                 /*
6324                  * We don't check uv_wm as the hardware doesn't actually
6325                  * use it. It only gets used for calculating the required
6326                  * ddb allocation.
6327                  */
6328                 if (!skl_wm_level_equals(skl_plane_wm_level(old_pipe_wm, plane->id, level),
6329                                          skl_plane_wm_level(new_pipe_wm, plane->id, level)))
6330                         return false;
6331         }
6332
6333         if (HAS_HW_SAGV_WM(i915)) {
6334                 const struct skl_plane_wm *old_wm = &old_pipe_wm->planes[plane->id];
6335                 const struct skl_plane_wm *new_wm = &new_pipe_wm->planes[plane->id];
6336
6337                 if (!skl_wm_level_equals(&old_wm->sagv.wm0, &new_wm->sagv.wm0) ||
6338                     !skl_wm_level_equals(&old_wm->sagv.trans_wm, &new_wm->sagv.trans_wm))
6339                         return false;
6340         }
6341
6342         return skl_wm_level_equals(skl_plane_trans_wm(old_pipe_wm, plane->id),
6343                                    skl_plane_trans_wm(new_pipe_wm, plane->id));
6344 }
6345
6346 /*
6347  * To make sure the cursor watermark registers are always consistent
6348  * with our computed state the following scenario needs special
6349  * treatment:
6350  *
6351  * 1. enable cursor
6352  * 2. move cursor entirely offscreen
6353  * 3. disable cursor
6354  *
6355  * Step 2. does call .disable_plane() but does not zero the watermarks
6356  * (since we consider an offscreen cursor still active for the purposes
6357  * of watermarks). Step 3. would not normally call .disable_plane()
6358  * because the actual plane visibility isn't changing, and we don't
6359  * deallocate the cursor ddb until the pipe gets disabled. So we must
6360  * force step 3. to call .disable_plane() to update the watermark
6361  * registers properly.
6362  *
6363  * Other planes do not suffer from this issues as their watermarks are
6364  * calculated based on the actual plane visibility. The only time this
6365  * can trigger for the other planes is during the initial readout as the
6366  * default value of the watermarks registers is not zero.
6367  */
6368 static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
6369                                       struct intel_crtc *crtc)
6370 {
6371         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6372         const struct intel_crtc_state *old_crtc_state =
6373                 intel_atomic_get_old_crtc_state(state, crtc);
6374         struct intel_crtc_state *new_crtc_state =
6375                 intel_atomic_get_new_crtc_state(state, crtc);
6376         struct intel_plane *plane;
6377
6378         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
6379                 struct intel_plane_state *plane_state;
6380                 enum plane_id plane_id = plane->id;
6381
6382                 /*
6383                  * Force a full wm update for every plane on modeset.
6384                  * Required because the reset value of the wm registers
6385                  * is non-zero, whereas we want all disabled planes to
6386                  * have zero watermarks. So if we turn off the relevant
6387                  * power well the hardware state will go out of sync
6388                  * with the software state.
6389                  */
6390                 if (!drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi) &&
6391                     skl_plane_selected_wm_equals(plane,
6392                                                  &old_crtc_state->wm.skl.optimal,
6393                                                  &new_crtc_state->wm.skl.optimal))
6394                         continue;
6395
6396                 plane_state = intel_atomic_get_plane_state(state, plane);
6397                 if (IS_ERR(plane_state))
6398                         return PTR_ERR(plane_state);
6399
6400                 new_crtc_state->update_planes |= BIT(plane_id);
6401         }
6402
6403         return 0;
6404 }
6405
6406 static int
6407 skl_compute_wm(struct intel_atomic_state *state)
6408 {
6409         struct intel_crtc *crtc;
6410         struct intel_crtc_state *new_crtc_state;
6411         int ret, i;
6412
6413         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6414                 ret = skl_build_pipe_wm(state, crtc);
6415                 if (ret)
6416                         return ret;
6417         }
6418
6419         ret = skl_compute_ddb(state);
6420         if (ret)
6421                 return ret;
6422
6423         ret = intel_compute_sagv_mask(state);
6424         if (ret)
6425                 return ret;
6426
6427         /*
6428          * skl_compute_ddb() will have adjusted the final watermarks
6429          * based on how much ddb is available. Now we can actually
6430          * check if the final watermarks changed.
6431          */
6432         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6433                 ret = skl_wm_add_affected_planes(state, crtc);
6434                 if (ret)
6435                         return ret;
6436         }
6437
6438         skl_print_wm_changes(state);
6439
6440         return 0;
6441 }
6442
6443 static void ilk_compute_wm_config(struct drm_i915_private *dev_priv,
6444                                   struct intel_wm_config *config)
6445 {
6446         struct intel_crtc *crtc;
6447
6448         /* Compute the currently _active_ config */
6449         for_each_intel_crtc(&dev_priv->drm, crtc) {
6450                 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
6451
6452                 if (!wm->pipe_enabled)
6453                         continue;
6454
6455                 config->sprites_enabled |= wm->sprites_enabled;
6456                 config->sprites_scaled |= wm->sprites_scaled;
6457                 config->num_pipes_active++;
6458         }
6459 }
6460
6461 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
6462 {
6463         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
6464         struct ilk_wm_maximums max;
6465         struct intel_wm_config config = {};
6466         struct ilk_wm_values results = {};
6467         enum intel_ddb_partitioning partitioning;
6468
6469         ilk_compute_wm_config(dev_priv, &config);
6470
6471         ilk_compute_wm_maximums(dev_priv, 1, &config, INTEL_DDB_PART_1_2, &max);
6472         ilk_wm_merge(dev_priv, &config, &max, &lp_wm_1_2);
6473
6474         /* 5/6 split only in single pipe config on IVB+ */
6475         if (DISPLAY_VER(dev_priv) >= 7 &&
6476             config.num_pipes_active == 1 && config.sprites_enabled) {
6477                 ilk_compute_wm_maximums(dev_priv, 1, &config, INTEL_DDB_PART_5_6, &max);
6478                 ilk_wm_merge(dev_priv, &config, &max, &lp_wm_5_6);
6479
6480                 best_lp_wm = ilk_find_best_result(dev_priv, &lp_wm_1_2, &lp_wm_5_6);
6481         } else {
6482                 best_lp_wm = &lp_wm_1_2;
6483         }
6484
6485         partitioning = (best_lp_wm == &lp_wm_1_2) ?
6486                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
6487
6488         ilk_compute_wm_results(dev_priv, best_lp_wm, partitioning, &results);
6489
6490         ilk_write_wm_values(dev_priv, &results);
6491 }
6492
6493 static void ilk_initial_watermarks(struct intel_atomic_state *state,
6494                                    struct intel_crtc *crtc)
6495 {
6496         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6497         const struct intel_crtc_state *crtc_state =
6498                 intel_atomic_get_new_crtc_state(state, crtc);
6499
6500         mutex_lock(&dev_priv->wm.wm_mutex);
6501         crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
6502         ilk_program_watermarks(dev_priv);
6503         mutex_unlock(&dev_priv->wm.wm_mutex);
6504 }
6505
6506 static void ilk_optimize_watermarks(struct intel_atomic_state *state,
6507                                     struct intel_crtc *crtc)
6508 {
6509         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6510         const struct intel_crtc_state *crtc_state =
6511                 intel_atomic_get_new_crtc_state(state, crtc);
6512
6513         if (!crtc_state->wm.need_postvbl_update)
6514                 return;
6515
6516         mutex_lock(&dev_priv->wm.wm_mutex);
6517         crtc->wm.active.ilk = crtc_state->wm.ilk.optimal;
6518         ilk_program_watermarks(dev_priv);
6519         mutex_unlock(&dev_priv->wm.wm_mutex);
6520 }
6521
6522 static void skl_wm_level_from_reg_val(u32 val, struct skl_wm_level *level)
6523 {
6524         level->enable = val & PLANE_WM_EN;
6525         level->ignore_lines = val & PLANE_WM_IGNORE_LINES;
6526         level->blocks = val & PLANE_WM_BLOCKS_MASK;
6527         level->lines = REG_FIELD_GET(PLANE_WM_LINES_MASK, val);
6528 }
6529
6530 void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
6531                               struct skl_pipe_wm *out)
6532 {
6533         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6534         enum pipe pipe = crtc->pipe;
6535         int level, max_level;
6536         enum plane_id plane_id;
6537         u32 val;
6538
6539         max_level = ilk_wm_max_level(dev_priv);
6540
6541         for_each_plane_id_on_crtc(crtc, plane_id) {
6542                 struct skl_plane_wm *wm = &out->planes[plane_id];
6543
6544                 for (level = 0; level <= max_level; level++) {
6545                         if (plane_id != PLANE_CURSOR)
6546                                 val = intel_uncore_read(&dev_priv->uncore, PLANE_WM(pipe, plane_id, level));
6547                         else
6548                                 val = intel_uncore_read(&dev_priv->uncore, CUR_WM(pipe, level));
6549
6550                         skl_wm_level_from_reg_val(val, &wm->wm[level]);
6551                 }
6552
6553                 if (plane_id != PLANE_CURSOR)
6554                         val = intel_uncore_read(&dev_priv->uncore, PLANE_WM_TRANS(pipe, plane_id));
6555                 else
6556                         val = intel_uncore_read(&dev_priv->uncore, CUR_WM_TRANS(pipe));
6557
6558                 skl_wm_level_from_reg_val(val, &wm->trans_wm);
6559
6560                 if (HAS_HW_SAGV_WM(dev_priv)) {
6561                         if (plane_id != PLANE_CURSOR)
6562                                 val = intel_uncore_read(&dev_priv->uncore,
6563                                                         PLANE_WM_SAGV(pipe, plane_id));
6564                         else
6565                                 val = intel_uncore_read(&dev_priv->uncore,
6566                                                         CUR_WM_SAGV(pipe));
6567
6568                         skl_wm_level_from_reg_val(val, &wm->sagv.wm0);
6569
6570                         if (plane_id != PLANE_CURSOR)
6571                                 val = intel_uncore_read(&dev_priv->uncore,
6572                                                         PLANE_WM_SAGV_TRANS(pipe, plane_id));
6573                         else
6574                                 val = intel_uncore_read(&dev_priv->uncore,
6575                                                         CUR_WM_SAGV_TRANS(pipe));
6576
6577                         skl_wm_level_from_reg_val(val, &wm->sagv.trans_wm);
6578                 } else if (DISPLAY_VER(dev_priv) >= 12) {
6579                         wm->sagv.wm0 = wm->wm[0];
6580                         wm->sagv.trans_wm = wm->trans_wm;
6581                 }
6582         }
6583 }
6584
6585 void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
6586 {
6587         struct intel_dbuf_state *dbuf_state =
6588                 to_intel_dbuf_state(dev_priv->dbuf.obj.state);
6589         struct intel_crtc *crtc;
6590
6591         if (IS_ALDERLAKE_P(dev_priv))
6592                 dbuf_state->joined_mbus = intel_de_read(dev_priv, MBUS_CTL) & MBUS_JOIN;
6593
6594         for_each_intel_crtc(&dev_priv->drm, crtc) {
6595                 struct intel_crtc_state *crtc_state =
6596                         to_intel_crtc_state(crtc->base.state);
6597                 enum pipe pipe = crtc->pipe;
6598                 unsigned int mbus_offset;
6599                 enum plane_id plane_id;
6600
6601                 skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);
6602                 crtc_state->wm.skl.raw = crtc_state->wm.skl.optimal;
6603
6604                 memset(&dbuf_state->ddb[pipe], 0, sizeof(dbuf_state->ddb[pipe]));
6605
6606                 for_each_plane_id_on_crtc(crtc, plane_id) {
6607                         struct skl_ddb_entry *ddb_y =
6608                                 &crtc_state->wm.skl.plane_ddb_y[plane_id];
6609                         struct skl_ddb_entry *ddb_uv =
6610                                 &crtc_state->wm.skl.plane_ddb_uv[plane_id];
6611
6612                         skl_ddb_get_hw_plane_state(dev_priv, crtc->pipe,
6613                                                    plane_id, ddb_y, ddb_uv);
6614
6615                         skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb_y);
6616                         skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb_uv);
6617                 }
6618
6619                 dbuf_state->slices[pipe] =
6620                         skl_compute_dbuf_slices(crtc, dbuf_state->active_pipes);
6621
6622                 dbuf_state->weight[pipe] = intel_crtc_ddb_weight(crtc_state);
6623
6624                 /*
6625                  * Used for checking overlaps, so we need absolute
6626                  * offsets instead of MBUS relative offsets.
6627                  */
6628                 mbus_offset = mbus_ddb_offset(dev_priv, dbuf_state->slices[pipe]);
6629                 crtc_state->wm.skl.ddb.start = mbus_offset + dbuf_state->ddb[pipe].start;
6630                 crtc_state->wm.skl.ddb.end = mbus_offset + dbuf_state->ddb[pipe].end;
6631
6632                 drm_dbg_kms(&dev_priv->drm,
6633                             "[CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 0x%x, mbus joined: %s\n",
6634                             crtc->base.base.id, crtc->base.name,
6635                             dbuf_state->slices[pipe], dbuf_state->ddb[pipe].start,
6636                             dbuf_state->ddb[pipe].end, dbuf_state->active_pipes,
6637                             yesno(dbuf_state->joined_mbus));
6638         }
6639
6640         dbuf_state->enabled_slices = dev_priv->dbuf.enabled_slices;
6641 }
6642
6643 static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
6644 {
6645         struct drm_device *dev = crtc->base.dev;
6646         struct drm_i915_private *dev_priv = to_i915(dev);
6647         struct ilk_wm_values *hw = &dev_priv->wm.hw;
6648         struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
6649         struct intel_pipe_wm *active = &crtc_state->wm.ilk.optimal;
6650         enum pipe pipe = crtc->pipe;
6651
6652         hw->wm_pipe[pipe] = intel_uncore_read(&dev_priv->uncore, WM0_PIPE_ILK(pipe));
6653
6654         memset(active, 0, sizeof(*active));
6655
6656         active->pipe_enabled = crtc->active;
6657
6658         if (active->pipe_enabled) {
6659                 u32 tmp = hw->wm_pipe[pipe];
6660
6661                 /*
6662                  * For active pipes LP0 watermark is marked as
6663                  * enabled, and LP1+ watermaks as disabled since
6664                  * we can't really reverse compute them in case
6665                  * multiple pipes are active.
6666                  */
6667                 active->wm[0].enable = true;
6668                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
6669                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
6670                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
6671         } else {
6672                 int level, max_level = ilk_wm_max_level(dev_priv);
6673
6674                 /*
6675                  * For inactive pipes, all watermark levels
6676                  * should be marked as enabled but zeroed,
6677                  * which is what we'd compute them to.
6678                  */
6679                 for (level = 0; level <= max_level; level++)
6680                         active->wm[level].enable = true;
6681         }
6682
6683         crtc->wm.active.ilk = *active;
6684 }
6685
6686 #define _FW_WM(value, plane) \
6687         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
6688 #define _FW_WM_VLV(value, plane) \
6689         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
6690
6691 static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
6692                                struct g4x_wm_values *wm)
6693 {
6694         u32 tmp;
6695
6696         tmp = intel_uncore_read(&dev_priv->uncore, DSPFW1);
6697         wm->sr.plane = _FW_WM(tmp, SR);
6698         wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
6699         wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB);
6700         wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA);
6701
6702         tmp = intel_uncore_read(&dev_priv->uncore, DSPFW2);
6703         wm->fbc_en = tmp & DSPFW_FBC_SR_EN;
6704         wm->sr.fbc = _FW_WM(tmp, FBC_SR);
6705         wm->hpll.fbc = _FW_WM(tmp, FBC_HPLL_SR);
6706         wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEB);
6707         wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
6708         wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA);
6709
6710         tmp = intel_uncore_read(&dev_priv->uncore, DSPFW3);
6711         wm->hpll_en = tmp & DSPFW_HPLL_SR_EN;
6712         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
6713         wm->hpll.cursor = _FW_WM(tmp, HPLL_CURSOR);
6714         wm->hpll.plane = _FW_WM(tmp, HPLL_SR);
6715 }
6716
6717 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
6718                                struct vlv_wm_values *wm)
6719 {
6720         enum pipe pipe;
6721         u32 tmp;
6722
6723         for_each_pipe(dev_priv, pipe) {
6724                 tmp = intel_uncore_read(&dev_priv->uncore, VLV_DDL(pipe));
6725
6726                 wm->ddl[pipe].plane[PLANE_PRIMARY] =
6727                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
6728                 wm->ddl[pipe].plane[PLANE_CURSOR] =
6729                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
6730                 wm->ddl[pipe].plane[PLANE_SPRITE0] =
6731                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
6732                 wm->ddl[pipe].plane[PLANE_SPRITE1] =
6733                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
6734         }
6735
6736         tmp = intel_uncore_read(&dev_priv->uncore, DSPFW1);
6737         wm->sr.plane = _FW_WM(tmp, SR);
6738         wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
6739         wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
6740         wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
6741
6742         tmp = intel_uncore_read(&dev_priv->uncore, DSPFW2);
6743         wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
6744         wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
6745         wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
6746
6747         tmp = intel_uncore_read(&dev_priv->uncore, DSPFW3);
6748         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
6749
6750         if (IS_CHERRYVIEW(dev_priv)) {
6751                 tmp = intel_uncore_read(&dev_priv->uncore, DSPFW7_CHV);
6752                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
6753                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
6754
6755                 tmp = intel_uncore_read(&dev_priv->uncore, DSPFW8_CHV);
6756                 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF);
6757                 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE);
6758
6759                 tmp = intel_uncore_read(&dev_priv->uncore, DSPFW9_CHV);
6760                 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC);
6761                 wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC);
6762
6763                 tmp = intel_uncore_read(&dev_priv->uncore, DSPHOWM);
6764                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
6765                 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
6766                 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
6767                 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8;
6768                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
6769                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
6770                 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
6771                 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
6772                 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
6773                 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
6774         } else {
6775                 tmp = intel_uncore_read(&dev_priv->uncore, DSPFW7);
6776                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
6777                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
6778
6779                 tmp = intel_uncore_read(&dev_priv->uncore, DSPHOWM);
6780                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
6781                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
6782                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
6783                 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
6784                 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
6785                 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
6786                 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
6787         }
6788 }
6789
6790 #undef _FW_WM
6791 #undef _FW_WM_VLV
6792
6793 void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv)
6794 {
6795         struct g4x_wm_values *wm = &dev_priv->wm.g4x;
6796         struct intel_crtc *crtc;
6797
6798         g4x_read_wm_values(dev_priv, wm);
6799
6800         wm->cxsr = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN;
6801
6802         for_each_intel_crtc(&dev_priv->drm, crtc) {
6803                 struct intel_crtc_state *crtc_state =
6804                         to_intel_crtc_state(crtc->base.state);
6805                 struct g4x_wm_state *active = &crtc->wm.active.g4x;
6806                 struct g4x_pipe_wm *raw;
6807                 enum pipe pipe = crtc->pipe;
6808                 enum plane_id plane_id;
6809                 int level, max_level;
6810
6811                 active->cxsr = wm->cxsr;
6812                 active->hpll_en = wm->hpll_en;
6813                 active->fbc_en = wm->fbc_en;
6814
6815                 active->sr = wm->sr;
6816                 active->hpll = wm->hpll;
6817
6818                 for_each_plane_id_on_crtc(crtc, plane_id) {
6819                         active->wm.plane[plane_id] =
6820                                 wm->pipe[pipe].plane[plane_id];
6821                 }
6822
6823                 if (wm->cxsr && wm->hpll_en)
6824                         max_level = G4X_WM_LEVEL_HPLL;
6825                 else if (wm->cxsr)
6826                         max_level = G4X_WM_LEVEL_SR;
6827                 else
6828                         max_level = G4X_WM_LEVEL_NORMAL;
6829
6830                 level = G4X_WM_LEVEL_NORMAL;
6831                 raw = &crtc_state->wm.g4x.raw[level];
6832                 for_each_plane_id_on_crtc(crtc, plane_id)
6833                         raw->plane[plane_id] = active->wm.plane[plane_id];
6834
6835                 if (++level > max_level)
6836                         goto out;
6837
6838                 raw = &crtc_state->wm.g4x.raw[level];
6839                 raw->plane[PLANE_PRIMARY] = active->sr.plane;
6840                 raw->plane[PLANE_CURSOR] = active->sr.cursor;
6841                 raw->plane[PLANE_SPRITE0] = 0;
6842                 raw->fbc = active->sr.fbc;
6843
6844                 if (++level > max_level)
6845                         goto out;
6846
6847                 raw = &crtc_state->wm.g4x.raw[level];
6848                 raw->plane[PLANE_PRIMARY] = active->hpll.plane;
6849                 raw->plane[PLANE_CURSOR] = active->hpll.cursor;
6850                 raw->plane[PLANE_SPRITE0] = 0;
6851                 raw->fbc = active->hpll.fbc;
6852
6853         out:
6854                 for_each_plane_id_on_crtc(crtc, plane_id)
6855                         g4x_raw_plane_wm_set(crtc_state, level,
6856                                              plane_id, USHRT_MAX);
6857                 g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX);
6858
6859                 crtc_state->wm.g4x.optimal = *active;
6860                 crtc_state->wm.g4x.intermediate = *active;
6861
6862                 drm_dbg_kms(&dev_priv->drm,
6863                             "Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite=%d\n",
6864                             pipe_name(pipe),
6865                             wm->pipe[pipe].plane[PLANE_PRIMARY],
6866                             wm->pipe[pipe].plane[PLANE_CURSOR],
6867                             wm->pipe[pipe].plane[PLANE_SPRITE0]);
6868         }
6869
6870         drm_dbg_kms(&dev_priv->drm,
6871                     "Initial SR watermarks: plane=%d, cursor=%d fbc=%d\n",
6872                     wm->sr.plane, wm->sr.cursor, wm->sr.fbc);
6873         drm_dbg_kms(&dev_priv->drm,
6874                     "Initial HPLL watermarks: plane=%d, SR cursor=%d fbc=%d\n",
6875                     wm->hpll.plane, wm->hpll.cursor, wm->hpll.fbc);
6876         drm_dbg_kms(&dev_priv->drm, "Initial SR=%s HPLL=%s FBC=%s\n",
6877                     yesno(wm->cxsr), yesno(wm->hpll_en), yesno(wm->fbc_en));
6878 }
6879
6880 void g4x_wm_sanitize(struct drm_i915_private *dev_priv)
6881 {
6882         struct intel_plane *plane;
6883         struct intel_crtc *crtc;
6884
6885         mutex_lock(&dev_priv->wm.wm_mutex);
6886
6887         for_each_intel_plane(&dev_priv->drm, plane) {
6888                 struct intel_crtc *crtc =
6889                         intel_get_crtc_for_pipe(dev_priv, plane->pipe);
6890                 struct intel_crtc_state *crtc_state =
6891                         to_intel_crtc_state(crtc->base.state);
6892                 struct intel_plane_state *plane_state =
6893                         to_intel_plane_state(plane->base.state);
6894                 struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
6895                 enum plane_id plane_id = plane->id;
6896                 int level;
6897
6898                 if (plane_state->uapi.visible)
6899                         continue;
6900
6901                 for (level = 0; level < 3; level++) {
6902                         struct g4x_pipe_wm *raw =
6903                                 &crtc_state->wm.g4x.raw[level];
6904
6905                         raw->plane[plane_id] = 0;
6906                         wm_state->wm.plane[plane_id] = 0;
6907                 }
6908
6909                 if (plane_id == PLANE_PRIMARY) {
6910                         for (level = 0; level < 3; level++) {
6911                                 struct g4x_pipe_wm *raw =
6912                                         &crtc_state->wm.g4x.raw[level];
6913                                 raw->fbc = 0;
6914                         }
6915
6916                         wm_state->sr.fbc = 0;
6917                         wm_state->hpll.fbc = 0;
6918                         wm_state->fbc_en = false;
6919                 }
6920         }
6921
6922         for_each_intel_crtc(&dev_priv->drm, crtc) {
6923                 struct intel_crtc_state *crtc_state =
6924                         to_intel_crtc_state(crtc->base.state);
6925
6926                 crtc_state->wm.g4x.intermediate =
6927                         crtc_state->wm.g4x.optimal;
6928                 crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
6929         }
6930
6931         g4x_program_watermarks(dev_priv);
6932
6933         mutex_unlock(&dev_priv->wm.wm_mutex);
6934 }
6935
6936 void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv)
6937 {
6938         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
6939         struct intel_crtc *crtc;
6940         u32 val;
6941
6942         vlv_read_wm_values(dev_priv, wm);
6943
6944         wm->cxsr = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
6945         wm->level = VLV_WM_LEVEL_PM2;
6946
6947         if (IS_CHERRYVIEW(dev_priv)) {
6948                 vlv_punit_get(dev_priv);
6949
6950                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
6951                 if (val & DSP_MAXFIFO_PM5_ENABLE)
6952                         wm->level = VLV_WM_LEVEL_PM5;
6953
6954                 /*
6955                  * If DDR DVFS is disabled in the BIOS, Punit
6956                  * will never ack the request. So if that happens
6957                  * assume we don't have to enable/disable DDR DVFS
6958                  * dynamically. To test that just set the REQ_ACK
6959                  * bit to poke the Punit, but don't change the
6960                  * HIGH/LOW bits so that we don't actually change
6961                  * the current state.
6962                  */
6963                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
6964                 val |= FORCE_DDR_FREQ_REQ_ACK;
6965                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
6966
6967                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
6968                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
6969                         drm_dbg_kms(&dev_priv->drm,
6970                                     "Punit not acking DDR DVFS request, "
6971                                     "assuming DDR DVFS is disabled\n");
6972                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
6973                 } else {
6974                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
6975                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
6976                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
6977                 }
6978
6979                 vlv_punit_put(dev_priv);
6980         }
6981
6982         for_each_intel_crtc(&dev_priv->drm, crtc) {
6983                 struct intel_crtc_state *crtc_state =
6984                         to_intel_crtc_state(crtc->base.state);
6985                 struct vlv_wm_state *active = &crtc->wm.active.vlv;
6986                 const struct vlv_fifo_state *fifo_state =
6987                         &crtc_state->wm.vlv.fifo_state;
6988                 enum pipe pipe = crtc->pipe;
6989                 enum plane_id plane_id;
6990                 int level;
6991
6992                 vlv_get_fifo_size(crtc_state);
6993
6994                 active->num_levels = wm->level + 1;
6995                 active->cxsr = wm->cxsr;
6996
6997                 for (level = 0; level < active->num_levels; level++) {
6998                         struct g4x_pipe_wm *raw =
6999                                 &crtc_state->wm.vlv.raw[level];
7000
7001                         active->sr[level].plane = wm->sr.plane;
7002                         active->sr[level].cursor = wm->sr.cursor;
7003
7004                         for_each_plane_id_on_crtc(crtc, plane_id) {
7005                                 active->wm[level].plane[plane_id] =
7006                                         wm->pipe[pipe].plane[plane_id];
7007
7008                                 raw->plane[plane_id] =
7009                                         vlv_invert_wm_value(active->wm[level].plane[plane_id],
7010                                                             fifo_state->plane[plane_id]);
7011                         }
7012                 }
7013
7014                 for_each_plane_id_on_crtc(crtc, plane_id)
7015                         vlv_raw_plane_wm_set(crtc_state, level,
7016                                              plane_id, USHRT_MAX);
7017                 vlv_invalidate_wms(crtc, active, level);
7018
7019                 crtc_state->wm.vlv.optimal = *active;
7020                 crtc_state->wm.vlv.intermediate = *active;
7021
7022                 drm_dbg_kms(&dev_priv->drm,
7023                             "Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
7024                             pipe_name(pipe),
7025                             wm->pipe[pipe].plane[PLANE_PRIMARY],
7026                             wm->pipe[pipe].plane[PLANE_CURSOR],
7027                             wm->pipe[pipe].plane[PLANE_SPRITE0],
7028                             wm->pipe[pipe].plane[PLANE_SPRITE1]);
7029         }
7030
7031         drm_dbg_kms(&dev_priv->drm,
7032                     "Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
7033                     wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
7034 }
7035
7036 void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
7037 {
7038         struct intel_plane *plane;
7039         struct intel_crtc *crtc;
7040
7041         mutex_lock(&dev_priv->wm.wm_mutex);
7042
7043         for_each_intel_plane(&dev_priv->drm, plane) {
7044                 struct intel_crtc *crtc =
7045                         intel_get_crtc_for_pipe(dev_priv, plane->pipe);
7046                 struct intel_crtc_state *crtc_state =
7047                         to_intel_crtc_state(crtc->base.state);
7048                 struct intel_plane_state *plane_state =
7049                         to_intel_plane_state(plane->base.state);
7050                 struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
7051                 const struct vlv_fifo_state *fifo_state =
7052                         &crtc_state->wm.vlv.fifo_state;
7053                 enum plane_id plane_id = plane->id;
7054                 int level;
7055
7056                 if (plane_state->uapi.visible)
7057                         continue;
7058
7059                 for (level = 0; level < wm_state->num_levels; level++) {
7060                         struct g4x_pipe_wm *raw =
7061                                 &crtc_state->wm.vlv.raw[level];
7062
7063                         raw->plane[plane_id] = 0;
7064
7065                         wm_state->wm[level].plane[plane_id] =
7066                                 vlv_invert_wm_value(raw->plane[plane_id],
7067                                                     fifo_state->plane[plane_id]);
7068                 }
7069         }
7070
7071         for_each_intel_crtc(&dev_priv->drm, crtc) {
7072                 struct intel_crtc_state *crtc_state =
7073                         to_intel_crtc_state(crtc->base.state);
7074
7075                 crtc_state->wm.vlv.intermediate =
7076                         crtc_state->wm.vlv.optimal;
7077                 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
7078         }
7079
7080         vlv_program_watermarks(dev_priv);
7081
7082         mutex_unlock(&dev_priv->wm.wm_mutex);
7083 }
7084
7085 /*
7086  * FIXME should probably kill this and improve
7087  * the real watermark readout/sanitation instead
7088  */
7089 static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
7090 {
7091         intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM3_LP_ILK) & ~WM1_LP_SR_EN);
7092         intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM2_LP_ILK) & ~WM1_LP_SR_EN);
7093         intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM1_LP_ILK) & ~WM1_LP_SR_EN);
7094
7095         /*
7096          * Don't touch WM1S_LP_EN here.
7097          * Doing so could cause underruns.
7098          */
7099 }
7100
7101 void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv)
7102 {
7103         struct ilk_wm_values *hw = &dev_priv->wm.hw;
7104         struct intel_crtc *crtc;
7105
7106         ilk_init_lp_watermarks(dev_priv);
7107
7108         for_each_intel_crtc(&dev_priv->drm, crtc)
7109                 ilk_pipe_wm_get_hw_state(crtc);
7110
7111         hw->wm_lp[0] = intel_uncore_read(&dev_priv->uncore, WM1_LP_ILK);
7112         hw->wm_lp[1] = intel_uncore_read(&dev_priv->uncore, WM2_LP_ILK);
7113         hw->wm_lp[2] = intel_uncore_read(&dev_priv->uncore, WM3_LP_ILK);
7114
7115         hw->wm_lp_spr[0] = intel_uncore_read(&dev_priv->uncore, WM1S_LP_ILK);
7116         if (DISPLAY_VER(dev_priv) >= 7) {
7117                 hw->wm_lp_spr[1] = intel_uncore_read(&dev_priv->uncore, WM2S_LP_IVB);
7118                 hw->wm_lp_spr[2] = intel_uncore_read(&dev_priv->uncore, WM3S_LP_IVB);
7119         }
7120
7121         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
7122                 hw->partitioning = (intel_uncore_read(&dev_priv->uncore, WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
7123                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
7124         else if (IS_IVYBRIDGE(dev_priv))
7125                 hw->partitioning = (intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
7126                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
7127
7128         hw->enable_fbc_wm =
7129                 !(intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) & DISP_FBC_WM_DIS);
7130 }
7131
7132 /**
7133  * intel_update_watermarks - update FIFO watermark values based on current modes
7134  * @crtc: the #intel_crtc on which to compute the WM
7135  *
7136  * Calculate watermark values for the various WM regs based on current mode
7137  * and plane configuration.
7138  *
7139  * There are several cases to deal with here:
7140  *   - normal (i.e. non-self-refresh)
7141  *   - self-refresh (SR) mode
7142  *   - lines are large relative to FIFO size (buffer can hold up to 2)
7143  *   - lines are small relative to FIFO size (buffer can hold more than 2
7144  *     lines), so need to account for TLB latency
7145  *
7146  *   The normal calculation is:
7147  *     watermark = dotclock * bytes per pixel * latency
7148  *   where latency is platform & configuration dependent (we assume pessimal
7149  *   values here).
7150  *
7151  *   The SR calculation is:
7152  *     watermark = (trunc(latency/line time)+1) * surface width *
7153  *       bytes per pixel
7154  *   where
7155  *     line time = htotal / dotclock
7156  *     surface width = hdisplay for normal plane and 64 for cursor
7157  *   and latency is assumed to be high, as above.
7158  *
7159  * The final value programmed to the register should always be rounded up,
7160  * and include an extra 2 entries to account for clock crossings.
7161  *
7162  * We don't use the sprite, so we can ignore that.  And on Crestline we have
7163  * to set the non-SR watermarks to 8.
7164  */
7165 void intel_update_watermarks(struct intel_crtc *crtc)
7166 {
7167         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7168
7169         if (dev_priv->display.update_wm)
7170                 dev_priv->display.update_wm(crtc);
7171 }
7172
7173 void intel_enable_ipc(struct drm_i915_private *dev_priv)
7174 {
7175         u32 val;
7176
7177         if (!HAS_IPC(dev_priv))
7178                 return;
7179
7180         val = intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL2);
7181
7182         if (dev_priv->ipc_enabled)
7183                 val |= DISP_IPC_ENABLE;
7184         else
7185                 val &= ~DISP_IPC_ENABLE;
7186
7187         intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL2, val);
7188 }
7189
7190 static bool intel_can_enable_ipc(struct drm_i915_private *dev_priv)
7191 {
7192         /* Display WA #0477 WaDisableIPC: skl */
7193         if (IS_SKYLAKE(dev_priv))
7194                 return false;
7195
7196         /* Display WA #1141: SKL:all KBL:all CFL */
7197         if (IS_KABYLAKE(dev_priv) ||
7198             IS_COFFEELAKE(dev_priv) ||
7199             IS_COMETLAKE(dev_priv))
7200                 return dev_priv->dram_info.symmetric_memory;
7201
7202         return true;
7203 }
7204
7205 void intel_init_ipc(struct drm_i915_private *dev_priv)
7206 {
7207         if (!HAS_IPC(dev_priv))
7208                 return;
7209
7210         dev_priv->ipc_enabled = intel_can_enable_ipc(dev_priv);
7211
7212         intel_enable_ipc(dev_priv);
7213 }
7214
7215 static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
7216 {
7217         /*
7218          * On Ibex Peak and Cougar Point, we need to disable clock
7219          * gating for the panel power sequencer or it will fail to
7220          * start up when no ports are active.
7221          */
7222         intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7223 }
7224
7225 static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
7226 {
7227         enum pipe pipe;
7228
7229         for_each_pipe(dev_priv, pipe) {
7230                 intel_uncore_write(&dev_priv->uncore, DSPCNTR(pipe),
7231                            intel_uncore_read(&dev_priv->uncore, DSPCNTR(pipe)) |
7232                            DISPPLANE_TRICKLE_FEED_DISABLE);
7233
7234                 intel_uncore_write(&dev_priv->uncore, DSPSURF(pipe), intel_uncore_read(&dev_priv->uncore, DSPSURF(pipe)));
7235                 intel_uncore_posting_read(&dev_priv->uncore, DSPSURF(pipe));
7236         }
7237 }
7238
7239 static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
7240 {
7241         u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
7242
7243         /*
7244          * Required for FBC
7245          * WaFbcDisableDpfcClockGating:ilk
7246          */
7247         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
7248                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
7249                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
7250
7251         intel_uncore_write(&dev_priv->uncore, PCH_3DCGDIS0,
7252                    MARIUNIT_CLOCK_GATE_DISABLE |
7253                    SVSMUNIT_CLOCK_GATE_DISABLE);
7254         intel_uncore_write(&dev_priv->uncore, PCH_3DCGDIS1,
7255                    VFMUNIT_CLOCK_GATE_DISABLE);
7256
7257         /*
7258          * According to the spec the following bits should be set in
7259          * order to enable memory self-refresh
7260          * The bit 22/21 of 0x42004
7261          * The bit 5 of 0x42020
7262          * The bit 15 of 0x45000
7263          */
7264         intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
7265                    (intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |
7266                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7267         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
7268         intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL,
7269                    (intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
7270                     DISP_FBC_WM_DIS));
7271
7272         /*
7273          * Based on the document from hardware guys the following bits
7274          * should be set unconditionally in order to enable FBC.
7275          * The bit 22 of 0x42000
7276          * The bit 22 of 0x42004
7277          * The bit 7,8,9 of 0x42020.
7278          */
7279         if (IS_IRONLAKE_M(dev_priv)) {
7280                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
7281                 intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1,
7282                            intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1) |
7283                            ILK_FBCQ_DIS);
7284                 intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
7285                            intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |
7286                            ILK_DPARB_GATE);
7287         }
7288
7289         intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
7290
7291         intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
7292                    intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |
7293                    ILK_ELPIN_409_SELECT);
7294
7295         g4x_disable_trickle_feed(dev_priv);
7296
7297         ibx_init_clock_gating(dev_priv);
7298 }
7299
7300 static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
7301 {
7302         enum pipe pipe;
7303         u32 val;
7304
7305         /*
7306          * On Ibex Peak and Cougar Point, we need to disable clock
7307          * gating for the panel power sequencer or it will fail to
7308          * start up when no ports are active.
7309          */
7310         intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
7311                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
7312                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
7313         intel_uncore_write(&dev_priv->uncore, SOUTH_CHICKEN2, intel_uncore_read(&dev_priv->uncore, SOUTH_CHICKEN2) |
7314                    DPLS_EDP_PPS_FIX_DIS);
7315         /* The below fixes the weird display corruption, a few pixels shifted
7316          * downward, on (only) LVDS of some HP laptops with IVY.
7317          */
7318         for_each_pipe(dev_priv, pipe) {
7319                 val = intel_uncore_read(&dev_priv->uncore, TRANS_CHICKEN2(pipe));
7320                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
7321                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
7322                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
7323                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
7324                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
7325                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
7326                 intel_uncore_write(&dev_priv->uncore, TRANS_CHICKEN2(pipe), val);
7327         }
7328         /* WADP0ClockGatingDisable */
7329         for_each_pipe(dev_priv, pipe) {
7330                 intel_uncore_write(&dev_priv->uncore, TRANS_CHICKEN1(pipe),
7331                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7332         }
7333 }
7334
7335 static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
7336 {
7337         u32 tmp;
7338
7339         tmp = intel_uncore_read(&dev_priv->uncore, MCH_SSKPD);
7340         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
7341                 drm_dbg_kms(&dev_priv->drm,
7342                             "Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
7343                             tmp);
7344 }
7345
7346 static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
7347 {
7348         u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
7349
7350         intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
7351
7352         intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
7353                    intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |
7354                    ILK_ELPIN_409_SELECT);
7355
7356         intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1,
7357                    intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) |
7358                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7359                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7360
7361         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7362          * gating disable must be set.  Failure to set it results in
7363          * flickering pixels due to Z write ordering failures after
7364          * some amount of runtime in the Mesa "fire" demo, and Unigine
7365          * Sanctuary and Tropics, and apparently anything else with
7366          * alpha test or pixel discard.
7367          *
7368          * According to the spec, bit 11 (RCCUNIT) must also be set,
7369          * but we didn't debug actual testcases to find it out.
7370          *
7371          * WaDisableRCCUnitClockGating:snb
7372          * WaDisableRCPBUnitClockGating:snb
7373          */
7374         intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2,
7375                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7376                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7377
7378         /*
7379          * According to the spec the following bits should be
7380          * set in order to enable memory self-refresh and fbc:
7381          * The bit21 and bit22 of 0x42000
7382          * The bit21 and bit22 of 0x42004
7383          * The bit5 and bit7 of 0x42020
7384          * The bit14 of 0x70180
7385          * The bit14 of 0x71180
7386          *
7387          * WaFbcAsynchFlipDisableFbcQueue:snb
7388          */
7389         intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1,
7390                    intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1) |
7391                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7392         intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
7393                    intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |
7394                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7395         intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D,
7396                    intel_uncore_read(&dev_priv->uncore, ILK_DSPCLK_GATE_D) |
7397                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
7398                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
7399
7400         g4x_disable_trickle_feed(dev_priv);
7401
7402         cpt_init_clock_gating(dev_priv);
7403
7404         gen6_check_mch_setup(dev_priv);
7405 }
7406
7407 static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
7408 {
7409         /*
7410          * TODO: this bit should only be enabled when really needed, then
7411          * disabled when not needed anymore in order to save power.
7412          */
7413         if (HAS_PCH_LPT_LP(dev_priv))
7414                 intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D,
7415                            intel_uncore_read(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D) |
7416                            PCH_LP_PARTITION_LEVEL_DISABLE);
7417
7418         /* WADPOClockGatingDisable:hsw */
7419         intel_uncore_write(&dev_priv->uncore, TRANS_CHICKEN1(PIPE_A),
7420                    intel_uncore_read(&dev_priv->uncore, TRANS_CHICKEN1(PIPE_A)) |
7421                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7422 }
7423
7424 static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
7425 {
7426         if (HAS_PCH_LPT_LP(dev_priv)) {
7427                 u32 val = intel_uncore_read(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D);
7428
7429                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7430                 intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, val);
7431         }
7432 }
7433
7434 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7435                                    int general_prio_credits,
7436                                    int high_prio_credits)
7437 {
7438         u32 misccpctl;
7439         u32 val;
7440
7441         /* WaTempDisableDOPClkGating:bdw */
7442         misccpctl = intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL);
7443         intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7444
7445         val = intel_uncore_read(&dev_priv->uncore, GEN8_L3SQCREG1);
7446         val &= ~L3_PRIO_CREDITS_MASK;
7447         val |= L3_GENERAL_PRIO_CREDITS(general_prio_credits);
7448         val |= L3_HIGH_PRIO_CREDITS(high_prio_credits);
7449         intel_uncore_write(&dev_priv->uncore, GEN8_L3SQCREG1, val);
7450
7451         /*
7452          * Wait at least 100 clocks before re-enabling clock gating.
7453          * See the definition of L3SQCREG1 in BSpec.
7454          */
7455         intel_uncore_posting_read(&dev_priv->uncore, GEN8_L3SQCREG1);
7456         udelay(1);
7457         intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl);
7458 }
7459
7460 static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
7461 {
7462         /* Wa_1409120013:icl,ehl */
7463         intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
7464                    ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
7465
7466         /*Wa_14010594013:icl, ehl */
7467         intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
7468                          0, ICL_DELAY_PMRSP);
7469 }
7470
7471 static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
7472 {
7473         /* Wa_1409120013:tgl,rkl,adl-s,dg1 */
7474         if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
7475             IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv))
7476                 intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
7477                                    ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
7478
7479         /* Wa_1409825376:tgl (pre-prod)*/
7480         if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
7481                 intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
7482                            TGL_VRH_GATING_DIS);
7483
7484         /* Wa_14013723622:tgl,rkl,dg1,adl-s */
7485         if (DISPLAY_VER(dev_priv) == 12)
7486                 intel_uncore_rmw(&dev_priv->uncore, CLKREQ_POLICY,
7487                                  CLKREQ_POLICY_MEM_UP_OVRD, 0);
7488 }
7489
7490 static void adlp_init_clock_gating(struct drm_i915_private *dev_priv)
7491 {
7492         gen12lp_init_clock_gating(dev_priv);
7493
7494         /* Wa_22011091694:adlp */
7495         intel_de_rmw(dev_priv, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS);
7496 }
7497
7498 static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)
7499 {
7500         gen12lp_init_clock_gating(dev_priv);
7501
7502         /* Wa_1409836686:dg1[a0] */
7503         if (IS_DG1_GT_STEP(dev_priv, STEP_A0, STEP_B0))
7504                 intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
7505                            DPT_GATING_DIS);
7506 }
7507
7508 static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
7509 {
7510         if (!HAS_PCH_CNP(dev_priv))
7511                 return;
7512
7513         /* Display WA #1181 WaSouthDisplayDisablePWMCGEGating: cnp */
7514         intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, intel_uncore_read(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D) |
7515                    CNP_PWM_CGE_GATING_DISABLE);
7516 }
7517
7518 static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
7519 {
7520         cnp_init_clock_gating(dev_priv);
7521         gen9_init_clock_gating(dev_priv);
7522
7523         /* WAC6entrylatency:cfl */
7524         intel_uncore_write(&dev_priv->uncore, FBC_LLC_READ_CTRL, intel_uncore_read(&dev_priv->uncore, FBC_LLC_READ_CTRL) |
7525                    FBC_LLC_FULLY_OPEN);
7526
7527         /*
7528          * WaFbcTurnOffFbcWatermark:cfl
7529          * Display WA #0562: cfl
7530          */
7531         intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
7532                    DISP_FBC_WM_DIS);
7533
7534         /*
7535          * WaFbcNukeOnHostModify:cfl
7536          * Display WA #0873: cfl
7537          */
7538         intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
7539                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7540 }
7541
7542 static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
7543 {
7544         gen9_init_clock_gating(dev_priv);
7545
7546         /* WAC6entrylatency:kbl */
7547         intel_uncore_write(&dev_priv->uncore, FBC_LLC_READ_CTRL, intel_uncore_read(&dev_priv->uncore, FBC_LLC_READ_CTRL) |
7548                    FBC_LLC_FULLY_OPEN);
7549
7550         /* WaDisableSDEUnitClockGating:kbl */
7551         if (IS_KBL_GT_STEP(dev_priv, 0, STEP_C0))
7552                 intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |
7553                            GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7554
7555         /* WaDisableGamClockGating:kbl */
7556         if (IS_KBL_GT_STEP(dev_priv, 0, STEP_C0))
7557                 intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1, intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) |
7558                            GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
7559
7560         /*
7561          * WaFbcTurnOffFbcWatermark:kbl
7562          * Display WA #0562: kbl
7563          */
7564         intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
7565                    DISP_FBC_WM_DIS);
7566
7567         /*
7568          * WaFbcNukeOnHostModify:kbl
7569          * Display WA #0873: kbl
7570          */
7571         intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
7572                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7573 }
7574
7575 static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
7576 {
7577         gen9_init_clock_gating(dev_priv);
7578
7579         /* WaDisableDopClockGating:skl */
7580         intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL) &
7581                    ~GEN7_DOP_CLOCK_GATE_ENABLE);
7582
7583         /* WAC6entrylatency:skl */
7584         intel_uncore_write(&dev_priv->uncore, FBC_LLC_READ_CTRL, intel_uncore_read(&dev_priv->uncore, FBC_LLC_READ_CTRL) |
7585                    FBC_LLC_FULLY_OPEN);
7586
7587         /*
7588          * WaFbcTurnOffFbcWatermark:skl
7589          * Display WA #0562: skl
7590          */
7591         intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
7592                    DISP_FBC_WM_DIS);
7593
7594         /*
7595          * WaFbcNukeOnHostModify:skl
7596          * Display WA #0873: skl
7597          */
7598         intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
7599                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7600
7601         /*
7602          * WaFbcHighMemBwCorruptionAvoidance:skl
7603          * Display WA #0883: skl
7604          */
7605         intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
7606                    ILK_DPFC_DISABLE_DUMMY0);
7607 }
7608
7609 static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
7610 {
7611         enum pipe pipe;
7612
7613         /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
7614         intel_uncore_write(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A),
7615                    intel_uncore_read(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A)) |
7616                    HSW_FBCQ_DIS);
7617
7618         /* WaSwitchSolVfFArbitrationPriority:bdw */
7619         intel_uncore_write(&dev_priv->uncore, GAM_ECOCHK, intel_uncore_read(&dev_priv->uncore, GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7620
7621         /* WaPsrDPAMaskVBlankInSRD:bdw */
7622         intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1,
7623                    intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7624
7625         for_each_pipe(dev_priv, pipe) {
7626                 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
7627                 intel_uncore_write(&dev_priv->uncore, CHICKEN_PIPESL_1(pipe),
7628                            intel_uncore_read(&dev_priv->uncore, CHICKEN_PIPESL_1(pipe)) |
7629                            BDW_DPRS_MASK_VBLANK_SRD);
7630
7631                 /* Undocumented but fixes async flip + VT-d corruption */
7632                 if (intel_vtd_active())
7633                         intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PIPESL_1(pipe),
7634                                          HSW_PRI_STRETCH_MAX_MASK, HSW_PRI_STRETCH_MAX_X1);
7635         }
7636
7637         /* WaVSRefCountFullforceMissDisable:bdw */
7638         /* WaDSRefCountFullforceMissDisable:bdw */
7639         intel_uncore_write(&dev_priv->uncore, GEN7_FF_THREAD_MODE,
7640                    intel_uncore_read(&dev_priv->uncore, GEN7_FF_THREAD_MODE) &
7641                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7642
7643         intel_uncore_write(&dev_priv->uncore, GEN6_RC_SLEEP_PSMI_CONTROL,
7644                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7645
7646         /* WaDisableSDEUnitClockGating:bdw */
7647         intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |
7648                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7649
7650         /* WaProgramL3SqcReg1Default:bdw */
7651         gen8_set_l3sqc_credits(dev_priv, 30, 2);
7652
7653         /* WaKVMNotificationOnConfigChange:bdw */
7654         intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR2_1, intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR2_1)
7655                    | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7656
7657         lpt_init_clock_gating(dev_priv);
7658
7659         /* WaDisableDopClockGating:bdw
7660          *
7661          * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
7662          * clock gating.
7663          */
7664         intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1,
7665                    intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
7666 }
7667
7668 static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
7669 {
7670         enum pipe pipe;
7671
7672         /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
7673         intel_uncore_write(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A),
7674                    intel_uncore_read(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A)) |
7675                    HSW_FBCQ_DIS);
7676
7677         for_each_pipe(dev_priv, pipe) {
7678                 /* Undocumented but fixes async flip + VT-d corruption */
7679                 if (intel_vtd_active())
7680                         intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PIPESL_1(pipe),
7681                                          HSW_PRI_STRETCH_MAX_MASK, HSW_PRI_STRETCH_MAX_X1);
7682         }
7683
7684         /* This is required by WaCatErrorRejectionIssue:hsw */
7685         intel_uncore_write(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7686                    intel_uncore_read(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7687                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7688
7689         /* WaSwitchSolVfFArbitrationPriority:hsw */
7690         intel_uncore_write(&dev_priv->uncore, GAM_ECOCHK, intel_uncore_read(&dev_priv->uncore, GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7691
7692         lpt_init_clock_gating(dev_priv);
7693 }
7694
7695 static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
7696 {
7697         u32 snpcr;
7698
7699         intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
7700
7701         /* WaFbcAsynchFlipDisableFbcQueue:ivb */
7702         intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1,
7703                    intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1) |
7704                    ILK_FBCQ_DIS);
7705
7706         /* WaDisableBackToBackFlipFix:ivb */
7707         intel_uncore_write(&dev_priv->uncore, IVB_CHICKEN3,
7708                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7709                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7710
7711         if (IS_IVB_GT1(dev_priv))
7712                 intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2,
7713                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7714         else {
7715                 /* must write both registers */
7716                 intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2,
7717                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7718                 intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2_GT2,
7719                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7720         }
7721
7722         /*
7723          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7724          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
7725          */
7726         intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2,
7727                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7728
7729         /* This is required by WaCatErrorRejectionIssue:ivb */
7730         intel_uncore_write(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7731                         intel_uncore_read(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7732                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7733
7734         g4x_disable_trickle_feed(dev_priv);
7735
7736         snpcr = intel_uncore_read(&dev_priv->uncore, GEN6_MBCUNIT_SNPCR);
7737         snpcr &= ~GEN6_MBC_SNPCR_MASK;
7738         snpcr |= GEN6_MBC_SNPCR_MED;
7739         intel_uncore_write(&dev_priv->uncore, GEN6_MBCUNIT_SNPCR, snpcr);
7740
7741         if (!HAS_PCH_NOP(dev_priv))
7742                 cpt_init_clock_gating(dev_priv);
7743
7744         gen6_check_mch_setup(dev_priv);
7745 }
7746
7747 static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
7748 {
7749         /* WaDisableBackToBackFlipFix:vlv */
7750         intel_uncore_write(&dev_priv->uncore, IVB_CHICKEN3,
7751                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7752                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7753
7754         /* WaDisableDopClockGating:vlv */
7755         intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2,
7756                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7757
7758         /* This is required by WaCatErrorRejectionIssue:vlv */
7759         intel_uncore_write(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7760                    intel_uncore_read(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7761                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7762
7763         /*
7764          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7765          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7766          */
7767         intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2,
7768                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7769
7770         /* WaDisableL3Bank2xClockGate:vlv
7771          * Disabling L3 clock gating- MMIO 940c[25] = 1
7772          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7773         intel_uncore_write(&dev_priv->uncore, GEN7_UCGCTL4,
7774                    intel_uncore_read(&dev_priv->uncore, GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
7775
7776         /*
7777          * WaDisableVLVClockGating_VBIIssue:vlv
7778          * Disable clock gating on th GCFG unit to prevent a delay
7779          * in the reporting of vblank events.
7780          */
7781         intel_uncore_write(&dev_priv->uncore, VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
7782 }
7783
7784 static void chv_init_clock_gating(struct drm_i915_private *dev_priv)
7785 {
7786         /* WaVSRefCountFullforceMissDisable:chv */
7787         /* WaDSRefCountFullforceMissDisable:chv */
7788         intel_uncore_write(&dev_priv->uncore, GEN7_FF_THREAD_MODE,
7789                    intel_uncore_read(&dev_priv->uncore, GEN7_FF_THREAD_MODE) &
7790                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7791
7792         /* WaDisableSemaphoreAndSyncFlipWait:chv */
7793         intel_uncore_write(&dev_priv->uncore, GEN6_RC_SLEEP_PSMI_CONTROL,
7794                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7795
7796         /* WaDisableCSUnitClockGating:chv */
7797         intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1, intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) |
7798                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7799
7800         /* WaDisableSDEUnitClockGating:chv */
7801         intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |
7802                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7803
7804         /*
7805          * WaProgramL3SqcReg1Default:chv
7806          * See gfxspecs/Related Documents/Performance Guide/
7807          * LSQC Setting Recommendations.
7808          */
7809         gen8_set_l3sqc_credits(dev_priv, 38, 2);
7810 }
7811
7812 static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
7813 {
7814         u32 dspclk_gate;
7815
7816         intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D1, 0);
7817         intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7818                    GS_UNIT_CLOCK_GATE_DISABLE |
7819                    CL_UNIT_CLOCK_GATE_DISABLE);
7820         intel_uncore_write(&dev_priv->uncore, RAMCLK_GATE_D, 0);
7821         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7822                 OVRUNIT_CLOCK_GATE_DISABLE |
7823                 OVCUNIT_CLOCK_GATE_DISABLE;
7824         if (IS_GM45(dev_priv))
7825                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7826         intel_uncore_write(&dev_priv->uncore, DSPCLK_GATE_D, dspclk_gate);
7827
7828         g4x_disable_trickle_feed(dev_priv);
7829 }
7830
7831 static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv)
7832 {
7833         struct intel_uncore *uncore = &dev_priv->uncore;
7834
7835         intel_uncore_write(uncore, RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7836         intel_uncore_write(uncore, RENCLK_GATE_D2, 0);
7837         intel_uncore_write(uncore, DSPCLK_GATE_D, 0);
7838         intel_uncore_write(uncore, RAMCLK_GATE_D, 0);
7839         intel_uncore_write16(uncore, DEUC, 0);
7840         intel_uncore_write(uncore,
7841                            MI_ARB_STATE,
7842                            _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7843 }
7844
7845 static void i965g_init_clock_gating(struct drm_i915_private *dev_priv)
7846 {
7847         intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7848                    I965_RCC_CLOCK_GATE_DISABLE |
7849                    I965_RCPB_CLOCK_GATE_DISABLE |
7850                    I965_ISC_CLOCK_GATE_DISABLE |
7851                    I965_FBC_CLOCK_GATE_DISABLE);
7852         intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D2, 0);
7853         intel_uncore_write(&dev_priv->uncore, MI_ARB_STATE,
7854                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7855 }
7856
7857 static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
7858 {
7859         u32 dstate = intel_uncore_read(&dev_priv->uncore, D_STATE);
7860
7861         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7862                 DSTATE_DOT_CLOCK_GATING;
7863         intel_uncore_write(&dev_priv->uncore, D_STATE, dstate);
7864
7865         if (IS_PINEVIEW(dev_priv))
7866                 intel_uncore_write(&dev_priv->uncore, ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7867
7868         /* IIR "flip pending" means done if this bit is set */
7869         intel_uncore_write(&dev_priv->uncore, ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7870
7871         /* interrupts should cause a wake up from C3 */
7872         intel_uncore_write(&dev_priv->uncore, INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7873
7874         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7875         intel_uncore_write(&dev_priv->uncore, MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7876
7877         intel_uncore_write(&dev_priv->uncore, MI_ARB_STATE,
7878                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7879 }
7880
7881 static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
7882 {
7883         intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7884
7885         /* interrupts should cause a wake up from C3 */
7886         intel_uncore_write(&dev_priv->uncore, MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7887                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7888
7889         intel_uncore_write(&dev_priv->uncore, MEM_MODE,
7890                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7891
7892         /*
7893          * Have FBC ignore 3D activity since we use software
7894          * render tracking, and otherwise a pure 3D workload
7895          * (even if it just renders a single frame and then does
7896          * abosultely nothing) would not allow FBC to recompress
7897          * until a 2D blit occurs.
7898          */
7899         intel_uncore_write(&dev_priv->uncore, SCPD0,
7900                    _MASKED_BIT_ENABLE(SCPD_FBC_IGNORE_3D));
7901 }
7902
7903 static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
7904 {
7905         intel_uncore_write(&dev_priv->uncore, MEM_MODE,
7906                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7907                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7908 }
7909
7910 void intel_init_clock_gating(struct drm_i915_private *dev_priv)
7911 {
7912         dev_priv->display.init_clock_gating(dev_priv);
7913 }
7914
7915 void intel_suspend_hw(struct drm_i915_private *dev_priv)
7916 {
7917         if (HAS_PCH_LPT(dev_priv))
7918                 lpt_suspend_hw(dev_priv);
7919 }
7920
7921 static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
7922 {
7923         drm_dbg_kms(&dev_priv->drm,
7924                     "No clock gating settings or workarounds applied.\n");
7925 }
7926
7927 /**
7928  * intel_init_clock_gating_hooks - setup the clock gating hooks
7929  * @dev_priv: device private
7930  *
7931  * Setup the hooks that configure which clocks of a given platform can be
7932  * gated and also apply various GT and display specific workarounds for these
7933  * platforms. Note that some GT specific workarounds are applied separately
7934  * when GPU contexts or batchbuffers start their execution.
7935  */
7936 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7937 {
7938         if (IS_ALDERLAKE_P(dev_priv))
7939                 dev_priv->display.init_clock_gating = adlp_init_clock_gating;
7940         else if (IS_DG1(dev_priv))
7941                 dev_priv->display.init_clock_gating = dg1_init_clock_gating;
7942         else if (GRAPHICS_VER(dev_priv) == 12)
7943                 dev_priv->display.init_clock_gating = gen12lp_init_clock_gating;
7944         else if (GRAPHICS_VER(dev_priv) == 11)
7945                 dev_priv->display.init_clock_gating = icl_init_clock_gating;
7946         else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
7947                 dev_priv->display.init_clock_gating = cfl_init_clock_gating;
7948         else if (IS_SKYLAKE(dev_priv))
7949                 dev_priv->display.init_clock_gating = skl_init_clock_gating;
7950         else if (IS_KABYLAKE(dev_priv))
7951                 dev_priv->display.init_clock_gating = kbl_init_clock_gating;
7952         else if (IS_BROXTON(dev_priv))
7953                 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7954         else if (IS_GEMINILAKE(dev_priv))
7955                 dev_priv->display.init_clock_gating = glk_init_clock_gating;
7956         else if (IS_BROADWELL(dev_priv))
7957                 dev_priv->display.init_clock_gating = bdw_init_clock_gating;
7958         else if (IS_CHERRYVIEW(dev_priv))
7959                 dev_priv->display.init_clock_gating = chv_init_clock_gating;
7960         else if (IS_HASWELL(dev_priv))
7961                 dev_priv->display.init_clock_gating = hsw_init_clock_gating;
7962         else if (IS_IVYBRIDGE(dev_priv))
7963                 dev_priv->display.init_clock_gating = ivb_init_clock_gating;
7964         else if (IS_VALLEYVIEW(dev_priv))
7965                 dev_priv->display.init_clock_gating = vlv_init_clock_gating;
7966         else if (GRAPHICS_VER(dev_priv) == 6)
7967                 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7968         else if (GRAPHICS_VER(dev_priv) == 5)
7969                 dev_priv->display.init_clock_gating = ilk_init_clock_gating;
7970         else if (IS_G4X(dev_priv))
7971                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7972         else if (IS_I965GM(dev_priv))
7973                 dev_priv->display.init_clock_gating = i965gm_init_clock_gating;
7974         else if (IS_I965G(dev_priv))
7975                 dev_priv->display.init_clock_gating = i965g_init_clock_gating;
7976         else if (GRAPHICS_VER(dev_priv) == 3)
7977                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7978         else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7979                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7980         else if (GRAPHICS_VER(dev_priv) == 2)
7981                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7982         else {
7983                 MISSING_CASE(INTEL_DEVID(dev_priv));
7984                 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7985         }
7986 }
7987
7988 /* Set up chip specific power management-related functions */
7989 void intel_init_pm(struct drm_i915_private *dev_priv)
7990 {
7991         /* For cxsr */
7992         if (IS_PINEVIEW(dev_priv))
7993                 pnv_get_mem_freq(dev_priv);
7994         else if (GRAPHICS_VER(dev_priv) == 5)
7995                 ilk_get_mem_freq(dev_priv);
7996
7997         if (intel_has_sagv(dev_priv))
7998                 skl_setup_sagv_block_time(dev_priv);
7999
8000         /* For FIFO watermark updates */
8001         if (DISPLAY_VER(dev_priv) >= 9) {
8002                 skl_setup_wm_latency(dev_priv);
8003                 dev_priv->display.compute_global_watermarks = skl_compute_wm;
8004         } else if (HAS_PCH_SPLIT(dev_priv)) {
8005                 ilk_setup_wm_latency(dev_priv);
8006
8007                 if ((DISPLAY_VER(dev_priv) == 5 && dev_priv->wm.pri_latency[1] &&
8008                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
8009                     (DISPLAY_VER(dev_priv) != 5 && dev_priv->wm.pri_latency[0] &&
8010                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
8011                         dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
8012                         dev_priv->display.compute_intermediate_wm =
8013                                 ilk_compute_intermediate_wm;
8014                         dev_priv->display.initial_watermarks =
8015                                 ilk_initial_watermarks;
8016                         dev_priv->display.optimize_watermarks =
8017                                 ilk_optimize_watermarks;
8018                 } else {
8019                         drm_dbg_kms(&dev_priv->drm,
8020                                     "Failed to read display plane latency. "
8021                                     "Disable CxSR\n");
8022                 }
8023         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
8024                 vlv_setup_wm_latency(dev_priv);
8025                 dev_priv->display.compute_pipe_wm = vlv_compute_pipe_wm;
8026                 dev_priv->display.compute_intermediate_wm = vlv_compute_intermediate_wm;
8027                 dev_priv->display.initial_watermarks = vlv_initial_watermarks;
8028                 dev_priv->display.optimize_watermarks = vlv_optimize_watermarks;
8029                 dev_priv->display.atomic_update_watermarks = vlv_atomic_update_fifo;
8030         } else if (IS_G4X(dev_priv)) {
8031                 g4x_setup_wm_latency(dev_priv);
8032                 dev_priv->display.compute_pipe_wm = g4x_compute_pipe_wm;
8033                 dev_priv->display.compute_intermediate_wm = g4x_compute_intermediate_wm;
8034                 dev_priv->display.initial_watermarks = g4x_initial_watermarks;
8035                 dev_priv->display.optimize_watermarks = g4x_optimize_watermarks;
8036         } else if (IS_PINEVIEW(dev_priv)) {
8037                 if (!intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
8038                                             dev_priv->is_ddr3,
8039                                             dev_priv->fsb_freq,
8040                                             dev_priv->mem_freq)) {
8041                         drm_info(&dev_priv->drm,
8042                                  "failed to find known CxSR latency "
8043                                  "(found ddr%s fsb freq %d, mem freq %d), "
8044                                  "disabling CxSR\n",
8045                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
8046                                  dev_priv->fsb_freq, dev_priv->mem_freq);
8047                         /* Disable CxSR and never update its watermark again */
8048                         intel_set_memory_cxsr(dev_priv, false);
8049                         dev_priv->display.update_wm = NULL;
8050                 } else
8051                         dev_priv->display.update_wm = pnv_update_wm;
8052         } else if (DISPLAY_VER(dev_priv) == 4) {
8053                 dev_priv->display.update_wm = i965_update_wm;
8054         } else if (DISPLAY_VER(dev_priv) == 3) {
8055                 dev_priv->display.update_wm = i9xx_update_wm;
8056                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8057         } else if (DISPLAY_VER(dev_priv) == 2) {
8058                 if (INTEL_NUM_PIPES(dev_priv) == 1) {
8059                         dev_priv->display.update_wm = i845_update_wm;
8060                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
8061                 } else {
8062                         dev_priv->display.update_wm = i9xx_update_wm;
8063                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
8064                 }
8065         } else {
8066                 drm_err(&dev_priv->drm,
8067                         "unexpected fall-through in %s\n", __func__);
8068         }
8069 }
8070
8071 void intel_pm_setup(struct drm_i915_private *dev_priv)
8072 {
8073         dev_priv->runtime_pm.suspended = false;
8074         atomic_set(&dev_priv->runtime_pm.wakeref_count, 0);
8075 }
8076
8077 static struct intel_global_state *intel_dbuf_duplicate_state(struct intel_global_obj *obj)
8078 {
8079         struct intel_dbuf_state *dbuf_state;
8080
8081         dbuf_state = kmemdup(obj->state, sizeof(*dbuf_state), GFP_KERNEL);
8082         if (!dbuf_state)
8083                 return NULL;
8084
8085         return &dbuf_state->base;
8086 }
8087
8088 static void intel_dbuf_destroy_state(struct intel_global_obj *obj,
8089                                      struct intel_global_state *state)
8090 {
8091         kfree(state);
8092 }
8093
8094 static const struct intel_global_state_funcs intel_dbuf_funcs = {
8095         .atomic_duplicate_state = intel_dbuf_duplicate_state,
8096         .atomic_destroy_state = intel_dbuf_destroy_state,
8097 };
8098
8099 struct intel_dbuf_state *
8100 intel_atomic_get_dbuf_state(struct intel_atomic_state *state)
8101 {
8102         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
8103         struct intel_global_state *dbuf_state;
8104
8105         dbuf_state = intel_atomic_get_global_obj_state(state, &dev_priv->dbuf.obj);
8106         if (IS_ERR(dbuf_state))
8107                 return ERR_CAST(dbuf_state);
8108
8109         return to_intel_dbuf_state(dbuf_state);
8110 }
8111
8112 int intel_dbuf_init(struct drm_i915_private *dev_priv)
8113 {
8114         struct intel_dbuf_state *dbuf_state;
8115
8116         dbuf_state = kzalloc(sizeof(*dbuf_state), GFP_KERNEL);
8117         if (!dbuf_state)
8118                 return -ENOMEM;
8119
8120         intel_atomic_global_obj_init(dev_priv, &dev_priv->dbuf.obj,
8121                                      &dbuf_state->base, &intel_dbuf_funcs);
8122
8123         return 0;
8124 }
8125
8126 /*
8127  * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
8128  * update the request state of all DBUS slices.
8129  */
8130 static void update_mbus_pre_enable(struct intel_atomic_state *state)
8131 {
8132         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
8133         u32 mbus_ctl, dbuf_min_tracker_val;
8134         enum dbuf_slice slice;
8135         const struct intel_dbuf_state *dbuf_state =
8136                 intel_atomic_get_new_dbuf_state(state);
8137
8138         if (!IS_ALDERLAKE_P(dev_priv))
8139                 return;
8140
8141         /*
8142          * TODO: Implement vblank synchronized MBUS joining changes.
8143          * Must be properly coordinated with dbuf reprogramming.
8144          */
8145         if (dbuf_state->joined_mbus) {
8146                 mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN |
8147                         MBUS_JOIN_PIPE_SELECT_NONE;
8148                 dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(3);
8149         } else {
8150                 mbus_ctl = MBUS_HASHING_MODE_2x2 |
8151                         MBUS_JOIN_PIPE_SELECT_NONE;
8152                 dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(1);
8153         }
8154
8155         intel_de_rmw(dev_priv, MBUS_CTL,
8156                      MBUS_HASHING_MODE_MASK | MBUS_JOIN |
8157                      MBUS_JOIN_PIPE_SELECT_MASK, mbus_ctl);
8158
8159         for_each_dbuf_slice(dev_priv, slice)
8160                 intel_de_rmw(dev_priv, DBUF_CTL_S(slice),
8161                              DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
8162                              dbuf_min_tracker_val);
8163 }
8164
8165 void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
8166 {
8167         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
8168         const struct intel_dbuf_state *new_dbuf_state =
8169                 intel_atomic_get_new_dbuf_state(state);
8170         const struct intel_dbuf_state *old_dbuf_state =
8171                 intel_atomic_get_old_dbuf_state(state);
8172
8173         if (!new_dbuf_state ||
8174             ((new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices)
8175             && (new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus)))
8176                 return;
8177
8178         WARN_ON(!new_dbuf_state->base.changed);
8179
8180         update_mbus_pre_enable(state);
8181         gen9_dbuf_slices_update(dev_priv,
8182                                 old_dbuf_state->enabled_slices |
8183                                 new_dbuf_state->enabled_slices);
8184 }
8185
8186 void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
8187 {
8188         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
8189         const struct intel_dbuf_state *new_dbuf_state =
8190                 intel_atomic_get_new_dbuf_state(state);
8191         const struct intel_dbuf_state *old_dbuf_state =
8192                 intel_atomic_get_old_dbuf_state(state);
8193
8194         if (!new_dbuf_state ||
8195             ((new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices)
8196             && (new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus)))
8197                 return;
8198
8199         WARN_ON(!new_dbuf_state->base.changed);
8200
8201         gen9_dbuf_slices_update(dev_priv,
8202                                 new_dbuf_state->enabled_slices);
8203 }