drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/delay.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/i2c.h>
  32 #include <linux/slab.h>
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_edid.h>
  37 #include <drm/drm_hdcp.h>
  38 #include <drm/drm_scdc_helper.h>
  39 #include <drm/i915_drm.h>
  40 #include <drm/intel_lpe_audio.h>
  41
  42 #include "i915_drv.h"
  43 #include "intel_audio.h"
  44 #include "intel_connector.h"
  45 #include "intel_ddi.h"
  46 #include "intel_dp.h"
  47 #include "intel_drv.h"
  48 #include "intel_hdcp.h"
  49 #include "intel_hdmi.h"
  50 #include "intel_lspcon.h"
  51 #include "intel_sdvo.h"
  52 #include "intel_panel.h"
  53
  54 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  55 {
  56         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  57 }
  58
  59 static void
  60 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  61 {
  62         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  63         struct drm_i915_private *dev_priv = to_i915(dev);
  64         u32 enabled_bits;
  65
  66         enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  67
  68         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  69              "HDMI port enabled, expecting disabled\n");
  70 }
  71
  72 static void
  73 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
  74                                      enum transcoder cpu_transcoder)
  75 {
  76         WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
  77              TRANS_DDI_FUNC_ENABLE,
  78              "HDMI transcoder function enabled, expecting disabled\n");
  79 }
  80
  81 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  82 {
  83         struct intel_digital_port *intel_dig_port =
  84                 container_of(encoder, struct intel_digital_port, base.base);
  85         return &intel_dig_port->hdmi;
  86 }
  87
  88 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  89 {
  90         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  91 }
  92
  93 static u32 g4x_infoframe_index(unsigned int type)
  94 {
  95         switch (type) {
  96         case HDMI_PACKET_TYPE_GAMUT_METADATA:
  97                 return VIDEO_DIP_SELECT_GAMUT;
  98         case HDMI_INFOFRAME_TYPE_AVI:
  99                 return VIDEO_DIP_SELECT_AVI;
 100         case HDMI_INFOFRAME_TYPE_SPD:
 101                 return VIDEO_DIP_SELECT_SPD;
 102         case HDMI_INFOFRAME_TYPE_VENDOR:
 103                 return VIDEO_DIP_SELECT_VENDOR;
 104         default:
 105                 MISSING_CASE(type);
 106                 return 0;
 107         }
 108 }
 109
 110 static u32 g4x_infoframe_enable(unsigned int type)
 111 {
 112         switch (type) {
 113         case HDMI_PACKET_TYPE_GENERAL_CONTROL:
 114                 return VIDEO_DIP_ENABLE_GCP;
 115         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 116                 return VIDEO_DIP_ENABLE_GAMUT;
 117         case DP_SDP_VSC:
 118                 return 0;
 119         case HDMI_INFOFRAME_TYPE_AVI:
 120                 return VIDEO_DIP_ENABLE_AVI;
 121         case HDMI_INFOFRAME_TYPE_SPD:
 122                 return VIDEO_DIP_ENABLE_SPD;
 123         case HDMI_INFOFRAME_TYPE_VENDOR:
 124                 return VIDEO_DIP_ENABLE_VENDOR;
 125         default:
 126                 MISSING_CASE(type);
 127                 return 0;
 128         }
 129 }
 130
 131 static u32 hsw_infoframe_enable(unsigned int type)
 132 {
 133         switch (type) {
 134         case HDMI_PACKET_TYPE_GENERAL_CONTROL:
 135                 return VIDEO_DIP_ENABLE_GCP_HSW;
 136         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 137                 return VIDEO_DIP_ENABLE_GMP_HSW;
 138         case DP_SDP_VSC:
 139                 return VIDEO_DIP_ENABLE_VSC_HSW;
 140         case DP_SDP_PPS:
 141                 return VDIP_ENABLE_PPS;
 142         case HDMI_INFOFRAME_TYPE_AVI:
 143                 return VIDEO_DIP_ENABLE_AVI_HSW;
 144         case HDMI_INFOFRAME_TYPE_SPD:
 145                 return VIDEO_DIP_ENABLE_SPD_HSW;
 146         case HDMI_INFOFRAME_TYPE_VENDOR:
 147                 return VIDEO_DIP_ENABLE_VS_HSW;
 148         default:
 149                 MISSING_CASE(type);
 150                 return 0;
 151         }
 152 }
 153
 154 static i915_reg_t
 155 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 156                  enum transcoder cpu_transcoder,
 157                  unsigned int type,
 158                  int i)
 159 {
 160         switch (type) {
 161         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 162                 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
 163         case DP_SDP_VSC:
 164                 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
 165         case DP_SDP_PPS:
 166                 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
 167         case HDMI_INFOFRAME_TYPE_AVI:
 168                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
 169         case HDMI_INFOFRAME_TYPE_SPD:
 170                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
 171         case HDMI_INFOFRAME_TYPE_VENDOR:
 172                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
 173         default:
 174                 MISSING_CASE(type);
 175                 return INVALID_MMIO_REG;
 176         }
 177 }
 178
 179 static int hsw_dip_data_size(unsigned int type)
 180 {
 181         switch (type) {
 182         case DP_SDP_VSC:
 183                 return VIDEO_DIP_VSC_DATA_SIZE;
 184         case DP_SDP_PPS:
 185                 return VIDEO_DIP_PPS_DATA_SIZE;
 186         default:
 187                 return VIDEO_DIP_DATA_SIZE;
 188         }
 189 }
 190
 191 static void g4x_write_infoframe(struct intel_encoder *encoder,
 192                                 const struct intel_crtc_state *crtc_state,
 193                                 unsigned int type,
 194                                 const void *frame, ssize_t len)
 195 {
 196         const u32 *data = frame;
 197         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 198         u32 val = I915_READ(VIDEO_DIP_CTL);
 199         int i;
 200
 201         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 202
 203         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 204         val |= g4x_infoframe_index(type);
 205
 206         val &= ~g4x_infoframe_enable(type);
 207
 208         I915_WRITE(VIDEO_DIP_CTL, val);
 209
 210         for (i = 0; i < len; i += 4) {
 211                 I915_WRITE(VIDEO_DIP_DATA, *data);
 212                 data++;
 213         }
 214         /* Write every possible data byte to force correct ECC calculation. */
 215         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 216                 I915_WRITE(VIDEO_DIP_DATA, 0);
 217
 218         val |= g4x_infoframe_enable(type);
 219         val &= ~VIDEO_DIP_FREQ_MASK;
 220         val |= VIDEO_DIP_FREQ_VSYNC;
 221
 222         I915_WRITE(VIDEO_DIP_CTL, val);
 223         POSTING_READ(VIDEO_DIP_CTL);
 224 }
 225
 226 static void g4x_read_infoframe(struct intel_encoder *encoder,
 227                                const struct intel_crtc_state *crtc_state,
 228                                unsigned int type,
 229                                void *frame, ssize_t len)
 230 {
 231         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 232         u32 val, *data = frame;
 233         int i;
 234
 235         val = I915_READ(VIDEO_DIP_CTL);
 236
 237         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 238         val |= g4x_infoframe_index(type);
 239
 240         I915_WRITE(VIDEO_DIP_CTL, val);
 241
 242         for (i = 0; i < len; i += 4)
 243                 *data++ = I915_READ(VIDEO_DIP_DATA);
 244 }
 245
 246 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
 247                                   const struct intel_crtc_state *pipe_config)
 248 {
 249         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 250         u32 val = I915_READ(VIDEO_DIP_CTL);
 251
 252         if ((val & VIDEO_DIP_ENABLE) == 0)
 253                 return 0;
 254
 255         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 256                 return 0;
 257
 258         return val & (VIDEO_DIP_ENABLE_AVI |
 259                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 260 }
 261
 262 static void ibx_write_infoframe(struct intel_encoder *encoder,
 263                                 const struct intel_crtc_state *crtc_state,
 264                                 unsigned int type,
 265                                 const void *frame, ssize_t len)
 266 {
 267         const u32 *data = frame;
 268         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 269         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 270         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 271         u32 val = I915_READ(reg);
 272         int i;
 273
 274         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 275
 276         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 277         val |= g4x_infoframe_index(type);
 278
 279         val &= ~g4x_infoframe_enable(type);
 280
 281         I915_WRITE(reg, val);
 282
 283         for (i = 0; i < len; i += 4) {
 284                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 285                 data++;
 286         }
 287         /* Write every possible data byte to force correct ECC calculation. */
 288         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 289                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 290
 291         val |= g4x_infoframe_enable(type);
 292         val &= ~VIDEO_DIP_FREQ_MASK;
 293         val |= VIDEO_DIP_FREQ_VSYNC;
 294
 295         I915_WRITE(reg, val);
 296         POSTING_READ(reg);
 297 }
 298
 299 static void ibx_read_infoframe(struct intel_encoder *encoder,
 300                                const struct intel_crtc_state *crtc_state,
 301                                unsigned int type,
 302                                void *frame, ssize_t len)
 303 {
 304         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 305         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 306         u32 val, *data = frame;
 307         int i;
 308
 309         val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe));
 310
 311         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 312         val |= g4x_infoframe_index(type);
 313
 314         I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val);
 315
 316         for (i = 0; i < len; i += 4)
 317                 *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe));
 318 }
 319
 320 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
 321                                   const struct intel_crtc_state *pipe_config)
 322 {
 323         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 324         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 325         i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
 326         u32 val = I915_READ(reg);
 327
 328         if ((val & VIDEO_DIP_ENABLE) == 0)
 329                 return 0;
 330
 331         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 332                 return 0;
 333
 334         return val & (VIDEO_DIP_ENABLE_AVI |
 335                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 336                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 337 }
 338
 339 static void cpt_write_infoframe(struct intel_encoder *encoder,
 340                                 const struct intel_crtc_state *crtc_state,
 341                                 unsigned int type,
 342                                 const void *frame, ssize_t len)
 343 {
 344         const u32 *data = frame;
 345         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 346         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 347         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 348         u32 val = I915_READ(reg);
 349         int i;
 350
 351         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 352
 353         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 354         val |= g4x_infoframe_index(type);
 355
 356         /* The DIP control register spec says that we need to update the AVI
 357          * infoframe without clearing its enable bit */
 358         if (type != HDMI_INFOFRAME_TYPE_AVI)
 359                 val &= ~g4x_infoframe_enable(type);
 360
 361         I915_WRITE(reg, val);
 362
 363         for (i = 0; i < len; i += 4) {
 364                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 365                 data++;
 366         }
 367         /* Write every possible data byte to force correct ECC calculation. */
 368         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 369                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 370
 371         val |= g4x_infoframe_enable(type);
 372         val &= ~VIDEO_DIP_FREQ_MASK;
 373         val |= VIDEO_DIP_FREQ_VSYNC;
 374
 375         I915_WRITE(reg, val);
 376         POSTING_READ(reg);
 377 }
 378
 379 static void cpt_read_infoframe(struct intel_encoder *encoder,
 380                                const struct intel_crtc_state *crtc_state,
 381                                unsigned int type,
 382                                void *frame, ssize_t len)
 383 {
 384         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 385         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 386         u32 val, *data = frame;
 387         int i;
 388
 389         val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe));
 390
 391         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 392         val |= g4x_infoframe_index(type);
 393
 394         I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val);
 395
 396         for (i = 0; i < len; i += 4)
 397                 *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe));
 398 }
 399
 400 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
 401                                   const struct intel_crtc_state *pipe_config)
 402 {
 403         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 404         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 405         u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
 406
 407         if ((val & VIDEO_DIP_ENABLE) == 0)
 408                 return 0;
 409
 410         return val & (VIDEO_DIP_ENABLE_AVI |
 411                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 412                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 413 }
 414
 415 static void vlv_write_infoframe(struct intel_encoder *encoder,
 416                                 const struct intel_crtc_state *crtc_state,
 417                                 unsigned int type,
 418                                 const void *frame, ssize_t len)
 419 {
 420         const u32 *data = frame;
 421         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 422         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 423         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 424         u32 val = I915_READ(reg);
 425         int i;
 426
 427         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 428
 429         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 430         val |= g4x_infoframe_index(type);
 431
 432         val &= ~g4x_infoframe_enable(type);
 433
 434         I915_WRITE(reg, val);
 435
 436         for (i = 0; i < len; i += 4) {
 437                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 438                 data++;
 439         }
 440         /* Write every possible data byte to force correct ECC calculation. */
 441         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 442                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 443
 444         val |= g4x_infoframe_enable(type);
 445         val &= ~VIDEO_DIP_FREQ_MASK;
 446         val |= VIDEO_DIP_FREQ_VSYNC;
 447
 448         I915_WRITE(reg, val);
 449         POSTING_READ(reg);
 450 }
 451
 452 static void vlv_read_infoframe(struct intel_encoder *encoder,
 453                                const struct intel_crtc_state *crtc_state,
 454                                unsigned int type,
 455                                void *frame, ssize_t len)
 456 {
 457         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 458         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 459         u32 val, *data = frame;
 460         int i;
 461
 462         val = I915_READ(VLV_TVIDEO_DIP_CTL(crtc->pipe));
 463
 464         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 465         val |= g4x_infoframe_index(type);
 466
 467         I915_WRITE(VLV_TVIDEO_DIP_CTL(crtc->pipe), val);
 468
 469         for (i = 0; i < len; i += 4)
 470                 *data++ = I915_READ(VLV_TVIDEO_DIP_DATA(crtc->pipe));
 471 }
 472
 473 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
 474                                   const struct intel_crtc_state *pipe_config)
 475 {
 476         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 477         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 478         u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
 479
 480         if ((val & VIDEO_DIP_ENABLE) == 0)
 481                 return 0;
 482
 483         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 484                 return 0;
 485
 486         return val & (VIDEO_DIP_ENABLE_AVI |
 487                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 488                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 489 }
 490
 491 static void hsw_write_infoframe(struct intel_encoder *encoder,
 492                                 const struct intel_crtc_state *crtc_state,
 493                                 unsigned int type,
 494                                 const void *frame, ssize_t len)
 495 {
 496         const u32 *data = frame;
 497         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 498         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 499         i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
 500         int data_size;
 501         int i;
 502         u32 val = I915_READ(ctl_reg);
 503
 504         data_size = hsw_dip_data_size(type);
 505
 506         val &= ~hsw_infoframe_enable(type);
 507         I915_WRITE(ctl_reg, val);
 508
 509         for (i = 0; i < len; i += 4) {
 510                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 511                                             type, i >> 2), *data);
 512                 data++;
 513         }
 514         /* Write every possible data byte to force correct ECC calculation. */
 515         for (; i < data_size; i += 4)
 516                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 517                                             type, i >> 2), 0);
 518
 519         val |= hsw_infoframe_enable(type);
 520         I915_WRITE(ctl_reg, val);
 521         POSTING_READ(ctl_reg);
 522 }
 523
 524 static void hsw_read_infoframe(struct intel_encoder *encoder,
 525                                const struct intel_crtc_state *crtc_state,
 526                                unsigned int type,
 527                                void *frame, ssize_t len)
 528 {
 529         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 530         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 531         u32 val, *data = frame;
 532         int i;
 533
 534         val = I915_READ(HSW_TVIDEO_DIP_CTL(cpu_transcoder));
 535
 536         for (i = 0; i < len; i += 4)
 537                 *data++ = I915_READ(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 538                                                      type, i >> 2));
 539 }
 540
 541 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
 542                                   const struct intel_crtc_state *pipe_config)
 543 {
 544         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 545         u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
 546
 547         return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 548                       VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 549                       VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 550 }
 551
 552 static const u8 infoframe_type_to_idx[] = {
 553         HDMI_PACKET_TYPE_GENERAL_CONTROL,
 554         HDMI_PACKET_TYPE_GAMUT_METADATA,
 555         DP_SDP_VSC,
 556         HDMI_INFOFRAME_TYPE_AVI,
 557         HDMI_INFOFRAME_TYPE_SPD,
 558         HDMI_INFOFRAME_TYPE_VENDOR,
 559 };
 560
 561 u32 intel_hdmi_infoframe_enable(unsigned int type)
 562 {
 563         int i;
 564
 565         for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
 566                 if (infoframe_type_to_idx[i] == type)
 567                         return BIT(i);
 568         }
 569
 570         return 0;
 571 }
 572
 573 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
 574                                   const struct intel_crtc_state *crtc_state)
 575 {
 576         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 577         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
 578         u32 val, ret = 0;
 579         int i;
 580
 581         val = dig_port->infoframes_enabled(encoder, crtc_state);
 582
 583         /* map from hardware bits to dip idx */
 584         for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
 585                 unsigned int type = infoframe_type_to_idx[i];
 586
 587                 if (HAS_DDI(dev_priv)) {
 588                         if (val & hsw_infoframe_enable(type))
 589                                 ret |= BIT(i);
 590                 } else {
 591                         if (val & g4x_infoframe_enable(type))
 592                                 ret |= BIT(i);
 593                 }
 594         }
 595
 596         return ret;
 597 }
 598
 599 /*
 600  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 601  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 602  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 603  * used for both technologies.
 604  *
 605  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 606  * DW1:       DB3       | DB2 | DB1 | DB0
 607  * DW2:       DB7       | DB6 | DB5 | DB4
 608  * DW3: ...
 609  *
 610  * (HB is Header Byte, DB is Data Byte)
 611  *
 612  * The hdmi pack() functions don't know about that hardware specific hole so we
 613  * trick them by giving an offset into the buffer and moving back the header
 614  * bytes by one.
 615  */
 616 static void intel_write_infoframe(struct intel_encoder *encoder,
 617                                   const struct intel_crtc_state *crtc_state,
 618                                   enum hdmi_infoframe_type type,
 619                                   const union hdmi_infoframe *frame)
 620 {
 621         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
 622         u8 buffer[VIDEO_DIP_DATA_SIZE];
 623         ssize_t len;
 624
 625         if ((crtc_state->infoframes.enable &
 626              intel_hdmi_infoframe_enable(type)) == 0)
 627                 return;
 628
 629         if (WARN_ON(frame->any.type != type))
 630                 return;
 631
 632         /* see comment above for the reason for this offset */
 633         len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
 634         if (WARN_ON(len < 0))
 635                 return;
 636
 637         /* Insert the 'hole' (see big comment above) at position 3 */
 638         memmove(&buffer[0], &buffer[1], 3);
 639         buffer[3] = 0;
 640         len++;
 641
 642         intel_dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
 643 }
 644
 645 void intel_read_infoframe(struct intel_encoder *encoder,
 646                           const struct intel_crtc_state *crtc_state,
 647                           enum hdmi_infoframe_type type,
 648                           union hdmi_infoframe *frame)
 649 {
 650         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
 651         u8 buffer[VIDEO_DIP_DATA_SIZE];
 652         int ret;
 653
 654         if ((crtc_state->infoframes.enable &
 655              intel_hdmi_infoframe_enable(type)) == 0)
 656                 return;
 657
 658         intel_dig_port->read_infoframe(encoder, crtc_state,
 659                                        type, buffer, sizeof(buffer));
 660
 661         /* Fill the 'hole' (see big comment above) at position 3 */
 662         memmove(&buffer[1], &buffer[0], 3);
 663
 664         /* see comment above for the reason for this offset */
 665         ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
 666         if (ret) {
 667                 DRM_DEBUG_KMS("Failed to unpack infoframe type 0x%02x\n", type);
 668                 return;
 669         }
 670
 671         if (frame->any.type != type)
 672                 DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
 673                               frame->any.type, type);
 674 }
 675
 676 static bool
 677 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
 678                                  struct intel_crtc_state *crtc_state,
 679                                  struct drm_connector_state *conn_state)
 680 {
 681         struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
 682         const struct drm_display_mode *adjusted_mode =
 683                 &crtc_state->base.adjusted_mode;
 684         struct drm_connector *connector = conn_state->connector;
 685         int ret;
 686
 687         if (!crtc_state->has_infoframe)
 688                 return true;
 689
 690         crtc_state->infoframes.enable |=
 691                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
 692
 693         ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector,
 694                                                        adjusted_mode);
 695         if (ret)
 696                 return false;
 697
 698         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 699                 frame->colorspace = HDMI_COLORSPACE_YUV420;
 700         else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 701                 frame->colorspace = HDMI_COLORSPACE_YUV444;
 702         else
 703                 frame->colorspace = HDMI_COLORSPACE_RGB;
 704
 705         drm_hdmi_avi_infoframe_colorspace(frame, conn_state);
 706
 707         drm_hdmi_avi_infoframe_quant_range(frame, connector,
 708                                            adjusted_mode,
 709                                            crtc_state->limited_color_range ?
 710                                            HDMI_QUANTIZATION_RANGE_LIMITED :
 711                                            HDMI_QUANTIZATION_RANGE_FULL);
 712
 713         drm_hdmi_avi_infoframe_content_type(frame, conn_state);
 714
 715         /* TODO: handle pixel repetition for YCBCR420 outputs */
 716
 717         ret = hdmi_avi_infoframe_check(frame);
 718         if (WARN_ON(ret))
 719                 return false;
 720
 721         return true;
 722 }
 723
 724 static bool
 725 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
 726                                  struct intel_crtc_state *crtc_state,
 727                                  struct drm_connector_state *conn_state)
 728 {
 729         struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
 730         int ret;
 731
 732         if (!crtc_state->has_infoframe)
 733                 return true;
 734
 735         crtc_state->infoframes.enable |=
 736                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
 737
 738         ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
 739         if (WARN_ON(ret))
 740                 return false;
 741
 742         frame->sdi = HDMI_SPD_SDI_PC;
 743
 744         ret = hdmi_spd_infoframe_check(frame);
 745         if (WARN_ON(ret))
 746                 return false;
 747
 748         return true;
 749 }
 750
 751 static bool
 752 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
 753                                   struct intel_crtc_state *crtc_state,
 754                                   struct drm_connector_state *conn_state)
 755 {
 756         struct hdmi_vendor_infoframe *frame =
 757                 &crtc_state->infoframes.hdmi.vendor.hdmi;
 758         const struct drm_display_info *info =
 759                 &conn_state->connector->display_info;
 760         int ret;
 761
 762         if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
 763                 return true;
 764
 765         crtc_state->infoframes.enable |=
 766                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);
 767
 768         ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
 769                                                           conn_state->connector,
 770                                                           &crtc_state->base.adjusted_mode);
 771         if (WARN_ON(ret))
 772                 return false;
 773
 774         ret = hdmi_vendor_infoframe_check(frame);
 775         if (WARN_ON(ret))
 776                 return false;
 777
 778         return true;
 779 }
 780
 781 static void g4x_set_infoframes(struct intel_encoder *encoder,
 782                                bool enable,
 783                                const struct intel_crtc_state *crtc_state,
 784                                const struct drm_connector_state *conn_state)
 785 {
 786         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 787         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
 788         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 789         i915_reg_t reg = VIDEO_DIP_CTL;
 790         u32 val = I915_READ(reg);
 791         u32 port = VIDEO_DIP_PORT(encoder->port);
 792
 793         assert_hdmi_port_disabled(intel_hdmi);
 794
 795         /* If the registers were not initialized yet, they might be zeroes,
 796          * which means we're selecting the AVI DIP and we're setting its
 797          * frequency to once. This seems to really confuse the HW and make
 798          * things stop working (the register spec says the AVI always needs to
 799          * be sent every VSync). So here we avoid writing to the register more
 800          * than we need and also explicitly select the AVI DIP and explicitly
 801          * set its frequency to every VSync. Avoiding to write it twice seems to
 802          * be enough to solve the problem, but being defensive shouldn't hurt us
 803          * either. */
 804         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 805
 806         if (!enable) {
 807                 if (!(val & VIDEO_DIP_ENABLE))
 808                         return;
 809                 if (port != (val & VIDEO_DIP_PORT_MASK)) {
 810                         DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
 811                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 812                         return;
 813                 }
 814                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 815                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 816                 I915_WRITE(reg, val);
 817                 POSTING_READ(reg);
 818                 return;
 819         }
 820
 821         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 822                 if (val & VIDEO_DIP_ENABLE) {
 823                         DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
 824                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 825                         return;
 826                 }
 827                 val &= ~VIDEO_DIP_PORT_MASK;
 828                 val |= port;
 829         }
 830
 831         val |= VIDEO_DIP_ENABLE;
 832         val &= ~(VIDEO_DIP_ENABLE_AVI |
 833                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 834
 835         I915_WRITE(reg, val);
 836         POSTING_READ(reg);
 837
 838         intel_write_infoframe(encoder, crtc_state,
 839                               HDMI_INFOFRAME_TYPE_AVI,
 840                               &crtc_state->infoframes.avi);
 841         intel_write_infoframe(encoder, crtc_state,
 842                               HDMI_INFOFRAME_TYPE_SPD,
 843                               &crtc_state->infoframes.spd);
 844         intel_write_infoframe(encoder, crtc_state,
 845                               HDMI_INFOFRAME_TYPE_VENDOR,
 846                               &crtc_state->infoframes.hdmi);
 847 }
 848
 849 static bool hdmi_sink_is_deep_color(const struct drm_connector_state *conn_state)
 850 {
 851         struct drm_connector *connector = conn_state->connector;
 852
 853         /*
 854          * HDMI cloning is only supported on g4x which doesn't
 855          * support deep color or GCP infoframes anyway so no
 856          * need to worry about multiple HDMI sinks here.
 857          */
 858
 859         return connector->display_info.bpc > 8;
 860 }
 861
 862 /*
 863  * Determine if default_phase=1 can be indicated in the GCP infoframe.
 864  *
 865  * From HDMI specification 1.4a:
 866  * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
 867  * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
 868  * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
 869  * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
 870  *   phase of 0
 871  */
 872 static bool gcp_default_phase_possible(int pipe_bpp,
 873                                        const struct drm_display_mode *mode)
 874 {
 875         unsigned int pixels_per_group;
 876
 877         switch (pipe_bpp) {
 878         case 30:
 879                 /* 4 pixels in 5 clocks */
 880                 pixels_per_group = 4;
 881                 break;
 882         case 36:
 883                 /* 2 pixels in 3 clocks */
 884                 pixels_per_group = 2;
 885                 break;
 886         case 48:
 887                 /* 1 pixel in 2 clocks */
 888                 pixels_per_group = 1;
 889                 break;
 890         default:
 891                 /* phase information not relevant for 8bpc */
 892                 return false;
 893         }
 894
 895         return mode->crtc_hdisplay % pixels_per_group == 0 &&
 896                 mode->crtc_htotal % pixels_per_group == 0 &&
 897                 mode->crtc_hblank_start % pixels_per_group == 0 &&
 898                 mode->crtc_hblank_end % pixels_per_group == 0 &&
 899                 mode->crtc_hsync_start % pixels_per_group == 0 &&
 900                 mode->crtc_hsync_end % pixels_per_group == 0 &&
 901                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
 902                  mode->crtc_htotal/2 % pixels_per_group == 0);
 903 }
 904
 905 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
 906                                          const struct intel_crtc_state *crtc_state,
 907                                          const struct drm_connector_state *conn_state)
 908 {
 909         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 910         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 911         i915_reg_t reg;
 912
 913         if ((crtc_state->infoframes.enable &
 914              intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
 915                 return false;
 916
 917         if (HAS_DDI(dev_priv))
 918                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
 919         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 920                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 921         else if (HAS_PCH_SPLIT(dev_priv))
 922                 reg = TVIDEO_DIP_GCP(crtc->pipe);
 923         else
 924                 return false;
 925
 926         I915_WRITE(reg, crtc_state->infoframes.gcp);
 927
 928         return true;
 929 }
 930
 931 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
 932                                    struct intel_crtc_state *crtc_state)
 933 {
 934         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 935         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 936         i915_reg_t reg;
 937
 938         if ((crtc_state->infoframes.enable &
 939              intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
 940                 return;
 941
 942         if (HAS_DDI(dev_priv))
 943                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
 944         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 945                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 946         else if (HAS_PCH_SPLIT(dev_priv))
 947                 reg = TVIDEO_DIP_GCP(crtc->pipe);
 948         else
 949                 return;
 950
 951         crtc_state->infoframes.gcp = I915_READ(reg);
 952 }
 953
 954 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
 955                                              struct intel_crtc_state *crtc_state,
 956                                              struct drm_connector_state *conn_state)
 957 {
 958         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 959
 960         if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
 961                 return;
 962
 963         crtc_state->infoframes.enable |=
 964                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
 965
 966         /* Indicate color depth whenever the sink supports deep color */
 967         if (hdmi_sink_is_deep_color(conn_state))
 968                 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
 969
 970         /* Enable default_phase whenever the display mode is suitably aligned */
 971         if (gcp_default_phase_possible(crtc_state->pipe_bpp,
 972                                        &crtc_state->base.adjusted_mode))
 973                 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
 974 }
 975
 976 static void ibx_set_infoframes(struct intel_encoder *encoder,
 977                                bool enable,
 978                                const struct intel_crtc_state *crtc_state,
 979                                const struct drm_connector_state *conn_state)
 980 {
 981         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 982         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 983         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
 984         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 985         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 986         u32 val = I915_READ(reg);
 987         u32 port = VIDEO_DIP_PORT(encoder->port);
 988
 989         assert_hdmi_port_disabled(intel_hdmi);
 990
 991         /* See the big comment in g4x_set_infoframes() */
 992         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 993
 994         if (!enable) {
 995                 if (!(val & VIDEO_DIP_ENABLE))
 996                         return;
 997                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 998                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 999                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1000                 I915_WRITE(reg, val);
1001                 POSTING_READ(reg);
1002                 return;
1003         }
1004
1005         if (port != (val & VIDEO_DIP_PORT_MASK)) {
1006                 WARN(val & VIDEO_DIP_ENABLE,
1007                      "DIP already enabled on port %c\n",
1008                      (val & VIDEO_DIP_PORT_MASK) >> 29);
1009                 val &= ~VIDEO_DIP_PORT_MASK;
1010                 val |= port;
1011         }
1012
1013         val |= VIDEO_DIP_ENABLE;
1014         val &= ~(VIDEO_DIP_ENABLE_AVI |
1015                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1016                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1017
1018         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1019                 val |= VIDEO_DIP_ENABLE_GCP;
1020
1021         I915_WRITE(reg, val);
1022         POSTING_READ(reg);
1023
1024         intel_write_infoframe(encoder, crtc_state,
1025                               HDMI_INFOFRAME_TYPE_AVI,
1026                               &crtc_state->infoframes.avi);
1027         intel_write_infoframe(encoder, crtc_state,
1028                               HDMI_INFOFRAME_TYPE_SPD,
1029                               &crtc_state->infoframes.spd);
1030         intel_write_infoframe(encoder, crtc_state,
1031                               HDMI_INFOFRAME_TYPE_VENDOR,
1032                               &crtc_state->infoframes.hdmi);
1033 }
1034
1035 static void cpt_set_infoframes(struct intel_encoder *encoder,
1036                                bool enable,
1037                                const struct intel_crtc_state *crtc_state,
1038                                const struct drm_connector_state *conn_state)
1039 {
1040         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1041         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1042         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1043         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
1044         u32 val = I915_READ(reg);
1045
1046         assert_hdmi_port_disabled(intel_hdmi);
1047
1048         /* See the big comment in g4x_set_infoframes() */
1049         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1050
1051         if (!enable) {
1052                 if (!(val & VIDEO_DIP_ENABLE))
1053                         return;
1054                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1055                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1056                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1057                 I915_WRITE(reg, val);
1058                 POSTING_READ(reg);
1059                 return;
1060         }
1061
1062         /* Set both together, unset both together: see the spec. */
1063         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
1064         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1065                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1066
1067         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1068                 val |= VIDEO_DIP_ENABLE_GCP;
1069
1070         I915_WRITE(reg, val);
1071         POSTING_READ(reg);
1072
1073         intel_write_infoframe(encoder, crtc_state,
1074                               HDMI_INFOFRAME_TYPE_AVI,
1075                               &crtc_state->infoframes.avi);
1076         intel_write_infoframe(encoder, crtc_state,
1077                               HDMI_INFOFRAME_TYPE_SPD,
1078                               &crtc_state->infoframes.spd);
1079         intel_write_infoframe(encoder, crtc_state,
1080                               HDMI_INFOFRAME_TYPE_VENDOR,
1081                               &crtc_state->infoframes.hdmi);
1082 }
1083
1084 static void vlv_set_infoframes(struct intel_encoder *encoder,
1085                                bool enable,
1086                                const struct intel_crtc_state *crtc_state,
1087                                const struct drm_connector_state *conn_state)
1088 {
1089         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1090         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1091         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1092         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
1093         u32 val = I915_READ(reg);
1094         u32 port = VIDEO_DIP_PORT(encoder->port);
1095
1096         assert_hdmi_port_disabled(intel_hdmi);
1097
1098         /* See the big comment in g4x_set_infoframes() */
1099         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1100
1101         if (!enable) {
1102                 if (!(val & VIDEO_DIP_ENABLE))
1103                         return;
1104                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1105                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1106                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1107                 I915_WRITE(reg, val);
1108                 POSTING_READ(reg);
1109                 return;
1110         }
1111
1112         if (port != (val & VIDEO_DIP_PORT_MASK)) {
1113                 WARN(val & VIDEO_DIP_ENABLE,
1114                      "DIP already enabled on port %c\n",
1115                      (val & VIDEO_DIP_PORT_MASK) >> 29);
1116                 val &= ~VIDEO_DIP_PORT_MASK;
1117                 val |= port;
1118         }
1119
1120         val |= VIDEO_DIP_ENABLE;
1121         val &= ~(VIDEO_DIP_ENABLE_AVI |
1122                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1123                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1124
1125         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1126                 val |= VIDEO_DIP_ENABLE_GCP;
1127
1128         I915_WRITE(reg, val);
1129         POSTING_READ(reg);
1130
1131         intel_write_infoframe(encoder, crtc_state,
1132                               HDMI_INFOFRAME_TYPE_AVI,
1133                               &crtc_state->infoframes.avi);
1134         intel_write_infoframe(encoder, crtc_state,
1135                               HDMI_INFOFRAME_TYPE_SPD,
1136                               &crtc_state->infoframes.spd);
1137         intel_write_infoframe(encoder, crtc_state,
1138                               HDMI_INFOFRAME_TYPE_VENDOR,
1139                               &crtc_state->infoframes.hdmi);
1140 }
1141
1142 static void hsw_set_infoframes(struct intel_encoder *encoder,
1143                                bool enable,
1144                                const struct intel_crtc_state *crtc_state,
1145                                const struct drm_connector_state *conn_state)
1146 {
1147         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1148         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
1149         u32 val = I915_READ(reg);
1150
1151         assert_hdmi_transcoder_func_disabled(dev_priv,
1152                                              crtc_state->cpu_transcoder);
1153
1154         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
1155                  VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
1156                  VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
1157
1158         if (!enable) {
1159                 I915_WRITE(reg, val);
1160                 POSTING_READ(reg);
1161                 return;
1162         }
1163
1164         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1165                 val |= VIDEO_DIP_ENABLE_GCP_HSW;
1166
1167         I915_WRITE(reg, val);
1168         POSTING_READ(reg);
1169
1170         intel_write_infoframe(encoder, crtc_state,
1171                               HDMI_INFOFRAME_TYPE_AVI,
1172                               &crtc_state->infoframes.avi);
1173         intel_write_infoframe(encoder, crtc_state,
1174                               HDMI_INFOFRAME_TYPE_SPD,
1175                               &crtc_state->infoframes.spd);
1176         intel_write_infoframe(encoder, crtc_state,
1177                               HDMI_INFOFRAME_TYPE_VENDOR,
1178                               &crtc_state->infoframes.hdmi);
1179 }
1180
1181 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
1182 {
1183         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1184         struct i2c_adapter *adapter =
1185                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1186
1187         if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
1188                 return;
1189
1190         DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
1191                       enable ? "Enabling" : "Disabling");
1192
1193         drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
1194                                          adapter, enable);
1195 }
1196
1197 static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port,
1198                                 unsigned int offset, void *buffer, size_t size)
1199 {
1200         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1201         struct drm_i915_private *dev_priv =
1202                 intel_dig_port->base.base.dev->dev_private;
1203         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
1204                                                               hdmi->ddc_bus);
1205         int ret;
1206         u8 start = offset & 0xff;
1207         struct i2c_msg msgs[] = {
1208                 {
1209                         .addr = DRM_HDCP_DDC_ADDR,
1210                         .flags = 0,
1211                         .len = 1,
1212                         .buf = &start,
1213                 },
1214                 {
1215                         .addr = DRM_HDCP_DDC_ADDR,
1216                         .flags = I2C_M_RD,
1217                         .len = size,
1218                         .buf = buffer
1219                 }
1220         };
1221         ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
1222         if (ret == ARRAY_SIZE(msgs))
1223                 return 0;
1224         return ret >= 0 ? -EIO : ret;
1225 }
1226
1227 static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port,
1228                                  unsigned int offset, void *buffer, size_t size)
1229 {
1230         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1231         struct drm_i915_private *dev_priv =
1232                 intel_dig_port->base.base.dev->dev_private;
1233         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
1234                                                               hdmi->ddc_bus);
1235         int ret;
1236         u8 *write_buf;
1237         struct i2c_msg msg;
1238
1239         write_buf = kzalloc(size + 1, GFP_KERNEL);
1240         if (!write_buf)
1241                 return -ENOMEM;
1242
1243         write_buf[0] = offset & 0xff;
1244         memcpy(&write_buf[1], buffer, size);
1245
1246         msg.addr = DRM_HDCP_DDC_ADDR;
1247         msg.flags = 0,
1248         msg.len = size + 1,
1249         msg.buf = write_buf;
1250
1251         ret = i2c_transfer(adapter, &msg, 1);
1252         if (ret == 1)
1253                 ret = 0;
1254         else if (ret >= 0)
1255                 ret = -EIO;
1256
1257         kfree(write_buf);
1258         return ret;
1259 }
1260
1261 static
1262 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
1263                                   u8 *an)
1264 {
1265         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1266         struct drm_i915_private *dev_priv =
1267                 intel_dig_port->base.base.dev->dev_private;
1268         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
1269                                                               hdmi->ddc_bus);
1270         int ret;
1271
1272         ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an,
1273                                     DRM_HDCP_AN_LEN);
1274         if (ret) {
1275                 DRM_DEBUG_KMS("Write An over DDC failed (%d)\n", ret);
1276                 return ret;
1277         }
1278
1279         ret = intel_gmbus_output_aksv(adapter);
1280         if (ret < 0) {
1281                 DRM_DEBUG_KMS("Failed to output aksv (%d)\n", ret);
1282                 return ret;
1283         }
1284         return 0;
1285 }
1286
1287 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
1288                                      u8 *bksv)
1289 {
1290         int ret;
1291         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv,
1292                                    DRM_HDCP_KSV_LEN);
1293         if (ret)
1294                 DRM_DEBUG_KMS("Read Bksv over DDC failed (%d)\n", ret);
1295         return ret;
1296 }
1297
1298 static
1299 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
1300                                  u8 *bstatus)
1301 {
1302         int ret;
1303         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS,
1304                                    bstatus, DRM_HDCP_BSTATUS_LEN);
1305         if (ret)
1306                 DRM_DEBUG_KMS("Read bstatus over DDC failed (%d)\n", ret);
1307         return ret;
1308 }
1309
1310 static
1311 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
1312                                      bool *repeater_present)
1313 {
1314         int ret;
1315         u8 val;
1316
1317         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1318         if (ret) {
1319                 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1320                 return ret;
1321         }
1322         *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1323         return 0;
1324 }
1325
1326 static
1327 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
1328                                   u8 *ri_prime)
1329 {
1330         int ret;
1331         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME,
1332                                    ri_prime, DRM_HDCP_RI_LEN);
1333         if (ret)
1334                 DRM_DEBUG_KMS("Read Ri' over DDC failed (%d)\n", ret);
1335         return ret;
1336 }
1337
1338 static
1339 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
1340                                    bool *ksv_ready)
1341 {
1342         int ret;
1343         u8 val;
1344
1345         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1346         if (ret) {
1347                 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1348                 return ret;
1349         }
1350         *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1351         return 0;
1352 }
1353
1354 static
1355 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
1356                                   int num_downstream, u8 *ksv_fifo)
1357 {
1358         int ret;
1359         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO,
1360                                    ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1361         if (ret) {
1362                 DRM_DEBUG_KMS("Read ksv fifo over DDC failed (%d)\n", ret);
1363                 return ret;
1364         }
1365         return 0;
1366 }
1367
1368 static
1369 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
1370                                       int i, u32 *part)
1371 {
1372         int ret;
1373
1374         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1375                 return -EINVAL;
1376
1377         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i),
1378                                    part, DRM_HDCP_V_PRIME_PART_LEN);
1379         if (ret)
1380                 DRM_DEBUG_KMS("Read V'[%d] over DDC failed (%d)\n", i, ret);
1381         return ret;
1382 }
1383
1384 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector)
1385 {
1386         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1387         struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
1388         struct drm_crtc *crtc = connector->base.state->crtc;
1389         struct intel_crtc *intel_crtc = container_of(crtc,
1390                                                      struct intel_crtc, base);
1391         u32 scanline;
1392         int ret;
1393
1394         for (;;) {
1395                 scanline = I915_READ(PIPEDSL(intel_crtc->pipe));
1396                 if (scanline > 100 && scanline < 200)
1397                         break;
1398                 usleep_range(25, 50);
1399         }
1400
1401         ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, false);
1402         if (ret) {
1403                 DRM_ERROR("Disable HDCP signalling failed (%d)\n", ret);
1404                 return ret;
1405         }
1406         ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, true);
1407         if (ret) {
1408                 DRM_ERROR("Enable HDCP signalling failed (%d)\n", ret);
1409                 return ret;
1410         }
1411
1412         return 0;
1413 }
1414
1415 static
1416 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
1417                                       bool enable)
1418 {
1419         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1420         struct intel_connector *connector = hdmi->attached_connector;
1421         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1422         int ret;
1423
1424         if (!enable)
1425                 usleep_range(6, 60); /* Bspec says >= 6us */
1426
1427         ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable);
1428         if (ret) {
1429                 DRM_ERROR("%s HDCP signalling failed (%d)\n",
1430                           enable ? "Enable" : "Disable", ret);
1431                 return ret;
1432         }
1433
1434         /*
1435          * WA: To fix incorrect positioning of the window of
1436          * opportunity and enc_en signalling in KABYLAKE.
1437          */
1438         if (IS_KABYLAKE(dev_priv) && enable)
1439                 return kbl_repositioning_enc_en_signal(connector);
1440
1441         return 0;
1442 }
1443
1444 static
1445 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
1446 {
1447         struct drm_i915_private *dev_priv =
1448                 intel_dig_port->base.base.dev->dev_private;
1449         enum port port = intel_dig_port->base.port;
1450         int ret;
1451         union {
1452                 u32 reg;
1453                 u8 shim[DRM_HDCP_RI_LEN];
1454         } ri;
1455
1456         ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim);
1457         if (ret)
1458                 return false;
1459
1460         I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
1461
1462         /* Wait for Ri prime match */
1463         if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
1464                      (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1465                 DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
1466                           I915_READ(PORT_HDCP_STATUS(port)));
1467                 return false;
1468         }
1469         return true;
1470 }
1471
1472 static struct hdcp2_hdmi_msg_data {
1473         u8 msg_id;
1474         u32 timeout;
1475         u32 timeout2;
1476         } hdcp2_msg_data[] = {
1477                 {HDCP_2_2_AKE_INIT, 0, 0},
1478                 {HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, 0},
1479                 {HDCP_2_2_AKE_NO_STORED_KM, 0, 0},
1480                 {HDCP_2_2_AKE_STORED_KM, 0, 0},
1481                 {HDCP_2_2_AKE_SEND_HPRIME, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
1482                                 HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS},
1483                 {HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS,
1484                                 0},
1485                 {HDCP_2_2_LC_INIT, 0, 0},
1486                 {HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, 0},
1487                 {HDCP_2_2_SKE_SEND_EKS, 0, 0},
1488                 {HDCP_2_2_REP_SEND_RECVID_LIST,
1489                                 HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0},
1490                 {HDCP_2_2_REP_SEND_ACK, 0, 0},
1491                 {HDCP_2_2_REP_STREAM_MANAGE, 0, 0},
1492                 {HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS,
1493                                 0},
1494         };
1495
1496 static
1497 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
1498                                     u8 *rx_status)
1499 {
1500         return intel_hdmi_hdcp_read(intel_dig_port,
1501                                     HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
1502                                     rx_status,
1503                                     HDCP_2_2_HDMI_RXSTATUS_LEN);
1504 }
1505
1506 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
1507 {
1508         int i;
1509
1510         for (i = 0; i < ARRAY_SIZE(hdcp2_msg_data); i++)
1511                 if (hdcp2_msg_data[i].msg_id == msg_id &&
1512                     (msg_id != HDCP_2_2_AKE_SEND_HPRIME || is_paired))
1513                         return hdcp2_msg_data[i].timeout;
1514                 else if (hdcp2_msg_data[i].msg_id == msg_id)
1515                         return hdcp2_msg_data[i].timeout2;
1516
1517         return -EINVAL;
1518 }
1519
1520 static inline
1521 int hdcp2_detect_msg_availability(struct intel_digital_port *intel_digital_port,
1522                                   u8 msg_id, bool *msg_ready,
1523                                   ssize_t *msg_sz)
1524 {
1525         u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1526         int ret;
1527
1528         ret = intel_hdmi_hdcp2_read_rx_status(intel_digital_port, rx_status);
1529         if (ret < 0) {
1530                 DRM_DEBUG_KMS("rx_status read failed. Err %d\n", ret);
1531                 return ret;
1532         }
1533
1534         *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
1535                   rx_status[0]);
1536
1537         if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
1538                 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
1539                              *msg_sz);
1540         else
1541                 *msg_ready = *msg_sz;
1542
1543         return 0;
1544 }
1545
1546 static ssize_t
1547 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
1548                               u8 msg_id, bool paired)
1549 {
1550         bool msg_ready = false;
1551         int timeout, ret;
1552         ssize_t msg_sz = 0;
1553
1554         timeout = get_hdcp2_msg_timeout(msg_id, paired);
1555         if (timeout < 0)
1556                 return timeout;
1557
1558         ret = __wait_for(ret = hdcp2_detect_msg_availability(intel_dig_port,
1559                                                              msg_id, &msg_ready,
1560                                                              &msg_sz),
1561                          !ret && msg_ready && msg_sz, timeout * 1000,
1562                          1000, 5 * 1000);
1563         if (ret)
1564                 DRM_DEBUG_KMS("msg_id: %d, ret: %d, timeout: %d\n",
1565                               msg_id, ret, timeout);
1566
1567         return ret ? ret : msg_sz;
1568 }
1569
1570 static
1571 int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
1572                                void *buf, size_t size)
1573 {
1574         unsigned int offset;
1575
1576         offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
1577         return intel_hdmi_hdcp_write(intel_dig_port, offset, buf, size);
1578 }
1579
1580 static
1581 int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
1582                               u8 msg_id, void *buf, size_t size)
1583 {
1584         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1585         struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
1586         unsigned int offset;
1587         ssize_t ret;
1588
1589         ret = intel_hdmi_hdcp2_wait_for_msg(intel_dig_port, msg_id,
1590                                             hdcp->is_paired);
1591         if (ret < 0)
1592                 return ret;
1593
1594         /*
1595          * Available msg size should be equal to or lesser than the
1596          * available buffer.
1597          */
1598         if (ret > size) {
1599                 DRM_DEBUG_KMS("msg_sz(%zd) is more than exp size(%zu)\n",
1600                               ret, size);
1601                 return -1;
1602         }
1603
1604         offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
1605         ret = intel_hdmi_hdcp_read(intel_dig_port, offset, buf, ret);
1606         if (ret)
1607                 DRM_DEBUG_KMS("Failed to read msg_id: %d(%zd)\n", msg_id, ret);
1608
1609         return ret;
1610 }
1611
1612 static
1613 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *intel_dig_port)
1614 {
1615         u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1616         int ret;
1617
1618         ret = intel_hdmi_hdcp2_read_rx_status(intel_dig_port, rx_status);
1619         if (ret)
1620                 return ret;
1621
1622         /*
1623          * Re-auth request and Link Integrity Failures are represented by
1624          * same bit. i.e reauth_req.
1625          */
1626         if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
1627                 ret = HDCP_REAUTH_REQUEST;
1628         else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
1629                 ret = HDCP_TOPOLOGY_CHANGE;
1630
1631         return ret;
1632 }
1633
1634 static
1635 int intel_hdmi_hdcp2_capable(struct intel_digital_port *intel_dig_port,
1636                              bool *capable)
1637 {
1638         u8 hdcp2_version;
1639         int ret;
1640
1641         *capable = false;
1642         ret = intel_hdmi_hdcp_read(intel_dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
1643                                    &hdcp2_version, sizeof(hdcp2_version));
1644         if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
1645                 *capable = true;
1646
1647         return ret;
1648 }
1649
1650 static inline
1651 enum hdcp_wired_protocol intel_hdmi_hdcp2_protocol(void)
1652 {
1653         return HDCP_PROTOCOL_HDMI;
1654 }
1655
1656 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1657         .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1658         .read_bksv = intel_hdmi_hdcp_read_bksv,
1659         .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1660         .repeater_present = intel_hdmi_hdcp_repeater_present,
1661         .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1662         .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1663         .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1664         .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1665         .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1666         .check_link = intel_hdmi_hdcp_check_link,
1667         .write_2_2_msg = intel_hdmi_hdcp2_write_msg,
1668         .read_2_2_msg = intel_hdmi_hdcp2_read_msg,
1669         .check_2_2_link = intel_hdmi_hdcp2_check_link,
1670         .hdcp_2_2_capable = intel_hdmi_hdcp2_capable,
1671         .protocol = HDCP_PROTOCOL_HDMI,
1672 };
1673
1674 static void intel_hdmi_prepare(struct intel_encoder *encoder,
1675                                const struct intel_crtc_state *crtc_state)
1676 {
1677         struct drm_device *dev = encoder->base.dev;
1678         struct drm_i915_private *dev_priv = to_i915(dev);
1679         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1680         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1681         const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
1682         u32 hdmi_val;
1683
1684         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1685
1686         hdmi_val = SDVO_ENCODING_HDMI;
1687         if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
1688                 hdmi_val |= HDMI_COLOR_RANGE_16_235;
1689         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1690                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
1691         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1692                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
1693
1694         if (crtc_state->pipe_bpp > 24)
1695                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
1696         else
1697                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
1698
1699         if (crtc_state->has_hdmi_sink)
1700                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
1701
1702         if (HAS_PCH_CPT(dev_priv))
1703                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1704         else if (IS_CHERRYVIEW(dev_priv))
1705                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
1706         else
1707                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
1708
1709         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
1710         POSTING_READ(intel_hdmi->hdmi_reg);
1711 }
1712
1713 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
1714                                     enum pipe *pipe)
1715 {
1716         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1717         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1718         intel_wakeref_t wakeref;
1719         bool ret;
1720
1721         wakeref = intel_display_power_get_if_enabled(dev_priv,
1722                                                      encoder->power_domain);
1723         if (!wakeref)
1724                 return false;
1725
1726         ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe);
1727
1728         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1729
1730         return ret;
1731 }
1732
1733 static void intel_hdmi_get_config(struct intel_encoder *encoder,
1734                                   struct intel_crtc_state *pipe_config)
1735 {
1736         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1737         struct drm_device *dev = encoder->base.dev;
1738         struct drm_i915_private *dev_priv = to_i915(dev);
1739         u32 tmp, flags = 0;
1740         int dotclock;
1741
1742         pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
1743
1744         tmp = I915_READ(intel_hdmi->hdmi_reg);
1745
1746         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
1747                 flags |= DRM_MODE_FLAG_PHSYNC;
1748         else
1749                 flags |= DRM_MODE_FLAG_NHSYNC;
1750
1751         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
1752                 flags |= DRM_MODE_FLAG_PVSYNC;
1753         else
1754                 flags |= DRM_MODE_FLAG_NVSYNC;
1755
1756         if (tmp & HDMI_MODE_SELECT_HDMI)
1757                 pipe_config->has_hdmi_sink = true;
1758
1759         pipe_config->infoframes.enable |=
1760                 intel_hdmi_infoframes_enabled(encoder, pipe_config);
1761
1762         if (pipe_config->infoframes.enable)
1763                 pipe_config->has_infoframe = true;
1764
1765         if (tmp & SDVO_AUDIO_ENABLE)
1766                 pipe_config->has_audio = true;
1767
1768         if (!HAS_PCH_SPLIT(dev_priv) &&
1769             tmp & HDMI_COLOR_RANGE_16_235)
1770                 pipe_config->limited_color_range = true;
1771
1772         pipe_config->base.adjusted_mode.flags |= flags;
1773
1774         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
1775                 dotclock = pipe_config->port_clock * 2 / 3;
1776         else
1777                 dotclock = pipe_config->port_clock;
1778
1779         if (pipe_config->pixel_multiplier)
1780                 dotclock /= pipe_config->pixel_multiplier;
1781
1782         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1783
1784         pipe_config->lane_count = 4;
1785
1786         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
1787
1788         intel_read_infoframe(encoder, pipe_config,
1789                              HDMI_INFOFRAME_TYPE_AVI,
1790                              &pipe_config->infoframes.avi);
1791         intel_read_infoframe(encoder, pipe_config,
1792                              HDMI_INFOFRAME_TYPE_SPD,
1793                              &pipe_config->infoframes.spd);
1794         intel_read_infoframe(encoder, pipe_config,
1795                              HDMI_INFOFRAME_TYPE_VENDOR,
1796                              &pipe_config->infoframes.hdmi);
1797 }
1798
1799 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
1800                                     const struct intel_crtc_state *pipe_config,
1801                                     const struct drm_connector_state *conn_state)
1802 {
1803         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1804
1805         WARN_ON(!pipe_config->has_hdmi_sink);
1806         DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
1807                          pipe_name(crtc->pipe));
1808         intel_audio_codec_enable(encoder, pipe_config, conn_state);
1809 }
1810
1811 static void g4x_enable_hdmi(struct intel_encoder *encoder,
1812                             const struct intel_crtc_state *pipe_config,
1813                             const struct drm_connector_state *conn_state)
1814 {
1815         struct drm_device *dev = encoder->base.dev;
1816         struct drm_i915_private *dev_priv = to_i915(dev);
1817         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1818         u32 temp;
1819
1820         temp = I915_READ(intel_hdmi->hdmi_reg);
1821
1822         temp |= SDVO_ENABLE;
1823         if (pipe_config->has_audio)
1824                 temp |= SDVO_AUDIO_ENABLE;
1825
1826         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1827         POSTING_READ(intel_hdmi->hdmi_reg);
1828
1829         if (pipe_config->has_audio)
1830                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1831 }
1832
1833 static void ibx_enable_hdmi(struct intel_encoder *encoder,
1834                             const struct intel_crtc_state *pipe_config,
1835                             const struct drm_connector_state *conn_state)
1836 {
1837         struct drm_device *dev = encoder->base.dev;
1838         struct drm_i915_private *dev_priv = to_i915(dev);
1839         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1840         u32 temp;
1841
1842         temp = I915_READ(intel_hdmi->hdmi_reg);
1843
1844         temp |= SDVO_ENABLE;
1845         if (pipe_config->has_audio)
1846                 temp |= SDVO_AUDIO_ENABLE;
1847
1848         /*
1849          * HW workaround, need to write this twice for issue
1850          * that may result in first write getting masked.
1851          */
1852         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1853         POSTING_READ(intel_hdmi->hdmi_reg);
1854         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1855         POSTING_READ(intel_hdmi->hdmi_reg);
1856
1857         /*
1858          * HW workaround, need to toggle enable bit off and on
1859          * for 12bpc with pixel repeat.
1860          *
1861          * FIXME: BSpec says this should be done at the end of
1862          * of the modeset sequence, so not sure if this isn't too soon.
1863          */
1864         if (pipe_config->pipe_bpp > 24 &&
1865             pipe_config->pixel_multiplier > 1) {
1866                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1867                 POSTING_READ(intel_hdmi->hdmi_reg);
1868
1869                 /*
1870                  * HW workaround, need to write this twice for issue
1871                  * that may result in first write getting masked.
1872                  */
1873                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1874                 POSTING_READ(intel_hdmi->hdmi_reg);
1875                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1876                 POSTING_READ(intel_hdmi->hdmi_reg);
1877         }
1878
1879         if (pipe_config->has_audio)
1880                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1881 }
1882
1883 static void cpt_enable_hdmi(struct intel_encoder *encoder,
1884                             const struct intel_crtc_state *pipe_config,
1885                             const struct drm_connector_state *conn_state)
1886 {
1887         struct drm_device *dev = encoder->base.dev;
1888         struct drm_i915_private *dev_priv = to_i915(dev);
1889         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1890         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1891         enum pipe pipe = crtc->pipe;
1892         u32 temp;
1893
1894         temp = I915_READ(intel_hdmi->hdmi_reg);
1895
1896         temp |= SDVO_ENABLE;
1897         if (pipe_config->has_audio)
1898                 temp |= SDVO_AUDIO_ENABLE;
1899
1900         /*
1901          * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1902          *
1903          * The procedure for 12bpc is as follows:
1904          * 1. disable HDMI clock gating
1905          * 2. enable HDMI with 8bpc
1906          * 3. enable HDMI with 12bpc
1907          * 4. enable HDMI clock gating
1908          */
1909
1910         if (pipe_config->pipe_bpp > 24) {
1911                 I915_WRITE(TRANS_CHICKEN1(pipe),
1912                            I915_READ(TRANS_CHICKEN1(pipe)) |
1913                            TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1914
1915                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1916                 temp |= SDVO_COLOR_FORMAT_8bpc;
1917         }
1918
1919         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1920         POSTING_READ(intel_hdmi->hdmi_reg);
1921
1922         if (pipe_config->pipe_bpp > 24) {
1923                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1924                 temp |= HDMI_COLOR_FORMAT_12bpc;
1925
1926                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1927                 POSTING_READ(intel_hdmi->hdmi_reg);
1928
1929                 I915_WRITE(TRANS_CHICKEN1(pipe),
1930                            I915_READ(TRANS_CHICKEN1(pipe)) &
1931                            ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1932         }
1933
1934         if (pipe_config->has_audio)
1935                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1936 }
1937
1938 static void vlv_enable_hdmi(struct intel_encoder *encoder,
1939                             const struct intel_crtc_state *pipe_config,
1940                             const struct drm_connector_state *conn_state)
1941 {
1942 }
1943
1944 static void intel_disable_hdmi(struct intel_encoder *encoder,
1945                                const struct intel_crtc_state *old_crtc_state,
1946                                const struct drm_connector_state *old_conn_state)
1947 {
1948         struct drm_device *dev = encoder->base.dev;
1949         struct drm_i915_private *dev_priv = to_i915(dev);
1950         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1951         struct intel_digital_port *intel_dig_port =
1952                 hdmi_to_dig_port(intel_hdmi);
1953         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1954         u32 temp;
1955
1956         temp = I915_READ(intel_hdmi->hdmi_reg);
1957
1958         temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1959         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1960         POSTING_READ(intel_hdmi->hdmi_reg);
1961
1962         /*
1963          * HW workaround for IBX, we need to move the port
1964          * to transcoder A after disabling it to allow the
1965          * matching DP port to be enabled on transcoder A.
1966          */
1967         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1968                 /*
1969                  * We get CPU/PCH FIFO underruns on the other pipe when
1970                  * doing the workaround. Sweep them under the rug.
1971                  */
1972                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1973                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1974
1975                 temp &= ~SDVO_PIPE_SEL_MASK;
1976                 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
1977                 /*
1978                  * HW workaround, need to write this twice for issue
1979                  * that may result in first write getting masked.
1980                  */
1981                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1982                 POSTING_READ(intel_hdmi->hdmi_reg);
1983                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1984                 POSTING_READ(intel_hdmi->hdmi_reg);
1985
1986                 temp &= ~SDVO_ENABLE;
1987                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1988                 POSTING_READ(intel_hdmi->hdmi_reg);
1989
1990                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1991                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1992                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1993         }
1994
1995         intel_dig_port->set_infoframes(encoder,
1996                                        false,
1997                                        old_crtc_state, old_conn_state);
1998
1999         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2000 }
2001
2002 static void g4x_disable_hdmi(struct intel_encoder *encoder,
2003                              const struct intel_crtc_state *old_crtc_state,
2004                              const struct drm_connector_state *old_conn_state)
2005 {
2006         if (old_crtc_state->has_audio)
2007                 intel_audio_codec_disable(encoder,
2008                                           old_crtc_state, old_conn_state);
2009
2010         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
2011 }
2012
2013 static void pch_disable_hdmi(struct intel_encoder *encoder,
2014                              const struct intel_crtc_state *old_crtc_state,
2015                              const struct drm_connector_state *old_conn_state)
2016 {
2017         if (old_crtc_state->has_audio)
2018                 intel_audio_codec_disable(encoder,
2019                                           old_crtc_state, old_conn_state);
2020 }
2021
2022 static void pch_post_disable_hdmi(struct intel_encoder *encoder,
2023                                   const struct intel_crtc_state *old_crtc_state,
2024                                   const struct drm_connector_state *old_conn_state)
2025 {
2026         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
2027 }
2028
2029 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
2030 {
2031         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2032         const struct ddi_vbt_port_info *info =
2033                 &dev_priv->vbt.ddi_port_info[encoder->port];
2034         int max_tmds_clock;
2035
2036         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2037                 max_tmds_clock = 594000;
2038         else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
2039                 max_tmds_clock = 300000;
2040         else if (INTEL_GEN(dev_priv) >= 5)
2041                 max_tmds_clock = 225000;
2042         else
2043                 max_tmds_clock = 165000;
2044
2045         if (info->max_tmds_clock)
2046                 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
2047
2048         return max_tmds_clock;
2049 }
2050
2051 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
2052                                  bool respect_downstream_limits,
2053                                  bool force_dvi)
2054 {
2055         struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
2056         int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
2057
2058         if (respect_downstream_limits) {
2059                 struct intel_connector *connector = hdmi->attached_connector;
2060                 const struct drm_display_info *info = &connector->base.display_info;
2061
2062                 if (hdmi->dp_dual_mode.max_tmds_clock)
2063                         max_tmds_clock = min(max_tmds_clock,
2064                                              hdmi->dp_dual_mode.max_tmds_clock);
2065
2066                 if (info->max_tmds_clock)
2067                         max_tmds_clock = min(max_tmds_clock,
2068                                              info->max_tmds_clock);
2069                 else if (!hdmi->has_hdmi_sink || force_dvi)
2070                         max_tmds_clock = min(max_tmds_clock, 165000);
2071         }
2072
2073         return max_tmds_clock;
2074 }
2075
2076 static enum drm_mode_status
2077 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
2078                       int clock, bool respect_downstream_limits,
2079                       bool force_dvi)
2080 {
2081         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
2082
2083         if (clock < 25000)
2084                 return MODE_CLOCK_LOW;
2085         if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi))
2086                 return MODE_CLOCK_HIGH;
2087
2088         /* BXT DPLL can't generate 223-240 MHz */
2089         if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
2090                 return MODE_CLOCK_RANGE;
2091
2092         /* CHV DPLL can't generate 216-240 MHz */
2093         if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
2094                 return MODE_CLOCK_RANGE;
2095
2096         return MODE_OK;
2097 }
2098
2099 static enum drm_mode_status
2100 intel_hdmi_mode_valid(struct drm_connector *connector,
2101                       struct drm_display_mode *mode)
2102 {
2103         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
2104         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
2105         struct drm_i915_private *dev_priv = to_i915(dev);
2106         enum drm_mode_status status;
2107         int clock;
2108         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
2109         bool force_dvi =
2110                 READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI;
2111
2112         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
2113                 return MODE_NO_DBLESCAN;
2114
2115         clock = mode->clock;
2116
2117         if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
2118                 clock *= 2;
2119
2120         if (clock > max_dotclk)
2121                 return MODE_CLOCK_HIGH;
2122
2123         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
2124                 clock *= 2;
2125
2126         if (drm_mode_is_420_only(&connector->display_info, mode))
2127                 clock /= 2;
2128
2129         /* check if we can do 8bpc */
2130         status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);
2131
2132         if (hdmi->has_hdmi_sink && !force_dvi) {
2133                 /* if we can't do 8bpc we may still be able to do 12bpc */
2134                 if (status != MODE_OK && !HAS_GMCH(dev_priv))
2135                         status = hdmi_port_clock_valid(hdmi, clock * 3 / 2,
2136                                                        true, force_dvi);
2137
2138                 /* if we can't do 8,12bpc we may still be able to do 10bpc */
2139                 if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11)
2140                         status = hdmi_port_clock_valid(hdmi, clock * 5 / 4,
2141                                                        true, force_dvi);
2142         }
2143
2144         return status;
2145 }
2146
2147 static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
2148                                      int bpc)
2149 {
2150         struct drm_i915_private *dev_priv =
2151                 to_i915(crtc_state->base.crtc->dev);
2152         struct drm_atomic_state *state = crtc_state->base.state;
2153         struct drm_connector_state *connector_state;
2154         struct drm_connector *connector;
2155         const struct drm_display_mode *adjusted_mode =
2156                 &crtc_state->base.adjusted_mode;
2157         int i;
2158
2159         if (HAS_GMCH(dev_priv))
2160                 return false;
2161
2162         if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
2163                 return false;
2164
2165         if (crtc_state->pipe_bpp <= 8*3)
2166                 return false;
2167
2168         if (!crtc_state->has_hdmi_sink)
2169                 return false;
2170
2171         /*
2172          * HDMI deep color affects the clocks, so it's only possible
2173          * when not cloning with other encoder types.
2174          */
2175         if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
2176                 return false;
2177
2178         for_each_new_connector_in_state(state, connector, connector_state, i) {
2179                 const struct drm_display_info *info = &connector->display_info;
2180
2181                 if (connector_state->crtc != crtc_state->base.crtc)
2182                         continue;
2183
2184                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2185                         const struct drm_hdmi_info *hdmi = &info->hdmi;
2186
2187                         if (bpc == 12 && !(hdmi->y420_dc_modes &
2188                                            DRM_EDID_YCBCR420_DC_36))
2189                                 return false;
2190                         else if (bpc == 10 && !(hdmi->y420_dc_modes &
2191                                                 DRM_EDID_YCBCR420_DC_30))
2192                                 return false;
2193                 } else {
2194                         if (bpc == 12 && !(info->edid_hdmi_dc_modes &
2195                                            DRM_EDID_HDMI_DC_36))
2196                                 return false;
2197                         else if (bpc == 10 && !(info->edid_hdmi_dc_modes &
2198                                                 DRM_EDID_HDMI_DC_30))
2199                                 return false;
2200                 }
2201         }
2202
2203         /* Display WA #1139: glk */
2204         if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
2205             adjusted_mode->htotal > 5460)
2206                 return false;
2207
2208         /* Display Wa_1405510057:icl */
2209         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
2210             bpc == 10 && INTEL_GEN(dev_priv) >= 11 &&
2211             (adjusted_mode->crtc_hblank_end -
2212              adjusted_mode->crtc_hblank_start) % 8 == 2)
2213                 return false;
2214
2215         return true;
2216 }
2217
2218 static bool
2219 intel_hdmi_ycbcr420_config(struct drm_connector *connector,
2220                            struct intel_crtc_state *config,
2221                            int *clock_12bpc, int *clock_10bpc,
2222                            int *clock_8bpc)
2223 {
2224         struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
2225
2226         if (!connector->ycbcr_420_allowed) {
2227                 DRM_ERROR("Platform doesn't support YCBCR420 output\n");
2228                 return false;
2229         }
2230
2231         /* YCBCR420 TMDS rate requirement is half the pixel clock */
2232         config->port_clock /= 2;
2233         *clock_12bpc /= 2;
2234         *clock_10bpc /= 2;
2235         *clock_8bpc /= 2;
2236         config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2237
2238         /* YCBCR 420 output conversion needs a scaler */
2239         if (skl_update_scaler_crtc(config)) {
2240                 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
2241                 return false;
2242         }
2243
2244         intel_pch_panel_fitting(intel_crtc, config,
2245                                 DRM_MODE_SCALE_FULLSCREEN);
2246
2247         return true;
2248 }
2249
2250 int intel_hdmi_compute_config(struct intel_encoder *encoder,
2251                               struct intel_crtc_state *pipe_config,
2252                               struct drm_connector_state *conn_state)
2253 {
2254         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2255         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2256         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2257         struct drm_connector *connector = conn_state->connector;
2258         struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
2259         struct intel_digital_connector_state *intel_conn_state =
2260                 to_intel_digital_connector_state(conn_state);
2261         int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
2262         int clock_10bpc = clock_8bpc * 5 / 4;
2263         int clock_12bpc = clock_8bpc * 3 / 2;
2264         int desired_bpp;
2265         bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
2266
2267         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2268                 return -EINVAL;
2269
2270         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2271         pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink;
2272
2273         if (pipe_config->has_hdmi_sink)
2274                 pipe_config->has_infoframe = true;
2275
2276         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2277                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
2278                 pipe_config->limited_color_range =
2279                         pipe_config->has_hdmi_sink &&
2280                         drm_default_rgb_quant_range(adjusted_mode) ==
2281                         HDMI_QUANTIZATION_RANGE_LIMITED;
2282         } else {
2283                 pipe_config->limited_color_range =
2284                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2285         }
2286
2287         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
2288                 pipe_config->pixel_multiplier = 2;
2289                 clock_8bpc *= 2;
2290                 clock_10bpc *= 2;
2291                 clock_12bpc *= 2;
2292         }
2293
2294         if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
2295                 if (!intel_hdmi_ycbcr420_config(connector, pipe_config,
2296                                                 &clock_12bpc, &clock_10bpc,
2297                                                 &clock_8bpc)) {
2298                         DRM_ERROR("Can't support YCBCR420 output\n");
2299                         return -EINVAL;
2300                 }
2301         }
2302
2303         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
2304                 pipe_config->has_pch_encoder = true;
2305
2306         if (pipe_config->has_hdmi_sink) {
2307                 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2308                         pipe_config->has_audio = intel_hdmi->has_audio;
2309                 else
2310                         pipe_config->has_audio =
2311                                 intel_conn_state->force_audio == HDMI_AUDIO_ON;
2312         }
2313
2314         /*
2315          * Note that g4x/vlv don't support 12bpc hdmi outputs. We also need
2316          * to check that the higher clock still fits within limits.
2317          */
2318         if (hdmi_deep_color_possible(pipe_config, 12) &&
2319             hdmi_port_clock_valid(intel_hdmi, clock_12bpc,
2320                                   true, force_dvi) == MODE_OK) {
2321                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
2322                 desired_bpp = 12*3;
2323
2324                 /* Need to adjust the port link by 1.5x for 12bpc. */
2325                 pipe_config->port_clock = clock_12bpc;
2326         } else if (hdmi_deep_color_possible(pipe_config, 10) &&
2327                    hdmi_port_clock_valid(intel_hdmi, clock_10bpc,
2328                                          true, force_dvi) == MODE_OK) {
2329                 DRM_DEBUG_KMS("picking bpc to 10 for HDMI output\n");
2330                 desired_bpp = 10 * 3;
2331
2332                 /* Need to adjust the port link by 1.25x for 10bpc. */
2333                 pipe_config->port_clock = clock_10bpc;
2334         } else {
2335                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
2336                 desired_bpp = 8*3;
2337
2338                 pipe_config->port_clock = clock_8bpc;
2339         }
2340
2341         if (!pipe_config->bw_constrained) {
2342                 DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp);
2343                 pipe_config->pipe_bpp = desired_bpp;
2344         }
2345
2346         if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
2347                                   false, force_dvi) != MODE_OK) {
2348                 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
2349                 return -EINVAL;
2350         }
2351
2352         /* Set user selected PAR to incoming mode's member */
2353         adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
2354
2355         pipe_config->lane_count = 4;
2356
2357         if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
2358                                            IS_GEMINILAKE(dev_priv))) {
2359                 if (scdc->scrambling.low_rates)
2360                         pipe_config->hdmi_scrambling = true;
2361
2362                 if (pipe_config->port_clock > 340000) {
2363                         pipe_config->hdmi_scrambling = true;
2364                         pipe_config->hdmi_high_tmds_clock_ratio = true;
2365                 }
2366         }
2367
2368         intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, conn_state);
2369
2370         if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
2371                 DRM_DEBUG_KMS("bad AVI infoframe\n");
2372                 return -EINVAL;
2373         }
2374
2375         if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
2376                 DRM_DEBUG_KMS("bad SPD infoframe\n");
2377                 return -EINVAL;
2378         }
2379
2380         if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
2381                 DRM_DEBUG_KMS("bad HDMI infoframe\n");
2382                 return -EINVAL;
2383         }
2384
2385         return 0;
2386 }
2387
2388 static void
2389 intel_hdmi_unset_edid(struct drm_connector *connector)
2390 {
2391         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2392
2393         intel_hdmi->has_hdmi_sink = false;
2394         intel_hdmi->has_audio = false;
2395
2396         intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
2397         intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
2398
2399         kfree(to_intel_connector(connector)->detect_edid);
2400         to_intel_connector(connector)->detect_edid = NULL;
2401 }
2402
2403 static void
2404 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
2405 {
2406         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2407         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
2408         enum port port = hdmi_to_dig_port(hdmi)->base.port;
2409         struct i2c_adapter *adapter =
2410                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
2411         enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
2412
2413         /*
2414          * Type 1 DVI adaptors are not required to implement any
2415          * registers, so we can't always detect their presence.
2416          * Ideally we should be able to check the state of the
2417          * CONFIG1 pin, but no such luck on our hardware.
2418          *
2419          * The only method left to us is to check the VBT to see
2420          * if the port is a dual mode capable DP port. But let's
2421          * only do that when we sucesfully read the EDID, to avoid
2422          * confusing log messages about DP dual mode adaptors when
2423          * there's nothing connected to the port.
2424          */
2425         if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
2426                 /* An overridden EDID imply that we want this port for testing.
2427                  * Make sure not to set limits for that port.
2428                  */
2429                 if (has_edid && !connector->override_edid &&
2430                     intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2431                         DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
2432                         type = DRM_DP_DUAL_MODE_TYPE1_DVI;
2433                 } else {
2434                         type = DRM_DP_DUAL_MODE_NONE;
2435                 }
2436         }
2437
2438         if (type == DRM_DP_DUAL_MODE_NONE)
2439                 return;
2440
2441         hdmi->dp_dual_mode.type = type;
2442         hdmi->dp_dual_mode.max_tmds_clock =
2443                 drm_dp_dual_mode_max_tmds_clock(type, adapter);
2444
2445         DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2446                       drm_dp_get_dual_mode_type_name(type),
2447                       hdmi->dp_dual_mode.max_tmds_clock);
2448 }
2449
2450 static bool
2451 intel_hdmi_set_edid(struct drm_connector *connector)
2452 {
2453         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2454         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2455         intel_wakeref_t wakeref;
2456         struct edid *edid;
2457         bool connected = false;
2458         struct i2c_adapter *i2c;
2459
2460         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2461
2462         i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2463
2464         edid = drm_get_edid(connector, i2c);
2465
2466         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
2467                 DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2468                 intel_gmbus_force_bit(i2c, true);
2469                 edid = drm_get_edid(connector, i2c);
2470                 intel_gmbus_force_bit(i2c, false);
2471         }
2472
2473         intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
2474
2475         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2476
2477         to_intel_connector(connector)->detect_edid = edid;
2478         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
2479                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
2480                 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
2481
2482                 connected = true;
2483         }
2484
2485         cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
2486
2487         return connected;
2488 }
2489
2490 static enum drm_connector_status
2491 intel_hdmi_detect(struct drm_connector *connector, bool force)
2492 {
2493         enum drm_connector_status status = connector_status_disconnected;
2494         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2495         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2496         struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2497         intel_wakeref_t wakeref;
2498
2499         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2500                       connector->base.id, connector->name);
2501
2502         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2503
2504         if (INTEL_GEN(dev_priv) >= 11 &&
2505             !intel_digital_port_connected(encoder))
2506                 goto out;
2507
2508         intel_hdmi_unset_edid(connector);
2509
2510         if (intel_hdmi_set_edid(connector))
2511                 status = connector_status_connected;
2512
2513 out:
2514         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2515
2516         if (status != connector_status_connected)
2517                 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
2518
2519         return status;
2520 }
2521
2522 static void
2523 intel_hdmi_force(struct drm_connector *connector)
2524 {
2525         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2526                       connector->base.id, connector->name);
2527
2528         intel_hdmi_unset_edid(connector);
2529
2530         if (connector->status != connector_status_connected)
2531                 return;
2532
2533         intel_hdmi_set_edid(connector);
2534 }
2535
2536 static int intel_hdmi_get_modes(struct drm_connector *connector)
2537 {
2538         struct edid *edid;
2539
2540         edid = to_intel_connector(connector)->detect_edid;
2541         if (edid == NULL)
2542                 return 0;
2543
2544         return intel_connector_update_modes(connector, edid);
2545 }
2546
2547 static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
2548                                   const struct intel_crtc_state *pipe_config,
2549                                   const struct drm_connector_state *conn_state)
2550 {
2551         struct intel_digital_port *intel_dig_port =
2552                 enc_to_dig_port(&encoder->base);
2553
2554         intel_hdmi_prepare(encoder, pipe_config);
2555
2556         intel_dig_port->set_infoframes(encoder,
2557                                        pipe_config->has_infoframe,
2558                                        pipe_config, conn_state);
2559 }
2560
2561 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
2562                                 const struct intel_crtc_state *pipe_config,
2563                                 const struct drm_connector_state *conn_state)
2564 {
2565         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2566         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2567
2568         vlv_phy_pre_encoder_enable(encoder, pipe_config);
2569
2570         /* HDMI 1.0V-2dB */
2571         vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
2572                                  0x2b247878);
2573
2574         dport->set_infoframes(encoder,
2575                               pipe_config->has_infoframe,
2576                               pipe_config, conn_state);
2577
2578         g4x_enable_hdmi(encoder, pipe_config, conn_state);
2579
2580         vlv_wait_port_ready(dev_priv, dport, 0x0);
2581 }
2582
2583 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2584                                     const struct intel_crtc_state *pipe_config,
2585                                     const struct drm_connector_state *conn_state)
2586 {
2587         intel_hdmi_prepare(encoder, pipe_config);
2588
2589         vlv_phy_pre_pll_enable(encoder, pipe_config);
2590 }
2591
2592 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2593                                     const struct intel_crtc_state *pipe_config,
2594                                     const struct drm_connector_state *conn_state)
2595 {
2596         intel_hdmi_prepare(encoder, pipe_config);
2597
2598         chv_phy_pre_pll_enable(encoder, pipe_config);
2599 }
2600
2601 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
2602                                       const struct intel_crtc_state *old_crtc_state,
2603                                       const struct drm_connector_state *old_conn_state)
2604 {
2605         chv_phy_post_pll_disable(encoder, old_crtc_state);
2606 }
2607
2608 static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
2609                                   const struct intel_crtc_state *old_crtc_state,
2610                                   const struct drm_connector_state *old_conn_state)
2611 {
2612         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
2613         vlv_phy_reset_lanes(encoder, old_crtc_state);
2614 }
2615
2616 static void chv_hdmi_post_disable(struct intel_encoder *encoder,
2617                                   const struct intel_crtc_state *old_crtc_state,
2618                                   const struct drm_connector_state *old_conn_state)
2619 {
2620         struct drm_device *dev = encoder->base.dev;
2621         struct drm_i915_private *dev_priv = to_i915(dev);
2622
2623         mutex_lock(&dev_priv->sb_lock);
2624
2625         /* Assert data lane reset */
2626         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2627
2628         mutex_unlock(&dev_priv->sb_lock);
2629 }
2630
2631 static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
2632                                 const struct intel_crtc_state *pipe_config,
2633                                 const struct drm_connector_state *conn_state)
2634 {
2635         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2636         struct drm_device *dev = encoder->base.dev;
2637         struct drm_i915_private *dev_priv = to_i915(dev);
2638
2639         chv_phy_pre_encoder_enable(encoder, pipe_config);
2640
2641         /* FIXME: Program the support xxx V-dB */
2642         /* Use 800mV-0dB */
2643         chv_set_phy_signal_level(encoder, 128, 102, false);
2644
2645         dport->set_infoframes(encoder,
2646                               pipe_config->has_infoframe,
2647                               pipe_config, conn_state);
2648
2649         g4x_enable_hdmi(encoder, pipe_config, conn_state);
2650
2651         vlv_wait_port_ready(dev_priv, dport, 0x0);
2652
2653         /* Second common lane will stay alive on its own now */
2654         chv_phy_release_cl2_override(encoder);
2655 }
2656
2657 static int
2658 intel_hdmi_connector_register(struct drm_connector *connector)
2659 {
2660         int ret;
2661
2662         ret = intel_connector_register(connector);
2663         if (ret)
2664                 return ret;
2665
2666         i915_debugfs_connector_add(connector);
2667
2668         return ret;
2669 }
2670
2671 static void intel_hdmi_destroy(struct drm_connector *connector)
2672 {
2673         if (intel_attached_hdmi(connector)->cec_notifier)
2674                 cec_notifier_put(intel_attached_hdmi(connector)->cec_notifier);
2675
2676         intel_connector_destroy(connector);
2677 }
2678
2679 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2680         .detect = intel_hdmi_detect,
2681         .force = intel_hdmi_force,
2682         .fill_modes = drm_helper_probe_single_connector_modes,
2683         .atomic_get_property = intel_digital_connector_atomic_get_property,
2684         .atomic_set_property = intel_digital_connector_atomic_set_property,
2685         .late_register = intel_hdmi_connector_register,
2686         .early_unregister = intel_connector_unregister,
2687         .destroy = intel_hdmi_destroy,
2688         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2689         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2690 };
2691
2692 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2693         .get_modes = intel_hdmi_get_modes,
2694         .mode_valid = intel_hdmi_mode_valid,
2695         .atomic_check = intel_digital_connector_atomic_check,
2696 };
2697
2698 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
2699         .destroy = intel_encoder_destroy,
2700 };
2701
2702 static void
2703 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2704 {
2705         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2706         struct intel_digital_port *intel_dig_port =
2707                                 hdmi_to_dig_port(intel_hdmi);
2708
2709         intel_attach_force_audio_property(connector);
2710         intel_attach_broadcast_rgb_property(connector);
2711         intel_attach_aspect_ratio_property(connector);
2712
2713         /*
2714          * Attach Colorspace property for Non LSPCON based device
2715          * ToDo: This needs to be extended for LSPCON implementation
2716          * as well. Will be implemented separately.
2717          */
2718         if (!intel_dig_port->lspcon.active)
2719                 intel_attach_colorspace_property(connector);
2720
2721         drm_connector_attach_content_type_property(connector);
2722         connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2723
2724         if (!HAS_GMCH(dev_priv))
2725                 drm_connector_attach_max_bpc_property(connector, 8, 12);
2726 }
2727
2728 /*
2729  * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2730  * @encoder: intel_encoder
2731  * @connector: drm_connector
2732  * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2733  *  or reset the high tmds clock ratio for scrambling
2734  * @scrambling: bool to Indicate if the function needs to set or reset
2735  *  sink scrambling
2736  *
2737  * This function handles scrambling on HDMI 2.0 capable sinks.
2738  * If required clock rate is > 340 Mhz && scrambling is supported by sink
2739  * it enables scrambling. This should be called before enabling the HDMI
2740  * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2741  * detect a scrambled clock within 100 ms.
2742  *
2743  * Returns:
2744  * True on success, false on failure.
2745  */
2746 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2747                                        struct drm_connector *connector,
2748                                        bool high_tmds_clock_ratio,
2749                                        bool scrambling)
2750 {
2751         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2752         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2753         struct drm_scrambling *sink_scrambling =
2754                 &connector->display_info.hdmi.scdc.scrambling;
2755         struct i2c_adapter *adapter =
2756                 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2757
2758         if (!sink_scrambling->supported)
2759                 return true;
2760
2761         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2762                       connector->base.id, connector->name,
2763                       yesno(scrambling), high_tmds_clock_ratio ? 40 : 10);
2764
2765         /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2766         return drm_scdc_set_high_tmds_clock_ratio(adapter,
2767                                                   high_tmds_clock_ratio) &&
2768                 drm_scdc_set_scrambling(adapter, scrambling);
2769 }
2770
2771 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2772 {
2773         u8 ddc_pin;
2774
2775         switch (port) {
2776         case PORT_B:
2777                 ddc_pin = GMBUS_PIN_DPB;
2778                 break;
2779         case PORT_C:
2780                 ddc_pin = GMBUS_PIN_DPC;
2781                 break;
2782         case PORT_D:
2783                 ddc_pin = GMBUS_PIN_DPD_CHV;
2784                 break;
2785         default:
2786                 MISSING_CASE(port);
2787                 ddc_pin = GMBUS_PIN_DPB;
2788                 break;
2789         }
2790         return ddc_pin;
2791 }
2792
2793 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2794 {
2795         u8 ddc_pin;
2796
2797         switch (port) {
2798         case PORT_B:
2799                 ddc_pin = GMBUS_PIN_1_BXT;
2800                 break;
2801         case PORT_C:
2802                 ddc_pin = GMBUS_PIN_2_BXT;
2803                 break;
2804         default:
2805                 MISSING_CASE(port);
2806                 ddc_pin = GMBUS_PIN_1_BXT;
2807                 break;
2808         }
2809         return ddc_pin;
2810 }
2811
2812 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2813                               enum port port)
2814 {
2815         u8 ddc_pin;
2816
2817         switch (port) {
2818         case PORT_B:
2819                 ddc_pin = GMBUS_PIN_1_BXT;
2820                 break;
2821         case PORT_C:
2822                 ddc_pin = GMBUS_PIN_2_BXT;
2823                 break;
2824         case PORT_D:
2825                 ddc_pin = GMBUS_PIN_4_CNP;
2826                 break;
2827         case PORT_F:
2828                 ddc_pin = GMBUS_PIN_3_BXT;
2829                 break;
2830         default:
2831                 MISSING_CASE(port);
2832                 ddc_pin = GMBUS_PIN_1_BXT;
2833                 break;
2834         }
2835         return ddc_pin;
2836 }
2837
2838 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2839 {
2840         u8 ddc_pin;
2841
2842         switch (port) {
2843         case PORT_A:
2844                 ddc_pin = GMBUS_PIN_1_BXT;
2845                 break;
2846         case PORT_B:
2847                 ddc_pin = GMBUS_PIN_2_BXT;
2848                 break;
2849         case PORT_C:
2850                 ddc_pin = GMBUS_PIN_9_TC1_ICP;
2851                 break;
2852         case PORT_D:
2853                 ddc_pin = GMBUS_PIN_10_TC2_ICP;
2854                 break;
2855         case PORT_E:
2856                 ddc_pin = GMBUS_PIN_11_TC3_ICP;
2857                 break;
2858         case PORT_F:
2859                 ddc_pin = GMBUS_PIN_12_TC4_ICP;
2860                 break;
2861         default:
2862                 MISSING_CASE(port);
2863                 ddc_pin = GMBUS_PIN_2_BXT;
2864                 break;
2865         }
2866         return ddc_pin;
2867 }
2868
2869 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2870                               enum port port)
2871 {
2872         u8 ddc_pin;
2873
2874         switch (port) {
2875         case PORT_B:
2876                 ddc_pin = GMBUS_PIN_DPB;
2877                 break;
2878         case PORT_C:
2879                 ddc_pin = GMBUS_PIN_DPC;
2880                 break;
2881         case PORT_D:
2882                 ddc_pin = GMBUS_PIN_DPD;
2883                 break;
2884         default:
2885                 MISSING_CASE(port);
2886                 ddc_pin = GMBUS_PIN_DPB;
2887                 break;
2888         }
2889         return ddc_pin;
2890 }
2891
2892 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
2893                              enum port port)
2894 {
2895         const struct ddi_vbt_port_info *info =
2896                 &dev_priv->vbt.ddi_port_info[port];
2897         u8 ddc_pin;
2898
2899         if (info->alternate_ddc_pin) {
2900                 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
2901                               info->alternate_ddc_pin, port_name(port));
2902                 return info->alternate_ddc_pin;
2903         }
2904
2905         if (HAS_PCH_ICP(dev_priv))
2906                 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
2907         else if (HAS_PCH_CNP(dev_priv))
2908                 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
2909         else if (IS_GEN9_LP(dev_priv))
2910                 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
2911         else if (IS_CHERRYVIEW(dev_priv))
2912                 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
2913         else
2914                 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
2915
2916         DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
2917                       ddc_pin, port_name(port));
2918
2919         return ddc_pin;
2920 }
2921
2922 void intel_infoframe_init(struct intel_digital_port *intel_dig_port)
2923 {
2924         struct drm_i915_private *dev_priv =
2925                 to_i915(intel_dig_port->base.base.dev);
2926
2927         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2928                 intel_dig_port->write_infoframe = vlv_write_infoframe;
2929                 intel_dig_port->read_infoframe = vlv_read_infoframe;
2930                 intel_dig_port->set_infoframes = vlv_set_infoframes;
2931                 intel_dig_port->infoframes_enabled = vlv_infoframes_enabled;
2932         } else if (IS_G4X(dev_priv)) {
2933                 intel_dig_port->write_infoframe = g4x_write_infoframe;
2934                 intel_dig_port->read_infoframe = g4x_read_infoframe;
2935                 intel_dig_port->set_infoframes = g4x_set_infoframes;
2936                 intel_dig_port->infoframes_enabled = g4x_infoframes_enabled;
2937         } else if (HAS_DDI(dev_priv)) {
2938                 if (intel_dig_port->lspcon.active) {
2939                         intel_dig_port->write_infoframe = lspcon_write_infoframe;
2940                         intel_dig_port->read_infoframe = lspcon_read_infoframe;
2941                         intel_dig_port->set_infoframes = lspcon_set_infoframes;
2942                         intel_dig_port->infoframes_enabled = lspcon_infoframes_enabled;
2943                 } else {
2944                         intel_dig_port->write_infoframe = hsw_write_infoframe;
2945                         intel_dig_port->read_infoframe = hsw_read_infoframe;
2946                         intel_dig_port->set_infoframes = hsw_set_infoframes;
2947                         intel_dig_port->infoframes_enabled = hsw_infoframes_enabled;
2948                 }
2949         } else if (HAS_PCH_IBX(dev_priv)) {
2950                 intel_dig_port->write_infoframe = ibx_write_infoframe;
2951                 intel_dig_port->read_infoframe = ibx_read_infoframe;
2952                 intel_dig_port->set_infoframes = ibx_set_infoframes;
2953                 intel_dig_port->infoframes_enabled = ibx_infoframes_enabled;
2954         } else {
2955                 intel_dig_port->write_infoframe = cpt_write_infoframe;
2956                 intel_dig_port->read_infoframe = cpt_read_infoframe;
2957                 intel_dig_port->set_infoframes = cpt_set_infoframes;
2958                 intel_dig_port->infoframes_enabled = cpt_infoframes_enabled;
2959         }
2960 }
2961
2962 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
2963                                struct intel_connector *intel_connector)
2964 {
2965         struct drm_connector *connector = &intel_connector->base;
2966         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2967         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2968         struct drm_device *dev = intel_encoder->base.dev;
2969         struct drm_i915_private *dev_priv = to_i915(dev);
2970         enum port port = intel_encoder->port;
2971
2972         DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
2973                       port_name(port));
2974
2975         if (WARN(intel_dig_port->max_lanes < 4,
2976                  "Not enough lanes (%d) for HDMI on port %c\n",
2977                  intel_dig_port->max_lanes, port_name(port)))
2978                 return;
2979
2980         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
2981                            DRM_MODE_CONNECTOR_HDMIA);
2982         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2983
2984         connector->interlace_allowed = 1;
2985         connector->doublescan_allowed = 0;
2986         connector->stereo_allowed = 1;
2987
2988         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2989                 connector->ycbcr_420_allowed = true;
2990
2991         intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
2992
2993         if (WARN_ON(port == PORT_A))
2994                 return;
2995         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
2996
2997         if (HAS_DDI(dev_priv))
2998                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2999         else
3000                 intel_connector->get_hw_state = intel_connector_get_hw_state;
3001
3002         intel_hdmi_add_properties(intel_hdmi, connector);
3003
3004         intel_connector_attach_encoder(intel_connector, intel_encoder);
3005         intel_hdmi->attached_connector = intel_connector;
3006
3007         if (is_hdcp_supported(dev_priv, port)) {
3008                 int ret = intel_hdcp_init(intel_connector,
3009                                           &intel_hdmi_hdcp_shim);
3010                 if (ret)
3011                         DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
3012         }
3013
3014         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3015          * 0xd.  Failure to do so will result in spurious interrupts being
3016          * generated on the port when a cable is not attached.
3017          */
3018         if (IS_G45(dev_priv)) {
3019                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3020                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3021         }
3022
3023         intel_hdmi->cec_notifier = cec_notifier_get_conn(dev->dev,
3024                                                          port_identifier(port));
3025         if (!intel_hdmi->cec_notifier)
3026                 DRM_DEBUG_KMS("CEC notifier get failed\n");
3027 }
3028
3029 void intel_hdmi_init(struct drm_i915_private *dev_priv,
3030                      i915_reg_t hdmi_reg, enum port port)
3031 {
3032         struct intel_digital_port *intel_dig_port;
3033         struct intel_encoder *intel_encoder;
3034         struct intel_connector *intel_connector;
3035
3036         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3037         if (!intel_dig_port)
3038                 return;
3039
3040         intel_connector = intel_connector_alloc();
3041         if (!intel_connector) {
3042                 kfree(intel_dig_port);
3043                 return;
3044         }
3045
3046         intel_encoder = &intel_dig_port->base;
3047
3048         drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
3049                          &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
3050                          "HDMI %c", port_name(port));
3051
3052         intel_encoder->hotplug = intel_encoder_hotplug;
3053         intel_encoder->compute_config = intel_hdmi_compute_config;
3054         if (HAS_PCH_SPLIT(dev_priv)) {
3055                 intel_encoder->disable = pch_disable_hdmi;
3056                 intel_encoder->post_disable = pch_post_disable_hdmi;
3057         } else {
3058                 intel_encoder->disable = g4x_disable_hdmi;
3059         }
3060         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
3061         intel_encoder->get_config = intel_hdmi_get_config;
3062         if (IS_CHERRYVIEW(dev_priv)) {
3063                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
3064                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
3065                 intel_encoder->enable = vlv_enable_hdmi;
3066                 intel_encoder->post_disable = chv_hdmi_post_disable;
3067                 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
3068         } else if (IS_VALLEYVIEW(dev_priv)) {
3069                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
3070                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
3071                 intel_encoder->enable = vlv_enable_hdmi;
3072                 intel_encoder->post_disable = vlv_hdmi_post_disable;
3073         } else {
3074                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
3075                 if (HAS_PCH_CPT(dev_priv))
3076                         intel_encoder->enable = cpt_enable_hdmi;
3077                 else if (HAS_PCH_IBX(dev_priv))
3078                         intel_encoder->enable = ibx_enable_hdmi;
3079                 else
3080                         intel_encoder->enable = g4x_enable_hdmi;
3081         }
3082
3083         intel_encoder->type = INTEL_OUTPUT_HDMI;
3084         intel_encoder->power_domain = intel_port_to_power_domain(port);
3085         intel_encoder->port = port;
3086         if (IS_CHERRYVIEW(dev_priv)) {
3087                 if (port == PORT_D)
3088                         intel_encoder->crtc_mask = 1 << 2;
3089                 else
3090                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
3091         } else {
3092                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3093         }
3094         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
3095         /*
3096          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
3097          * to work on real hardware. And since g4x can send infoframes to
3098          * only one port anyway, nothing is lost by allowing it.
3099          */
3100         if (IS_G4X(dev_priv))
3101                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
3102
3103         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
3104         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
3105         intel_dig_port->max_lanes = 4;
3106
3107         intel_infoframe_init(intel_dig_port);
3108
3109         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
3110         intel_hdmi_init_connector(intel_dig_port, intel_connector);
3111 }