drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/delay.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/i2c.h>
  32 #include <linux/slab.h>
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_edid.h>
  37 #include <drm/drm_hdcp.h>
  38 #include <drm/drm_scdc_helper.h>
  39 #include <drm/i915_drm.h>
  40 #include <drm/intel_lpe_audio.h>
  41
  42 #include "i915_debugfs.h"
  43 #include "i915_drv.h"
  44 #include "intel_atomic.h"
  45 #include "intel_audio.h"
  46 #include "intel_connector.h"
  47 #include "intel_ddi.h"
  48 #include "intel_dp.h"
  49 #include "intel_dpio_phy.h"
  50 #include "intel_drv.h"
  51 #include "intel_fifo_underrun.h"
  52 #include "intel_gmbus.h"
  53 #include "intel_hdcp.h"
  54 #include "intel_hdmi.h"
  55 #include "intel_hotplug.h"
  56 #include "intel_lspcon.h"
  57 #include "intel_sdvo.h"
  58 #include "intel_panel.h"
  59 #include "intel_sideband.h"
  60
  61 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  62 {
  63         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  64 }
  65
  66 static void
  67 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  68 {
  69         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  70         struct drm_i915_private *dev_priv = to_i915(dev);
  71         u32 enabled_bits;
  72
  73         enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  74
  75         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  76              "HDMI port enabled, expecting disabled\n");
  77 }
  78
  79 static void
  80 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
  81                                      enum transcoder cpu_transcoder)
  82 {
  83         WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
  84              TRANS_DDI_FUNC_ENABLE,
  85              "HDMI transcoder function enabled, expecting disabled\n");
  86 }
  87
  88 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  89 {
  90         struct intel_digital_port *intel_dig_port =
  91                 container_of(encoder, struct intel_digital_port, base.base);
  92         return &intel_dig_port->hdmi;
  93 }
  94
  95 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  96 {
  97         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  98 }
  99
 100 static u32 g4x_infoframe_index(unsigned int type)
 101 {
 102         switch (type) {
 103         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 104                 return VIDEO_DIP_SELECT_GAMUT;
 105         case HDMI_INFOFRAME_TYPE_AVI:
 106                 return VIDEO_DIP_SELECT_AVI;
 107         case HDMI_INFOFRAME_TYPE_SPD:
 108                 return VIDEO_DIP_SELECT_SPD;
 109         case HDMI_INFOFRAME_TYPE_VENDOR:
 110                 return VIDEO_DIP_SELECT_VENDOR;
 111         default:
 112                 MISSING_CASE(type);
 113                 return 0;
 114         }
 115 }
 116
 117 static u32 g4x_infoframe_enable(unsigned int type)
 118 {
 119         switch (type) {
 120         case HDMI_PACKET_TYPE_GENERAL_CONTROL:
 121                 return VIDEO_DIP_ENABLE_GCP;
 122         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 123                 return VIDEO_DIP_ENABLE_GAMUT;
 124         case DP_SDP_VSC:
 125                 return 0;
 126         case HDMI_INFOFRAME_TYPE_AVI:
 127                 return VIDEO_DIP_ENABLE_AVI;
 128         case HDMI_INFOFRAME_TYPE_SPD:
 129                 return VIDEO_DIP_ENABLE_SPD;
 130         case HDMI_INFOFRAME_TYPE_VENDOR:
 131                 return VIDEO_DIP_ENABLE_VENDOR;
 132         default:
 133                 MISSING_CASE(type);
 134                 return 0;
 135         }
 136 }
 137
 138 static u32 hsw_infoframe_enable(unsigned int type)
 139 {
 140         switch (type) {
 141         case HDMI_PACKET_TYPE_GENERAL_CONTROL:
 142                 return VIDEO_DIP_ENABLE_GCP_HSW;
 143         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 144                 return VIDEO_DIP_ENABLE_GMP_HSW;
 145         case DP_SDP_VSC:
 146                 return VIDEO_DIP_ENABLE_VSC_HSW;
 147         case DP_SDP_PPS:
 148                 return VDIP_ENABLE_PPS;
 149         case HDMI_INFOFRAME_TYPE_AVI:
 150                 return VIDEO_DIP_ENABLE_AVI_HSW;
 151         case HDMI_INFOFRAME_TYPE_SPD:
 152                 return VIDEO_DIP_ENABLE_SPD_HSW;
 153         case HDMI_INFOFRAME_TYPE_VENDOR:
 154                 return VIDEO_DIP_ENABLE_VS_HSW;
 155         default:
 156                 MISSING_CASE(type);
 157                 return 0;
 158         }
 159 }
 160
 161 static i915_reg_t
 162 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 163                  enum transcoder cpu_transcoder,
 164                  unsigned int type,
 165                  int i)
 166 {
 167         switch (type) {
 168         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 169                 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
 170         case DP_SDP_VSC:
 171                 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
 172         case DP_SDP_PPS:
 173                 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
 174         case HDMI_INFOFRAME_TYPE_AVI:
 175                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
 176         case HDMI_INFOFRAME_TYPE_SPD:
 177                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
 178         case HDMI_INFOFRAME_TYPE_VENDOR:
 179                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
 180         default:
 181                 MISSING_CASE(type);
 182                 return INVALID_MMIO_REG;
 183         }
 184 }
 185
 186 static int hsw_dip_data_size(unsigned int type)
 187 {
 188         switch (type) {
 189         case DP_SDP_VSC:
 190                 return VIDEO_DIP_VSC_DATA_SIZE;
 191         case DP_SDP_PPS:
 192                 return VIDEO_DIP_PPS_DATA_SIZE;
 193         default:
 194                 return VIDEO_DIP_DATA_SIZE;
 195         }
 196 }
 197
 198 static void g4x_write_infoframe(struct intel_encoder *encoder,
 199                                 const struct intel_crtc_state *crtc_state,
 200                                 unsigned int type,
 201                                 const void *frame, ssize_t len)
 202 {
 203         const u32 *data = frame;
 204         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 205         u32 val = I915_READ(VIDEO_DIP_CTL);
 206         int i;
 207
 208         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 209
 210         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 211         val |= g4x_infoframe_index(type);
 212
 213         val &= ~g4x_infoframe_enable(type);
 214
 215         I915_WRITE(VIDEO_DIP_CTL, val);
 216
 217         mmiowb();
 218         for (i = 0; i < len; i += 4) {
 219                 I915_WRITE(VIDEO_DIP_DATA, *data);
 220                 data++;
 221         }
 222         /* Write every possible data byte to force correct ECC calculation. */
 223         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 224                 I915_WRITE(VIDEO_DIP_DATA, 0);
 225         mmiowb();
 226
 227         val |= g4x_infoframe_enable(type);
 228         val &= ~VIDEO_DIP_FREQ_MASK;
 229         val |= VIDEO_DIP_FREQ_VSYNC;
 230
 231         I915_WRITE(VIDEO_DIP_CTL, val);
 232         POSTING_READ(VIDEO_DIP_CTL);
 233 }
 234
 235 static void g4x_read_infoframe(struct intel_encoder *encoder,
 236                                const struct intel_crtc_state *crtc_state,
 237                                unsigned int type,
 238                                void *frame, ssize_t len)
 239 {
 240         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 241         u32 val, *data = frame;
 242         int i;
 243
 244         val = I915_READ(VIDEO_DIP_CTL);
 245
 246         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 247         val |= g4x_infoframe_index(type);
 248
 249         I915_WRITE(VIDEO_DIP_CTL, val);
 250
 251         for (i = 0; i < len; i += 4)
 252                 *data++ = I915_READ(VIDEO_DIP_DATA);
 253 }
 254
 255 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
 256                                   const struct intel_crtc_state *pipe_config)
 257 {
 258         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 259         u32 val = I915_READ(VIDEO_DIP_CTL);
 260
 261         if ((val & VIDEO_DIP_ENABLE) == 0)
 262                 return 0;
 263
 264         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 265                 return 0;
 266
 267         return val & (VIDEO_DIP_ENABLE_AVI |
 268                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 269 }
 270
 271 static void ibx_write_infoframe(struct intel_encoder *encoder,
 272                                 const struct intel_crtc_state *crtc_state,
 273                                 unsigned int type,
 274                                 const void *frame, ssize_t len)
 275 {
 276         const u32 *data = frame;
 277         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 278         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 279         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 280         u32 val = I915_READ(reg);
 281         int i;
 282
 283         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 284
 285         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 286         val |= g4x_infoframe_index(type);
 287
 288         val &= ~g4x_infoframe_enable(type);
 289
 290         I915_WRITE(reg, val);
 291
 292         mmiowb();
 293         for (i = 0; i < len; i += 4) {
 294                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 295                 data++;
 296         }
 297         /* Write every possible data byte to force correct ECC calculation. */
 298         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 299                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 300         mmiowb();
 301
 302         val |= g4x_infoframe_enable(type);
 303         val &= ~VIDEO_DIP_FREQ_MASK;
 304         val |= VIDEO_DIP_FREQ_VSYNC;
 305
 306         I915_WRITE(reg, val);
 307         POSTING_READ(reg);
 308 }
 309
 310 static void ibx_read_infoframe(struct intel_encoder *encoder,
 311                                const struct intel_crtc_state *crtc_state,
 312                                unsigned int type,
 313                                void *frame, ssize_t len)
 314 {
 315         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 316         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 317         u32 val, *data = frame;
 318         int i;
 319
 320         val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe));
 321
 322         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 323         val |= g4x_infoframe_index(type);
 324
 325         I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val);
 326
 327         for (i = 0; i < len; i += 4)
 328                 *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe));
 329 }
 330
 331 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
 332                                   const struct intel_crtc_state *pipe_config)
 333 {
 334         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 335         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 336         i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
 337         u32 val = I915_READ(reg);
 338
 339         if ((val & VIDEO_DIP_ENABLE) == 0)
 340                 return 0;
 341
 342         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 343                 return 0;
 344
 345         return val & (VIDEO_DIP_ENABLE_AVI |
 346                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 347                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 348 }
 349
 350 static void cpt_write_infoframe(struct intel_encoder *encoder,
 351                                 const struct intel_crtc_state *crtc_state,
 352                                 unsigned int type,
 353                                 const void *frame, ssize_t len)
 354 {
 355         const u32 *data = frame;
 356         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 357         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 358         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 359         u32 val = I915_READ(reg);
 360         int i;
 361
 362         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 363
 364         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 365         val |= g4x_infoframe_index(type);
 366
 367         /* The DIP control register spec says that we need to update the AVI
 368          * infoframe without clearing its enable bit */
 369         if (type != HDMI_INFOFRAME_TYPE_AVI)
 370                 val &= ~g4x_infoframe_enable(type);
 371
 372         I915_WRITE(reg, val);
 373
 374         mmiowb();
 375         for (i = 0; i < len; i += 4) {
 376                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 377                 data++;
 378         }
 379         /* Write every possible data byte to force correct ECC calculation. */
 380         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 381                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 382         mmiowb();
 383
 384         val |= g4x_infoframe_enable(type);
 385         val &= ~VIDEO_DIP_FREQ_MASK;
 386         val |= VIDEO_DIP_FREQ_VSYNC;
 387
 388         I915_WRITE(reg, val);
 389         POSTING_READ(reg);
 390 }
 391
 392 static void cpt_read_infoframe(struct intel_encoder *encoder,
 393                                const struct intel_crtc_state *crtc_state,
 394                                unsigned int type,
 395                                void *frame, ssize_t len)
 396 {
 397         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 398         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 399         u32 val, *data = frame;
 400         int i;
 401
 402         val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe));
 403
 404         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 405         val |= g4x_infoframe_index(type);
 406
 407         I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val);
 408
 409         for (i = 0; i < len; i += 4)
 410                 *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe));
 411 }
 412
 413 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
 414                                   const struct intel_crtc_state *pipe_config)
 415 {
 416         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 417         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 418         u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
 419
 420         if ((val & VIDEO_DIP_ENABLE) == 0)
 421                 return 0;
 422
 423         return val & (VIDEO_DIP_ENABLE_AVI |
 424                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 425                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 426 }
 427
 428 static void vlv_write_infoframe(struct intel_encoder *encoder,
 429                                 const struct intel_crtc_state *crtc_state,
 430                                 unsigned int type,
 431                                 const void *frame, ssize_t len)
 432 {
 433         const u32 *data = frame;
 434         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 435         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 436         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 437         u32 val = I915_READ(reg);
 438         int i;
 439
 440         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 441
 442         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 443         val |= g4x_infoframe_index(type);
 444
 445         val &= ~g4x_infoframe_enable(type);
 446
 447         I915_WRITE(reg, val);
 448
 449         mmiowb();
 450         for (i = 0; i < len; i += 4) {
 451                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 452                 data++;
 453         }
 454         /* Write every possible data byte to force correct ECC calculation. */
 455         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 456                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 457         mmiowb();
 458
 459         val |= g4x_infoframe_enable(type);
 460         val &= ~VIDEO_DIP_FREQ_MASK;
 461         val |= VIDEO_DIP_FREQ_VSYNC;
 462
 463         I915_WRITE(reg, val);
 464         POSTING_READ(reg);
 465 }
 466
 467 static void vlv_read_infoframe(struct intel_encoder *encoder,
 468                                const struct intel_crtc_state *crtc_state,
 469                                unsigned int type,
 470                                void *frame, ssize_t len)
 471 {
 472         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 473         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 474         u32 val, *data = frame;
 475         int i;
 476
 477         val = I915_READ(VLV_TVIDEO_DIP_CTL(crtc->pipe));
 478
 479         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 480         val |= g4x_infoframe_index(type);
 481
 482         I915_WRITE(VLV_TVIDEO_DIP_CTL(crtc->pipe), val);
 483
 484         for (i = 0; i < len; i += 4)
 485                 *data++ = I915_READ(VLV_TVIDEO_DIP_DATA(crtc->pipe));
 486 }
 487
 488 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
 489                                   const struct intel_crtc_state *pipe_config)
 490 {
 491         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 492         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 493         u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
 494
 495         if ((val & VIDEO_DIP_ENABLE) == 0)
 496                 return 0;
 497
 498         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 499                 return 0;
 500
 501         return val & (VIDEO_DIP_ENABLE_AVI |
 502                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 503                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 504 }
 505
 506 static void hsw_write_infoframe(struct intel_encoder *encoder,
 507                                 const struct intel_crtc_state *crtc_state,
 508                                 unsigned int type,
 509                                 const void *frame, ssize_t len)
 510 {
 511         const u32 *data = frame;
 512         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 513         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 514         i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
 515         int data_size;
 516         int i;
 517         u32 val = I915_READ(ctl_reg);
 518
 519         data_size = hsw_dip_data_size(type);
 520
 521         val &= ~hsw_infoframe_enable(type);
 522         I915_WRITE(ctl_reg, val);
 523
 524         mmiowb();
 525         for (i = 0; i < len; i += 4) {
 526                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 527                                             type, i >> 2), *data);
 528                 data++;
 529         }
 530         /* Write every possible data byte to force correct ECC calculation. */
 531         for (; i < data_size; i += 4)
 532                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 533                                             type, i >> 2), 0);
 534         mmiowb();
 535
 536         val |= hsw_infoframe_enable(type);
 537         I915_WRITE(ctl_reg, val);
 538         POSTING_READ(ctl_reg);
 539 }
 540
 541 static void hsw_read_infoframe(struct intel_encoder *encoder,
 542                                const struct intel_crtc_state *crtc_state,
 543                                unsigned int type,
 544                                void *frame, ssize_t len)
 545 {
 546         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 547         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 548         u32 val, *data = frame;
 549         int i;
 550
 551         val = I915_READ(HSW_TVIDEO_DIP_CTL(cpu_transcoder));
 552
 553         for (i = 0; i < len; i += 4)
 554                 *data++ = I915_READ(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 555                                                      type, i >> 2));
 556 }
 557
 558 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
 559                                   const struct intel_crtc_state *pipe_config)
 560 {
 561         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 562         u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
 563
 564         return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 565                       VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 566                       VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 567 }
 568
 569 static const u8 infoframe_type_to_idx[] = {
 570         HDMI_PACKET_TYPE_GENERAL_CONTROL,
 571         HDMI_PACKET_TYPE_GAMUT_METADATA,
 572         DP_SDP_VSC,
 573         HDMI_INFOFRAME_TYPE_AVI,
 574         HDMI_INFOFRAME_TYPE_SPD,
 575         HDMI_INFOFRAME_TYPE_VENDOR,
 576 };
 577
 578 u32 intel_hdmi_infoframe_enable(unsigned int type)
 579 {
 580         int i;
 581
 582         for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
 583                 if (infoframe_type_to_idx[i] == type)
 584                         return BIT(i);
 585         }
 586
 587         return 0;
 588 }
 589
 590 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
 591                                   const struct intel_crtc_state *crtc_state)
 592 {
 593         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 594         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
 595         u32 val, ret = 0;
 596         int i;
 597
 598         val = dig_port->infoframes_enabled(encoder, crtc_state);
 599
 600         /* map from hardware bits to dip idx */
 601         for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
 602                 unsigned int type = infoframe_type_to_idx[i];
 603
 604                 if (HAS_DDI(dev_priv)) {
 605                         if (val & hsw_infoframe_enable(type))
 606                                 ret |= BIT(i);
 607                 } else {
 608                         if (val & g4x_infoframe_enable(type))
 609                                 ret |= BIT(i);
 610                 }
 611         }
 612
 613         return ret;
 614 }
 615
 616 /*
 617  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 618  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 619  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 620  * used for both technologies.
 621  *
 622  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 623  * DW1:       DB3       | DB2 | DB1 | DB0
 624  * DW2:       DB7       | DB6 | DB5 | DB4
 625  * DW3: ...
 626  *
 627  * (HB is Header Byte, DB is Data Byte)
 628  *
 629  * The hdmi pack() functions don't know about that hardware specific hole so we
 630  * trick them by giving an offset into the buffer and moving back the header
 631  * bytes by one.
 632  */
 633 static void intel_write_infoframe(struct intel_encoder *encoder,
 634                                   const struct intel_crtc_state *crtc_state,
 635                                   enum hdmi_infoframe_type type,
 636                                   const union hdmi_infoframe *frame)
 637 {
 638         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
 639         u8 buffer[VIDEO_DIP_DATA_SIZE];
 640         ssize_t len;
 641
 642         if ((crtc_state->infoframes.enable &
 643              intel_hdmi_infoframe_enable(type)) == 0)
 644                 return;
 645
 646         if (WARN_ON(frame->any.type != type))
 647                 return;
 648
 649         /* see comment above for the reason for this offset */
 650         len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
 651         if (WARN_ON(len < 0))
 652                 return;
 653
 654         /* Insert the 'hole' (see big comment above) at position 3 */
 655         memmove(&buffer[0], &buffer[1], 3);
 656         buffer[3] = 0;
 657         len++;
 658
 659         intel_dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
 660 }
 661
 662 void intel_read_infoframe(struct intel_encoder *encoder,
 663                           const struct intel_crtc_state *crtc_state,
 664                           enum hdmi_infoframe_type type,
 665                           union hdmi_infoframe *frame)
 666 {
 667         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
 668         u8 buffer[VIDEO_DIP_DATA_SIZE];
 669         int ret;
 670
 671         if ((crtc_state->infoframes.enable &
 672              intel_hdmi_infoframe_enable(type)) == 0)
 673                 return;
 674
 675         intel_dig_port->read_infoframe(encoder, crtc_state,
 676                                        type, buffer, sizeof(buffer));
 677
 678         /* Fill the 'hole' (see big comment above) at position 3 */
 679         memmove(&buffer[1], &buffer[0], 3);
 680
 681         /* see comment above for the reason for this offset */
 682         ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
 683         if (ret) {
 684                 DRM_DEBUG_KMS("Failed to unpack infoframe type 0x%02x\n", type);
 685                 return;
 686         }
 687
 688         if (frame->any.type != type)
 689                 DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
 690                               frame->any.type, type);
 691 }
 692
 693 static bool
 694 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
 695                                  struct intel_crtc_state *crtc_state,
 696                                  struct drm_connector_state *conn_state)
 697 {
 698         struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
 699         const struct drm_display_mode *adjusted_mode =
 700                 &crtc_state->base.adjusted_mode;
 701         struct drm_connector *connector = conn_state->connector;
 702         int ret;
 703
 704         if (!crtc_state->has_infoframe)
 705                 return true;
 706
 707         crtc_state->infoframes.enable |=
 708                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
 709
 710         ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector,
 711                                                        adjusted_mode);
 712         if (ret)
 713                 return false;
 714
 715         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 716                 frame->colorspace = HDMI_COLORSPACE_YUV420;
 717         else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 718                 frame->colorspace = HDMI_COLORSPACE_YUV444;
 719         else
 720                 frame->colorspace = HDMI_COLORSPACE_RGB;
 721
 722         drm_hdmi_avi_infoframe_colorspace(frame, conn_state);
 723
 724         drm_hdmi_avi_infoframe_quant_range(frame, connector,
 725                                            adjusted_mode,
 726                                            crtc_state->limited_color_range ?
 727                                            HDMI_QUANTIZATION_RANGE_LIMITED :
 728                                            HDMI_QUANTIZATION_RANGE_FULL);
 729
 730         drm_hdmi_avi_infoframe_content_type(frame, conn_state);
 731
 732         /* TODO: handle pixel repetition for YCBCR420 outputs */
 733
 734         ret = hdmi_avi_infoframe_check(frame);
 735         if (WARN_ON(ret))
 736                 return false;
 737
 738         return true;
 739 }
 740
 741 static bool
 742 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
 743                                  struct intel_crtc_state *crtc_state,
 744                                  struct drm_connector_state *conn_state)
 745 {
 746         struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
 747         int ret;
 748
 749         if (!crtc_state->has_infoframe)
 750                 return true;
 751
 752         crtc_state->infoframes.enable |=
 753                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
 754
 755         ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
 756         if (WARN_ON(ret))
 757                 return false;
 758
 759         frame->sdi = HDMI_SPD_SDI_PC;
 760
 761         ret = hdmi_spd_infoframe_check(frame);
 762         if (WARN_ON(ret))
 763                 return false;
 764
 765         return true;
 766 }
 767
 768 static bool
 769 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
 770                                   struct intel_crtc_state *crtc_state,
 771                                   struct drm_connector_state *conn_state)
 772 {
 773         struct hdmi_vendor_infoframe *frame =
 774                 &crtc_state->infoframes.hdmi.vendor.hdmi;
 775         const struct drm_display_info *info =
 776                 &conn_state->connector->display_info;
 777         int ret;
 778
 779         if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
 780                 return true;
 781
 782         crtc_state->infoframes.enable |=
 783                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);
 784
 785         ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
 786                                                           conn_state->connector,
 787                                                           &crtc_state->base.adjusted_mode);
 788         if (WARN_ON(ret))
 789                 return false;
 790
 791         ret = hdmi_vendor_infoframe_check(frame);
 792         if (WARN_ON(ret))
 793                 return false;
 794
 795         return true;
 796 }
 797
 798 static void g4x_set_infoframes(struct intel_encoder *encoder,
 799                                bool enable,
 800                                const struct intel_crtc_state *crtc_state,
 801                                const struct drm_connector_state *conn_state)
 802 {
 803         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 804         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
 805         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 806         i915_reg_t reg = VIDEO_DIP_CTL;
 807         u32 val = I915_READ(reg);
 808         u32 port = VIDEO_DIP_PORT(encoder->port);
 809
 810         assert_hdmi_port_disabled(intel_hdmi);
 811
 812         /* If the registers were not initialized yet, they might be zeroes,
 813          * which means we're selecting the AVI DIP and we're setting its
 814          * frequency to once. This seems to really confuse the HW and make
 815          * things stop working (the register spec says the AVI always needs to
 816          * be sent every VSync). So here we avoid writing to the register more
 817          * than we need and also explicitly select the AVI DIP and explicitly
 818          * set its frequency to every VSync. Avoiding to write it twice seems to
 819          * be enough to solve the problem, but being defensive shouldn't hurt us
 820          * either. */
 821         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 822
 823         if (!enable) {
 824                 if (!(val & VIDEO_DIP_ENABLE))
 825                         return;
 826                 if (port != (val & VIDEO_DIP_PORT_MASK)) {
 827                         DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
 828                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 829                         return;
 830                 }
 831                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 832                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 833                 I915_WRITE(reg, val);
 834                 POSTING_READ(reg);
 835                 return;
 836         }
 837
 838         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 839                 if (val & VIDEO_DIP_ENABLE) {
 840                         DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
 841                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 842                         return;
 843                 }
 844                 val &= ~VIDEO_DIP_PORT_MASK;
 845                 val |= port;
 846         }
 847
 848         val |= VIDEO_DIP_ENABLE;
 849         val &= ~(VIDEO_DIP_ENABLE_AVI |
 850                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 851
 852         I915_WRITE(reg, val);
 853         POSTING_READ(reg);
 854
 855         intel_write_infoframe(encoder, crtc_state,
 856                               HDMI_INFOFRAME_TYPE_AVI,
 857                               &crtc_state->infoframes.avi);
 858         intel_write_infoframe(encoder, crtc_state,
 859                               HDMI_INFOFRAME_TYPE_SPD,
 860                               &crtc_state->infoframes.spd);
 861         intel_write_infoframe(encoder, crtc_state,
 862                               HDMI_INFOFRAME_TYPE_VENDOR,
 863                               &crtc_state->infoframes.hdmi);
 864 }
 865
 866 /*
 867  * Determine if default_phase=1 can be indicated in the GCP infoframe.
 868  *
 869  * From HDMI specification 1.4a:
 870  * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
 871  * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
 872  * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
 873  * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
 874  *   phase of 0
 875  */
 876 static bool gcp_default_phase_possible(int pipe_bpp,
 877                                        const struct drm_display_mode *mode)
 878 {
 879         unsigned int pixels_per_group;
 880
 881         switch (pipe_bpp) {
 882         case 30:
 883                 /* 4 pixels in 5 clocks */
 884                 pixels_per_group = 4;
 885                 break;
 886         case 36:
 887                 /* 2 pixels in 3 clocks */
 888                 pixels_per_group = 2;
 889                 break;
 890         case 48:
 891                 /* 1 pixel in 2 clocks */
 892                 pixels_per_group = 1;
 893                 break;
 894         default:
 895                 /* phase information not relevant for 8bpc */
 896                 return false;
 897         }
 898
 899         return mode->crtc_hdisplay % pixels_per_group == 0 &&
 900                 mode->crtc_htotal % pixels_per_group == 0 &&
 901                 mode->crtc_hblank_start % pixels_per_group == 0 &&
 902                 mode->crtc_hblank_end % pixels_per_group == 0 &&
 903                 mode->crtc_hsync_start % pixels_per_group == 0 &&
 904                 mode->crtc_hsync_end % pixels_per_group == 0 &&
 905                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
 906                  mode->crtc_htotal/2 % pixels_per_group == 0);
 907 }
 908
 909 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
 910                                          const struct intel_crtc_state *crtc_state,
 911                                          const struct drm_connector_state *conn_state)
 912 {
 913         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 914         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 915         i915_reg_t reg;
 916
 917         if ((crtc_state->infoframes.enable &
 918              intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
 919                 return false;
 920
 921         if (HAS_DDI(dev_priv))
 922                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
 923         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 924                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 925         else if (HAS_PCH_SPLIT(dev_priv))
 926                 reg = TVIDEO_DIP_GCP(crtc->pipe);
 927         else
 928                 return false;
 929
 930         I915_WRITE(reg, crtc_state->infoframes.gcp);
 931
 932         return true;
 933 }
 934
 935 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
 936                                    struct intel_crtc_state *crtc_state)
 937 {
 938         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 939         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 940         i915_reg_t reg;
 941
 942         if ((crtc_state->infoframes.enable &
 943              intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
 944                 return;
 945
 946         if (HAS_DDI(dev_priv))
 947                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
 948         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 949                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 950         else if (HAS_PCH_SPLIT(dev_priv))
 951                 reg = TVIDEO_DIP_GCP(crtc->pipe);
 952         else
 953                 return;
 954
 955         crtc_state->infoframes.gcp = I915_READ(reg);
 956 }
 957
 958 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
 959                                              struct intel_crtc_state *crtc_state,
 960                                              struct drm_connector_state *conn_state)
 961 {
 962         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 963
 964         if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
 965                 return;
 966
 967         crtc_state->infoframes.enable |=
 968                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
 969
 970         /* Indicate color indication for deep color mode */
 971         if (crtc_state->pipe_bpp > 24)
 972                 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
 973
 974         /* Enable default_phase whenever the display mode is suitably aligned */
 975         if (gcp_default_phase_possible(crtc_state->pipe_bpp,
 976                                        &crtc_state->base.adjusted_mode))
 977                 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
 978 }
 979
 980 static void ibx_set_infoframes(struct intel_encoder *encoder,
 981                                bool enable,
 982                                const struct intel_crtc_state *crtc_state,
 983                                const struct drm_connector_state *conn_state)
 984 {
 985         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 986         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 987         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
 988         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 989         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 990         u32 val = I915_READ(reg);
 991         u32 port = VIDEO_DIP_PORT(encoder->port);
 992
 993         assert_hdmi_port_disabled(intel_hdmi);
 994
 995         /* See the big comment in g4x_set_infoframes() */
 996         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 997
 998         if (!enable) {
 999                 if (!(val & VIDEO_DIP_ENABLE))
1000                         return;
1001                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1002                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1003                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1004                 I915_WRITE(reg, val);
1005                 POSTING_READ(reg);
1006                 return;
1007         }
1008
1009         if (port != (val & VIDEO_DIP_PORT_MASK)) {
1010                 WARN(val & VIDEO_DIP_ENABLE,
1011                      "DIP already enabled on port %c\n",
1012                      (val & VIDEO_DIP_PORT_MASK) >> 29);
1013                 val &= ~VIDEO_DIP_PORT_MASK;
1014                 val |= port;
1015         }
1016
1017         val |= VIDEO_DIP_ENABLE;
1018         val &= ~(VIDEO_DIP_ENABLE_AVI |
1019                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1020                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1021
1022         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1023                 val |= VIDEO_DIP_ENABLE_GCP;
1024
1025         I915_WRITE(reg, val);
1026         POSTING_READ(reg);
1027
1028         intel_write_infoframe(encoder, crtc_state,
1029                               HDMI_INFOFRAME_TYPE_AVI,
1030                               &crtc_state->infoframes.avi);
1031         intel_write_infoframe(encoder, crtc_state,
1032                               HDMI_INFOFRAME_TYPE_SPD,
1033                               &crtc_state->infoframes.spd);
1034         intel_write_infoframe(encoder, crtc_state,
1035                               HDMI_INFOFRAME_TYPE_VENDOR,
1036                               &crtc_state->infoframes.hdmi);
1037 }
1038
1039 static void cpt_set_infoframes(struct intel_encoder *encoder,
1040                                bool enable,
1041                                const struct intel_crtc_state *crtc_state,
1042                                const struct drm_connector_state *conn_state)
1043 {
1044         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1045         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1046         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1047         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
1048         u32 val = I915_READ(reg);
1049
1050         assert_hdmi_port_disabled(intel_hdmi);
1051
1052         /* See the big comment in g4x_set_infoframes() */
1053         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1054
1055         if (!enable) {
1056                 if (!(val & VIDEO_DIP_ENABLE))
1057                         return;
1058                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1059                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1060                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1061                 I915_WRITE(reg, val);
1062                 POSTING_READ(reg);
1063                 return;
1064         }
1065
1066         /* Set both together, unset both together: see the spec. */
1067         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
1068         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1069                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1070
1071         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1072                 val |= VIDEO_DIP_ENABLE_GCP;
1073
1074         I915_WRITE(reg, val);
1075         POSTING_READ(reg);
1076
1077         intel_write_infoframe(encoder, crtc_state,
1078                               HDMI_INFOFRAME_TYPE_AVI,
1079                               &crtc_state->infoframes.avi);
1080         intel_write_infoframe(encoder, crtc_state,
1081                               HDMI_INFOFRAME_TYPE_SPD,
1082                               &crtc_state->infoframes.spd);
1083         intel_write_infoframe(encoder, crtc_state,
1084                               HDMI_INFOFRAME_TYPE_VENDOR,
1085                               &crtc_state->infoframes.hdmi);
1086 }
1087
1088 static void vlv_set_infoframes(struct intel_encoder *encoder,
1089                                bool enable,
1090                                const struct intel_crtc_state *crtc_state,
1091                                const struct drm_connector_state *conn_state)
1092 {
1093         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1094         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1095         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1096         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
1097         u32 val = I915_READ(reg);
1098         u32 port = VIDEO_DIP_PORT(encoder->port);
1099
1100         assert_hdmi_port_disabled(intel_hdmi);
1101
1102         /* See the big comment in g4x_set_infoframes() */
1103         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1104
1105         if (!enable) {
1106                 if (!(val & VIDEO_DIP_ENABLE))
1107                         return;
1108                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1109                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1110                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1111                 I915_WRITE(reg, val);
1112                 POSTING_READ(reg);
1113                 return;
1114         }
1115
1116         if (port != (val & VIDEO_DIP_PORT_MASK)) {
1117                 WARN(val & VIDEO_DIP_ENABLE,
1118                      "DIP already enabled on port %c\n",
1119                      (val & VIDEO_DIP_PORT_MASK) >> 29);
1120                 val &= ~VIDEO_DIP_PORT_MASK;
1121                 val |= port;
1122         }
1123
1124         val |= VIDEO_DIP_ENABLE;
1125         val &= ~(VIDEO_DIP_ENABLE_AVI |
1126                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1127                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1128
1129         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1130                 val |= VIDEO_DIP_ENABLE_GCP;
1131
1132         I915_WRITE(reg, val);
1133         POSTING_READ(reg);
1134
1135         intel_write_infoframe(encoder, crtc_state,
1136                               HDMI_INFOFRAME_TYPE_AVI,
1137                               &crtc_state->infoframes.avi);
1138         intel_write_infoframe(encoder, crtc_state,
1139                               HDMI_INFOFRAME_TYPE_SPD,
1140                               &crtc_state->infoframes.spd);
1141         intel_write_infoframe(encoder, crtc_state,
1142                               HDMI_INFOFRAME_TYPE_VENDOR,
1143                               &crtc_state->infoframes.hdmi);
1144 }
1145
1146 static void hsw_set_infoframes(struct intel_encoder *encoder,
1147                                bool enable,
1148                                const struct intel_crtc_state *crtc_state,
1149                                const struct drm_connector_state *conn_state)
1150 {
1151         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1152         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
1153         u32 val = I915_READ(reg);
1154
1155         assert_hdmi_transcoder_func_disabled(dev_priv,
1156                                              crtc_state->cpu_transcoder);
1157
1158         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
1159                  VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
1160                  VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
1161
1162         if (!enable) {
1163                 I915_WRITE(reg, val);
1164                 POSTING_READ(reg);
1165                 return;
1166         }
1167
1168         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1169                 val |= VIDEO_DIP_ENABLE_GCP_HSW;
1170
1171         I915_WRITE(reg, val);
1172         POSTING_READ(reg);
1173
1174         intel_write_infoframe(encoder, crtc_state,
1175                               HDMI_INFOFRAME_TYPE_AVI,
1176                               &crtc_state->infoframes.avi);
1177         intel_write_infoframe(encoder, crtc_state,
1178                               HDMI_INFOFRAME_TYPE_SPD,
1179                               &crtc_state->infoframes.spd);
1180         intel_write_infoframe(encoder, crtc_state,
1181                               HDMI_INFOFRAME_TYPE_VENDOR,
1182                               &crtc_state->infoframes.hdmi);
1183 }
1184
1185 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
1186 {
1187         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1188         struct i2c_adapter *adapter =
1189                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1190
1191         if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
1192                 return;
1193
1194         DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
1195                       enable ? "Enabling" : "Disabling");
1196
1197         drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
1198                                          adapter, enable);
1199 }
1200
1201 static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port,
1202                                 unsigned int offset, void *buffer, size_t size)
1203 {
1204         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1205         struct drm_i915_private *dev_priv =
1206                 intel_dig_port->base.base.dev->dev_private;
1207         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
1208                                                               hdmi->ddc_bus);
1209         int ret;
1210         u8 start = offset & 0xff;
1211         struct i2c_msg msgs[] = {
1212                 {
1213                         .addr = DRM_HDCP_DDC_ADDR,
1214                         .flags = 0,
1215                         .len = 1,
1216                         .buf = &start,
1217                 },
1218                 {
1219                         .addr = DRM_HDCP_DDC_ADDR,
1220                         .flags = I2C_M_RD,
1221                         .len = size,
1222                         .buf = buffer
1223                 }
1224         };
1225         ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
1226         if (ret == ARRAY_SIZE(msgs))
1227                 return 0;
1228         return ret >= 0 ? -EIO : ret;
1229 }
1230
1231 static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port,
1232                                  unsigned int offset, void *buffer, size_t size)
1233 {
1234         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1235         struct drm_i915_private *dev_priv =
1236                 intel_dig_port->base.base.dev->dev_private;
1237         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
1238                                                               hdmi->ddc_bus);
1239         int ret;
1240         u8 *write_buf;
1241         struct i2c_msg msg;
1242
1243         write_buf = kzalloc(size + 1, GFP_KERNEL);
1244         if (!write_buf)
1245                 return -ENOMEM;
1246
1247         write_buf[0] = offset & 0xff;
1248         memcpy(&write_buf[1], buffer, size);
1249
1250         msg.addr = DRM_HDCP_DDC_ADDR;
1251         msg.flags = 0,
1252         msg.len = size + 1,
1253         msg.buf = write_buf;
1254
1255         ret = i2c_transfer(adapter, &msg, 1);
1256         if (ret == 1)
1257                 ret = 0;
1258         else if (ret >= 0)
1259                 ret = -EIO;
1260
1261         kfree(write_buf);
1262         return ret;
1263 }
1264
1265 static
1266 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
1267                                   u8 *an)
1268 {
1269         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1270         struct drm_i915_private *dev_priv =
1271                 intel_dig_port->base.base.dev->dev_private;
1272         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
1273                                                               hdmi->ddc_bus);
1274         int ret;
1275
1276         ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an,
1277                                     DRM_HDCP_AN_LEN);
1278         if (ret) {
1279                 DRM_DEBUG_KMS("Write An over DDC failed (%d)\n", ret);
1280                 return ret;
1281         }
1282
1283         ret = intel_gmbus_output_aksv(adapter);
1284         if (ret < 0) {
1285                 DRM_DEBUG_KMS("Failed to output aksv (%d)\n", ret);
1286                 return ret;
1287         }
1288         return 0;
1289 }
1290
1291 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
1292                                      u8 *bksv)
1293 {
1294         int ret;
1295         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv,
1296                                    DRM_HDCP_KSV_LEN);
1297         if (ret)
1298                 DRM_DEBUG_KMS("Read Bksv over DDC failed (%d)\n", ret);
1299         return ret;
1300 }
1301
1302 static
1303 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
1304                                  u8 *bstatus)
1305 {
1306         int ret;
1307         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS,
1308                                    bstatus, DRM_HDCP_BSTATUS_LEN);
1309         if (ret)
1310                 DRM_DEBUG_KMS("Read bstatus over DDC failed (%d)\n", ret);
1311         return ret;
1312 }
1313
1314 static
1315 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
1316                                      bool *repeater_present)
1317 {
1318         int ret;
1319         u8 val;
1320
1321         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1322         if (ret) {
1323                 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1324                 return ret;
1325         }
1326         *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1327         return 0;
1328 }
1329
1330 static
1331 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
1332                                   u8 *ri_prime)
1333 {
1334         int ret;
1335         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME,
1336                                    ri_prime, DRM_HDCP_RI_LEN);
1337         if (ret)
1338                 DRM_DEBUG_KMS("Read Ri' over DDC failed (%d)\n", ret);
1339         return ret;
1340 }
1341
1342 static
1343 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
1344                                    bool *ksv_ready)
1345 {
1346         int ret;
1347         u8 val;
1348
1349         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1350         if (ret) {
1351                 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1352                 return ret;
1353         }
1354         *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1355         return 0;
1356 }
1357
1358 static
1359 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
1360                                   int num_downstream, u8 *ksv_fifo)
1361 {
1362         int ret;
1363         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO,
1364                                    ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1365         if (ret) {
1366                 DRM_DEBUG_KMS("Read ksv fifo over DDC failed (%d)\n", ret);
1367                 return ret;
1368         }
1369         return 0;
1370 }
1371
1372 static
1373 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
1374                                       int i, u32 *part)
1375 {
1376         int ret;
1377
1378         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1379                 return -EINVAL;
1380
1381         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i),
1382                                    part, DRM_HDCP_V_PRIME_PART_LEN);
1383         if (ret)
1384                 DRM_DEBUG_KMS("Read V'[%d] over DDC failed (%d)\n", i, ret);
1385         return ret;
1386 }
1387
1388 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector)
1389 {
1390         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1391         struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
1392         struct drm_crtc *crtc = connector->base.state->crtc;
1393         struct intel_crtc *intel_crtc = container_of(crtc,
1394                                                      struct intel_crtc, base);
1395         u32 scanline;
1396         int ret;
1397
1398         for (;;) {
1399                 scanline = I915_READ(PIPEDSL(intel_crtc->pipe));
1400                 if (scanline > 100 && scanline < 200)
1401                         break;
1402                 usleep_range(25, 50);
1403         }
1404
1405         ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, false);
1406         if (ret) {
1407                 DRM_ERROR("Disable HDCP signalling failed (%d)\n", ret);
1408                 return ret;
1409         }
1410         ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, true);
1411         if (ret) {
1412                 DRM_ERROR("Enable HDCP signalling failed (%d)\n", ret);
1413                 return ret;
1414         }
1415
1416         return 0;
1417 }
1418
1419 static
1420 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
1421                                       bool enable)
1422 {
1423         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1424         struct intel_connector *connector = hdmi->attached_connector;
1425         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1426         int ret;
1427
1428         if (!enable)
1429                 usleep_range(6, 60); /* Bspec says >= 6us */
1430
1431         ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable);
1432         if (ret) {
1433                 DRM_ERROR("%s HDCP signalling failed (%d)\n",
1434                           enable ? "Enable" : "Disable", ret);
1435                 return ret;
1436         }
1437
1438         /*
1439          * WA: To fix incorrect positioning of the window of
1440          * opportunity and enc_en signalling in KABYLAKE.
1441          */
1442         if (IS_KABYLAKE(dev_priv) && enable)
1443                 return kbl_repositioning_enc_en_signal(connector);
1444
1445         return 0;
1446 }
1447
1448 static
1449 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
1450 {
1451         struct drm_i915_private *dev_priv =
1452                 intel_dig_port->base.base.dev->dev_private;
1453         enum port port = intel_dig_port->base.port;
1454         int ret;
1455         union {
1456                 u32 reg;
1457                 u8 shim[DRM_HDCP_RI_LEN];
1458         } ri;
1459
1460         ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim);
1461         if (ret)
1462                 return false;
1463
1464         I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
1465
1466         /* Wait for Ri prime match */
1467         if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
1468                      (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1469                 DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
1470                           I915_READ(PORT_HDCP_STATUS(port)));
1471                 return false;
1472         }
1473         return true;
1474 }
1475
1476 static struct hdcp2_hdmi_msg_data {
1477         u8 msg_id;
1478         u32 timeout;
1479         u32 timeout2;
1480         } hdcp2_msg_data[] = {
1481                 {HDCP_2_2_AKE_INIT, 0, 0},
1482                 {HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, 0},
1483                 {HDCP_2_2_AKE_NO_STORED_KM, 0, 0},
1484                 {HDCP_2_2_AKE_STORED_KM, 0, 0},
1485                 {HDCP_2_2_AKE_SEND_HPRIME, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
1486                                 HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS},
1487                 {HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS,
1488                                 0},
1489                 {HDCP_2_2_LC_INIT, 0, 0},
1490                 {HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, 0},
1491                 {HDCP_2_2_SKE_SEND_EKS, 0, 0},
1492                 {HDCP_2_2_REP_SEND_RECVID_LIST,
1493                                 HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0},
1494                 {HDCP_2_2_REP_SEND_ACK, 0, 0},
1495                 {HDCP_2_2_REP_STREAM_MANAGE, 0, 0},
1496                 {HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS,
1497                                 0},
1498         };
1499
1500 static
1501 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
1502                                     u8 *rx_status)
1503 {
1504         return intel_hdmi_hdcp_read(intel_dig_port,
1505                                     HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
1506                                     rx_status,
1507                                     HDCP_2_2_HDMI_RXSTATUS_LEN);
1508 }
1509
1510 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
1511 {
1512         int i;
1513
1514         for (i = 0; i < ARRAY_SIZE(hdcp2_msg_data); i++)
1515                 if (hdcp2_msg_data[i].msg_id == msg_id &&
1516                     (msg_id != HDCP_2_2_AKE_SEND_HPRIME || is_paired))
1517                         return hdcp2_msg_data[i].timeout;
1518                 else if (hdcp2_msg_data[i].msg_id == msg_id)
1519                         return hdcp2_msg_data[i].timeout2;
1520
1521         return -EINVAL;
1522 }
1523
1524 static inline
1525 int hdcp2_detect_msg_availability(struct intel_digital_port *intel_digital_port,
1526                                   u8 msg_id, bool *msg_ready,
1527                                   ssize_t *msg_sz)
1528 {
1529         u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1530         int ret;
1531
1532         ret = intel_hdmi_hdcp2_read_rx_status(intel_digital_port, rx_status);
1533         if (ret < 0) {
1534                 DRM_DEBUG_KMS("rx_status read failed. Err %d\n", ret);
1535                 return ret;
1536         }
1537
1538         *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
1539                   rx_status[0]);
1540
1541         if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
1542                 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
1543                              *msg_sz);
1544         else
1545                 *msg_ready = *msg_sz;
1546
1547         return 0;
1548 }
1549
1550 static ssize_t
1551 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
1552                               u8 msg_id, bool paired)
1553 {
1554         bool msg_ready = false;
1555         int timeout, ret;
1556         ssize_t msg_sz = 0;
1557
1558         timeout = get_hdcp2_msg_timeout(msg_id, paired);
1559         if (timeout < 0)
1560                 return timeout;
1561
1562         ret = __wait_for(ret = hdcp2_detect_msg_availability(intel_dig_port,
1563                                                              msg_id, &msg_ready,
1564                                                              &msg_sz),
1565                          !ret && msg_ready && msg_sz, timeout * 1000,
1566                          1000, 5 * 1000);
1567         if (ret)
1568                 DRM_DEBUG_KMS("msg_id: %d, ret: %d, timeout: %d\n",
1569                               msg_id, ret, timeout);
1570
1571         return ret ? ret : msg_sz;
1572 }
1573
1574 static
1575 int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
1576                                void *buf, size_t size)
1577 {
1578         unsigned int offset;
1579
1580         offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
1581         return intel_hdmi_hdcp_write(intel_dig_port, offset, buf, size);
1582 }
1583
1584 static
1585 int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
1586                               u8 msg_id, void *buf, size_t size)
1587 {
1588         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1589         struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
1590         unsigned int offset;
1591         ssize_t ret;
1592
1593         ret = intel_hdmi_hdcp2_wait_for_msg(intel_dig_port, msg_id,
1594                                             hdcp->is_paired);
1595         if (ret < 0)
1596                 return ret;
1597
1598         /*
1599          * Available msg size should be equal to or lesser than the
1600          * available buffer.
1601          */
1602         if (ret > size) {
1603                 DRM_DEBUG_KMS("msg_sz(%zd) is more than exp size(%zu)\n",
1604                               ret, size);
1605                 return -1;
1606         }
1607
1608         offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
1609         ret = intel_hdmi_hdcp_read(intel_dig_port, offset, buf, ret);
1610         if (ret)
1611                 DRM_DEBUG_KMS("Failed to read msg_id: %d(%zd)\n", msg_id, ret);
1612
1613         return ret;
1614 }
1615
1616 static
1617 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *intel_dig_port)
1618 {
1619         u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1620         int ret;
1621
1622         ret = intel_hdmi_hdcp2_read_rx_status(intel_dig_port, rx_status);
1623         if (ret)
1624                 return ret;
1625
1626         /*
1627          * Re-auth request and Link Integrity Failures are represented by
1628          * same bit. i.e reauth_req.
1629          */
1630         if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
1631                 ret = HDCP_REAUTH_REQUEST;
1632         else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
1633                 ret = HDCP_TOPOLOGY_CHANGE;
1634
1635         return ret;
1636 }
1637
1638 static
1639 int intel_hdmi_hdcp2_capable(struct intel_digital_port *intel_dig_port,
1640                              bool *capable)
1641 {
1642         u8 hdcp2_version;
1643         int ret;
1644
1645         *capable = false;
1646         ret = intel_hdmi_hdcp_read(intel_dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
1647                                    &hdcp2_version, sizeof(hdcp2_version));
1648         if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
1649                 *capable = true;
1650
1651         return ret;
1652 }
1653
1654 static inline
1655 enum hdcp_wired_protocol intel_hdmi_hdcp2_protocol(void)
1656 {
1657         return HDCP_PROTOCOL_HDMI;
1658 }
1659
1660 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1661         .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1662         .read_bksv = intel_hdmi_hdcp_read_bksv,
1663         .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1664         .repeater_present = intel_hdmi_hdcp_repeater_present,
1665         .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1666         .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1667         .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1668         .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1669         .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1670         .check_link = intel_hdmi_hdcp_check_link,
1671         .write_2_2_msg = intel_hdmi_hdcp2_write_msg,
1672         .read_2_2_msg = intel_hdmi_hdcp2_read_msg,
1673         .check_2_2_link = intel_hdmi_hdcp2_check_link,
1674         .hdcp_2_2_capable = intel_hdmi_hdcp2_capable,
1675         .protocol = HDCP_PROTOCOL_HDMI,
1676 };
1677
1678 static void intel_hdmi_prepare(struct intel_encoder *encoder,
1679                                const struct intel_crtc_state *crtc_state)
1680 {
1681         struct drm_device *dev = encoder->base.dev;
1682         struct drm_i915_private *dev_priv = to_i915(dev);
1683         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1684         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1685         const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
1686         u32 hdmi_val;
1687
1688         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1689
1690         hdmi_val = SDVO_ENCODING_HDMI;
1691         if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
1692                 hdmi_val |= HDMI_COLOR_RANGE_16_235;
1693         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1694                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
1695         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1696                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
1697
1698         if (crtc_state->pipe_bpp > 24)
1699                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
1700         else
1701                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
1702
1703         if (crtc_state->has_hdmi_sink)
1704                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
1705
1706         if (HAS_PCH_CPT(dev_priv))
1707                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1708         else if (IS_CHERRYVIEW(dev_priv))
1709                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
1710         else
1711                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
1712
1713         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
1714         POSTING_READ(intel_hdmi->hdmi_reg);
1715 }
1716
1717 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
1718                                     enum pipe *pipe)
1719 {
1720         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1721         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1722         intel_wakeref_t wakeref;
1723         bool ret;
1724
1725         wakeref = intel_display_power_get_if_enabled(dev_priv,
1726                                                      encoder->power_domain);
1727         if (!wakeref)
1728                 return false;
1729
1730         ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe);
1731
1732         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1733
1734         return ret;
1735 }
1736
1737 static void intel_hdmi_get_config(struct intel_encoder *encoder,
1738                                   struct intel_crtc_state *pipe_config)
1739 {
1740         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1741         struct drm_device *dev = encoder->base.dev;
1742         struct drm_i915_private *dev_priv = to_i915(dev);
1743         u32 tmp, flags = 0;
1744         int dotclock;
1745
1746         pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
1747
1748         tmp = I915_READ(intel_hdmi->hdmi_reg);
1749
1750         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
1751                 flags |= DRM_MODE_FLAG_PHSYNC;
1752         else
1753                 flags |= DRM_MODE_FLAG_NHSYNC;
1754
1755         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
1756                 flags |= DRM_MODE_FLAG_PVSYNC;
1757         else
1758                 flags |= DRM_MODE_FLAG_NVSYNC;
1759
1760         if (tmp & HDMI_MODE_SELECT_HDMI)
1761                 pipe_config->has_hdmi_sink = true;
1762
1763         pipe_config->infoframes.enable |=
1764                 intel_hdmi_infoframes_enabled(encoder, pipe_config);
1765
1766         if (pipe_config->infoframes.enable)
1767                 pipe_config->has_infoframe = true;
1768
1769         if (tmp & SDVO_AUDIO_ENABLE)
1770                 pipe_config->has_audio = true;
1771
1772         if (!HAS_PCH_SPLIT(dev_priv) &&
1773             tmp & HDMI_COLOR_RANGE_16_235)
1774                 pipe_config->limited_color_range = true;
1775
1776         pipe_config->base.adjusted_mode.flags |= flags;
1777
1778         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
1779                 dotclock = pipe_config->port_clock * 2 / 3;
1780         else
1781                 dotclock = pipe_config->port_clock;
1782
1783         if (pipe_config->pixel_multiplier)
1784                 dotclock /= pipe_config->pixel_multiplier;
1785
1786         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1787
1788         pipe_config->lane_count = 4;
1789
1790         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
1791
1792         intel_read_infoframe(encoder, pipe_config,
1793                              HDMI_INFOFRAME_TYPE_AVI,
1794                              &pipe_config->infoframes.avi);
1795         intel_read_infoframe(encoder, pipe_config,
1796                              HDMI_INFOFRAME_TYPE_SPD,
1797                              &pipe_config->infoframes.spd);
1798         intel_read_infoframe(encoder, pipe_config,
1799                              HDMI_INFOFRAME_TYPE_VENDOR,
1800                              &pipe_config->infoframes.hdmi);
1801 }
1802
1803 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
1804                                     const struct intel_crtc_state *pipe_config,
1805                                     const struct drm_connector_state *conn_state)
1806 {
1807         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1808
1809         WARN_ON(!pipe_config->has_hdmi_sink);
1810         DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
1811                          pipe_name(crtc->pipe));
1812         intel_audio_codec_enable(encoder, pipe_config, conn_state);
1813 }
1814
1815 static void g4x_enable_hdmi(struct intel_encoder *encoder,
1816                             const struct intel_crtc_state *pipe_config,
1817                             const struct drm_connector_state *conn_state)
1818 {
1819         struct drm_device *dev = encoder->base.dev;
1820         struct drm_i915_private *dev_priv = to_i915(dev);
1821         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1822         u32 temp;
1823
1824         temp = I915_READ(intel_hdmi->hdmi_reg);
1825
1826         temp |= SDVO_ENABLE;
1827         if (pipe_config->has_audio)
1828                 temp |= SDVO_AUDIO_ENABLE;
1829
1830         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1831         POSTING_READ(intel_hdmi->hdmi_reg);
1832
1833         if (pipe_config->has_audio)
1834                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1835 }
1836
1837 static void ibx_enable_hdmi(struct intel_encoder *encoder,
1838                             const struct intel_crtc_state *pipe_config,
1839                             const struct drm_connector_state *conn_state)
1840 {
1841         struct drm_device *dev = encoder->base.dev;
1842         struct drm_i915_private *dev_priv = to_i915(dev);
1843         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1844         u32 temp;
1845
1846         temp = I915_READ(intel_hdmi->hdmi_reg);
1847
1848         temp |= SDVO_ENABLE;
1849         if (pipe_config->has_audio)
1850                 temp |= SDVO_AUDIO_ENABLE;
1851
1852         /*
1853          * HW workaround, need to write this twice for issue
1854          * that may result in first write getting masked.
1855          */
1856         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1857         POSTING_READ(intel_hdmi->hdmi_reg);
1858         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1859         POSTING_READ(intel_hdmi->hdmi_reg);
1860
1861         /*
1862          * HW workaround, need to toggle enable bit off and on
1863          * for 12bpc with pixel repeat.
1864          *
1865          * FIXME: BSpec says this should be done at the end of
1866          * of the modeset sequence, so not sure if this isn't too soon.
1867          */
1868         if (pipe_config->pipe_bpp > 24 &&
1869             pipe_config->pixel_multiplier > 1) {
1870                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1871                 POSTING_READ(intel_hdmi->hdmi_reg);
1872
1873                 /*
1874                  * HW workaround, need to write this twice for issue
1875                  * that may result in first write getting masked.
1876                  */
1877                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1878                 POSTING_READ(intel_hdmi->hdmi_reg);
1879                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1880                 POSTING_READ(intel_hdmi->hdmi_reg);
1881         }
1882
1883         if (pipe_config->has_audio)
1884                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1885 }
1886
1887 static void cpt_enable_hdmi(struct intel_encoder *encoder,
1888                             const struct intel_crtc_state *pipe_config,
1889                             const struct drm_connector_state *conn_state)
1890 {
1891         struct drm_device *dev = encoder->base.dev;
1892         struct drm_i915_private *dev_priv = to_i915(dev);
1893         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1894         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1895         enum pipe pipe = crtc->pipe;
1896         u32 temp;
1897
1898         temp = I915_READ(intel_hdmi->hdmi_reg);
1899
1900         temp |= SDVO_ENABLE;
1901         if (pipe_config->has_audio)
1902                 temp |= SDVO_AUDIO_ENABLE;
1903
1904         /*
1905          * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1906          *
1907          * The procedure for 12bpc is as follows:
1908          * 1. disable HDMI clock gating
1909          * 2. enable HDMI with 8bpc
1910          * 3. enable HDMI with 12bpc
1911          * 4. enable HDMI clock gating
1912          */
1913
1914         if (pipe_config->pipe_bpp > 24) {
1915                 I915_WRITE(TRANS_CHICKEN1(pipe),
1916                            I915_READ(TRANS_CHICKEN1(pipe)) |
1917                            TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1918
1919                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1920                 temp |= SDVO_COLOR_FORMAT_8bpc;
1921         }
1922
1923         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1924         POSTING_READ(intel_hdmi->hdmi_reg);
1925
1926         if (pipe_config->pipe_bpp > 24) {
1927                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1928                 temp |= HDMI_COLOR_FORMAT_12bpc;
1929
1930                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1931                 POSTING_READ(intel_hdmi->hdmi_reg);
1932
1933                 I915_WRITE(TRANS_CHICKEN1(pipe),
1934                            I915_READ(TRANS_CHICKEN1(pipe)) &
1935                            ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1936         }
1937
1938         if (pipe_config->has_audio)
1939                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1940 }
1941
1942 static void vlv_enable_hdmi(struct intel_encoder *encoder,
1943                             const struct intel_crtc_state *pipe_config,
1944                             const struct drm_connector_state *conn_state)
1945 {
1946 }
1947
1948 static void intel_disable_hdmi(struct intel_encoder *encoder,
1949                                const struct intel_crtc_state *old_crtc_state,
1950                                const struct drm_connector_state *old_conn_state)
1951 {
1952         struct drm_device *dev = encoder->base.dev;
1953         struct drm_i915_private *dev_priv = to_i915(dev);
1954         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1955         struct intel_digital_port *intel_dig_port =
1956                 hdmi_to_dig_port(intel_hdmi);
1957         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1958         u32 temp;
1959
1960         temp = I915_READ(intel_hdmi->hdmi_reg);
1961
1962         temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1963         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1964         POSTING_READ(intel_hdmi->hdmi_reg);
1965
1966         /*
1967          * HW workaround for IBX, we need to move the port
1968          * to transcoder A after disabling it to allow the
1969          * matching DP port to be enabled on transcoder A.
1970          */
1971         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1972                 /*
1973                  * We get CPU/PCH FIFO underruns on the other pipe when
1974                  * doing the workaround. Sweep them under the rug.
1975                  */
1976                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1977                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1978
1979                 temp &= ~SDVO_PIPE_SEL_MASK;
1980                 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
1981                 /*
1982                  * HW workaround, need to write this twice for issue
1983                  * that may result in first write getting masked.
1984                  */
1985                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1986                 POSTING_READ(intel_hdmi->hdmi_reg);
1987                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1988                 POSTING_READ(intel_hdmi->hdmi_reg);
1989
1990                 temp &= ~SDVO_ENABLE;
1991                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1992                 POSTING_READ(intel_hdmi->hdmi_reg);
1993
1994                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1995                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1996                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1997         }
1998
1999         intel_dig_port->set_infoframes(encoder,
2000                                        false,
2001                                        old_crtc_state, old_conn_state);
2002
2003         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2004 }
2005
2006 static void g4x_disable_hdmi(struct intel_encoder *encoder,
2007                              const struct intel_crtc_state *old_crtc_state,
2008                              const struct drm_connector_state *old_conn_state)
2009 {
2010         if (old_crtc_state->has_audio)
2011                 intel_audio_codec_disable(encoder,
2012                                           old_crtc_state, old_conn_state);
2013
2014         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
2015 }
2016
2017 static void pch_disable_hdmi(struct intel_encoder *encoder,
2018                              const struct intel_crtc_state *old_crtc_state,
2019                              const struct drm_connector_state *old_conn_state)
2020 {
2021         if (old_crtc_state->has_audio)
2022                 intel_audio_codec_disable(encoder,
2023                                           old_crtc_state, old_conn_state);
2024 }
2025
2026 static void pch_post_disable_hdmi(struct intel_encoder *encoder,
2027                                   const struct intel_crtc_state *old_crtc_state,
2028                                   const struct drm_connector_state *old_conn_state)
2029 {
2030         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
2031 }
2032
2033 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
2034 {
2035         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2036         const struct ddi_vbt_port_info *info =
2037                 &dev_priv->vbt.ddi_port_info[encoder->port];
2038         int max_tmds_clock;
2039
2040         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2041                 max_tmds_clock = 594000;
2042         else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
2043                 max_tmds_clock = 300000;
2044         else if (INTEL_GEN(dev_priv) >= 5)
2045                 max_tmds_clock = 225000;
2046         else
2047                 max_tmds_clock = 165000;
2048
2049         if (info->max_tmds_clock)
2050                 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
2051
2052         return max_tmds_clock;
2053 }
2054
2055 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
2056                                  bool respect_downstream_limits,
2057                                  bool force_dvi)
2058 {
2059         struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
2060         int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
2061
2062         if (respect_downstream_limits) {
2063                 struct intel_connector *connector = hdmi->attached_connector;
2064                 const struct drm_display_info *info = &connector->base.display_info;
2065
2066                 if (hdmi->dp_dual_mode.max_tmds_clock)
2067                         max_tmds_clock = min(max_tmds_clock,
2068                                              hdmi->dp_dual_mode.max_tmds_clock);
2069
2070                 if (info->max_tmds_clock)
2071                         max_tmds_clock = min(max_tmds_clock,
2072                                              info->max_tmds_clock);
2073                 else if (!hdmi->has_hdmi_sink || force_dvi)
2074                         max_tmds_clock = min(max_tmds_clock, 165000);
2075         }
2076
2077         return max_tmds_clock;
2078 }
2079
2080 static enum drm_mode_status
2081 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
2082                       int clock, bool respect_downstream_limits,
2083                       bool force_dvi)
2084 {
2085         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
2086
2087         if (clock < 25000)
2088                 return MODE_CLOCK_LOW;
2089         if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi))
2090                 return MODE_CLOCK_HIGH;
2091
2092         /* BXT DPLL can't generate 223-240 MHz */
2093         if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
2094                 return MODE_CLOCK_RANGE;
2095
2096         /* CHV DPLL can't generate 216-240 MHz */
2097         if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
2098                 return MODE_CLOCK_RANGE;
2099
2100         return MODE_OK;
2101 }
2102
2103 static enum drm_mode_status
2104 intel_hdmi_mode_valid(struct drm_connector *connector,
2105                       struct drm_display_mode *mode)
2106 {
2107         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
2108         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
2109         struct drm_i915_private *dev_priv = to_i915(dev);
2110         enum drm_mode_status status;
2111         int clock;
2112         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
2113         bool force_dvi =
2114                 READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI;
2115
2116         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
2117                 return MODE_NO_DBLESCAN;
2118
2119         clock = mode->clock;
2120
2121         if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
2122                 clock *= 2;
2123
2124         if (clock > max_dotclk)
2125                 return MODE_CLOCK_HIGH;
2126
2127         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
2128                 clock *= 2;
2129
2130         if (drm_mode_is_420_only(&connector->display_info, mode))
2131                 clock /= 2;
2132
2133         /* check if we can do 8bpc */
2134         status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);
2135
2136         if (hdmi->has_hdmi_sink && !force_dvi) {
2137                 /* if we can't do 8bpc we may still be able to do 12bpc */
2138                 if (status != MODE_OK && !HAS_GMCH(dev_priv))
2139                         status = hdmi_port_clock_valid(hdmi, clock * 3 / 2,
2140                                                        true, force_dvi);
2141
2142                 /* if we can't do 8,12bpc we may still be able to do 10bpc */
2143                 if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11)
2144                         status = hdmi_port_clock_valid(hdmi, clock * 5 / 4,
2145                                                        true, force_dvi);
2146         }
2147
2148         return status;
2149 }
2150
2151 static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
2152                                      int bpc)
2153 {
2154         struct drm_i915_private *dev_priv =
2155                 to_i915(crtc_state->base.crtc->dev);
2156         struct drm_atomic_state *state = crtc_state->base.state;
2157         struct drm_connector_state *connector_state;
2158         struct drm_connector *connector;
2159         const struct drm_display_mode *adjusted_mode =
2160                 &crtc_state->base.adjusted_mode;
2161         int i;
2162
2163         if (HAS_GMCH(dev_priv))
2164                 return false;
2165
2166         if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
2167                 return false;
2168
2169         if (crtc_state->pipe_bpp < bpc * 3)
2170                 return false;
2171
2172         if (!crtc_state->has_hdmi_sink)
2173                 return false;
2174
2175         /*
2176          * HDMI deep color affects the clocks, so it's only possible
2177          * when not cloning with other encoder types.
2178          */
2179         if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
2180                 return false;
2181
2182         for_each_new_connector_in_state(state, connector, connector_state, i) {
2183                 const struct drm_display_info *info = &connector->display_info;
2184
2185                 if (connector_state->crtc != crtc_state->base.crtc)
2186                         continue;
2187
2188                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2189                         const struct drm_hdmi_info *hdmi = &info->hdmi;
2190
2191                         if (bpc == 12 && !(hdmi->y420_dc_modes &
2192                                            DRM_EDID_YCBCR420_DC_36))
2193                                 return false;
2194                         else if (bpc == 10 && !(hdmi->y420_dc_modes &
2195                                                 DRM_EDID_YCBCR420_DC_30))
2196                                 return false;
2197                 } else {
2198                         if (bpc == 12 && !(info->edid_hdmi_dc_modes &
2199                                            DRM_EDID_HDMI_DC_36))
2200                                 return false;
2201                         else if (bpc == 10 && !(info->edid_hdmi_dc_modes &
2202                                                 DRM_EDID_HDMI_DC_30))
2203                                 return false;
2204                 }
2205         }
2206
2207         /* Display WA #1139: glk */
2208         if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
2209             adjusted_mode->htotal > 5460)
2210                 return false;
2211
2212         /* Display Wa_1405510057:icl */
2213         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
2214             bpc == 10 && INTEL_GEN(dev_priv) >= 11 &&
2215             (adjusted_mode->crtc_hblank_end -
2216              adjusted_mode->crtc_hblank_start) % 8 == 2)
2217                 return false;
2218
2219         return true;
2220 }
2221
2222 static bool
2223 intel_hdmi_ycbcr420_config(struct drm_connector *connector,
2224                            struct intel_crtc_state *config,
2225                            int *clock_12bpc, int *clock_10bpc,
2226                            int *clock_8bpc)
2227 {
2228         struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
2229
2230         if (!connector->ycbcr_420_allowed) {
2231                 DRM_ERROR("Platform doesn't support YCBCR420 output\n");
2232                 return false;
2233         }
2234
2235         /* YCBCR420 TMDS rate requirement is half the pixel clock */
2236         config->port_clock /= 2;
2237         *clock_12bpc /= 2;
2238         *clock_10bpc /= 2;
2239         *clock_8bpc /= 2;
2240         config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2241
2242         /* YCBCR 420 output conversion needs a scaler */
2243         if (skl_update_scaler_crtc(config)) {
2244                 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
2245                 return false;
2246         }
2247
2248         intel_pch_panel_fitting(intel_crtc, config,
2249                                 DRM_MODE_SCALE_FULLSCREEN);
2250
2251         return true;
2252 }
2253
2254 int intel_hdmi_compute_config(struct intel_encoder *encoder,
2255                               struct intel_crtc_state *pipe_config,
2256                               struct drm_connector_state *conn_state)
2257 {
2258         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2259         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2260         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2261         struct drm_connector *connector = conn_state->connector;
2262         struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
2263         struct intel_digital_connector_state *intel_conn_state =
2264                 to_intel_digital_connector_state(conn_state);
2265         int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
2266         int clock_10bpc = clock_8bpc * 5 / 4;
2267         int clock_12bpc = clock_8bpc * 3 / 2;
2268         int desired_bpp;
2269         bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
2270
2271         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2272                 return -EINVAL;
2273
2274         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2275         pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink;
2276
2277         if (pipe_config->has_hdmi_sink)
2278                 pipe_config->has_infoframe = true;
2279
2280         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2281                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
2282                 pipe_config->limited_color_range =
2283                         pipe_config->has_hdmi_sink &&
2284                         drm_default_rgb_quant_range(adjusted_mode) ==
2285                         HDMI_QUANTIZATION_RANGE_LIMITED;
2286         } else {
2287                 pipe_config->limited_color_range =
2288                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2289         }
2290
2291         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
2292                 pipe_config->pixel_multiplier = 2;
2293                 clock_8bpc *= 2;
2294                 clock_10bpc *= 2;
2295                 clock_12bpc *= 2;
2296         }
2297
2298         if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
2299                 if (!intel_hdmi_ycbcr420_config(connector, pipe_config,
2300                                                 &clock_12bpc, &clock_10bpc,
2301                                                 &clock_8bpc)) {
2302                         DRM_ERROR("Can't support YCBCR420 output\n");
2303                         return -EINVAL;
2304                 }
2305         }
2306
2307         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
2308                 pipe_config->has_pch_encoder = true;
2309
2310         if (pipe_config->has_hdmi_sink) {
2311                 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2312                         pipe_config->has_audio = intel_hdmi->has_audio;
2313                 else
2314                         pipe_config->has_audio =
2315                                 intel_conn_state->force_audio == HDMI_AUDIO_ON;
2316         }
2317
2318         /*
2319          * Note that g4x/vlv don't support 12bpc hdmi outputs. We also need
2320          * to check that the higher clock still fits within limits.
2321          */
2322         if (hdmi_deep_color_possible(pipe_config, 12) &&
2323             hdmi_port_clock_valid(intel_hdmi, clock_12bpc,
2324                                   true, force_dvi) == MODE_OK) {
2325                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
2326                 desired_bpp = 12*3;
2327
2328                 /* Need to adjust the port link by 1.5x for 12bpc. */
2329                 pipe_config->port_clock = clock_12bpc;
2330         } else if (hdmi_deep_color_possible(pipe_config, 10) &&
2331                    hdmi_port_clock_valid(intel_hdmi, clock_10bpc,
2332                                          true, force_dvi) == MODE_OK) {
2333                 DRM_DEBUG_KMS("picking bpc to 10 for HDMI output\n");
2334                 desired_bpp = 10 * 3;
2335
2336                 /* Need to adjust the port link by 1.25x for 10bpc. */
2337                 pipe_config->port_clock = clock_10bpc;
2338         } else {
2339                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
2340                 desired_bpp = 8*3;
2341
2342                 pipe_config->port_clock = clock_8bpc;
2343         }
2344
2345         if (!pipe_config->bw_constrained) {
2346                 DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp);
2347                 pipe_config->pipe_bpp = desired_bpp;
2348         }
2349
2350         if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
2351                                   false, force_dvi) != MODE_OK) {
2352                 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
2353                 return -EINVAL;
2354         }
2355
2356         /* Set user selected PAR to incoming mode's member */
2357         adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
2358
2359         pipe_config->lane_count = 4;
2360
2361         if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
2362                                            IS_GEMINILAKE(dev_priv))) {
2363                 if (scdc->scrambling.low_rates)
2364                         pipe_config->hdmi_scrambling = true;
2365
2366                 if (pipe_config->port_clock > 340000) {
2367                         pipe_config->hdmi_scrambling = true;
2368                         pipe_config->hdmi_high_tmds_clock_ratio = true;
2369                 }
2370         }
2371
2372         intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, conn_state);
2373
2374         if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
2375                 DRM_DEBUG_KMS("bad AVI infoframe\n");
2376                 return -EINVAL;
2377         }
2378
2379         if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
2380                 DRM_DEBUG_KMS("bad SPD infoframe\n");
2381                 return -EINVAL;
2382         }
2383
2384         if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
2385                 DRM_DEBUG_KMS("bad HDMI infoframe\n");
2386                 return -EINVAL;
2387         }
2388
2389         return 0;
2390 }
2391
2392 static void
2393 intel_hdmi_unset_edid(struct drm_connector *connector)
2394 {
2395         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2396
2397         intel_hdmi->has_hdmi_sink = false;
2398         intel_hdmi->has_audio = false;
2399
2400         intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
2401         intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
2402
2403         kfree(to_intel_connector(connector)->detect_edid);
2404         to_intel_connector(connector)->detect_edid = NULL;
2405 }
2406
2407 static void
2408 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
2409 {
2410         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2411         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
2412         enum port port = hdmi_to_dig_port(hdmi)->base.port;
2413         struct i2c_adapter *adapter =
2414                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
2415         enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
2416
2417         /*
2418          * Type 1 DVI adaptors are not required to implement any
2419          * registers, so we can't always detect their presence.
2420          * Ideally we should be able to check the state of the
2421          * CONFIG1 pin, but no such luck on our hardware.
2422          *
2423          * The only method left to us is to check the VBT to see
2424          * if the port is a dual mode capable DP port. But let's
2425          * only do that when we sucesfully read the EDID, to avoid
2426          * confusing log messages about DP dual mode adaptors when
2427          * there's nothing connected to the port.
2428          */
2429         if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
2430                 /* An overridden EDID imply that we want this port for testing.
2431                  * Make sure not to set limits for that port.
2432                  */
2433                 if (has_edid && !connector->override_edid &&
2434                     intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2435                         DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
2436                         type = DRM_DP_DUAL_MODE_TYPE1_DVI;
2437                 } else {
2438                         type = DRM_DP_DUAL_MODE_NONE;
2439                 }
2440         }
2441
2442         if (type == DRM_DP_DUAL_MODE_NONE)
2443                 return;
2444
2445         hdmi->dp_dual_mode.type = type;
2446         hdmi->dp_dual_mode.max_tmds_clock =
2447                 drm_dp_dual_mode_max_tmds_clock(type, adapter);
2448
2449         DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2450                       drm_dp_get_dual_mode_type_name(type),
2451                       hdmi->dp_dual_mode.max_tmds_clock);
2452 }
2453
2454 static bool
2455 intel_hdmi_set_edid(struct drm_connector *connector)
2456 {
2457         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2458         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2459         intel_wakeref_t wakeref;
2460         struct edid *edid;
2461         bool connected = false;
2462         struct i2c_adapter *i2c;
2463
2464         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2465
2466         i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2467
2468         edid = drm_get_edid(connector, i2c);
2469
2470         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
2471                 DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2472                 intel_gmbus_force_bit(i2c, true);
2473                 edid = drm_get_edid(connector, i2c);
2474                 intel_gmbus_force_bit(i2c, false);
2475         }
2476
2477         intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
2478
2479         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2480
2481         to_intel_connector(connector)->detect_edid = edid;
2482         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
2483                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
2484                 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
2485
2486                 connected = true;
2487         }
2488
2489         cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
2490
2491         return connected;
2492 }
2493
2494 static enum drm_connector_status
2495 intel_hdmi_detect(struct drm_connector *connector, bool force)
2496 {
2497         enum drm_connector_status status = connector_status_disconnected;
2498         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2499         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2500         struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2501         intel_wakeref_t wakeref;
2502
2503         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2504                       connector->base.id, connector->name);
2505
2506         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2507
2508         if (INTEL_GEN(dev_priv) >= 11 &&
2509             !intel_digital_port_connected(encoder))
2510                 goto out;
2511
2512         intel_hdmi_unset_edid(connector);
2513
2514         if (intel_hdmi_set_edid(connector))
2515                 status = connector_status_connected;
2516
2517 out:
2518         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2519
2520         if (status != connector_status_connected)
2521                 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
2522
2523         return status;
2524 }
2525
2526 static void
2527 intel_hdmi_force(struct drm_connector *connector)
2528 {
2529         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2530                       connector->base.id, connector->name);
2531
2532         intel_hdmi_unset_edid(connector);
2533
2534         if (connector->status != connector_status_connected)
2535                 return;
2536
2537         intel_hdmi_set_edid(connector);
2538 }
2539
2540 static int intel_hdmi_get_modes(struct drm_connector *connector)
2541 {
2542         struct edid *edid;
2543
2544         edid = to_intel_connector(connector)->detect_edid;
2545         if (edid == NULL)
2546                 return 0;
2547
2548         return intel_connector_update_modes(connector, edid);
2549 }
2550
2551 static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
2552                                   const struct intel_crtc_state *pipe_config,
2553                                   const struct drm_connector_state *conn_state)
2554 {
2555         struct intel_digital_port *intel_dig_port =
2556                 enc_to_dig_port(&encoder->base);
2557
2558         intel_hdmi_prepare(encoder, pipe_config);
2559
2560         intel_dig_port->set_infoframes(encoder,
2561                                        pipe_config->has_infoframe,
2562                                        pipe_config, conn_state);
2563 }
2564
2565 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
2566                                 const struct intel_crtc_state *pipe_config,
2567                                 const struct drm_connector_state *conn_state)
2568 {
2569         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2570         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2571
2572         vlv_phy_pre_encoder_enable(encoder, pipe_config);
2573
2574         /* HDMI 1.0V-2dB */
2575         vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
2576                                  0x2b247878);
2577
2578         dport->set_infoframes(encoder,
2579                               pipe_config->has_infoframe,
2580                               pipe_config, conn_state);
2581
2582         g4x_enable_hdmi(encoder, pipe_config, conn_state);
2583
2584         vlv_wait_port_ready(dev_priv, dport, 0x0);
2585 }
2586
2587 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2588                                     const struct intel_crtc_state *pipe_config,
2589                                     const struct drm_connector_state *conn_state)
2590 {
2591         intel_hdmi_prepare(encoder, pipe_config);
2592
2593         vlv_phy_pre_pll_enable(encoder, pipe_config);
2594 }
2595
2596 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2597                                     const struct intel_crtc_state *pipe_config,
2598                                     const struct drm_connector_state *conn_state)
2599 {
2600         intel_hdmi_prepare(encoder, pipe_config);
2601
2602         chv_phy_pre_pll_enable(encoder, pipe_config);
2603 }
2604
2605 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
2606                                       const struct intel_crtc_state *old_crtc_state,
2607                                       const struct drm_connector_state *old_conn_state)
2608 {
2609         chv_phy_post_pll_disable(encoder, old_crtc_state);
2610 }
2611
2612 static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
2613                                   const struct intel_crtc_state *old_crtc_state,
2614                                   const struct drm_connector_state *old_conn_state)
2615 {
2616         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
2617         vlv_phy_reset_lanes(encoder, old_crtc_state);
2618 }
2619
2620 static void chv_hdmi_post_disable(struct intel_encoder *encoder,
2621                                   const struct intel_crtc_state *old_crtc_state,
2622                                   const struct drm_connector_state *old_conn_state)
2623 {
2624         struct drm_device *dev = encoder->base.dev;
2625         struct drm_i915_private *dev_priv = to_i915(dev);
2626
2627         vlv_dpio_get(dev_priv);
2628
2629         /* Assert data lane reset */
2630         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2631
2632         vlv_dpio_put(dev_priv);
2633 }
2634
2635 static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
2636                                 const struct intel_crtc_state *pipe_config,
2637                                 const struct drm_connector_state *conn_state)
2638 {
2639         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2640         struct drm_device *dev = encoder->base.dev;
2641         struct drm_i915_private *dev_priv = to_i915(dev);
2642
2643         chv_phy_pre_encoder_enable(encoder, pipe_config);
2644
2645         /* FIXME: Program the support xxx V-dB */
2646         /* Use 800mV-0dB */
2647         chv_set_phy_signal_level(encoder, 128, 102, false);
2648
2649         dport->set_infoframes(encoder,
2650                               pipe_config->has_infoframe,
2651                               pipe_config, conn_state);
2652
2653         g4x_enable_hdmi(encoder, pipe_config, conn_state);
2654
2655         vlv_wait_port_ready(dev_priv, dport, 0x0);
2656
2657         /* Second common lane will stay alive on its own now */
2658         chv_phy_release_cl2_override(encoder);
2659 }
2660
2661 static int
2662 intel_hdmi_connector_register(struct drm_connector *connector)
2663 {
2664         int ret;
2665
2666         ret = intel_connector_register(connector);
2667         if (ret)
2668                 return ret;
2669
2670         i915_debugfs_connector_add(connector);
2671
2672         return ret;
2673 }
2674
2675 static void intel_hdmi_destroy(struct drm_connector *connector)
2676 {
2677         if (intel_attached_hdmi(connector)->cec_notifier)
2678                 cec_notifier_put(intel_attached_hdmi(connector)->cec_notifier);
2679
2680         intel_connector_destroy(connector);
2681 }
2682
2683 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2684         .detect = intel_hdmi_detect,
2685         .force = intel_hdmi_force,
2686         .fill_modes = drm_helper_probe_single_connector_modes,
2687         .atomic_get_property = intel_digital_connector_atomic_get_property,
2688         .atomic_set_property = intel_digital_connector_atomic_set_property,
2689         .late_register = intel_hdmi_connector_register,
2690         .early_unregister = intel_connector_unregister,
2691         .destroy = intel_hdmi_destroy,
2692         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2693         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2694 };
2695
2696 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2697         .get_modes = intel_hdmi_get_modes,
2698         .mode_valid = intel_hdmi_mode_valid,
2699         .atomic_check = intel_digital_connector_atomic_check,
2700 };
2701
2702 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
2703         .destroy = intel_encoder_destroy,
2704 };
2705
2706 static void
2707 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2708 {
2709         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2710         struct intel_digital_port *intel_dig_port =
2711                                 hdmi_to_dig_port(intel_hdmi);
2712
2713         intel_attach_force_audio_property(connector);
2714         intel_attach_broadcast_rgb_property(connector);
2715         intel_attach_aspect_ratio_property(connector);
2716
2717         /*
2718          * Attach Colorspace property for Non LSPCON based device
2719          * ToDo: This needs to be extended for LSPCON implementation
2720          * as well. Will be implemented separately.
2721          */
2722         if (!intel_dig_port->lspcon.active)
2723                 intel_attach_colorspace_property(connector);
2724
2725         drm_connector_attach_content_type_property(connector);
2726         connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2727
2728         if (!HAS_GMCH(dev_priv))
2729                 drm_connector_attach_max_bpc_property(connector, 8, 12);
2730 }
2731
2732 /*
2733  * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2734  * @encoder: intel_encoder
2735  * @connector: drm_connector
2736  * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2737  *  or reset the high tmds clock ratio for scrambling
2738  * @scrambling: bool to Indicate if the function needs to set or reset
2739  *  sink scrambling
2740  *
2741  * This function handles scrambling on HDMI 2.0 capable sinks.
2742  * If required clock rate is > 340 Mhz && scrambling is supported by sink
2743  * it enables scrambling. This should be called before enabling the HDMI
2744  * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2745  * detect a scrambled clock within 100 ms.
2746  *
2747  * Returns:
2748  * True on success, false on failure.
2749  */
2750 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2751                                        struct drm_connector *connector,
2752                                        bool high_tmds_clock_ratio,
2753                                        bool scrambling)
2754 {
2755         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2756         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2757         struct drm_scrambling *sink_scrambling =
2758                 &connector->display_info.hdmi.scdc.scrambling;
2759         struct i2c_adapter *adapter =
2760                 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2761
2762         if (!sink_scrambling->supported)
2763                 return true;
2764
2765         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2766                       connector->base.id, connector->name,
2767                       yesno(scrambling), high_tmds_clock_ratio ? 40 : 10);
2768
2769         /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2770         return drm_scdc_set_high_tmds_clock_ratio(adapter,
2771                                                   high_tmds_clock_ratio) &&
2772                 drm_scdc_set_scrambling(adapter, scrambling);
2773 }
2774
2775 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2776 {
2777         u8 ddc_pin;
2778
2779         switch (port) {
2780         case PORT_B:
2781                 ddc_pin = GMBUS_PIN_DPB;
2782                 break;
2783         case PORT_C:
2784                 ddc_pin = GMBUS_PIN_DPC;
2785                 break;
2786         case PORT_D:
2787                 ddc_pin = GMBUS_PIN_DPD_CHV;
2788                 break;
2789         default:
2790                 MISSING_CASE(port);
2791                 ddc_pin = GMBUS_PIN_DPB;
2792                 break;
2793         }
2794         return ddc_pin;
2795 }
2796
2797 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2798 {
2799         u8 ddc_pin;
2800
2801         switch (port) {
2802         case PORT_B:
2803                 ddc_pin = GMBUS_PIN_1_BXT;
2804                 break;
2805         case PORT_C:
2806                 ddc_pin = GMBUS_PIN_2_BXT;
2807                 break;
2808         default:
2809                 MISSING_CASE(port);
2810                 ddc_pin = GMBUS_PIN_1_BXT;
2811                 break;
2812         }
2813         return ddc_pin;
2814 }
2815
2816 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2817                               enum port port)
2818 {
2819         u8 ddc_pin;
2820
2821         switch (port) {
2822         case PORT_B:
2823                 ddc_pin = GMBUS_PIN_1_BXT;
2824                 break;
2825         case PORT_C:
2826                 ddc_pin = GMBUS_PIN_2_BXT;
2827                 break;
2828         case PORT_D:
2829                 ddc_pin = GMBUS_PIN_4_CNP;
2830                 break;
2831         case PORT_F:
2832                 ddc_pin = GMBUS_PIN_3_BXT;
2833                 break;
2834         default:
2835                 MISSING_CASE(port);
2836                 ddc_pin = GMBUS_PIN_1_BXT;
2837                 break;
2838         }
2839         return ddc_pin;
2840 }
2841
2842 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2843 {
2844         u8 ddc_pin;
2845
2846         switch (port) {
2847         case PORT_A:
2848                 ddc_pin = GMBUS_PIN_1_BXT;
2849                 break;
2850         case PORT_B:
2851                 ddc_pin = GMBUS_PIN_2_BXT;
2852                 break;
2853         case PORT_C:
2854                 ddc_pin = GMBUS_PIN_9_TC1_ICP;
2855                 break;
2856         case PORT_D:
2857                 ddc_pin = GMBUS_PIN_10_TC2_ICP;
2858                 break;
2859         case PORT_E:
2860                 ddc_pin = GMBUS_PIN_11_TC3_ICP;
2861                 break;
2862         case PORT_F:
2863                 ddc_pin = GMBUS_PIN_12_TC4_ICP;
2864                 break;
2865         default:
2866                 MISSING_CASE(port);
2867                 ddc_pin = GMBUS_PIN_2_BXT;
2868                 break;
2869         }
2870         return ddc_pin;
2871 }
2872
2873 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2874                               enum port port)
2875 {
2876         u8 ddc_pin;
2877
2878         switch (port) {
2879         case PORT_B:
2880                 ddc_pin = GMBUS_PIN_DPB;
2881                 break;
2882         case PORT_C:
2883                 ddc_pin = GMBUS_PIN_DPC;
2884                 break;
2885         case PORT_D:
2886                 ddc_pin = GMBUS_PIN_DPD;
2887                 break;
2888         default:
2889                 MISSING_CASE(port);
2890                 ddc_pin = GMBUS_PIN_DPB;
2891                 break;
2892         }
2893         return ddc_pin;
2894 }
2895
2896 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
2897                              enum port port)
2898 {
2899         const struct ddi_vbt_port_info *info =
2900                 &dev_priv->vbt.ddi_port_info[port];
2901         u8 ddc_pin;
2902
2903         if (info->alternate_ddc_pin) {
2904                 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
2905                               info->alternate_ddc_pin, port_name(port));
2906                 return info->alternate_ddc_pin;
2907         }
2908
2909         if (HAS_PCH_ICP(dev_priv))
2910                 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
2911         else if (HAS_PCH_CNP(dev_priv))
2912                 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
2913         else if (IS_GEN9_LP(dev_priv))
2914                 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
2915         else if (IS_CHERRYVIEW(dev_priv))
2916                 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
2917         else
2918                 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
2919
2920         DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
2921                       ddc_pin, port_name(port));
2922
2923         return ddc_pin;
2924 }
2925
2926 void intel_infoframe_init(struct intel_digital_port *intel_dig_port)
2927 {
2928         struct drm_i915_private *dev_priv =
2929                 to_i915(intel_dig_port->base.base.dev);
2930
2931         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2932                 intel_dig_port->write_infoframe = vlv_write_infoframe;
2933                 intel_dig_port->read_infoframe = vlv_read_infoframe;
2934                 intel_dig_port->set_infoframes = vlv_set_infoframes;
2935                 intel_dig_port->infoframes_enabled = vlv_infoframes_enabled;
2936         } else if (IS_G4X(dev_priv)) {
2937                 intel_dig_port->write_infoframe = g4x_write_infoframe;
2938                 intel_dig_port->read_infoframe = g4x_read_infoframe;
2939                 intel_dig_port->set_infoframes = g4x_set_infoframes;
2940                 intel_dig_port->infoframes_enabled = g4x_infoframes_enabled;
2941         } else if (HAS_DDI(dev_priv)) {
2942                 if (intel_dig_port->lspcon.active) {
2943                         intel_dig_port->write_infoframe = lspcon_write_infoframe;
2944                         intel_dig_port->read_infoframe = lspcon_read_infoframe;
2945                         intel_dig_port->set_infoframes = lspcon_set_infoframes;
2946                         intel_dig_port->infoframes_enabled = lspcon_infoframes_enabled;
2947                 } else {
2948                         intel_dig_port->write_infoframe = hsw_write_infoframe;
2949                         intel_dig_port->read_infoframe = hsw_read_infoframe;
2950                         intel_dig_port->set_infoframes = hsw_set_infoframes;
2951                         intel_dig_port->infoframes_enabled = hsw_infoframes_enabled;
2952                 }
2953         } else if (HAS_PCH_IBX(dev_priv)) {
2954                 intel_dig_port->write_infoframe = ibx_write_infoframe;
2955                 intel_dig_port->read_infoframe = ibx_read_infoframe;
2956                 intel_dig_port->set_infoframes = ibx_set_infoframes;
2957                 intel_dig_port->infoframes_enabled = ibx_infoframes_enabled;
2958         } else {
2959                 intel_dig_port->write_infoframe = cpt_write_infoframe;
2960                 intel_dig_port->read_infoframe = cpt_read_infoframe;
2961                 intel_dig_port->set_infoframes = cpt_set_infoframes;
2962                 intel_dig_port->infoframes_enabled = cpt_infoframes_enabled;
2963         }
2964 }
2965
2966 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
2967                                struct intel_connector *intel_connector)
2968 {
2969         struct drm_connector *connector = &intel_connector->base;
2970         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2971         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2972         struct drm_device *dev = intel_encoder->base.dev;
2973         struct drm_i915_private *dev_priv = to_i915(dev);
2974         enum port port = intel_encoder->port;
2975
2976         DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
2977                       port_name(port));
2978
2979         if (WARN(intel_dig_port->max_lanes < 4,
2980                  "Not enough lanes (%d) for HDMI on port %c\n",
2981                  intel_dig_port->max_lanes, port_name(port)))
2982                 return;
2983
2984         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
2985                            DRM_MODE_CONNECTOR_HDMIA);
2986         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2987
2988         connector->interlace_allowed = 1;
2989         connector->doublescan_allowed = 0;
2990         connector->stereo_allowed = 1;
2991
2992         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2993                 connector->ycbcr_420_allowed = true;
2994
2995         intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
2996
2997         if (WARN_ON(port == PORT_A))
2998                 return;
2999         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
3000
3001         if (HAS_DDI(dev_priv))
3002                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3003         else
3004                 intel_connector->get_hw_state = intel_connector_get_hw_state;
3005
3006         intel_hdmi_add_properties(intel_hdmi, connector);
3007
3008         intel_connector_attach_encoder(intel_connector, intel_encoder);
3009         intel_hdmi->attached_connector = intel_connector;
3010
3011         if (is_hdcp_supported(dev_priv, port)) {
3012                 int ret = intel_hdcp_init(intel_connector,
3013                                           &intel_hdmi_hdcp_shim);
3014                 if (ret)
3015                         DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
3016         }
3017
3018         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3019          * 0xd.  Failure to do so will result in spurious interrupts being
3020          * generated on the port when a cable is not attached.
3021          */
3022         if (IS_G45(dev_priv)) {
3023                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3024                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3025         }
3026
3027         intel_hdmi->cec_notifier = cec_notifier_get_conn(dev->dev,
3028                                                          port_identifier(port));
3029         if (!intel_hdmi->cec_notifier)
3030                 DRM_DEBUG_KMS("CEC notifier get failed\n");
3031 }
3032
3033 void intel_hdmi_init(struct drm_i915_private *dev_priv,
3034                      i915_reg_t hdmi_reg, enum port port)
3035 {
3036         struct intel_digital_port *intel_dig_port;
3037         struct intel_encoder *intel_encoder;
3038         struct intel_connector *intel_connector;
3039
3040         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3041         if (!intel_dig_port)
3042                 return;
3043
3044         intel_connector = intel_connector_alloc();
3045         if (!intel_connector) {
3046                 kfree(intel_dig_port);
3047                 return;
3048         }
3049
3050         intel_encoder = &intel_dig_port->base;
3051
3052         drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
3053                          &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
3054                          "HDMI %c", port_name(port));
3055
3056         intel_encoder->hotplug = intel_encoder_hotplug;
3057         intel_encoder->compute_config = intel_hdmi_compute_config;
3058         if (HAS_PCH_SPLIT(dev_priv)) {
3059                 intel_encoder->disable = pch_disable_hdmi;
3060                 intel_encoder->post_disable = pch_post_disable_hdmi;
3061         } else {
3062                 intel_encoder->disable = g4x_disable_hdmi;
3063         }
3064         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
3065         intel_encoder->get_config = intel_hdmi_get_config;
3066         if (IS_CHERRYVIEW(dev_priv)) {
3067                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
3068                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
3069                 intel_encoder->enable = vlv_enable_hdmi;
3070                 intel_encoder->post_disable = chv_hdmi_post_disable;
3071                 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
3072         } else if (IS_VALLEYVIEW(dev_priv)) {
3073                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
3074                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
3075                 intel_encoder->enable = vlv_enable_hdmi;
3076                 intel_encoder->post_disable = vlv_hdmi_post_disable;
3077         } else {
3078                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
3079                 if (HAS_PCH_CPT(dev_priv))
3080                         intel_encoder->enable = cpt_enable_hdmi;
3081                 else if (HAS_PCH_IBX(dev_priv))
3082                         intel_encoder->enable = ibx_enable_hdmi;
3083                 else
3084                         intel_encoder->enable = g4x_enable_hdmi;
3085         }
3086
3087         intel_encoder->type = INTEL_OUTPUT_HDMI;
3088         intel_encoder->power_domain = intel_port_to_power_domain(port);
3089         intel_encoder->port = port;
3090         if (IS_CHERRYVIEW(dev_priv)) {
3091                 if (port == PORT_D)
3092                         intel_encoder->crtc_mask = 1 << 2;
3093                 else
3094                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
3095         } else {
3096                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3097         }
3098         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
3099         /*
3100          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
3101          * to work on real hardware. And since g4x can send infoframes to
3102          * only one port anyway, nothing is lost by allowing it.
3103          */
3104         if (IS_G4X(dev_priv))
3105                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
3106
3107         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
3108         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
3109         intel_dig_port->max_lanes = 4;
3110
3111         intel_infoframe_init(intel_dig_port);
3112
3113         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
3114         intel_hdmi_init_connector(intel_dig_port, intel_connector);
3115 }