drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/sched/clock.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_encoder.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_dp_dual_mode_helper.h>
  39 #include <drm/drm_dp_mst_helper.h>
  40 #include <drm/drm_rect.h>
  41 #include <drm/drm_atomic.h>
  42
  43 /**
  44  * _wait_for - magic (register) wait macro
  45  *
  46  * Does the right thing for modeset paths when run under kdgb or similar atomic
  47  * contexts. Note that it's important that we check the condition again after
  48  * having timed out, since the timeout could be due to preemption or similar and
  49  * we've never had a chance to check the condition before the timeout.
  50  */
  51 #define _wait_for(COND, US, W) ({ \
  52         unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;   \
  53         int ret__;                                                      \
  54         might_sleep();                                                  \
  55         for (;;) {                                                      \
  56                 bool expired__ = time_after(jiffies, timeout__);        \
  57                 if (COND) {                                             \
  58                         ret__ = 0;                                      \
  59                         break;                                          \
  60                 }                                                       \
  61                 if (expired__) {                                        \
  62                         ret__ = -ETIMEDOUT;                             \
  63                         break;                                          \
  64                 }                                                       \
  65                 usleep_range((W), (W) * 2);                             \
  66         }                                                               \
  67         ret__;                                                          \
  68 })
  69
  70 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 1000)
  71
  72 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  73 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  74 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  75 #else
  76 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  77 #endif
  78
  79 #define _wait_for_atomic(COND, US, ATOMIC) \
  80 ({ \
  81         int cpu, ret, timeout = (US) * 1000; \
  82         u64 base; \
  83         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  84         if (!(ATOMIC)) { \
  85                 preempt_disable(); \
  86                 cpu = smp_processor_id(); \
  87         } \
  88         base = local_clock(); \
  89         for (;;) { \
  90                 u64 now = local_clock(); \
  91                 if (!(ATOMIC)) \
  92                         preempt_enable(); \
  93                 if (COND) { \
  94                         ret = 0; \
  95                         break; \
  96                 } \
  97                 if (now - base >= timeout) { \
  98                         ret = -ETIMEDOUT; \
  99                         break; \
 100                 } \
 101                 cpu_relax(); \
 102                 if (!(ATOMIC)) { \
 103                         preempt_disable(); \
 104                         if (unlikely(cpu != smp_processor_id())) { \
 105                                 timeout -= now - base; \
 106                                 cpu = smp_processor_id(); \
 107                                 base = local_clock(); \
 108                         } \
 109                 } \
 110         } \
 111         ret; \
 112 })
 113
 114 #define wait_for_us(COND, US) \
 115 ({ \
 116         int ret__; \
 117         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 118         if ((US) > 10) \
 119                 ret__ = _wait_for((COND), (US), 10); \
 120         else \
 121                 ret__ = _wait_for_atomic((COND), (US), 0); \
 122         ret__; \
 123 })
 124
 125 #define wait_for_atomic_us(COND, US) \
 126 ({ \
 127         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 128         BUILD_BUG_ON((US) > 50000); \
 129         _wait_for_atomic((COND), (US), 1); \
 130 })
 131
 132 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
 133
 134 #define KHz(x) (1000 * (x))
 135 #define MHz(x) KHz(1000 * (x))
 136
 137 /*
 138  * Display related stuff
 139  */
 140
 141 /* store information about an Ixxx DVO */
 142 /* The i830->i865 use multiple DVOs with multiple i2cs */
 143 /* the i915, i945 have a single sDVO i2c bus - which is different */
 144 #define MAX_OUTPUTS 6
 145 /* maximum connectors per crtcs in the mode set */
 146
 147 /* Maximum cursor sizes */
 148 #define GEN2_CURSOR_WIDTH 64
 149 #define GEN2_CURSOR_HEIGHT 64
 150 #define MAX_CURSOR_WIDTH 256
 151 #define MAX_CURSOR_HEIGHT 256
 152
 153 #define INTEL_I2C_BUS_DVO 1
 154 #define INTEL_I2C_BUS_SDVO 2
 155
 156 /* these are outputs from the chip - integrated only
 157    external chips are via DVO or SDVO output */
 158 enum intel_output_type {
 159         INTEL_OUTPUT_UNUSED = 0,
 160         INTEL_OUTPUT_ANALOG = 1,
 161         INTEL_OUTPUT_DVO = 2,
 162         INTEL_OUTPUT_SDVO = 3,
 163         INTEL_OUTPUT_LVDS = 4,
 164         INTEL_OUTPUT_TVOUT = 5,
 165         INTEL_OUTPUT_HDMI = 6,
 166         INTEL_OUTPUT_DP = 7,
 167         INTEL_OUTPUT_EDP = 8,
 168         INTEL_OUTPUT_DSI = 9,
 169         INTEL_OUTPUT_DDI = 10,
 170         INTEL_OUTPUT_DP_MST = 11,
 171 };
 172
 173 #define INTEL_DVO_CHIP_NONE 0
 174 #define INTEL_DVO_CHIP_LVDS 1
 175 #define INTEL_DVO_CHIP_TMDS 2
 176 #define INTEL_DVO_CHIP_TVOUT 4
 177
 178 #define INTEL_DSI_VIDEO_MODE    0
 179 #define INTEL_DSI_COMMAND_MODE  1
 180
 181 struct intel_framebuffer {
 182         struct drm_framebuffer base;
 183         struct drm_i915_gem_object *obj;
 184         struct intel_rotation_info rot_info;
 185
 186         /* for each plane in the normal GTT view */
 187         struct {
 188                 unsigned int x, y;
 189         } normal[2];
 190         /* for each plane in the rotated GTT view */
 191         struct {
 192                 unsigned int x, y;
 193                 unsigned int pitch; /* pixels */
 194         } rotated[2];
 195 };
 196
 197 struct intel_fbdev {
 198         struct drm_fb_helper helper;
 199         struct intel_framebuffer *fb;
 200         struct i915_vma *vma;
 201         async_cookie_t cookie;
 202         int preferred_bpp;
 203 };
 204
 205 struct intel_encoder {
 206         struct drm_encoder base;
 207
 208         enum intel_output_type type;
 209         enum port port;
 210         unsigned int cloneable;
 211         void (*hot_plug)(struct intel_encoder *);
 212         enum intel_output_type (*compute_output_type)(struct intel_encoder *,
 213                                                       struct intel_crtc_state *,
 214                                                       struct drm_connector_state *);
 215         bool (*compute_config)(struct intel_encoder *,
 216                                struct intel_crtc_state *,
 217                                struct drm_connector_state *);
 218         void (*pre_pll_enable)(struct intel_encoder *,
 219                                const struct intel_crtc_state *,
 220                                const struct drm_connector_state *);
 221         void (*pre_enable)(struct intel_encoder *,
 222                            const struct intel_crtc_state *,
 223                            const struct drm_connector_state *);
 224         void (*enable)(struct intel_encoder *,
 225                        const struct intel_crtc_state *,
 226                        const struct drm_connector_state *);
 227         void (*disable)(struct intel_encoder *,
 228                         const struct intel_crtc_state *,
 229                         const struct drm_connector_state *);
 230         void (*post_disable)(struct intel_encoder *,
 231                              const struct intel_crtc_state *,
 232                              const struct drm_connector_state *);
 233         void (*post_pll_disable)(struct intel_encoder *,
 234                                  const struct intel_crtc_state *,
 235                                  const struct drm_connector_state *);
 236         /* Read out the current hw state of this connector, returning true if
 237          * the encoder is active. If the encoder is enabled it also set the pipe
 238          * it is connected to in the pipe parameter. */
 239         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 240         /* Reconstructs the equivalent mode flags for the current hardware
 241          * state. This must be called _after_ display->get_pipe_config has
 242          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 243          * be set correctly before calling this function. */
 244         void (*get_config)(struct intel_encoder *,
 245                            struct intel_crtc_state *pipe_config);
 246         /* Returns a mask of power domains that need to be referenced as part
 247          * of the hardware state readout code. */
 248         u64 (*get_power_domains)(struct intel_encoder *encoder);
 249         /*
 250          * Called during system suspend after all pending requests for the
 251          * encoder are flushed (for example for DP AUX transactions) and
 252          * device interrupts are disabled.
 253          */
 254         void (*suspend)(struct intel_encoder *);
 255         int crtc_mask;
 256         enum hpd_pin hpd_pin;
 257         enum intel_display_power_domain power_domain;
 258         /* for communication with audio component; protected by av_mutex */
 259         const struct drm_connector *audio_connector;
 260 };
 261
 262 struct intel_panel {
 263         struct drm_display_mode *fixed_mode;
 264         struct drm_display_mode *alt_fixed_mode;
 265         struct drm_display_mode *downclock_mode;
 266
 267         /* backlight */
 268         struct {
 269                 bool present;
 270                 u32 level;
 271                 u32 min;
 272                 u32 max;
 273                 bool enabled;
 274                 bool combination_mode;  /* gen 2/4 only */
 275                 bool active_low_pwm;
 276                 bool alternate_pwm_increment;   /* lpt+ */
 277
 278                 /* PWM chip */
 279                 bool util_pin_active_low;       /* bxt+ */
 280                 u8 controller;          /* bxt+ only */
 281                 struct pwm_device *pwm;
 282
 283                 struct backlight_device *device;
 284
 285                 /* Connector and platform specific backlight functions */
 286                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 287                 uint32_t (*get)(struct intel_connector *connector);
 288                 void (*set)(const struct drm_connector_state *conn_state, uint32_t level);
 289                 void (*disable)(const struct drm_connector_state *conn_state);
 290                 void (*enable)(const struct intel_crtc_state *crtc_state,
 291                                const struct drm_connector_state *conn_state);
 292                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 293                                       uint32_t hz);
 294                 void (*power)(struct intel_connector *, bool enable);
 295         } backlight;
 296 };
 297
 298 struct intel_connector {
 299         struct drm_connector base;
 300         /*
 301          * The fixed encoder this connector is connected to.
 302          */
 303         struct intel_encoder *encoder;
 304
 305         /* ACPI device id for ACPI and driver cooperation */
 306         u32 acpi_device_id;
 307
 308         /* Reads out the current hw, returning true if the connector is enabled
 309          * and active (i.e. dpms ON state). */
 310         bool (*get_hw_state)(struct intel_connector *);
 311
 312         /* Panel info for eDP and LVDS */
 313         struct intel_panel panel;
 314
 315         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 316         struct edid *edid;
 317         struct edid *detect_edid;
 318
 319         /* since POLL and HPD connectors may use the same HPD line keep the native
 320            state of connector->polled in case hotplug storm detection changes it */
 321         u8 polled;
 322
 323         void *port; /* store this opaque as its illegal to dereference it */
 324
 325         struct intel_dp *mst_port;
 326
 327         /* Work struct to schedule a uevent on link train failure */
 328         struct work_struct modeset_retry_work;
 329 };
 330
 331 struct intel_digital_connector_state {
 332         struct drm_connector_state base;
 333
 334         enum hdmi_force_audio force_audio;
 335         int broadcast_rgb;
 336 };
 337
 338 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
 339
 340 struct dpll {
 341         /* given values */
 342         int n;
 343         int m1, m2;
 344         int p1, p2;
 345         /* derived values */
 346         int     dot;
 347         int     vco;
 348         int     m;
 349         int     p;
 350 };
 351
 352 struct intel_atomic_state {
 353         struct drm_atomic_state base;
 354
 355         struct {
 356                 /*
 357                  * Logical state of cdclk (used for all scaling, watermark,
 358                  * etc. calculations and checks). This is computed as if all
 359                  * enabled crtcs were active.
 360                  */
 361                 struct intel_cdclk_state logical;
 362
 363                 /*
 364                  * Actual state of cdclk, can be different from the logical
 365                  * state only when all crtc's are DPMS off.
 366                  */
 367                 struct intel_cdclk_state actual;
 368         } cdclk;
 369
 370         bool dpll_set, modeset;
 371
 372         /*
 373          * Does this transaction change the pipes that are active?  This mask
 374          * tracks which CRTC's have changed their active state at the end of
 375          * the transaction (not counting the temporary disable during modesets).
 376          * This mask should only be non-zero when intel_state->modeset is true,
 377          * but the converse is not necessarily true; simply changing a mode may
 378          * not flip the final active status of any CRTC's
 379          */
 380         unsigned int active_pipe_changes;
 381
 382         unsigned int active_crtcs;
 383         /* minimum acceptable cdclk for each pipe */
 384         int min_cdclk[I915_MAX_PIPES];
 385         /* minimum acceptable voltage level for each pipe */
 386         u8 min_voltage_level[I915_MAX_PIPES];
 387
 388         struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
 389
 390         /*
 391          * Current watermarks can't be trusted during hardware readout, so
 392          * don't bother calculating intermediate watermarks.
 393          */
 394         bool skip_intermediate_wm;
 395
 396         /* Gen9+ only */
 397         struct skl_wm_values wm_results;
 398
 399         struct i915_sw_fence commit_ready;
 400
 401         struct llist_node freed;
 402 };
 403
 404 struct intel_plane_state {
 405         struct drm_plane_state base;
 406         struct drm_rect clip;
 407         struct i915_vma *vma;
 408
 409         struct {
 410                 u32 offset;
 411                 int x, y;
 412         } main;
 413         struct {
 414                 u32 offset;
 415                 int x, y;
 416         } aux;
 417
 418         /* plane control register */
 419         u32 ctl;
 420
 421         /* plane color control register */
 422         u32 color_ctl;
 423
 424         /*
 425          * scaler_id
 426          *    = -1 : not using a scaler
 427          *    >=  0 : using a scalers
 428          *
 429          * plane requiring a scaler:
 430          *   - During check_plane, its bit is set in
 431          *     crtc_state->scaler_state.scaler_users by calling helper function
 432          *     update_scaler_plane.
 433          *   - scaler_id indicates the scaler it got assigned.
 434          *
 435          * plane doesn't require a scaler:
 436          *   - this can happen when scaling is no more required or plane simply
 437          *     got disabled.
 438          *   - During check_plane, corresponding bit is reset in
 439          *     crtc_state->scaler_state.scaler_users by calling helper function
 440          *     update_scaler_plane.
 441          */
 442         int scaler_id;
 443
 444         struct drm_intel_sprite_colorkey ckey;
 445 };
 446
 447 struct intel_initial_plane_config {
 448         struct intel_framebuffer *fb;
 449         unsigned int tiling;
 450         int size;
 451         u32 base;
 452 };
 453
 454 #define SKL_MIN_SRC_W 8
 455 #define SKL_MAX_SRC_W 4096
 456 #define SKL_MIN_SRC_H 8
 457 #define SKL_MAX_SRC_H 4096
 458 #define SKL_MIN_DST_W 8
 459 #define SKL_MAX_DST_W 4096
 460 #define SKL_MIN_DST_H 8
 461 #define SKL_MAX_DST_H 4096
 462
 463 struct intel_scaler {
 464         int in_use;
 465         uint32_t mode;
 466 };
 467
 468 struct intel_crtc_scaler_state {
 469 #define SKL_NUM_SCALERS 2
 470         struct intel_scaler scalers[SKL_NUM_SCALERS];
 471
 472         /*
 473          * scaler_users: keeps track of users requesting scalers on this crtc.
 474          *
 475          *     If a bit is set, a user is using a scaler.
 476          *     Here user can be a plane or crtc as defined below:
 477          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 478          *       bit 31    - crtc
 479          *
 480          * Instead of creating a new index to cover planes and crtc, using
 481          * existing drm_plane_index for planes which is well less than 31
 482          * planes and bit 31 for crtc. This should be fine to cover all
 483          * our platforms.
 484          *
 485          * intel_atomic_setup_scalers will setup available scalers to users
 486          * requesting scalers. It will gracefully fail if request exceeds
 487          * avilability.
 488          */
 489 #define SKL_CRTC_INDEX 31
 490         unsigned scaler_users;
 491
 492         /* scaler used by crtc for panel fitting purpose */
 493         int scaler_id;
 494 };
 495
 496 /* drm_mode->private_flags */
 497 #define I915_MODE_FLAG_INHERITED 1
 498 /* Flag to get scanline using frame time stamps */
 499 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
 500
 501 struct intel_pipe_wm {
 502         struct intel_wm_level wm[5];
 503         uint32_t linetime;
 504         bool fbc_wm_enabled;
 505         bool pipe_enabled;
 506         bool sprites_enabled;
 507         bool sprites_scaled;
 508 };
 509
 510 struct skl_plane_wm {
 511         struct skl_wm_level wm[8];
 512         struct skl_wm_level trans_wm;
 513 };
 514
 515 struct skl_pipe_wm {
 516         struct skl_plane_wm planes[I915_MAX_PLANES];
 517         uint32_t linetime;
 518 };
 519
 520 enum vlv_wm_level {
 521         VLV_WM_LEVEL_PM2,
 522         VLV_WM_LEVEL_PM5,
 523         VLV_WM_LEVEL_DDR_DVFS,
 524         NUM_VLV_WM_LEVELS,
 525 };
 526
 527 struct vlv_wm_state {
 528         struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
 529         struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
 530         uint8_t num_levels;
 531         bool cxsr;
 532 };
 533
 534 struct vlv_fifo_state {
 535         u16 plane[I915_MAX_PLANES];
 536 };
 537
 538 enum g4x_wm_level {
 539         G4X_WM_LEVEL_NORMAL,
 540         G4X_WM_LEVEL_SR,
 541         G4X_WM_LEVEL_HPLL,
 542         NUM_G4X_WM_LEVELS,
 543 };
 544
 545 struct g4x_wm_state {
 546         struct g4x_pipe_wm wm;
 547         struct g4x_sr_wm sr;
 548         struct g4x_sr_wm hpll;
 549         bool cxsr;
 550         bool hpll_en;
 551         bool fbc_en;
 552 };
 553
 554 struct intel_crtc_wm_state {
 555         union {
 556                 struct {
 557                         /*
 558                          * Intermediate watermarks; these can be
 559                          * programmed immediately since they satisfy
 560                          * both the current configuration we're
 561                          * switching away from and the new
 562                          * configuration we're switching to.
 563                          */
 564                         struct intel_pipe_wm intermediate;
 565
 566                         /*
 567                          * Optimal watermarks, programmed post-vblank
 568                          * when this state is committed.
 569                          */
 570                         struct intel_pipe_wm optimal;
 571                 } ilk;
 572
 573                 struct {
 574                         /* gen9+ only needs 1-step wm programming */
 575                         struct skl_pipe_wm optimal;
 576                         struct skl_ddb_entry ddb;
 577                 } skl;
 578
 579                 struct {
 580                         /* "raw" watermarks (not inverted) */
 581                         struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
 582                         /* intermediate watermarks (inverted) */
 583                         struct vlv_wm_state intermediate;
 584                         /* optimal watermarks (inverted) */
 585                         struct vlv_wm_state optimal;
 586                         /* display FIFO split */
 587                         struct vlv_fifo_state fifo_state;
 588                 } vlv;
 589
 590                 struct {
 591                         /* "raw" watermarks */
 592                         struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
 593                         /* intermediate watermarks */
 594                         struct g4x_wm_state intermediate;
 595                         /* optimal watermarks */
 596                         struct g4x_wm_state optimal;
 597                 } g4x;
 598         };
 599
 600         /*
 601          * Platforms with two-step watermark programming will need to
 602          * update watermark programming post-vblank to switch from the
 603          * safe intermediate watermarks to the optimal final
 604          * watermarks.
 605          */
 606         bool need_postvbl_update;
 607 };
 608
 609 struct intel_crtc_state {
 610         struct drm_crtc_state base;
 611
 612         /**
 613          * quirks - bitfield with hw state readout quirks
 614          *
 615          * For various reasons the hw state readout code might not be able to
 616          * completely faithfully read out the current state. These cases are
 617          * tracked with quirk flags so that fastboot and state checker can act
 618          * accordingly.
 619          */
 620 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 621         unsigned long quirks;
 622
 623         unsigned fb_bits; /* framebuffers to flip */
 624         bool update_pipe; /* can a fast modeset be performed? */
 625         bool disable_cxsr;
 626         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 627         bool fb_changed; /* fb on any of the planes is changed */
 628         bool fifo_changed; /* FIFO split is changed */
 629
 630         /* Pipe source size (ie. panel fitter input size)
 631          * All planes will be positioned inside this space,
 632          * and get clipped at the edges. */
 633         int pipe_src_w, pipe_src_h;
 634
 635         /*
 636          * Pipe pixel rate, adjusted for
 637          * panel fitter/pipe scaler downscaling.
 638          */
 639         unsigned int pixel_rate;
 640
 641         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 642          * between pch encoders and cpu encoders. */
 643         bool has_pch_encoder;
 644
 645         /* Are we sending infoframes on the attached port */
 646         bool has_infoframe;
 647
 648         /* CPU Transcoder for the pipe. Currently this can only differ from the
 649          * pipe on Haswell and later (where we have a special eDP transcoder)
 650          * and Broxton (where we have special DSI transcoders). */
 651         enum transcoder cpu_transcoder;
 652
 653         /*
 654          * Use reduced/limited/broadcast rbg range, compressing from the full
 655          * range fed into the crtcs.
 656          */
 657         bool limited_color_range;
 658
 659         /* Bitmask of encoder types (enum intel_output_type)
 660          * driven by the pipe.
 661          */
 662         unsigned int output_types;
 663
 664         /* Whether we should send NULL infoframes. Required for audio. */
 665         bool has_hdmi_sink;
 666
 667         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 668          * has_dp_encoder is set. */
 669         bool has_audio;
 670
 671         /*
 672          * Enable dithering, used when the selected pipe bpp doesn't match the
 673          * plane bpp.
 674          */
 675         bool dither;
 676
 677         /*
 678          * Dither gets enabled for 18bpp which causes CRC mismatch errors for
 679          * compliance video pattern tests.
 680          * Disable dither only if it is a compliance test request for
 681          * 18bpp.
 682          */
 683         bool dither_force_disable;
 684
 685         /* Controls for the clock computation, to override various stages. */
 686         bool clock_set;
 687
 688         /* SDVO TV has a bunch of special case. To make multifunction encoders
 689          * work correctly, we need to track this at runtime.*/
 690         bool sdvo_tv_clock;
 691
 692         /*
 693          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 694          * required. This is set in the 2nd loop of calling encoder's
 695          * ->compute_config if the first pick doesn't work out.
 696          */
 697         bool bw_constrained;
 698
 699         /* Settings for the intel dpll used on pretty much everything but
 700          * haswell. */
 701         struct dpll dpll;
 702
 703         /* Selected dpll when shared or NULL. */
 704         struct intel_shared_dpll *shared_dpll;
 705
 706         /* Actual register state of the dpll, for shared dpll cross-checking. */
 707         struct intel_dpll_hw_state dpll_hw_state;
 708
 709         /* DSI PLL registers */
 710         struct {
 711                 u32 ctrl, div;
 712         } dsi_pll;
 713
 714         int pipe_bpp;
 715         struct intel_link_m_n dp_m_n;
 716
 717         /* m2_n2 for eDP downclock */
 718         struct intel_link_m_n dp_m2_n2;
 719         bool has_drrs;
 720
 721         bool has_psr;
 722         bool has_psr2;
 723
 724         /*
 725          * Frequence the dpll for the port should run at. Differs from the
 726          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 727          * already multiplied by pixel_multiplier.
 728          */
 729         int port_clock;
 730
 731         /* Used by SDVO (and if we ever fix it, HDMI). */
 732         unsigned pixel_multiplier;
 733
 734         uint8_t lane_count;
 735
 736         /*
 737          * Used by platforms having DP/HDMI PHY with programmable lane
 738          * latency optimization.
 739          */
 740         uint8_t lane_lat_optim_mask;
 741
 742         /* minimum acceptable voltage level */
 743         u8 min_voltage_level;
 744
 745         /* Panel fitter controls for gen2-gen4 + VLV */
 746         struct {
 747                 u32 control;
 748                 u32 pgm_ratios;
 749                 u32 lvds_border_bits;
 750         } gmch_pfit;
 751
 752         /* Panel fitter placement and size for Ironlake+ */
 753         struct {
 754                 u32 pos;
 755                 u32 size;
 756                 bool enabled;
 757                 bool force_thru;
 758         } pch_pfit;
 759
 760         /* FDI configuration, only valid if has_pch_encoder is set. */
 761         int fdi_lanes;
 762         struct intel_link_m_n fdi_m_n;
 763
 764         bool ips_enabled;
 765         bool ips_force_disable;
 766
 767         bool enable_fbc;
 768
 769         bool double_wide;
 770
 771         int pbn;
 772
 773         struct intel_crtc_scaler_state scaler_state;
 774
 775         /* w/a for waiting 2 vblanks during crtc enable */
 776         enum pipe hsw_workaround_pipe;
 777
 778         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 779         bool disable_lp_wm;
 780
 781         struct intel_crtc_wm_state wm;
 782
 783         /* Gamma mode programmed on the pipe */
 784         uint32_t gamma_mode;
 785
 786         /* bitmask of visible planes (enum plane_id) */
 787         u8 active_planes;
 788
 789         /* HDMI scrambling status */
 790         bool hdmi_scrambling;
 791
 792         /* HDMI High TMDS char rate ratio */
 793         bool hdmi_high_tmds_clock_ratio;
 794
 795         /* output format is YCBCR 4:2:0 */
 796         bool ycbcr420;
 797 };
 798
 799 struct intel_crtc {
 800         struct drm_crtc base;
 801         enum pipe pipe;
 802         enum plane plane;
 803         /*
 804          * Whether the crtc and the connected output pipeline is active. Implies
 805          * that crtc->enabled is set, i.e. the current mode configuration has
 806          * some outputs connected to this crtc.
 807          */
 808         bool active;
 809         u8 plane_ids_mask;
 810         unsigned long long enabled_power_domains;
 811         struct intel_overlay *overlay;
 812
 813         struct intel_crtc_state *config;
 814
 815         /* global reset count when the last flip was submitted */
 816         unsigned int reset_count;
 817
 818         /* Access to these should be protected by dev_priv->irq_lock. */
 819         bool cpu_fifo_underrun_disabled;
 820         bool pch_fifo_underrun_disabled;
 821
 822         /* per-pipe watermark state */
 823         struct {
 824                 /* watermarks currently being used  */
 825                 union {
 826                         struct intel_pipe_wm ilk;
 827                         struct vlv_wm_state vlv;
 828                         struct g4x_wm_state g4x;
 829                 } active;
 830         } wm;
 831
 832         int scanline_offset;
 833
 834         struct {
 835                 unsigned start_vbl_count;
 836                 ktime_t start_vbl_time;
 837                 int min_vbl, max_vbl;
 838                 int scanline_start;
 839         } debug;
 840
 841         /* scalers available on this crtc */
 842         int num_scalers;
 843 };
 844
 845 struct intel_plane {
 846         struct drm_plane base;
 847         u8 plane;
 848         enum plane_id id;
 849         enum pipe pipe;
 850         bool can_scale;
 851         int max_downscale;
 852         uint32_t frontbuffer_bit;
 853
 854         struct {
 855                 u32 base, cntl, size;
 856         } cursor;
 857
 858         /*
 859          * NOTE: Do not place new plane state fields here (e.g., when adding
 860          * new plane properties).  New runtime state should now be placed in
 861          * the intel_plane_state structure and accessed via plane_state.
 862          */
 863
 864         void (*update_plane)(struct intel_plane *plane,
 865                              const struct intel_crtc_state *crtc_state,
 866                              const struct intel_plane_state *plane_state);
 867         void (*disable_plane)(struct intel_plane *plane,
 868                               struct intel_crtc *crtc);
 869         int (*check_plane)(struct intel_plane *plane,
 870                            struct intel_crtc_state *crtc_state,
 871                            struct intel_plane_state *state);
 872 };
 873
 874 struct intel_watermark_params {
 875         u16 fifo_size;
 876         u16 max_wm;
 877         u8 default_wm;
 878         u8 guard_size;
 879         u8 cacheline_size;
 880 };
 881
 882 struct cxsr_latency {
 883         bool is_desktop : 1;
 884         bool is_ddr3 : 1;
 885         u16 fsb_freq;
 886         u16 mem_freq;
 887         u16 display_sr;
 888         u16 display_hpll_disable;
 889         u16 cursor_sr;
 890         u16 cursor_hpll_disable;
 891 };
 892
 893 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 894 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 895 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 896 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 897 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 898 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 899 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 900 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 901 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 902
 903 struct intel_hdmi {
 904         i915_reg_t hdmi_reg;
 905         int ddc_bus;
 906         struct {
 907                 enum drm_dp_dual_mode_type type;
 908                 int max_tmds_clock;
 909         } dp_dual_mode;
 910         bool has_hdmi_sink;
 911         bool has_audio;
 912         bool rgb_quant_range_selectable;
 913         struct intel_connector *attached_connector;
 914 };
 915
 916 struct intel_dp_mst_encoder;
 917 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 918
 919 /*
 920  * enum link_m_n_set:
 921  *      When platform provides two set of M_N registers for dp, we can
 922  *      program them and switch between them incase of DRRS.
 923  *      But When only one such register is provided, we have to program the
 924  *      required divider value on that registers itself based on the DRRS state.
 925  *
 926  * M1_N1        : Program dp_m_n on M1_N1 registers
 927  *                        dp_m2_n2 on M2_N2 registers (If supported)
 928  *
 929  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 930  *                        M2_N2 registers are not supported
 931  */
 932
 933 enum link_m_n_set {
 934         /* Sets the m1_n1 and m2_n2 */
 935         M1_N1 = 0,
 936         M2_N2
 937 };
 938
 939 struct intel_dp_compliance_data {
 940         unsigned long edid;
 941         uint8_t video_pattern;
 942         uint16_t hdisplay, vdisplay;
 943         uint8_t bpc;
 944 };
 945
 946 struct intel_dp_compliance {
 947         unsigned long test_type;
 948         struct intel_dp_compliance_data test_data;
 949         bool test_active;
 950         int test_link_rate;
 951         u8 test_lane_count;
 952 };
 953
 954 struct intel_dp {
 955         i915_reg_t output_reg;
 956         i915_reg_t aux_ch_ctl_reg;
 957         i915_reg_t aux_ch_data_reg[5];
 958         uint32_t DP;
 959         int link_rate;
 960         uint8_t lane_count;
 961         uint8_t sink_count;
 962         bool link_mst;
 963         bool has_audio;
 964         bool detect_done;
 965         bool channel_eq_status;
 966         bool reset_link_params;
 967         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 968         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 969         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 970         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 971         /* source rates */
 972         int num_source_rates;
 973         const int *source_rates;
 974         /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
 975         int num_sink_rates;
 976         int sink_rates[DP_MAX_SUPPORTED_RATES];
 977         bool use_rate_select;
 978         /* intersection of source and sink rates */
 979         int num_common_rates;
 980         int common_rates[DP_MAX_SUPPORTED_RATES];
 981         /* Max lane count for the current link */
 982         int max_link_lane_count;
 983         /* Max rate for the current link */
 984         int max_link_rate;
 985         /* sink or branch descriptor */
 986         struct drm_dp_desc desc;
 987         struct drm_dp_aux aux;
 988         enum intel_display_power_domain aux_power_domain;
 989         uint8_t train_set[4];
 990         int panel_power_up_delay;
 991         int panel_power_down_delay;
 992         int panel_power_cycle_delay;
 993         int backlight_on_delay;
 994         int backlight_off_delay;
 995         struct delayed_work panel_vdd_work;
 996         bool want_panel_vdd;
 997         unsigned long last_power_on;
 998         unsigned long last_backlight_off;
 999         ktime_t panel_power_off_time;
1000
1001         struct notifier_block edp_notifier;
1002
1003         /*
1004          * Pipe whose power sequencer is currently locked into
1005          * this port. Only relevant on VLV/CHV.
1006          */
1007         enum pipe pps_pipe;
1008         /*
1009          * Pipe currently driving the port. Used for preventing
1010          * the use of the PPS for any pipe currentrly driving
1011          * external DP as that will mess things up on VLV.
1012          */
1013         enum pipe active_pipe;
1014         /*
1015          * Set if the sequencer may be reset due to a power transition,
1016          * requiring a reinitialization. Only relevant on BXT.
1017          */
1018         bool pps_reset;
1019         struct edp_power_seq pps_delays;
1020
1021         bool can_mst; /* this port supports mst */
1022         bool is_mst;
1023         int active_mst_links;
1024         /* connector directly attached - won't be use for modeset in mst world */
1025         struct intel_connector *attached_connector;
1026
1027         /* mst connector list */
1028         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1029         struct drm_dp_mst_topology_mgr mst_mgr;
1030
1031         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1032         /*
1033          * This function returns the value we have to program the AUX_CTL
1034          * register with to kick off an AUX transaction.
1035          */
1036         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1037                                      bool has_aux_irq,
1038                                      int send_bytes,
1039                                      uint32_t aux_clock_divider);
1040
1041         /* This is called before a link training is starterd */
1042         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1043
1044         /* Displayport compliance testing */
1045         struct intel_dp_compliance compliance;
1046 };
1047
1048 struct intel_lspcon {
1049         bool active;
1050         enum drm_lspcon_mode mode;
1051 };
1052
1053 struct intel_digital_port {
1054         struct intel_encoder base;
1055         u32 saved_port_bits;
1056         struct intel_dp dp;
1057         struct intel_hdmi hdmi;
1058         struct intel_lspcon lspcon;
1059         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1060         bool release_cl2_override;
1061         uint8_t max_lanes;
1062         enum intel_display_power_domain ddi_io_power_domain;
1063
1064         void (*write_infoframe)(struct drm_encoder *encoder,
1065                                 const struct intel_crtc_state *crtc_state,
1066                                 unsigned int type,
1067                                 const void *frame, ssize_t len);
1068         void (*set_infoframes)(struct drm_encoder *encoder,
1069                                bool enable,
1070                                const struct intel_crtc_state *crtc_state,
1071                                const struct drm_connector_state *conn_state);
1072         bool (*infoframe_enabled)(struct drm_encoder *encoder,
1073                                   const struct intel_crtc_state *pipe_config);
1074 };
1075
1076 struct intel_dp_mst_encoder {
1077         struct intel_encoder base;
1078         enum pipe pipe;
1079         struct intel_digital_port *primary;
1080         struct intel_connector *connector;
1081 };
1082
1083 static inline enum dpio_channel
1084 vlv_dport_to_channel(struct intel_digital_port *dport)
1085 {
1086         switch (dport->base.port) {
1087         case PORT_B:
1088         case PORT_D:
1089                 return DPIO_CH0;
1090         case PORT_C:
1091                 return DPIO_CH1;
1092         default:
1093                 BUG();
1094         }
1095 }
1096
1097 static inline enum dpio_phy
1098 vlv_dport_to_phy(struct intel_digital_port *dport)
1099 {
1100         switch (dport->base.port) {
1101         case PORT_B:
1102         case PORT_C:
1103                 return DPIO_PHY0;
1104         case PORT_D:
1105                 return DPIO_PHY1;
1106         default:
1107                 BUG();
1108         }
1109 }
1110
1111 static inline enum dpio_channel
1112 vlv_pipe_to_channel(enum pipe pipe)
1113 {
1114         switch (pipe) {
1115         case PIPE_A:
1116         case PIPE_C:
1117                 return DPIO_CH0;
1118         case PIPE_B:
1119                 return DPIO_CH1;
1120         default:
1121                 BUG();
1122         }
1123 }
1124
1125 static inline struct intel_crtc *
1126 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1127 {
1128         return dev_priv->pipe_to_crtc_mapping[pipe];
1129 }
1130
1131 static inline struct intel_crtc *
1132 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum plane plane)
1133 {
1134         return dev_priv->plane_to_crtc_mapping[plane];
1135 }
1136
1137 struct intel_load_detect_pipe {
1138         struct drm_atomic_state *restore_state;
1139 };
1140
1141 static inline struct intel_encoder *
1142 intel_attached_encoder(struct drm_connector *connector)
1143 {
1144         return to_intel_connector(connector)->encoder;
1145 }
1146
1147 static inline struct intel_digital_port *
1148 enc_to_dig_port(struct drm_encoder *encoder)
1149 {
1150         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1151
1152         switch (intel_encoder->type) {
1153         case INTEL_OUTPUT_DDI:
1154                 WARN_ON(!HAS_DDI(to_i915(encoder->dev)));
1155         case INTEL_OUTPUT_DP:
1156         case INTEL_OUTPUT_EDP:
1157         case INTEL_OUTPUT_HDMI:
1158                 return container_of(encoder, struct intel_digital_port,
1159                                     base.base);
1160         default:
1161                 return NULL;
1162         }
1163 }
1164
1165 static inline struct intel_dp_mst_encoder *
1166 enc_to_mst(struct drm_encoder *encoder)
1167 {
1168         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1169 }
1170
1171 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1172 {
1173         return &enc_to_dig_port(encoder)->dp;
1174 }
1175
1176 static inline struct intel_digital_port *
1177 dp_to_dig_port(struct intel_dp *intel_dp)
1178 {
1179         return container_of(intel_dp, struct intel_digital_port, dp);
1180 }
1181
1182 static inline struct intel_lspcon *
1183 dp_to_lspcon(struct intel_dp *intel_dp)
1184 {
1185         return &dp_to_dig_port(intel_dp)->lspcon;
1186 }
1187
1188 static inline struct intel_digital_port *
1189 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1190 {
1191         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1192 }
1193
1194 static inline struct intel_plane_state *
1195 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1196                                  struct intel_plane *plane)
1197 {
1198         return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1199                                                                    &plane->base));
1200 }
1201
1202 static inline struct intel_crtc_state *
1203 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1204                                 struct intel_crtc *crtc)
1205 {
1206         return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1207                                                                  &crtc->base));
1208 }
1209
1210 static inline struct intel_crtc_state *
1211 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1212                                 struct intel_crtc *crtc)
1213 {
1214         return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1215                                                                  &crtc->base));
1216 }
1217
1218 /* intel_fifo_underrun.c */
1219 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1220                                            enum pipe pipe, bool enable);
1221 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1222                                            enum pipe pch_transcoder,
1223                                            bool enable);
1224 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1225                                          enum pipe pipe);
1226 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1227                                          enum pipe pch_transcoder);
1228 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1229 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1230
1231 /* i915_irq.c */
1232 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1233 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1234 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1235 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1236 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1237 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1238 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1239
1240 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1241                                             u32 mask)
1242 {
1243         return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
1244 }
1245
1246 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1247 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1248 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1249 {
1250         /*
1251          * We only use drm_irq_uninstall() at unload and VT switch, so
1252          * this is the only thing we need to check.
1253          */
1254         return dev_priv->runtime_pm.irqs_enabled;
1255 }
1256
1257 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1258 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1259                                      u8 pipe_mask);
1260 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1261                                      u8 pipe_mask);
1262 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1263 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1264 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1265
1266 /* intel_crt.c */
1267 void intel_crt_init(struct drm_i915_private *dev_priv);
1268 void intel_crt_reset(struct drm_encoder *encoder);
1269
1270 /* intel_ddi.c */
1271 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1272                                 const struct intel_crtc_state *old_crtc_state,
1273                                 const struct drm_connector_state *old_conn_state);
1274 void hsw_fdi_link_train(struct intel_crtc *crtc,
1275                         const struct intel_crtc_state *crtc_state);
1276 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1277 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1278 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1279 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1280                                        enum transcoder cpu_transcoder);
1281 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1282 void intel_ddi_disable_pipe_clock(const  struct intel_crtc_state *crtc_state);
1283 struct intel_encoder *
1284 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1285 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1286 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1287 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1288 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
1289                                  struct intel_crtc *intel_crtc);
1290 void intel_ddi_get_config(struct intel_encoder *encoder,
1291                           struct intel_crtc_state *pipe_config);
1292
1293 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1294                                     bool state);
1295 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
1296                                          struct intel_crtc_state *crtc_state);
1297 u32 bxt_signal_levels(struct intel_dp *intel_dp);
1298 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1299 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1300
1301 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1302                                    int plane, unsigned int height);
1303
1304 /* intel_audio.c */
1305 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1306 void intel_audio_codec_enable(struct intel_encoder *encoder,
1307                               const struct intel_crtc_state *crtc_state,
1308                               const struct drm_connector_state *conn_state);
1309 void intel_audio_codec_disable(struct intel_encoder *encoder,
1310                                const struct intel_crtc_state *old_crtc_state,
1311                                const struct drm_connector_state *old_conn_state);
1312 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1313 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1314 void intel_audio_init(struct drm_i915_private *dev_priv);
1315 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1316
1317 /* intel_cdclk.c */
1318 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
1319 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1320 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1321 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
1322 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1323 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1324 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1325 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1326 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1327 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1328 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1329 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
1330                                const struct intel_cdclk_state *b);
1331 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
1332                          const struct intel_cdclk_state *b);
1333 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1334                      const struct intel_cdclk_state *cdclk_state);
1335 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
1336                             const char *context);
1337
1338 /* intel_display.c */
1339 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1340 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1341 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1342 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1343 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1344 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1345                       const char *name, u32 reg, int ref_freq);
1346 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1347                            const char *name, u32 reg);
1348 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1349 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1350 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1351 unsigned int intel_fb_xy_to_linear(int x, int y,
1352                                    const struct intel_plane_state *state,
1353                                    int plane);
1354 void intel_add_fb_offsets(int *x, int *y,
1355                           const struct intel_plane_state *state, int plane);
1356 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1357 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1358 void intel_mark_busy(struct drm_i915_private *dev_priv);
1359 void intel_mark_idle(struct drm_i915_private *dev_priv);
1360 int intel_display_suspend(struct drm_device *dev);
1361 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1362 void intel_encoder_destroy(struct drm_encoder *encoder);
1363 int intel_connector_init(struct intel_connector *);
1364 struct intel_connector *intel_connector_alloc(void);
1365 void intel_connector_free(struct intel_connector *connector);
1366 bool intel_connector_get_hw_state(struct intel_connector *connector);
1367 void intel_connector_attach_encoder(struct intel_connector *connector,
1368                                     struct intel_encoder *encoder);
1369 struct drm_display_mode *
1370 intel_encoder_current_mode(struct intel_encoder *encoder);
1371
1372 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1373 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1374                                 struct drm_file *file_priv);
1375 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1376                                              enum pipe pipe);
1377 static inline bool
1378 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1379                     enum intel_output_type type)
1380 {
1381         return crtc_state->output_types & (1 << type);
1382 }
1383 static inline bool
1384 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1385 {
1386         return crtc_state->output_types &
1387                 ((1 << INTEL_OUTPUT_DP) |
1388                  (1 << INTEL_OUTPUT_DP_MST) |
1389                  (1 << INTEL_OUTPUT_EDP));
1390 }
1391 static inline void
1392 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1393 {
1394         drm_wait_one_vblank(&dev_priv->drm, pipe);
1395 }
1396 static inline void
1397 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1398 {
1399         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1400
1401         if (crtc->active)
1402                 intel_wait_for_vblank(dev_priv, pipe);
1403 }
1404
1405 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1406
1407 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1408 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1409                          struct intel_digital_port *dport,
1410                          unsigned int expected_mask);
1411 int intel_get_load_detect_pipe(struct drm_connector *connector,
1412                                const struct drm_display_mode *mode,
1413                                struct intel_load_detect_pipe *old,
1414                                struct drm_modeset_acquire_ctx *ctx);
1415 void intel_release_load_detect_pipe(struct drm_connector *connector,
1416                                     struct intel_load_detect_pipe *old,
1417                                     struct drm_modeset_acquire_ctx *ctx);
1418 struct i915_vma *
1419 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1420 void intel_unpin_fb_vma(struct i915_vma *vma);
1421 struct drm_framebuffer *
1422 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1423                          struct drm_mode_fb_cmd2 *mode_cmd);
1424 int intel_prepare_plane_fb(struct drm_plane *plane,
1425                            struct drm_plane_state *new_state);
1426 void intel_cleanup_plane_fb(struct drm_plane *plane,
1427                             struct drm_plane_state *old_state);
1428 int intel_plane_atomic_get_property(struct drm_plane *plane,
1429                                     const struct drm_plane_state *state,
1430                                     struct drm_property *property,
1431                                     uint64_t *val);
1432 int intel_plane_atomic_set_property(struct drm_plane *plane,
1433                                     struct drm_plane_state *state,
1434                                     struct drm_property *property,
1435                                     uint64_t val);
1436 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
1437                                     struct drm_crtc_state *crtc_state,
1438                                     const struct intel_plane_state *old_plane_state,
1439                                     struct drm_plane_state *plane_state);
1440
1441 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1442                                     enum pipe pipe);
1443
1444 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1445                      const struct dpll *dpll);
1446 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1447 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1448
1449 /* modesetting asserts */
1450 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1451                            enum pipe pipe);
1452 void assert_pll(struct drm_i915_private *dev_priv,
1453                 enum pipe pipe, bool state);
1454 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1455 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1456 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1457 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1458 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1459 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1460                        enum pipe pipe, bool state);
1461 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1462 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1463 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1464 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1465 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1466 u32 intel_compute_tile_offset(int *x, int *y,
1467                               const struct intel_plane_state *state, int plane);
1468 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1469 void intel_finish_reset(struct drm_i915_private *dev_priv);
1470 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1471 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1472 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1473 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1474 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1475 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1476 unsigned int skl_cdclk_get_vco(unsigned int freq);
1477 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1478 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1479 void intel_dp_get_m_n(struct intel_crtc *crtc,
1480                       struct intel_crtc_state *pipe_config);
1481 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1482 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1483 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1484                         struct dpll *best_clock);
1485 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1486
1487 bool intel_crtc_active(struct intel_crtc *crtc);
1488 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
1489 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
1490 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1491 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1492                                  struct intel_crtc_state *pipe_config);
1493
1494 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1495 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1496
1497 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1498 {
1499         return i915_ggtt_offset(state->vma);
1500 }
1501
1502 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1503                         const struct intel_plane_state *plane_state);
1504 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1505                   const struct intel_plane_state *plane_state);
1506 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1507                      unsigned int rotation);
1508 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1509 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1510
1511 /* intel_csr.c */
1512 void intel_csr_ucode_init(struct drm_i915_private *);
1513 void intel_csr_load_program(struct drm_i915_private *);
1514 void intel_csr_ucode_fini(struct drm_i915_private *);
1515 void intel_csr_ucode_suspend(struct drm_i915_private *);
1516 void intel_csr_ucode_resume(struct drm_i915_private *);
1517
1518 /* intel_dp.c */
1519 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1520                    enum port port);
1521 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1522                              struct intel_connector *intel_connector);
1523 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1524                               int link_rate, uint8_t lane_count,
1525                               bool link_mst);
1526 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1527                                             int link_rate, uint8_t lane_count);
1528 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1529 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1530 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1531 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1532 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1533 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1534 int intel_dp_sink_crc(struct intel_dp *intel_dp,
1535                       struct intel_crtc_state *crtc_state, u8 *crc);
1536 bool intel_dp_compute_config(struct intel_encoder *encoder,
1537                              struct intel_crtc_state *pipe_config,
1538                              struct drm_connector_state *conn_state);
1539 bool intel_dp_is_edp(struct intel_dp *intel_dp);
1540 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
1541 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1542                                   bool long_hpd);
1543 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1544                             const struct drm_connector_state *conn_state);
1545 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1546 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1547 void intel_edp_panel_on(struct intel_dp *intel_dp);
1548 void intel_edp_panel_off(struct intel_dp *intel_dp);
1549 void intel_dp_mst_suspend(struct drm_device *dev);
1550 void intel_dp_mst_resume(struct drm_device *dev);
1551 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1552 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1553 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1554 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1555 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1556 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1557 void intel_plane_destroy(struct drm_plane *plane);
1558 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1559                            const struct intel_crtc_state *crtc_state);
1560 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1561                             const struct intel_crtc_state *crtc_state);
1562 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1563                                unsigned int frontbuffer_bits);
1564 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1565                           unsigned int frontbuffer_bits);
1566
1567 void
1568 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1569                                        uint8_t dp_train_pat);
1570 void
1571 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1572 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1573 uint8_t
1574 intel_dp_voltage_max(struct intel_dp *intel_dp);
1575 uint8_t
1576 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1577 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1578                            uint8_t *link_bw, uint8_t *rate_select);
1579 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1580 bool
1581 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1582
1583 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1584 {
1585         return ~((1 << lane_count) - 1) & 0xf;
1586 }
1587
1588 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1589 int intel_dp_link_required(int pixel_clock, int bpp);
1590 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1591 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1592                                   struct intel_digital_port *port);
1593
1594 /* intel_dp_aux_backlight.c */
1595 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1596
1597 /* intel_dp_mst.c */
1598 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1599 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1600 /* intel_dsi.c */
1601 void intel_dsi_init(struct drm_i915_private *dev_priv);
1602
1603 /* intel_dsi_dcs_backlight.c */
1604 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1605
1606 /* intel_dvo.c */
1607 void intel_dvo_init(struct drm_i915_private *dev_priv);
1608 /* intel_hotplug.c */
1609 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1610
1611
1612 /* legacy fbdev emulation in intel_fbdev.c */
1613 #ifdef CONFIG_DRM_FBDEV_EMULATION
1614 extern int intel_fbdev_init(struct drm_device *dev);
1615 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1616 extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
1617 extern void intel_fbdev_fini(struct drm_i915_private *dev_priv);
1618 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1619 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1620 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1621 #else
1622 static inline int intel_fbdev_init(struct drm_device *dev)
1623 {
1624         return 0;
1625 }
1626
1627 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1628 {
1629 }
1630
1631 static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
1632 {
1633 }
1634
1635 static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv)
1636 {
1637 }
1638
1639 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1640 {
1641 }
1642
1643 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1644 {
1645 }
1646
1647 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1648 {
1649 }
1650 #endif
1651
1652 /* intel_fbc.c */
1653 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1654                            struct drm_atomic_state *state);
1655 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1656 void intel_fbc_pre_update(struct intel_crtc *crtc,
1657                           struct intel_crtc_state *crtc_state,
1658                           struct intel_plane_state *plane_state);
1659 void intel_fbc_post_update(struct intel_crtc *crtc);
1660 void intel_fbc_init(struct drm_i915_private *dev_priv);
1661 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1662 void intel_fbc_enable(struct intel_crtc *crtc,
1663                       struct intel_crtc_state *crtc_state,
1664                       struct intel_plane_state *plane_state);
1665 void intel_fbc_disable(struct intel_crtc *crtc);
1666 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1667 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1668                           unsigned int frontbuffer_bits,
1669                           enum fb_op_origin origin);
1670 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1671                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1672 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1673 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1674
1675 /* intel_hdmi.c */
1676 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1677                      enum port port);
1678 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1679                                struct intel_connector *intel_connector);
1680 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1681 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1682                                struct intel_crtc_state *pipe_config,
1683                                struct drm_connector_state *conn_state);
1684 void intel_hdmi_handle_sink_scrambling(struct intel_encoder *intel_encoder,
1685                                        struct drm_connector *connector,
1686                                        bool high_tmds_clock_ratio,
1687                                        bool scrambling);
1688 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1689 void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
1690
1691
1692 /* intel_lvds.c */
1693 void intel_lvds_init(struct drm_i915_private *dev_priv);
1694 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1695 bool intel_is_dual_link_lvds(struct drm_device *dev);
1696
1697
1698 /* intel_modes.c */
1699 int intel_connector_update_modes(struct drm_connector *connector,
1700                                  struct edid *edid);
1701 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1702 void intel_attach_force_audio_property(struct drm_connector *connector);
1703 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1704 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1705
1706
1707 /* intel_overlay.c */
1708 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1709 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1710 int intel_overlay_switch_off(struct intel_overlay *overlay);
1711 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1712                                   struct drm_file *file_priv);
1713 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1714                               struct drm_file *file_priv);
1715 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1716
1717
1718 /* intel_panel.c */
1719 int intel_panel_init(struct intel_panel *panel,
1720                      struct drm_display_mode *fixed_mode,
1721                      struct drm_display_mode *alt_fixed_mode,
1722                      struct drm_display_mode *downclock_mode);
1723 void intel_panel_fini(struct intel_panel *panel);
1724 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1725                             struct drm_display_mode *adjusted_mode);
1726 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1727                              struct intel_crtc_state *pipe_config,
1728                              int fitting_mode);
1729 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1730                               struct intel_crtc_state *pipe_config,
1731                               int fitting_mode);
1732 void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
1733                                     u32 level, u32 max);
1734 int intel_panel_setup_backlight(struct drm_connector *connector,
1735                                 enum pipe pipe);
1736 void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
1737                                   const struct drm_connector_state *conn_state);
1738 void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
1739 void intel_panel_destroy_backlight(struct drm_connector *connector);
1740 enum drm_connector_status intel_panel_detect(struct drm_i915_private *dev_priv);
1741 extern struct drm_display_mode *intel_find_panel_downclock(
1742                                 struct drm_i915_private *dev_priv,
1743                                 struct drm_display_mode *fixed_mode,
1744                                 struct drm_connector *connector);
1745
1746 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1747 int intel_backlight_device_register(struct intel_connector *connector);
1748 void intel_backlight_device_unregister(struct intel_connector *connector);
1749 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1750 static inline int intel_backlight_device_register(struct intel_connector *connector)
1751 {
1752         return 0;
1753 }
1754 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1755 {
1756 }
1757 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1758
1759
1760 /* intel_psr.c */
1761 void intel_psr_enable(struct intel_dp *intel_dp,
1762                       const struct intel_crtc_state *crtc_state);
1763 void intel_psr_disable(struct intel_dp *intel_dp,
1764                       const struct intel_crtc_state *old_crtc_state);
1765 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1766                           unsigned frontbuffer_bits);
1767 void intel_psr_flush(struct drm_i915_private *dev_priv,
1768                      unsigned frontbuffer_bits,
1769                      enum fb_op_origin origin);
1770 void intel_psr_init(struct drm_i915_private *dev_priv);
1771 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1772                                    unsigned frontbuffer_bits);
1773 void intel_psr_compute_config(struct intel_dp *intel_dp,
1774                               struct intel_crtc_state *crtc_state);
1775
1776 /* intel_runtime_pm.c */
1777 int intel_power_domains_init(struct drm_i915_private *);
1778 void intel_power_domains_fini(struct drm_i915_private *);
1779 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1780 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1781 void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
1782 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1783 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1784 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1785 const char *
1786 intel_display_power_domain_str(enum intel_display_power_domain domain);
1787
1788 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1789                                     enum intel_display_power_domain domain);
1790 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1791                                       enum intel_display_power_domain domain);
1792 void intel_display_power_get(struct drm_i915_private *dev_priv,
1793                              enum intel_display_power_domain domain);
1794 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1795                                         enum intel_display_power_domain domain);
1796 void intel_display_power_put(struct drm_i915_private *dev_priv,
1797                              enum intel_display_power_domain domain);
1798
1799 static inline void
1800 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1801 {
1802         WARN_ONCE(dev_priv->runtime_pm.suspended,
1803                   "Device suspended during HW access\n");
1804 }
1805
1806 static inline void
1807 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1808 {
1809         assert_rpm_device_not_suspended(dev_priv);
1810         WARN_ONCE(!atomic_read(&dev_priv->runtime_pm.wakeref_count),
1811                   "RPM wakelock ref not held during HW access");
1812 }
1813
1814 /**
1815  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1816  * @dev_priv: i915 device instance
1817  *
1818  * This function disable asserts that check if we hold an RPM wakelock
1819  * reference, while keeping the device-not-suspended checks still enabled.
1820  * It's meant to be used only in special circumstances where our rule about
1821  * the wakelock refcount wrt. the device power state doesn't hold. According
1822  * to this rule at any point where we access the HW or want to keep the HW in
1823  * an active state we must hold an RPM wakelock reference acquired via one of
1824  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1825  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1826  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1827  * users should avoid using this function.
1828  *
1829  * Any calls to this function must have a symmetric call to
1830  * enable_rpm_wakeref_asserts().
1831  */
1832 static inline void
1833 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1834 {
1835         atomic_inc(&dev_priv->runtime_pm.wakeref_count);
1836 }
1837
1838 /**
1839  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1840  * @dev_priv: i915 device instance
1841  *
1842  * This function re-enables the RPM assert checks after disabling them with
1843  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1844  * circumstances otherwise its use should be avoided.
1845  *
1846  * Any calls to this function must have a symmetric call to
1847  * disable_rpm_wakeref_asserts().
1848  */
1849 static inline void
1850 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1851 {
1852         atomic_dec(&dev_priv->runtime_pm.wakeref_count);
1853 }
1854
1855 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1856 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1857 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1858 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1859
1860 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1861
1862 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1863                              bool override, unsigned int mask);
1864 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1865                           enum dpio_channel ch, bool override);
1866
1867
1868 /* intel_pm.c */
1869 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
1870 void intel_suspend_hw(struct drm_i915_private *dev_priv);
1871 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
1872 void intel_update_watermarks(struct intel_crtc *crtc);
1873 void intel_init_pm(struct drm_i915_private *dev_priv);
1874 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1875 void intel_pm_setup(struct drm_i915_private *dev_priv);
1876 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1877 void intel_gpu_ips_teardown(void);
1878 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1879 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1880 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1881 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1882 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1883 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1884 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1885 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1886 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1887 void gen6_rps_boost(struct drm_i915_gem_request *rq,
1888                     struct intel_rps_client *rps);
1889 void g4x_wm_get_hw_state(struct drm_device *dev);
1890 void vlv_wm_get_hw_state(struct drm_device *dev);
1891 void ilk_wm_get_hw_state(struct drm_device *dev);
1892 void skl_wm_get_hw_state(struct drm_device *dev);
1893 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1894                           struct skl_ddb_allocation *ddb /* out */);
1895 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
1896                               struct skl_pipe_wm *out);
1897 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
1898 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
1899 bool intel_can_enable_sagv(struct drm_atomic_state *state);
1900 int intel_enable_sagv(struct drm_i915_private *dev_priv);
1901 int intel_disable_sagv(struct drm_i915_private *dev_priv);
1902 bool skl_wm_level_equals(const struct skl_wm_level *l1,
1903                          const struct skl_wm_level *l2);
1904 bool skl_ddb_allocation_overlaps(struct drm_i915_private *dev_priv,
1905                                  const struct skl_ddb_entry **entries,
1906                                  const struct skl_ddb_entry *ddb,
1907                                  int ignore);
1908 bool ilk_disable_lp_wm(struct drm_device *dev);
1909 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1910 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
1911                                   struct intel_crtc_state *cstate);
1912 void intel_init_ipc(struct drm_i915_private *dev_priv);
1913 void intel_enable_ipc(struct drm_i915_private *dev_priv);
1914 static inline int intel_rc6_enabled(void)
1915 {
1916         return i915_modparams.enable_rc6;
1917 }
1918
1919 /* intel_sdvo.c */
1920 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
1921                      i915_reg_t reg, enum port port);
1922
1923
1924 /* intel_sprite.c */
1925 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
1926                              int usecs);
1927 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1928                                               enum pipe pipe, int plane);
1929 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1930                               struct drm_file *file_priv);
1931 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
1932 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
1933 void skl_update_plane(struct intel_plane *plane,
1934                       const struct intel_crtc_state *crtc_state,
1935                       const struct intel_plane_state *plane_state);
1936 void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc);
1937
1938 /* intel_tv.c */
1939 void intel_tv_init(struct drm_i915_private *dev_priv);
1940
1941 /* intel_atomic.c */
1942 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
1943                                                 const struct drm_connector_state *state,
1944                                                 struct drm_property *property,
1945                                                 uint64_t *val);
1946 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
1947                                                 struct drm_connector_state *state,
1948                                                 struct drm_property *property,
1949                                                 uint64_t val);
1950 int intel_digital_connector_atomic_check(struct drm_connector *conn,
1951                                          struct drm_connector_state *new_state);
1952 struct drm_connector_state *
1953 intel_digital_connector_duplicate_state(struct drm_connector *connector);
1954
1955 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1956 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1957                                struct drm_crtc_state *state);
1958 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1959 void intel_atomic_state_clear(struct drm_atomic_state *);
1960
1961 static inline struct intel_crtc_state *
1962 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1963                             struct intel_crtc *crtc)
1964 {
1965         struct drm_crtc_state *crtc_state;
1966         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1967         if (IS_ERR(crtc_state))
1968                 return ERR_CAST(crtc_state);
1969
1970         return to_intel_crtc_state(crtc_state);
1971 }
1972
1973 static inline struct intel_crtc_state *
1974 intel_atomic_get_existing_crtc_state(struct drm_atomic_state *state,
1975                                      struct intel_crtc *crtc)
1976 {
1977         struct drm_crtc_state *crtc_state;
1978
1979         crtc_state = drm_atomic_get_existing_crtc_state(state, &crtc->base);
1980
1981         if (crtc_state)
1982                 return to_intel_crtc_state(crtc_state);
1983         else
1984                 return NULL;
1985 }
1986
1987 static inline struct intel_plane_state *
1988 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1989                                       struct intel_plane *plane)
1990 {
1991         struct drm_plane_state *plane_state;
1992
1993         plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1994
1995         return to_intel_plane_state(plane_state);
1996 }
1997
1998 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
1999                                struct intel_crtc *intel_crtc,
2000                                struct intel_crtc_state *crtc_state);
2001
2002 /* intel_atomic_plane.c */
2003 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
2004 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
2005 void intel_plane_destroy_state(struct drm_plane *plane,
2006                                struct drm_plane_state *state);
2007 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
2008 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
2009                                         struct intel_crtc_state *crtc_state,
2010                                         const struct intel_plane_state *old_plane_state,
2011                                         struct intel_plane_state *intel_state);
2012
2013 /* intel_color.c */
2014 void intel_color_init(struct drm_crtc *crtc);
2015 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
2016 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
2017 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
2018
2019 /* intel_lspcon.c */
2020 bool lspcon_init(struct intel_digital_port *intel_dig_port);
2021 void lspcon_resume(struct intel_lspcon *lspcon);
2022 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
2023
2024 /* intel_pipe_crc.c */
2025 int intel_pipe_crc_create(struct drm_minor *minor);
2026 #ifdef CONFIG_DEBUG_FS
2027 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
2028                               size_t *values_cnt);
2029 #else
2030 #define intel_crtc_set_crc_source NULL
2031 #endif
2032 extern const struct file_operations i915_display_crc_ctl_fops;
2033 #endif /* __INTEL_DRV_H__ */