drivers/gpu/drm/i915/intel_display.h

   1 /*
   2  * Copyright © 2006-2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #ifndef _INTEL_DISPLAY_H_
  26 #define _INTEL_DISPLAY_H_
  27
  28 enum i915_gpio {
  29         GPIOA,
  30         GPIOB,
  31         GPIOC,
  32         GPIOD,
  33         GPIOE,
  34         GPIOF,
  35         GPIOG,
  36         GPIOH,
  37         __GPIOI_UNUSED,
  38         GPIOJ,
  39         GPIOK,
  40         GPIOL,
  41         GPIOM,
  42 };
  43
  44 enum pipe {
  45         INVALID_PIPE = -1,
  46
  47         PIPE_A = 0,
  48         PIPE_B,
  49         PIPE_C,
  50         _PIPE_EDP,
  51
  52         I915_MAX_PIPES = _PIPE_EDP
  53 };
  54
  55 #define pipe_name(p) ((p) + 'A')
  56
  57 enum transcoder {
  58         TRANSCODER_A = 0,
  59         TRANSCODER_B,
  60         TRANSCODER_C,
  61         TRANSCODER_EDP,
  62         TRANSCODER_DSI_A,
  63         TRANSCODER_DSI_C,
  64
  65         I915_MAX_TRANSCODERS
  66 };
  67
  68 static inline const char *transcoder_name(enum transcoder transcoder)
  69 {
  70         switch (transcoder) {
  71         case TRANSCODER_A:
  72                 return "A";
  73         case TRANSCODER_B:
  74                 return "B";
  75         case TRANSCODER_C:
  76                 return "C";
  77         case TRANSCODER_EDP:
  78                 return "EDP";
  79         case TRANSCODER_DSI_A:
  80                 return "DSI A";
  81         case TRANSCODER_DSI_C:
  82                 return "DSI C";
  83         default:
  84                 return "<invalid>";
  85         }
  86 }
  87
  88 static inline bool transcoder_is_dsi(enum transcoder transcoder)
  89 {
  90         return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
  91 }
  92
  93 /*
  94  * Global legacy plane identifier. Valid only for primary/sprite
  95  * planes on pre-g4x, and only for primary planes on g4x-bdw.
  96  */
  97 enum i9xx_plane_id {
  98         PLANE_A,
  99         PLANE_B,
 100         PLANE_C,
 101 };
 102
 103 #define plane_name(p) ((p) + 'A')
 104 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
 105
 106 /*
 107  * Per-pipe plane identifier.
 108  * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
 109  * number of planes per CRTC.  Not all platforms really have this many planes,
 110  * which means some arrays of size I915_MAX_PLANES may have unused entries
 111  * between the topmost sprite plane and the cursor plane.
 112  *
 113  * This is expected to be passed to various register macros
 114  * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
 115  */
 116 enum plane_id {
 117         PLANE_PRIMARY,
 118         PLANE_SPRITE0,
 119         PLANE_SPRITE1,
 120         PLANE_SPRITE2,
 121         PLANE_CURSOR,
 122
 123         I915_MAX_PLANES,
 124 };
 125
 126 #define for_each_plane_id_on_crtc(__crtc, __p) \
 127         for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
 128                 for_each_if((__crtc)->plane_ids_mask & BIT(__p))
 129
 130 enum port {
 131         PORT_NONE = -1,
 132
 133         PORT_A = 0,
 134         PORT_B,
 135         PORT_C,
 136         PORT_D,
 137         PORT_E,
 138         PORT_F,
 139
 140         I915_MAX_PORTS
 141 };
 142
 143 #define port_name(p) ((p) + 'A')
 144
 145 /*
 146  * Ports identifier referenced from other drivers.
 147  * Expected to remain stable over time
 148  */
 149 static inline const char *port_identifier(enum port port)
 150 {
 151         switch (port) {
 152         case PORT_A:
 153                 return "Port A";
 154         case PORT_B:
 155                 return "Port B";
 156         case PORT_C:
 157                 return "Port C";
 158         case PORT_D:
 159                 return "Port D";
 160         case PORT_E:
 161                 return "Port E";
 162         case PORT_F:
 163                 return "Port F";
 164         default:
 165                 return "<invalid>";
 166         }
 167 }
 168
 169 enum tc_port {
 170         PORT_TC_NONE = -1,
 171
 172         PORT_TC1 = 0,
 173         PORT_TC2,
 174         PORT_TC3,
 175         PORT_TC4,
 176
 177         I915_MAX_TC_PORTS
 178 };
 179
 180 enum tc_port_type {
 181         TC_PORT_UNKNOWN = 0,
 182         TC_PORT_TYPEC,
 183         TC_PORT_TBT,
 184         TC_PORT_LEGACY,
 185 };
 186
 187 enum dpio_channel {
 188         DPIO_CH0,
 189         DPIO_CH1
 190 };
 191
 192 enum dpio_phy {
 193         DPIO_PHY0,
 194         DPIO_PHY1,
 195         DPIO_PHY2,
 196 };
 197
 198 #define I915_NUM_PHYS_VLV 2
 199
 200 enum aux_ch {
 201         AUX_CH_A,
 202         AUX_CH_B,
 203         AUX_CH_C,
 204         AUX_CH_D,
 205         AUX_CH_E, /* ICL+ */
 206         AUX_CH_F,
 207 };
 208
 209 #define aux_ch_name(a) ((a) + 'A')
 210
 211 enum intel_display_power_domain {
 212         POWER_DOMAIN_PIPE_A,
 213         POWER_DOMAIN_PIPE_B,
 214         POWER_DOMAIN_PIPE_C,
 215         POWER_DOMAIN_PIPE_A_PANEL_FITTER,
 216         POWER_DOMAIN_PIPE_B_PANEL_FITTER,
 217         POWER_DOMAIN_PIPE_C_PANEL_FITTER,
 218         POWER_DOMAIN_TRANSCODER_A,
 219         POWER_DOMAIN_TRANSCODER_B,
 220         POWER_DOMAIN_TRANSCODER_C,
 221         POWER_DOMAIN_TRANSCODER_EDP,
 222         POWER_DOMAIN_TRANSCODER_DSI_A,
 223         POWER_DOMAIN_TRANSCODER_DSI_C,
 224         POWER_DOMAIN_PORT_DDI_A_LANES,
 225         POWER_DOMAIN_PORT_DDI_B_LANES,
 226         POWER_DOMAIN_PORT_DDI_C_LANES,
 227         POWER_DOMAIN_PORT_DDI_D_LANES,
 228         POWER_DOMAIN_PORT_DDI_E_LANES,
 229         POWER_DOMAIN_PORT_DDI_F_LANES,
 230         POWER_DOMAIN_PORT_DDI_A_IO,
 231         POWER_DOMAIN_PORT_DDI_B_IO,
 232         POWER_DOMAIN_PORT_DDI_C_IO,
 233         POWER_DOMAIN_PORT_DDI_D_IO,
 234         POWER_DOMAIN_PORT_DDI_E_IO,
 235         POWER_DOMAIN_PORT_DDI_F_IO,
 236         POWER_DOMAIN_PORT_DSI,
 237         POWER_DOMAIN_PORT_CRT,
 238         POWER_DOMAIN_PORT_OTHER,
 239         POWER_DOMAIN_VGA,
 240         POWER_DOMAIN_AUDIO,
 241         POWER_DOMAIN_PLLS,
 242         POWER_DOMAIN_AUX_A,
 243         POWER_DOMAIN_AUX_B,
 244         POWER_DOMAIN_AUX_C,
 245         POWER_DOMAIN_AUX_D,
 246         POWER_DOMAIN_AUX_E,
 247         POWER_DOMAIN_AUX_F,
 248         POWER_DOMAIN_AUX_IO_A,
 249         POWER_DOMAIN_AUX_TBT1,
 250         POWER_DOMAIN_AUX_TBT2,
 251         POWER_DOMAIN_AUX_TBT3,
 252         POWER_DOMAIN_AUX_TBT4,
 253         POWER_DOMAIN_GMBUS,
 254         POWER_DOMAIN_MODESET,
 255         POWER_DOMAIN_GT_IRQ,
 256         POWER_DOMAIN_INIT,
 257
 258         POWER_DOMAIN_NUM,
 259 };
 260
 261 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
 262 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
 263                 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
 264 #define POWER_DOMAIN_TRANSCODER(tran) \
 265         ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
 266          (tran) + POWER_DOMAIN_TRANSCODER_A)
 267
 268 /* Used by dp and fdi links */
 269 struct intel_link_m_n {
 270         u32 tu;
 271         u32 gmch_m;
 272         u32 gmch_n;
 273         u32 link_m;
 274         u32 link_n;
 275 };
 276
 277 #define for_each_pipe(__dev_priv, __p) \
 278         for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
 279
 280 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
 281         for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
 282                 for_each_if((__mask) & BIT(__p))
 283
 284 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
 285         for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++)  \
 286                 for_each_if ((__mask) & (1 << (__t)))
 287
 288 #define for_each_universal_plane(__dev_priv, __pipe, __p)               \
 289         for ((__p) = 0;                                                 \
 290              (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
 291              (__p)++)
 292
 293 #define for_each_sprite(__dev_priv, __p, __s)                           \
 294         for ((__s) = 0;                                                 \
 295              (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)];        \
 296              (__s)++)
 297
 298 #define for_each_port_masked(__port, __ports_mask) \
 299         for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)  \
 300                 for_each_if((__ports_mask) & BIT(__port))
 301
 302 #define for_each_crtc(dev, crtc) \
 303         list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
 304
 305 #define for_each_intel_plane(dev, intel_plane) \
 306         list_for_each_entry(intel_plane,                        \
 307                             &(dev)->mode_config.plane_list,     \
 308                             base.head)
 309
 310 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask)         \
 311         list_for_each_entry(intel_plane,                                \
 312                             &(dev)->mode_config.plane_list,             \
 313                             base.head)                                  \
 314                 for_each_if((plane_mask) &                              \
 315                             drm_plane_mask(&intel_plane->base)))
 316
 317 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)      \
 318         list_for_each_entry(intel_plane,                                \
 319                             &(dev)->mode_config.plane_list,             \
 320                             base.head)                                  \
 321                 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
 322
 323 #define for_each_intel_crtc(dev, intel_crtc)                            \
 324         list_for_each_entry(intel_crtc,                                 \
 325                             &(dev)->mode_config.crtc_list,              \
 326                             base.head)
 327
 328 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask)            \
 329         list_for_each_entry(intel_crtc,                                 \
 330                             &(dev)->mode_config.crtc_list,              \
 331                             base.head)                                  \
 332                 for_each_if((crtc_mask) & drm_crtc_mask(&intel_crtc->base))
 333
 334 #define for_each_intel_encoder(dev, intel_encoder)              \
 335         list_for_each_entry(intel_encoder,                      \
 336                             &(dev)->mode_config.encoder_list,   \
 337                             base.head)
 338
 339 #define for_each_intel_dp(dev, intel_encoder)                   \
 340         for_each_intel_encoder(dev, intel_encoder)              \
 341                 for_each_if(intel_encoder_is_dp(intel_encoder))
 342
 343 #define for_each_intel_connector_iter(intel_connector, iter) \
 344         while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
 345
 346 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
 347         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
 348                 for_each_if((intel_encoder)->base.crtc == (__crtc))
 349
 350 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
 351         list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
 352                 for_each_if((intel_connector)->base.encoder == (__encoder))
 353
 354 #define for_each_power_domain(domain, mask)                             \
 355         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
 356                 for_each_if(BIT_ULL(domain) & (mask))
 357
 358 #define for_each_power_well(__dev_priv, __power_well)                           \
 359         for ((__power_well) = (__dev_priv)->power_domains.power_wells;  \
 360              (__power_well) - (__dev_priv)->power_domains.power_wells < \
 361                 (__dev_priv)->power_domains.power_well_count;           \
 362              (__power_well)++)
 363
 364 #define for_each_power_well_rev(__dev_priv, __power_well)                       \
 365         for ((__power_well) = (__dev_priv)->power_domains.power_wells +         \
 366                               (__dev_priv)->power_domains.power_well_count - 1; \
 367              (__power_well) - (__dev_priv)->power_domains.power_wells >= 0;     \
 368              (__power_well)--)
 369
 370 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask)     \
 371         for_each_power_well(__dev_priv, __power_well)                           \
 372                 for_each_if((__power_well)->desc->domains & (__domain_mask))
 373
 374 #define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \
 375         for_each_power_well_rev(__dev_priv, __power_well)                       \
 376                 for_each_if((__power_well)->desc->domains & (__domain_mask))
 377
 378 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
 379         for ((__i) = 0; \
 380              (__i) < (__state)->base.dev->mode_config.num_total_plane && \
 381                      ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
 382                       (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
 383              (__i)++) \
 384                 for_each_if(plane)
 385
 386 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
 387         for ((__i) = 0; \
 388              (__i) < (__state)->base.dev->mode_config.num_crtc && \
 389                      ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
 390                       (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
 391              (__i)++) \
 392                 for_each_if(crtc)
 393
 394 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
 395         for ((__i) = 0; \
 396              (__i) < (__state)->base.dev->mode_config.num_total_plane && \
 397                      ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
 398                       (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
 399                       (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
 400              (__i)++) \
 401                 for_each_if(plane)
 402
 403 void intel_link_compute_m_n(int bpp, int nlanes,
 404                             int pixel_clock, int link_clock,
 405                             struct intel_link_m_n *m_n,
 406                             bool reduce_m_n);
 407
 408 bool is_ccs_modifier(u64 modifier);
 409 #endif