drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/circ_buf.h>
  32 #include <linux/slab.h>
  33 #include <linux/sysrq.h>
  34
  35 #include <drm/drm_drv.h>
  36 #include <drm/drm_irq.h>
  37
  38 #include "display/intel_display_types.h"
  39 #include "display/intel_fifo_underrun.h"
  40 #include "display/intel_hotplug.h"
  41 #include "display/intel_lpe_audio.h"
  42 #include "display/intel_psr.h"
  43
  44 #include "gt/intel_breadcrumbs.h"
  45 #include "gt/intel_gt.h"
  46 #include "gt/intel_gt_irq.h"
  47 #include "gt/intel_gt_pm_irq.h"
  48 #include "gt/intel_rps.h"
  49
  50 #include "i915_drv.h"
  51 #include "i915_irq.h"
  52 #include "i915_trace.h"
  53 #include "intel_pm.h"
  54
  55 /**
  56  * DOC: interrupt handling
  57  *
  58  * These functions provide the basic support for enabling and disabling the
  59  * interrupt handling support. There's a lot more functionality in i915_irq.c
  60  * and related files, but that will be described in separate chapters.
  61  */
  62
  63 typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val);
  64
  65 static const u32 hpd_ilk[HPD_NUM_PINS] = {
  66         [HPD_PORT_A] = DE_DP_A_HOTPLUG,
  67 };
  68
  69 static const u32 hpd_ivb[HPD_NUM_PINS] = {
  70         [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
  71 };
  72
  73 static const u32 hpd_bdw[HPD_NUM_PINS] = {
  74         [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
  75 };
  76
  77 static const u32 hpd_ibx[HPD_NUM_PINS] = {
  78         [HPD_CRT] = SDE_CRT_HOTPLUG,
  79         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  80         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  81         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  82         [HPD_PORT_D] = SDE_PORTD_HOTPLUG,
  83 };
  84
  85 static const u32 hpd_cpt[HPD_NUM_PINS] = {
  86         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  87         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  88         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  89         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  90         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
  91 };
  92
  93 static const u32 hpd_spt[HPD_NUM_PINS] = {
  94         [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
  95         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  96         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  97         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
  98         [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT,
  99 };
 100
 101 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
 102         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
 103         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
 104         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
 105         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
 106         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
 107         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN,
 108 };
 109
 110 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
 111         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
 112         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
 113         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
 114         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
 115         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
 116         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
 117 };
 118
 119 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
 120         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
 121         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
 122         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
 123         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
 124         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
 125         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
 126 };
 127
 128 static const u32 hpd_bxt[HPD_NUM_PINS] = {
 129         [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
 130         [HPD_PORT_B] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_B),
 131         [HPD_PORT_C] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_C),
 132 };
 133
 134 static const u32 hpd_gen11[HPD_NUM_PINS] = {
 135         [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(TC_PORT_1) | GEN11_TBT_HOTPLUG(TC_PORT_1),
 136         [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(TC_PORT_2) | GEN11_TBT_HOTPLUG(TC_PORT_2),
 137         [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(TC_PORT_3) | GEN11_TBT_HOTPLUG(TC_PORT_3),
 138         [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(TC_PORT_4) | GEN11_TBT_HOTPLUG(TC_PORT_4),
 139         [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(TC_PORT_5) | GEN11_TBT_HOTPLUG(TC_PORT_5),
 140         [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(TC_PORT_6) | GEN11_TBT_HOTPLUG(TC_PORT_6),
 141 };
 142
 143 static const u32 hpd_icp[HPD_NUM_PINS] = {
 144         [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
 145         [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
 146         [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PORT_C),
 147         [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(TC_PORT_1),
 148         [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(TC_PORT_2),
 149         [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(TC_PORT_3),
 150         [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(TC_PORT_4),
 151         [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(TC_PORT_5),
 152         [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(TC_PORT_6),
 153 };
 154
 155 static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
 156         [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
 157         [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
 158         [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PORT_C),
 159         [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(PORT_D),
 160 };
 161
 162 static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
 163 {
 164         struct i915_hotplug *hpd = &dev_priv->hotplug;
 165
 166         if (HAS_GMCH(dev_priv)) {
 167                 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
 168                     IS_CHERRYVIEW(dev_priv))
 169                         hpd->hpd = hpd_status_g4x;
 170                 else
 171                         hpd->hpd = hpd_status_i915;
 172                 return;
 173         }
 174
 175         if (INTEL_GEN(dev_priv) >= 11)
 176                 hpd->hpd = hpd_gen11;
 177         else if (IS_GEN9_LP(dev_priv))
 178                 hpd->hpd = hpd_bxt;
 179         else if (INTEL_GEN(dev_priv) >= 8)
 180                 hpd->hpd = hpd_bdw;
 181         else if (INTEL_GEN(dev_priv) >= 7)
 182                 hpd->hpd = hpd_ivb;
 183         else
 184                 hpd->hpd = hpd_ilk;
 185
 186         if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) &&
 187             (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
 188                 return;
 189
 190         if (HAS_PCH_DG1(dev_priv))
 191                 hpd->pch_hpd = hpd_sde_dg1;
 192         else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) ||
 193                  HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
 194                 hpd->pch_hpd = hpd_icp;
 195         else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
 196                 hpd->pch_hpd = hpd_spt;
 197         else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_CPT(dev_priv))
 198                 hpd->pch_hpd = hpd_cpt;
 199         else if (HAS_PCH_IBX(dev_priv))
 200                 hpd->pch_hpd = hpd_ibx;
 201         else
 202                 MISSING_CASE(INTEL_PCH_TYPE(dev_priv));
 203 }
 204
 205 static void
 206 intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
 207 {
 208         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
 209
 210         drm_crtc_handle_vblank(&crtc->base);
 211 }
 212
 213 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
 214                     i915_reg_t iir, i915_reg_t ier)
 215 {
 216         intel_uncore_write(uncore, imr, 0xffffffff);
 217         intel_uncore_posting_read(uncore, imr);
 218
 219         intel_uncore_write(uncore, ier, 0);
 220
 221         /* IIR can theoretically queue up two events. Be paranoid. */
 222         intel_uncore_write(uncore, iir, 0xffffffff);
 223         intel_uncore_posting_read(uncore, iir);
 224         intel_uncore_write(uncore, iir, 0xffffffff);
 225         intel_uncore_posting_read(uncore, iir);
 226 }
 227
 228 void gen2_irq_reset(struct intel_uncore *uncore)
 229 {
 230         intel_uncore_write16(uncore, GEN2_IMR, 0xffff);
 231         intel_uncore_posting_read16(uncore, GEN2_IMR);
 232
 233         intel_uncore_write16(uncore, GEN2_IER, 0);
 234
 235         /* IIR can theoretically queue up two events. Be paranoid. */
 236         intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
 237         intel_uncore_posting_read16(uncore, GEN2_IIR);
 238         intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
 239         intel_uncore_posting_read16(uncore, GEN2_IIR);
 240 }
 241
 242 /*
 243  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
 244  */
 245 static void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)
 246 {
 247         u32 val = intel_uncore_read(uncore, reg);
 248
 249         if (val == 0)
 250                 return;
 251
 252         drm_WARN(&uncore->i915->drm, 1,
 253                  "Interrupt register 0x%x is not zero: 0x%08x\n",
 254                  i915_mmio_reg_offset(reg), val);
 255         intel_uncore_write(uncore, reg, 0xffffffff);
 256         intel_uncore_posting_read(uncore, reg);
 257         intel_uncore_write(uncore, reg, 0xffffffff);
 258         intel_uncore_posting_read(uncore, reg);
 259 }
 260
 261 static void gen2_assert_iir_is_zero(struct intel_uncore *uncore)
 262 {
 263         u16 val = intel_uncore_read16(uncore, GEN2_IIR);
 264
 265         if (val == 0)
 266                 return;
 267
 268         drm_WARN(&uncore->i915->drm, 1,
 269                  "Interrupt register 0x%x is not zero: 0x%08x\n",
 270                  i915_mmio_reg_offset(GEN2_IIR), val);
 271         intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
 272         intel_uncore_posting_read16(uncore, GEN2_IIR);
 273         intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
 274         intel_uncore_posting_read16(uncore, GEN2_IIR);
 275 }
 276
 277 void gen3_irq_init(struct intel_uncore *uncore,
 278                    i915_reg_t imr, u32 imr_val,
 279                    i915_reg_t ier, u32 ier_val,
 280                    i915_reg_t iir)
 281 {
 282         gen3_assert_iir_is_zero(uncore, iir);
 283
 284         intel_uncore_write(uncore, ier, ier_val);
 285         intel_uncore_write(uncore, imr, imr_val);
 286         intel_uncore_posting_read(uncore, imr);
 287 }
 288
 289 void gen2_irq_init(struct intel_uncore *uncore,
 290                    u32 imr_val, u32 ier_val)
 291 {
 292         gen2_assert_iir_is_zero(uncore);
 293
 294         intel_uncore_write16(uncore, GEN2_IER, ier_val);
 295         intel_uncore_write16(uncore, GEN2_IMR, imr_val);
 296         intel_uncore_posting_read16(uncore, GEN2_IMR);
 297 }
 298
 299 /* For display hotplug interrupt */
 300 static inline void
 301 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
 302                                      u32 mask,
 303                                      u32 bits)
 304 {
 305         u32 val;
 306
 307         lockdep_assert_held(&dev_priv->irq_lock);
 308         drm_WARN_ON(&dev_priv->drm, bits & ~mask);
 309
 310         val = I915_READ(PORT_HOTPLUG_EN);
 311         val &= ~mask;
 312         val |= bits;
 313         I915_WRITE(PORT_HOTPLUG_EN, val);
 314 }
 315
 316 /**
 317  * i915_hotplug_interrupt_update - update hotplug interrupt enable
 318  * @dev_priv: driver private
 319  * @mask: bits to update
 320  * @bits: bits to enable
 321  * NOTE: the HPD enable bits are modified both inside and outside
 322  * of an interrupt context. To avoid that read-modify-write cycles
 323  * interfer, these bits are protected by a spinlock. Since this
 324  * function is usually not called from a context where the lock is
 325  * held already, this function acquires the lock itself. A non-locking
 326  * version is also available.
 327  */
 328 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
 329                                    u32 mask,
 330                                    u32 bits)
 331 {
 332         spin_lock_irq(&dev_priv->irq_lock);
 333         i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
 334         spin_unlock_irq(&dev_priv->irq_lock);
 335 }
 336
 337 /**
 338  * ilk_update_display_irq - update DEIMR
 339  * @dev_priv: driver private
 340  * @interrupt_mask: mask of interrupt bits to update
 341  * @enabled_irq_mask: mask of interrupt bits to enable
 342  */
 343 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
 344                             u32 interrupt_mask,
 345                             u32 enabled_irq_mask)
 346 {
 347         u32 new_val;
 348
 349         lockdep_assert_held(&dev_priv->irq_lock);
 350         drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
 351
 352         new_val = dev_priv->irq_mask;
 353         new_val &= ~interrupt_mask;
 354         new_val |= (~enabled_irq_mask & interrupt_mask);
 355
 356         if (new_val != dev_priv->irq_mask &&
 357             !drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) {
 358                 dev_priv->irq_mask = new_val;
 359                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 360                 POSTING_READ(DEIMR);
 361         }
 362 }
 363
 364 /**
 365  * bdw_update_port_irq - update DE port interrupt
 366  * @dev_priv: driver private
 367  * @interrupt_mask: mask of interrupt bits to update
 368  * @enabled_irq_mask: mask of interrupt bits to enable
 369  */
 370 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
 371                                 u32 interrupt_mask,
 372                                 u32 enabled_irq_mask)
 373 {
 374         u32 new_val;
 375         u32 old_val;
 376
 377         lockdep_assert_held(&dev_priv->irq_lock);
 378
 379         drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
 380
 381         if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
 382                 return;
 383
 384         old_val = I915_READ(GEN8_DE_PORT_IMR);
 385
 386         new_val = old_val;
 387         new_val &= ~interrupt_mask;
 388         new_val |= (~enabled_irq_mask & interrupt_mask);
 389
 390         if (new_val != old_val) {
 391                 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
 392                 POSTING_READ(GEN8_DE_PORT_IMR);
 393         }
 394 }
 395
 396 /**
 397  * bdw_update_pipe_irq - update DE pipe interrupt
 398  * @dev_priv: driver private
 399  * @pipe: pipe whose interrupt to update
 400  * @interrupt_mask: mask of interrupt bits to update
 401  * @enabled_irq_mask: mask of interrupt bits to enable
 402  */
 403 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
 404                          enum pipe pipe,
 405                          u32 interrupt_mask,
 406                          u32 enabled_irq_mask)
 407 {
 408         u32 new_val;
 409
 410         lockdep_assert_held(&dev_priv->irq_lock);
 411
 412         drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
 413
 414         if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
 415                 return;
 416
 417         new_val = dev_priv->de_irq_mask[pipe];
 418         new_val &= ~interrupt_mask;
 419         new_val |= (~enabled_irq_mask & interrupt_mask);
 420
 421         if (new_val != dev_priv->de_irq_mask[pipe]) {
 422                 dev_priv->de_irq_mask[pipe] = new_val;
 423                 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
 424                 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
 425         }
 426 }
 427
 428 /**
 429  * ibx_display_interrupt_update - update SDEIMR
 430  * @dev_priv: driver private
 431  * @interrupt_mask: mask of interrupt bits to update
 432  * @enabled_irq_mask: mask of interrupt bits to enable
 433  */
 434 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 435                                   u32 interrupt_mask,
 436                                   u32 enabled_irq_mask)
 437 {
 438         u32 sdeimr = I915_READ(SDEIMR);
 439         sdeimr &= ~interrupt_mask;
 440         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 441
 442         drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
 443
 444         lockdep_assert_held(&dev_priv->irq_lock);
 445
 446         if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
 447                 return;
 448
 449         I915_WRITE(SDEIMR, sdeimr);
 450         POSTING_READ(SDEIMR);
 451 }
 452
 453 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
 454                               enum pipe pipe)
 455 {
 456         u32 status_mask = dev_priv->pipestat_irq_mask[pipe];
 457         u32 enable_mask = status_mask << 16;
 458
 459         lockdep_assert_held(&dev_priv->irq_lock);
 460
 461         if (INTEL_GEN(dev_priv) < 5)
 462                 goto out;
 463
 464         /*
 465          * On pipe A we don't support the PSR interrupt yet,
 466          * on pipe B and C the same bit MBZ.
 467          */
 468         if (drm_WARN_ON_ONCE(&dev_priv->drm,
 469                              status_mask & PIPE_A_PSR_STATUS_VLV))
 470                 return 0;
 471         /*
 472          * On pipe B and C we don't support the PSR interrupt yet, on pipe
 473          * A the same bit is for perf counters which we don't use either.
 474          */
 475         if (drm_WARN_ON_ONCE(&dev_priv->drm,
 476                              status_mask & PIPE_B_PSR_STATUS_VLV))
 477                 return 0;
 478
 479         enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
 480                          SPRITE0_FLIP_DONE_INT_EN_VLV |
 481                          SPRITE1_FLIP_DONE_INT_EN_VLV);
 482         if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
 483                 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
 484         if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
 485                 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
 486
 487 out:
 488         drm_WARN_ONCE(&dev_priv->drm,
 489                       enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 490                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 491                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 492                       pipe_name(pipe), enable_mask, status_mask);
 493
 494         return enable_mask;
 495 }
 496
 497 void i915_enable_pipestat(struct drm_i915_private *dev_priv,
 498                           enum pipe pipe, u32 status_mask)
 499 {
 500         i915_reg_t reg = PIPESTAT(pipe);
 501         u32 enable_mask;
 502
 503         drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
 504                       "pipe %c: status_mask=0x%x\n",
 505                       pipe_name(pipe), status_mask);
 506
 507         lockdep_assert_held(&dev_priv->irq_lock);
 508         drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
 509
 510         if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask)
 511                 return;
 512
 513         dev_priv->pipestat_irq_mask[pipe] |= status_mask;
 514         enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
 515
 516         I915_WRITE(reg, enable_mask | status_mask);
 517         POSTING_READ(reg);
 518 }
 519
 520 void i915_disable_pipestat(struct drm_i915_private *dev_priv,
 521                            enum pipe pipe, u32 status_mask)
 522 {
 523         i915_reg_t reg = PIPESTAT(pipe);
 524         u32 enable_mask;
 525
 526         drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
 527                       "pipe %c: status_mask=0x%x\n",
 528                       pipe_name(pipe), status_mask);
 529
 530         lockdep_assert_held(&dev_priv->irq_lock);
 531         drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
 532
 533         if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0)
 534                 return;
 535
 536         dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
 537         enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
 538
 539         I915_WRITE(reg, enable_mask | status_mask);
 540         POSTING_READ(reg);
 541 }
 542
 543 static bool i915_has_asle(struct drm_i915_private *dev_priv)
 544 {
 545         if (!dev_priv->opregion.asle)
 546                 return false;
 547
 548         return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
 549 }
 550
 551 /**
 552  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 553  * @dev_priv: i915 device private
 554  */
 555 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
 556 {
 557         if (!i915_has_asle(dev_priv))
 558                 return;
 559
 560         spin_lock_irq(&dev_priv->irq_lock);
 561
 562         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
 563         if (INTEL_GEN(dev_priv) >= 4)
 564                 i915_enable_pipestat(dev_priv, PIPE_A,
 565                                      PIPE_LEGACY_BLC_EVENT_STATUS);
 566
 567         spin_unlock_irq(&dev_priv->irq_lock);
 568 }
 569
 570 /*
 571  * This timing diagram depicts the video signal in and
 572  * around the vertical blanking period.
 573  *
 574  * Assumptions about the fictitious mode used in this example:
 575  *  vblank_start >= 3
 576  *  vsync_start = vblank_start + 1
 577  *  vsync_end = vblank_start + 2
 578  *  vtotal = vblank_start + 3
 579  *
 580  *           start of vblank:
 581  *           latch double buffered registers
 582  *           increment frame counter (ctg+)
 583  *           generate start of vblank interrupt (gen4+)
 584  *           |
 585  *           |          frame start:
 586  *           |          generate frame start interrupt (aka. vblank interrupt) (gmch)
 587  *           |          may be shifted forward 1-3 extra lines via PIPECONF
 588  *           |          |
 589  *           |          |  start of vsync:
 590  *           |          |  generate vsync interrupt
 591  *           |          |  |
 592  * ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx
 593  *       .   \hs/   .      \hs/          \hs/          \hs/   .      \hs/
 594  * ----va---> <-----------------vb--------------------> <--------va-------------
 595  *       |          |       <----vs----->                     |
 596  * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
 597  * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
 598  * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
 599  *       |          |                                         |
 600  *       last visible pixel                                   first visible pixel
 601  *                  |                                         increment frame counter (gen3/4)
 602  *                  pixel counter = vblank_start * htotal     pixel counter = 0 (gen3/4)
 603  *
 604  * x  = horizontal active
 605  * _  = horizontal blanking
 606  * hs = horizontal sync
 607  * va = vertical active
 608  * vb = vertical blanking
 609  * vs = vertical sync
 610  * vbs = vblank_start (number)
 611  *
 612  * Summary:
 613  * - most events happen at the start of horizontal sync
 614  * - frame start happens at the start of horizontal blank, 1-4 lines
 615  *   (depending on PIPECONF settings) after the start of vblank
 616  * - gen3/4 pixel and frame counter are synchronized with the start
 617  *   of horizontal active on the first line of vertical active
 618  */
 619
 620 /* Called from drm generic code, passed a 'crtc', which
 621  * we use as a pipe index
 622  */
 623 u32 i915_get_vblank_counter(struct drm_crtc *crtc)
 624 {
 625         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 626         struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];
 627         const struct drm_display_mode *mode = &vblank->hwmode;
 628         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 629         i915_reg_t high_frame, low_frame;
 630         u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
 631         unsigned long irqflags;
 632
 633         /*
 634          * On i965gm TV output the frame counter only works up to
 635          * the point when we enable the TV encoder. After that the
 636          * frame counter ceases to work and reads zero. We need a
 637          * vblank wait before enabling the TV encoder and so we
 638          * have to enable vblank interrupts while the frame counter
 639          * is still in a working state. However the core vblank code
 640          * does not like us returning non-zero frame counter values
 641          * when we've told it that we don't have a working frame
 642          * counter. Thus we must stop non-zero values leaking out.
 643          */
 644         if (!vblank->max_vblank_count)
 645                 return 0;
 646
 647         htotal = mode->crtc_htotal;
 648         hsync_start = mode->crtc_hsync_start;
 649         vbl_start = mode->crtc_vblank_start;
 650         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 651                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 652
 653         /* Convert to pixel count */
 654         vbl_start *= htotal;
 655
 656         /* Start of vblank event occurs at start of hsync */
 657         vbl_start -= htotal - hsync_start;
 658
 659         high_frame = PIPEFRAME(pipe);
 660         low_frame = PIPEFRAMEPIXEL(pipe);
 661
 662         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 663
 664         /*
 665          * High & low register fields aren't synchronized, so make sure
 666          * we get a low value that's stable across two reads of the high
 667          * register.
 668          */
 669         do {
 670                 high1 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK;
 671                 low   = intel_de_read_fw(dev_priv, low_frame);
 672                 high2 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK;
 673         } while (high1 != high2);
 674
 675         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 676
 677         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 678         pixel = low & PIPE_PIXEL_MASK;
 679         low >>= PIPE_FRAME_LOW_SHIFT;
 680
 681         /*
 682          * The frame counter increments at beginning of active.
 683          * Cook up a vblank counter by also checking the pixel
 684          * counter against vblank start.
 685          */
 686         return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
 687 }
 688
 689 u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
 690 {
 691         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 692         struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];
 693         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 694
 695         if (!vblank->max_vblank_count)
 696                 return 0;
 697
 698         return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
 699 }
 700
 701 /*
 702  * On certain encoders on certain platforms, pipe
 703  * scanline register will not work to get the scanline,
 704  * since the timings are driven from the PORT or issues
 705  * with scanline register updates.
 706  * This function will use Framestamp and current
 707  * timestamp registers to calculate the scanline.
 708  */
 709 static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
 710 {
 711         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 712         struct drm_vblank_crtc *vblank =
 713                 &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
 714         const struct drm_display_mode *mode = &vblank->hwmode;
 715         u32 vblank_start = mode->crtc_vblank_start;
 716         u32 vtotal = mode->crtc_vtotal;
 717         u32 htotal = mode->crtc_htotal;
 718         u32 clock = mode->crtc_clock;
 719         u32 scanline, scan_prev_time, scan_curr_time, scan_post_time;
 720
 721         /*
 722          * To avoid the race condition where we might cross into the
 723          * next vblank just between the PIPE_FRMTMSTMP and TIMESTAMP_CTR
 724          * reads. We make sure we read PIPE_FRMTMSTMP and TIMESTAMP_CTR
 725          * during the same frame.
 726          */
 727         do {
 728                 /*
 729                  * This field provides read back of the display
 730                  * pipe frame time stamp. The time stamp value
 731                  * is sampled at every start of vertical blank.
 732                  */
 733                 scan_prev_time = intel_de_read_fw(dev_priv,
 734                                                   PIPE_FRMTMSTMP(crtc->pipe));
 735
 736                 /*
 737                  * The TIMESTAMP_CTR register has the current
 738                  * time stamp value.
 739                  */
 740                 scan_curr_time = intel_de_read_fw(dev_priv, IVB_TIMESTAMP_CTR);
 741
 742                 scan_post_time = intel_de_read_fw(dev_priv,
 743                                                   PIPE_FRMTMSTMP(crtc->pipe));
 744         } while (scan_post_time != scan_prev_time);
 745
 746         scanline = div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
 747                                         clock), 1000 * htotal);
 748         scanline = min(scanline, vtotal - 1);
 749         scanline = (scanline + vblank_start) % vtotal;
 750
 751         return scanline;
 752 }
 753
 754 /*
 755  * intel_de_read_fw(), only for fast reads of display block, no need for
 756  * forcewake etc.
 757  */
 758 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
 759 {
 760         struct drm_device *dev = crtc->base.dev;
 761         struct drm_i915_private *dev_priv = to_i915(dev);
 762         const struct drm_display_mode *mode;
 763         struct drm_vblank_crtc *vblank;
 764         enum pipe pipe = crtc->pipe;
 765         int position, vtotal;
 766
 767         if (!crtc->active)
 768                 return -1;
 769
 770         vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
 771         mode = &vblank->hwmode;
 772
 773         if (crtc->mode_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
 774                 return __intel_get_crtc_scanline_from_timestamp(crtc);
 775
 776         vtotal = mode->crtc_vtotal;
 777         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 778                 vtotal /= 2;
 779
 780         if (IS_GEN(dev_priv, 2))
 781                 position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
 782         else
 783                 position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 784
 785         /*
 786          * On HSW, the DSL reg (0x70000) appears to return 0 if we
 787          * read it just before the start of vblank.  So try it again
 788          * so we don't accidentally end up spanning a vblank frame
 789          * increment, causing the pipe_update_end() code to squak at us.
 790          *
 791          * The nature of this problem means we can't simply check the ISR
 792          * bit and return the vblank start value; nor can we use the scanline
 793          * debug register in the transcoder as it appears to have the same
 794          * problem.  We may need to extend this to include other platforms,
 795          * but so far testing only shows the problem on HSW.
 796          */
 797         if (HAS_DDI(dev_priv) && !position) {
 798                 int i, temp;
 799
 800                 for (i = 0; i < 100; i++) {
 801                         udelay(1);
 802                         temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 803                         if (temp != position) {
 804                                 position = temp;
 805                                 break;
 806                         }
 807                 }
 808         }
 809
 810         /*
 811          * See update_scanline_offset() for the details on the
 812          * scanline_offset adjustment.
 813          */
 814         return (position + crtc->scanline_offset) % vtotal;
 815 }
 816
 817 static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
 818                                      bool in_vblank_irq,
 819                                      int *vpos, int *hpos,
 820                                      ktime_t *stime, ktime_t *etime,
 821                                      const struct drm_display_mode *mode)
 822 {
 823         struct drm_device *dev = _crtc->dev;
 824         struct drm_i915_private *dev_priv = to_i915(dev);
 825         struct intel_crtc *crtc = to_intel_crtc(_crtc);
 826         enum pipe pipe = crtc->pipe;
 827         int position;
 828         int vbl_start, vbl_end, hsync_start, htotal, vtotal;
 829         unsigned long irqflags;
 830         bool use_scanline_counter = INTEL_GEN(dev_priv) >= 5 ||
 831                 IS_G4X(dev_priv) || IS_GEN(dev_priv, 2) ||
 832                 crtc->mode_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER;
 833
 834         if (drm_WARN_ON(&dev_priv->drm, !mode->crtc_clock)) {
 835                 drm_dbg(&dev_priv->drm,
 836                         "trying to get scanoutpos for disabled "
 837                         "pipe %c\n", pipe_name(pipe));
 838                 return false;
 839         }
 840
 841         htotal = mode->crtc_htotal;
 842         hsync_start = mode->crtc_hsync_start;
 843         vtotal = mode->crtc_vtotal;
 844         vbl_start = mode->crtc_vblank_start;
 845         vbl_end = mode->crtc_vblank_end;
 846
 847         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 848                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 849                 vbl_end /= 2;
 850                 vtotal /= 2;
 851         }
 852
 853         /*
 854          * Lock uncore.lock, as we will do multiple timing critical raw
 855          * register reads, potentially with preemption disabled, so the
 856          * following code must not block on uncore.lock.
 857          */
 858         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 859
 860         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 861
 862         /* Get optional system timestamp before query. */
 863         if (stime)
 864                 *stime = ktime_get();
 865
 866         if (use_scanline_counter) {
 867                 /* No obvious pixelcount register. Only query vertical
 868                  * scanout position from Display scan line register.
 869                  */
 870                 position = __intel_get_crtc_scanline(crtc);
 871         } else {
 872                 /* Have access to pixelcount since start of frame.
 873                  * We can split this into vertical and horizontal
 874                  * scanout position.
 875                  */
 876                 position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 877
 878                 /* convert to pixel counts */
 879                 vbl_start *= htotal;
 880                 vbl_end *= htotal;
 881                 vtotal *= htotal;
 882
 883                 /*
 884                  * In interlaced modes, the pixel counter counts all pixels,
 885                  * so one field will have htotal more pixels. In order to avoid
 886                  * the reported position from jumping backwards when the pixel
 887                  * counter is beyond the length of the shorter field, just
 888                  * clamp the position the length of the shorter field. This
 889                  * matches how the scanline counter based position works since
 890                  * the scanline counter doesn't count the two half lines.
 891                  */
 892                 if (position >= vtotal)
 893                         position = vtotal - 1;
 894
 895                 /*
 896                  * Start of vblank interrupt is triggered at start of hsync,
 897                  * just prior to the first active line of vblank. However we
 898                  * consider lines to start at the leading edge of horizontal
 899                  * active. So, should we get here before we've crossed into
 900                  * the horizontal active of the first line in vblank, we would
 901                  * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
 902                  * always add htotal-hsync_start to the current pixel position.
 903                  */
 904                 position = (position + htotal - hsync_start) % vtotal;
 905         }
 906
 907         /* Get optional system timestamp after query. */
 908         if (etime)
 909                 *etime = ktime_get();
 910
 911         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 912
 913         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 914
 915         /*
 916          * While in vblank, position will be negative
 917          * counting up towards 0 at vbl_end. And outside
 918          * vblank, position will be positive counting
 919          * up since vbl_end.
 920          */
 921         if (position >= vbl_start)
 922                 position -= vbl_end;
 923         else
 924                 position += vtotal - vbl_end;
 925
 926         if (use_scanline_counter) {
 927                 *vpos = position;
 928                 *hpos = 0;
 929         } else {
 930                 *vpos = position / htotal;
 931                 *hpos = position - (*vpos * htotal);
 932         }
 933
 934         return true;
 935 }
 936
 937 bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error,
 938                                      ktime_t *vblank_time, bool in_vblank_irq)
 939 {
 940         return drm_crtc_vblank_helper_get_vblank_timestamp_internal(
 941                 crtc, max_error, vblank_time, in_vblank_irq,
 942                 i915_get_crtc_scanoutpos);
 943 }
 944
 945 int intel_get_crtc_scanline(struct intel_crtc *crtc)
 946 {
 947         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 948         unsigned long irqflags;
 949         int position;
 950
 951         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 952         position = __intel_get_crtc_scanline(crtc);
 953         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 954
 955         return position;
 956 }
 957
 958 /**
 959  * ivb_parity_work - Workqueue called when a parity error interrupt
 960  * occurred.
 961  * @work: workqueue struct
 962  *
 963  * Doesn't actually do anything except notify userspace. As a consequence of
 964  * this event, userspace should try to remap the bad rows since statistically
 965  * it is likely the same row is more likely to go bad again.
 966  */
 967 static void ivb_parity_work(struct work_struct *work)
 968 {
 969         struct drm_i915_private *dev_priv =
 970                 container_of(work, typeof(*dev_priv), l3_parity.error_work);
 971         struct intel_gt *gt = &dev_priv->gt;
 972         u32 error_status, row, bank, subbank;
 973         char *parity_event[6];
 974         u32 misccpctl;
 975         u8 slice = 0;
 976
 977         /* We must turn off DOP level clock gating to access the L3 registers.
 978          * In order to prevent a get/put style interface, acquire struct mutex
 979          * any time we access those registers.
 980          */
 981         mutex_lock(&dev_priv->drm.struct_mutex);
 982
 983         /* If we've screwed up tracking, just let the interrupt fire again */
 984         if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice))
 985                 goto out;
 986
 987         misccpctl = I915_READ(GEN7_MISCCPCTL);
 988         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
 989         POSTING_READ(GEN7_MISCCPCTL);
 990
 991         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
 992                 i915_reg_t reg;
 993
 994                 slice--;
 995                 if (drm_WARN_ON_ONCE(&dev_priv->drm,
 996                                      slice >= NUM_L3_SLICES(dev_priv)))
 997                         break;
 998
 999                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1000
1001                 reg = GEN7_L3CDERRST1(slice);
1002
1003                 error_status = I915_READ(reg);
1004                 row = GEN7_PARITY_ERROR_ROW(error_status);
1005                 bank = GEN7_PARITY_ERROR_BANK(error_status);
1006                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1007
1008                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1009                 POSTING_READ(reg);
1010
1011                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1012                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1013                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1014                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1015                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1016                 parity_event[5] = NULL;
1017
1018                 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
1019                                    KOBJ_CHANGE, parity_event);
1020
1021                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1022                           slice, row, bank, subbank);
1023
1024                 kfree(parity_event[4]);
1025                 kfree(parity_event[3]);
1026                 kfree(parity_event[2]);
1027                 kfree(parity_event[1]);
1028         }
1029
1030         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1031
1032 out:
1033         drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice);
1034         spin_lock_irq(&gt->irq_lock);
1035         gen5_gt_enable_irq(gt, GT_PARITY_ERROR(dev_priv));
1036         spin_unlock_irq(&gt->irq_lock);
1037
1038         mutex_unlock(&dev_priv->drm.struct_mutex);
1039 }
1040
1041 static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1042 {
1043         switch (pin) {
1044         case HPD_PORT_TC1:
1045                 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_1);
1046         case HPD_PORT_TC2:
1047                 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_2);
1048         case HPD_PORT_TC3:
1049                 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_3);
1050         case HPD_PORT_TC4:
1051                 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_4);
1052         case HPD_PORT_TC5:
1053                 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_5);
1054         case HPD_PORT_TC6:
1055                 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_6);
1056         default:
1057                 return false;
1058         }
1059 }
1060
1061 static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1062 {
1063         switch (pin) {
1064         case HPD_PORT_A:
1065                 return val & PORTA_HOTPLUG_LONG_DETECT;
1066         case HPD_PORT_B:
1067                 return val & PORTB_HOTPLUG_LONG_DETECT;
1068         case HPD_PORT_C:
1069                 return val & PORTC_HOTPLUG_LONG_DETECT;
1070         default:
1071                 return false;
1072         }
1073 }
1074
1075 static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1076 {
1077         switch (pin) {
1078         case HPD_PORT_A:
1079                 return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_A);
1080         case HPD_PORT_B:
1081                 return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B);
1082         case HPD_PORT_C:
1083                 return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C);
1084         case HPD_PORT_D:
1085                 return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_D);
1086         default:
1087                 return false;
1088         }
1089 }
1090
1091 static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1092 {
1093         switch (pin) {
1094         case HPD_PORT_TC1:
1095                 return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_1);
1096         case HPD_PORT_TC2:
1097                 return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_2);
1098         case HPD_PORT_TC3:
1099                 return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_3);
1100         case HPD_PORT_TC4:
1101                 return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_4);
1102         case HPD_PORT_TC5:
1103                 return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_5);
1104         case HPD_PORT_TC6:
1105                 return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_6);
1106         default:
1107                 return false;
1108         }
1109 }
1110
1111 static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
1112 {
1113         switch (pin) {
1114         case HPD_PORT_E:
1115                 return val & PORTE_HOTPLUG_LONG_DETECT;
1116         default:
1117                 return false;
1118         }
1119 }
1120
1121 static bool spt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1122 {
1123         switch (pin) {
1124         case HPD_PORT_A:
1125                 return val & PORTA_HOTPLUG_LONG_DETECT;
1126         case HPD_PORT_B:
1127                 return val & PORTB_HOTPLUG_LONG_DETECT;
1128         case HPD_PORT_C:
1129                 return val & PORTC_HOTPLUG_LONG_DETECT;
1130         case HPD_PORT_D:
1131                 return val & PORTD_HOTPLUG_LONG_DETECT;
1132         default:
1133                 return false;
1134         }
1135 }
1136
1137 static bool ilk_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1138 {
1139         switch (pin) {
1140         case HPD_PORT_A:
1141                 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1142         default:
1143                 return false;
1144         }
1145 }
1146
1147 static bool pch_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1148 {
1149         switch (pin) {
1150         case HPD_PORT_B:
1151                 return val & PORTB_HOTPLUG_LONG_DETECT;
1152         case HPD_PORT_C:
1153                 return val & PORTC_HOTPLUG_LONG_DETECT;
1154         case HPD_PORT_D:
1155                 return val & PORTD_HOTPLUG_LONG_DETECT;
1156         default:
1157                 return false;
1158         }
1159 }
1160
1161 static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1162 {
1163         switch (pin) {
1164         case HPD_PORT_B:
1165                 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1166         case HPD_PORT_C:
1167                 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1168         case HPD_PORT_D:
1169                 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1170         default:
1171                 return false;
1172         }
1173 }
1174
1175 /*
1176  * Get a bit mask of pins that have triggered, and which ones may be long.
1177  * This can be called multiple times with the same masks to accumulate
1178  * hotplug detection results from several registers.
1179  *
1180  * Note that the caller is expected to zero out the masks initially.
1181  */
1182 static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
1183                                u32 *pin_mask, u32 *long_mask,
1184                                u32 hotplug_trigger, u32 dig_hotplug_reg,
1185                                const u32 hpd[HPD_NUM_PINS],
1186                                bool long_pulse_detect(enum hpd_pin pin, u32 val))
1187 {
1188         enum hpd_pin pin;
1189
1190         BUILD_BUG_ON(BITS_PER_TYPE(*pin_mask) < HPD_NUM_PINS);
1191
1192         for_each_hpd_pin(pin) {
1193                 if ((hpd[pin] & hotplug_trigger) == 0)
1194                         continue;
1195
1196                 *pin_mask |= BIT(pin);
1197
1198                 if (long_pulse_detect(pin, dig_hotplug_reg))
1199                         *long_mask |= BIT(pin);
1200         }
1201
1202         drm_dbg(&dev_priv->drm,
1203                 "hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n",
1204                 hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask);
1205
1206 }
1207
1208 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1209 {
1210         wake_up_all(&dev_priv->gmbus_wait_queue);
1211 }
1212
1213 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1214 {
1215         wake_up_all(&dev_priv->gmbus_wait_queue);
1216 }
1217
1218 #if defined(CONFIG_DEBUG_FS)
1219 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1220                                          enum pipe pipe,
1221                                          u32 crc0, u32 crc1,
1222                                          u32 crc2, u32 crc3,
1223                                          u32 crc4)
1224 {
1225         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1226         struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
1227         u32 crcs[5] = { crc0, crc1, crc2, crc3, crc4 };
1228
1229         trace_intel_pipe_crc(crtc, crcs);
1230
1231         spin_lock(&pipe_crc->lock);
1232         /*
1233          * For some not yet identified reason, the first CRC is
1234          * bonkers. So let's just wait for the next vblank and read
1235          * out the buggy result.
1236          *
1237          * On GEN8+ sometimes the second CRC is bonkers as well, so
1238          * don't trust that one either.
1239          */
1240         if (pipe_crc->skipped <= 0 ||
1241             (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
1242                 pipe_crc->skipped++;
1243                 spin_unlock(&pipe_crc->lock);
1244                 return;
1245         }
1246         spin_unlock(&pipe_crc->lock);
1247
1248         drm_crtc_add_crc_entry(&crtc->base, true,
1249                                 drm_crtc_accurate_vblank_count(&crtc->base),
1250                                 crcs);
1251 }
1252 #else
1253 static inline void
1254 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1255                              enum pipe pipe,
1256                              u32 crc0, u32 crc1,
1257                              u32 crc2, u32 crc3,
1258                              u32 crc4) {}
1259 #endif
1260
1261 static void flip_done_handler(struct drm_i915_private *i915,
1262                               enum pipe pipe)
1263 {
1264         struct intel_crtc *crtc = intel_get_crtc_for_pipe(i915, pipe);
1265         struct drm_crtc_state *crtc_state = crtc->base.state;
1266         struct drm_pending_vblank_event *e = crtc_state->event;
1267         struct drm_device *dev = &i915->drm;
1268         unsigned long irqflags;
1269
1270         spin_lock_irqsave(&dev->event_lock, irqflags);
1271
1272         crtc_state->event = NULL;
1273
1274         drm_crtc_send_vblank_event(&crtc->base, e);
1275
1276         spin_unlock_irqrestore(&dev->event_lock, irqflags);
1277 }
1278
1279 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1280                                      enum pipe pipe)
1281 {
1282         display_pipe_crc_irq_handler(dev_priv, pipe,
1283                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1284                                      0, 0, 0, 0);
1285 }
1286
1287 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1288                                      enum pipe pipe)
1289 {
1290         display_pipe_crc_irq_handler(dev_priv, pipe,
1291                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1292                                      I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1293                                      I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1294                                      I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1295                                      I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1296 }
1297
1298 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1299                                       enum pipe pipe)
1300 {
1301         u32 res1, res2;
1302
1303         if (INTEL_GEN(dev_priv) >= 3)
1304                 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1305         else
1306                 res1 = 0;
1307
1308         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1309                 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1310         else
1311                 res2 = 0;
1312
1313         display_pipe_crc_irq_handler(dev_priv, pipe,
1314                                      I915_READ(PIPE_CRC_RES_RED(pipe)),
1315                                      I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1316                                      I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1317                                      res1, res2);
1318 }
1319
1320 static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
1321 {
1322         enum pipe pipe;
1323
1324         for_each_pipe(dev_priv, pipe) {
1325                 I915_WRITE(PIPESTAT(pipe),
1326                            PIPESTAT_INT_STATUS_MASK |
1327                            PIPE_FIFO_UNDERRUN_STATUS);
1328
1329                 dev_priv->pipestat_irq_mask[pipe] = 0;
1330         }
1331 }
1332
1333 static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1334                                   u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1335 {
1336         enum pipe pipe;
1337
1338         spin_lock(&dev_priv->irq_lock);
1339
1340         if (!dev_priv->display_irqs_enabled) {
1341                 spin_unlock(&dev_priv->irq_lock);
1342                 return;
1343         }
1344
1345         for_each_pipe(dev_priv, pipe) {
1346                 i915_reg_t reg;
1347                 u32 status_mask, enable_mask, iir_bit = 0;
1348
1349                 /*
1350                  * PIPESTAT bits get signalled even when the interrupt is
1351                  * disabled with the mask bits, and some of the status bits do
1352                  * not generate interrupts at all (like the underrun bit). Hence
1353                  * we need to be careful that we only handle what we want to
1354                  * handle.
1355                  */
1356
1357                 /* fifo underruns are filterered in the underrun handler. */
1358                 status_mask = PIPE_FIFO_UNDERRUN_STATUS;
1359
1360                 switch (pipe) {
1361                 default:
1362                 case PIPE_A:
1363                         iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1364                         break;
1365                 case PIPE_B:
1366                         iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1367                         break;
1368                 case PIPE_C:
1369                         iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1370                         break;
1371                 }
1372                 if (iir & iir_bit)
1373                         status_mask |= dev_priv->pipestat_irq_mask[pipe];
1374
1375                 if (!status_mask)
1376                         continue;
1377
1378                 reg = PIPESTAT(pipe);
1379                 pipe_stats[pipe] = I915_READ(reg) & status_mask;
1380                 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
1381
1382                 /*
1383                  * Clear the PIPE*STAT regs before the IIR
1384                  *
1385                  * Toggle the enable bits to make sure we get an
1386                  * edge in the ISR pipe event bit if we don't clear
1387                  * all the enabled status bits. Otherwise the edge
1388                  * triggered IIR on i965/g4x wouldn't notice that
1389                  * an interrupt is still pending.
1390                  */
1391                 if (pipe_stats[pipe]) {
1392                         I915_WRITE(reg, pipe_stats[pipe]);
1393                         I915_WRITE(reg, enable_mask);
1394                 }
1395         }
1396         spin_unlock(&dev_priv->irq_lock);
1397 }
1398
1399 static void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1400                                       u16 iir, u32 pipe_stats[I915_MAX_PIPES])
1401 {
1402         enum pipe pipe;
1403
1404         for_each_pipe(dev_priv, pipe) {
1405                 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1406                         intel_handle_vblank(dev_priv, pipe);
1407
1408                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1409                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1410
1411                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1412                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1413         }
1414 }
1415
1416 static void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1417                                       u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1418 {
1419         bool blc_event = false;
1420         enum pipe pipe;
1421
1422         for_each_pipe(dev_priv, pipe) {
1423                 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1424                         intel_handle_vblank(dev_priv, pipe);
1425
1426                 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1427                         blc_event = true;
1428
1429                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1430                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1431
1432                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1433                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1434         }
1435
1436         if (blc_event || (iir & I915_ASLE_INTERRUPT))
1437                 intel_opregion_asle_intr(dev_priv);
1438 }
1439
1440 static void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1441                                       u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1442 {
1443         bool blc_event = false;
1444         enum pipe pipe;
1445
1446         for_each_pipe(dev_priv, pipe) {
1447                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1448                         intel_handle_vblank(dev_priv, pipe);
1449
1450                 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1451                         blc_event = true;
1452
1453                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1454                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1455
1456                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1457                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1458         }
1459
1460         if (blc_event || (iir & I915_ASLE_INTERRUPT))
1461                 intel_opregion_asle_intr(dev_priv);
1462
1463         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1464                 gmbus_irq_handler(dev_priv);
1465 }
1466
1467 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1468                                             u32 pipe_stats[I915_MAX_PIPES])
1469 {
1470         enum pipe pipe;
1471
1472         for_each_pipe(dev_priv, pipe) {
1473                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1474                         intel_handle_vblank(dev_priv, pipe);
1475
1476                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1477                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1478
1479                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1480                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1481         }
1482
1483         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1484                 gmbus_irq_handler(dev_priv);
1485 }
1486
1487 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1488 {
1489         u32 hotplug_status = 0, hotplug_status_mask;
1490         int i;
1491
1492         if (IS_G4X(dev_priv) ||
1493             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1494                 hotplug_status_mask = HOTPLUG_INT_STATUS_G4X |
1495                         DP_AUX_CHANNEL_MASK_INT_STATUS_G4X;
1496         else
1497                 hotplug_status_mask = HOTPLUG_INT_STATUS_I915;
1498
1499         /*
1500          * We absolutely have to clear all the pending interrupt
1501          * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port
1502          * interrupt bit won't have an edge, and the i965/g4x
1503          * edge triggered IIR will not notice that an interrupt
1504          * is still pending. We can't use PORT_HOTPLUG_EN to
1505          * guarantee the edge as the act of toggling the enable
1506          * bits can itself generate a new hotplug interrupt :(
1507          */
1508         for (i = 0; i < 10; i++) {
1509                 u32 tmp = I915_READ(PORT_HOTPLUG_STAT) & hotplug_status_mask;
1510
1511                 if (tmp == 0)
1512                         return hotplug_status;
1513
1514                 hotplug_status |= tmp;
1515                 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1516         }
1517
1518         drm_WARN_ONCE(&dev_priv->drm, 1,
1519                       "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
1520                       I915_READ(PORT_HOTPLUG_STAT));
1521
1522         return hotplug_status;
1523 }
1524
1525 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1526                                  u32 hotplug_status)
1527 {
1528         u32 pin_mask = 0, long_mask = 0;
1529         u32 hotplug_trigger;
1530
1531         if (IS_G4X(dev_priv) ||
1532             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1533                 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1534         else
1535                 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1536
1537         if (hotplug_trigger) {
1538                 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1539                                    hotplug_trigger, hotplug_trigger,
1540                                    dev_priv->hotplug.hpd,
1541                                    i9xx_port_hotplug_long_detect);
1542
1543                 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1544         }
1545
1546         if ((IS_G4X(dev_priv) ||
1547              IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1548             hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1549                 dp_aux_irq_handler(dev_priv);
1550 }
1551
1552 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1553 {
1554         struct drm_i915_private *dev_priv = arg;
1555         irqreturn_t ret = IRQ_NONE;
1556
1557         if (!intel_irqs_enabled(dev_priv))
1558                 return IRQ_NONE;
1559
1560         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1561         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1562
1563         do {
1564                 u32 iir, gt_iir, pm_iir;
1565                 u32 pipe_stats[I915_MAX_PIPES] = {};
1566                 u32 hotplug_status = 0;
1567                 u32 ier = 0;
1568
1569                 gt_iir = I915_READ(GTIIR);
1570                 pm_iir = I915_READ(GEN6_PMIIR);
1571                 iir = I915_READ(VLV_IIR);
1572
1573                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1574                         break;
1575
1576                 ret = IRQ_HANDLED;
1577
1578                 /*
1579                  * Theory on interrupt generation, based on empirical evidence:
1580                  *
1581                  * x = ((VLV_IIR & VLV_IER) ||
1582                  *      (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1583                  *       (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1584                  *
1585                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1586                  * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1587                  * guarantee the CPU interrupt will be raised again even if we
1588                  * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1589                  * bits this time around.
1590                  */
1591                 I915_WRITE(VLV_MASTER_IER, 0);
1592                 ier = I915_READ(VLV_IER);
1593                 I915_WRITE(VLV_IER, 0);
1594
1595                 if (gt_iir)
1596                         I915_WRITE(GTIIR, gt_iir);
1597                 if (pm_iir)
1598                         I915_WRITE(GEN6_PMIIR, pm_iir);
1599
1600                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1601                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1602
1603                 /* Call regardless, as some status bits might not be
1604                  * signalled in iir */
1605                 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1606
1607                 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1608                            I915_LPE_PIPE_B_INTERRUPT))
1609                         intel_lpe_audio_irq_handler(dev_priv);
1610
1611                 /*
1612                  * VLV_IIR is single buffered, and reflects the level
1613                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1614                  */
1615                 if (iir)
1616                         I915_WRITE(VLV_IIR, iir);
1617
1618                 I915_WRITE(VLV_IER, ier);
1619                 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1620
1621                 if (gt_iir)
1622                         gen6_gt_irq_handler(&dev_priv->gt, gt_iir);
1623                 if (pm_iir)
1624                         gen6_rps_irq_handler(&dev_priv->gt.rps, pm_iir);
1625
1626                 if (hotplug_status)
1627                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1628
1629                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1630         } while (0);
1631
1632         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1633
1634         return ret;
1635 }
1636
1637 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1638 {
1639         struct drm_i915_private *dev_priv = arg;
1640         irqreturn_t ret = IRQ_NONE;
1641
1642         if (!intel_irqs_enabled(dev_priv))
1643                 return IRQ_NONE;
1644
1645         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1646         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1647
1648         do {
1649                 u32 master_ctl, iir;
1650                 u32 pipe_stats[I915_MAX_PIPES] = {};
1651                 u32 hotplug_status = 0;
1652                 u32 ier = 0;
1653
1654                 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1655                 iir = I915_READ(VLV_IIR);
1656
1657                 if (master_ctl == 0 && iir == 0)
1658                         break;
1659
1660                 ret = IRQ_HANDLED;
1661
1662                 /*
1663                  * Theory on interrupt generation, based on empirical evidence:
1664                  *
1665                  * x = ((VLV_IIR & VLV_IER) ||
1666                  *      ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1667                  *       (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1668                  *
1669                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1670                  * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
1671                  * guarantee the CPU interrupt will be raised again even if we
1672                  * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
1673                  * bits this time around.
1674                  */
1675                 I915_WRITE(GEN8_MASTER_IRQ, 0);
1676                 ier = I915_READ(VLV_IER);
1677                 I915_WRITE(VLV_IER, 0);
1678
1679                 gen8_gt_irq_handler(&dev_priv->gt, master_ctl);
1680
1681                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1682                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1683
1684                 /* Call regardless, as some status bits might not be
1685                  * signalled in iir */
1686                 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1687
1688                 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1689                            I915_LPE_PIPE_B_INTERRUPT |
1690                            I915_LPE_PIPE_C_INTERRUPT))
1691                         intel_lpe_audio_irq_handler(dev_priv);
1692
1693                 /*
1694                  * VLV_IIR is single buffered, and reflects the level
1695                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1696                  */
1697                 if (iir)
1698                         I915_WRITE(VLV_IIR, iir);
1699
1700                 I915_WRITE(VLV_IER, ier);
1701                 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1702
1703                 if (hotplug_status)
1704                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1705
1706                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1707         } while (0);
1708
1709         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1710
1711         return ret;
1712 }
1713
1714 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1715                                 u32 hotplug_trigger)
1716 {
1717         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1718
1719         /*
1720          * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
1721          * unless we touch the hotplug register, even if hotplug_trigger is
1722          * zero. Not acking leads to "The master control interrupt lied (SDE)!"
1723          * errors.
1724          */
1725         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1726         if (!hotplug_trigger) {
1727                 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
1728                         PORTD_HOTPLUG_STATUS_MASK |
1729                         PORTC_HOTPLUG_STATUS_MASK |
1730                         PORTB_HOTPLUG_STATUS_MASK;
1731                 dig_hotplug_reg &= ~mask;
1732         }
1733
1734         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1735         if (!hotplug_trigger)
1736                 return;
1737
1738         intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1739                            hotplug_trigger, dig_hotplug_reg,
1740                            dev_priv->hotplug.pch_hpd,
1741                            pch_port_hotplug_long_detect);
1742
1743         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1744 }
1745
1746 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1747 {
1748         enum pipe pipe;
1749         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1750
1751         ibx_hpd_irq_handler(dev_priv, hotplug_trigger);
1752
1753         if (pch_iir & SDE_AUDIO_POWER_MASK) {
1754                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1755                                SDE_AUDIO_POWER_SHIFT);
1756                 drm_dbg(&dev_priv->drm, "PCH audio power change on port %d\n",
1757                         port_name(port));
1758         }
1759
1760         if (pch_iir & SDE_AUX_MASK)
1761                 dp_aux_irq_handler(dev_priv);
1762
1763         if (pch_iir & SDE_GMBUS)
1764                 gmbus_irq_handler(dev_priv);
1765
1766         if (pch_iir & SDE_AUDIO_HDCP_MASK)
1767                 drm_dbg(&dev_priv->drm, "PCH HDCP audio interrupt\n");
1768
1769         if (pch_iir & SDE_AUDIO_TRANS_MASK)
1770                 drm_dbg(&dev_priv->drm, "PCH transcoder audio interrupt\n");
1771
1772         if (pch_iir & SDE_POISON)
1773                 drm_err(&dev_priv->drm, "PCH poison interrupt\n");
1774
1775         if (pch_iir & SDE_FDI_MASK) {
1776                 for_each_pipe(dev_priv, pipe)
1777                         drm_dbg(&dev_priv->drm, "  pipe %c FDI IIR: 0x%08x\n",
1778                                 pipe_name(pipe),
1779                                 I915_READ(FDI_RX_IIR(pipe)));
1780         }
1781
1782         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1783                 drm_dbg(&dev_priv->drm, "PCH transcoder CRC done interrupt\n");
1784
1785         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1786                 drm_dbg(&dev_priv->drm,
1787                         "PCH transcoder CRC error interrupt\n");
1788
1789         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1790                 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
1791
1792         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1793                 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
1794 }
1795
1796 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
1797 {
1798         u32 err_int = I915_READ(GEN7_ERR_INT);
1799         enum pipe pipe;
1800
1801         if (err_int & ERR_INT_POISON)
1802                 drm_err(&dev_priv->drm, "Poison interrupt\n");
1803
1804         for_each_pipe(dev_priv, pipe) {
1805                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
1806                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1807
1808                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1809                         if (IS_IVYBRIDGE(dev_priv))
1810                                 ivb_pipe_crc_irq_handler(dev_priv, pipe);
1811                         else
1812                                 hsw_pipe_crc_irq_handler(dev_priv, pipe);
1813                 }
1814         }
1815
1816         I915_WRITE(GEN7_ERR_INT, err_int);
1817 }
1818
1819 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
1820 {
1821         u32 serr_int = I915_READ(SERR_INT);
1822         enum pipe pipe;
1823
1824         if (serr_int & SERR_INT_POISON)
1825                 drm_err(&dev_priv->drm, "PCH poison interrupt\n");
1826
1827         for_each_pipe(dev_priv, pipe)
1828                 if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe))
1829                         intel_pch_fifo_underrun_irq_handler(dev_priv, pipe);
1830
1831         I915_WRITE(SERR_INT, serr_int);
1832 }
1833
1834 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1835 {
1836         enum pipe pipe;
1837         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1838
1839         ibx_hpd_irq_handler(dev_priv, hotplug_trigger);
1840
1841         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1842                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1843                                SDE_AUDIO_POWER_SHIFT_CPT);
1844                 drm_dbg(&dev_priv->drm, "PCH audio power change on port %c\n",
1845                         port_name(port));
1846         }
1847
1848         if (pch_iir & SDE_AUX_MASK_CPT)
1849                 dp_aux_irq_handler(dev_priv);
1850
1851         if (pch_iir & SDE_GMBUS_CPT)
1852                 gmbus_irq_handler(dev_priv);
1853
1854         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1855                 drm_dbg(&dev_priv->drm, "Audio CP request interrupt\n");
1856
1857         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1858                 drm_dbg(&dev_priv->drm, "Audio CP change interrupt\n");
1859
1860         if (pch_iir & SDE_FDI_MASK_CPT) {
1861                 for_each_pipe(dev_priv, pipe)
1862                         drm_dbg(&dev_priv->drm, "  pipe %c FDI IIR: 0x%08x\n",
1863                                 pipe_name(pipe),
1864                                 I915_READ(FDI_RX_IIR(pipe)));
1865         }
1866
1867         if (pch_iir & SDE_ERROR_CPT)
1868                 cpt_serr_int_handler(dev_priv);
1869 }
1870
1871 static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1872 {
1873         u32 ddi_hotplug_trigger, tc_hotplug_trigger;
1874         u32 pin_mask = 0, long_mask = 0;
1875
1876         if (HAS_PCH_DG1(dev_priv)) {
1877                 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_DG1;
1878                 tc_hotplug_trigger = 0;
1879         } else if (HAS_PCH_TGP(dev_priv)) {
1880                 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
1881                 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
1882         } else if (HAS_PCH_JSP(dev_priv)) {
1883                 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
1884                 tc_hotplug_trigger = 0;
1885         } else if (HAS_PCH_MCC(dev_priv)) {
1886                 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
1887                 tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(TC_PORT_1);
1888         } else {
1889                 drm_WARN(&dev_priv->drm, !HAS_PCH_ICP(dev_priv),
1890                          "Unrecognized PCH type 0x%x\n",
1891                          INTEL_PCH_TYPE(dev_priv));
1892
1893                 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
1894                 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
1895         }
1896
1897         if (ddi_hotplug_trigger) {
1898                 u32 dig_hotplug_reg;
1899
1900                 dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
1901                 I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
1902
1903                 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1904                                    ddi_hotplug_trigger, dig_hotplug_reg,
1905                                    dev_priv->hotplug.pch_hpd,
1906                                    icp_ddi_port_hotplug_long_detect);
1907         }
1908
1909         if (tc_hotplug_trigger) {
1910                 u32 dig_hotplug_reg;
1911
1912                 dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
1913                 I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
1914
1915                 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1916                                    tc_hotplug_trigger, dig_hotplug_reg,
1917                                    dev_priv->hotplug.pch_hpd,
1918                                    icp_tc_port_hotplug_long_detect);
1919         }
1920
1921         if (pin_mask)
1922                 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1923
1924         if (pch_iir & SDE_GMBUS_ICP)
1925                 gmbus_irq_handler(dev_priv);
1926 }
1927
1928 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1929 {
1930         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
1931                 ~SDE_PORTE_HOTPLUG_SPT;
1932         u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
1933         u32 pin_mask = 0, long_mask = 0;
1934
1935         if (hotplug_trigger) {
1936                 u32 dig_hotplug_reg;
1937
1938                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1939                 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1940
1941                 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1942                                    hotplug_trigger, dig_hotplug_reg,
1943                                    dev_priv->hotplug.pch_hpd,
1944                                    spt_port_hotplug_long_detect);
1945         }
1946
1947         if (hotplug2_trigger) {
1948                 u32 dig_hotplug_reg;
1949
1950                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
1951                 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
1952
1953                 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1954                                    hotplug2_trigger, dig_hotplug_reg,
1955                                    dev_priv->hotplug.pch_hpd,
1956                                    spt_port_hotplug2_long_detect);
1957         }
1958
1959         if (pin_mask)
1960                 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1961
1962         if (pch_iir & SDE_GMBUS_CPT)
1963                 gmbus_irq_handler(dev_priv);
1964 }
1965
1966 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
1967                                 u32 hotplug_trigger)
1968 {
1969         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1970
1971         dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
1972         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
1973
1974         intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1975                            hotplug_trigger, dig_hotplug_reg,
1976                            dev_priv->hotplug.hpd,
1977                            ilk_port_hotplug_long_detect);
1978
1979         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1980 }
1981
1982 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
1983                                     u32 de_iir)
1984 {
1985         enum pipe pipe;
1986         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
1987
1988         if (hotplug_trigger)
1989                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
1990
1991         if (de_iir & DE_AUX_CHANNEL_A)
1992                 dp_aux_irq_handler(dev_priv);
1993
1994         if (de_iir & DE_GSE)
1995                 intel_opregion_asle_intr(dev_priv);
1996
1997         if (de_iir & DE_POISON)
1998                 drm_err(&dev_priv->drm, "Poison interrupt\n");
1999
2000         for_each_pipe(dev_priv, pipe) {
2001                 if (de_iir & DE_PIPE_VBLANK(pipe))
2002                         intel_handle_vblank(dev_priv, pipe);
2003
2004                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2005                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2006
2007                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2008                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2009         }
2010
2011         /* check event from PCH */
2012         if (de_iir & DE_PCH_EVENT) {
2013                 u32 pch_iir = I915_READ(SDEIIR);
2014
2015                 if (HAS_PCH_CPT(dev_priv))
2016                         cpt_irq_handler(dev_priv, pch_iir);
2017                 else
2018                         ibx_irq_handler(dev_priv, pch_iir);
2019
2020                 /* should clear PCH hotplug event before clear CPU irq */
2021                 I915_WRITE(SDEIIR, pch_iir);
2022         }
2023
2024         if (IS_GEN(dev_priv, 5) && de_iir & DE_PCU_EVENT)
2025                 gen5_rps_irq_handler(&dev_priv->gt.rps);
2026 }
2027
2028 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2029                                     u32 de_iir)
2030 {
2031         enum pipe pipe;
2032         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2033
2034         if (hotplug_trigger)
2035                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
2036
2037         if (de_iir & DE_ERR_INT_IVB)
2038                 ivb_err_int_handler(dev_priv);
2039
2040         if (de_iir & DE_EDP_PSR_INT_HSW) {
2041                 u32 psr_iir = I915_READ(EDP_PSR_IIR);
2042
2043                 intel_psr_irq_handler(dev_priv, psr_iir);
2044                 I915_WRITE(EDP_PSR_IIR, psr_iir);
2045         }
2046
2047         if (de_iir & DE_AUX_CHANNEL_A_IVB)
2048                 dp_aux_irq_handler(dev_priv);
2049
2050         if (de_iir & DE_GSE_IVB)
2051                 intel_opregion_asle_intr(dev_priv);
2052
2053         for_each_pipe(dev_priv, pipe) {
2054                 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
2055                         intel_handle_vblank(dev_priv, pipe);
2056         }
2057
2058         /* check event from PCH */
2059         if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2060                 u32 pch_iir = I915_READ(SDEIIR);
2061
2062                 cpt_irq_handler(dev_priv, pch_iir);
2063
2064                 /* clear PCH hotplug event before clear CPU irq */
2065                 I915_WRITE(SDEIIR, pch_iir);
2066         }
2067 }
2068
2069 /*
2070  * To handle irqs with the minimum potential races with fresh interrupts, we:
2071  * 1 - Disable Master Interrupt Control.
2072  * 2 - Find the source(s) of the interrupt.
2073  * 3 - Clear the Interrupt Identity bits (IIR).
2074  * 4 - Process the interrupt(s) that had bits set in the IIRs.
2075  * 5 - Re-enable Master Interrupt Control.
2076  */
2077 static irqreturn_t ilk_irq_handler(int irq, void *arg)
2078 {
2079         struct drm_i915_private *i915 = arg;
2080         void __iomem * const regs = i915->uncore.regs;
2081         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2082         irqreturn_t ret = IRQ_NONE;
2083
2084         if (unlikely(!intel_irqs_enabled(i915)))
2085                 return IRQ_NONE;
2086
2087         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2088         disable_rpm_wakeref_asserts(&i915->runtime_pm);
2089
2090         /* disable master interrupt before clearing iir  */
2091         de_ier = raw_reg_read(regs, DEIER);
2092         raw_reg_write(regs, DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2093
2094         /* Disable south interrupts. We'll only write to SDEIIR once, so further
2095          * interrupts will will be stored on its back queue, and then we'll be
2096          * able to process them after we restore SDEIER (as soon as we restore
2097          * it, we'll get an interrupt if SDEIIR still has something to process
2098          * due to its back queue). */
2099         if (!HAS_PCH_NOP(i915)) {
2100                 sde_ier = raw_reg_read(regs, SDEIER);
2101                 raw_reg_write(regs, SDEIER, 0);
2102         }
2103
2104         /* Find, clear, then process each source of interrupt */
2105
2106         gt_iir = raw_reg_read(regs, GTIIR);
2107         if (gt_iir) {
2108                 raw_reg_write(regs, GTIIR, gt_iir);
2109                 if (INTEL_GEN(i915) >= 6)
2110                         gen6_gt_irq_handler(&i915->gt, gt_iir);
2111                 else
2112                         gen5_gt_irq_handler(&i915->gt, gt_iir);
2113                 ret = IRQ_HANDLED;
2114         }
2115
2116         de_iir = raw_reg_read(regs, DEIIR);
2117         if (de_iir) {
2118                 raw_reg_write(regs, DEIIR, de_iir);
2119                 if (INTEL_GEN(i915) >= 7)
2120                         ivb_display_irq_handler(i915, de_iir);
2121                 else
2122                         ilk_display_irq_handler(i915, de_iir);
2123                 ret = IRQ_HANDLED;
2124         }
2125
2126         if (INTEL_GEN(i915) >= 6) {
2127                 u32 pm_iir = raw_reg_read(regs, GEN6_PMIIR);
2128                 if (pm_iir) {
2129                         raw_reg_write(regs, GEN6_PMIIR, pm_iir);
2130                         gen6_rps_irq_handler(&i915->gt.rps, pm_iir);
2131                         ret = IRQ_HANDLED;
2132                 }
2133         }
2134
2135         raw_reg_write(regs, DEIER, de_ier);
2136         if (sde_ier)
2137                 raw_reg_write(regs, SDEIER, sde_ier);
2138
2139         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2140         enable_rpm_wakeref_asserts(&i915->runtime_pm);
2141
2142         return ret;
2143 }
2144
2145 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2146                                 u32 hotplug_trigger)
2147 {
2148         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2149
2150         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2151         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2152
2153         intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2154                            hotplug_trigger, dig_hotplug_reg,
2155                            dev_priv->hotplug.hpd,
2156                            bxt_port_hotplug_long_detect);
2157
2158         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2159 }
2160
2161 static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
2162 {
2163         u32 pin_mask = 0, long_mask = 0;
2164         u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
2165         u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;
2166
2167         if (trigger_tc) {
2168                 u32 dig_hotplug_reg;
2169
2170                 dig_hotplug_reg = I915_READ(GEN11_TC_HOTPLUG_CTL);
2171                 I915_WRITE(GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg);
2172
2173                 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2174                                    trigger_tc, dig_hotplug_reg,
2175                                    dev_priv->hotplug.hpd,
2176                                    gen11_port_hotplug_long_detect);
2177         }
2178
2179         if (trigger_tbt) {
2180                 u32 dig_hotplug_reg;
2181
2182                 dig_hotplug_reg = I915_READ(GEN11_TBT_HOTPLUG_CTL);
2183                 I915_WRITE(GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg);
2184
2185                 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2186                                    trigger_tbt, dig_hotplug_reg,
2187                                    dev_priv->hotplug.hpd,
2188                                    gen11_port_hotplug_long_detect);
2189         }
2190
2191         if (pin_mask)
2192                 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2193         else
2194                 drm_err(&dev_priv->drm,
2195                         "Unexpected DE HPD interrupt 0x%08x\n", iir);
2196 }
2197
2198 static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
2199 {
2200         u32 mask;
2201
2202         if (INTEL_GEN(dev_priv) >= 12)
2203                 return TGL_DE_PORT_AUX_DDIA |
2204                         TGL_DE_PORT_AUX_DDIB |
2205                         TGL_DE_PORT_AUX_DDIC |
2206                         TGL_DE_PORT_AUX_USBC1 |
2207                         TGL_DE_PORT_AUX_USBC2 |
2208                         TGL_DE_PORT_AUX_USBC3 |
2209                         TGL_DE_PORT_AUX_USBC4 |
2210                         TGL_DE_PORT_AUX_USBC5 |
2211                         TGL_DE_PORT_AUX_USBC6;
2212
2213
2214         mask = GEN8_AUX_CHANNEL_A;
2215         if (INTEL_GEN(dev_priv) >= 9)
2216                 mask |= GEN9_AUX_CHANNEL_B |
2217                         GEN9_AUX_CHANNEL_C |
2218                         GEN9_AUX_CHANNEL_D;
2219
2220         if (IS_CNL_WITH_PORT_F(dev_priv) || IS_GEN(dev_priv, 11))
2221                 mask |= CNL_AUX_CHANNEL_F;
2222
2223         if (IS_GEN(dev_priv, 11))
2224                 mask |= ICL_AUX_CHANNEL_E;
2225
2226         return mask;
2227 }
2228
2229 static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
2230 {
2231         if (IS_ROCKETLAKE(dev_priv))
2232                 return RKL_DE_PIPE_IRQ_FAULT_ERRORS;
2233         else if (INTEL_GEN(dev_priv) >= 11)
2234                 return GEN11_DE_PIPE_IRQ_FAULT_ERRORS;
2235         else if (INTEL_GEN(dev_priv) >= 9)
2236                 return GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2237         else
2238                 return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2239 }
2240
2241 static void
2242 gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
2243 {
2244         bool found = false;
2245
2246         if (iir & GEN8_DE_MISC_GSE) {
2247                 intel_opregion_asle_intr(dev_priv);
2248                 found = true;
2249         }
2250
2251         if (iir & GEN8_DE_EDP_PSR) {
2252                 u32 psr_iir;
2253                 i915_reg_t iir_reg;
2254
2255                 if (INTEL_GEN(dev_priv) >= 12)
2256                         iir_reg = TRANS_PSR_IIR(dev_priv->psr.transcoder);
2257                 else
2258                         iir_reg = EDP_PSR_IIR;
2259
2260                 psr_iir = I915_READ(iir_reg);
2261                 I915_WRITE(iir_reg, psr_iir);
2262
2263                 if (psr_iir)
2264                         found = true;
2265
2266                 intel_psr_irq_handler(dev_priv, psr_iir);
2267         }
2268
2269         if (!found)
2270                 drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt\n");
2271 }
2272
2273 static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
2274                                            u32 te_trigger)
2275 {
2276         enum pipe pipe = INVALID_PIPE;
2277         enum transcoder dsi_trans;
2278         enum port port;
2279         u32 val, tmp;
2280
2281         /*
2282          * Incase of dual link, TE comes from DSI_1
2283          * this is to check if dual link is enabled
2284          */
2285         val = I915_READ(TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0));
2286         val &= PORT_SYNC_MODE_ENABLE;
2287
2288         /*
2289          * if dual link is enabled, then read DSI_0
2290          * transcoder registers
2291          */
2292         port = ((te_trigger & DSI1_TE && val) || (te_trigger & DSI0_TE)) ?
2293                                                   PORT_A : PORT_B;
2294         dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1;
2295
2296         /* Check if DSI configured in command mode */
2297         val = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
2298         val = val & OP_MODE_MASK;
2299
2300         if (val != CMD_MODE_NO_GATE && val != CMD_MODE_TE_GATE) {
2301                 drm_err(&dev_priv->drm, "DSI trancoder not configured in command mode\n");
2302                 return;
2303         }
2304
2305         /* Get PIPE for handling VBLANK event */
2306         val = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
2307         switch (val & TRANS_DDI_EDP_INPUT_MASK) {
2308         case TRANS_DDI_EDP_INPUT_A_ON:
2309                 pipe = PIPE_A;
2310                 break;
2311         case TRANS_DDI_EDP_INPUT_B_ONOFF:
2312                 pipe = PIPE_B;
2313                 break;
2314         case TRANS_DDI_EDP_INPUT_C_ONOFF:
2315                 pipe = PIPE_C;
2316                 break;
2317         default:
2318                 drm_err(&dev_priv->drm, "Invalid PIPE\n");
2319                 return;
2320         }
2321
2322         intel_handle_vblank(dev_priv, pipe);
2323
2324         /* clear TE in dsi IIR */
2325         port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A;
2326         tmp = I915_READ(DSI_INTR_IDENT_REG(port));
2327         I915_WRITE(DSI_INTR_IDENT_REG(port), tmp);
2328 }
2329
2330 static irqreturn_t
2331 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2332 {
2333         irqreturn_t ret = IRQ_NONE;
2334         u32 iir;
2335         enum pipe pipe;
2336
2337         if (master_ctl & GEN8_DE_MISC_IRQ) {
2338                 iir = I915_READ(GEN8_DE_MISC_IIR);
2339                 if (iir) {
2340                         I915_WRITE(GEN8_DE_MISC_IIR, iir);
2341                         ret = IRQ_HANDLED;
2342                         gen8_de_misc_irq_handler(dev_priv, iir);
2343                 } else {
2344                         drm_err(&dev_priv->drm,
2345                                 "The master control interrupt lied (DE MISC)!\n");
2346                 }
2347         }
2348
2349         if (INTEL_GEN(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
2350                 iir = I915_READ(GEN11_DE_HPD_IIR);
2351                 if (iir) {
2352                         I915_WRITE(GEN11_DE_HPD_IIR, iir);
2353                         ret = IRQ_HANDLED;
2354                         gen11_hpd_irq_handler(dev_priv, iir);
2355                 } else {
2356                         drm_err(&dev_priv->drm,
2357                                 "The master control interrupt lied, (DE HPD)!\n");
2358                 }
2359         }
2360
2361         if (master_ctl & GEN8_DE_PORT_IRQ) {
2362                 iir = I915_READ(GEN8_DE_PORT_IIR);
2363                 if (iir) {
2364                         u32 tmp_mask;
2365                         bool found = false;
2366
2367                         I915_WRITE(GEN8_DE_PORT_IIR, iir);
2368                         ret = IRQ_HANDLED;
2369
2370                         if (iir & gen8_de_port_aux_mask(dev_priv)) {
2371                                 dp_aux_irq_handler(dev_priv);
2372                                 found = true;
2373                         }
2374
2375                         if (IS_GEN9_LP(dev_priv)) {
2376                                 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2377                                 if (tmp_mask) {
2378                                         bxt_hpd_irq_handler(dev_priv, tmp_mask);
2379                                         found = true;
2380                                 }
2381                         } else if (IS_BROADWELL(dev_priv)) {
2382                                 tmp_mask = iir & BDW_DE_PORT_HOTPLUG_MASK;
2383                                 if (tmp_mask) {
2384                                         ilk_hpd_irq_handler(dev_priv, tmp_mask);
2385                                         found = true;
2386                                 }
2387                         }
2388
2389                         if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2390                                 gmbus_irq_handler(dev_priv);
2391                                 found = true;
2392                         }
2393
2394                         if (INTEL_GEN(dev_priv) >= 11) {
2395                                 tmp_mask = iir & (DSI0_TE | DSI1_TE);
2396                                 if (tmp_mask) {
2397                                         gen11_dsi_te_interrupt_handler(dev_priv, tmp_mask);
2398                                         found = true;
2399                                 }
2400                         }
2401
2402                         if (!found)
2403                                 drm_err(&dev_priv->drm,
2404                                         "Unexpected DE Port interrupt\n");
2405                 }
2406                 else
2407                         drm_err(&dev_priv->drm,
2408                                 "The master control interrupt lied (DE PORT)!\n");
2409         }
2410
2411         for_each_pipe(dev_priv, pipe) {
2412                 u32 fault_errors;
2413
2414                 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2415                         continue;
2416
2417                 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2418                 if (!iir) {
2419                         drm_err(&dev_priv->drm,
2420                                 "The master control interrupt lied (DE PIPE)!\n");
2421                         continue;
2422                 }
2423
2424                 ret = IRQ_HANDLED;
2425                 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2426
2427                 if (iir & GEN8_PIPE_VBLANK)
2428                         intel_handle_vblank(dev_priv, pipe);
2429
2430                 if (iir & GEN9_PIPE_PLANE1_FLIP_DONE)
2431                         flip_done_handler(dev_priv, pipe);
2432
2433                 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2434                         hsw_pipe_crc_irq_handler(dev_priv, pipe);
2435
2436                 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2437                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2438
2439                 fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv);
2440                 if (fault_errors)
2441                         drm_err(&dev_priv->drm,
2442                                 "Fault errors on pipe %c: 0x%08x\n",
2443                                 pipe_name(pipe),
2444                                 fault_errors);
2445         }
2446
2447         if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2448             master_ctl & GEN8_DE_PCH_IRQ) {
2449                 /*
2450                  * FIXME(BDW): Assume for now that the new interrupt handling
2451                  * scheme also closed the SDE interrupt handling race we've seen
2452                  * on older pch-split platforms. But this needs testing.
2453                  */
2454                 iir = I915_READ(SDEIIR);
2455                 if (iir) {
2456                         I915_WRITE(SDEIIR, iir);
2457                         ret = IRQ_HANDLED;
2458
2459                         if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2460                                 icp_irq_handler(dev_priv, iir);
2461                         else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
2462                                 spt_irq_handler(dev_priv, iir);
2463                         else
2464                                 cpt_irq_handler(dev_priv, iir);
2465                 } else {
2466                         /*
2467                          * Like on previous PCH there seems to be something
2468                          * fishy going on with forwarding PCH interrupts.
2469                          */
2470                         drm_dbg(&dev_priv->drm,
2471                                 "The master control interrupt lied (SDE)!\n");
2472                 }
2473         }
2474
2475         return ret;
2476 }
2477
2478 static inline u32 gen8_master_intr_disable(void __iomem * const regs)
2479 {
2480         raw_reg_write(regs, GEN8_MASTER_IRQ, 0);
2481
2482         /*
2483          * Now with master disabled, get a sample of level indications
2484          * for this interrupt. Indications will be cleared on related acks.
2485          * New indications can and will light up during processing,
2486          * and will generate new interrupt after enabling master.
2487          */
2488         return raw_reg_read(regs, GEN8_MASTER_IRQ);
2489 }
2490
2491 static inline void gen8_master_intr_enable(void __iomem * const regs)
2492 {
2493         raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2494 }
2495
2496 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2497 {
2498         struct drm_i915_private *dev_priv = arg;
2499         void __iomem * const regs = dev_priv->uncore.regs;
2500         u32 master_ctl;
2501
2502         if (!intel_irqs_enabled(dev_priv))
2503                 return IRQ_NONE;
2504
2505         master_ctl = gen8_master_intr_disable(regs);
2506         if (!master_ctl) {
2507                 gen8_master_intr_enable(regs);
2508                 return IRQ_NONE;
2509         }
2510
2511         /* Find, queue (onto bottom-halves), then clear each source */
2512         gen8_gt_irq_handler(&dev_priv->gt, master_ctl);
2513
2514         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2515         if (master_ctl & ~GEN8_GT_IRQS) {
2516                 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2517                 gen8_de_irq_handler(dev_priv, master_ctl);
2518                 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2519         }
2520
2521         gen8_master_intr_enable(regs);
2522
2523         return IRQ_HANDLED;
2524 }
2525
2526 static u32
2527 gen11_gu_misc_irq_ack(struct intel_gt *gt, const u32 master_ctl)
2528 {
2529         void __iomem * const regs = gt->uncore->regs;
2530         u32 iir;
2531
2532         if (!(master_ctl & GEN11_GU_MISC_IRQ))
2533                 return 0;
2534
2535         iir = raw_reg_read(regs, GEN11_GU_MISC_IIR);
2536         if (likely(iir))
2537                 raw_reg_write(regs, GEN11_GU_MISC_IIR, iir);
2538
2539         return iir;
2540 }
2541
2542 static void
2543 gen11_gu_misc_irq_handler(struct intel_gt *gt, const u32 iir)
2544 {
2545         if (iir & GEN11_GU_MISC_GSE)
2546                 intel_opregion_asle_intr(gt->i915);
2547 }
2548
2549 static inline u32 gen11_master_intr_disable(void __iomem * const regs)
2550 {
2551         raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0);
2552
2553         /*
2554          * Now with master disabled, get a sample of level indications
2555          * for this interrupt. Indications will be cleared on related acks.
2556          * New indications can and will light up during processing,
2557          * and will generate new interrupt after enabling master.
2558          */
2559         return raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
2560 }
2561
2562 static inline void gen11_master_intr_enable(void __iomem * const regs)
2563 {
2564         raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
2565 }
2566
2567 static void
2568 gen11_display_irq_handler(struct drm_i915_private *i915)
2569 {
2570         void __iomem * const regs = i915->uncore.regs;
2571         const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
2572
2573         disable_rpm_wakeref_asserts(&i915->runtime_pm);
2574         /*
2575          * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
2576          * for the display related bits.
2577          */
2578         raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 0x0);
2579         gen8_de_irq_handler(i915, disp_ctl);
2580         raw_reg_write(regs, GEN11_DISPLAY_INT_CTL,
2581                       GEN11_DISPLAY_IRQ_ENABLE);
2582
2583         enable_rpm_wakeref_asserts(&i915->runtime_pm);
2584 }
2585
2586 static __always_inline irqreturn_t
2587 __gen11_irq_handler(struct drm_i915_private * const i915,
2588                     u32 (*intr_disable)(void __iomem * const regs),
2589                     void (*intr_enable)(void __iomem * const regs))
2590 {
2591         void __iomem * const regs = i915->uncore.regs;
2592         struct intel_gt *gt = &i915->gt;
2593         u32 master_ctl;
2594         u32 gu_misc_iir;
2595
2596         if (!intel_irqs_enabled(i915))
2597                 return IRQ_NONE;
2598
2599         master_ctl = intr_disable(regs);
2600         if (!master_ctl) {
2601                 intr_enable(regs);
2602                 return IRQ_NONE;
2603         }
2604
2605         /* Find, queue (onto bottom-halves), then clear each source */
2606         gen11_gt_irq_handler(gt, master_ctl);
2607
2608         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2609         if (master_ctl & GEN11_DISPLAY_IRQ)
2610                 gen11_display_irq_handler(i915);
2611
2612         gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
2613
2614         intr_enable(regs);
2615
2616         gen11_gu_misc_irq_handler(gt, gu_misc_iir);
2617
2618         return IRQ_HANDLED;
2619 }
2620
2621 static irqreturn_t gen11_irq_handler(int irq, void *arg)
2622 {
2623         return __gen11_irq_handler(arg,
2624                                    gen11_master_intr_disable,
2625                                    gen11_master_intr_enable);
2626 }
2627
2628 static u32 dg1_master_intr_disable_and_ack(void __iomem * const regs)
2629 {
2630         u32 val;
2631
2632         /* First disable interrupts */
2633         raw_reg_write(regs, DG1_MSTR_UNIT_INTR, 0);
2634
2635         /* Get the indication levels and ack the master unit */
2636         val = raw_reg_read(regs, DG1_MSTR_UNIT_INTR);
2637         if (unlikely(!val))
2638                 return 0;
2639
2640         raw_reg_write(regs, DG1_MSTR_UNIT_INTR, val);
2641
2642         /*
2643          * Now with master disabled, get a sample of level indications
2644          * for this interrupt and ack them right away - we keep GEN11_MASTER_IRQ
2645          * out as this bit doesn't exist anymore for DG1
2646          */
2647         val = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ) & ~GEN11_MASTER_IRQ;
2648         if (unlikely(!val))
2649                 return 0;
2650
2651         raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, val);
2652
2653         return val;
2654 }
2655
2656 static inline void dg1_master_intr_enable(void __iomem * const regs)
2657 {
2658         raw_reg_write(regs, DG1_MSTR_UNIT_INTR, DG1_MSTR_IRQ);
2659 }
2660
2661 static irqreturn_t dg1_irq_handler(int irq, void *arg)
2662 {
2663         return __gen11_irq_handler(arg,
2664                                    dg1_master_intr_disable_and_ack,
2665                                    dg1_master_intr_enable);
2666 }
2667
2668 /* Called from drm generic code, passed 'crtc' which
2669  * we use as a pipe index
2670  */
2671 int i8xx_enable_vblank(struct drm_crtc *crtc)
2672 {
2673         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2674         enum pipe pipe = to_intel_crtc(crtc)->pipe;
2675         unsigned long irqflags;
2676
2677         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2678         i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2679         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2680
2681         return 0;
2682 }
2683
2684 int i915gm_enable_vblank(struct drm_crtc *crtc)
2685 {
2686         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2687
2688         /*
2689          * Vblank interrupts fail to wake the device up from C2+.
2690          * Disabling render clock gating during C-states avoids
2691          * the problem. There is a small power cost so we do this
2692          * only when vblank interrupts are actually enabled.
2693          */
2694         if (dev_priv->vblank_enabled++ == 0)
2695                 I915_WRITE(SCPD0, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
2696
2697         return i8xx_enable_vblank(crtc);
2698 }
2699
2700 int i965_enable_vblank(struct drm_crtc *crtc)
2701 {
2702         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2703         enum pipe pipe = to_intel_crtc(crtc)->pipe;
2704         unsigned long irqflags;
2705
2706         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2707         i915_enable_pipestat(dev_priv, pipe,
2708                              PIPE_START_VBLANK_INTERRUPT_STATUS);
2709         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2710
2711         return 0;
2712 }
2713
2714 int ilk_enable_vblank(struct drm_crtc *crtc)
2715 {
2716         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2717         enum pipe pipe = to_intel_crtc(crtc)->pipe;
2718         unsigned long irqflags;
2719         u32 bit = INTEL_GEN(dev_priv) >= 7 ?
2720                 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2721
2722         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2723         ilk_enable_display_irq(dev_priv, bit);
2724         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2725
2726         /* Even though there is no DMC, frame counter can get stuck when
2727          * PSR is active as no frames are generated.
2728          */
2729         if (HAS_PSR(dev_priv))
2730                 drm_crtc_vblank_restore(crtc);
2731
2732         return 0;
2733 }
2734
2735 static bool gen11_dsi_configure_te(struct intel_crtc *intel_crtc,
2736                                    bool enable)
2737 {
2738         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
2739         enum port port;
2740         u32 tmp;
2741
2742         if (!(intel_crtc->mode_flags &
2743             (I915_MODE_FLAG_DSI_USE_TE1 | I915_MODE_FLAG_DSI_USE_TE0)))
2744                 return false;
2745
2746         /* for dual link cases we consider TE from slave */
2747         if (intel_crtc->mode_flags & I915_MODE_FLAG_DSI_USE_TE1)
2748                 port = PORT_B;
2749         else
2750                 port = PORT_A;
2751
2752         tmp =  I915_READ(DSI_INTR_MASK_REG(port));
2753         if (enable)
2754                 tmp &= ~DSI_TE_EVENT;
2755         else
2756                 tmp |= DSI_TE_EVENT;
2757
2758         I915_WRITE(DSI_INTR_MASK_REG(port), tmp);
2759
2760         tmp = I915_READ(DSI_INTR_IDENT_REG(port));
2761         I915_WRITE(DSI_INTR_IDENT_REG(port), tmp);
2762
2763         return true;
2764 }
2765
2766 int bdw_enable_vblank(struct drm_crtc *crtc)
2767 {
2768         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2769         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2770         enum pipe pipe = intel_crtc->pipe;
2771         unsigned long irqflags;
2772
2773         if (gen11_dsi_configure_te(intel_crtc, true))
2774                 return 0;
2775
2776         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2777         bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2778         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2779
2780         /* Even if there is no DMC, frame counter can get stuck when
2781          * PSR is active as no frames are generated, so check only for PSR.
2782          */
2783         if (HAS_PSR(dev_priv))
2784                 drm_crtc_vblank_restore(crtc);
2785
2786         return 0;
2787 }
2788
2789 void skl_enable_flip_done(struct intel_crtc *crtc)
2790 {
2791         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2792         enum pipe pipe = crtc->pipe;
2793         unsigned long irqflags;
2794
2795         spin_lock_irqsave(&i915->irq_lock, irqflags);
2796
2797         bdw_enable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
2798
2799         spin_unlock_irqrestore(&i915->irq_lock, irqflags);
2800 }
2801
2802 /* Called from drm generic code, passed 'crtc' which
2803  * we use as a pipe index
2804  */
2805 void i8xx_disable_vblank(struct drm_crtc *crtc)
2806 {
2807         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2808         enum pipe pipe = to_intel_crtc(crtc)->pipe;
2809         unsigned long irqflags;
2810
2811         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2812         i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2813         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2814 }
2815
2816 void i915gm_disable_vblank(struct drm_crtc *crtc)
2817 {
2818         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2819
2820         i8xx_disable_vblank(crtc);
2821
2822         if (--dev_priv->vblank_enabled == 0)
2823                 I915_WRITE(SCPD0, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
2824 }
2825
2826 void i965_disable_vblank(struct drm_crtc *crtc)
2827 {
2828         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2829         enum pipe pipe = to_intel_crtc(crtc)->pipe;
2830         unsigned long irqflags;
2831
2832         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2833         i915_disable_pipestat(dev_priv, pipe,
2834                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2835         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2836 }
2837
2838 void ilk_disable_vblank(struct drm_crtc *crtc)
2839 {
2840         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2841         enum pipe pipe = to_intel_crtc(crtc)->pipe;
2842         unsigned long irqflags;
2843         u32 bit = INTEL_GEN(dev_priv) >= 7 ?
2844                 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2845
2846         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2847         ilk_disable_display_irq(dev_priv, bit);
2848         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2849 }
2850
2851 void bdw_disable_vblank(struct drm_crtc *crtc)
2852 {
2853         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2854         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2855         enum pipe pipe = intel_crtc->pipe;
2856         unsigned long irqflags;
2857
2858         if (gen11_dsi_configure_te(intel_crtc, false))
2859                 return;
2860
2861         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2862         bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2863         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2864 }
2865
2866 void skl_disable_flip_done(struct intel_crtc *crtc)
2867 {
2868         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2869         enum pipe pipe = crtc->pipe;
2870         unsigned long irqflags;
2871
2872         spin_lock_irqsave(&i915->irq_lock, irqflags);
2873
2874         bdw_disable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
2875
2876         spin_unlock_irqrestore(&i915->irq_lock, irqflags);
2877 }
2878
2879 static void ibx_irq_reset(struct drm_i915_private *dev_priv)
2880 {
2881         struct intel_uncore *uncore = &dev_priv->uncore;
2882
2883         if (HAS_PCH_NOP(dev_priv))
2884                 return;
2885
2886         GEN3_IRQ_RESET(uncore, SDE);
2887
2888         if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
2889                 I915_WRITE(SERR_INT, 0xffffffff);
2890 }
2891
2892 /*
2893  * SDEIER is also touched by the interrupt handler to work around missed PCH
2894  * interrupts. Hence we can't update it after the interrupt handler is enabled -
2895  * instead we unconditionally enable all PCH interrupt sources here, but then
2896  * only unmask them as needed with SDEIMR.
2897  *
2898  * This function needs to be called before interrupts are enabled.
2899  */
2900 static void ibx_irq_pre_postinstall(struct drm_i915_private *dev_priv)
2901 {
2902         if (HAS_PCH_NOP(dev_priv))
2903                 return;
2904
2905         drm_WARN_ON(&dev_priv->drm, I915_READ(SDEIER) != 0);
2906         I915_WRITE(SDEIER, 0xffffffff);
2907         POSTING_READ(SDEIER);
2908 }
2909
2910 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
2911 {
2912         struct intel_uncore *uncore = &dev_priv->uncore;
2913
2914         if (IS_CHERRYVIEW(dev_priv))
2915                 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
2916         else
2917                 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK);
2918
2919         i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
2920         intel_uncore_write(uncore, PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2921
2922         i9xx_pipestat_irq_reset(dev_priv);
2923
2924         GEN3_IRQ_RESET(uncore, VLV_);
2925         dev_priv->irq_mask = ~0u;
2926 }
2927
2928 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
2929 {
2930         struct intel_uncore *uncore = &dev_priv->uncore;
2931
2932         u32 pipestat_mask;
2933         u32 enable_mask;
2934         enum pipe pipe;
2935
2936         pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS;
2937
2938         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
2939         for_each_pipe(dev_priv, pipe)
2940                 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
2941
2942         enable_mask = I915_DISPLAY_PORT_INTERRUPT |
2943                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2944                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2945                 I915_LPE_PIPE_A_INTERRUPT |
2946                 I915_LPE_PIPE_B_INTERRUPT;
2947
2948         if (IS_CHERRYVIEW(dev_priv))
2949                 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT |
2950                         I915_LPE_PIPE_C_INTERRUPT;
2951
2952         drm_WARN_ON(&dev_priv->drm, dev_priv->irq_mask != ~0u);
2953
2954         dev_priv->irq_mask = ~enable_mask;
2955
2956         GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask);
2957 }
2958
2959 /* drm_dma.h hooks
2960 */
2961 static void ilk_irq_reset(struct drm_i915_private *dev_priv)
2962 {
2963         struct intel_uncore *uncore = &dev_priv->uncore;
2964
2965         GEN3_IRQ_RESET(uncore, DE);
2966         dev_priv->irq_mask = ~0u;
2967
2968         if (IS_GEN(dev_priv, 7))
2969                 intel_uncore_write(uncore, GEN7_ERR_INT, 0xffffffff);
2970
2971         if (IS_HASWELL(dev_priv)) {
2972                 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
2973                 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
2974         }
2975
2976         gen5_gt_irq_reset(&dev_priv->gt);
2977
2978         ibx_irq_reset(dev_priv);
2979 }
2980
2981 static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
2982 {
2983         I915_WRITE(VLV_MASTER_IER, 0);
2984         POSTING_READ(VLV_MASTER_IER);
2985
2986         gen5_gt_irq_reset(&dev_priv->gt);
2987
2988         spin_lock_irq(&dev_priv->irq_lock);
2989         if (dev_priv->display_irqs_enabled)
2990                 vlv_display_irq_reset(dev_priv);
2991         spin_unlock_irq(&dev_priv->irq_lock);
2992 }
2993
2994 static void gen8_irq_reset(struct drm_i915_private *dev_priv)
2995 {
2996         struct intel_uncore *uncore = &dev_priv->uncore;
2997         enum pipe pipe;
2998
2999         gen8_master_intr_disable(dev_priv->uncore.regs);
3000
3001         gen8_gt_irq_reset(&dev_priv->gt);
3002
3003         intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
3004         intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
3005
3006         for_each_pipe(dev_priv, pipe)
3007                 if (intel_display_power_is_enabled(dev_priv,
3008                                                    POWER_DOMAIN_PIPE(pipe)))
3009                         GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3010
3011         GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
3012         GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
3013         GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3014
3015         if (HAS_PCH_SPLIT(dev_priv))
3016                 ibx_irq_reset(dev_priv);
3017 }
3018
3019 static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
3020 {
3021         struct intel_uncore *uncore = &dev_priv->uncore;
3022         enum pipe pipe;
3023         u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
3024                 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
3025
3026         intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0);
3027
3028         if (INTEL_GEN(dev_priv) >= 12) {
3029                 enum transcoder trans;
3030
3031                 for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
3032                         enum intel_display_power_domain domain;
3033
3034                         domain = POWER_DOMAIN_TRANSCODER(trans);
3035                         if (!intel_display_power_is_enabled(dev_priv, domain))
3036                                 continue;
3037
3038                         intel_uncore_write(uncore, TRANS_PSR_IMR(trans), 0xffffffff);
3039                         intel_uncore_write(uncore, TRANS_PSR_IIR(trans), 0xffffffff);
3040                 }
3041         } else {
3042                 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
3043                 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
3044         }
3045
3046         for_each_pipe(dev_priv, pipe)
3047                 if (intel_display_power_is_enabled(dev_priv,
3048                                                    POWER_DOMAIN_PIPE(pipe)))
3049                         GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3050
3051         GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
3052         GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
3053         GEN3_IRQ_RESET(uncore, GEN11_DE_HPD_);
3054
3055         if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3056                 GEN3_IRQ_RESET(uncore, SDE);
3057
3058         /* Wa_14010685332:icl,jsl,ehl,tgl,rkl */
3059         if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
3060                 intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
3061                                  SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
3062                 intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
3063                                  SBCLK_RUN_REFCLK_DIS, 0);
3064         }
3065 }
3066
3067 static void gen11_irq_reset(struct drm_i915_private *dev_priv)
3068 {
3069         struct intel_uncore *uncore = &dev_priv->uncore;
3070
3071         if (HAS_MASTER_UNIT_IRQ(dev_priv))
3072                 dg1_master_intr_disable_and_ack(dev_priv->uncore.regs);
3073         else
3074                 gen11_master_intr_disable(dev_priv->uncore.regs);
3075
3076         gen11_gt_irq_reset(&dev_priv->gt);
3077         gen11_display_irq_reset(dev_priv);
3078
3079         GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
3080         GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3081 }
3082
3083 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3084                                      u8 pipe_mask)
3085 {
3086         struct intel_uncore *uncore = &dev_priv->uncore;
3087
3088         u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3089         enum pipe pipe;
3090
3091         if (INTEL_GEN(dev_priv) >= 9)
3092                 extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE;
3093
3094         spin_lock_irq(&dev_priv->irq_lock);
3095
3096         if (!intel_irqs_enabled(dev_priv)) {
3097                 spin_unlock_irq(&dev_priv->irq_lock);
3098                 return;
3099         }
3100
3101         for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3102                 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
3103                                   dev_priv->de_irq_mask[pipe],
3104                                   ~dev_priv->de_irq_mask[pipe] | extra_ier);
3105
3106         spin_unlock_irq(&dev_priv->irq_lock);
3107 }
3108
3109 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3110                                      u8 pipe_mask)
3111 {
3112         struct intel_uncore *uncore = &dev_priv->uncore;
3113         enum pipe pipe;
3114
3115         spin_lock_irq(&dev_priv->irq_lock);
3116
3117         if (!intel_irqs_enabled(dev_priv)) {
3118                 spin_unlock_irq(&dev_priv->irq_lock);
3119                 return;
3120         }
3121
3122         for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3123                 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3124
3125         spin_unlock_irq(&dev_priv->irq_lock);
3126
3127         /* make sure we're done processing display irqs */
3128         intel_synchronize_irq(dev_priv);
3129 }
3130
3131 static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
3132 {
3133         struct intel_uncore *uncore = &dev_priv->uncore;
3134
3135         I915_WRITE(GEN8_MASTER_IRQ, 0);
3136         POSTING_READ(GEN8_MASTER_IRQ);
3137
3138         gen8_gt_irq_reset(&dev_priv->gt);
3139
3140         GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3141
3142         spin_lock_irq(&dev_priv->irq_lock);
3143         if (dev_priv->display_irqs_enabled)
3144                 vlv_display_irq_reset(dev_priv);
3145         spin_unlock_irq(&dev_priv->irq_lock);
3146 }
3147
3148 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
3149                                   const u32 hpd[HPD_NUM_PINS])
3150 {
3151         struct intel_encoder *encoder;
3152         u32 enabled_irqs = 0;
3153
3154         for_each_intel_encoder(&dev_priv->drm, encoder)
3155                 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3156                         enabled_irqs |= hpd[encoder->hpd_pin];
3157
3158         return enabled_irqs;
3159 }
3160
3161 static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv,
3162                                   const u32 hpd[HPD_NUM_PINS])
3163 {
3164         struct intel_encoder *encoder;
3165         u32 hotplug_irqs = 0;
3166
3167         for_each_intel_encoder(&dev_priv->drm, encoder)
3168                 hotplug_irqs |= hpd[encoder->hpd_pin];
3169
3170         return hotplug_irqs;
3171 }
3172
3173 static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
3174 {
3175         u32 hotplug;
3176
3177         /*
3178          * Enable digital hotplug on the PCH, and configure the DP short pulse
3179          * duration to 2ms (which is the minimum in the Display Port spec).
3180          * The pulse duration bits are reserved on LPT+.
3181          */
3182         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3183         hotplug &= ~(PORTB_PULSE_DURATION_MASK |
3184                      PORTC_PULSE_DURATION_MASK |
3185                      PORTD_PULSE_DURATION_MASK);
3186         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3187         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3188         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3189         /*
3190          * When CPU and PCH are on the same package, port A
3191          * HPD must be enabled in both north and south.
3192          */
3193         if (HAS_PCH_LPT_LP(dev_priv))
3194                 hotplug |= PORTA_HOTPLUG_ENABLE;
3195         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3196 }
3197
3198 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3199 {
3200         u32 hotplug_irqs, enabled_irqs;
3201
3202         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3203         hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3204
3205         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3206
3207         ibx_hpd_detection_setup(dev_priv);
3208 }
3209
3210 static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv,
3211                                         u32 enable_mask)
3212 {
3213         u32 hotplug;
3214
3215         hotplug = I915_READ(SHOTPLUG_CTL_DDI);
3216         hotplug |= enable_mask;
3217         I915_WRITE(SHOTPLUG_CTL_DDI, hotplug);
3218 }
3219
3220 static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv,
3221                                        u32 enable_mask)
3222 {
3223         u32 hotplug;
3224
3225         hotplug = I915_READ(SHOTPLUG_CTL_TC);
3226         hotplug |= enable_mask;
3227         I915_WRITE(SHOTPLUG_CTL_TC, hotplug);
3228 }
3229
3230 static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv,
3231                               u32 ddi_enable_mask, u32 tc_enable_mask)
3232 {
3233         u32 hotplug_irqs, enabled_irqs;
3234
3235         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3236         hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3237
3238         if (INTEL_PCH_TYPE(dev_priv) <= PCH_TGP)
3239                 I915_WRITE(SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
3240
3241         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3242
3243         icp_ddi_hpd_detection_setup(dev_priv, ddi_enable_mask);
3244         if (tc_enable_mask)
3245                 icp_tc_hpd_detection_setup(dev_priv, tc_enable_mask);
3246 }
3247
3248 /*
3249  * EHL doesn't need most of gen11_hpd_irq_setup, it's handling only the
3250  * equivalent of SDE.
3251  */
3252 static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv)
3253 {
3254         icp_hpd_irq_setup(dev_priv,
3255                           ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(TC_PORT_1));
3256 }
3257
3258 /*
3259  * JSP behaves exactly the same as MCC above except that port C is mapped to
3260  * the DDI-C pins instead of the TC1 pins.  This means we should follow TGP's
3261  * masks & tables rather than ICP's masks & tables.
3262  */
3263 static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
3264 {
3265         icp_hpd_irq_setup(dev_priv,
3266                           TGP_DDI_HPD_ENABLE_MASK, 0);
3267 }
3268
3269 static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
3270 {
3271         u32 val;
3272
3273         val = I915_READ(SOUTH_CHICKEN1);
3274         val |= (INVERT_DDIA_HPD |
3275                 INVERT_DDIB_HPD |
3276                 INVERT_DDIC_HPD |
3277                 INVERT_DDID_HPD);
3278         I915_WRITE(SOUTH_CHICKEN1, val);
3279
3280         icp_hpd_irq_setup(dev_priv,
3281                           DG1_DDI_HPD_ENABLE_MASK, 0);
3282 }
3283
3284 static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
3285 {
3286         u32 hotplug;
3287
3288         hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL);
3289         hotplug |= GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_1) |
3290                    GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_2) |
3291                    GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_3) |
3292                    GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_4) |
3293                    GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_5) |
3294                    GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_6);
3295         I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
3296
3297         hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
3298         hotplug |= GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_1) |
3299                    GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_2) |
3300                    GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_3) |
3301                    GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_4) |
3302                    GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_5) |
3303                    GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_6);
3304         I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug);
3305 }
3306
3307 static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
3308 {
3309         u32 hotplug_irqs, enabled_irqs;
3310         u32 val;
3311
3312         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
3313         hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
3314
3315         val = I915_READ(GEN11_DE_HPD_IMR);
3316         val &= ~hotplug_irqs;
3317         val |= ~enabled_irqs & hotplug_irqs;
3318         I915_WRITE(GEN11_DE_HPD_IMR, val);
3319         POSTING_READ(GEN11_DE_HPD_IMR);
3320
3321         gen11_hpd_detection_setup(dev_priv);
3322
3323         if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP)
3324                 icp_hpd_irq_setup(dev_priv,
3325                                   TGP_DDI_HPD_ENABLE_MASK, TGP_TC_HPD_ENABLE_MASK);
3326         else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3327                 icp_hpd_irq_setup(dev_priv,
3328                                   ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE_MASK);
3329 }
3330
3331 static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3332 {
3333         u32 val, hotplug;
3334
3335         /* Display WA #1179 WaHardHangonHotPlug: cnp */
3336         if (HAS_PCH_CNP(dev_priv)) {
3337                 val = I915_READ(SOUTH_CHICKEN1);
3338                 val &= ~CHASSIS_CLK_REQ_DURATION_MASK;
3339                 val |= CHASSIS_CLK_REQ_DURATION(0xf);
3340                 I915_WRITE(SOUTH_CHICKEN1, val);
3341         }
3342
3343         /* Enable digital hotplug on the PCH */
3344         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3345         hotplug |= PORTA_HOTPLUG_ENABLE |
3346                    PORTB_HOTPLUG_ENABLE |
3347                    PORTC_HOTPLUG_ENABLE |
3348                    PORTD_HOTPLUG_ENABLE;
3349         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3350
3351         hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3352         hotplug |= PORTE_HOTPLUG_ENABLE;
3353         I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3354 }
3355
3356 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3357 {
3358         u32 hotplug_irqs, enabled_irqs;
3359
3360         if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
3361                 I915_WRITE(SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
3362
3363         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3364         hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3365
3366         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3367
3368         spt_hpd_detection_setup(dev_priv);
3369 }
3370
3371 static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
3372 {
3373         u32 hotplug;
3374
3375         /*
3376          * Enable digital hotplug on the CPU, and configure the DP short pulse
3377          * duration to 2ms (which is the minimum in the Display Port spec)
3378          * The pulse duration bits are reserved on HSW+.
3379          */
3380         hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3381         hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3382         hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE |
3383                    DIGITAL_PORTA_PULSE_DURATION_2ms;
3384         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3385 }
3386
3387 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3388 {
3389         u32 hotplug_irqs, enabled_irqs;
3390
3391         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
3392         hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
3393
3394         if (INTEL_GEN(dev_priv) >= 8)
3395                 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3396         else
3397                 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3398
3399         ilk_hpd_detection_setup(dev_priv);
3400
3401         ibx_hpd_irq_setup(dev_priv);
3402 }
3403
3404 static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
3405                                       u32 enabled_irqs)
3406 {
3407         u32 hotplug;
3408
3409         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3410         hotplug |= PORTA_HOTPLUG_ENABLE |
3411                    PORTB_HOTPLUG_ENABLE |
3412                    PORTC_HOTPLUG_ENABLE;
3413
3414         drm_dbg_kms(&dev_priv->drm,
3415                     "Invert bit setting: hp_ctl:%x hp_port:%x\n",
3416                     hotplug, enabled_irqs);
3417         hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
3418
3419         /*
3420          * For BXT invert bit has to be set based on AOB design
3421          * for HPD detection logic, update it based on VBT fields.
3422          */
3423         if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)) &&
3424             intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
3425                 hotplug |= BXT_DDIA_HPD_INVERT;
3426         if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_B)) &&
3427             intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
3428                 hotplug |= BXT_DDIB_HPD_INVERT;
3429         if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)) &&
3430             intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
3431                 hotplug |= BXT_DDIC_HPD_INVERT;
3432
3433         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3434 }
3435
3436 static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3437 {
3438         __bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK);
3439 }
3440
3441 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3442 {
3443         u32 hotplug_irqs, enabled_irqs;
3444
3445         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
3446         hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
3447
3448         bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3449
3450         __bxt_hpd_detection_setup(dev_priv, enabled_irqs);
3451 }
3452
3453 static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
3454 {
3455         u32 mask;
3456
3457         if (HAS_PCH_NOP(dev_priv))
3458                 return;
3459
3460         if (HAS_PCH_IBX(dev_priv))
3461                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3462         else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
3463                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3464         else
3465                 mask = SDE_GMBUS_CPT;
3466
3467         gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
3468         I915_WRITE(SDEIMR, ~mask);
3469
3470         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
3471             HAS_PCH_LPT(dev_priv))
3472                 ibx_hpd_detection_setup(dev_priv);
3473         else
3474                 spt_hpd_detection_setup(dev_priv);
3475 }
3476
3477 static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
3478 {
3479         struct intel_uncore *uncore = &dev_priv->uncore;
3480         u32 display_mask, extra_mask;
3481
3482         if (INTEL_GEN(dev_priv) >= 7) {
3483                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3484                                 DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB);
3485                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3486                               DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3487                               DE_DP_A_HOTPLUG_IVB);
3488         } else {
3489                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3490                                 DE_AUX_CHANNEL_A | DE_PIPEB_CRC_DONE |
3491                                 DE_PIPEA_CRC_DONE | DE_POISON);
3492                 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK |
3493                               DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3494                               DE_DP_A_HOTPLUG);
3495         }
3496
3497         if (IS_HASWELL(dev_priv)) {
3498                 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
3499                 display_mask |= DE_EDP_PSR_INT_HSW;
3500         }
3501
3502         if (IS_IRONLAKE_M(dev_priv))
3503                 extra_mask |= DE_PCU_EVENT;
3504
3505         dev_priv->irq_mask = ~display_mask;
3506
3507         ibx_irq_pre_postinstall(dev_priv);
3508
3509         gen5_gt_irq_postinstall(&dev_priv->gt);
3510
3511         GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,
3512                       display_mask | extra_mask);
3513
3514         ilk_hpd_detection_setup(dev_priv);
3515
3516         ibx_irq_postinstall(dev_priv);
3517 }
3518
3519 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3520 {
3521         lockdep_assert_held(&dev_priv->irq_lock);
3522
3523         if (dev_priv->display_irqs_enabled)
3524                 return;
3525
3526         dev_priv->display_irqs_enabled = true;
3527
3528         if (intel_irqs_enabled(dev_priv)) {
3529                 vlv_display_irq_reset(dev_priv);
3530                 vlv_display_irq_postinstall(dev_priv);
3531         }
3532 }
3533
3534 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3535 {
3536         lockdep_assert_held(&dev_priv->irq_lock);
3537
3538         if (!dev_priv->display_irqs_enabled)
3539                 return;
3540
3541         dev_priv->display_irqs_enabled = false;
3542
3543         if (intel_irqs_enabled(dev_priv))
3544                 vlv_display_irq_reset(dev_priv);
3545 }
3546
3547
3548 static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
3549 {
3550         gen5_gt_irq_postinstall(&dev_priv->gt);
3551
3552         spin_lock_irq(&dev_priv->irq_lock);
3553         if (dev_priv->display_irqs_enabled)
3554                 vlv_display_irq_postinstall(dev_priv);
3555         spin_unlock_irq(&dev_priv->irq_lock);
3556
3557         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3558         POSTING_READ(VLV_MASTER_IER);
3559 }
3560
3561 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3562 {
3563         struct intel_uncore *uncore = &dev_priv->uncore;
3564
3565         u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) |
3566                 GEN8_PIPE_CDCLK_CRC_DONE;
3567         u32 de_pipe_enables;
3568         u32 de_port_masked = gen8_de_port_aux_mask(dev_priv);
3569         u32 de_port_enables;
3570         u32 de_misc_masked = GEN8_DE_EDP_PSR;
3571         u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
3572                 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
3573         enum pipe pipe;
3574
3575         if (INTEL_GEN(dev_priv) <= 10)
3576                 de_misc_masked |= GEN8_DE_MISC_GSE;
3577
3578         if (IS_GEN9_LP(dev_priv))
3579                 de_port_masked |= BXT_DE_PORT_GMBUS;
3580
3581         if (INTEL_GEN(dev_priv) >= 11) {
3582                 enum port port;
3583
3584                 if (intel_bios_is_dsi_present(dev_priv, &port))
3585                         de_port_masked |= DSI0_TE | DSI1_TE;
3586         }
3587
3588         de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3589                                            GEN8_PIPE_FIFO_UNDERRUN;
3590
3591         if (INTEL_GEN(dev_priv) >= 9)
3592                 de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE;
3593
3594         de_port_enables = de_port_masked;
3595         if (IS_GEN9_LP(dev_priv))
3596                 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3597         else if (IS_BROADWELL(dev_priv))
3598                 de_port_enables |= BDW_DE_PORT_HOTPLUG_MASK;
3599
3600         if (INTEL_GEN(dev_priv) >= 12) {
3601                 enum transcoder trans;
3602
3603                 for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
3604                         enum intel_display_power_domain domain;
3605
3606                         domain = POWER_DOMAIN_TRANSCODER(trans);
3607                         if (!intel_display_power_is_enabled(dev_priv, domain))
3608                                 continue;
3609
3610                         gen3_assert_iir_is_zero(uncore, TRANS_PSR_IIR(trans));
3611                 }
3612         } else {
3613                 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
3614         }
3615
3616         for_each_pipe(dev_priv, pipe) {
3617                 dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;
3618
3619                 if (intel_display_power_is_enabled(dev_priv,
3620                                 POWER_DOMAIN_PIPE(pipe)))
3621                         GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
3622                                           dev_priv->de_irq_mask[pipe],
3623                                           de_pipe_enables);
3624         }
3625
3626         GEN3_IRQ_INIT(uncore, GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3627         GEN3_IRQ_INIT(uncore, GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
3628
3629         if (INTEL_GEN(dev_priv) >= 11) {
3630                 u32 de_hpd_masked = 0;
3631                 u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK |
3632                                      GEN11_DE_TBT_HOTPLUG_MASK;
3633
3634                 GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,
3635                               de_hpd_enables);
3636                 gen11_hpd_detection_setup(dev_priv);
3637         } else if (IS_GEN9_LP(dev_priv)) {
3638                 bxt_hpd_detection_setup(dev_priv);
3639         } else if (IS_BROADWELL(dev_priv)) {
3640                 ilk_hpd_detection_setup(dev_priv);
3641         }
3642 }
3643
3644 static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
3645 {
3646         if (HAS_PCH_SPLIT(dev_priv))
3647                 ibx_irq_pre_postinstall(dev_priv);
3648
3649         gen8_gt_irq_postinstall(&dev_priv->gt);
3650         gen8_de_irq_postinstall(dev_priv);
3651
3652         if (HAS_PCH_SPLIT(dev_priv))
3653                 ibx_irq_postinstall(dev_priv);
3654
3655         gen8_master_intr_enable(dev_priv->uncore.regs);
3656 }
3657
3658 static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
3659 {
3660         u32 mask = SDE_GMBUS_ICP;
3661
3662         drm_WARN_ON(&dev_priv->drm, I915_READ(SDEIER) != 0);
3663         I915_WRITE(SDEIER, 0xffffffff);
3664         POSTING_READ(SDEIER);
3665
3666         gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
3667         I915_WRITE(SDEIMR, ~mask);
3668
3669         if (HAS_PCH_DG1(dev_priv))
3670                 icp_ddi_hpd_detection_setup(dev_priv, DG1_DDI_HPD_ENABLE_MASK);
3671         else if (HAS_PCH_TGP(dev_priv)) {
3672                 icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
3673                 icp_tc_hpd_detection_setup(dev_priv, TGP_TC_HPD_ENABLE_MASK);
3674         } else if (HAS_PCH_JSP(dev_priv)) {
3675                 icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
3676         } else if (HAS_PCH_MCC(dev_priv)) {
3677                 icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
3678                 icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(TC_PORT_1));
3679         } else {
3680                 icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
3681                 icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE_MASK);
3682         }
3683 }
3684
3685 static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
3686 {
3687         struct intel_uncore *uncore = &dev_priv->uncore;
3688         u32 gu_misc_masked = GEN11_GU_MISC_GSE;
3689
3690         if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3691                 icp_irq_postinstall(dev_priv);
3692
3693         gen11_gt_irq_postinstall(&dev_priv->gt);
3694         gen8_de_irq_postinstall(dev_priv);
3695
3696         GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
3697
3698         I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
3699
3700         if (HAS_MASTER_UNIT_IRQ(dev_priv)) {
3701                 dg1_master_intr_enable(uncore->regs);
3702                 POSTING_READ(DG1_MSTR_UNIT_INTR);
3703         } else {
3704                 gen11_master_intr_enable(uncore->regs);
3705                 POSTING_READ(GEN11_GFX_MSTR_IRQ);
3706         }
3707 }
3708
3709 static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
3710 {
3711         gen8_gt_irq_postinstall(&dev_priv->gt);
3712
3713         spin_lock_irq(&dev_priv->irq_lock);
3714         if (dev_priv->display_irqs_enabled)
3715                 vlv_display_irq_postinstall(dev_priv);
3716         spin_unlock_irq(&dev_priv->irq_lock);
3717
3718         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3719         POSTING_READ(GEN8_MASTER_IRQ);
3720 }
3721
3722 static void i8xx_irq_reset(struct drm_i915_private *dev_priv)
3723 {
3724         struct intel_uncore *uncore = &dev_priv->uncore;
3725
3726         i9xx_pipestat_irq_reset(dev_priv);
3727
3728         GEN2_IRQ_RESET(uncore);
3729         dev_priv->irq_mask = ~0u;
3730 }
3731
3732 static void i8xx_irq_postinstall(struct drm_i915_private *dev_priv)
3733 {
3734         struct intel_uncore *uncore = &dev_priv->uncore;
3735         u16 enable_mask;
3736
3737         intel_uncore_write16(uncore,
3738                              EMR,
3739                              ~(I915_ERROR_PAGE_TABLE |
3740                                I915_ERROR_MEMORY_REFRESH));
3741
3742         /* Unmask the interrupts that we always want on. */
3743         dev_priv->irq_mask =
3744                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3745                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3746                   I915_MASTER_ERROR_INTERRUPT);
3747
3748         enable_mask =
3749                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3750                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3751                 I915_MASTER_ERROR_INTERRUPT |
3752                 I915_USER_INTERRUPT;
3753
3754         GEN2_IRQ_INIT(uncore, dev_priv->irq_mask, enable_mask);
3755
3756         /* Interrupt setup is already guaranteed to be single-threaded, this is
3757          * just to make the assert_spin_locked check happy. */
3758         spin_lock_irq(&dev_priv->irq_lock);
3759         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3760         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3761         spin_unlock_irq(&dev_priv->irq_lock);
3762 }
3763
3764 static void i8xx_error_irq_ack(struct drm_i915_private *i915,
3765                                u16 *eir, u16 *eir_stuck)
3766 {
3767         struct intel_uncore *uncore = &i915->uncore;
3768         u16 emr;
3769
3770         *eir = intel_uncore_read16(uncore, EIR);
3771
3772         if (*eir)
3773                 intel_uncore_write16(uncore, EIR, *eir);
3774
3775         *eir_stuck = intel_uncore_read16(uncore, EIR);
3776         if (*eir_stuck == 0)
3777                 return;
3778
3779         /*
3780          * Toggle all EMR bits to make sure we get an edge
3781          * in the ISR master error bit if we don't clear
3782          * all the EIR bits. Otherwise the edge triggered
3783          * IIR on i965/g4x wouldn't notice that an interrupt
3784          * is still pending. Also some EIR bits can't be
3785          * cleared except by handling the underlying error
3786          * (or by a GPU reset) so we mask any bit that
3787          * remains set.
3788          */
3789         emr = intel_uncore_read16(uncore, EMR);
3790         intel_uncore_write16(uncore, EMR, 0xffff);
3791         intel_uncore_write16(uncore, EMR, emr | *eir_stuck);
3792 }
3793
3794 static void i8xx_error_irq_handler(struct drm_i915_private *dev_priv,
3795                                    u16 eir, u16 eir_stuck)
3796 {
3797         DRM_DEBUG("Master Error: EIR 0x%04x\n", eir);
3798
3799         if (eir_stuck)
3800                 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%04x, masked\n",
3801                         eir_stuck);
3802 }
3803
3804 static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv,
3805                                u32 *eir, u32 *eir_stuck)
3806 {
3807         u32 emr;
3808
3809         *eir = I915_READ(EIR);
3810
3811         I915_WRITE(EIR, *eir);
3812
3813         *eir_stuck = I915_READ(EIR);
3814         if (*eir_stuck == 0)
3815                 return;
3816
3817         /*
3818          * Toggle all EMR bits to make sure we get an edge
3819          * in the ISR master error bit if we don't clear
3820          * all the EIR bits. Otherwise the edge triggered
3821          * IIR on i965/g4x wouldn't notice that an interrupt
3822          * is still pending. Also some EIR bits can't be
3823          * cleared except by handling the underlying error
3824          * (or by a GPU reset) so we mask any bit that
3825          * remains set.
3826          */
3827         emr = I915_READ(EMR);
3828         I915_WRITE(EMR, 0xffffffff);
3829         I915_WRITE(EMR, emr | *eir_stuck);
3830 }
3831
3832 static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv,
3833                                    u32 eir, u32 eir_stuck)
3834 {
3835         DRM_DEBUG("Master Error, EIR 0x%08x\n", eir);
3836
3837         if (eir_stuck)
3838                 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%08x, masked\n",
3839                         eir_stuck);
3840 }
3841
3842 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3843 {
3844         struct drm_i915_private *dev_priv = arg;
3845         irqreturn_t ret = IRQ_NONE;
3846
3847         if (!intel_irqs_enabled(dev_priv))
3848                 return IRQ_NONE;
3849
3850         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3851         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3852
3853         do {
3854                 u32 pipe_stats[I915_MAX_PIPES] = {};
3855                 u16 eir = 0, eir_stuck = 0;
3856                 u16 iir;
3857
3858                 iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR);
3859                 if (iir == 0)
3860                         break;
3861
3862                 ret = IRQ_HANDLED;
3863
3864                 /* Call regardless, as some status bits might not be
3865                  * signalled in iir */
3866                 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
3867
3868                 if (iir & I915_MASTER_ERROR_INTERRUPT)
3869                         i8xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
3870
3871                 intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir);
3872
3873                 if (iir & I915_USER_INTERRUPT)
3874                         intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
3875
3876                 if (iir & I915_MASTER_ERROR_INTERRUPT)
3877                         i8xx_error_irq_handler(dev_priv, eir, eir_stuck);
3878
3879                 i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats);
3880         } while (0);
3881
3882         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3883
3884         return ret;
3885 }
3886
3887 static void i915_irq_reset(struct drm_i915_private *dev_priv)
3888 {
3889         struct intel_uncore *uncore = &dev_priv->uncore;
3890
3891         if (I915_HAS_HOTPLUG(dev_priv)) {
3892                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3893                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3894         }
3895
3896         i9xx_pipestat_irq_reset(dev_priv);
3897
3898         GEN3_IRQ_RESET(uncore, GEN2_);
3899         dev_priv->irq_mask = ~0u;
3900 }
3901
3902 static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
3903 {
3904         struct intel_uncore *uncore = &dev_priv->uncore;
3905         u32 enable_mask;
3906
3907         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE |
3908                           I915_ERROR_MEMORY_REFRESH));
3909
3910         /* Unmask the interrupts that we always want on. */
3911         dev_priv->irq_mask =
3912                 ~(I915_ASLE_INTERRUPT |
3913                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3914                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3915                   I915_MASTER_ERROR_INTERRUPT);
3916
3917         enable_mask =
3918                 I915_ASLE_INTERRUPT |
3919                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3920                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3921                 I915_MASTER_ERROR_INTERRUPT |
3922                 I915_USER_INTERRUPT;
3923
3924         if (I915_HAS_HOTPLUG(dev_priv)) {
3925                 /* Enable in IER... */
3926                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3927                 /* and unmask in IMR */
3928                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3929         }
3930
3931         GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
3932
3933         /* Interrupt setup is already guaranteed to be single-threaded, this is
3934          * just to make the assert_spin_locked check happy. */
3935         spin_lock_irq(&dev_priv->irq_lock);
3936         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3937         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3938         spin_unlock_irq(&dev_priv->irq_lock);
3939
3940         i915_enable_asle_pipestat(dev_priv);
3941 }
3942
3943 static irqreturn_t i915_irq_handler(int irq, void *arg)
3944 {
3945         struct drm_i915_private *dev_priv = arg;
3946         irqreturn_t ret = IRQ_NONE;
3947
3948         if (!intel_irqs_enabled(dev_priv))
3949                 return IRQ_NONE;
3950
3951         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3952         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3953
3954         do {
3955                 u32 pipe_stats[I915_MAX_PIPES] = {};
3956                 u32 eir = 0, eir_stuck = 0;
3957                 u32 hotplug_status = 0;
3958                 u32 iir;
3959
3960                 iir = I915_READ(GEN2_IIR);
3961                 if (iir == 0)
3962                         break;
3963
3964                 ret = IRQ_HANDLED;
3965
3966                 if (I915_HAS_HOTPLUG(dev_priv) &&
3967                     iir & I915_DISPLAY_PORT_INTERRUPT)
3968                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
3969
3970                 /* Call regardless, as some status bits might not be
3971                  * signalled in iir */
3972                 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
3973
3974                 if (iir & I915_MASTER_ERROR_INTERRUPT)
3975                         i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
3976
3977                 I915_WRITE(GEN2_IIR, iir);
3978
3979                 if (iir & I915_USER_INTERRUPT)
3980                         intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
3981
3982                 if (iir & I915_MASTER_ERROR_INTERRUPT)
3983                         i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
3984
3985                 if (hotplug_status)
3986                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
3987
3988                 i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);
3989         } while (0);
3990
3991         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3992
3993         return ret;
3994 }
3995
3996 static void i965_irq_reset(struct drm_i915_private *dev_priv)
3997 {
3998         struct intel_uncore *uncore = &dev_priv->uncore;
3999
4000         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4001         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4002
4003         i9xx_pipestat_irq_reset(dev_priv);
4004
4005         GEN3_IRQ_RESET(uncore, GEN2_);
4006         dev_priv->irq_mask = ~0u;
4007 }
4008
4009 static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
4010 {
4011         struct intel_uncore *uncore = &dev_priv->uncore;
4012         u32 enable_mask;
4013         u32 error_mask;
4014
4015         /*
4016          * Enable some error detection, note the instruction error mask
4017          * bit is reserved, so we leave it masked.
4018          */
4019         if (IS_G4X(dev_priv)) {
4020                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4021                                GM45_ERROR_MEM_PRIV |
4022                                GM45_ERROR_CP_PRIV |
4023                                I915_ERROR_MEMORY_REFRESH);
4024         } else {
4025                 error_mask = ~(I915_ERROR_PAGE_TABLE |
4026                                I915_ERROR_MEMORY_REFRESH);
4027         }
4028         I915_WRITE(EMR, error_mask);
4029
4030         /* Unmask the interrupts that we always want on. */
4031         dev_priv->irq_mask =
4032                 ~(I915_ASLE_INTERRUPT |
4033                   I915_DISPLAY_PORT_INTERRUPT |
4034                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4035                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4036                   I915_MASTER_ERROR_INTERRUPT);
4037
4038         enable_mask =
4039                 I915_ASLE_INTERRUPT |
4040                 I915_DISPLAY_PORT_INTERRUPT |
4041                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4042                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4043                 I915_MASTER_ERROR_INTERRUPT |
4044                 I915_USER_INTERRUPT;
4045
4046         if (IS_G4X(dev_priv))
4047                 enable_mask |= I915_BSD_USER_INTERRUPT;
4048
4049         GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
4050
4051         /* Interrupt setup is already guaranteed to be single-threaded, this is
4052          * just to make the assert_spin_locked check happy. */
4053         spin_lock_irq(&dev_priv->irq_lock);
4054         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4055         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4056         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4057         spin_unlock_irq(&dev_priv->irq_lock);
4058
4059         i915_enable_asle_pipestat(dev_priv);
4060 }
4061
4062 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
4063 {
4064         u32 hotplug_en;
4065
4066         lockdep_assert_held(&dev_priv->irq_lock);
4067
4068         /* Note HDMI and DP share hotplug bits */
4069         /* enable bits are the same for all generations */
4070         hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
4071         /* Programming the CRT detection parameters tends
4072            to generate a spurious hotplug event about three
4073            seconds later.  So just do it once.
4074         */
4075         if (IS_G4X(dev_priv))
4076                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4077         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4078
4079         /* Ignore TV since it's buggy */
4080         i915_hotplug_interrupt_update_locked(dev_priv,
4081                                              HOTPLUG_INT_EN_MASK |
4082                                              CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
4083                                              CRT_HOTPLUG_ACTIVATION_PERIOD_64,
4084                                              hotplug_en);
4085 }
4086
4087 static irqreturn_t i965_irq_handler(int irq, void *arg)
4088 {
4089         struct drm_i915_private *dev_priv = arg;
4090         irqreturn_t ret = IRQ_NONE;
4091
4092         if (!intel_irqs_enabled(dev_priv))
4093                 return IRQ_NONE;
4094
4095         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4096         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4097
4098         do {
4099                 u32 pipe_stats[I915_MAX_PIPES] = {};
4100                 u32 eir = 0, eir_stuck = 0;
4101                 u32 hotplug_status = 0;
4102                 u32 iir;
4103
4104                 iir = I915_READ(GEN2_IIR);
4105                 if (iir == 0)
4106                         break;
4107
4108                 ret = IRQ_HANDLED;
4109
4110                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4111                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4112
4113                 /* Call regardless, as some status bits might not be
4114                  * signalled in iir */
4115                 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
4116
4117                 if (iir & I915_MASTER_ERROR_INTERRUPT)
4118                         i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
4119
4120                 I915_WRITE(GEN2_IIR, iir);
4121
4122                 if (iir & I915_USER_INTERRUPT)
4123                         intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
4124
4125                 if (iir & I915_BSD_USER_INTERRUPT)
4126                         intel_engine_signal_breadcrumbs(dev_priv->gt.engine[VCS0]);
4127
4128                 if (iir & I915_MASTER_ERROR_INTERRUPT)
4129                         i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
4130
4131                 if (hotplug_status)
4132                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4133
4134                 i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);
4135         } while (0);
4136
4137         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4138
4139         return ret;
4140 }
4141
4142 /**
4143  * intel_irq_init - initializes irq support
4144  * @dev_priv: i915 device instance
4145  *
4146  * This function initializes all the irq support including work items, timers
4147  * and all the vtables. It does not setup the interrupt itself though.
4148  */
4149 void intel_irq_init(struct drm_i915_private *dev_priv)
4150 {
4151         struct drm_device *dev = &dev_priv->drm;
4152         int i;
4153
4154         intel_hpd_init_pins(dev_priv);
4155
4156         intel_hpd_init_work(dev_priv);
4157
4158         INIT_WORK(&dev_priv->l3_parity.error_work, ivb_parity_work);
4159         for (i = 0; i < MAX_L3_SLICES; ++i)
4160                 dev_priv->l3_parity.remap_info[i] = NULL;
4161
4162         /* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */
4163         if (HAS_GT_UC(dev_priv) && INTEL_GEN(dev_priv) < 11)
4164                 dev_priv->gt.pm_guc_events = GUC_INTR_GUC2HOST << 16;
4165
4166         dev->vblank_disable_immediate = true;
4167
4168         /* Most platforms treat the display irq block as an always-on
4169          * power domain. vlv/chv can disable it at runtime and need
4170          * special care to avoid writing any of the display block registers
4171          * outside of the power domain. We defer setting up the display irqs
4172          * in this case to the runtime pm.
4173          */
4174         dev_priv->display_irqs_enabled = true;
4175         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4176                 dev_priv->display_irqs_enabled = false;
4177
4178         dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
4179         /* If we have MST support, we want to avoid doing short HPD IRQ storm
4180          * detection, as short HPD storms will occur as a natural part of
4181          * sideband messaging with MST.
4182          * On older platforms however, IRQ storms can occur with both long and
4183          * short pulses, as seen on some G4x systems.
4184          */
4185         dev_priv->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv);
4186
4187         if (HAS_GMCH(dev_priv)) {
4188                 if (I915_HAS_HOTPLUG(dev_priv))
4189                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4190         } else {
4191                 if (HAS_PCH_DG1(dev_priv))
4192                         dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
4193                 else if (HAS_PCH_JSP(dev_priv))
4194                         dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
4195                 else if (HAS_PCH_MCC(dev_priv))
4196                         dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
4197                 else if (INTEL_GEN(dev_priv) >= 11)
4198                         dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
4199                 else if (IS_GEN9_LP(dev_priv))
4200                         dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4201                 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
4202                         dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4203                 else
4204                         dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4205         }
4206 }
4207
4208 /**
4209  * intel_irq_fini - deinitializes IRQ support
4210  * @i915: i915 device instance
4211  *
4212  * This function deinitializes all the IRQ support.
4213  */
4214 void intel_irq_fini(struct drm_i915_private *i915)
4215 {
4216         int i;
4217
4218         for (i = 0; i < MAX_L3_SLICES; ++i)
4219                 kfree(i915->l3_parity.remap_info[i]);
4220 }
4221
4222 static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv)
4223 {
4224         if (HAS_GMCH(dev_priv)) {
4225                 if (IS_CHERRYVIEW(dev_priv))
4226                         return cherryview_irq_handler;
4227                 else if (IS_VALLEYVIEW(dev_priv))
4228                         return valleyview_irq_handler;
4229                 else if (IS_GEN(dev_priv, 4))
4230                         return i965_irq_handler;
4231                 else if (IS_GEN(dev_priv, 3))
4232                         return i915_irq_handler;
4233                 else
4234                         return i8xx_irq_handler;
4235         } else {
4236                 if (HAS_MASTER_UNIT_IRQ(dev_priv))
4237                         return dg1_irq_handler;
4238                 if (INTEL_GEN(dev_priv) >= 11)
4239                         return gen11_irq_handler;
4240                 else if (INTEL_GEN(dev_priv) >= 8)
4241                         return gen8_irq_handler;
4242                 else
4243                         return ilk_irq_handler;
4244         }
4245 }
4246
4247 static void intel_irq_reset(struct drm_i915_private *dev_priv)
4248 {
4249         if (HAS_GMCH(dev_priv)) {
4250                 if (IS_CHERRYVIEW(dev_priv))
4251                         cherryview_irq_reset(dev_priv);
4252                 else if (IS_VALLEYVIEW(dev_priv))
4253                         valleyview_irq_reset(dev_priv);
4254                 else if (IS_GEN(dev_priv, 4))
4255                         i965_irq_reset(dev_priv);
4256                 else if (IS_GEN(dev_priv, 3))
4257                         i915_irq_reset(dev_priv);
4258                 else
4259                         i8xx_irq_reset(dev_priv);
4260         } else {
4261                 if (INTEL_GEN(dev_priv) >= 11)
4262                         gen11_irq_reset(dev_priv);
4263                 else if (INTEL_GEN(dev_priv) >= 8)
4264                         gen8_irq_reset(dev_priv);
4265                 else
4266                         ilk_irq_reset(dev_priv);
4267         }
4268 }
4269
4270 static void intel_irq_postinstall(struct drm_i915_private *dev_priv)
4271 {
4272         if (HAS_GMCH(dev_priv)) {
4273                 if (IS_CHERRYVIEW(dev_priv))
4274                         cherryview_irq_postinstall(dev_priv);
4275                 else if (IS_VALLEYVIEW(dev_priv))
4276                         valleyview_irq_postinstall(dev_priv);
4277                 else if (IS_GEN(dev_priv, 4))
4278                         i965_irq_postinstall(dev_priv);
4279                 else if (IS_GEN(dev_priv, 3))
4280                         i915_irq_postinstall(dev_priv);
4281                 else
4282                         i8xx_irq_postinstall(dev_priv);
4283         } else {
4284                 if (INTEL_GEN(dev_priv) >= 11)
4285                         gen11_irq_postinstall(dev_priv);
4286                 else if (INTEL_GEN(dev_priv) >= 8)
4287                         gen8_irq_postinstall(dev_priv);
4288                 else
4289                         ilk_irq_postinstall(dev_priv);
4290         }
4291 }
4292
4293 /**
4294  * intel_irq_install - enables the hardware interrupt
4295  * @dev_priv: i915 device instance
4296  *
4297  * This function enables the hardware interrupt handling, but leaves the hotplug
4298  * handling still disabled. It is called after intel_irq_init().
4299  *
4300  * In the driver load and resume code we need working interrupts in a few places
4301  * but don't want to deal with the hassle of concurrent probe and hotplug
4302  * workers. Hence the split into this two-stage approach.
4303  */
4304 int intel_irq_install(struct drm_i915_private *dev_priv)
4305 {
4306         int irq = dev_priv->drm.pdev->irq;
4307         int ret;
4308
4309         /*
4310          * We enable some interrupt sources in our postinstall hooks, so mark
4311          * interrupts as enabled _before_ actually enabling them to avoid
4312          * special cases in our ordering checks.
4313          */
4314         dev_priv->runtime_pm.irqs_enabled = true;
4315
4316         dev_priv->drm.irq_enabled = true;
4317
4318         intel_irq_reset(dev_priv);
4319
4320         ret = request_irq(irq, intel_irq_handler(dev_priv),
4321                           IRQF_SHARED, DRIVER_NAME, dev_priv);
4322         if (ret < 0) {
4323                 dev_priv->drm.irq_enabled = false;
4324                 return ret;
4325         }
4326
4327         intel_irq_postinstall(dev_priv);
4328
4329         return ret;
4330 }
4331
4332 /**
4333  * intel_irq_uninstall - finilizes all irq handling
4334  * @dev_priv: i915 device instance
4335  *
4336  * This stops interrupt and hotplug handling and unregisters and frees all
4337  * resources acquired in the init functions.
4338  */
4339 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4340 {
4341         int irq = dev_priv->drm.pdev->irq;
4342
4343         /*
4344          * FIXME we can get called twice during driver probe
4345          * error handling as well as during driver remove due to
4346          * intel_modeset_driver_remove() calling us out of sequence.
4347          * Would be nice if it didn't do that...
4348          */
4349         if (!dev_priv->drm.irq_enabled)
4350                 return;
4351
4352         dev_priv->drm.irq_enabled = false;
4353
4354         intel_irq_reset(dev_priv);
4355
4356         free_irq(irq, dev_priv);
4357
4358         intel_hpd_cancel_work(dev_priv);
4359         dev_priv->runtime_pm.irqs_enabled = false;
4360 }
4361
4362 /**
4363  * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4364  * @dev_priv: i915 device instance
4365  *
4366  * This function is used to disable interrupts at runtime, both in the runtime
4367  * pm and the system suspend/resume code.
4368  */
4369 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4370 {
4371         intel_irq_reset(dev_priv);
4372         dev_priv->runtime_pm.irqs_enabled = false;
4373         intel_synchronize_irq(dev_priv);
4374 }
4375
4376 /**
4377  * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4378  * @dev_priv: i915 device instance
4379  *
4380  * This function is used to enable interrupts at runtime, both in the runtime
4381  * pm and the system suspend/resume code.
4382  */
4383 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4384 {
4385         dev_priv->runtime_pm.irqs_enabled = true;
4386         intel_irq_reset(dev_priv);
4387         intel_irq_postinstall(dev_priv);
4388 }
4389
4390 bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
4391 {
4392         /*
4393          * We only use drm_irq_uninstall() at unload and VT switch, so
4394          * this is the only thing we need to check.
4395          */
4396         return dev_priv->runtime_pm.irqs_enabled;
4397 }
4398
4399 void intel_synchronize_irq(struct drm_i915_private *i915)
4400 {
4401         synchronize_irq(i915->drm.pdev->irq);
4402 }