1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
35 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include "intel_drv.h"
41 * DOC: interrupt handling
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
48 static const u32 hpd_ilk[HPD_NUM_PINS] = {
49 [HPD_PORT_A] = DE_DP_A_HOTPLUG,
52 static const u32 hpd_ivb[HPD_NUM_PINS] = {
53 [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
56 static const u32 hpd_bdw[HPD_NUM_PINS] = {
57 [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
60 static const u32 hpd_ibx[HPD_NUM_PINS] = {
61 [HPD_CRT] = SDE_CRT_HOTPLUG,
62 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
63 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
64 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
65 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
68 static const u32 hpd_cpt[HPD_NUM_PINS] = {
69 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
70 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
71 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
72 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
73 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
76 static const u32 hpd_spt[HPD_NUM_PINS] = {
77 [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
78 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
79 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
80 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
81 [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
84 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
85 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
86 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
87 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
88 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
89 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
90 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
93 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
94 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
95 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
96 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
97 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
98 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
99 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
102 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
103 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
104 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
105 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
106 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
107 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
108 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
112 static const u32 hpd_bxt[HPD_NUM_PINS] = {
113 [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
114 [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
115 [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
118 /* IIR can theoretically queue up two events. Be paranoid. */
119 #define GEN8_IRQ_RESET_NDX(type, which) do { \
120 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
121 POSTING_READ(GEN8_##type##_IMR(which)); \
122 I915_WRITE(GEN8_##type##_IER(which), 0); \
123 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
124 POSTING_READ(GEN8_##type##_IIR(which)); \
125 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
126 POSTING_READ(GEN8_##type##_IIR(which)); \
129 #define GEN3_IRQ_RESET(type) do { \
130 I915_WRITE(type##IMR, 0xffffffff); \
131 POSTING_READ(type##IMR); \
132 I915_WRITE(type##IER, 0); \
133 I915_WRITE(type##IIR, 0xffffffff); \
134 POSTING_READ(type##IIR); \
135 I915_WRITE(type##IIR, 0xffffffff); \
136 POSTING_READ(type##IIR); \
139 #define GEN2_IRQ_RESET(type) do { \
140 I915_WRITE16(type##IMR, 0xffff); \
141 POSTING_READ16(type##IMR); \
142 I915_WRITE16(type##IER, 0); \
143 I915_WRITE16(type##IIR, 0xffff); \
144 POSTING_READ16(type##IIR); \
145 I915_WRITE16(type##IIR, 0xffff); \
146 POSTING_READ16(type##IIR); \
150 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
152 static void gen3_assert_iir_is_zero(struct drm_i915_private *dev_priv,
155 u32 val = I915_READ(reg);
160 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
161 i915_mmio_reg_offset(reg), val);
162 I915_WRITE(reg, 0xffffffff);
164 I915_WRITE(reg, 0xffffffff);
168 static void gen2_assert_iir_is_zero(struct drm_i915_private *dev_priv,
171 u16 val = I915_READ16(reg);
176 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
177 i915_mmio_reg_offset(reg), val);
178 I915_WRITE16(reg, 0xffff);
180 I915_WRITE16(reg, 0xffff);
184 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
185 gen3_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
186 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
187 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
188 POSTING_READ(GEN8_##type##_IMR(which)); \
191 #define GEN3_IRQ_INIT(type, imr_val, ier_val) do { \
192 gen3_assert_iir_is_zero(dev_priv, type##IIR); \
193 I915_WRITE(type##IER, (ier_val)); \
194 I915_WRITE(type##IMR, (imr_val)); \
195 POSTING_READ(type##IMR); \
198 #define GEN2_IRQ_INIT(type, imr_val, ier_val) do { \
199 gen2_assert_iir_is_zero(dev_priv, type##IIR); \
200 I915_WRITE16(type##IER, (ier_val)); \
201 I915_WRITE16(type##IMR, (imr_val)); \
202 POSTING_READ16(type##IMR); \
205 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
206 static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
208 /* For display hotplug interrupt */
210 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
216 lockdep_assert_held(&dev_priv->irq_lock);
217 WARN_ON(bits & ~mask);
219 val = I915_READ(PORT_HOTPLUG_EN);
222 I915_WRITE(PORT_HOTPLUG_EN, val);
226 * i915_hotplug_interrupt_update - update hotplug interrupt enable
227 * @dev_priv: driver private
228 * @mask: bits to update
229 * @bits: bits to enable
230 * NOTE: the HPD enable bits are modified both inside and outside
231 * of an interrupt context. To avoid that read-modify-write cycles
232 * interfer, these bits are protected by a spinlock. Since this
233 * function is usually not called from a context where the lock is
234 * held already, this function acquires the lock itself. A non-locking
235 * version is also available.
237 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
241 spin_lock_irq(&dev_priv->irq_lock);
242 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
243 spin_unlock_irq(&dev_priv->irq_lock);
247 gen11_gt_engine_identity(struct drm_i915_private * const i915,
248 const unsigned int bank, const unsigned int bit);
250 bool gen11_reset_one_iir(struct drm_i915_private * const i915,
251 const unsigned int bank,
252 const unsigned int bit)
254 void __iomem * const regs = i915->regs;
257 lockdep_assert_held(&i915->irq_lock);
259 dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
262 * According to the BSpec, DW_IIR bits cannot be cleared without
263 * first servicing the Selector & Shared IIR registers.
265 gen11_gt_engine_identity(i915, bank, bit);
268 * We locked GT INT DW by reading it. If we want to (try
269 * to) recover from this succesfully, we need to clear
270 * our bit, otherwise we are locking the register for
273 raw_reg_write(regs, GEN11_GT_INTR_DW(bank), BIT(bit));
282 * ilk_update_display_irq - update DEIMR
283 * @dev_priv: driver private
284 * @interrupt_mask: mask of interrupt bits to update
285 * @enabled_irq_mask: mask of interrupt bits to enable
287 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
288 uint32_t interrupt_mask,
289 uint32_t enabled_irq_mask)
293 lockdep_assert_held(&dev_priv->irq_lock);
295 WARN_ON(enabled_irq_mask & ~interrupt_mask);
297 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
300 new_val = dev_priv->irq_mask;
301 new_val &= ~interrupt_mask;
302 new_val |= (~enabled_irq_mask & interrupt_mask);
304 if (new_val != dev_priv->irq_mask) {
305 dev_priv->irq_mask = new_val;
306 I915_WRITE(DEIMR, dev_priv->irq_mask);
312 * ilk_update_gt_irq - update GTIMR
313 * @dev_priv: driver private
314 * @interrupt_mask: mask of interrupt bits to update
315 * @enabled_irq_mask: mask of interrupt bits to enable
317 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
318 uint32_t interrupt_mask,
319 uint32_t enabled_irq_mask)
321 lockdep_assert_held(&dev_priv->irq_lock);
323 WARN_ON(enabled_irq_mask & ~interrupt_mask);
325 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
328 dev_priv->gt_irq_mask &= ~interrupt_mask;
329 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
330 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
333 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
335 ilk_update_gt_irq(dev_priv, mask, mask);
336 POSTING_READ_FW(GTIMR);
339 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
341 ilk_update_gt_irq(dev_priv, mask, 0);
344 static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
346 WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11);
348 return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
351 static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
353 if (INTEL_GEN(dev_priv) >= 11)
354 return GEN11_GPM_WGBOXPERF_INTR_MASK;
355 else if (INTEL_GEN(dev_priv) >= 8)
356 return GEN8_GT_IMR(2);
361 static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
363 if (INTEL_GEN(dev_priv) >= 11)
364 return GEN11_GPM_WGBOXPERF_INTR_ENABLE;
365 else if (INTEL_GEN(dev_priv) >= 8)
366 return GEN8_GT_IER(2);
372 * snb_update_pm_irq - update GEN6_PMIMR
373 * @dev_priv: driver private
374 * @interrupt_mask: mask of interrupt bits to update
375 * @enabled_irq_mask: mask of interrupt bits to enable
377 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
378 uint32_t interrupt_mask,
379 uint32_t enabled_irq_mask)
383 WARN_ON(enabled_irq_mask & ~interrupt_mask);
385 lockdep_assert_held(&dev_priv->irq_lock);
387 new_val = dev_priv->pm_imr;
388 new_val &= ~interrupt_mask;
389 new_val |= (~enabled_irq_mask & interrupt_mask);
391 if (new_val != dev_priv->pm_imr) {
392 dev_priv->pm_imr = new_val;
393 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_imr);
394 POSTING_READ(gen6_pm_imr(dev_priv));
398 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
400 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
403 snb_update_pm_irq(dev_priv, mask, mask);
406 static void __gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
408 snb_update_pm_irq(dev_priv, mask, 0);
411 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
413 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
416 __gen6_mask_pm_irq(dev_priv, mask);
419 static void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
421 i915_reg_t reg = gen6_pm_iir(dev_priv);
423 lockdep_assert_held(&dev_priv->irq_lock);
425 I915_WRITE(reg, reset_mask);
426 I915_WRITE(reg, reset_mask);
430 static void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
432 lockdep_assert_held(&dev_priv->irq_lock);
434 dev_priv->pm_ier |= enable_mask;
435 I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
436 gen6_unmask_pm_irq(dev_priv, enable_mask);
437 /* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
440 static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
442 lockdep_assert_held(&dev_priv->irq_lock);
444 dev_priv->pm_ier &= ~disable_mask;
445 __gen6_mask_pm_irq(dev_priv, disable_mask);
446 I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
447 /* though a barrier is missing here, but don't really need a one */
450 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv)
452 spin_lock_irq(&dev_priv->irq_lock);
454 while (gen11_reset_one_iir(dev_priv, 0, GEN11_GTPM))
457 dev_priv->gt_pm.rps.pm_iir = 0;
459 spin_unlock_irq(&dev_priv->irq_lock);
462 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
464 spin_lock_irq(&dev_priv->irq_lock);
465 gen6_reset_pm_iir(dev_priv, dev_priv->pm_rps_events);
466 dev_priv->gt_pm.rps.pm_iir = 0;
467 spin_unlock_irq(&dev_priv->irq_lock);
470 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
472 struct intel_rps *rps = &dev_priv->gt_pm.rps;
474 if (READ_ONCE(rps->interrupts_enabled))
477 spin_lock_irq(&dev_priv->irq_lock);
478 WARN_ON_ONCE(rps->pm_iir);
480 if (INTEL_GEN(dev_priv) >= 11)
481 WARN_ON_ONCE(gen11_reset_one_iir(dev_priv, 0, GEN11_GTPM));
483 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
485 rps->interrupts_enabled = true;
486 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
488 spin_unlock_irq(&dev_priv->irq_lock);
491 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
493 struct intel_rps *rps = &dev_priv->gt_pm.rps;
495 if (!READ_ONCE(rps->interrupts_enabled))
498 spin_lock_irq(&dev_priv->irq_lock);
499 rps->interrupts_enabled = false;
501 I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));
503 gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
505 spin_unlock_irq(&dev_priv->irq_lock);
506 synchronize_irq(dev_priv->drm.irq);
508 /* Now that we will not be generating any more work, flush any
509 * outstanding tasks. As we are called on the RPS idle path,
510 * we will reset the GPU to minimum frequencies, so the current
511 * state of the worker can be discarded.
513 cancel_work_sync(&rps->work);
514 if (INTEL_GEN(dev_priv) >= 11)
515 gen11_reset_rps_interrupts(dev_priv);
517 gen6_reset_rps_interrupts(dev_priv);
520 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
522 assert_rpm_wakelock_held(dev_priv);
524 spin_lock_irq(&dev_priv->irq_lock);
525 gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
526 spin_unlock_irq(&dev_priv->irq_lock);
529 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
531 assert_rpm_wakelock_held(dev_priv);
533 spin_lock_irq(&dev_priv->irq_lock);
534 if (!dev_priv->guc.interrupts_enabled) {
535 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
536 dev_priv->pm_guc_events);
537 dev_priv->guc.interrupts_enabled = true;
538 gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
540 spin_unlock_irq(&dev_priv->irq_lock);
543 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
545 assert_rpm_wakelock_held(dev_priv);
547 spin_lock_irq(&dev_priv->irq_lock);
548 dev_priv->guc.interrupts_enabled = false;
550 gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events);
552 spin_unlock_irq(&dev_priv->irq_lock);
553 synchronize_irq(dev_priv->drm.irq);
555 gen9_reset_guc_interrupts(dev_priv);
559 * bdw_update_port_irq - update DE port interrupt
560 * @dev_priv: driver private
561 * @interrupt_mask: mask of interrupt bits to update
562 * @enabled_irq_mask: mask of interrupt bits to enable
564 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
565 uint32_t interrupt_mask,
566 uint32_t enabled_irq_mask)
571 lockdep_assert_held(&dev_priv->irq_lock);
573 WARN_ON(enabled_irq_mask & ~interrupt_mask);
575 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
578 old_val = I915_READ(GEN8_DE_PORT_IMR);
581 new_val &= ~interrupt_mask;
582 new_val |= (~enabled_irq_mask & interrupt_mask);
584 if (new_val != old_val) {
585 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
586 POSTING_READ(GEN8_DE_PORT_IMR);
591 * bdw_update_pipe_irq - update DE pipe interrupt
592 * @dev_priv: driver private
593 * @pipe: pipe whose interrupt to update
594 * @interrupt_mask: mask of interrupt bits to update
595 * @enabled_irq_mask: mask of interrupt bits to enable
597 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
599 uint32_t interrupt_mask,
600 uint32_t enabled_irq_mask)
604 lockdep_assert_held(&dev_priv->irq_lock);
606 WARN_ON(enabled_irq_mask & ~interrupt_mask);
608 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
611 new_val = dev_priv->de_irq_mask[pipe];
612 new_val &= ~interrupt_mask;
613 new_val |= (~enabled_irq_mask & interrupt_mask);
615 if (new_val != dev_priv->de_irq_mask[pipe]) {
616 dev_priv->de_irq_mask[pipe] = new_val;
617 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
618 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
623 * ibx_display_interrupt_update - update SDEIMR
624 * @dev_priv: driver private
625 * @interrupt_mask: mask of interrupt bits to update
626 * @enabled_irq_mask: mask of interrupt bits to enable
628 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
629 uint32_t interrupt_mask,
630 uint32_t enabled_irq_mask)
632 uint32_t sdeimr = I915_READ(SDEIMR);
633 sdeimr &= ~interrupt_mask;
634 sdeimr |= (~enabled_irq_mask & interrupt_mask);
636 WARN_ON(enabled_irq_mask & ~interrupt_mask);
638 lockdep_assert_held(&dev_priv->irq_lock);
640 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
643 I915_WRITE(SDEIMR, sdeimr);
644 POSTING_READ(SDEIMR);
647 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
650 u32 status_mask = dev_priv->pipestat_irq_mask[pipe];
651 u32 enable_mask = status_mask << 16;
653 lockdep_assert_held(&dev_priv->irq_lock);
655 if (INTEL_GEN(dev_priv) < 5)
659 * On pipe A we don't support the PSR interrupt yet,
660 * on pipe B and C the same bit MBZ.
662 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
665 * On pipe B and C we don't support the PSR interrupt yet, on pipe
666 * A the same bit is for perf counters which we don't use either.
668 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
671 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
672 SPRITE0_FLIP_DONE_INT_EN_VLV |
673 SPRITE1_FLIP_DONE_INT_EN_VLV);
674 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
675 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
676 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
677 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
680 WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
681 status_mask & ~PIPESTAT_INT_STATUS_MASK,
682 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
683 pipe_name(pipe), enable_mask, status_mask);
688 void i915_enable_pipestat(struct drm_i915_private *dev_priv,
689 enum pipe pipe, u32 status_mask)
691 i915_reg_t reg = PIPESTAT(pipe);
694 WARN_ONCE(status_mask & ~PIPESTAT_INT_STATUS_MASK,
695 "pipe %c: status_mask=0x%x\n",
696 pipe_name(pipe), status_mask);
698 lockdep_assert_held(&dev_priv->irq_lock);
699 WARN_ON(!intel_irqs_enabled(dev_priv));
701 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask)
704 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
705 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
707 I915_WRITE(reg, enable_mask | status_mask);
711 void i915_disable_pipestat(struct drm_i915_private *dev_priv,
712 enum pipe pipe, u32 status_mask)
714 i915_reg_t reg = PIPESTAT(pipe);
717 WARN_ONCE(status_mask & ~PIPESTAT_INT_STATUS_MASK,
718 "pipe %c: status_mask=0x%x\n",
719 pipe_name(pipe), status_mask);
721 lockdep_assert_held(&dev_priv->irq_lock);
722 WARN_ON(!intel_irqs_enabled(dev_priv));
724 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0)
727 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
728 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
730 I915_WRITE(reg, enable_mask | status_mask);
735 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
736 * @dev_priv: i915 device private
738 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
740 if (!dev_priv->opregion.asle || !IS_MOBILE(dev_priv))
743 spin_lock_irq(&dev_priv->irq_lock);
745 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
746 if (INTEL_GEN(dev_priv) >= 4)
747 i915_enable_pipestat(dev_priv, PIPE_A,
748 PIPE_LEGACY_BLC_EVENT_STATUS);
750 spin_unlock_irq(&dev_priv->irq_lock);
754 * This timing diagram depicts the video signal in and
755 * around the vertical blanking period.
757 * Assumptions about the fictitious mode used in this example:
759 * vsync_start = vblank_start + 1
760 * vsync_end = vblank_start + 2
761 * vtotal = vblank_start + 3
764 * latch double buffered registers
765 * increment frame counter (ctg+)
766 * generate start of vblank interrupt (gen4+)
769 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
770 * | may be shifted forward 1-3 extra lines via PIPECONF
772 * | | start of vsync:
773 * | | generate vsync interrupt
775 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
776 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
777 * ----va---> <-----------------vb--------------------> <--------va-------------
778 * | | <----vs-----> |
779 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
780 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
781 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
783 * last visible pixel first visible pixel
784 * | increment frame counter (gen3/4)
785 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
787 * x = horizontal active
788 * _ = horizontal blanking
789 * hs = horizontal sync
790 * va = vertical active
791 * vb = vertical blanking
793 * vbs = vblank_start (number)
796 * - most events happen at the start of horizontal sync
797 * - frame start happens at the start of horizontal blank, 1-4 lines
798 * (depending on PIPECONF settings) after the start of vblank
799 * - gen3/4 pixel and frame counter are synchronized with the start
800 * of horizontal active on the first line of vertical active
803 /* Called from drm generic code, passed a 'crtc', which
804 * we use as a pipe index
806 static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
808 struct drm_i915_private *dev_priv = to_i915(dev);
809 i915_reg_t high_frame, low_frame;
810 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
811 const struct drm_display_mode *mode = &dev->vblank[pipe].hwmode;
812 unsigned long irqflags;
814 htotal = mode->crtc_htotal;
815 hsync_start = mode->crtc_hsync_start;
816 vbl_start = mode->crtc_vblank_start;
817 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
818 vbl_start = DIV_ROUND_UP(vbl_start, 2);
820 /* Convert to pixel count */
823 /* Start of vblank event occurs at start of hsync */
824 vbl_start -= htotal - hsync_start;
826 high_frame = PIPEFRAME(pipe);
827 low_frame = PIPEFRAMEPIXEL(pipe);
829 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
832 * High & low register fields aren't synchronized, so make sure
833 * we get a low value that's stable across two reads of the high
837 high1 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK;
838 low = I915_READ_FW(low_frame);
839 high2 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK;
840 } while (high1 != high2);
842 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
844 high1 >>= PIPE_FRAME_HIGH_SHIFT;
845 pixel = low & PIPE_PIXEL_MASK;
846 low >>= PIPE_FRAME_LOW_SHIFT;
849 * The frame counter increments at beginning of active.
850 * Cook up a vblank counter by also checking the pixel
851 * counter against vblank start.
853 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
856 static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
858 struct drm_i915_private *dev_priv = to_i915(dev);
860 return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
864 * On certain encoders on certain platforms, pipe
865 * scanline register will not work to get the scanline,
866 * since the timings are driven from the PORT or issues
867 * with scanline register updates.
868 * This function will use Framestamp and current
869 * timestamp registers to calculate the scanline.
871 static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
873 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
874 struct drm_vblank_crtc *vblank =
875 &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
876 const struct drm_display_mode *mode = &vblank->hwmode;
877 u32 vblank_start = mode->crtc_vblank_start;
878 u32 vtotal = mode->crtc_vtotal;
879 u32 htotal = mode->crtc_htotal;
880 u32 clock = mode->crtc_clock;
881 u32 scanline, scan_prev_time, scan_curr_time, scan_post_time;
884 * To avoid the race condition where we might cross into the
885 * next vblank just between the PIPE_FRMTMSTMP and TIMESTAMP_CTR
886 * reads. We make sure we read PIPE_FRMTMSTMP and TIMESTAMP_CTR
887 * during the same frame.
891 * This field provides read back of the display
892 * pipe frame time stamp. The time stamp value
893 * is sampled at every start of vertical blank.
895 scan_prev_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe));
898 * The TIMESTAMP_CTR register has the current
901 scan_curr_time = I915_READ_FW(IVB_TIMESTAMP_CTR);
903 scan_post_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe));
904 } while (scan_post_time != scan_prev_time);
906 scanline = div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
907 clock), 1000 * htotal);
908 scanline = min(scanline, vtotal - 1);
909 scanline = (scanline + vblank_start) % vtotal;
914 /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
915 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
917 struct drm_device *dev = crtc->base.dev;
918 struct drm_i915_private *dev_priv = to_i915(dev);
919 const struct drm_display_mode *mode;
920 struct drm_vblank_crtc *vblank;
921 enum pipe pipe = crtc->pipe;
922 int position, vtotal;
927 vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
928 mode = &vblank->hwmode;
930 if (mode->private_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
931 return __intel_get_crtc_scanline_from_timestamp(crtc);
933 vtotal = mode->crtc_vtotal;
934 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
937 if (IS_GEN2(dev_priv))
938 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
940 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
943 * On HSW, the DSL reg (0x70000) appears to return 0 if we
944 * read it just before the start of vblank. So try it again
945 * so we don't accidentally end up spanning a vblank frame
946 * increment, causing the pipe_update_end() code to squak at us.
948 * The nature of this problem means we can't simply check the ISR
949 * bit and return the vblank start value; nor can we use the scanline
950 * debug register in the transcoder as it appears to have the same
951 * problem. We may need to extend this to include other platforms,
952 * but so far testing only shows the problem on HSW.
954 if (HAS_DDI(dev_priv) && !position) {
957 for (i = 0; i < 100; i++) {
959 temp = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
960 if (temp != position) {
968 * See update_scanline_offset() for the details on the
969 * scanline_offset adjustment.
971 return (position + crtc->scanline_offset) % vtotal;
974 static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
975 bool in_vblank_irq, int *vpos, int *hpos,
976 ktime_t *stime, ktime_t *etime,
977 const struct drm_display_mode *mode)
979 struct drm_i915_private *dev_priv = to_i915(dev);
980 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
983 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
984 unsigned long irqflags;
986 if (WARN_ON(!mode->crtc_clock)) {
987 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
988 "pipe %c\n", pipe_name(pipe));
992 htotal = mode->crtc_htotal;
993 hsync_start = mode->crtc_hsync_start;
994 vtotal = mode->crtc_vtotal;
995 vbl_start = mode->crtc_vblank_start;
996 vbl_end = mode->crtc_vblank_end;
998 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
999 vbl_start = DIV_ROUND_UP(vbl_start, 2);
1005 * Lock uncore.lock, as we will do multiple timing critical raw
1006 * register reads, potentially with preemption disabled, so the
1007 * following code must not block on uncore.lock.
1009 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1011 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1013 /* Get optional system timestamp before query. */
1015 *stime = ktime_get();
1017 if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
1018 /* No obvious pixelcount register. Only query vertical
1019 * scanout position from Display scan line register.
1021 position = __intel_get_crtc_scanline(intel_crtc);
1023 /* Have access to pixelcount since start of frame.
1024 * We can split this into vertical and horizontal
1027 position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
1029 /* convert to pixel counts */
1030 vbl_start *= htotal;
1035 * In interlaced modes, the pixel counter counts all pixels,
1036 * so one field will have htotal more pixels. In order to avoid
1037 * the reported position from jumping backwards when the pixel
1038 * counter is beyond the length of the shorter field, just
1039 * clamp the position the length of the shorter field. This
1040 * matches how the scanline counter based position works since
1041 * the scanline counter doesn't count the two half lines.
1043 if (position >= vtotal)
1044 position = vtotal - 1;
1047 * Start of vblank interrupt is triggered at start of hsync,
1048 * just prior to the first active line of vblank. However we
1049 * consider lines to start at the leading edge of horizontal
1050 * active. So, should we get here before we've crossed into
1051 * the horizontal active of the first line in vblank, we would
1052 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
1053 * always add htotal-hsync_start to the current pixel position.
1055 position = (position + htotal - hsync_start) % vtotal;
1058 /* Get optional system timestamp after query. */
1060 *etime = ktime_get();
1062 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1064 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1067 * While in vblank, position will be negative
1068 * counting up towards 0 at vbl_end. And outside
1069 * vblank, position will be positive counting
1072 if (position >= vbl_start)
1073 position -= vbl_end;
1075 position += vtotal - vbl_end;
1077 if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
1081 *vpos = position / htotal;
1082 *hpos = position - (*vpos * htotal);
1088 int intel_get_crtc_scanline(struct intel_crtc *crtc)
1090 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1091 unsigned long irqflags;
1094 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1095 position = __intel_get_crtc_scanline(crtc);
1096 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1101 static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
1103 u32 busy_up, busy_down, max_avg, min_avg;
1106 spin_lock(&mchdev_lock);
1108 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
1110 new_delay = dev_priv->ips.cur_delay;
1112 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
1113 busy_up = I915_READ(RCPREVBSYTUPAVG);
1114 busy_down = I915_READ(RCPREVBSYTDNAVG);
1115 max_avg = I915_READ(RCBMAXAVG);
1116 min_avg = I915_READ(RCBMINAVG);
1118 /* Handle RCS change request from hw */
1119 if (busy_up > max_avg) {
1120 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1121 new_delay = dev_priv->ips.cur_delay - 1;
1122 if (new_delay < dev_priv->ips.max_delay)
1123 new_delay = dev_priv->ips.max_delay;
1124 } else if (busy_down < min_avg) {
1125 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1126 new_delay = dev_priv->ips.cur_delay + 1;
1127 if (new_delay > dev_priv->ips.min_delay)
1128 new_delay = dev_priv->ips.min_delay;
1131 if (ironlake_set_drps(dev_priv, new_delay))
1132 dev_priv->ips.cur_delay = new_delay;
1134 spin_unlock(&mchdev_lock);
1139 static void notify_ring(struct intel_engine_cs *engine)
1141 struct i915_request *rq = NULL;
1142 struct intel_wait *wait;
1144 if (!engine->breadcrumbs.irq_armed)
1147 atomic_inc(&engine->irq_count);
1148 set_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted);
1150 spin_lock(&engine->breadcrumbs.irq_lock);
1151 wait = engine->breadcrumbs.irq_wait;
1153 bool wakeup = engine->irq_seqno_barrier;
1155 /* We use a callback from the dma-fence to submit
1156 * requests after waiting on our own requests. To
1157 * ensure minimum delay in queuing the next request to
1158 * hardware, signal the fence now rather than wait for
1159 * the signaler to be woken up. We still wake up the
1160 * waiter in order to handle the irq-seqno coherency
1161 * issues (we may receive the interrupt before the
1162 * seqno is written, see __i915_request_irq_complete())
1163 * and to handle coalescing of multiple seqno updates
1166 if (i915_seqno_passed(intel_engine_get_seqno(engine),
1168 struct i915_request *waiter = wait->request;
1171 if (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
1172 &waiter->fence.flags) &&
1173 intel_wait_check_request(wait, waiter))
1174 rq = i915_request_get(waiter);
1178 wake_up_process(wait->tsk);
1180 if (engine->breadcrumbs.irq_armed)
1181 __intel_engine_disarm_breadcrumbs(engine);
1183 spin_unlock(&engine->breadcrumbs.irq_lock);
1186 dma_fence_signal(&rq->fence);
1187 GEM_BUG_ON(!i915_request_completed(rq));
1188 i915_request_put(rq);
1191 trace_intel_engine_notify(engine, wait);
1194 static void vlv_c0_read(struct drm_i915_private *dev_priv,
1195 struct intel_rps_ei *ei)
1197 ei->ktime = ktime_get_raw();
1198 ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
1199 ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
1202 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1204 memset(&dev_priv->gt_pm.rps.ei, 0, sizeof(dev_priv->gt_pm.rps.ei));
1207 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1209 struct intel_rps *rps = &dev_priv->gt_pm.rps;
1210 const struct intel_rps_ei *prev = &rps->ei;
1211 struct intel_rps_ei now;
1214 if ((pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) == 0)
1217 vlv_c0_read(dev_priv, &now);
1223 time = ktime_us_delta(now.ktime, prev->ktime);
1225 time *= dev_priv->czclk_freq;
1227 /* Workload can be split between render + media,
1228 * e.g. SwapBuffers being blitted in X after being rendered in
1229 * mesa. To account for this we need to combine both engines
1230 * into our activity counter.
1232 render = now.render_c0 - prev->render_c0;
1233 media = now.media_c0 - prev->media_c0;
1234 c0 = max(render, media);
1235 c0 *= 1000 * 100 << 8; /* to usecs and scale to threshold% */
1237 if (c0 > time * rps->up_threshold)
1238 events = GEN6_PM_RP_UP_THRESHOLD;
1239 else if (c0 < time * rps->down_threshold)
1240 events = GEN6_PM_RP_DOWN_THRESHOLD;
1247 static void gen6_pm_rps_work(struct work_struct *work)
1249 struct drm_i915_private *dev_priv =
1250 container_of(work, struct drm_i915_private, gt_pm.rps.work);
1251 struct intel_rps *rps = &dev_priv->gt_pm.rps;
1252 bool client_boost = false;
1253 int new_delay, adj, min, max;
1256 spin_lock_irq(&dev_priv->irq_lock);
1257 if (rps->interrupts_enabled) {
1258 pm_iir = fetch_and_zero(&rps->pm_iir);
1259 client_boost = atomic_read(&rps->num_waiters);
1261 spin_unlock_irq(&dev_priv->irq_lock);
1263 /* Make sure we didn't queue anything we're not going to process. */
1264 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1265 if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1268 mutex_lock(&dev_priv->pcu_lock);
1270 pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1272 adj = rps->last_adj;
1273 new_delay = rps->cur_freq;
1274 min = rps->min_freq_softlimit;
1275 max = rps->max_freq_softlimit;
1277 max = rps->max_freq;
1278 if (client_boost && new_delay < rps->boost_freq) {
1279 new_delay = rps->boost_freq;
1281 } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1284 else /* CHV needs even encode values */
1285 adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1287 if (new_delay >= rps->max_freq_softlimit)
1289 } else if (client_boost) {
1291 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1292 if (rps->cur_freq > rps->efficient_freq)
1293 new_delay = rps->efficient_freq;
1294 else if (rps->cur_freq > rps->min_freq_softlimit)
1295 new_delay = rps->min_freq_softlimit;
1297 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1300 else /* CHV needs even encode values */
1301 adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1303 if (new_delay <= rps->min_freq_softlimit)
1305 } else { /* unknown event */
1309 rps->last_adj = adj;
1311 /* sysfs frequency interfaces may have snuck in while servicing the
1315 new_delay = clamp_t(int, new_delay, min, max);
1317 if (intel_set_rps(dev_priv, new_delay)) {
1318 DRM_DEBUG_DRIVER("Failed to set new GPU frequency\n");
1322 mutex_unlock(&dev_priv->pcu_lock);
1325 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1326 spin_lock_irq(&dev_priv->irq_lock);
1327 if (rps->interrupts_enabled)
1328 gen6_unmask_pm_irq(dev_priv, dev_priv->pm_rps_events);
1329 spin_unlock_irq(&dev_priv->irq_lock);
1334 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1336 * @work: workqueue struct
1338 * Doesn't actually do anything except notify userspace. As a consequence of
1339 * this event, userspace should try to remap the bad rows since statistically
1340 * it is likely the same row is more likely to go bad again.
1342 static void ivybridge_parity_work(struct work_struct *work)
1344 struct drm_i915_private *dev_priv =
1345 container_of(work, typeof(*dev_priv), l3_parity.error_work);
1346 u32 error_status, row, bank, subbank;
1347 char *parity_event[6];
1351 /* We must turn off DOP level clock gating to access the L3 registers.
1352 * In order to prevent a get/put style interface, acquire struct mutex
1353 * any time we access those registers.
1355 mutex_lock(&dev_priv->drm.struct_mutex);
1357 /* If we've screwed up tracking, just let the interrupt fire again */
1358 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1361 misccpctl = I915_READ(GEN7_MISCCPCTL);
1362 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1363 POSTING_READ(GEN7_MISCCPCTL);
1365 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1369 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv)))
1372 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1374 reg = GEN7_L3CDERRST1(slice);
1376 error_status = I915_READ(reg);
1377 row = GEN7_PARITY_ERROR_ROW(error_status);
1378 bank = GEN7_PARITY_ERROR_BANK(error_status);
1379 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1381 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1384 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1385 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1386 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1387 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1388 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1389 parity_event[5] = NULL;
1391 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
1392 KOBJ_CHANGE, parity_event);
1394 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1395 slice, row, bank, subbank);
1397 kfree(parity_event[4]);
1398 kfree(parity_event[3]);
1399 kfree(parity_event[2]);
1400 kfree(parity_event[1]);
1403 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1406 WARN_ON(dev_priv->l3_parity.which_slice);
1407 spin_lock_irq(&dev_priv->irq_lock);
1408 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1409 spin_unlock_irq(&dev_priv->irq_lock);
1411 mutex_unlock(&dev_priv->drm.struct_mutex);
1414 static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv,
1417 if (!HAS_L3_DPF(dev_priv))
1420 spin_lock(&dev_priv->irq_lock);
1421 gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1422 spin_unlock(&dev_priv->irq_lock);
1424 iir &= GT_PARITY_ERROR(dev_priv);
1425 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1426 dev_priv->l3_parity.which_slice |= 1 << 1;
1428 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1429 dev_priv->l3_parity.which_slice |= 1 << 0;
1431 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1434 static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
1437 if (gt_iir & GT_RENDER_USER_INTERRUPT)
1438 notify_ring(dev_priv->engine[RCS]);
1439 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1440 notify_ring(dev_priv->engine[VCS]);
1443 static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
1446 if (gt_iir & GT_RENDER_USER_INTERRUPT)
1447 notify_ring(dev_priv->engine[RCS]);
1448 if (gt_iir & GT_BSD_USER_INTERRUPT)
1449 notify_ring(dev_priv->engine[VCS]);
1450 if (gt_iir & GT_BLT_USER_INTERRUPT)
1451 notify_ring(dev_priv->engine[BCS]);
1453 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1454 GT_BSD_CS_ERROR_INTERRUPT |
1455 GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1456 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1458 if (gt_iir & GT_PARITY_ERROR(dev_priv))
1459 ivybridge_parity_error_irq_handler(dev_priv, gt_iir);
1463 gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
1465 struct intel_engine_execlists * const execlists = &engine->execlists;
1466 bool tasklet = false;
1468 if (iir & GT_CONTEXT_SWITCH_INTERRUPT) {
1469 if (READ_ONCE(engine->execlists.active))
1470 tasklet = !test_and_set_bit(ENGINE_IRQ_EXECLIST,
1471 &engine->irq_posted);
1474 if (iir & GT_RENDER_USER_INTERRUPT) {
1475 notify_ring(engine);
1476 tasklet |= USES_GUC_SUBMISSION(engine->i915);
1480 tasklet_hi_schedule(&execlists->tasklet);
1483 static void gen8_gt_irq_ack(struct drm_i915_private *i915,
1484 u32 master_ctl, u32 gt_iir[4])
1486 void __iomem * const regs = i915->regs;
1488 #define GEN8_GT_IRQS (GEN8_GT_RCS_IRQ | \
1490 GEN8_GT_VCS1_IRQ | \
1491 GEN8_GT_VCS2_IRQ | \
1492 GEN8_GT_VECS_IRQ | \
1496 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1497 gt_iir[0] = raw_reg_read(regs, GEN8_GT_IIR(0));
1498 if (likely(gt_iir[0]))
1499 raw_reg_write(regs, GEN8_GT_IIR(0), gt_iir[0]);
1502 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1503 gt_iir[1] = raw_reg_read(regs, GEN8_GT_IIR(1));
1504 if (likely(gt_iir[1]))
1505 raw_reg_write(regs, GEN8_GT_IIR(1), gt_iir[1]);
1508 if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
1509 gt_iir[2] = raw_reg_read(regs, GEN8_GT_IIR(2));
1510 if (likely(gt_iir[2] & (i915->pm_rps_events |
1511 i915->pm_guc_events)))
1512 raw_reg_write(regs, GEN8_GT_IIR(2),
1513 gt_iir[2] & (i915->pm_rps_events |
1514 i915->pm_guc_events));
1517 if (master_ctl & GEN8_GT_VECS_IRQ) {
1518 gt_iir[3] = raw_reg_read(regs, GEN8_GT_IIR(3));
1519 if (likely(gt_iir[3]))
1520 raw_reg_write(regs, GEN8_GT_IIR(3), gt_iir[3]);
1524 static void gen8_gt_irq_handler(struct drm_i915_private *i915,
1525 u32 master_ctl, u32 gt_iir[4])
1527 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1528 gen8_cs_irq_handler(i915->engine[RCS],
1529 gt_iir[0] >> GEN8_RCS_IRQ_SHIFT);
1530 gen8_cs_irq_handler(i915->engine[BCS],
1531 gt_iir[0] >> GEN8_BCS_IRQ_SHIFT);
1534 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1535 gen8_cs_irq_handler(i915->engine[VCS],
1536 gt_iir[1] >> GEN8_VCS1_IRQ_SHIFT);
1537 gen8_cs_irq_handler(i915->engine[VCS2],
1538 gt_iir[1] >> GEN8_VCS2_IRQ_SHIFT);
1541 if (master_ctl & GEN8_GT_VECS_IRQ) {
1542 gen8_cs_irq_handler(i915->engine[VECS],
1543 gt_iir[3] >> GEN8_VECS_IRQ_SHIFT);
1546 if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
1547 gen6_rps_irq_handler(i915, gt_iir[2]);
1548 gen9_guc_irq_handler(i915, gt_iir[2]);
1552 static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
1556 return val & PORTA_HOTPLUG_LONG_DETECT;
1558 return val & PORTB_HOTPLUG_LONG_DETECT;
1560 return val & PORTC_HOTPLUG_LONG_DETECT;
1566 static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
1570 return val & PORTE_HOTPLUG_LONG_DETECT;
1576 static bool spt_port_hotplug_long_detect(enum port port, u32 val)
1580 return val & PORTA_HOTPLUG_LONG_DETECT;
1582 return val & PORTB_HOTPLUG_LONG_DETECT;
1584 return val & PORTC_HOTPLUG_LONG_DETECT;
1586 return val & PORTD_HOTPLUG_LONG_DETECT;
1592 static bool ilk_port_hotplug_long_detect(enum port port, u32 val)
1596 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1602 static bool pch_port_hotplug_long_detect(enum port port, u32 val)
1606 return val & PORTB_HOTPLUG_LONG_DETECT;
1608 return val & PORTC_HOTPLUG_LONG_DETECT;
1610 return val & PORTD_HOTPLUG_LONG_DETECT;
1616 static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
1620 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1622 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1624 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1631 * Get a bit mask of pins that have triggered, and which ones may be long.
1632 * This can be called multiple times with the same masks to accumulate
1633 * hotplug detection results from several registers.
1635 * Note that the caller is expected to zero out the masks initially.
1637 static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
1638 u32 *pin_mask, u32 *long_mask,
1639 u32 hotplug_trigger, u32 dig_hotplug_reg,
1640 const u32 hpd[HPD_NUM_PINS],
1641 bool long_pulse_detect(enum port port, u32 val))
1646 for_each_hpd_pin(i) {
1647 if ((hpd[i] & hotplug_trigger) == 0)
1650 *pin_mask |= BIT(i);
1652 port = intel_hpd_pin_to_port(dev_priv, i);
1653 if (port == PORT_NONE)
1656 if (long_pulse_detect(port, dig_hotplug_reg))
1657 *long_mask |= BIT(i);
1660 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1661 hotplug_trigger, dig_hotplug_reg, *pin_mask);
1665 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1667 wake_up_all(&dev_priv->gmbus_wait_queue);
1670 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1672 wake_up_all(&dev_priv->gmbus_wait_queue);
1675 #if defined(CONFIG_DEBUG_FS)
1676 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1678 uint32_t crc0, uint32_t crc1,
1679 uint32_t crc2, uint32_t crc3,
1682 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1683 struct intel_pipe_crc_entry *entry;
1684 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1685 struct drm_driver *driver = dev_priv->drm.driver;
1689 spin_lock(&pipe_crc->lock);
1690 if (pipe_crc->source && !crtc->base.crc.opened) {
1691 if (!pipe_crc->entries) {
1692 spin_unlock(&pipe_crc->lock);
1693 DRM_DEBUG_KMS("spurious interrupt\n");
1697 head = pipe_crc->head;
1698 tail = pipe_crc->tail;
1700 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1701 spin_unlock(&pipe_crc->lock);
1702 DRM_ERROR("CRC buffer overflowing\n");
1706 entry = &pipe_crc->entries[head];
1708 entry->frame = driver->get_vblank_counter(&dev_priv->drm, pipe);
1709 entry->crc[0] = crc0;
1710 entry->crc[1] = crc1;
1711 entry->crc[2] = crc2;
1712 entry->crc[3] = crc3;
1713 entry->crc[4] = crc4;
1715 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1716 pipe_crc->head = head;
1718 spin_unlock(&pipe_crc->lock);
1720 wake_up_interruptible(&pipe_crc->wq);
1723 * For some not yet identified reason, the first CRC is
1724 * bonkers. So let's just wait for the next vblank and read
1725 * out the buggy result.
1727 * On GEN8+ sometimes the second CRC is bonkers as well, so
1728 * don't trust that one either.
1730 if (pipe_crc->skipped <= 0 ||
1731 (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
1732 pipe_crc->skipped++;
1733 spin_unlock(&pipe_crc->lock);
1736 spin_unlock(&pipe_crc->lock);
1742 drm_crtc_add_crc_entry(&crtc->base, true,
1743 drm_crtc_accurate_vblank_count(&crtc->base),
1749 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1751 uint32_t crc0, uint32_t crc1,
1752 uint32_t crc2, uint32_t crc3,
1757 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1760 display_pipe_crc_irq_handler(dev_priv, pipe,
1761 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1765 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1768 display_pipe_crc_irq_handler(dev_priv, pipe,
1769 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1770 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1771 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1772 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1773 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1776 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1779 uint32_t res1, res2;
1781 if (INTEL_GEN(dev_priv) >= 3)
1782 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1786 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1787 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1791 display_pipe_crc_irq_handler(dev_priv, pipe,
1792 I915_READ(PIPE_CRC_RES_RED(pipe)),
1793 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1794 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1798 /* The RPS events need forcewake, so we add them to a work queue and mask their
1799 * IMR bits until the work is done. Other interrupts can be processed without
1800 * the work queue. */
1801 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1803 struct intel_rps *rps = &dev_priv->gt_pm.rps;
1805 if (pm_iir & dev_priv->pm_rps_events) {
1806 spin_lock(&dev_priv->irq_lock);
1807 gen6_mask_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1808 if (rps->interrupts_enabled) {
1809 rps->pm_iir |= pm_iir & dev_priv->pm_rps_events;
1810 schedule_work(&rps->work);
1812 spin_unlock(&dev_priv->irq_lock);
1815 if (INTEL_GEN(dev_priv) >= 8)
1818 if (HAS_VEBOX(dev_priv)) {
1819 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1820 notify_ring(dev_priv->engine[VECS]);
1822 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1823 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1827 static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
1829 if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT)
1830 intel_guc_to_host_event_handler(&dev_priv->guc);
1833 static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
1837 for_each_pipe(dev_priv, pipe) {
1838 I915_WRITE(PIPESTAT(pipe),
1839 PIPESTAT_INT_STATUS_MASK |
1840 PIPE_FIFO_UNDERRUN_STATUS);
1842 dev_priv->pipestat_irq_mask[pipe] = 0;
1846 static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1847 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1851 spin_lock(&dev_priv->irq_lock);
1853 if (!dev_priv->display_irqs_enabled) {
1854 spin_unlock(&dev_priv->irq_lock);
1858 for_each_pipe(dev_priv, pipe) {
1860 u32 status_mask, enable_mask, iir_bit = 0;
1863 * PIPESTAT bits get signalled even when the interrupt is
1864 * disabled with the mask bits, and some of the status bits do
1865 * not generate interrupts at all (like the underrun bit). Hence
1866 * we need to be careful that we only handle what we want to
1870 /* fifo underruns are filterered in the underrun handler. */
1871 status_mask = PIPE_FIFO_UNDERRUN_STATUS;
1875 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1878 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1881 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1885 status_mask |= dev_priv->pipestat_irq_mask[pipe];
1890 reg = PIPESTAT(pipe);
1891 pipe_stats[pipe] = I915_READ(reg) & status_mask;
1892 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
1895 * Clear the PIPE*STAT regs before the IIR
1897 if (pipe_stats[pipe])
1898 I915_WRITE(reg, enable_mask | pipe_stats[pipe]);
1900 spin_unlock(&dev_priv->irq_lock);
1903 static void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1904 u16 iir, u32 pipe_stats[I915_MAX_PIPES])
1908 for_each_pipe(dev_priv, pipe) {
1909 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1910 drm_handle_vblank(&dev_priv->drm, pipe);
1912 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1913 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1915 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1916 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1920 static void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1921 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1923 bool blc_event = false;
1926 for_each_pipe(dev_priv, pipe) {
1927 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1928 drm_handle_vblank(&dev_priv->drm, pipe);
1930 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1933 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1934 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1936 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1937 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1940 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1941 intel_opregion_asle_intr(dev_priv);
1944 static void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1945 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1947 bool blc_event = false;
1950 for_each_pipe(dev_priv, pipe) {
1951 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1952 drm_handle_vblank(&dev_priv->drm, pipe);
1954 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1957 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1958 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1960 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1961 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1964 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1965 intel_opregion_asle_intr(dev_priv);
1967 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1968 gmbus_irq_handler(dev_priv);
1971 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1972 u32 pipe_stats[I915_MAX_PIPES])
1976 for_each_pipe(dev_priv, pipe) {
1977 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1978 drm_handle_vblank(&dev_priv->drm, pipe);
1980 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1981 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1983 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1984 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1987 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1988 gmbus_irq_handler(dev_priv);
1991 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1993 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1996 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1998 return hotplug_status;
2001 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
2004 u32 pin_mask = 0, long_mask = 0;
2006 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
2007 IS_CHERRYVIEW(dev_priv)) {
2008 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
2010 if (hotplug_trigger) {
2011 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2012 hotplug_trigger, hotplug_trigger,
2014 i9xx_port_hotplug_long_detect);
2016 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2019 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
2020 dp_aux_irq_handler(dev_priv);
2022 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
2024 if (hotplug_trigger) {
2025 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2026 hotplug_trigger, hotplug_trigger,
2028 i9xx_port_hotplug_long_detect);
2029 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2034 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
2036 struct drm_device *dev = arg;
2037 struct drm_i915_private *dev_priv = to_i915(dev);
2038 irqreturn_t ret = IRQ_NONE;
2040 if (!intel_irqs_enabled(dev_priv))
2043 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2044 disable_rpm_wakeref_asserts(dev_priv);
2047 u32 iir, gt_iir, pm_iir;
2048 u32 pipe_stats[I915_MAX_PIPES] = {};
2049 u32 hotplug_status = 0;
2052 gt_iir = I915_READ(GTIIR);
2053 pm_iir = I915_READ(GEN6_PMIIR);
2054 iir = I915_READ(VLV_IIR);
2056 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
2062 * Theory on interrupt generation, based on empirical evidence:
2064 * x = ((VLV_IIR & VLV_IER) ||
2065 * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
2066 * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
2068 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
2069 * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
2070 * guarantee the CPU interrupt will be raised again even if we
2071 * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
2072 * bits this time around.
2074 I915_WRITE(VLV_MASTER_IER, 0);
2075 ier = I915_READ(VLV_IER);
2076 I915_WRITE(VLV_IER, 0);
2079 I915_WRITE(GTIIR, gt_iir);
2081 I915_WRITE(GEN6_PMIIR, pm_iir);
2083 if (iir & I915_DISPLAY_PORT_INTERRUPT)
2084 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
2086 /* Call regardless, as some status bits might not be
2087 * signalled in iir */
2088 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
2090 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
2091 I915_LPE_PIPE_B_INTERRUPT))
2092 intel_lpe_audio_irq_handler(dev_priv);
2095 * VLV_IIR is single buffered, and reflects the level
2096 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
2099 I915_WRITE(VLV_IIR, iir);
2101 I915_WRITE(VLV_IER, ier);
2102 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2103 POSTING_READ(VLV_MASTER_IER);
2106 snb_gt_irq_handler(dev_priv, gt_iir);
2108 gen6_rps_irq_handler(dev_priv, pm_iir);
2111 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
2113 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
2116 enable_rpm_wakeref_asserts(dev_priv);
2121 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
2123 struct drm_device *dev = arg;
2124 struct drm_i915_private *dev_priv = to_i915(dev);
2125 irqreturn_t ret = IRQ_NONE;
2127 if (!intel_irqs_enabled(dev_priv))
2130 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2131 disable_rpm_wakeref_asserts(dev_priv);
2134 u32 master_ctl, iir;
2135 u32 pipe_stats[I915_MAX_PIPES] = {};
2136 u32 hotplug_status = 0;
2140 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
2141 iir = I915_READ(VLV_IIR);
2143 if (master_ctl == 0 && iir == 0)
2149 * Theory on interrupt generation, based on empirical evidence:
2151 * x = ((VLV_IIR & VLV_IER) ||
2152 * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
2153 * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
2155 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
2156 * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
2157 * guarantee the CPU interrupt will be raised again even if we
2158 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
2159 * bits this time around.
2161 I915_WRITE(GEN8_MASTER_IRQ, 0);
2162 ier = I915_READ(VLV_IER);
2163 I915_WRITE(VLV_IER, 0);
2165 gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
2167 if (iir & I915_DISPLAY_PORT_INTERRUPT)
2168 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
2170 /* Call regardless, as some status bits might not be
2171 * signalled in iir */
2172 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
2174 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
2175 I915_LPE_PIPE_B_INTERRUPT |
2176 I915_LPE_PIPE_C_INTERRUPT))
2177 intel_lpe_audio_irq_handler(dev_priv);
2180 * VLV_IIR is single buffered, and reflects the level
2181 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
2184 I915_WRITE(VLV_IIR, iir);
2186 I915_WRITE(VLV_IER, ier);
2187 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2188 POSTING_READ(GEN8_MASTER_IRQ);
2190 gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
2193 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
2195 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
2198 enable_rpm_wakeref_asserts(dev_priv);
2203 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
2204 u32 hotplug_trigger,
2205 const u32 hpd[HPD_NUM_PINS])
2207 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2210 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
2211 * unless we touch the hotplug register, even if hotplug_trigger is
2212 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
2215 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2216 if (!hotplug_trigger) {
2217 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
2218 PORTD_HOTPLUG_STATUS_MASK |
2219 PORTC_HOTPLUG_STATUS_MASK |
2220 PORTB_HOTPLUG_STATUS_MASK;
2221 dig_hotplug_reg &= ~mask;
2224 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2225 if (!hotplug_trigger)
2228 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
2229 dig_hotplug_reg, hpd,
2230 pch_port_hotplug_long_detect);
2232 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2235 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2238 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
2240 ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx);
2242 if (pch_iir & SDE_AUDIO_POWER_MASK) {
2243 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
2244 SDE_AUDIO_POWER_SHIFT);
2245 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
2249 if (pch_iir & SDE_AUX_MASK)
2250 dp_aux_irq_handler(dev_priv);
2252 if (pch_iir & SDE_GMBUS)
2253 gmbus_irq_handler(dev_priv);
2255 if (pch_iir & SDE_AUDIO_HDCP_MASK)
2256 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
2258 if (pch_iir & SDE_AUDIO_TRANS_MASK)
2259 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
2261 if (pch_iir & SDE_POISON)
2262 DRM_ERROR("PCH poison interrupt\n");
2264 if (pch_iir & SDE_FDI_MASK)
2265 for_each_pipe(dev_priv, pipe)
2266 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2268 I915_READ(FDI_RX_IIR(pipe)));
2270 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
2271 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
2273 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
2274 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
2276 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
2277 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
2279 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
2280 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
2283 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
2285 u32 err_int = I915_READ(GEN7_ERR_INT);
2288 if (err_int & ERR_INT_POISON)
2289 DRM_ERROR("Poison interrupt\n");
2291 for_each_pipe(dev_priv, pipe) {
2292 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
2293 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2295 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
2296 if (IS_IVYBRIDGE(dev_priv))
2297 ivb_pipe_crc_irq_handler(dev_priv, pipe);
2299 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2303 I915_WRITE(GEN7_ERR_INT, err_int);
2306 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
2308 u32 serr_int = I915_READ(SERR_INT);
2311 if (serr_int & SERR_INT_POISON)
2312 DRM_ERROR("PCH poison interrupt\n");
2314 for_each_pipe(dev_priv, pipe)
2315 if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe))
2316 intel_pch_fifo_underrun_irq_handler(dev_priv, pipe);
2318 I915_WRITE(SERR_INT, serr_int);
2321 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2324 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2326 ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt);
2328 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2329 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2330 SDE_AUDIO_POWER_SHIFT_CPT);
2331 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2335 if (pch_iir & SDE_AUX_MASK_CPT)
2336 dp_aux_irq_handler(dev_priv);
2338 if (pch_iir & SDE_GMBUS_CPT)
2339 gmbus_irq_handler(dev_priv);
2341 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2342 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2344 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2345 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2347 if (pch_iir & SDE_FDI_MASK_CPT)
2348 for_each_pipe(dev_priv, pipe)
2349 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2351 I915_READ(FDI_RX_IIR(pipe)));
2353 if (pch_iir & SDE_ERROR_CPT)
2354 cpt_serr_int_handler(dev_priv);
2357 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2359 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
2360 ~SDE_PORTE_HOTPLUG_SPT;
2361 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
2362 u32 pin_mask = 0, long_mask = 0;
2364 if (hotplug_trigger) {
2365 u32 dig_hotplug_reg;
2367 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2368 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2370 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2371 hotplug_trigger, dig_hotplug_reg, hpd_spt,
2372 spt_port_hotplug_long_detect);
2375 if (hotplug2_trigger) {
2376 u32 dig_hotplug_reg;
2378 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
2379 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2381 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2382 hotplug2_trigger, dig_hotplug_reg, hpd_spt,
2383 spt_port_hotplug2_long_detect);
2387 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2389 if (pch_iir & SDE_GMBUS_CPT)
2390 gmbus_irq_handler(dev_priv);
2393 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
2394 u32 hotplug_trigger,
2395 const u32 hpd[HPD_NUM_PINS])
2397 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2399 dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2400 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2402 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
2403 dig_hotplug_reg, hpd,
2404 ilk_port_hotplug_long_detect);
2406 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2409 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2413 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2415 if (hotplug_trigger)
2416 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
2418 if (de_iir & DE_AUX_CHANNEL_A)
2419 dp_aux_irq_handler(dev_priv);
2421 if (de_iir & DE_GSE)
2422 intel_opregion_asle_intr(dev_priv);
2424 if (de_iir & DE_POISON)
2425 DRM_ERROR("Poison interrupt\n");
2427 for_each_pipe(dev_priv, pipe) {
2428 if (de_iir & DE_PIPE_VBLANK(pipe))
2429 drm_handle_vblank(&dev_priv->drm, pipe);
2431 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2432 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2434 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2435 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2438 /* check event from PCH */
2439 if (de_iir & DE_PCH_EVENT) {
2440 u32 pch_iir = I915_READ(SDEIIR);
2442 if (HAS_PCH_CPT(dev_priv))
2443 cpt_irq_handler(dev_priv, pch_iir);
2445 ibx_irq_handler(dev_priv, pch_iir);
2447 /* should clear PCH hotplug event before clear CPU irq */
2448 I915_WRITE(SDEIIR, pch_iir);
2451 if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT)
2452 ironlake_rps_change_irq_handler(dev_priv);
2455 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2459 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2461 if (hotplug_trigger)
2462 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
2464 if (de_iir & DE_ERR_INT_IVB)
2465 ivb_err_int_handler(dev_priv);
2467 if (de_iir & DE_EDP_PSR_INT_HSW) {
2468 u32 psr_iir = I915_READ(EDP_PSR_IIR);
2470 intel_psr_irq_handler(dev_priv, psr_iir);
2471 I915_WRITE(EDP_PSR_IIR, psr_iir);
2474 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2475 dp_aux_irq_handler(dev_priv);
2477 if (de_iir & DE_GSE_IVB)
2478 intel_opregion_asle_intr(dev_priv);
2480 for_each_pipe(dev_priv, pipe) {
2481 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
2482 drm_handle_vblank(&dev_priv->drm, pipe);
2485 /* check event from PCH */
2486 if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2487 u32 pch_iir = I915_READ(SDEIIR);
2489 cpt_irq_handler(dev_priv, pch_iir);
2491 /* clear PCH hotplug event before clear CPU irq */
2492 I915_WRITE(SDEIIR, pch_iir);
2497 * To handle irqs with the minimum potential races with fresh interrupts, we:
2498 * 1 - Disable Master Interrupt Control.
2499 * 2 - Find the source(s) of the interrupt.
2500 * 3 - Clear the Interrupt Identity bits (IIR).
2501 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2502 * 5 - Re-enable Master Interrupt Control.
2504 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2506 struct drm_device *dev = arg;
2507 struct drm_i915_private *dev_priv = to_i915(dev);
2508 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2509 irqreturn_t ret = IRQ_NONE;
2511 if (!intel_irqs_enabled(dev_priv))
2514 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2515 disable_rpm_wakeref_asserts(dev_priv);
2517 /* disable master interrupt before clearing iir */
2518 de_ier = I915_READ(DEIER);
2519 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2520 POSTING_READ(DEIER);
2522 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2523 * interrupts will will be stored on its back queue, and then we'll be
2524 * able to process them after we restore SDEIER (as soon as we restore
2525 * it, we'll get an interrupt if SDEIIR still has something to process
2526 * due to its back queue). */
2527 if (!HAS_PCH_NOP(dev_priv)) {
2528 sde_ier = I915_READ(SDEIER);
2529 I915_WRITE(SDEIER, 0);
2530 POSTING_READ(SDEIER);
2533 /* Find, clear, then process each source of interrupt */
2535 gt_iir = I915_READ(GTIIR);
2537 I915_WRITE(GTIIR, gt_iir);
2539 if (INTEL_GEN(dev_priv) >= 6)
2540 snb_gt_irq_handler(dev_priv, gt_iir);
2542 ilk_gt_irq_handler(dev_priv, gt_iir);
2545 de_iir = I915_READ(DEIIR);
2547 I915_WRITE(DEIIR, de_iir);
2549 if (INTEL_GEN(dev_priv) >= 7)
2550 ivb_display_irq_handler(dev_priv, de_iir);
2552 ilk_display_irq_handler(dev_priv, de_iir);
2555 if (INTEL_GEN(dev_priv) >= 6) {
2556 u32 pm_iir = I915_READ(GEN6_PMIIR);
2558 I915_WRITE(GEN6_PMIIR, pm_iir);
2560 gen6_rps_irq_handler(dev_priv, pm_iir);
2564 I915_WRITE(DEIER, de_ier);
2565 POSTING_READ(DEIER);
2566 if (!HAS_PCH_NOP(dev_priv)) {
2567 I915_WRITE(SDEIER, sde_ier);
2568 POSTING_READ(SDEIER);
2571 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2572 enable_rpm_wakeref_asserts(dev_priv);
2577 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2578 u32 hotplug_trigger,
2579 const u32 hpd[HPD_NUM_PINS])
2581 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2583 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2584 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2586 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
2587 dig_hotplug_reg, hpd,
2588 bxt_port_hotplug_long_detect);
2590 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2594 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2596 irqreturn_t ret = IRQ_NONE;
2600 if (master_ctl & GEN8_DE_MISC_IRQ) {
2601 iir = I915_READ(GEN8_DE_MISC_IIR);
2605 I915_WRITE(GEN8_DE_MISC_IIR, iir);
2608 if (iir & GEN8_DE_MISC_GSE) {
2609 intel_opregion_asle_intr(dev_priv);
2613 if (iir & GEN8_DE_EDP_PSR) {
2614 u32 psr_iir = I915_READ(EDP_PSR_IIR);
2616 intel_psr_irq_handler(dev_priv, psr_iir);
2617 I915_WRITE(EDP_PSR_IIR, psr_iir);
2622 DRM_ERROR("Unexpected DE Misc interrupt\n");
2625 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2628 if (master_ctl & GEN8_DE_PORT_IRQ) {
2629 iir = I915_READ(GEN8_DE_PORT_IIR);
2634 I915_WRITE(GEN8_DE_PORT_IIR, iir);
2637 tmp_mask = GEN8_AUX_CHANNEL_A;
2638 if (INTEL_GEN(dev_priv) >= 9)
2639 tmp_mask |= GEN9_AUX_CHANNEL_B |
2640 GEN9_AUX_CHANNEL_C |
2643 if (IS_CNL_WITH_PORT_F(dev_priv))
2644 tmp_mask |= CNL_AUX_CHANNEL_F;
2646 if (iir & tmp_mask) {
2647 dp_aux_irq_handler(dev_priv);
2651 if (IS_GEN9_LP(dev_priv)) {
2652 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2654 bxt_hpd_irq_handler(dev_priv, tmp_mask,
2658 } else if (IS_BROADWELL(dev_priv)) {
2659 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2661 ilk_hpd_irq_handler(dev_priv,
2667 if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2668 gmbus_irq_handler(dev_priv);
2673 DRM_ERROR("Unexpected DE Port interrupt\n");
2676 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2679 for_each_pipe(dev_priv, pipe) {
2682 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2685 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2687 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2692 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2694 if (iir & GEN8_PIPE_VBLANK)
2695 drm_handle_vblank(&dev_priv->drm, pipe);
2697 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2698 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2700 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2701 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2704 if (INTEL_GEN(dev_priv) >= 9)
2705 fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2707 fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2710 DRM_ERROR("Fault errors on pipe %c: 0x%08x\n",
2715 if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2716 master_ctl & GEN8_DE_PCH_IRQ) {
2718 * FIXME(BDW): Assume for now that the new interrupt handling
2719 * scheme also closed the SDE interrupt handling race we've seen
2720 * on older pch-split platforms. But this needs testing.
2722 iir = I915_READ(SDEIIR);
2724 I915_WRITE(SDEIIR, iir);
2727 if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv) ||
2728 HAS_PCH_CNP(dev_priv))
2729 spt_irq_handler(dev_priv, iir);
2731 cpt_irq_handler(dev_priv, iir);
2734 * Like on previous PCH there seems to be something
2735 * fishy going on with forwarding PCH interrupts.
2737 DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2744 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2746 struct drm_i915_private *dev_priv = to_i915(arg);
2750 if (!intel_irqs_enabled(dev_priv))
2753 master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2754 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2758 I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2760 /* Find, clear, then process each source of interrupt */
2761 gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
2763 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2764 if (master_ctl & ~GEN8_GT_IRQS) {
2765 disable_rpm_wakeref_asserts(dev_priv);
2766 gen8_de_irq_handler(dev_priv, master_ctl);
2767 enable_rpm_wakeref_asserts(dev_priv);
2770 I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2772 gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
2778 struct delayed_work work;
2779 struct drm_i915_private *i915;
2783 static void wedge_me(struct work_struct *work)
2785 struct wedge_me *w = container_of(work, typeof(*w), work.work);
2787 dev_err(w->i915->drm.dev,
2788 "%s timed out, cancelling all in-flight rendering.\n",
2790 i915_gem_set_wedged(w->i915);
2793 static void __init_wedge(struct wedge_me *w,
2794 struct drm_i915_private *i915,
2801 INIT_DELAYED_WORK_ONSTACK(&w->work, wedge_me);
2802 schedule_delayed_work(&w->work, timeout);
2805 static void __fini_wedge(struct wedge_me *w)
2807 cancel_delayed_work_sync(&w->work);
2808 destroy_delayed_work_on_stack(&w->work);
2812 #define i915_wedge_on_timeout(W, DEV, TIMEOUT) \
2813 for (__init_wedge((W), (DEV), (TIMEOUT), __func__); \
2818 gen11_gt_engine_identity(struct drm_i915_private * const i915,
2819 const unsigned int bank, const unsigned int bit)
2821 void __iomem * const regs = i915->regs;
2825 lockdep_assert_held(&i915->irq_lock);
2827 raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit));
2830 * NB: Specs do not specify how long to spin wait,
2831 * so we do ~100us as an educated guess.
2833 timeout_ts = (local_clock() >> 10) + 100;
2835 ident = raw_reg_read(regs, GEN11_INTR_IDENTITY_REG(bank));
2836 } while (!(ident & GEN11_INTR_DATA_VALID) &&
2837 !time_after32(local_clock() >> 10, timeout_ts));
2839 if (unlikely(!(ident & GEN11_INTR_DATA_VALID))) {
2840 DRM_ERROR("INTR_IDENTITY_REG%u:%u 0x%08x not valid!\n",
2845 raw_reg_write(regs, GEN11_INTR_IDENTITY_REG(bank),
2846 GEN11_INTR_DATA_VALID);
2852 gen11_other_irq_handler(struct drm_i915_private * const i915,
2853 const u8 instance, const u16 iir)
2855 if (instance == OTHER_GTPM_INSTANCE)
2856 return gen6_rps_irq_handler(i915, iir);
2858 WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
2863 gen11_engine_irq_handler(struct drm_i915_private * const i915,
2864 const u8 class, const u8 instance, const u16 iir)
2866 struct intel_engine_cs *engine;
2868 if (instance <= MAX_ENGINE_INSTANCE)
2869 engine = i915->engine_class[class][instance];
2874 return gen8_cs_irq_handler(engine, iir);
2876 WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n",
2881 gen11_gt_identity_handler(struct drm_i915_private * const i915,
2884 const u8 class = GEN11_INTR_ENGINE_CLASS(identity);
2885 const u8 instance = GEN11_INTR_ENGINE_INSTANCE(identity);
2886 const u16 intr = GEN11_INTR_ENGINE_INTR(identity);
2888 if (unlikely(!intr))
2891 if (class <= COPY_ENGINE_CLASS)
2892 return gen11_engine_irq_handler(i915, class, instance, intr);
2894 if (class == OTHER_CLASS)
2895 return gen11_other_irq_handler(i915, instance, intr);
2897 WARN_ONCE(1, "unknown interrupt class=0x%x, instance=0x%x, intr=0x%x\n",
2898 class, instance, intr);
2902 gen11_gt_bank_handler(struct drm_i915_private * const i915,
2903 const unsigned int bank)
2905 void __iomem * const regs = i915->regs;
2906 unsigned long intr_dw;
2909 lockdep_assert_held(&i915->irq_lock);
2911 intr_dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
2913 if (unlikely(!intr_dw)) {
2914 DRM_ERROR("GT_INTR_DW%u blank!\n", bank);
2918 for_each_set_bit(bit, &intr_dw, 32) {
2919 const u32 ident = gen11_gt_engine_identity(i915,
2922 gen11_gt_identity_handler(i915, ident);
2925 /* Clear must be after shared has been served for engine */
2926 raw_reg_write(regs, GEN11_GT_INTR_DW(bank), intr_dw);
2930 gen11_gt_irq_handler(struct drm_i915_private * const i915,
2931 const u32 master_ctl)
2935 spin_lock(&i915->irq_lock);
2937 for (bank = 0; bank < 2; bank++) {
2938 if (master_ctl & GEN11_GT_DW_IRQ(bank))
2939 gen11_gt_bank_handler(i915, bank);
2942 spin_unlock(&i915->irq_lock);
2945 static irqreturn_t gen11_irq_handler(int irq, void *arg)
2947 struct drm_i915_private * const i915 = to_i915(arg);
2948 void __iomem * const regs = i915->regs;
2951 if (!intel_irqs_enabled(i915))
2954 master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
2955 master_ctl &= ~GEN11_MASTER_IRQ;
2959 /* Disable interrupts. */
2960 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0);
2962 /* Find, clear, then process each source of interrupt. */
2963 gen11_gt_irq_handler(i915, master_ctl);
2965 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2966 if (master_ctl & GEN11_DISPLAY_IRQ) {
2967 const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
2969 disable_rpm_wakeref_asserts(i915);
2971 * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
2972 * for the display related bits.
2974 gen8_de_irq_handler(i915, disp_ctl);
2975 enable_rpm_wakeref_asserts(i915);
2978 /* Acknowledge and enable interrupts. */
2979 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ | master_ctl);
2984 static void i915_reset_device(struct drm_i915_private *dev_priv,
2988 struct i915_gpu_error *error = &dev_priv->gpu_error;
2989 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
2990 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2991 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2992 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2995 kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
2997 DRM_DEBUG_DRIVER("resetting chip\n");
2998 kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
3000 /* Use a watchdog to ensure that our reset completes */
3001 i915_wedge_on_timeout(&w, dev_priv, 5*HZ) {
3002 intel_prepare_reset(dev_priv);
3004 error->reason = reason;
3005 error->stalled_mask = engine_mask;
3007 /* Signal that locked waiters should reset the GPU */
3008 smp_mb__before_atomic();
3009 set_bit(I915_RESET_HANDOFF, &error->flags);
3010 wake_up_all(&error->wait_queue);
3012 /* Wait for anyone holding the lock to wakeup, without
3013 * blocking indefinitely on struct_mutex.
3016 if (mutex_trylock(&dev_priv->drm.struct_mutex)) {
3017 i915_reset(dev_priv, engine_mask, reason);
3018 mutex_unlock(&dev_priv->drm.struct_mutex);
3020 } while (wait_on_bit_timeout(&error->flags,
3022 TASK_UNINTERRUPTIBLE,
3025 error->stalled_mask = 0;
3026 error->reason = NULL;
3028 intel_finish_reset(dev_priv);
3031 if (!test_bit(I915_WEDGED, &error->flags))
3032 kobject_uevent_env(kobj, KOBJ_CHANGE, reset_done_event);
3035 static void i915_clear_error_registers(struct drm_i915_private *dev_priv)
3039 if (!IS_GEN2(dev_priv))
3040 I915_WRITE(PGTBL_ER, I915_READ(PGTBL_ER));
3042 if (INTEL_GEN(dev_priv) < 4)
3043 I915_WRITE(IPEIR, I915_READ(IPEIR));
3045 I915_WRITE(IPEIR_I965, I915_READ(IPEIR_I965));
3047 I915_WRITE(EIR, I915_READ(EIR));
3048 eir = I915_READ(EIR);
3051 * some errors might have become stuck,
3054 DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
3055 I915_WRITE(EMR, I915_READ(EMR) | eir);
3056 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3061 * i915_handle_error - handle a gpu error
3062 * @dev_priv: i915 device private
3063 * @engine_mask: mask representing engines that are hung
3064 * @flags: control flags
3065 * @fmt: Error message format string
3067 * Do some basic checking of register state at error time and
3068 * dump it to the syslog. Also call i915_capture_error_state() to make
3069 * sure we get a record and make it available in debugfs. Fire a uevent
3070 * so userspace knows something bad happened (should trigger collection
3071 * of a ring dump etc.).
3073 void i915_handle_error(struct drm_i915_private *dev_priv,
3075 unsigned long flags,
3076 const char *fmt, ...)
3078 struct intel_engine_cs *engine;
3086 va_start(args, fmt);
3087 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
3094 * In most cases it's guaranteed that we get here with an RPM
3095 * reference held, for example because there is a pending GPU
3096 * request that won't finish until the reset is done. This
3097 * isn't the case at least when we get here by doing a
3098 * simulated reset via debugfs, so get an RPM reference.
3100 intel_runtime_pm_get(dev_priv);
3102 engine_mask &= INTEL_INFO(dev_priv)->ring_mask;
3104 if (flags & I915_ERROR_CAPTURE) {
3105 i915_capture_error_state(dev_priv, engine_mask, msg);
3106 i915_clear_error_registers(dev_priv);
3110 * Try engine reset when available. We fall back to full reset if
3111 * single reset fails.
3113 if (intel_has_reset_engine(dev_priv)) {
3114 for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
3115 BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);
3116 if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
3117 &dev_priv->gpu_error.flags))
3120 if (i915_reset_engine(engine, msg) == 0)
3121 engine_mask &= ~intel_engine_flag(engine);
3123 clear_bit(I915_RESET_ENGINE + engine->id,
3124 &dev_priv->gpu_error.flags);
3125 wake_up_bit(&dev_priv->gpu_error.flags,
3126 I915_RESET_ENGINE + engine->id);
3133 /* Full reset needs the mutex, stop any other user trying to do so. */
3134 if (test_and_set_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags)) {
3135 wait_event(dev_priv->gpu_error.reset_queue,
3136 !test_bit(I915_RESET_BACKOFF,
3137 &dev_priv->gpu_error.flags));
3141 /* Prevent any other reset-engine attempt. */
3142 for_each_engine(engine, dev_priv, tmp) {
3143 while (test_and_set_bit(I915_RESET_ENGINE + engine->id,
3144 &dev_priv->gpu_error.flags))
3145 wait_on_bit(&dev_priv->gpu_error.flags,
3146 I915_RESET_ENGINE + engine->id,
3147 TASK_UNINTERRUPTIBLE);
3150 i915_reset_device(dev_priv, engine_mask, msg);
3152 for_each_engine(engine, dev_priv, tmp) {
3153 clear_bit(I915_RESET_ENGINE + engine->id,
3154 &dev_priv->gpu_error.flags);
3157 clear_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags);
3158 wake_up_all(&dev_priv->gpu_error.reset_queue);
3161 intel_runtime_pm_put(dev_priv);
3164 /* Called from drm generic code, passed 'crtc' which
3165 * we use as a pipe index
3167 static int i8xx_enable_vblank(struct drm_device *dev, unsigned int pipe)
3169 struct drm_i915_private *dev_priv = to_i915(dev);
3170 unsigned long irqflags;
3172 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3173 i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
3174 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3179 static int i965_enable_vblank(struct drm_device *dev, unsigned int pipe)
3181 struct drm_i915_private *dev_priv = to_i915(dev);
3182 unsigned long irqflags;
3184 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3185 i915_enable_pipestat(dev_priv, pipe,
3186 PIPE_START_VBLANK_INTERRUPT_STATUS);
3187 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3192 static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
3194 struct drm_i915_private *dev_priv = to_i915(dev);
3195 unsigned long irqflags;
3196 uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
3197 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
3199 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3200 ilk_enable_display_irq(dev_priv, bit);
3201 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3203 /* Even though there is no DMC, frame counter can get stuck when
3204 * PSR is active as no frames are generated.
3206 if (HAS_PSR(dev_priv))
3207 drm_vblank_restore(dev, pipe);
3212 static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
3214 struct drm_i915_private *dev_priv = to_i915(dev);
3215 unsigned long irqflags;
3217 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3218 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
3219 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3221 /* Even if there is no DMC, frame counter can get stuck when
3222 * PSR is active as no frames are generated, so check only for PSR.
3224 if (HAS_PSR(dev_priv))
3225 drm_vblank_restore(dev, pipe);
3230 /* Called from drm generic code, passed 'crtc' which
3231 * we use as a pipe index
3233 static void i8xx_disable_vblank(struct drm_device *dev, unsigned int pipe)
3235 struct drm_i915_private *dev_priv = to_i915(dev);
3236 unsigned long irqflags;
3238 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3239 i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
3240 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3243 static void i965_disable_vblank(struct drm_device *dev, unsigned int pipe)
3245 struct drm_i915_private *dev_priv = to_i915(dev);
3246 unsigned long irqflags;
3248 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3249 i915_disable_pipestat(dev_priv, pipe,
3250 PIPE_START_VBLANK_INTERRUPT_STATUS);
3251 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3254 static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
3256 struct drm_i915_private *dev_priv = to_i915(dev);
3257 unsigned long irqflags;
3258 uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
3259 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
3261 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3262 ilk_disable_display_irq(dev_priv, bit);
3263 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3266 static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
3268 struct drm_i915_private *dev_priv = to_i915(dev);
3269 unsigned long irqflags;
3271 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3272 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
3273 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3276 static void ibx_irq_reset(struct drm_i915_private *dev_priv)
3278 if (HAS_PCH_NOP(dev_priv))
3281 GEN3_IRQ_RESET(SDE);
3283 if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
3284 I915_WRITE(SERR_INT, 0xffffffff);
3288 * SDEIER is also touched by the interrupt handler to work around missed PCH
3289 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3290 * instead we unconditionally enable all PCH interrupt sources here, but then
3291 * only unmask them as needed with SDEIMR.
3293 * This function needs to be called before interrupts are enabled.
3295 static void ibx_irq_pre_postinstall(struct drm_device *dev)
3297 struct drm_i915_private *dev_priv = to_i915(dev);
3299 if (HAS_PCH_NOP(dev_priv))
3302 WARN_ON(I915_READ(SDEIER) != 0);
3303 I915_WRITE(SDEIER, 0xffffffff);
3304 POSTING_READ(SDEIER);
3307 static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv)
3310 if (INTEL_GEN(dev_priv) >= 6)
3311 GEN3_IRQ_RESET(GEN6_PM);
3314 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3316 if (IS_CHERRYVIEW(dev_priv))
3317 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3319 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3321 i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
3322 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3324 i9xx_pipestat_irq_reset(dev_priv);
3326 GEN3_IRQ_RESET(VLV_);
3327 dev_priv->irq_mask = ~0u;
3330 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3336 pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS;
3338 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3339 for_each_pipe(dev_priv, pipe)
3340 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3342 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
3343 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3344 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3345 I915_LPE_PIPE_A_INTERRUPT |
3346 I915_LPE_PIPE_B_INTERRUPT;
3348 if (IS_CHERRYVIEW(dev_priv))
3349 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT |
3350 I915_LPE_PIPE_C_INTERRUPT;
3352 WARN_ON(dev_priv->irq_mask != ~0u);
3354 dev_priv->irq_mask = ~enable_mask;
3356 GEN3_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
3361 static void ironlake_irq_reset(struct drm_device *dev)
3363 struct drm_i915_private *dev_priv = to_i915(dev);
3365 if (IS_GEN5(dev_priv))
3366 I915_WRITE(HWSTAM, 0xffffffff);
3369 if (IS_GEN7(dev_priv))
3370 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3372 if (IS_HASWELL(dev_priv)) {
3373 I915_WRITE(EDP_PSR_IMR, 0xffffffff);
3374 I915_WRITE(EDP_PSR_IIR, 0xffffffff);
3377 gen5_gt_irq_reset(dev_priv);
3379 ibx_irq_reset(dev_priv);
3382 static void valleyview_irq_reset(struct drm_device *dev)
3384 struct drm_i915_private *dev_priv = to_i915(dev);
3386 I915_WRITE(VLV_MASTER_IER, 0);
3387 POSTING_READ(VLV_MASTER_IER);
3389 gen5_gt_irq_reset(dev_priv);
3391 spin_lock_irq(&dev_priv->irq_lock);
3392 if (dev_priv->display_irqs_enabled)
3393 vlv_display_irq_reset(dev_priv);
3394 spin_unlock_irq(&dev_priv->irq_lock);
3397 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3399 GEN8_IRQ_RESET_NDX(GT, 0);
3400 GEN8_IRQ_RESET_NDX(GT, 1);
3401 GEN8_IRQ_RESET_NDX(GT, 2);
3402 GEN8_IRQ_RESET_NDX(GT, 3);
3405 static void gen8_irq_reset(struct drm_device *dev)
3407 struct drm_i915_private *dev_priv = to_i915(dev);
3410 I915_WRITE(GEN8_MASTER_IRQ, 0);
3411 POSTING_READ(GEN8_MASTER_IRQ);
3413 gen8_gt_irq_reset(dev_priv);
3415 I915_WRITE(EDP_PSR_IMR, 0xffffffff);
3416 I915_WRITE(EDP_PSR_IIR, 0xffffffff);
3418 for_each_pipe(dev_priv, pipe)
3419 if (intel_display_power_is_enabled(dev_priv,
3420 POWER_DOMAIN_PIPE(pipe)))
3421 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3423 GEN3_IRQ_RESET(GEN8_DE_PORT_);
3424 GEN3_IRQ_RESET(GEN8_DE_MISC_);
3425 GEN3_IRQ_RESET(GEN8_PCU_);
3427 if (HAS_PCH_SPLIT(dev_priv))
3428 ibx_irq_reset(dev_priv);
3431 static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv)
3433 /* Disable RCS, BCS, VCS and VECS class engines. */
3434 I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, 0);
3435 I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE, 0);
3437 /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
3438 I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK, ~0);
3439 I915_WRITE(GEN11_BCS_RSVD_INTR_MASK, ~0);
3440 I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK, ~0);
3441 I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK, ~0);
3442 I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK, ~0);
3444 I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
3445 I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
3448 static void gen11_irq_reset(struct drm_device *dev)
3450 struct drm_i915_private *dev_priv = dev->dev_private;
3453 I915_WRITE(GEN11_GFX_MSTR_IRQ, 0);
3454 POSTING_READ(GEN11_GFX_MSTR_IRQ);
3456 gen11_gt_irq_reset(dev_priv);
3458 I915_WRITE(GEN11_DISPLAY_INT_CTL, 0);
3460 for_each_pipe(dev_priv, pipe)
3461 if (intel_display_power_is_enabled(dev_priv,
3462 POWER_DOMAIN_PIPE(pipe)))
3463 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3465 GEN3_IRQ_RESET(GEN8_DE_PORT_);
3466 GEN3_IRQ_RESET(GEN8_DE_MISC_);
3467 GEN3_IRQ_RESET(GEN8_PCU_);
3470 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3473 uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3476 spin_lock_irq(&dev_priv->irq_lock);
3478 if (!intel_irqs_enabled(dev_priv)) {
3479 spin_unlock_irq(&dev_priv->irq_lock);
3483 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3484 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3485 dev_priv->de_irq_mask[pipe],
3486 ~dev_priv->de_irq_mask[pipe] | extra_ier);
3488 spin_unlock_irq(&dev_priv->irq_lock);
3491 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3496 spin_lock_irq(&dev_priv->irq_lock);
3498 if (!intel_irqs_enabled(dev_priv)) {
3499 spin_unlock_irq(&dev_priv->irq_lock);
3503 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3504 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3506 spin_unlock_irq(&dev_priv->irq_lock);
3508 /* make sure we're done processing display irqs */
3509 synchronize_irq(dev_priv->drm.irq);
3512 static void cherryview_irq_reset(struct drm_device *dev)
3514 struct drm_i915_private *dev_priv = to_i915(dev);
3516 I915_WRITE(GEN8_MASTER_IRQ, 0);
3517 POSTING_READ(GEN8_MASTER_IRQ);
3519 gen8_gt_irq_reset(dev_priv);
3521 GEN3_IRQ_RESET(GEN8_PCU_);
3523 spin_lock_irq(&dev_priv->irq_lock);
3524 if (dev_priv->display_irqs_enabled)
3525 vlv_display_irq_reset(dev_priv);
3526 spin_unlock_irq(&dev_priv->irq_lock);
3529 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
3530 const u32 hpd[HPD_NUM_PINS])
3532 struct intel_encoder *encoder;
3533 u32 enabled_irqs = 0;
3535 for_each_intel_encoder(&dev_priv->drm, encoder)
3536 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3537 enabled_irqs |= hpd[encoder->hpd_pin];
3539 return enabled_irqs;
3542 static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
3547 * Enable digital hotplug on the PCH, and configure the DP short pulse
3548 * duration to 2ms (which is the minimum in the Display Port spec).
3549 * The pulse duration bits are reserved on LPT+.
3551 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3552 hotplug &= ~(PORTB_PULSE_DURATION_MASK |
3553 PORTC_PULSE_DURATION_MASK |
3554 PORTD_PULSE_DURATION_MASK);
3555 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3556 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3557 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3559 * When CPU and PCH are on the same package, port A
3560 * HPD must be enabled in both north and south.
3562 if (HAS_PCH_LPT_LP(dev_priv))
3563 hotplug |= PORTA_HOTPLUG_ENABLE;
3564 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3567 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3569 u32 hotplug_irqs, enabled_irqs;
3571 if (HAS_PCH_IBX(dev_priv)) {
3572 hotplug_irqs = SDE_HOTPLUG_MASK;
3573 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx);
3575 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3576 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt);
3579 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3581 ibx_hpd_detection_setup(dev_priv);
3584 static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3588 /* Display WA #1179 WaHardHangonHotPlug: cnp */
3589 if (HAS_PCH_CNP(dev_priv)) {
3590 val = I915_READ(SOUTH_CHICKEN1);
3591 val &= ~CHASSIS_CLK_REQ_DURATION_MASK;
3592 val |= CHASSIS_CLK_REQ_DURATION(0xf);
3593 I915_WRITE(SOUTH_CHICKEN1, val);
3596 /* Enable digital hotplug on the PCH */
3597 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3598 hotplug |= PORTA_HOTPLUG_ENABLE |
3599 PORTB_HOTPLUG_ENABLE |
3600 PORTC_HOTPLUG_ENABLE |
3601 PORTD_HOTPLUG_ENABLE;
3602 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3604 hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3605 hotplug |= PORTE_HOTPLUG_ENABLE;
3606 I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3609 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3611 u32 hotplug_irqs, enabled_irqs;
3613 hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3614 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt);
3616 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3618 spt_hpd_detection_setup(dev_priv);
3621 static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
3626 * Enable digital hotplug on the CPU, and configure the DP short pulse
3627 * duration to 2ms (which is the minimum in the Display Port spec)
3628 * The pulse duration bits are reserved on HSW+.
3630 hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3631 hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3632 hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE |
3633 DIGITAL_PORTA_PULSE_DURATION_2ms;
3634 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3637 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3639 u32 hotplug_irqs, enabled_irqs;
3641 if (INTEL_GEN(dev_priv) >= 8) {
3642 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3643 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
3645 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3646 } else if (INTEL_GEN(dev_priv) >= 7) {
3647 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3648 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
3650 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3652 hotplug_irqs = DE_DP_A_HOTPLUG;
3653 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk);
3655 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3658 ilk_hpd_detection_setup(dev_priv);
3660 ibx_hpd_irq_setup(dev_priv);
3663 static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
3668 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3669 hotplug |= PORTA_HOTPLUG_ENABLE |
3670 PORTB_HOTPLUG_ENABLE |
3671 PORTC_HOTPLUG_ENABLE;
3673 DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3674 hotplug, enabled_irqs);
3675 hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
3678 * For BXT invert bit has to be set based on AOB design
3679 * for HPD detection logic, update it based on VBT fields.
3681 if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
3682 intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
3683 hotplug |= BXT_DDIA_HPD_INVERT;
3684 if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
3685 intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
3686 hotplug |= BXT_DDIB_HPD_INVERT;
3687 if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
3688 intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
3689 hotplug |= BXT_DDIC_HPD_INVERT;
3691 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3694 static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3696 __bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK);
3699 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3701 u32 hotplug_irqs, enabled_irqs;
3703 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt);
3704 hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3706 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3708 __bxt_hpd_detection_setup(dev_priv, enabled_irqs);
3711 static void ibx_irq_postinstall(struct drm_device *dev)
3713 struct drm_i915_private *dev_priv = to_i915(dev);
3716 if (HAS_PCH_NOP(dev_priv))
3719 if (HAS_PCH_IBX(dev_priv))
3720 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3721 else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
3722 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3724 mask = SDE_GMBUS_CPT;
3726 gen3_assert_iir_is_zero(dev_priv, SDEIIR);
3727 I915_WRITE(SDEIMR, ~mask);
3729 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
3730 HAS_PCH_LPT(dev_priv))
3731 ibx_hpd_detection_setup(dev_priv);
3733 spt_hpd_detection_setup(dev_priv);
3736 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3738 struct drm_i915_private *dev_priv = to_i915(dev);
3739 u32 pm_irqs, gt_irqs;
3741 pm_irqs = gt_irqs = 0;
3743 dev_priv->gt_irq_mask = ~0;
3744 if (HAS_L3_DPF(dev_priv)) {
3745 /* L3 parity interrupt is always unmasked. */
3746 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev_priv);
3747 gt_irqs |= GT_PARITY_ERROR(dev_priv);
3750 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3751 if (IS_GEN5(dev_priv)) {
3752 gt_irqs |= ILK_BSD_USER_INTERRUPT;
3754 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3757 GEN3_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3759 if (INTEL_GEN(dev_priv) >= 6) {
3761 * RPS interrupts will get enabled/disabled on demand when RPS
3762 * itself is enabled/disabled.
3764 if (HAS_VEBOX(dev_priv)) {
3765 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3766 dev_priv->pm_ier |= PM_VEBOX_USER_INTERRUPT;
3769 dev_priv->pm_imr = 0xffffffff;
3770 GEN3_IRQ_INIT(GEN6_PM, dev_priv->pm_imr, pm_irqs);
3774 static int ironlake_irq_postinstall(struct drm_device *dev)
3776 struct drm_i915_private *dev_priv = to_i915(dev);
3777 u32 display_mask, extra_mask;
3779 if (INTEL_GEN(dev_priv) >= 7) {
3780 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3781 DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB);
3782 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3783 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3784 DE_DP_A_HOTPLUG_IVB);
3786 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3787 DE_AUX_CHANNEL_A | DE_PIPEB_CRC_DONE |
3788 DE_PIPEA_CRC_DONE | DE_POISON);
3789 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3790 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3794 if (IS_HASWELL(dev_priv)) {
3795 gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR);
3796 intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
3797 display_mask |= DE_EDP_PSR_INT_HSW;
3800 dev_priv->irq_mask = ~display_mask;
3802 ibx_irq_pre_postinstall(dev);
3804 GEN3_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3806 gen5_gt_irq_postinstall(dev);
3808 ilk_hpd_detection_setup(dev_priv);
3810 ibx_irq_postinstall(dev);
3812 if (IS_IRONLAKE_M(dev_priv)) {
3813 /* Enable PCU event interrupts
3815 * spinlocking not required here for correctness since interrupt
3816 * setup is guaranteed to run in single-threaded context. But we
3817 * need it to make the assert_spin_locked happy. */
3818 spin_lock_irq(&dev_priv->irq_lock);
3819 ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
3820 spin_unlock_irq(&dev_priv->irq_lock);
3826 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3828 lockdep_assert_held(&dev_priv->irq_lock);
3830 if (dev_priv->display_irqs_enabled)
3833 dev_priv->display_irqs_enabled = true;
3835 if (intel_irqs_enabled(dev_priv)) {
3836 vlv_display_irq_reset(dev_priv);
3837 vlv_display_irq_postinstall(dev_priv);
3841 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3843 lockdep_assert_held(&dev_priv->irq_lock);
3845 if (!dev_priv->display_irqs_enabled)
3848 dev_priv->display_irqs_enabled = false;
3850 if (intel_irqs_enabled(dev_priv))
3851 vlv_display_irq_reset(dev_priv);
3855 static int valleyview_irq_postinstall(struct drm_device *dev)
3857 struct drm_i915_private *dev_priv = to_i915(dev);
3859 gen5_gt_irq_postinstall(dev);
3861 spin_lock_irq(&dev_priv->irq_lock);
3862 if (dev_priv->display_irqs_enabled)
3863 vlv_display_irq_postinstall(dev_priv);
3864 spin_unlock_irq(&dev_priv->irq_lock);
3866 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3867 POSTING_READ(VLV_MASTER_IER);
3872 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3874 /* These are interrupts we'll toggle with the ring mask register */
3875 uint32_t gt_interrupts[] = {
3876 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3877 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3878 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3879 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3880 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3881 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3882 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3883 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3885 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3886 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3889 if (HAS_L3_DPF(dev_priv))
3890 gt_interrupts[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
3892 dev_priv->pm_ier = 0x0;
3893 dev_priv->pm_imr = ~dev_priv->pm_ier;
3894 GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3895 GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3897 * RPS interrupts will get enabled/disabled on demand when RPS itself
3898 * is enabled/disabled. Same wil be the case for GuC interrupts.
3900 GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_imr, dev_priv->pm_ier);
3901 GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3904 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3906 uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3907 uint32_t de_pipe_enables;
3908 u32 de_port_masked = GEN8_AUX_CHANNEL_A;
3909 u32 de_port_enables;
3910 u32 de_misc_masked = GEN8_DE_MISC_GSE | GEN8_DE_EDP_PSR;
3913 if (INTEL_GEN(dev_priv) >= 9) {
3914 de_pipe_masked |= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3915 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3917 if (IS_GEN9_LP(dev_priv))
3918 de_port_masked |= BXT_DE_PORT_GMBUS;
3920 de_pipe_masked |= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3923 if (IS_CNL_WITH_PORT_F(dev_priv))
3924 de_port_masked |= CNL_AUX_CHANNEL_F;
3926 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3927 GEN8_PIPE_FIFO_UNDERRUN;
3929 de_port_enables = de_port_masked;
3930 if (IS_GEN9_LP(dev_priv))
3931 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3932 else if (IS_BROADWELL(dev_priv))
3933 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
3935 gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR);
3936 intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
3938 for_each_pipe(dev_priv, pipe) {
3939 dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;
3941 if (intel_display_power_is_enabled(dev_priv,
3942 POWER_DOMAIN_PIPE(pipe)))
3943 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3944 dev_priv->de_irq_mask[pipe],
3948 GEN3_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3949 GEN3_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
3951 if (IS_GEN9_LP(dev_priv))
3952 bxt_hpd_detection_setup(dev_priv);
3953 else if (IS_BROADWELL(dev_priv))
3954 ilk_hpd_detection_setup(dev_priv);
3957 static int gen8_irq_postinstall(struct drm_device *dev)
3959 struct drm_i915_private *dev_priv = to_i915(dev);
3961 if (HAS_PCH_SPLIT(dev_priv))
3962 ibx_irq_pre_postinstall(dev);
3964 gen8_gt_irq_postinstall(dev_priv);
3965 gen8_de_irq_postinstall(dev_priv);
3967 if (HAS_PCH_SPLIT(dev_priv))
3968 ibx_irq_postinstall(dev);
3970 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3971 POSTING_READ(GEN8_MASTER_IRQ);
3976 static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3978 const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT;
3980 BUILD_BUG_ON(irqs & 0xffff0000);
3982 /* Enable RCS, BCS, VCS and VECS class interrupts. */
3983 I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, irqs << 16 | irqs);
3984 I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE, irqs << 16 | irqs);
3986 /* Unmask irqs on RCS, BCS, VCS and VECS engines. */
3987 I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK, ~(irqs << 16));
3988 I915_WRITE(GEN11_BCS_RSVD_INTR_MASK, ~(irqs << 16));
3989 I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK, ~(irqs | irqs << 16));
3990 I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK, ~(irqs | irqs << 16));
3991 I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK, ~(irqs | irqs << 16));
3994 * RPS interrupts will get enabled/disabled on demand when RPS itself
3995 * is enabled/disabled.
3997 dev_priv->pm_ier = 0x0;
3998 dev_priv->pm_imr = ~dev_priv->pm_ier;
3999 I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
4000 I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
4003 static int gen11_irq_postinstall(struct drm_device *dev)
4005 struct drm_i915_private *dev_priv = dev->dev_private;
4007 gen11_gt_irq_postinstall(dev_priv);
4008 gen8_de_irq_postinstall(dev_priv);
4010 I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
4012 I915_WRITE(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
4013 POSTING_READ(GEN11_GFX_MSTR_IRQ);
4018 static int cherryview_irq_postinstall(struct drm_device *dev)
4020 struct drm_i915_private *dev_priv = to_i915(dev);
4022 gen8_gt_irq_postinstall(dev_priv);
4024 spin_lock_irq(&dev_priv->irq_lock);
4025 if (dev_priv->display_irqs_enabled)
4026 vlv_display_irq_postinstall(dev_priv);
4027 spin_unlock_irq(&dev_priv->irq_lock);
4029 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
4030 POSTING_READ(GEN8_MASTER_IRQ);
4035 static void i8xx_irq_reset(struct drm_device *dev)
4037 struct drm_i915_private *dev_priv = to_i915(dev);
4039 i9xx_pipestat_irq_reset(dev_priv);
4041 I915_WRITE16(HWSTAM, 0xffff);
4046 static int i8xx_irq_postinstall(struct drm_device *dev)
4048 struct drm_i915_private *dev_priv = to_i915(dev);
4051 I915_WRITE16(EMR, ~(I915_ERROR_PAGE_TABLE |
4052 I915_ERROR_MEMORY_REFRESH));
4054 /* Unmask the interrupts that we always want on. */
4055 dev_priv->irq_mask =
4056 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4057 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT);
4060 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4061 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4062 I915_USER_INTERRUPT;
4064 GEN2_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
4066 /* Interrupt setup is already guaranteed to be single-threaded, this is
4067 * just to make the assert_spin_locked check happy. */
4068 spin_lock_irq(&dev_priv->irq_lock);
4069 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4070 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4071 spin_unlock_irq(&dev_priv->irq_lock);
4076 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
4078 struct drm_device *dev = arg;
4079 struct drm_i915_private *dev_priv = to_i915(dev);
4080 irqreturn_t ret = IRQ_NONE;
4082 if (!intel_irqs_enabled(dev_priv))
4085 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4086 disable_rpm_wakeref_asserts(dev_priv);
4089 u32 pipe_stats[I915_MAX_PIPES] = {};
4092 iir = I915_READ16(IIR);
4098 /* Call regardless, as some status bits might not be
4099 * signalled in iir */
4100 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
4102 I915_WRITE16(IIR, iir);
4104 if (iir & I915_USER_INTERRUPT)
4105 notify_ring(dev_priv->engine[RCS]);
4107 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4108 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4110 i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats);
4113 enable_rpm_wakeref_asserts(dev_priv);
4118 static void i915_irq_reset(struct drm_device *dev)
4120 struct drm_i915_private *dev_priv = to_i915(dev);
4122 if (I915_HAS_HOTPLUG(dev_priv)) {
4123 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4124 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4127 i9xx_pipestat_irq_reset(dev_priv);
4129 I915_WRITE(HWSTAM, 0xffffffff);
4134 static int i915_irq_postinstall(struct drm_device *dev)
4136 struct drm_i915_private *dev_priv = to_i915(dev);
4139 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE |
4140 I915_ERROR_MEMORY_REFRESH));
4142 /* Unmask the interrupts that we always want on. */
4143 dev_priv->irq_mask =
4144 ~(I915_ASLE_INTERRUPT |
4145 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4146 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT);
4149 I915_ASLE_INTERRUPT |
4150 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4151 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4152 I915_USER_INTERRUPT;
4154 if (I915_HAS_HOTPLUG(dev_priv)) {
4155 /* Enable in IER... */
4156 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
4157 /* and unmask in IMR */
4158 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
4161 GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
4163 /* Interrupt setup is already guaranteed to be single-threaded, this is
4164 * just to make the assert_spin_locked check happy. */
4165 spin_lock_irq(&dev_priv->irq_lock);
4166 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4167 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4168 spin_unlock_irq(&dev_priv->irq_lock);
4170 i915_enable_asle_pipestat(dev_priv);
4175 static irqreturn_t i915_irq_handler(int irq, void *arg)
4177 struct drm_device *dev = arg;
4178 struct drm_i915_private *dev_priv = to_i915(dev);
4179 irqreturn_t ret = IRQ_NONE;
4181 if (!intel_irqs_enabled(dev_priv))
4184 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4185 disable_rpm_wakeref_asserts(dev_priv);
4188 u32 pipe_stats[I915_MAX_PIPES] = {};
4189 u32 hotplug_status = 0;
4192 iir = I915_READ(IIR);
4198 if (I915_HAS_HOTPLUG(dev_priv) &&
4199 iir & I915_DISPLAY_PORT_INTERRUPT)
4200 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4202 /* Call regardless, as some status bits might not be
4203 * signalled in iir */
4204 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
4206 I915_WRITE(IIR, iir);
4208 if (iir & I915_USER_INTERRUPT)
4209 notify_ring(dev_priv->engine[RCS]);
4211 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4212 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4215 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4217 i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);
4220 enable_rpm_wakeref_asserts(dev_priv);
4225 static void i965_irq_reset(struct drm_device *dev)
4227 struct drm_i915_private *dev_priv = to_i915(dev);
4229 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4230 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4232 i9xx_pipestat_irq_reset(dev_priv);
4234 I915_WRITE(HWSTAM, 0xffffffff);
4239 static int i965_irq_postinstall(struct drm_device *dev)
4241 struct drm_i915_private *dev_priv = to_i915(dev);
4246 * Enable some error detection, note the instruction error mask
4247 * bit is reserved, so we leave it masked.
4249 if (IS_G4X(dev_priv)) {
4250 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4251 GM45_ERROR_MEM_PRIV |
4252 GM45_ERROR_CP_PRIV |
4253 I915_ERROR_MEMORY_REFRESH);
4255 error_mask = ~(I915_ERROR_PAGE_TABLE |
4256 I915_ERROR_MEMORY_REFRESH);
4258 I915_WRITE(EMR, error_mask);
4260 /* Unmask the interrupts that we always want on. */
4261 dev_priv->irq_mask =
4262 ~(I915_ASLE_INTERRUPT |
4263 I915_DISPLAY_PORT_INTERRUPT |
4264 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4265 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4266 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4269 I915_ASLE_INTERRUPT |
4270 I915_DISPLAY_PORT_INTERRUPT |
4271 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4272 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4273 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
4274 I915_USER_INTERRUPT;
4276 if (IS_G4X(dev_priv))
4277 enable_mask |= I915_BSD_USER_INTERRUPT;
4279 GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
4281 /* Interrupt setup is already guaranteed to be single-threaded, this is
4282 * just to make the assert_spin_locked check happy. */
4283 spin_lock_irq(&dev_priv->irq_lock);
4284 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4285 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4286 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4287 spin_unlock_irq(&dev_priv->irq_lock);
4289 i915_enable_asle_pipestat(dev_priv);
4294 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
4298 lockdep_assert_held(&dev_priv->irq_lock);
4300 /* Note HDMI and DP share hotplug bits */
4301 /* enable bits are the same for all generations */
4302 hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
4303 /* Programming the CRT detection parameters tends
4304 to generate a spurious hotplug event about three
4305 seconds later. So just do it once.
4307 if (IS_G4X(dev_priv))
4308 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4309 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4311 /* Ignore TV since it's buggy */
4312 i915_hotplug_interrupt_update_locked(dev_priv,
4313 HOTPLUG_INT_EN_MASK |
4314 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
4315 CRT_HOTPLUG_ACTIVATION_PERIOD_64,
4319 static irqreturn_t i965_irq_handler(int irq, void *arg)
4321 struct drm_device *dev = arg;
4322 struct drm_i915_private *dev_priv = to_i915(dev);
4323 irqreturn_t ret = IRQ_NONE;
4325 if (!intel_irqs_enabled(dev_priv))
4328 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4329 disable_rpm_wakeref_asserts(dev_priv);
4332 u32 pipe_stats[I915_MAX_PIPES] = {};
4333 u32 hotplug_status = 0;
4336 iir = I915_READ(IIR);
4342 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4343 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4345 /* Call regardless, as some status bits might not be
4346 * signalled in iir */
4347 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
4349 I915_WRITE(IIR, iir);
4351 if (iir & I915_USER_INTERRUPT)
4352 notify_ring(dev_priv->engine[RCS]);
4354 if (iir & I915_BSD_USER_INTERRUPT)
4355 notify_ring(dev_priv->engine[VCS]);
4357 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4358 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4361 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4363 i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);
4366 enable_rpm_wakeref_asserts(dev_priv);
4372 * intel_irq_init - initializes irq support
4373 * @dev_priv: i915 device instance
4375 * This function initializes all the irq support including work items, timers
4376 * and all the vtables. It does not setup the interrupt itself though.
4378 void intel_irq_init(struct drm_i915_private *dev_priv)
4380 struct drm_device *dev = &dev_priv->drm;
4381 struct intel_rps *rps = &dev_priv->gt_pm.rps;
4384 intel_hpd_init_work(dev_priv);
4386 INIT_WORK(&rps->work, gen6_pm_rps_work);
4388 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4389 for (i = 0; i < MAX_L3_SLICES; ++i)
4390 dev_priv->l3_parity.remap_info[i] = NULL;
4392 if (HAS_GUC_SCHED(dev_priv))
4393 dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
4395 /* Let's track the enabled rps events */
4396 if (IS_VALLEYVIEW(dev_priv))
4397 /* WaGsvRC0ResidencyMethod:vlv */
4398 dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
4400 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4402 rps->pm_intrmsk_mbz = 0;
4405 * SNB,IVB,HSW can while VLV,CHV may hard hang on looping batchbuffer
4406 * if GEN6_PM_UP_EI_EXPIRED is masked.
4408 * TODO: verify if this can be reproduced on VLV,CHV.
4410 if (INTEL_GEN(dev_priv) <= 7)
4411 rps->pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED;
4413 if (INTEL_GEN(dev_priv) >= 8)
4414 rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
4416 if (IS_GEN2(dev_priv)) {
4417 /* Gen2 doesn't have a hardware frame counter */
4418 dev->max_vblank_count = 0;
4419 } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
4420 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4421 dev->driver->get_vblank_counter = g4x_get_vblank_counter;
4423 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4424 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4428 * Opt out of the vblank disable timer on everything except gen2.
4429 * Gen2 doesn't have a hardware frame counter and so depends on
4430 * vblank interrupts to produce sane vblank seuquence numbers.
4432 if (!IS_GEN2(dev_priv))
4433 dev->vblank_disable_immediate = true;
4435 /* Most platforms treat the display irq block as an always-on
4436 * power domain. vlv/chv can disable it at runtime and need
4437 * special care to avoid writing any of the display block registers
4438 * outside of the power domain. We defer setting up the display irqs
4439 * in this case to the runtime pm.
4441 dev_priv->display_irqs_enabled = true;
4442 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4443 dev_priv->display_irqs_enabled = false;
4445 dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
4447 dev->driver->get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos;
4448 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4450 if (IS_CHERRYVIEW(dev_priv)) {
4451 dev->driver->irq_handler = cherryview_irq_handler;
4452 dev->driver->irq_preinstall = cherryview_irq_reset;
4453 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4454 dev->driver->irq_uninstall = cherryview_irq_reset;
4455 dev->driver->enable_vblank = i965_enable_vblank;
4456 dev->driver->disable_vblank = i965_disable_vblank;
4457 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4458 } else if (IS_VALLEYVIEW(dev_priv)) {
4459 dev->driver->irq_handler = valleyview_irq_handler;
4460 dev->driver->irq_preinstall = valleyview_irq_reset;
4461 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4462 dev->driver->irq_uninstall = valleyview_irq_reset;
4463 dev->driver->enable_vblank = i965_enable_vblank;
4464 dev->driver->disable_vblank = i965_disable_vblank;
4465 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4466 } else if (INTEL_GEN(dev_priv) >= 11) {
4467 dev->driver->irq_handler = gen11_irq_handler;
4468 dev->driver->irq_preinstall = gen11_irq_reset;
4469 dev->driver->irq_postinstall = gen11_irq_postinstall;
4470 dev->driver->irq_uninstall = gen11_irq_reset;
4471 dev->driver->enable_vblank = gen8_enable_vblank;
4472 dev->driver->disable_vblank = gen8_disable_vblank;
4473 dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4474 } else if (INTEL_GEN(dev_priv) >= 8) {
4475 dev->driver->irq_handler = gen8_irq_handler;
4476 dev->driver->irq_preinstall = gen8_irq_reset;
4477 dev->driver->irq_postinstall = gen8_irq_postinstall;
4478 dev->driver->irq_uninstall = gen8_irq_reset;
4479 dev->driver->enable_vblank = gen8_enable_vblank;
4480 dev->driver->disable_vblank = gen8_disable_vblank;
4481 if (IS_GEN9_LP(dev_priv))
4482 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4483 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv) ||
4484 HAS_PCH_CNP(dev_priv))
4485 dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4487 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4488 } else if (HAS_PCH_SPLIT(dev_priv)) {
4489 dev->driver->irq_handler = ironlake_irq_handler;
4490 dev->driver->irq_preinstall = ironlake_irq_reset;
4491 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4492 dev->driver->irq_uninstall = ironlake_irq_reset;
4493 dev->driver->enable_vblank = ironlake_enable_vblank;
4494 dev->driver->disable_vblank = ironlake_disable_vblank;
4495 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4497 if (IS_GEN2(dev_priv)) {
4498 dev->driver->irq_preinstall = i8xx_irq_reset;
4499 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4500 dev->driver->irq_handler = i8xx_irq_handler;
4501 dev->driver->irq_uninstall = i8xx_irq_reset;
4502 dev->driver->enable_vblank = i8xx_enable_vblank;
4503 dev->driver->disable_vblank = i8xx_disable_vblank;
4504 } else if (IS_GEN3(dev_priv)) {
4505 dev->driver->irq_preinstall = i915_irq_reset;
4506 dev->driver->irq_postinstall = i915_irq_postinstall;
4507 dev->driver->irq_uninstall = i915_irq_reset;
4508 dev->driver->irq_handler = i915_irq_handler;
4509 dev->driver->enable_vblank = i8xx_enable_vblank;
4510 dev->driver->disable_vblank = i8xx_disable_vblank;
4512 dev->driver->irq_preinstall = i965_irq_reset;
4513 dev->driver->irq_postinstall = i965_irq_postinstall;
4514 dev->driver->irq_uninstall = i965_irq_reset;
4515 dev->driver->irq_handler = i965_irq_handler;
4516 dev->driver->enable_vblank = i965_enable_vblank;
4517 dev->driver->disable_vblank = i965_disable_vblank;
4519 if (I915_HAS_HOTPLUG(dev_priv))
4520 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4525 * intel_irq_fini - deinitializes IRQ support
4526 * @i915: i915 device instance
4528 * This function deinitializes all the IRQ support.
4530 void intel_irq_fini(struct drm_i915_private *i915)
4534 for (i = 0; i < MAX_L3_SLICES; ++i)
4535 kfree(i915->l3_parity.remap_info[i]);
4539 * intel_irq_install - enables the hardware interrupt
4540 * @dev_priv: i915 device instance
4542 * This function enables the hardware interrupt handling, but leaves the hotplug
4543 * handling still disabled. It is called after intel_irq_init().
4545 * In the driver load and resume code we need working interrupts in a few places
4546 * but don't want to deal with the hassle of concurrent probe and hotplug
4547 * workers. Hence the split into this two-stage approach.
4549 int intel_irq_install(struct drm_i915_private *dev_priv)
4552 * We enable some interrupt sources in our postinstall hooks, so mark
4553 * interrupts as enabled _before_ actually enabling them to avoid
4554 * special cases in our ordering checks.
4556 dev_priv->runtime_pm.irqs_enabled = true;
4558 return drm_irq_install(&dev_priv->drm, dev_priv->drm.pdev->irq);
4562 * intel_irq_uninstall - finilizes all irq handling
4563 * @dev_priv: i915 device instance
4565 * This stops interrupt and hotplug handling and unregisters and frees all
4566 * resources acquired in the init functions.
4568 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4570 drm_irq_uninstall(&dev_priv->drm);
4571 intel_hpd_cancel_work(dev_priv);
4572 dev_priv->runtime_pm.irqs_enabled = false;
4576 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4577 * @dev_priv: i915 device instance
4579 * This function is used to disable interrupts at runtime, both in the runtime
4580 * pm and the system suspend/resume code.
4582 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4584 dev_priv->drm.driver->irq_uninstall(&dev_priv->drm);
4585 dev_priv->runtime_pm.irqs_enabled = false;
4586 synchronize_irq(dev_priv->drm.irq);
4590 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4591 * @dev_priv: i915 device instance
4593 * This function is used to enable interrupts at runtime, both in the runtime
4594 * pm and the system suspend/resume code.
4596 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4598 dev_priv->runtime_pm.irqs_enabled = true;
4599 dev_priv->drm.driver->irq_preinstall(&dev_priv->drm);
4600 dev_priv->drm.driver->irq_postinstall(&dev_priv->drm);