2 * Copyright © 2008,2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
29 #include <linux/dma_remapping.h>
30 #include <linux/reservation.h>
31 #include <linux/sync_file.h>
32 #include <linux/uaccess.h>
35 #include <drm/drm_syncobj.h>
36 #include <drm/i915_drm.h>
39 #include "i915_gem_clflush.h"
40 #include "i915_trace.h"
41 #include "intel_drv.h"
42 #include "intel_frontbuffer.h"
48 #define DBG_FORCE_RELOC 0 /* choose one of the above! */
51 #define __EXEC_OBJECT_HAS_REF BIT(31)
52 #define __EXEC_OBJECT_HAS_PIN BIT(30)
53 #define __EXEC_OBJECT_HAS_FENCE BIT(29)
54 #define __EXEC_OBJECT_NEEDS_MAP BIT(28)
55 #define __EXEC_OBJECT_NEEDS_BIAS BIT(27)
56 #define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 27) /* all of the above */
57 #define __EXEC_OBJECT_RESERVED (__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE)
59 #define __EXEC_HAS_RELOC BIT(31)
60 #define __EXEC_VALIDATED BIT(30)
61 #define UPDATE PIN_OFFSET_FIXED
63 #define BATCH_OFFSET_BIAS (256*1024)
65 #define __I915_EXEC_ILLEGAL_FLAGS \
66 (__I915_EXEC_UNKNOWN_FLAGS | I915_EXEC_CONSTANTS_MASK)
69 * DOC: User command execution
71 * Userspace submits commands to be executed on the GPU as an instruction
72 * stream within a GEM object we call a batchbuffer. This instructions may
73 * refer to other GEM objects containing auxiliary state such as kernels,
74 * samplers, render targets and even secondary batchbuffers. Userspace does
75 * not know where in the GPU memory these objects reside and so before the
76 * batchbuffer is passed to the GPU for execution, those addresses in the
77 * batchbuffer and auxiliary objects are updated. This is known as relocation,
78 * or patching. To try and avoid having to relocate each object on the next
79 * execution, userspace is told the location of those objects in this pass,
80 * but this remains just a hint as the kernel may choose a new location for
81 * any object in the future.
83 * Processing an execbuf ioctl is conceptually split up into a few phases.
85 * 1. Validation - Ensure all the pointers, handles and flags are valid.
86 * 2. Reservation - Assign GPU address space for every object
87 * 3. Relocation - Update any addresses to point to the final locations
88 * 4. Serialisation - Order the request with respect to its dependencies
89 * 5. Construction - Construct a request to execute the batchbuffer
90 * 6. Submission (at some point in the future execution)
92 * Reserving resources for the execbuf is the most complicated phase. We
93 * neither want to have to migrate the object in the address space, nor do
94 * we want to have to update any relocations pointing to this object. Ideally,
95 * we want to leave the object where it is and for all the existing relocations
96 * to match. If the object is given a new address, or if userspace thinks the
97 * object is elsewhere, we have to parse all the relocation entries and update
98 * the addresses. Userspace can set the I915_EXEC_NORELOC flag to hint that
99 * all the target addresses in all of its objects match the value in the
100 * relocation entries and that they all match the presumed offsets given by the
101 * list of execbuffer objects. Using this knowledge, we know that if we haven't
102 * moved any buffers, all the relocation entries are valid and we can skip
103 * the update. (If userspace is wrong, the likely outcome is an impromptu GPU
104 * hang.) The requirement for using I915_EXEC_NO_RELOC are:
106 * The addresses written in the objects must match the corresponding
107 * reloc.presumed_offset which in turn must match the corresponding
110 * Any render targets written to in the batch must be flagged with
113 * To avoid stalling, execobject.offset should match the current
114 * address of that object within the active context.
116 * The reservation is done is multiple phases. First we try and keep any
117 * object already bound in its current location - so as long as meets the
118 * constraints imposed by the new execbuffer. Any object left unbound after the
119 * first pass is then fitted into any available idle space. If an object does
120 * not fit, all objects are removed from the reservation and the process rerun
121 * after sorting the objects into a priority order (more difficult to fit
122 * objects are tried first). Failing that, the entire VM is cleared and we try
123 * to fit the execbuf once last time before concluding that it simply will not
126 * A small complication to all of this is that we allow userspace not only to
127 * specify an alignment and a size for the object in the address space, but
128 * we also allow userspace to specify the exact offset. This objects are
129 * simpler to place (the location is known a priori) all we have to do is make
130 * sure the space is available.
132 * Once all the objects are in place, patching up the buried pointers to point
133 * to the final locations is a fairly simple job of walking over the relocation
134 * entry arrays, looking up the right address and rewriting the value into
135 * the object. Simple! ... The relocation entries are stored in user memory
136 * and so to access them we have to copy them into a local buffer. That copy
137 * has to avoid taking any pagefaults as they may lead back to a GEM object
138 * requiring the struct_mutex (i.e. recursive deadlock). So once again we split
139 * the relocation into multiple passes. First we try to do everything within an
140 * atomic context (avoid the pagefaults) which requires that we never wait. If
141 * we detect that we may wait, or if we need to fault, then we have to fallback
142 * to a slower path. The slowpath has to drop the mutex. (Can you hear alarm
143 * bells yet?) Dropping the mutex means that we lose all the state we have
144 * built up so far for the execbuf and we must reset any global data. However,
145 * we do leave the objects pinned in their final locations - which is a
146 * potential issue for concurrent execbufs. Once we have left the mutex, we can
147 * allocate and copy all the relocation entries into a large array at our
148 * leisure, reacquire the mutex, reclaim all the objects and other state and
149 * then proceed to update any incorrect addresses with the objects.
151 * As we process the relocation entries, we maintain a record of whether the
152 * object is being written to. Using NORELOC, we expect userspace to provide
153 * this information instead. We also check whether we can skip the relocation
154 * by comparing the expected value inside the relocation entry with the target's
155 * final address. If they differ, we have to map the current object and rewrite
156 * the 4 or 8 byte pointer within.
158 * Serialising an execbuf is quite simple according to the rules of the GEM
159 * ABI. Execution within each context is ordered by the order of submission.
160 * Writes to any GEM object are in order of submission and are exclusive. Reads
161 * from a GEM object are unordered with respect to other reads, but ordered by
162 * writes. A write submitted after a read cannot occur before the read, and
163 * similarly any read submitted after a write cannot occur before the write.
164 * Writes are ordered between engines such that only one write occurs at any
165 * time (completing any reads beforehand) - using semaphores where available
166 * and CPU serialisation otherwise. Other GEM access obey the same rules, any
167 * write (either via mmaps using set-domain, or via pwrite) must flush all GPU
168 * reads before starting, and any read (either using set-domain or pread) must
169 * flush all GPU writes before starting. (Note we only employ a barrier before,
170 * we currently rely on userspace not concurrently starting a new execution
171 * whilst reading or writing to an object. This may be an advantage or not
172 * depending on how much you trust userspace not to shoot themselves in the
173 * foot.) Serialisation may just result in the request being inserted into
174 * a DAG awaiting its turn, but most simple is to wait on the CPU until
175 * all dependencies are resolved.
177 * After all of that, is just a matter of closing the request and handing it to
178 * the hardware (well, leaving it in a queue to be executed). However, we also
179 * offer the ability for batchbuffers to be run with elevated privileges so
180 * that they access otherwise hidden registers. (Used to adjust L3 cache etc.)
181 * Before any batch is given extra privileges we first must check that it
182 * contains no nefarious instructions, we check that each instruction is from
183 * our whitelist and all registers are also from an allowed list. We first
184 * copy the user's batchbuffer to a shadow (so that the user doesn't have
185 * access to it, either by the CPU or GPU as we scan it) and then parse each
186 * instruction. If everything is ok, we set a flag telling the hardware to run
187 * the batchbuffer in trusted mode, otherwise the ioctl is rejected.
190 struct i915_execbuffer {
191 struct drm_i915_private *i915; /** i915 backpointer */
192 struct drm_file *file; /** per-file lookup tables and limits */
193 struct drm_i915_gem_execbuffer2 *args; /** ioctl parameters */
194 struct drm_i915_gem_exec_object2 *exec; /** ioctl execobj[] */
195 struct i915_vma **vma;
198 struct intel_engine_cs *engine; /** engine to queue the request to */
199 struct i915_gem_context *ctx; /** context for building the request */
200 struct i915_address_space *vm; /** GTT and vma for the request */
202 struct drm_i915_gem_request *request; /** our request to build */
203 struct i915_vma *batch; /** identity of the batch obj/vma */
205 /** actual size of execobj[] as we may extend it for the cmdparser */
206 unsigned int buffer_count;
208 /** list of vma not yet bound during reservation phase */
209 struct list_head unbound;
211 /** list of vma that have execobj.relocation_count */
212 struct list_head relocs;
215 * Track the most recently used object for relocations, as we
216 * frequently have to perform multiple relocations within the same
220 struct drm_mm_node node; /** temporary GTT binding */
221 unsigned long vaddr; /** Current kmap address */
222 unsigned long page; /** Currently mapped page index */
223 unsigned int gen; /** Cached value of INTEL_GEN */
224 bool use_64bit_reloc : 1;
227 bool needs_unfenced : 1;
229 struct drm_i915_gem_request *rq;
231 unsigned int rq_size;
234 u64 invalid_flags; /** Set of execobj.flags that are invalid */
235 u32 context_flags; /** Set of execobj.flags to insert from the ctx */
237 u32 batch_start_offset; /** Location within object of batch */
238 u32 batch_len; /** Length of batch within object */
239 u32 batch_flags; /** Flags composed for emit_bb_start() */
242 * Indicate either the size of the hastable used to resolve
243 * relocation handles, or if negative that we are using a direct
244 * index into the execobj[].
247 struct hlist_head *buckets; /** ht for relocation handles */
250 #define exec_entry(EB, VMA) (&(EB)->exec[(VMA)->exec_flags - (EB)->flags])
253 * Used to convert any address to canonical form.
254 * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS,
255 * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the
256 * addresses to be in a canonical form:
257 * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct
258 * canonical form [63:48] == [47]."
260 #define GEN8_HIGH_ADDRESS_BIT 47
261 static inline u64 gen8_canonical_addr(u64 address)
263 return sign_extend64(address, GEN8_HIGH_ADDRESS_BIT);
266 static inline u64 gen8_noncanonical_addr(u64 address)
268 return address & GENMASK_ULL(GEN8_HIGH_ADDRESS_BIT, 0);
271 static int eb_create(struct i915_execbuffer *eb)
273 if (!(eb->args->flags & I915_EXEC_HANDLE_LUT)) {
274 unsigned int size = 1 + ilog2(eb->buffer_count);
277 * Without a 1:1 association between relocation handles and
278 * the execobject[] index, we instead create a hashtable.
279 * We size it dynamically based on available memory, starting
280 * first with 1:1 assocative hash and scaling back until
281 * the allocation succeeds.
283 * Later on we use a positive lut_size to indicate we are
284 * using this hashtable, and a negative value to indicate a
290 /* While we can still reduce the allocation size, don't
291 * raise a warning and allow the allocation to fail.
292 * On the last pass though, we want to try as hard
293 * as possible to perform the allocation and warn
296 flags = GFP_TEMPORARY;
298 flags |= __GFP_NORETRY | __GFP_NOWARN;
300 eb->buckets = kzalloc(sizeof(struct hlist_head) << size,
311 eb->lut_size = -eb->buffer_count;
318 eb_vma_misplaced(const struct drm_i915_gem_exec_object2 *entry,
319 const struct i915_vma *vma,
322 if (vma->node.size < entry->pad_to_size)
325 if (entry->alignment && !IS_ALIGNED(vma->node.start, entry->alignment))
328 if (flags & EXEC_OBJECT_PINNED &&
329 vma->node.start != entry->offset)
332 if (flags & __EXEC_OBJECT_NEEDS_BIAS &&
333 vma->node.start < BATCH_OFFSET_BIAS)
336 if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) &&
337 (vma->node.start + vma->node.size - 1) >> 32)
344 eb_pin_vma(struct i915_execbuffer *eb,
345 const struct drm_i915_gem_exec_object2 *entry,
346 struct i915_vma *vma)
348 unsigned int exec_flags = *vma->exec_flags;
352 pin_flags = vma->node.start;
354 pin_flags = entry->offset & PIN_OFFSET_MASK;
356 pin_flags |= PIN_USER | PIN_NOEVICT | PIN_OFFSET_FIXED;
357 if (unlikely(exec_flags & EXEC_OBJECT_NEEDS_GTT))
358 pin_flags |= PIN_GLOBAL;
360 if (unlikely(i915_vma_pin(vma, 0, 0, pin_flags)))
363 if (unlikely(exec_flags & EXEC_OBJECT_NEEDS_FENCE)) {
364 if (unlikely(i915_vma_get_fence(vma))) {
369 if (i915_vma_pin_fence(vma))
370 exec_flags |= __EXEC_OBJECT_HAS_FENCE;
373 *vma->exec_flags = exec_flags | __EXEC_OBJECT_HAS_PIN;
374 return !eb_vma_misplaced(entry, vma, exec_flags);
377 static inline void __eb_unreserve_vma(struct i915_vma *vma, unsigned int flags)
379 GEM_BUG_ON(!(flags & __EXEC_OBJECT_HAS_PIN));
381 if (unlikely(flags & __EXEC_OBJECT_HAS_FENCE))
382 i915_vma_unpin_fence(vma);
384 __i915_vma_unpin(vma);
388 eb_unreserve_vma(struct i915_vma *vma, unsigned int *flags)
390 if (!(*flags & __EXEC_OBJECT_HAS_PIN))
393 __eb_unreserve_vma(vma, *flags);
394 *flags &= ~__EXEC_OBJECT_RESERVED;
398 eb_validate_vma(struct i915_execbuffer *eb,
399 struct drm_i915_gem_exec_object2 *entry,
400 struct i915_vma *vma)
402 if (unlikely(entry->flags & eb->invalid_flags))
405 if (unlikely(entry->alignment && !is_power_of_2(entry->alignment)))
409 * Offset can be used as input (EXEC_OBJECT_PINNED), reject
410 * any non-page-aligned or non-canonical addresses.
412 if (unlikely(entry->flags & EXEC_OBJECT_PINNED &&
413 entry->offset != gen8_canonical_addr(entry->offset & PAGE_MASK)))
416 /* pad_to_size was once a reserved field, so sanitize it */
417 if (entry->flags & EXEC_OBJECT_PAD_TO_SIZE) {
418 if (unlikely(offset_in_page(entry->pad_to_size)))
421 entry->pad_to_size = 0;
424 if (unlikely(vma->exec_flags)) {
425 DRM_DEBUG("Object [handle %d, index %d] appears more than once in object list\n",
426 entry->handle, (int)(entry - eb->exec));
431 * From drm_mm perspective address space is continuous,
432 * so from this point we're always using non-canonical
435 entry->offset = gen8_noncanonical_addr(entry->offset);
437 if (!eb->reloc_cache.has_fence) {
438 entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
440 if ((entry->flags & EXEC_OBJECT_NEEDS_FENCE ||
441 eb->reloc_cache.needs_unfenced) &&
442 i915_gem_object_is_tiled(vma->obj))
443 entry->flags |= EXEC_OBJECT_NEEDS_GTT | __EXEC_OBJECT_NEEDS_MAP;
446 if (!(entry->flags & EXEC_OBJECT_PINNED))
447 entry->flags |= eb->context_flags;
453 eb_add_vma(struct i915_execbuffer *eb, unsigned int i, struct i915_vma *vma)
455 struct drm_i915_gem_exec_object2 *entry = &eb->exec[i];
458 GEM_BUG_ON(i915_vma_is_closed(vma));
460 if (!(eb->args->flags & __EXEC_VALIDATED)) {
461 err = eb_validate_vma(eb, entry, vma);
466 if (eb->lut_size > 0) {
467 vma->exec_handle = entry->handle;
468 hlist_add_head(&vma->exec_node,
469 &eb->buckets[hash_32(entry->handle,
473 if (entry->relocation_count)
474 list_add_tail(&vma->reloc_link, &eb->relocs);
477 * Stash a pointer from the vma to execobj, so we can query its flags,
478 * size, alignment etc as provided by the user. Also we stash a pointer
479 * to the vma inside the execobj so that we can use a direct lookup
480 * to find the right target VMA when doing relocations.
483 eb->flags[i] = entry->flags;
484 vma->exec_flags = &eb->flags[i];
487 if (eb_pin_vma(eb, entry, vma)) {
488 if (entry->offset != vma->node.start) {
489 entry->offset = vma->node.start | UPDATE;
490 eb->args->flags |= __EXEC_HAS_RELOC;
493 eb_unreserve_vma(vma, vma->exec_flags);
495 list_add_tail(&vma->exec_link, &eb->unbound);
496 if (drm_mm_node_allocated(&vma->node))
497 err = i915_vma_unbind(vma);
502 static inline int use_cpu_reloc(const struct reloc_cache *cache,
503 const struct drm_i915_gem_object *obj)
505 if (!i915_gem_object_has_struct_page(obj))
508 if (DBG_FORCE_RELOC == FORCE_CPU_RELOC)
511 if (DBG_FORCE_RELOC == FORCE_GTT_RELOC)
514 return (cache->has_llc ||
516 obj->cache_level != I915_CACHE_NONE);
519 static int eb_reserve_vma(const struct i915_execbuffer *eb,
520 struct i915_vma *vma)
522 struct drm_i915_gem_exec_object2 *entry = exec_entry(eb, vma);
523 unsigned int exec_flags = *vma->exec_flags;
527 pin_flags = PIN_USER | PIN_NONBLOCK;
528 if (exec_flags & EXEC_OBJECT_NEEDS_GTT)
529 pin_flags |= PIN_GLOBAL;
532 * Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset,
533 * limit address to the first 4GBs for unflagged objects.
535 if (!(exec_flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS))
536 pin_flags |= PIN_ZONE_4G;
538 if (exec_flags & __EXEC_OBJECT_NEEDS_MAP)
539 pin_flags |= PIN_MAPPABLE;
541 if (exec_flags & EXEC_OBJECT_PINNED) {
542 pin_flags |= entry->offset | PIN_OFFSET_FIXED;
543 pin_flags &= ~PIN_NONBLOCK; /* force overlapping checks */
544 } else if (exec_flags & __EXEC_OBJECT_NEEDS_BIAS) {
545 pin_flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
548 err = i915_vma_pin(vma,
549 entry->pad_to_size, entry->alignment,
554 if (entry->offset != vma->node.start) {
555 entry->offset = vma->node.start | UPDATE;
556 eb->args->flags |= __EXEC_HAS_RELOC;
559 if (unlikely(exec_flags & EXEC_OBJECT_NEEDS_FENCE)) {
560 err = i915_vma_get_fence(vma);
566 if (i915_vma_pin_fence(vma))
567 exec_flags |= __EXEC_OBJECT_HAS_FENCE;
570 *vma->exec_flags = exec_flags | __EXEC_OBJECT_HAS_PIN;
571 GEM_BUG_ON(eb_vma_misplaced(entry, vma, exec_flags));
576 static int eb_reserve(struct i915_execbuffer *eb)
578 const unsigned int count = eb->buffer_count;
579 struct list_head last;
580 struct i915_vma *vma;
581 unsigned int i, pass;
585 * Attempt to pin all of the buffers into the GTT.
586 * This is done in 3 phases:
588 * 1a. Unbind all objects that do not match the GTT constraints for
589 * the execbuffer (fenceable, mappable, alignment etc).
590 * 1b. Increment pin count for already bound objects.
591 * 2. Bind new objects.
592 * 3. Decrement pin count.
594 * This avoid unnecessary unbinding of later objects in order to make
595 * room for the earlier objects *unless* we need to defragment.
601 list_for_each_entry(vma, &eb->unbound, exec_link) {
602 err = eb_reserve_vma(eb, vma);
609 /* Resort *all* the objects into priority order */
610 INIT_LIST_HEAD(&eb->unbound);
611 INIT_LIST_HEAD(&last);
612 for (i = 0; i < count; i++) {
613 unsigned int flags = eb->flags[i];
614 struct i915_vma *vma = eb->vma[i];
616 if (flags & EXEC_OBJECT_PINNED &&
617 flags & __EXEC_OBJECT_HAS_PIN)
620 eb_unreserve_vma(vma, &eb->flags[i]);
622 if (flags & EXEC_OBJECT_PINNED)
623 list_add(&vma->exec_link, &eb->unbound);
624 else if (flags & __EXEC_OBJECT_NEEDS_MAP)
625 list_add_tail(&vma->exec_link, &eb->unbound);
627 list_add_tail(&vma->exec_link, &last);
629 list_splice_tail(&last, &eb->unbound);
636 /* Too fragmented, unbind everything and retry */
637 err = i915_gem_evict_vm(eb->vm);
648 static unsigned int eb_batch_index(const struct i915_execbuffer *eb)
650 if (eb->args->flags & I915_EXEC_BATCH_FIRST)
653 return eb->buffer_count - 1;
656 static int eb_select_context(struct i915_execbuffer *eb)
658 struct i915_gem_context *ctx;
660 ctx = i915_gem_context_lookup(eb->file->driver_priv, eb->args->rsvd1);
665 eb->vm = ctx->ppgtt ? &ctx->ppgtt->base : &eb->i915->ggtt.base;
667 eb->context_flags = 0;
668 if (ctx->flags & CONTEXT_NO_ZEROMAP)
669 eb->context_flags |= __EXEC_OBJECT_NEEDS_BIAS;
674 static int eb_lookup_vmas(struct i915_execbuffer *eb)
676 struct radix_tree_root *handles_vma = &eb->ctx->handles_vma;
677 struct drm_i915_gem_object *uninitialized_var(obj);
681 if (unlikely(i915_gem_context_is_closed(eb->ctx)))
684 if (unlikely(i915_gem_context_is_banned(eb->ctx)))
687 INIT_LIST_HEAD(&eb->relocs);
688 INIT_LIST_HEAD(&eb->unbound);
690 for (i = 0; i < eb->buffer_count; i++) {
691 u32 handle = eb->exec[i].handle;
692 struct i915_lut_handle *lut;
693 struct i915_vma *vma;
695 vma = radix_tree_lookup(handles_vma, handle);
699 obj = i915_gem_object_lookup(eb->file, handle);
700 if (unlikely(!obj)) {
705 vma = i915_vma_instance(obj, eb->vm, NULL);
706 if (unlikely(IS_ERR(vma))) {
711 lut = kmem_cache_alloc(eb->i915->luts, GFP_KERNEL);
712 if (unlikely(!lut)) {
717 err = radix_tree_insert(handles_vma, handle, vma);
723 list_add(&lut->obj_link, &obj->lut_list);
724 list_add(&lut->ctx_link, &eb->ctx->handles_list);
726 lut->handle = handle;
728 /* transfer ref to ctx */
732 err = eb_add_vma(eb, i, vma);
736 GEM_BUG_ON(vma != eb->vma[i]);
737 GEM_BUG_ON(vma->exec_flags != &eb->flags[i]);
740 /* take note of the batch buffer before we might reorder the lists */
741 i = eb_batch_index(eb);
742 eb->batch = eb->vma[i];
743 GEM_BUG_ON(eb->batch->exec_flags != &eb->flags[i]);
746 * SNA is doing fancy tricks with compressing batch buffers, which leads
747 * to negative relocation deltas. Usually that works out ok since the
748 * relocate address is still positive, except when the batch is placed
749 * very low in the GTT. Ensure this doesn't happen.
751 * Note that actual hangs have only been observed on gen7, but for
752 * paranoia do it everywhere.
754 if (!(eb->flags[i] & EXEC_OBJECT_PINNED))
755 eb->flags[i] |= __EXEC_OBJECT_NEEDS_BIAS;
756 if (eb->reloc_cache.has_fence)
757 eb->flags[i] |= EXEC_OBJECT_NEEDS_FENCE;
759 eb->args->flags |= __EXEC_VALIDATED;
760 return eb_reserve(eb);
764 i915_gem_object_put(obj);
770 static struct i915_vma *
771 eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle)
773 if (eb->lut_size < 0) {
774 if (handle >= -eb->lut_size)
776 return eb->vma[handle];
778 struct hlist_head *head;
779 struct i915_vma *vma;
781 head = &eb->buckets[hash_32(handle, eb->lut_size)];
782 hlist_for_each_entry(vma, head, exec_node) {
783 if (vma->exec_handle == handle)
790 static void eb_release_vmas(const struct i915_execbuffer *eb)
792 const unsigned int count = eb->buffer_count;
795 for (i = 0; i < count; i++) {
796 struct i915_vma *vma = eb->vma[i];
797 unsigned int flags = eb->flags[i];
802 GEM_BUG_ON(vma->exec_flags != &eb->flags[i]);
803 vma->exec_flags = NULL;
806 if (flags & __EXEC_OBJECT_HAS_PIN)
807 __eb_unreserve_vma(vma, flags);
809 if (flags & __EXEC_OBJECT_HAS_REF)
814 static void eb_reset_vmas(const struct i915_execbuffer *eb)
817 if (eb->lut_size > 0)
818 memset(eb->buckets, 0,
819 sizeof(struct hlist_head) << eb->lut_size);
822 static void eb_destroy(const struct i915_execbuffer *eb)
824 GEM_BUG_ON(eb->reloc_cache.rq);
826 if (eb->lut_size > 0)
831 relocation_target(const struct drm_i915_gem_relocation_entry *reloc,
832 const struct i915_vma *target)
834 return gen8_canonical_addr((int)reloc->delta + target->node.start);
837 static void reloc_cache_init(struct reloc_cache *cache,
838 struct drm_i915_private *i915)
842 /* Must be a variable in the struct to allow GCC to unroll. */
843 cache->gen = INTEL_GEN(i915);
844 cache->has_llc = HAS_LLC(i915);
845 cache->use_64bit_reloc = HAS_64BIT_RELOC(i915);
846 cache->has_fence = cache->gen < 4;
847 cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment;
848 cache->node.allocated = false;
853 static inline void *unmask_page(unsigned long p)
855 return (void *)(uintptr_t)(p & PAGE_MASK);
858 static inline unsigned int unmask_flags(unsigned long p)
860 return p & ~PAGE_MASK;
863 #define KMAP 0x4 /* after CLFLUSH_FLAGS */
865 static inline struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache)
867 struct drm_i915_private *i915 =
868 container_of(cache, struct i915_execbuffer, reloc_cache)->i915;
872 static void reloc_gpu_flush(struct reloc_cache *cache)
874 GEM_BUG_ON(cache->rq_size >= cache->rq->batch->obj->base.size / sizeof(u32));
875 cache->rq_cmd[cache->rq_size] = MI_BATCH_BUFFER_END;
876 i915_gem_object_unpin_map(cache->rq->batch->obj);
877 i915_gem_chipset_flush(cache->rq->i915);
879 __i915_add_request(cache->rq, true);
883 static void reloc_cache_reset(struct reloc_cache *cache)
888 reloc_gpu_flush(cache);
893 vaddr = unmask_page(cache->vaddr);
894 if (cache->vaddr & KMAP) {
895 if (cache->vaddr & CLFLUSH_AFTER)
898 kunmap_atomic(vaddr);
899 i915_gem_obj_finish_shmem_access((struct drm_i915_gem_object *)cache->node.mm);
902 io_mapping_unmap_atomic((void __iomem *)vaddr);
903 if (cache->node.allocated) {
904 struct i915_ggtt *ggtt = cache_to_ggtt(cache);
906 ggtt->base.clear_range(&ggtt->base,
909 drm_mm_remove_node(&cache->node);
911 i915_vma_unpin((struct i915_vma *)cache->node.mm);
919 static void *reloc_kmap(struct drm_i915_gem_object *obj,
920 struct reloc_cache *cache,
926 kunmap_atomic(unmask_page(cache->vaddr));
928 unsigned int flushes;
931 err = i915_gem_obj_prepare_shmem_write(obj, &flushes);
935 BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS);
936 BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK);
938 cache->vaddr = flushes | KMAP;
939 cache->node.mm = (void *)obj;
944 vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, page));
945 cache->vaddr = unmask_flags(cache->vaddr) | (unsigned long)vaddr;
951 static void *reloc_iomap(struct drm_i915_gem_object *obj,
952 struct reloc_cache *cache,
955 struct i915_ggtt *ggtt = cache_to_ggtt(cache);
956 unsigned long offset;
960 io_mapping_unmap_atomic((void __force __iomem *) unmask_page(cache->vaddr));
962 struct i915_vma *vma;
965 if (use_cpu_reloc(cache, obj))
968 err = i915_gem_object_set_to_gtt_domain(obj, true);
972 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
973 PIN_MAPPABLE | PIN_NONBLOCK);
975 memset(&cache->node, 0, sizeof(cache->node));
976 err = drm_mm_insert_node_in_range
977 (&ggtt->base.mm, &cache->node,
978 PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE,
979 0, ggtt->mappable_end,
981 if (err) /* no inactive aperture space, use cpu reloc */
984 err = i915_vma_put_fence(vma);
990 cache->node.start = vma->node.start;
991 cache->node.mm = (void *)vma;
995 offset = cache->node.start;
996 if (cache->node.allocated) {
998 ggtt->base.insert_page(&ggtt->base,
999 i915_gem_object_get_dma_address(obj, page),
1000 offset, I915_CACHE_NONE, 0);
1002 offset += page << PAGE_SHIFT;
1005 vaddr = (void __force *)io_mapping_map_atomic_wc(&ggtt->mappable,
1008 cache->vaddr = (unsigned long)vaddr;
1013 static void *reloc_vaddr(struct drm_i915_gem_object *obj,
1014 struct reloc_cache *cache,
1019 if (cache->page == page) {
1020 vaddr = unmask_page(cache->vaddr);
1023 if ((cache->vaddr & KMAP) == 0)
1024 vaddr = reloc_iomap(obj, cache, page);
1026 vaddr = reloc_kmap(obj, cache, page);
1032 static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
1034 if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
1035 if (flushes & CLFLUSH_BEFORE) {
1043 * Writes to the same cacheline are serialised by the CPU
1044 * (including clflush). On the write path, we only require
1045 * that it hits memory in an orderly fashion and place
1046 * mb barriers at the start and end of the relocation phase
1047 * to ensure ordering of clflush wrt to the system.
1049 if (flushes & CLFLUSH_AFTER)
1055 static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
1056 struct i915_vma *vma,
1059 struct reloc_cache *cache = &eb->reloc_cache;
1060 struct drm_i915_gem_object *obj;
1061 struct drm_i915_gem_request *rq;
1062 struct i915_vma *batch;
1066 GEM_BUG_ON(vma->obj->base.write_domain & I915_GEM_DOMAIN_CPU);
1068 obj = i915_gem_batch_pool_get(&eb->engine->batch_pool, PAGE_SIZE);
1070 return PTR_ERR(obj);
1072 cmd = i915_gem_object_pin_map(obj,
1073 cache->has_llc ? I915_MAP_WB : I915_MAP_WC);
1074 i915_gem_object_unpin_pages(obj);
1076 return PTR_ERR(cmd);
1078 err = i915_gem_object_set_to_wc_domain(obj, false);
1082 batch = i915_vma_instance(obj, vma->vm, NULL);
1083 if (IS_ERR(batch)) {
1084 err = PTR_ERR(batch);
1088 err = i915_vma_pin(batch, 0, 0, PIN_USER | PIN_NONBLOCK);
1092 rq = i915_gem_request_alloc(eb->engine, eb->ctx);
1098 err = i915_gem_request_await_object(rq, vma->obj, true);
1102 err = eb->engine->emit_flush(rq, EMIT_INVALIDATE);
1106 err = i915_switch_context(rq);
1110 err = eb->engine->emit_bb_start(rq,
1111 batch->node.start, PAGE_SIZE,
1112 cache->gen > 5 ? 0 : I915_DISPATCH_SECURE);
1116 GEM_BUG_ON(!reservation_object_test_signaled_rcu(batch->resv, true));
1117 i915_vma_move_to_active(batch, rq, 0);
1118 reservation_object_lock(batch->resv, NULL);
1119 reservation_object_add_excl_fence(batch->resv, &rq->fence);
1120 reservation_object_unlock(batch->resv);
1121 i915_vma_unpin(batch);
1123 i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
1124 reservation_object_lock(vma->resv, NULL);
1125 reservation_object_add_excl_fence(vma->resv, &rq->fence);
1126 reservation_object_unlock(vma->resv);
1131 cache->rq_cmd = cmd;
1134 /* Return with batch mapping (cmd) still pinned */
1138 i915_add_request(rq);
1140 i915_vma_unpin(batch);
1142 i915_gem_object_unpin_map(obj);
1146 static u32 *reloc_gpu(struct i915_execbuffer *eb,
1147 struct i915_vma *vma,
1150 struct reloc_cache *cache = &eb->reloc_cache;
1153 if (cache->rq_size > PAGE_SIZE/sizeof(u32) - (len + 1))
1154 reloc_gpu_flush(cache);
1156 if (unlikely(!cache->rq)) {
1159 err = __reloc_gpu_alloc(eb, vma, len);
1161 return ERR_PTR(err);
1164 cmd = cache->rq_cmd + cache->rq_size;
1165 cache->rq_size += len;
1171 relocate_entry(struct i915_vma *vma,
1172 const struct drm_i915_gem_relocation_entry *reloc,
1173 struct i915_execbuffer *eb,
1174 const struct i915_vma *target)
1176 u64 offset = reloc->offset;
1177 u64 target_offset = relocation_target(reloc, target);
1178 bool wide = eb->reloc_cache.use_64bit_reloc;
1181 if (!eb->reloc_cache.vaddr &&
1182 (DBG_FORCE_RELOC == FORCE_GPU_RELOC ||
1183 !reservation_object_test_signaled_rcu(vma->resv, true)) &&
1184 __intel_engine_can_store_dword(eb->reloc_cache.gen,
1185 eb->engine->class)) {
1186 const unsigned int gen = eb->reloc_cache.gen;
1192 len = offset & 7 ? 8 : 5;
1198 batch = reloc_gpu(eb, vma, len);
1202 addr = gen8_canonical_addr(vma->node.start + offset);
1205 *batch++ = MI_STORE_DWORD_IMM_GEN4;
1206 *batch++ = lower_32_bits(addr);
1207 *batch++ = upper_32_bits(addr);
1208 *batch++ = lower_32_bits(target_offset);
1210 addr = gen8_canonical_addr(addr + 4);
1212 *batch++ = MI_STORE_DWORD_IMM_GEN4;
1213 *batch++ = lower_32_bits(addr);
1214 *batch++ = upper_32_bits(addr);
1215 *batch++ = upper_32_bits(target_offset);
1217 *batch++ = (MI_STORE_DWORD_IMM_GEN4 | (1 << 21)) + 1;
1218 *batch++ = lower_32_bits(addr);
1219 *batch++ = upper_32_bits(addr);
1220 *batch++ = lower_32_bits(target_offset);
1221 *batch++ = upper_32_bits(target_offset);
1223 } else if (gen >= 6) {
1224 *batch++ = MI_STORE_DWORD_IMM_GEN4;
1227 *batch++ = target_offset;
1228 } else if (gen >= 4) {
1229 *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
1232 *batch++ = target_offset;
1234 *batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
1236 *batch++ = target_offset;
1243 vaddr = reloc_vaddr(vma->obj, &eb->reloc_cache, offset >> PAGE_SHIFT);
1245 return PTR_ERR(vaddr);
1247 clflush_write32(vaddr + offset_in_page(offset),
1248 lower_32_bits(target_offset),
1249 eb->reloc_cache.vaddr);
1252 offset += sizeof(u32);
1253 target_offset >>= 32;
1259 return target->node.start | UPDATE;
1263 eb_relocate_entry(struct i915_execbuffer *eb,
1264 struct i915_vma *vma,
1265 const struct drm_i915_gem_relocation_entry *reloc)
1267 struct i915_vma *target;
1270 /* we've already hold a reference to all valid objects */
1271 target = eb_get_vma(eb, reloc->target_handle);
1272 if (unlikely(!target))
1275 /* Validate that the target is in a valid r/w GPU domain */
1276 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
1277 DRM_DEBUG("reloc with multiple write domains: "
1278 "target %d offset %d "
1279 "read %08x write %08x",
1280 reloc->target_handle,
1281 (int) reloc->offset,
1282 reloc->read_domains,
1283 reloc->write_domain);
1286 if (unlikely((reloc->write_domain | reloc->read_domains)
1287 & ~I915_GEM_GPU_DOMAINS)) {
1288 DRM_DEBUG("reloc with read/write non-GPU domains: "
1289 "target %d offset %d "
1290 "read %08x write %08x",
1291 reloc->target_handle,
1292 (int) reloc->offset,
1293 reloc->read_domains,
1294 reloc->write_domain);
1298 if (reloc->write_domain) {
1299 *target->exec_flags |= EXEC_OBJECT_WRITE;
1302 * Sandybridge PPGTT errata: We need a global gtt mapping
1303 * for MI and pipe_control writes because the gpu doesn't
1304 * properly redirect them through the ppgtt for non_secure
1307 if (reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
1308 IS_GEN6(eb->i915)) {
1309 err = i915_vma_bind(target, target->obj->cache_level,
1312 "Unexpected failure to bind target VMA!"))
1318 * If the relocation already has the right value in it, no
1319 * more work needs to be done.
1321 if (!DBG_FORCE_RELOC &&
1322 gen8_canonical_addr(target->node.start) == reloc->presumed_offset)
1325 /* Check that the relocation address is valid... */
1326 if (unlikely(reloc->offset >
1327 vma->size - (eb->reloc_cache.use_64bit_reloc ? 8 : 4))) {
1328 DRM_DEBUG("Relocation beyond object bounds: "
1329 "target %d offset %d size %d.\n",
1330 reloc->target_handle,
1335 if (unlikely(reloc->offset & 3)) {
1336 DRM_DEBUG("Relocation not 4-byte aligned: "
1337 "target %d offset %d.\n",
1338 reloc->target_handle,
1339 (int)reloc->offset);
1344 * If we write into the object, we need to force the synchronisation
1345 * barrier, either with an asynchronous clflush or if we executed the
1346 * patching using the GPU (though that should be serialised by the
1347 * timeline). To be completely sure, and since we are required to
1348 * do relocations we are already stalling, disable the user's opt
1349 * out of our synchronisation.
1351 *vma->exec_flags &= ~EXEC_OBJECT_ASYNC;
1353 /* and update the user's relocation entry */
1354 return relocate_entry(vma, reloc, eb, target);
1357 static int eb_relocate_vma(struct i915_execbuffer *eb, struct i915_vma *vma)
1359 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
1360 struct drm_i915_gem_relocation_entry stack[N_RELOC(512)];
1361 struct drm_i915_gem_relocation_entry __user *urelocs;
1362 const struct drm_i915_gem_exec_object2 *entry = exec_entry(eb, vma);
1363 unsigned int remain;
1365 urelocs = u64_to_user_ptr(entry->relocs_ptr);
1366 remain = entry->relocation_count;
1367 if (unlikely(remain > N_RELOC(ULONG_MAX)))
1371 * We must check that the entire relocation array is safe
1372 * to read. However, if the array is not writable the user loses
1373 * the updated relocation values.
1375 if (unlikely(!access_ok(VERIFY_READ, urelocs, remain*sizeof(*urelocs))))
1379 struct drm_i915_gem_relocation_entry *r = stack;
1380 unsigned int count =
1381 min_t(unsigned int, remain, ARRAY_SIZE(stack));
1382 unsigned int copied;
1385 * This is the fast path and we cannot handle a pagefault
1386 * whilst holding the struct mutex lest the user pass in the
1387 * relocations contained within a mmaped bo. For in such a case
1388 * we, the page fault handler would call i915_gem_fault() and
1389 * we would try to acquire the struct mutex again. Obviously
1390 * this is bad and so lockdep complains vehemently.
1392 pagefault_disable();
1393 copied = __copy_from_user_inatomic(r, urelocs, count * sizeof(r[0]));
1395 if (unlikely(copied)) {
1402 u64 offset = eb_relocate_entry(eb, vma, r);
1404 if (likely(offset == 0)) {
1405 } else if ((s64)offset < 0) {
1406 remain = (int)offset;
1410 * Note that reporting an error now
1411 * leaves everything in an inconsistent
1412 * state as we have *already* changed
1413 * the relocation value inside the
1414 * object. As we have not changed the
1415 * reloc.presumed_offset or will not
1416 * change the execobject.offset, on the
1417 * call we may not rewrite the value
1418 * inside the object, leaving it
1419 * dangling and causing a GPU hang. Unless
1420 * userspace dynamically rebuilds the
1421 * relocations on each execbuf rather than
1422 * presume a static tree.
1424 * We did previously check if the relocations
1425 * were writable (access_ok), an error now
1426 * would be a strange race with mprotect,
1427 * having already demonstrated that we
1428 * can read from this userspace address.
1430 offset = gen8_canonical_addr(offset & ~UPDATE);
1432 &urelocs[r-stack].presumed_offset);
1434 } while (r++, --count);
1435 urelocs += ARRAY_SIZE(stack);
1438 reloc_cache_reset(&eb->reloc_cache);
1443 eb_relocate_vma_slow(struct i915_execbuffer *eb, struct i915_vma *vma)
1445 const struct drm_i915_gem_exec_object2 *entry = exec_entry(eb, vma);
1446 struct drm_i915_gem_relocation_entry *relocs =
1447 u64_to_ptr(typeof(*relocs), entry->relocs_ptr);
1451 for (i = 0; i < entry->relocation_count; i++) {
1452 u64 offset = eb_relocate_entry(eb, vma, &relocs[i]);
1454 if ((s64)offset < 0) {
1461 reloc_cache_reset(&eb->reloc_cache);
1465 static int check_relocations(const struct drm_i915_gem_exec_object2 *entry)
1467 const char __user *addr, *end;
1469 char __maybe_unused c;
1471 size = entry->relocation_count;
1475 if (size > N_RELOC(ULONG_MAX))
1478 addr = u64_to_user_ptr(entry->relocs_ptr);
1479 size *= sizeof(struct drm_i915_gem_relocation_entry);
1480 if (!access_ok(VERIFY_READ, addr, size))
1484 for (; addr < end; addr += PAGE_SIZE) {
1485 int err = __get_user(c, addr);
1489 return __get_user(c, end - 1);
1492 static int eb_copy_relocations(const struct i915_execbuffer *eb)
1494 const unsigned int count = eb->buffer_count;
1498 for (i = 0; i < count; i++) {
1499 const unsigned int nreloc = eb->exec[i].relocation_count;
1500 struct drm_i915_gem_relocation_entry __user *urelocs;
1501 struct drm_i915_gem_relocation_entry *relocs;
1503 unsigned long copied;
1508 err = check_relocations(&eb->exec[i]);
1512 urelocs = u64_to_user_ptr(eb->exec[i].relocs_ptr);
1513 size = nreloc * sizeof(*relocs);
1515 relocs = kvmalloc_array(size, 1, GFP_TEMPORARY);
1522 /* copy_from_user is limited to < 4GiB */
1526 min_t(u64, BIT_ULL(31), size - copied);
1528 if (__copy_from_user((char *)relocs + copied,
1529 (char *)urelocs + copied,
1537 } while (copied < size);
1540 * As we do not update the known relocation offsets after
1541 * relocating (due to the complexities in lock handling),
1542 * we need to mark them as invalid now so that we force the
1543 * relocation processing next time. Just in case the target
1544 * object is evicted and then rebound into its old
1545 * presumed_offset before the next execbuffer - if that
1546 * happened we would make the mistake of assuming that the
1547 * relocations were valid.
1549 user_access_begin();
1550 for (copied = 0; copied < nreloc; copied++)
1552 &urelocs[copied].presumed_offset,
1557 eb->exec[i].relocs_ptr = (uintptr_t)relocs;
1564 struct drm_i915_gem_relocation_entry *relocs =
1565 u64_to_ptr(typeof(*relocs), eb->exec[i].relocs_ptr);
1566 if (eb->exec[i].relocation_count)
1572 static int eb_prefault_relocations(const struct i915_execbuffer *eb)
1574 const unsigned int count = eb->buffer_count;
1577 if (unlikely(i915.prefault_disable))
1580 for (i = 0; i < count; i++) {
1583 err = check_relocations(&eb->exec[i]);
1591 static noinline int eb_relocate_slow(struct i915_execbuffer *eb)
1593 struct drm_device *dev = &eb->i915->drm;
1594 bool have_copy = false;
1595 struct i915_vma *vma;
1599 if (signal_pending(current)) {
1604 /* We may process another execbuffer during the unlock... */
1606 mutex_unlock(&dev->struct_mutex);
1609 * We take 3 passes through the slowpatch.
1611 * 1 - we try to just prefault all the user relocation entries and
1612 * then attempt to reuse the atomic pagefault disabled fast path again.
1614 * 2 - we copy the user entries to a local buffer here outside of the
1615 * local and allow ourselves to wait upon any rendering before
1618 * 3 - we already have a local copy of the relocation entries, but
1619 * were interrupted (EAGAIN) whilst waiting for the objects, try again.
1622 err = eb_prefault_relocations(eb);
1623 } else if (!have_copy) {
1624 err = eb_copy_relocations(eb);
1625 have_copy = err == 0;
1631 mutex_lock(&dev->struct_mutex);
1635 /* A frequent cause for EAGAIN are currently unavailable client pages */
1636 flush_workqueue(eb->i915->mm.userptr_wq);
1638 err = i915_mutex_lock_interruptible(dev);
1640 mutex_lock(&dev->struct_mutex);
1644 /* reacquire the objects */
1645 err = eb_lookup_vmas(eb);
1649 GEM_BUG_ON(!eb->batch);
1651 list_for_each_entry(vma, &eb->relocs, reloc_link) {
1653 pagefault_disable();
1654 err = eb_relocate_vma(eb, vma);
1659 err = eb_relocate_vma_slow(eb, vma);
1666 * Leave the user relocations as are, this is the painfully slow path,
1667 * and we want to avoid the complication of dropping the lock whilst
1668 * having buffers reserved in the aperture and so causing spurious
1669 * ENOSPC for random operations.
1678 const unsigned int count = eb->buffer_count;
1681 for (i = 0; i < count; i++) {
1682 const struct drm_i915_gem_exec_object2 *entry =
1684 struct drm_i915_gem_relocation_entry *relocs;
1686 if (!entry->relocation_count)
1689 relocs = u64_to_ptr(typeof(*relocs), entry->relocs_ptr);
1697 static int eb_relocate(struct i915_execbuffer *eb)
1699 if (eb_lookup_vmas(eb))
1702 /* The objects are in their final locations, apply the relocations. */
1703 if (eb->args->flags & __EXEC_HAS_RELOC) {
1704 struct i915_vma *vma;
1706 list_for_each_entry(vma, &eb->relocs, reloc_link) {
1707 if (eb_relocate_vma(eb, vma))
1715 return eb_relocate_slow(eb);
1718 static void eb_export_fence(struct i915_vma *vma,
1719 struct drm_i915_gem_request *req,
1722 struct reservation_object *resv = vma->resv;
1725 * Ignore errors from failing to allocate the new fence, we can't
1726 * handle an error right now. Worst case should be missed
1727 * synchronisation leading to rendering corruption.
1729 reservation_object_lock(resv, NULL);
1730 if (flags & EXEC_OBJECT_WRITE)
1731 reservation_object_add_excl_fence(resv, &req->fence);
1732 else if (reservation_object_reserve_shared(resv) == 0)
1733 reservation_object_add_shared_fence(resv, &req->fence);
1734 reservation_object_unlock(resv);
1737 static int eb_move_to_gpu(struct i915_execbuffer *eb)
1739 const unsigned int count = eb->buffer_count;
1743 for (i = 0; i < count; i++) {
1744 unsigned int flags = eb->flags[i];
1745 struct i915_vma *vma = eb->vma[i];
1746 struct drm_i915_gem_object *obj = vma->obj;
1748 if (flags & EXEC_OBJECT_CAPTURE) {
1749 struct i915_gem_capture_list *capture;
1751 capture = kmalloc(sizeof(*capture), GFP_KERNEL);
1752 if (unlikely(!capture))
1755 capture->next = eb->request->capture_list;
1756 capture->vma = eb->vma[i];
1757 eb->request->capture_list = capture;
1761 * If the GPU is not _reading_ through the CPU cache, we need
1762 * to make sure that any writes (both previous GPU writes from
1763 * before a change in snooping levels and normal CPU writes)
1764 * caught in that cache are flushed to main memory.
1767 * obj->cache_dirty &&
1768 * !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)
1769 * but gcc's optimiser doesn't handle that as well and emits
1770 * two jumps instead of one. Maybe one day...
1772 if (unlikely(obj->cache_dirty & ~obj->cache_coherent)) {
1773 if (i915_gem_clflush_object(obj, 0))
1774 flags &= ~EXEC_OBJECT_ASYNC;
1777 if (flags & EXEC_OBJECT_ASYNC)
1780 err = i915_gem_request_await_object
1781 (eb->request, obj, flags & EXEC_OBJECT_WRITE);
1786 for (i = 0; i < count; i++) {
1787 unsigned int flags = eb->flags[i];
1788 struct i915_vma *vma = eb->vma[i];
1790 i915_vma_move_to_active(vma, eb->request, flags);
1791 eb_export_fence(vma, eb->request, flags);
1793 __eb_unreserve_vma(vma, flags);
1794 vma->exec_flags = NULL;
1796 if (unlikely(flags & __EXEC_OBJECT_HAS_REF))
1801 /* Unconditionally flush any chipset caches (for streaming writes). */
1802 i915_gem_chipset_flush(eb->i915);
1804 /* Unconditionally invalidate GPU caches and TLBs. */
1805 return eb->engine->emit_flush(eb->request, EMIT_INVALIDATE);
1808 static bool i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
1810 if (exec->flags & __I915_EXEC_ILLEGAL_FLAGS)
1813 /* Kernel clipping was a DRI1 misfeature */
1814 if (!(exec->flags & I915_EXEC_FENCE_ARRAY)) {
1815 if (exec->num_cliprects || exec->cliprects_ptr)
1819 if (exec->DR4 == 0xffffffff) {
1820 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
1823 if (exec->DR1 || exec->DR4)
1826 if ((exec->batch_start_offset | exec->batch_len) & 0x7)
1832 void i915_vma_move_to_active(struct i915_vma *vma,
1833 struct drm_i915_gem_request *req,
1836 struct drm_i915_gem_object *obj = vma->obj;
1837 const unsigned int idx = req->engine->id;
1839 lockdep_assert_held(&req->i915->drm.struct_mutex);
1840 GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
1843 * Add a reference if we're newly entering the active list.
1844 * The order in which we add operations to the retirement queue is
1845 * vital here: mark_active adds to the start of the callback list,
1846 * such that subsequent callbacks are called first. Therefore we
1847 * add the active reference first and queue for it to be dropped
1850 if (!i915_vma_is_active(vma))
1851 obj->active_count++;
1852 i915_vma_set_active(vma, idx);
1853 i915_gem_active_set(&vma->last_read[idx], req);
1854 list_move_tail(&vma->vm_link, &vma->vm->active_list);
1856 obj->base.write_domain = 0;
1857 if (flags & EXEC_OBJECT_WRITE) {
1858 obj->base.write_domain = I915_GEM_DOMAIN_RENDER;
1860 if (intel_fb_obj_invalidate(obj, ORIGIN_CS))
1861 i915_gem_active_set(&obj->frontbuffer_write, req);
1863 obj->base.read_domains = 0;
1865 obj->base.read_domains |= I915_GEM_GPU_DOMAINS;
1867 if (flags & EXEC_OBJECT_NEEDS_FENCE)
1868 i915_gem_active_set(&vma->last_fence, req);
1871 static int i915_reset_gen7_sol_offsets(struct drm_i915_gem_request *req)
1876 if (!IS_GEN7(req->i915) || req->engine->id != RCS) {
1877 DRM_DEBUG("sol reset is gen7/rcs only\n");
1881 cs = intel_ring_begin(req, 4 * 2 + 2);
1885 *cs++ = MI_LOAD_REGISTER_IMM(4);
1886 for (i = 0; i < 4; i++) {
1887 *cs++ = i915_mmio_reg_offset(GEN7_SO_WRITE_OFFSET(i));
1891 intel_ring_advance(req, cs);
1896 static struct i915_vma *eb_parse(struct i915_execbuffer *eb, bool is_master)
1898 struct drm_i915_gem_object *shadow_batch_obj;
1899 struct i915_vma *vma;
1902 shadow_batch_obj = i915_gem_batch_pool_get(&eb->engine->batch_pool,
1903 PAGE_ALIGN(eb->batch_len));
1904 if (IS_ERR(shadow_batch_obj))
1905 return ERR_CAST(shadow_batch_obj);
1907 err = intel_engine_cmd_parser(eb->engine,
1910 eb->batch_start_offset,
1914 if (err == -EACCES) /* unhandled chained batch */
1921 vma = i915_gem_object_ggtt_pin(shadow_batch_obj, NULL, 0, 0, 0);
1925 eb->vma[eb->buffer_count] = i915_vma_get(vma);
1926 eb->flags[eb->buffer_count] =
1927 __EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_REF;
1928 vma->exec_flags = &eb->flags[eb->buffer_count];
1932 i915_gem_object_unpin_pages(shadow_batch_obj);
1937 add_to_client(struct drm_i915_gem_request *req, struct drm_file *file)
1939 req->file_priv = file->driver_priv;
1940 list_add_tail(&req->client_link, &req->file_priv->mm.request_list);
1943 static int eb_submit(struct i915_execbuffer *eb)
1947 err = eb_move_to_gpu(eb);
1951 err = i915_switch_context(eb->request);
1955 if (eb->args->flags & I915_EXEC_GEN7_SOL_RESET) {
1956 err = i915_reset_gen7_sol_offsets(eb->request);
1961 err = eb->engine->emit_bb_start(eb->request,
1962 eb->batch->node.start +
1963 eb->batch_start_offset,
1973 * Find one BSD ring to dispatch the corresponding BSD command.
1974 * The engine index is returned.
1977 gen8_dispatch_bsd_engine(struct drm_i915_private *dev_priv,
1978 struct drm_file *file)
1980 struct drm_i915_file_private *file_priv = file->driver_priv;
1982 /* Check whether the file_priv has already selected one ring. */
1983 if ((int)file_priv->bsd_engine < 0)
1984 file_priv->bsd_engine = atomic_fetch_xor(1,
1985 &dev_priv->mm.bsd_engine_dispatch_index);
1987 return file_priv->bsd_engine;
1990 #define I915_USER_RINGS (4)
1992 static const enum intel_engine_id user_ring_map[I915_USER_RINGS + 1] = {
1993 [I915_EXEC_DEFAULT] = RCS,
1994 [I915_EXEC_RENDER] = RCS,
1995 [I915_EXEC_BLT] = BCS,
1996 [I915_EXEC_BSD] = VCS,
1997 [I915_EXEC_VEBOX] = VECS
2000 static struct intel_engine_cs *
2001 eb_select_engine(struct drm_i915_private *dev_priv,
2002 struct drm_file *file,
2003 struct drm_i915_gem_execbuffer2 *args)
2005 unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK;
2006 struct intel_engine_cs *engine;
2008 if (user_ring_id > I915_USER_RINGS) {
2009 DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id);
2013 if ((user_ring_id != I915_EXEC_BSD) &&
2014 ((args->flags & I915_EXEC_BSD_MASK) != 0)) {
2015 DRM_DEBUG("execbuf with non bsd ring but with invalid "
2016 "bsd dispatch flags: %d\n", (int)(args->flags));
2020 if (user_ring_id == I915_EXEC_BSD && HAS_BSD2(dev_priv)) {
2021 unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK;
2023 if (bsd_idx == I915_EXEC_BSD_DEFAULT) {
2024 bsd_idx = gen8_dispatch_bsd_engine(dev_priv, file);
2025 } else if (bsd_idx >= I915_EXEC_BSD_RING1 &&
2026 bsd_idx <= I915_EXEC_BSD_RING2) {
2027 bsd_idx >>= I915_EXEC_BSD_SHIFT;
2030 DRM_DEBUG("execbuf with unknown bsd ring: %u\n",
2035 engine = dev_priv->engine[_VCS(bsd_idx)];
2037 engine = dev_priv->engine[user_ring_map[user_ring_id]];
2041 DRM_DEBUG("execbuf with invalid ring: %u\n", user_ring_id);
2049 __free_fence_array(struct drm_syncobj **fences, unsigned int n)
2052 drm_syncobj_put(ptr_mask_bits(fences[n], 2));
2056 static struct drm_syncobj **
2057 get_fence_array(struct drm_i915_gem_execbuffer2 *args,
2058 struct drm_file *file)
2060 const unsigned int nfences = args->num_cliprects;
2061 struct drm_i915_gem_exec_fence __user *user;
2062 struct drm_syncobj **fences;
2066 if (!(args->flags & I915_EXEC_FENCE_ARRAY))
2069 if (nfences > SIZE_MAX / sizeof(*fences))
2070 return ERR_PTR(-EINVAL);
2072 user = u64_to_user_ptr(args->cliprects_ptr);
2073 if (!access_ok(VERIFY_READ, user, nfences * 2 * sizeof(u32)))
2074 return ERR_PTR(-EFAULT);
2076 fences = kvmalloc_array(args->num_cliprects, sizeof(*fences),
2077 __GFP_NOWARN | GFP_TEMPORARY);
2079 return ERR_PTR(-ENOMEM);
2081 for (n = 0; n < nfences; n++) {
2082 struct drm_i915_gem_exec_fence fence;
2083 struct drm_syncobj *syncobj;
2085 if (__copy_from_user(&fence, user++, sizeof(fence))) {
2090 syncobj = drm_syncobj_find(file, fence.handle);
2092 DRM_DEBUG("Invalid syncobj handle provided\n");
2097 fences[n] = ptr_pack_bits(syncobj, fence.flags, 2);
2103 __free_fence_array(fences, n);
2104 return ERR_PTR(err);
2108 put_fence_array(struct drm_i915_gem_execbuffer2 *args,
2109 struct drm_syncobj **fences)
2112 __free_fence_array(fences, args->num_cliprects);
2116 await_fence_array(struct i915_execbuffer *eb,
2117 struct drm_syncobj **fences)
2119 const unsigned int nfences = eb->args->num_cliprects;
2123 for (n = 0; n < nfences; n++) {
2124 struct drm_syncobj *syncobj;
2125 struct dma_fence *fence;
2128 syncobj = ptr_unpack_bits(fences[n], &flags, 2);
2129 if (!(flags & I915_EXEC_FENCE_WAIT))
2132 fence = drm_syncobj_fence_get(syncobj);
2136 err = i915_gem_request_await_dma_fence(eb->request, fence);
2137 dma_fence_put(fence);
2146 signal_fence_array(struct i915_execbuffer *eb,
2147 struct drm_syncobj **fences)
2149 const unsigned int nfences = eb->args->num_cliprects;
2150 struct dma_fence * const fence = &eb->request->fence;
2153 for (n = 0; n < nfences; n++) {
2154 struct drm_syncobj *syncobj;
2157 syncobj = ptr_unpack_bits(fences[n], &flags, 2);
2158 if (!(flags & I915_EXEC_FENCE_SIGNAL))
2161 drm_syncobj_replace_fence(syncobj, fence);
2166 i915_gem_do_execbuffer(struct drm_device *dev,
2167 struct drm_file *file,
2168 struct drm_i915_gem_execbuffer2 *args,
2169 struct drm_i915_gem_exec_object2 *exec,
2170 struct drm_syncobj **fences)
2172 struct i915_execbuffer eb;
2173 struct dma_fence *in_fence = NULL;
2174 struct sync_file *out_fence = NULL;
2175 int out_fence_fd = -1;
2178 BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS &
2179 ~__EXEC_OBJECT_UNKNOWN_FLAGS);
2181 eb.i915 = to_i915(dev);
2184 if (DBG_FORCE_RELOC || !(args->flags & I915_EXEC_NO_RELOC))
2185 args->flags |= __EXEC_HAS_RELOC;
2188 eb.vma = (struct i915_vma **)(exec + args->buffer_count + 1);
2190 eb.flags = (unsigned int *)(eb.vma + args->buffer_count + 1);
2192 eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
2193 if (USES_FULL_PPGTT(eb.i915))
2194 eb.invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
2195 reloc_cache_init(&eb.reloc_cache, eb.i915);
2197 eb.buffer_count = args->buffer_count;
2198 eb.batch_start_offset = args->batch_start_offset;
2199 eb.batch_len = args->batch_len;
2202 if (args->flags & I915_EXEC_SECURE) {
2203 if (!drm_is_current_master(file) || !capable(CAP_SYS_ADMIN))
2206 eb.batch_flags |= I915_DISPATCH_SECURE;
2208 if (args->flags & I915_EXEC_IS_PINNED)
2209 eb.batch_flags |= I915_DISPATCH_PINNED;
2211 eb.engine = eb_select_engine(eb.i915, file, args);
2215 if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
2216 if (!HAS_RESOURCE_STREAMER(eb.i915)) {
2217 DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
2220 if (eb.engine->id != RCS) {
2221 DRM_DEBUG("RS is not available on %s\n",
2226 eb.batch_flags |= I915_DISPATCH_RS;
2229 if (args->flags & I915_EXEC_FENCE_IN) {
2230 in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));
2235 if (args->flags & I915_EXEC_FENCE_OUT) {
2236 out_fence_fd = get_unused_fd_flags(O_CLOEXEC);
2237 if (out_fence_fd < 0) {
2243 err = eb_create(&eb);
2247 GEM_BUG_ON(!eb.lut_size);
2249 err = eb_select_context(&eb);
2254 * Take a local wakeref for preparing to dispatch the execbuf as
2255 * we expect to access the hardware fairly frequently in the
2256 * process. Upon first dispatch, we acquire another prolonged
2257 * wakeref that we hold until the GPU has been idle for at least
2260 intel_runtime_pm_get(eb.i915);
2262 err = i915_mutex_lock_interruptible(dev);
2266 err = eb_relocate(&eb);
2269 * If the user expects the execobject.offset and
2270 * reloc.presumed_offset to be an exact match,
2271 * as for using NO_RELOC, then we cannot update
2272 * the execobject.offset until we have completed
2275 args->flags &= ~__EXEC_HAS_RELOC;
2279 if (unlikely(*eb.batch->exec_flags & EXEC_OBJECT_WRITE)) {
2280 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
2284 if (eb.batch_start_offset > eb.batch->size ||
2285 eb.batch_len > eb.batch->size - eb.batch_start_offset) {
2286 DRM_DEBUG("Attempting to use out-of-bounds batch\n");
2291 if (eb.engine->needs_cmd_parser && eb.batch_len) {
2292 struct i915_vma *vma;
2294 vma = eb_parse(&eb, drm_is_current_master(file));
2302 * Batch parsed and accepted:
2304 * Set the DISPATCH_SECURE bit to remove the NON_SECURE
2305 * bit from MI_BATCH_BUFFER_START commands issued in
2306 * the dispatch_execbuffer implementations. We
2307 * specifically don't want that set on batches the
2308 * command parser has accepted.
2310 eb.batch_flags |= I915_DISPATCH_SECURE;
2311 eb.batch_start_offset = 0;
2316 if (eb.batch_len == 0)
2317 eb.batch_len = eb.batch->size - eb.batch_start_offset;
2320 * snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
2321 * batch" bit. Hence we need to pin secure batches into the global gtt.
2322 * hsw should have this fixed, but bdw mucks it up again. */
2323 if (eb.batch_flags & I915_DISPATCH_SECURE) {
2324 struct i915_vma *vma;
2327 * So on first glance it looks freaky that we pin the batch here
2328 * outside of the reservation loop. But:
2329 * - The batch is already pinned into the relevant ppgtt, so we
2330 * already have the backing storage fully allocated.
2331 * - No other BO uses the global gtt (well contexts, but meh),
2332 * so we don't really have issues with multiple objects not
2333 * fitting due to fragmentation.
2334 * So this is actually safe.
2336 vma = i915_gem_object_ggtt_pin(eb.batch->obj, NULL, 0, 0, 0);
2345 /* All GPU relocation batches must be submitted prior to the user rq */
2346 GEM_BUG_ON(eb.reloc_cache.rq);
2348 /* Allocate a request for this batch buffer nice and early. */
2349 eb.request = i915_gem_request_alloc(eb.engine, eb.ctx);
2350 if (IS_ERR(eb.request)) {
2351 err = PTR_ERR(eb.request);
2352 goto err_batch_unpin;
2356 err = i915_gem_request_await_dma_fence(eb.request, in_fence);
2362 err = await_fence_array(&eb, fences);
2367 if (out_fence_fd != -1) {
2368 out_fence = sync_file_create(&eb.request->fence);
2376 * Whilst this request exists, batch_obj will be on the
2377 * active_list, and so will hold the active reference. Only when this
2378 * request is retired will the the batch_obj be moved onto the
2379 * inactive_list and lose its active reference. Hence we do not need
2380 * to explicitly hold another reference here.
2382 eb.request->batch = eb.batch;
2384 trace_i915_gem_request_queue(eb.request, eb.batch_flags);
2385 err = eb_submit(&eb);
2387 __i915_add_request(eb.request, err == 0);
2388 add_to_client(eb.request, file);
2391 signal_fence_array(&eb, fences);
2395 fd_install(out_fence_fd, out_fence->file);
2396 args->rsvd2 &= GENMASK_ULL(0, 31); /* keep in-fence */
2397 args->rsvd2 |= (u64)out_fence_fd << 32;
2400 fput(out_fence->file);
2405 if (eb.batch_flags & I915_DISPATCH_SECURE)
2406 i915_vma_unpin(eb.batch);
2409 eb_release_vmas(&eb);
2410 mutex_unlock(&dev->struct_mutex);
2412 intel_runtime_pm_put(eb.i915);
2413 i915_gem_context_put(eb.ctx);
2417 if (out_fence_fd != -1)
2418 put_unused_fd(out_fence_fd);
2420 dma_fence_put(in_fence);
2425 * Legacy execbuffer just creates an exec2 list from the original exec object
2426 * list array and passes it to the real function.
2429 i915_gem_execbuffer(struct drm_device *dev, void *data,
2430 struct drm_file *file)
2432 const size_t sz = (sizeof(struct drm_i915_gem_exec_object2) +
2433 sizeof(struct i915_vma *) +
2434 sizeof(unsigned int));
2435 struct drm_i915_gem_execbuffer *args = data;
2436 struct drm_i915_gem_execbuffer2 exec2;
2437 struct drm_i915_gem_exec_object *exec_list = NULL;
2438 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
2442 if (args->buffer_count < 1 || args->buffer_count > SIZE_MAX / sz - 1) {
2443 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
2447 exec2.buffers_ptr = args->buffers_ptr;
2448 exec2.buffer_count = args->buffer_count;
2449 exec2.batch_start_offset = args->batch_start_offset;
2450 exec2.batch_len = args->batch_len;
2451 exec2.DR1 = args->DR1;
2452 exec2.DR4 = args->DR4;
2453 exec2.num_cliprects = args->num_cliprects;
2454 exec2.cliprects_ptr = args->cliprects_ptr;
2455 exec2.flags = I915_EXEC_RENDER;
2456 i915_execbuffer2_set_context_id(exec2, 0);
2458 if (!i915_gem_check_execbuffer(&exec2))
2461 /* Copy in the exec list from userland */
2462 exec_list = kvmalloc_array(args->buffer_count, sizeof(*exec_list),
2463 __GFP_NOWARN | GFP_TEMPORARY);
2464 exec2_list = kvmalloc_array(args->buffer_count + 1, sz,
2465 __GFP_NOWARN | GFP_TEMPORARY);
2466 if (exec_list == NULL || exec2_list == NULL) {
2467 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
2468 args->buffer_count);
2473 err = copy_from_user(exec_list,
2474 u64_to_user_ptr(args->buffers_ptr),
2475 sizeof(*exec_list) * args->buffer_count);
2477 DRM_DEBUG("copy %d exec entries failed %d\n",
2478 args->buffer_count, err);
2484 for (i = 0; i < args->buffer_count; i++) {
2485 exec2_list[i].handle = exec_list[i].handle;
2486 exec2_list[i].relocation_count = exec_list[i].relocation_count;
2487 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
2488 exec2_list[i].alignment = exec_list[i].alignment;
2489 exec2_list[i].offset = exec_list[i].offset;
2490 if (INTEL_GEN(to_i915(dev)) < 4)
2491 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
2493 exec2_list[i].flags = 0;
2496 err = i915_gem_do_execbuffer(dev, file, &exec2, exec2_list, NULL);
2497 if (exec2.flags & __EXEC_HAS_RELOC) {
2498 struct drm_i915_gem_exec_object __user *user_exec_list =
2499 u64_to_user_ptr(args->buffers_ptr);
2501 /* Copy the new buffer offsets back to the user's exec list. */
2502 for (i = 0; i < args->buffer_count; i++) {
2503 if (!(exec2_list[i].offset & UPDATE))
2506 exec2_list[i].offset =
2507 gen8_canonical_addr(exec2_list[i].offset & PIN_OFFSET_MASK);
2508 exec2_list[i].offset &= PIN_OFFSET_MASK;
2509 if (__copy_to_user(&user_exec_list[i].offset,
2510 &exec2_list[i].offset,
2511 sizeof(user_exec_list[i].offset)))
2522 i915_gem_execbuffer2(struct drm_device *dev, void *data,
2523 struct drm_file *file)
2525 const size_t sz = (sizeof(struct drm_i915_gem_exec_object2) +
2526 sizeof(struct i915_vma *) +
2527 sizeof(unsigned int));
2528 struct drm_i915_gem_execbuffer2 *args = data;
2529 struct drm_i915_gem_exec_object2 *exec2_list;
2530 struct drm_syncobj **fences = NULL;
2533 if (args->buffer_count < 1 || args->buffer_count > SIZE_MAX / sz - 1) {
2534 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
2538 if (!i915_gem_check_execbuffer(args))
2541 /* Allocate an extra slot for use by the command parser */
2542 exec2_list = kvmalloc_array(args->buffer_count + 1, sz,
2543 __GFP_NOWARN | GFP_TEMPORARY);
2544 if (exec2_list == NULL) {
2545 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
2546 args->buffer_count);
2549 if (copy_from_user(exec2_list,
2550 u64_to_user_ptr(args->buffers_ptr),
2551 sizeof(*exec2_list) * args->buffer_count)) {
2552 DRM_DEBUG("copy %d exec entries failed\n", args->buffer_count);
2557 if (args->flags & I915_EXEC_FENCE_ARRAY) {
2558 fences = get_fence_array(args, file);
2559 if (IS_ERR(fences)) {
2561 return PTR_ERR(fences);
2565 err = i915_gem_do_execbuffer(dev, file, args, exec2_list, fences);
2568 * Now that we have begun execution of the batchbuffer, we ignore
2569 * any new error after this point. Also given that we have already
2570 * updated the associated relocations, we try to write out the current
2571 * object locations irrespective of any error.
2573 if (args->flags & __EXEC_HAS_RELOC) {
2574 struct drm_i915_gem_exec_object2 __user *user_exec_list =
2575 u64_to_user_ptr(args->buffers_ptr);
2578 /* Copy the new buffer offsets back to the user's exec list. */
2579 user_access_begin();
2580 for (i = 0; i < args->buffer_count; i++) {
2581 if (!(exec2_list[i].offset & UPDATE))
2584 exec2_list[i].offset =
2585 gen8_canonical_addr(exec2_list[i].offset & PIN_OFFSET_MASK);
2586 unsafe_put_user(exec2_list[i].offset,
2587 &user_exec_list[i].offset,
2594 args->flags &= ~__I915_EXEC_UNKNOWN_FLAGS;
2595 put_fence_array(args, fences);