drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include <uapi/drm/i915_drm.h>
  34 #include <uapi/drm/drm_fourcc.h>
  35
  36 #include <linux/io-mapping.h>
  37 #include <linux/i2c.h>
  38 #include <linux/i2c-algo-bit.h>
  39 #include <linux/backlight.h>
  40 #include <linux/hash.h>
  41 #include <linux/intel-iommu.h>
  42 #include <linux/kref.h>
  43 #include <linux/mm_types.h>
  44 #include <linux/perf_event.h>
  45 #include <linux/pm_qos.h>
  46 #include <linux/dma-resv.h>
  47 #include <linux/shmem_fs.h>
  48 #include <linux/stackdepot.h>
  49 #include <linux/xarray.h>
  50
  51 #include <drm/intel-gtt.h>
  52 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
  53 #include <drm/drm_gem.h>
  54 #include <drm/drm_auth.h>
  55 #include <drm/drm_cache.h>
  56 #include <drm/drm_util.h>
  57 #include <drm/drm_dsc.h>
  58 #include <drm/drm_atomic.h>
  59 #include <drm/drm_connector.h>
  60 #include <drm/i915_mei_hdcp_interface.h>
  61
  62 #include "i915_params.h"
  63 #include "i915_reg.h"
  64 #include "i915_utils.h"
  65
  66 #include "display/intel_bios.h"
  67 #include "display/intel_display.h"
  68 #include "display/intel_display_power.h"
  69 #include "display/intel_dpll_mgr.h"
  70 #include "display/intel_dsb.h"
  71 #include "display/intel_frontbuffer.h"
  72 #include "display/intel_global_state.h"
  73 #include "display/intel_gmbus.h"
  74 #include "display/intel_opregion.h"
  75
  76 #include "gem/i915_gem_context_types.h"
  77 #include "gem/i915_gem_shrinker.h"
  78 #include "gem/i915_gem_stolen.h"
  79
  80 #include "gt/intel_lrc.h"
  81 #include "gt/intel_engine.h"
  82 #include "gt/intel_gt_types.h"
  83 #include "gt/intel_workarounds.h"
  84 #include "gt/uc/intel_uc.h"
  85
  86 #include "intel_device_info.h"
  87 #include "intel_pch.h"
  88 #include "intel_runtime_pm.h"
  89 #include "intel_memory_region.h"
  90 #include "intel_uncore.h"
  91 #include "intel_wakeref.h"
  92 #include "intel_wopcm.h"
  93
  94 #include "i915_gem.h"
  95 #include "i915_gem_gtt.h"
  96 #include "i915_gpu_error.h"
  97 #include "i915_perf_types.h"
  98 #include "i915_request.h"
  99 #include "i915_scheduler.h"
 100 #include "gt/intel_timeline.h"
 101 #include "i915_vma.h"
 102 #include "i915_irq.h"
 103
 104 #include "intel_region_lmem.h"
 105
 106 /* General customization:
 107  */
 108
 109 #define DRIVER_NAME             "i915"
 110 #define DRIVER_DESC             "Intel Graphics"
 111 #define DRIVER_DATE             "20200824"
 112 #define DRIVER_TIMESTAMP        1598293597
 113
 114 struct drm_i915_gem_object;
 115
 116 /*
 117  * The code assumes that the hpd_pins below have consecutive values and
 118  * starting with HPD_PORT_A, the HPD pin associated with any port can be
 119  * retrieved by adding the corresponding port (or phy) enum value to
 120  * HPD_PORT_A in most cases. For example:
 121  * HPD_PORT_C = HPD_PORT_A + PHY_C - PHY_A
 122  */
 123 enum hpd_pin {
 124         HPD_NONE = 0,
 125         HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
 126         HPD_CRT,
 127         HPD_SDVO_B,
 128         HPD_SDVO_C,
 129         HPD_PORT_A,
 130         HPD_PORT_B,
 131         HPD_PORT_C,
 132         HPD_PORT_D,
 133         HPD_PORT_E,
 134         HPD_PORT_F,
 135         HPD_PORT_G,
 136         HPD_PORT_H,
 137         HPD_PORT_I,
 138
 139         HPD_NUM_PINS
 140 };
 141
 142 #define for_each_hpd_pin(__pin) \
 143         for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
 144
 145 /* Threshold == 5 for long IRQs, 50 for short */
 146 #define HPD_STORM_DEFAULT_THRESHOLD 50
 147
 148 struct i915_hotplug {
 149         struct delayed_work hotplug_work;
 150
 151         const u32 *hpd, *pch_hpd;
 152
 153         struct {
 154                 unsigned long last_jiffies;
 155                 int count;
 156                 enum {
 157                         HPD_ENABLED = 0,
 158                         HPD_DISABLED = 1,
 159                         HPD_MARK_DISABLED = 2
 160                 } state;
 161         } stats[HPD_NUM_PINS];
 162         u32 event_bits;
 163         u32 retry_bits;
 164         struct delayed_work reenable_work;
 165
 166         u32 long_port_mask;
 167         u32 short_port_mask;
 168         struct work_struct dig_port_work;
 169
 170         struct work_struct poll_init_work;
 171         bool poll_enabled;
 172
 173         unsigned int hpd_storm_threshold;
 174         /* Whether or not to count short HPD IRQs in HPD storms */
 175         u8 hpd_short_storm_enabled;
 176
 177         /*
 178          * if we get a HPD irq from DP and a HPD irq from non-DP
 179          * the non-DP HPD could block the workqueue on a mode config
 180          * mutex getting, that userspace may have taken. However
 181          * userspace is waiting on the DP workqueue to run which is
 182          * blocked behind the non-DP one.
 183          */
 184         struct workqueue_struct *dp_wq;
 185 };
 186
 187 #define I915_GEM_GPU_DOMAINS \
 188         (I915_GEM_DOMAIN_RENDER | \
 189          I915_GEM_DOMAIN_SAMPLER | \
 190          I915_GEM_DOMAIN_COMMAND | \
 191          I915_GEM_DOMAIN_INSTRUCTION | \
 192          I915_GEM_DOMAIN_VERTEX)
 193
 194 struct drm_i915_private;
 195 struct i915_mm_struct;
 196 struct i915_mmu_object;
 197
 198 struct drm_i915_file_private {
 199         struct drm_i915_private *dev_priv;
 200
 201         union {
 202                 struct drm_file *file;
 203                 struct rcu_head rcu;
 204         };
 205
 206         struct xarray context_xa;
 207         struct xarray vm_xa;
 208
 209         unsigned int bsd_engine;
 210
 211 /*
 212  * Every context ban increments per client ban score. Also
 213  * hangs in short succession increments ban score. If ban threshold
 214  * is reached, client is considered banned and submitting more work
 215  * will fail. This is a stop gap measure to limit the badly behaving
 216  * clients access to gpu. Note that unbannable contexts never increment
 217  * the client ban score.
 218  */
 219 #define I915_CLIENT_SCORE_HANG_FAST     1
 220 #define   I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
 221 #define I915_CLIENT_SCORE_CONTEXT_BAN   3
 222 #define I915_CLIENT_SCORE_BANNED        9
 223         /** ban_score: Accumulated score of all ctx bans and fast hangs. */
 224         atomic_t ban_score;
 225         unsigned long hang_timestamp;
 226 };
 227
 228 /* Interface history:
 229  *
 230  * 1.1: Original.
 231  * 1.2: Add Power Management
 232  * 1.3: Add vblank support
 233  * 1.4: Fix cmdbuffer path, add heap destroy
 234  * 1.5: Add vblank pipe configuration
 235  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 236  *      - Support vertical blank on secondary display pipe
 237  */
 238 #define DRIVER_MAJOR            1
 239 #define DRIVER_MINOR            6
 240 #define DRIVER_PATCHLEVEL       0
 241
 242 struct intel_overlay;
 243 struct intel_overlay_error_state;
 244
 245 struct sdvo_device_mapping {
 246         u8 initialized;
 247         u8 dvo_port;
 248         u8 slave_addr;
 249         u8 dvo_wiring;
 250         u8 i2c_pin;
 251         u8 ddc_pin;
 252 };
 253
 254 struct intel_connector;
 255 struct intel_encoder;
 256 struct intel_atomic_state;
 257 struct intel_cdclk_config;
 258 struct intel_cdclk_state;
 259 struct intel_cdclk_vals;
 260 struct intel_initial_plane_config;
 261 struct intel_crtc;
 262 struct intel_limit;
 263 struct dpll;
 264
 265 struct drm_i915_display_funcs {
 266         void (*get_cdclk)(struct drm_i915_private *dev_priv,
 267                           struct intel_cdclk_config *cdclk_config);
 268         void (*set_cdclk)(struct drm_i915_private *dev_priv,
 269                           const struct intel_cdclk_config *cdclk_config,
 270                           enum pipe pipe);
 271         int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
 272         int (*get_fifo_size)(struct drm_i915_private *dev_priv,
 273                              enum i9xx_plane_id i9xx_plane);
 274         int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
 275         int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
 276         void (*initial_watermarks)(struct intel_atomic_state *state,
 277                                    struct intel_crtc *crtc);
 278         void (*atomic_update_watermarks)(struct intel_atomic_state *state,
 279                                          struct intel_crtc *crtc);
 280         void (*optimize_watermarks)(struct intel_atomic_state *state,
 281                                     struct intel_crtc *crtc);
 282         int (*compute_global_watermarks)(struct intel_atomic_state *state);
 283         void (*update_wm)(struct intel_crtc *crtc);
 284         int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
 285         u8 (*calc_voltage_level)(int cdclk);
 286         /* Returns the active state of the crtc, and if the crtc is active,
 287          * fills out the pipe-config with the hw state. */
 288         bool (*get_pipe_config)(struct intel_crtc *,
 289                                 struct intel_crtc_state *);
 290         void (*get_initial_plane_config)(struct intel_crtc *,
 291                                          struct intel_initial_plane_config *);
 292         int (*crtc_compute_clock)(struct intel_crtc *crtc,
 293                                   struct intel_crtc_state *crtc_state);
 294         void (*crtc_enable)(struct intel_atomic_state *state,
 295                             struct intel_crtc *crtc);
 296         void (*crtc_disable)(struct intel_atomic_state *state,
 297                              struct intel_crtc *crtc);
 298         void (*commit_modeset_enables)(struct intel_atomic_state *state);
 299         void (*commit_modeset_disables)(struct intel_atomic_state *state);
 300         void (*audio_codec_enable)(struct intel_encoder *encoder,
 301                                    const struct intel_crtc_state *crtc_state,
 302                                    const struct drm_connector_state *conn_state);
 303         void (*audio_codec_disable)(struct intel_encoder *encoder,
 304                                     const struct intel_crtc_state *old_crtc_state,
 305                                     const struct drm_connector_state *old_conn_state);
 306         void (*fdi_link_train)(struct intel_crtc *crtc,
 307                                const struct intel_crtc_state *crtc_state);
 308         void (*init_clock_gating)(struct drm_i915_private *dev_priv);
 309         void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
 310         /* clock updates for mode set */
 311         /* cursor updates */
 312         /* render clock increase/decrease */
 313         /* display clock increase/decrease */
 314         /* pll clock increase/decrease */
 315
 316         int (*color_check)(struct intel_crtc_state *crtc_state);
 317         /*
 318          * Program double buffered color management registers during
 319          * vblank evasion. The registers should then latch during the
 320          * next vblank start, alongside any other double buffered registers
 321          * involved with the same commit.
 322          */
 323         void (*color_commit)(const struct intel_crtc_state *crtc_state);
 324         /*
 325          * Load LUTs (and other single buffered color management
 326          * registers). Will (hopefully) be called during the vblank
 327          * following the latching of any double buffered registers
 328          * involved with the same commit.
 329          */
 330         void (*load_luts)(const struct intel_crtc_state *crtc_state);
 331         void (*read_luts)(struct intel_crtc_state *crtc_state);
 332 };
 333
 334 struct intel_csr {
 335         struct work_struct work;
 336         const char *fw_path;
 337         u32 required_version;
 338         u32 max_fw_size; /* bytes */
 339         u32 *dmc_payload;
 340         u32 dmc_fw_size; /* dwords */
 341         u32 version;
 342         u32 mmio_count;
 343         i915_reg_t mmioaddr[20];
 344         u32 mmiodata[20];
 345         u32 dc_state;
 346         u32 target_dc_state;
 347         u32 allowed_dc_mask;
 348         intel_wakeref_t wakeref;
 349 };
 350
 351 enum i915_cache_level {
 352         I915_CACHE_NONE = 0,
 353         I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
 354         I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
 355                               caches, eg sampler/render caches, and the
 356                               large Last-Level-Cache. LLC is coherent with
 357                               the CPU, but L3 is only visible to the GPU. */
 358         I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
 359 };
 360
 361 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
 362
 363 struct intel_fbc {
 364         /* This is always the inner lock when overlapping with struct_mutex and
 365          * it's the outer lock when overlapping with stolen_lock. */
 366         struct mutex lock;
 367         unsigned threshold;
 368         unsigned int possible_framebuffer_bits;
 369         unsigned int busy_bits;
 370         struct intel_crtc *crtc;
 371
 372         struct drm_mm_node compressed_fb;
 373         struct drm_mm_node *compressed_llb;
 374
 375         bool false_color;
 376
 377         bool active;
 378         bool activated;
 379         bool flip_pending;
 380
 381         bool underrun_detected;
 382         struct work_struct underrun_work;
 383
 384         /*
 385          * Due to the atomic rules we can't access some structures without the
 386          * appropriate locking, so we cache information here in order to avoid
 387          * these problems.
 388          */
 389         struct intel_fbc_state_cache {
 390                 struct {
 391                         unsigned int mode_flags;
 392                         u32 hsw_bdw_pixel_rate;
 393                 } crtc;
 394
 395                 struct {
 396                         unsigned int rotation;
 397                         int src_w;
 398                         int src_h;
 399                         bool visible;
 400                         /*
 401                          * Display surface base address adjustement for
 402                          * pageflips. Note that on gen4+ this only adjusts up
 403                          * to a tile, offsets within a tile are handled in
 404                          * the hw itself (with the TILEOFF register).
 405                          */
 406                         int adjusted_x;
 407                         int adjusted_y;
 408
 409                         u16 pixel_blend_mode;
 410                 } plane;
 411
 412                 struct {
 413                         const struct drm_format_info *format;
 414                         unsigned int stride;
 415                         u64 modifier;
 416                 } fb;
 417
 418                 unsigned int fence_y_offset;
 419                 u16 gen9_wa_cfb_stride;
 420                 u16 interval;
 421                 s8 fence_id;
 422         } state_cache;
 423
 424         /*
 425          * This structure contains everything that's relevant to program the
 426          * hardware registers. When we want to figure out if we need to disable
 427          * and re-enable FBC for a new configuration we just check if there's
 428          * something different in the struct. The genx_fbc_activate functions
 429          * are supposed to read from it in order to program the registers.
 430          */
 431         struct intel_fbc_reg_params {
 432                 struct {
 433                         enum pipe pipe;
 434                         enum i9xx_plane_id i9xx_plane;
 435                 } crtc;
 436
 437                 struct {
 438                         const struct drm_format_info *format;
 439                         unsigned int stride;
 440                         u64 modifier;
 441                 } fb;
 442
 443                 int cfb_size;
 444                 unsigned int fence_y_offset;
 445                 u16 gen9_wa_cfb_stride;
 446                 u16 interval;
 447                 s8 fence_id;
 448                 bool plane_visible;
 449         } params;
 450
 451         const char *no_fbc_reason;
 452 };
 453
 454 /*
 455  * HIGH_RR is the highest eDP panel refresh rate read from EDID
 456  * LOW_RR is the lowest eDP panel refresh rate found from EDID
 457  * parsing for same resolution.
 458  */
 459 enum drrs_refresh_rate_type {
 460         DRRS_HIGH_RR,
 461         DRRS_LOW_RR,
 462         DRRS_MAX_RR, /* RR count */
 463 };
 464
 465 enum drrs_support_type {
 466         DRRS_NOT_SUPPORTED = 0,
 467         STATIC_DRRS_SUPPORT = 1,
 468         SEAMLESS_DRRS_SUPPORT = 2
 469 };
 470
 471 struct intel_dp;
 472 struct i915_drrs {
 473         struct mutex mutex;
 474         struct delayed_work work;
 475         struct intel_dp *dp;
 476         unsigned busy_frontbuffer_bits;
 477         enum drrs_refresh_rate_type refresh_rate_type;
 478         enum drrs_support_type type;
 479 };
 480
 481 struct i915_psr {
 482         struct mutex lock;
 483
 484 #define I915_PSR_DEBUG_MODE_MASK        0x0f
 485 #define I915_PSR_DEBUG_DEFAULT          0x00
 486 #define I915_PSR_DEBUG_DISABLE          0x01
 487 #define I915_PSR_DEBUG_ENABLE           0x02
 488 #define I915_PSR_DEBUG_FORCE_PSR1       0x03
 489 #define I915_PSR_DEBUG_IRQ              0x10
 490
 491         u32 debug;
 492         bool sink_support;
 493         bool enabled;
 494         struct intel_dp *dp;
 495         enum pipe pipe;
 496         enum transcoder transcoder;
 497         bool active;
 498         struct work_struct work;
 499         unsigned busy_frontbuffer_bits;
 500         bool sink_psr2_support;
 501         bool link_standby;
 502         bool colorimetry_support;
 503         bool psr2_enabled;
 504         bool psr2_sel_fetch_enabled;
 505         u8 sink_sync_latency;
 506         ktime_t last_entry_attempt;
 507         ktime_t last_exit;
 508         bool sink_not_reliable;
 509         bool irq_aux_error;
 510         u16 su_x_granularity;
 511         bool dc3co_enabled;
 512         u32 dc3co_exit_delay;
 513         struct delayed_work dc3co_work;
 514         bool force_mode_changed;
 515         struct drm_dp_vsc_sdp vsc;
 516 };
 517
 518 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
 519 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
 520 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
 521 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
 522 #define QUIRK_INCREASE_T12_DELAY (1<<6)
 523 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
 524
 525 struct intel_fbdev;
 526 struct intel_fbc_work;
 527
 528 struct intel_gmbus {
 529         struct i2c_adapter adapter;
 530 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
 531         u32 force_bit;
 532         u32 reg0;
 533         i915_reg_t gpio_reg;
 534         struct i2c_algo_bit_data bit_algo;
 535         struct drm_i915_private *dev_priv;
 536 };
 537
 538 struct i915_suspend_saved_registers {
 539         u32 saveDSPARB;
 540         u32 saveFBC_CONTROL;
 541         u32 saveCACHE_MODE_0;
 542         u32 saveMI_ARB_STATE;
 543         u32 saveSWF0[16];
 544         u32 saveSWF1[16];
 545         u32 saveSWF3[3];
 546         u32 savePCH_PORT_HOTPLUG;
 547         u16 saveGCDGMBUS;
 548 };
 549
 550 struct vlv_s0ix_state;
 551
 552 #define MAX_L3_SLICES 2
 553 struct intel_l3_parity {
 554         u32 *remap_info[MAX_L3_SLICES];
 555         struct work_struct error_work;
 556         int which_slice;
 557 };
 558
 559 struct i915_gem_mm {
 560         /** Memory allocator for GTT stolen memory */
 561         struct drm_mm stolen;
 562         /** Protects the usage of the GTT stolen memory allocator. This is
 563          * always the inner lock when overlapping with struct_mutex. */
 564         struct mutex stolen_lock;
 565
 566         /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
 567         spinlock_t obj_lock;
 568
 569         /**
 570          * List of objects which are purgeable.
 571          */
 572         struct list_head purge_list;
 573
 574         /**
 575          * List of objects which have allocated pages and are shrinkable.
 576          */
 577         struct list_head shrink_list;
 578
 579         /**
 580          * List of objects which are pending destruction.
 581          */
 582         struct llist_head free_list;
 583         struct work_struct free_work;
 584         /**
 585          * Count of objects pending destructions. Used to skip needlessly
 586          * waiting on an RCU barrier if no objects are waiting to be freed.
 587          */
 588         atomic_t free_count;
 589
 590         /**
 591          * tmpfs instance used for shmem backed objects
 592          */
 593         struct vfsmount *gemfs;
 594
 595         struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
 596
 597         struct notifier_block oom_notifier;
 598         struct notifier_block vmap_notifier;
 599         struct shrinker shrinker;
 600
 601         /**
 602          * Workqueue to fault in userptr pages, flushed by the execbuf
 603          * when required but otherwise left to userspace to try again
 604          * on EAGAIN.
 605          */
 606         struct workqueue_struct *userptr_wq;
 607
 608         /* shrinker accounting, also useful for userland debugging */
 609         u64 shrink_memory;
 610         u32 shrink_count;
 611 };
 612
 613 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
 614
 615 unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915,
 616                                          u64 context);
 617
 618 static inline unsigned long
 619 i915_fence_timeout(const struct drm_i915_private *i915)
 620 {
 621         return i915_fence_context_timeout(i915, U64_MAX);
 622 }
 623
 624 /* Amount of SAGV/QGV points, BSpec precisely defines this */
 625 #define I915_NUM_QGV_POINTS 8
 626
 627 struct ddi_vbt_port_info {
 628         /* Non-NULL if port present. */
 629         const struct child_device_config *child;
 630
 631         int max_tmds_clock;
 632
 633         /* This is an index in the HDMI/DVI DDI buffer translation table. */
 634         u8 hdmi_level_shift;
 635         u8 hdmi_level_shift_set:1;
 636
 637         u8 supports_dvi:1;
 638         u8 supports_hdmi:1;
 639         u8 supports_dp:1;
 640         u8 supports_edp:1;
 641         u8 supports_typec_usb:1;
 642         u8 supports_tbt:1;
 643
 644         u8 alternate_aux_channel;
 645         u8 alternate_ddc_pin;
 646
 647         u8 dp_boost_level;
 648         u8 hdmi_boost_level;
 649         int dp_max_link_rate;           /* 0 for not limited by VBT */
 650 };
 651
 652 enum psr_lines_to_wait {
 653         PSR_0_LINES_TO_WAIT = 0,
 654         PSR_1_LINE_TO_WAIT,
 655         PSR_4_LINES_TO_WAIT,
 656         PSR_8_LINES_TO_WAIT
 657 };
 658
 659 struct intel_vbt_data {
 660         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
 661         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
 662
 663         /* Feature bits */
 664         unsigned int int_tv_support:1;
 665         unsigned int lvds_dither:1;
 666         unsigned int int_crt_support:1;
 667         unsigned int lvds_use_ssc:1;
 668         unsigned int int_lvds_support:1;
 669         unsigned int display_clock_mode:1;
 670         unsigned int fdi_rx_polarity_inverted:1;
 671         unsigned int panel_type:4;
 672         int lvds_ssc_freq;
 673         unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
 674         enum drm_panel_orientation orientation;
 675
 676         enum drrs_support_type drrs_type;
 677
 678         struct {
 679                 int rate;
 680                 int lanes;
 681                 int preemphasis;
 682                 int vswing;
 683                 bool low_vswing;
 684                 bool initialized;
 685                 int bpp;
 686                 struct edp_power_seq pps;
 687                 bool hobl;
 688         } edp;
 689
 690         struct {
 691                 bool enable;
 692                 bool full_link;
 693                 bool require_aux_wakeup;
 694                 int idle_frames;
 695                 enum psr_lines_to_wait lines_to_wait;
 696                 int tp1_wakeup_time_us;
 697                 int tp2_tp3_wakeup_time_us;
 698                 int psr2_tp2_tp3_wakeup_time_us;
 699         } psr;
 700
 701         struct {
 702                 u16 pwm_freq_hz;
 703                 bool present;
 704                 bool active_low_pwm;
 705                 u8 min_brightness;      /* min_brightness/255 of max */
 706                 u8 controller;          /* brightness controller number */
 707                 enum intel_backlight_type type;
 708         } backlight;
 709
 710         /* MIPI DSI */
 711         struct {
 712                 u16 panel_id;
 713                 struct mipi_config *config;
 714                 struct mipi_pps_data *pps;
 715                 u16 bl_ports;
 716                 u16 cabc_ports;
 717                 u8 seq_version;
 718                 u32 size;
 719                 u8 *data;
 720                 const u8 *sequence[MIPI_SEQ_MAX];
 721                 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
 722                 enum drm_panel_orientation orientation;
 723         } dsi;
 724
 725         int crt_ddc_pin;
 726
 727         struct list_head display_devices;
 728
 729         struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
 730         struct sdvo_device_mapping sdvo_mappings[2];
 731 };
 732
 733 enum intel_ddb_partitioning {
 734         INTEL_DDB_PART_1_2,
 735         INTEL_DDB_PART_5_6, /* IVB+ */
 736 };
 737
 738 struct ilk_wm_values {
 739         u32 wm_pipe[3];
 740         u32 wm_lp[3];
 741         u32 wm_lp_spr[3];
 742         bool enable_fbc_wm;
 743         enum intel_ddb_partitioning partitioning;
 744 };
 745
 746 struct g4x_pipe_wm {
 747         u16 plane[I915_MAX_PLANES];
 748         u16 fbc;
 749 };
 750
 751 struct g4x_sr_wm {
 752         u16 plane;
 753         u16 cursor;
 754         u16 fbc;
 755 };
 756
 757 struct vlv_wm_ddl_values {
 758         u8 plane[I915_MAX_PLANES];
 759 };
 760
 761 struct vlv_wm_values {
 762         struct g4x_pipe_wm pipe[3];
 763         struct g4x_sr_wm sr;
 764         struct vlv_wm_ddl_values ddl[3];
 765         u8 level;
 766         bool cxsr;
 767 };
 768
 769 struct g4x_wm_values {
 770         struct g4x_pipe_wm pipe[2];
 771         struct g4x_sr_wm sr;
 772         struct g4x_sr_wm hpll;
 773         bool cxsr;
 774         bool hpll_en;
 775         bool fbc_en;
 776 };
 777
 778 struct skl_ddb_entry {
 779         u16 start, end; /* in number of blocks, 'end' is exclusive */
 780 };
 781
 782 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
 783 {
 784         return entry->end - entry->start;
 785 }
 786
 787 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
 788                                        const struct skl_ddb_entry *e2)
 789 {
 790         if (e1->start == e2->start && e1->end == e2->end)
 791                 return true;
 792
 793         return false;
 794 }
 795
 796 struct i915_frontbuffer_tracking {
 797         spinlock_t lock;
 798
 799         /*
 800          * Tracking bits for delayed frontbuffer flushing du to gpu activity or
 801          * scheduled flips.
 802          */
 803         unsigned busy_bits;
 804         unsigned flip_bits;
 805 };
 806
 807 struct i915_virtual_gpu {
 808         struct mutex lock; /* serialises sending of g2v_notify command pkts */
 809         bool active;
 810         u32 caps;
 811 };
 812
 813 struct intel_cdclk_config {
 814         unsigned int cdclk, vco, ref, bypass;
 815         u8 voltage_level;
 816 };
 817
 818 struct i915_selftest_stash {
 819         atomic_t counter;
 820 };
 821
 822 struct drm_i915_private {
 823         struct drm_device drm;
 824
 825         /* FIXME: Device release actions should all be moved to drmm_ */
 826         bool do_release;
 827
 828         /* i915 device parameters */
 829         struct i915_params params;
 830
 831         const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
 832         struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
 833         struct intel_driver_caps caps;
 834
 835         /**
 836          * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
 837          * end of stolen which we can optionally use to create GEM objects
 838          * backed by stolen memory. Note that stolen_usable_size tells us
 839          * exactly how much of this we are actually allowed to use, given that
 840          * some portion of it is in fact reserved for use by hardware functions.
 841          */
 842         struct resource dsm;
 843         /**
 844          * Reseved portion of Data Stolen Memory
 845          */
 846         struct resource dsm_reserved;
 847
 848         /*
 849          * Stolen memory is segmented in hardware with different portions
 850          * offlimits to certain functions.
 851          *
 852          * The drm_mm is initialised to the total accessible range, as found
 853          * from the PCI config. On Broadwell+, this is further restricted to
 854          * avoid the first page! The upper end of stolen memory is reserved for
 855          * hardware functions and similarly removed from the accessible range.
 856          */
 857         resource_size_t stolen_usable_size;     /* Total size minus reserved ranges */
 858
 859         struct intel_uncore uncore;
 860         struct intel_uncore_mmio_debug mmio_debug;
 861
 862         struct i915_virtual_gpu vgpu;
 863
 864         struct intel_gvt *gvt;
 865
 866         struct intel_wopcm wopcm;
 867
 868         struct intel_csr csr;
 869
 870         struct intel_gmbus gmbus[GMBUS_NUM_PINS];
 871
 872         /** gmbus_mutex protects against concurrent usage of the single hw gmbus
 873          * controller on different i2c buses. */
 874         struct mutex gmbus_mutex;
 875
 876         /**
 877          * Base address of where the gmbus and gpio blocks are located (either
 878          * on PCH or on SoC for platforms without PCH).
 879          */
 880         u32 gpio_mmio_base;
 881
 882         u32 hsw_psr_mmio_adjust;
 883
 884         /* MMIO base address for MIPI regs */
 885         u32 mipi_mmio_base;
 886
 887         u32 pps_mmio_base;
 888
 889         wait_queue_head_t gmbus_wait_queue;
 890
 891         struct pci_dev *bridge_dev;
 892
 893         struct rb_root uabi_engines;
 894
 895         struct resource mch_res;
 896
 897         /* protects the irq masks */
 898         spinlock_t irq_lock;
 899
 900         bool display_irqs_enabled;
 901
 902         /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
 903         struct pm_qos_request pm_qos;
 904
 905         /* Sideband mailbox protection */
 906         struct mutex sb_lock;
 907         struct pm_qos_request sb_qos;
 908
 909         /** Cached value of IMR to avoid reads in updating the bitfield */
 910         union {
 911                 u32 irq_mask;
 912                 u32 de_irq_mask[I915_MAX_PIPES];
 913         };
 914         u32 pipestat_irq_mask[I915_MAX_PIPES];
 915
 916         struct i915_hotplug hotplug;
 917         struct intel_fbc fbc;
 918         struct i915_drrs drrs;
 919         struct intel_opregion opregion;
 920         struct intel_vbt_data vbt;
 921
 922         bool preserve_bios_swizzle;
 923
 924         /* overlay */
 925         struct intel_overlay *overlay;
 926
 927         /* backlight registers and fields in struct intel_panel */
 928         struct mutex backlight_lock;
 929
 930         /* protects panel power sequencer state */
 931         struct mutex pps_mutex;
 932
 933         unsigned int fsb_freq, mem_freq, is_ddr3;
 934         unsigned int skl_preferred_vco_freq;
 935         unsigned int max_cdclk_freq;
 936
 937         unsigned int max_dotclk_freq;
 938         unsigned int hpll_freq;
 939         unsigned int fdi_pll_freq;
 940         unsigned int czclk_freq;
 941
 942         struct {
 943                 /* The current hardware cdclk configuration */
 944                 struct intel_cdclk_config hw;
 945
 946                 /* cdclk, divider, and ratio table from bspec */
 947                 const struct intel_cdclk_vals *table;
 948
 949                 struct intel_global_obj obj;
 950         } cdclk;
 951
 952         struct {
 953                 /* The current hardware dbuf configuration */
 954                 u8 enabled_slices;
 955
 956                 struct intel_global_obj obj;
 957         } dbuf;
 958
 959         /**
 960          * wq - Driver workqueue for GEM.
 961          *
 962          * NOTE: Work items scheduled here are not allowed to grab any modeset
 963          * locks, for otherwise the flushing done in the pageflip code will
 964          * result in deadlocks.
 965          */
 966         struct workqueue_struct *wq;
 967
 968         /* ordered wq for modesets */
 969         struct workqueue_struct *modeset_wq;
 970         /* unbound hipri wq for page flips/plane updates */
 971         struct workqueue_struct *flip_wq;
 972
 973         /* Display functions */
 974         struct drm_i915_display_funcs display;
 975
 976         /* PCH chipset type */
 977         enum intel_pch pch_type;
 978         unsigned short pch_id;
 979
 980         unsigned long quirks;
 981
 982         struct drm_atomic_state *modeset_restore_state;
 983         struct drm_modeset_acquire_ctx reset_ctx;
 984
 985         struct i915_ggtt ggtt; /* VM representing the global address space */
 986
 987         struct i915_gem_mm mm;
 988         DECLARE_HASHTABLE(mm_structs, 7);
 989         spinlock_t mm_lock;
 990
 991         /* Kernel Modesetting */
 992
 993         struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
 994         struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
 995
 996         /**
 997          * dpll and cdclk state is protected by connection_mutex
 998          * dpll.lock serializes intel_{prepare,enable,disable}_shared_dpll.
 999          * Must be global rather than per dpll, because on some platforms plls
1000          * share registers.
1001          */
1002         struct {
1003                 struct mutex lock;
1004
1005                 int num_shared_dpll;
1006                 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1007                 const struct intel_dpll_mgr *mgr;
1008
1009                 struct {
1010                         int nssc;
1011                         int ssc;
1012                 } ref_clks;
1013         } dpll;
1014
1015         struct list_head global_obj_list;
1016
1017         /*
1018          * For reading active_pipes holding any crtc lock is
1019          * sufficient, for writing must hold all of them.
1020          */
1021         u8 active_pipes;
1022
1023         struct i915_wa_list gt_wa_list;
1024
1025         struct i915_frontbuffer_tracking fb_tracking;
1026
1027         struct intel_atomic_helper {
1028                 struct llist_head free_list;
1029                 struct work_struct free_work;
1030         } atomic_helper;
1031
1032         bool mchbar_need_disable;
1033
1034         struct intel_l3_parity l3_parity;
1035
1036         /*
1037          * HTI (aka HDPORT) state read during initial hw readout.  Most
1038          * platforms don't have HTI, so this will just stay 0.  Those that do
1039          * will use this later to figure out which PLLs and PHYs are unavailable
1040          * for driver usage.
1041          */
1042         u32 hti_state;
1043
1044         /*
1045          * edram size in MB.
1046          * Cannot be determined by PCIID. You must always read a register.
1047          */
1048         u32 edram_size_mb;
1049
1050         struct i915_power_domains power_domains;
1051
1052         struct i915_psr psr;
1053
1054         struct i915_gpu_error gpu_error;
1055
1056         struct drm_i915_gem_object *vlv_pctx;
1057
1058         /* list of fbdev register on this device */
1059         struct intel_fbdev *fbdev;
1060         struct work_struct fbdev_suspend_work;
1061
1062         struct drm_property *broadcast_rgb_property;
1063         struct drm_property *force_audio_property;
1064
1065         /* hda/i915 audio component */
1066         struct i915_audio_component *audio_component;
1067         bool audio_component_registered;
1068         /**
1069          * av_mutex - mutex for audio/video sync
1070          *
1071          */
1072         struct mutex av_mutex;
1073         int audio_power_refcount;
1074         u32 audio_freq_cntrl;
1075
1076         u32 fdi_rx_config;
1077
1078         /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1079         u32 chv_phy_control;
1080         /*
1081          * Shadows for CHV DPLL_MD regs to keep the state
1082          * checker somewhat working in the presence hardware
1083          * crappiness (can't read out DPLL_MD for pipes B & C).
1084          */
1085         u32 chv_dpll_md[I915_MAX_PIPES];
1086         u32 bxt_phy_grc;
1087
1088         u32 suspend_count;
1089         bool power_domains_suspended;
1090         struct i915_suspend_saved_registers regfile;
1091         struct vlv_s0ix_state *vlv_s0ix_state;
1092
1093         enum {
1094                 I915_SAGV_UNKNOWN = 0,
1095                 I915_SAGV_DISABLED,
1096                 I915_SAGV_ENABLED,
1097                 I915_SAGV_NOT_CONTROLLED
1098         } sagv_status;
1099
1100         u32 sagv_block_time_us;
1101
1102         struct {
1103                 /*
1104                  * Raw watermark latency values:
1105                  * in 0.1us units for WM0,
1106                  * in 0.5us units for WM1+.
1107                  */
1108                 /* primary */
1109                 u16 pri_latency[5];
1110                 /* sprite */
1111                 u16 spr_latency[5];
1112                 /* cursor */
1113                 u16 cur_latency[5];
1114                 /*
1115                  * Raw watermark memory latency values
1116                  * for SKL for all 8 levels
1117                  * in 1us units.
1118                  */
1119                 u16 skl_latency[8];
1120
1121                 /* current hardware state */
1122                 union {
1123                         struct ilk_wm_values hw;
1124                         struct vlv_wm_values vlv;
1125                         struct g4x_wm_values g4x;
1126                 };
1127
1128                 u8 max_level;
1129
1130                 /*
1131                  * Should be held around atomic WM register writing; also
1132                  * protects * intel_crtc->wm.active and
1133                  * crtc_state->wm.need_postvbl_update.
1134                  */
1135                 struct mutex wm_mutex;
1136
1137                 /*
1138                  * Set during HW readout of watermarks/DDB.  Some platforms
1139                  * need to know when we're still using BIOS-provided values
1140                  * (which we don't fully trust).
1141                  *
1142                  * FIXME get rid of this.
1143                  */
1144                 bool distrust_bios_wm;
1145         } wm;
1146
1147         struct dram_info {
1148                 bool valid;
1149                 bool is_16gb_dimm;
1150                 u8 num_channels;
1151                 u8 ranks;
1152                 u32 bandwidth_kbps;
1153                 bool symmetric_memory;
1154                 enum intel_dram_type {
1155                         INTEL_DRAM_UNKNOWN,
1156                         INTEL_DRAM_DDR3,
1157                         INTEL_DRAM_DDR4,
1158                         INTEL_DRAM_LPDDR3,
1159                         INTEL_DRAM_LPDDR4
1160                 } type;
1161         } dram_info;
1162
1163         struct intel_bw_info {
1164                 /* for each QGV point */
1165                 unsigned int deratedbw[I915_NUM_QGV_POINTS];
1166                 u8 num_qgv_points;
1167                 u8 num_planes;
1168         } max_bw[6];
1169
1170         struct intel_global_obj bw_obj;
1171
1172         struct intel_runtime_pm runtime_pm;
1173
1174         struct i915_perf perf;
1175
1176         /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1177         struct intel_gt gt;
1178
1179         struct {
1180                 struct i915_gem_contexts {
1181                         spinlock_t lock; /* locks list */
1182                         struct list_head list;
1183
1184                         struct llist_head free_list;
1185                         struct work_struct free_work;
1186                 } contexts;
1187
1188                 /*
1189                  * We replace the local file with a global mappings as the
1190                  * backing storage for the mmap is on the device and not
1191                  * on the struct file, and we do not want to prolong the
1192                  * lifetime of the local fd. To minimise the number of
1193                  * anonymous inodes we create, we use a global singleton to
1194                  * share the global mapping.
1195                  */
1196                 struct file *mmap_singleton;
1197         } gem;
1198
1199         u8 pch_ssc_use;
1200
1201         /* For i915gm/i945gm vblank irq workaround */
1202         u8 vblank_enabled;
1203
1204         /* perform PHY state sanity checks? */
1205         bool chv_phy_assert[2];
1206
1207         bool ipc_enabled;
1208
1209         /* Used to save the pipe-to-encoder mapping for audio */
1210         struct intel_encoder *av_enc_map[I915_MAX_PIPES];
1211
1212         /* necessary resource sharing with HDMI LPE audio driver. */
1213         struct {
1214                 struct platform_device *platdev;
1215                 int     irq;
1216         } lpe_audio;
1217
1218         struct i915_pmu pmu;
1219
1220         struct i915_hdcp_comp_master *hdcp_master;
1221         bool hdcp_comp_added;
1222
1223         /* Mutex to protect the above hdcp component related values. */
1224         struct mutex hdcp_comp_mutex;
1225
1226         I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
1227
1228         /*
1229          * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1230          * will be rejected. Instead look for a better place.
1231          */
1232 };
1233
1234 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1235 {
1236         return container_of(dev, struct drm_i915_private, drm);
1237 }
1238
1239 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
1240 {
1241         return dev_get_drvdata(kdev);
1242 }
1243
1244 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
1245 {
1246         return pci_get_drvdata(pdev);
1247 }
1248
1249 /* Simple iterator over all initialised engines */
1250 #define for_each_engine(engine__, dev_priv__, id__) \
1251         for ((id__) = 0; \
1252              (id__) < I915_NUM_ENGINES; \
1253              (id__)++) \
1254                 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
1255
1256 /* Iterator over subset of engines selected by mask */
1257 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
1258         for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
1259              (tmp__) ? \
1260              ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
1261              0;)
1262
1263 #define rb_to_uabi_engine(rb) \
1264         rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
1265
1266 #define for_each_uabi_engine(engine__, i915__) \
1267         for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
1268              (engine__); \
1269              (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
1270
1271 #define for_each_uabi_class_engine(engine__, class__, i915__) \
1272         for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \
1273              (engine__) && (engine__)->uabi_class == (class__); \
1274              (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
1275
1276 #define I915_GTT_OFFSET_NONE ((u32)-1)
1277
1278 /*
1279  * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1280  * considered to be the frontbuffer for the given plane interface-wise. This
1281  * doesn't mean that the hw necessarily already scans it out, but that any
1282  * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1283  *
1284  * We have one bit per pipe and per scanout plane type.
1285  */
1286 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
1287 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
1288         BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
1289         BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
1290         BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
1291 })
1292 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1293         BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1294 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1295         GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
1296                 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1297
1298 #define INTEL_INFO(dev_priv)    (&(dev_priv)->__info)
1299 #define RUNTIME_INFO(dev_priv)  (&(dev_priv)->__runtime)
1300 #define DRIVER_CAPS(dev_priv)   (&(dev_priv)->caps)
1301
1302 #define INTEL_GEN(dev_priv)     (INTEL_INFO(dev_priv)->gen)
1303 #define INTEL_DEVID(dev_priv)   (RUNTIME_INFO(dev_priv)->device_id)
1304
1305 #define REVID_FOREVER           0xff
1306 #define INTEL_REVID(dev_priv)   ((dev_priv)->drm.pdev->revision)
1307
1308 #define INTEL_GEN_MASK(s, e) ( \
1309         BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
1310         BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
1311         GENMASK((e) - 1, (s) - 1))
1312
1313 /* Returns true if Gen is in inclusive range [Start, End] */
1314 #define IS_GEN_RANGE(dev_priv, s, e) \
1315         (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
1316
1317 #define IS_GEN(dev_priv, n) \
1318         (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
1319          INTEL_INFO(dev_priv)->gen == (n))
1320
1321 #define HAS_DSB(dev_priv)       (INTEL_INFO(dev_priv)->display.has_dsb)
1322
1323 /*
1324  * Return true if revision is in range [since,until] inclusive.
1325  *
1326  * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
1327  */
1328 #define IS_REVID(p, since, until) \
1329         (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
1330
1331 static __always_inline unsigned int
1332 __platform_mask_index(const struct intel_runtime_info *info,
1333                       enum intel_platform p)
1334 {
1335         const unsigned int pbits =
1336                 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1337
1338         /* Expand the platform_mask array if this fails. */
1339         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
1340                      pbits * ARRAY_SIZE(info->platform_mask));
1341
1342         return p / pbits;
1343 }
1344
1345 static __always_inline unsigned int
1346 __platform_mask_bit(const struct intel_runtime_info *info,
1347                     enum intel_platform p)
1348 {
1349         const unsigned int pbits =
1350                 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1351
1352         return p % pbits + INTEL_SUBPLATFORM_BITS;
1353 }
1354
1355 static inline u32
1356 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
1357 {
1358         const unsigned int pi = __platform_mask_index(info, p);
1359
1360         return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS;
1361 }
1362
1363 static __always_inline bool
1364 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
1365 {
1366         const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1367         const unsigned int pi = __platform_mask_index(info, p);
1368         const unsigned int pb = __platform_mask_bit(info, p);
1369
1370         BUILD_BUG_ON(!__builtin_constant_p(p));
1371
1372         return info->platform_mask[pi] & BIT(pb);
1373 }
1374
1375 static __always_inline bool
1376 IS_SUBPLATFORM(const struct drm_i915_private *i915,
1377                enum intel_platform p, unsigned int s)
1378 {
1379         const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1380         const unsigned int pi = __platform_mask_index(info, p);
1381         const unsigned int pb = __platform_mask_bit(info, p);
1382         const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
1383         const u32 mask = info->platform_mask[pi];
1384
1385         BUILD_BUG_ON(!__builtin_constant_p(p));
1386         BUILD_BUG_ON(!__builtin_constant_p(s));
1387         BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
1388
1389         /* Shift and test on the MSB position so sign flag can be used. */
1390         return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
1391 }
1392
1393 #define IS_MOBILE(dev_priv)     (INTEL_INFO(dev_priv)->is_mobile)
1394 #define IS_DGFX(dev_priv)   (INTEL_INFO(dev_priv)->is_dgfx)
1395
1396 #define IS_I830(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I830)
1397 #define IS_I845G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I845G)
1398 #define IS_I85X(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I85X)
1399 #define IS_I865G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I865G)
1400 #define IS_I915G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I915G)
1401 #define IS_I915GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I915GM)
1402 #define IS_I945G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I945G)
1403 #define IS_I945GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I945GM)
1404 #define IS_I965G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I965G)
1405 #define IS_I965GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I965GM)
1406 #define IS_G45(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G45)
1407 #define IS_GM45(dev_priv)       IS_PLATFORM(dev_priv, INTEL_GM45)
1408 #define IS_G4X(dev_priv)        (IS_G45(dev_priv) || IS_GM45(dev_priv))
1409 #define IS_PINEVIEW(dev_priv)   IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
1410 #define IS_G33(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G33)
1411 #define IS_IRONLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
1412 #define IS_IRONLAKE_M(dev_priv) \
1413         (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
1414 #define IS_IVYBRIDGE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
1415 #define IS_IVB_GT1(dev_priv)    (IS_IVYBRIDGE(dev_priv) && \
1416                                  INTEL_INFO(dev_priv)->gt == 1)
1417 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
1418 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
1419 #define IS_HASWELL(dev_priv)    IS_PLATFORM(dev_priv, INTEL_HASWELL)
1420 #define IS_BROADWELL(dev_priv)  IS_PLATFORM(dev_priv, INTEL_BROADWELL)
1421 #define IS_SKYLAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
1422 #define IS_BROXTON(dev_priv)    IS_PLATFORM(dev_priv, INTEL_BROXTON)
1423 #define IS_KABYLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
1424 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
1425 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
1426 #define IS_COMETLAKE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
1427 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
1428 #define IS_ICELAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_ICELAKE)
1429 #define IS_ELKHARTLAKE(dev_priv)        IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
1430 #define IS_TIGERLAKE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
1431 #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
1432 #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
1433 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
1434                                     (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
1435 #define IS_BDW_ULT(dev_priv) \
1436         IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
1437 #define IS_BDW_ULX(dev_priv) \
1438         IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
1439 #define IS_BDW_GT3(dev_priv)    (IS_BROADWELL(dev_priv) && \
1440                                  INTEL_INFO(dev_priv)->gt == 3)
1441 #define IS_HSW_ULT(dev_priv) \
1442         IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
1443 #define IS_HSW_GT3(dev_priv)    (IS_HASWELL(dev_priv) && \
1444                                  INTEL_INFO(dev_priv)->gt == 3)
1445 #define IS_HSW_GT1(dev_priv)    (IS_HASWELL(dev_priv) && \
1446                                  INTEL_INFO(dev_priv)->gt == 1)
1447 /* ULX machines are also considered ULT. */
1448 #define IS_HSW_ULX(dev_priv) \
1449         IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
1450 #define IS_SKL_ULT(dev_priv) \
1451         IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
1452 #define IS_SKL_ULX(dev_priv) \
1453         IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
1454 #define IS_KBL_ULT(dev_priv) \
1455         IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
1456 #define IS_KBL_ULX(dev_priv) \
1457         IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
1458 #define IS_SKL_GT2(dev_priv)    (IS_SKYLAKE(dev_priv) && \
1459                                  INTEL_INFO(dev_priv)->gt == 2)
1460 #define IS_SKL_GT3(dev_priv)    (IS_SKYLAKE(dev_priv) && \
1461                                  INTEL_INFO(dev_priv)->gt == 3)
1462 #define IS_SKL_GT4(dev_priv)    (IS_SKYLAKE(dev_priv) && \
1463                                  INTEL_INFO(dev_priv)->gt == 4)
1464 #define IS_KBL_GT2(dev_priv)    (IS_KABYLAKE(dev_priv) && \
1465                                  INTEL_INFO(dev_priv)->gt == 2)
1466 #define IS_KBL_GT3(dev_priv)    (IS_KABYLAKE(dev_priv) && \
1467                                  INTEL_INFO(dev_priv)->gt == 3)
1468 #define IS_CFL_ULT(dev_priv) \
1469         IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
1470 #define IS_CFL_ULX(dev_priv) \
1471         IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
1472 #define IS_CFL_GT2(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
1473                                  INTEL_INFO(dev_priv)->gt == 2)
1474 #define IS_CFL_GT3(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
1475                                  INTEL_INFO(dev_priv)->gt == 3)
1476
1477 #define IS_CML_ULT(dev_priv) \
1478         IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
1479 #define IS_CML_ULX(dev_priv) \
1480         IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
1481 #define IS_CML_GT2(dev_priv)    (IS_COMETLAKE(dev_priv) && \
1482                                  INTEL_INFO(dev_priv)->gt == 2)
1483
1484 #define IS_CNL_WITH_PORT_F(dev_priv) \
1485         IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
1486 #define IS_ICL_WITH_PORT_F(dev_priv) \
1487         IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
1488
1489 #define IS_TGL_U(dev_priv) \
1490         IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULT)
1491
1492 #define IS_TGL_Y(dev_priv) \
1493         IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULX)
1494
1495 #define SKL_REVID_A0            0x0
1496 #define SKL_REVID_B0            0x1
1497 #define SKL_REVID_C0            0x2
1498 #define SKL_REVID_D0            0x3
1499 #define SKL_REVID_E0            0x4
1500 #define SKL_REVID_F0            0x5
1501 #define SKL_REVID_G0            0x6
1502 #define SKL_REVID_H0            0x7
1503
1504 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
1505
1506 #define BXT_REVID_A0            0x0
1507 #define BXT_REVID_A1            0x1
1508 #define BXT_REVID_B0            0x3
1509 #define BXT_REVID_B_LAST        0x8
1510 #define BXT_REVID_C0            0x9
1511
1512 #define IS_BXT_REVID(dev_priv, since, until) \
1513         (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
1514
1515 enum {
1516         KBL_REVID_A0,
1517         KBL_REVID_B0,
1518         KBL_REVID_B1,
1519         KBL_REVID_C0,
1520         KBL_REVID_D0,
1521         KBL_REVID_D1,
1522         KBL_REVID_E0,
1523         KBL_REVID_F0,
1524         KBL_REVID_G0,
1525 };
1526
1527 struct i915_rev_steppings {
1528         u8 gt_stepping;
1529         u8 disp_stepping;
1530 };
1531
1532 /* Defined in intel_workarounds.c */
1533 extern const struct i915_rev_steppings kbl_revids[];
1534
1535 #define IS_KBL_GT_REVID(dev_priv, since, until) \
1536         (IS_KABYLAKE(dev_priv) && \
1537          kbl_revids[INTEL_REVID(dev_priv)].gt_stepping >= since && \
1538          kbl_revids[INTEL_REVID(dev_priv)].gt_stepping <= until)
1539 #define IS_KBL_DISP_REVID(dev_priv, since, until) \
1540         (IS_KABYLAKE(dev_priv) && \
1541          kbl_revids[INTEL_REVID(dev_priv)].disp_stepping >= since && \
1542          kbl_revids[INTEL_REVID(dev_priv)].disp_stepping <= until)
1543
1544 #define GLK_REVID_A0            0x0
1545 #define GLK_REVID_A1            0x1
1546 #define GLK_REVID_A2            0x2
1547 #define GLK_REVID_B0            0x3
1548
1549 #define IS_GLK_REVID(dev_priv, since, until) \
1550         (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
1551
1552 #define CNL_REVID_A0            0x0
1553 #define CNL_REVID_B0            0x1
1554 #define CNL_REVID_C0            0x2
1555
1556 #define IS_CNL_REVID(p, since, until) \
1557         (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
1558
1559 #define ICL_REVID_A0            0x0
1560 #define ICL_REVID_A2            0x1
1561 #define ICL_REVID_B0            0x3
1562 #define ICL_REVID_B2            0x4
1563 #define ICL_REVID_C0            0x5
1564
1565 #define IS_ICL_REVID(p, since, until) \
1566         (IS_ICELAKE(p) && IS_REVID(p, since, until))
1567
1568 #define EHL_REVID_A0            0x0
1569
1570 #define IS_EHL_REVID(p, since, until) \
1571         (IS_ELKHARTLAKE(p) && IS_REVID(p, since, until))
1572
1573 enum {
1574         TGL_REVID_A0,
1575         TGL_REVID_B0,
1576         TGL_REVID_B1,
1577         TGL_REVID_C0,
1578         TGL_REVID_D0,
1579 };
1580
1581 extern const struct i915_rev_steppings tgl_uy_revids[];
1582 extern const struct i915_rev_steppings tgl_revids[];
1583
1584 static inline const struct i915_rev_steppings *
1585 tgl_revids_get(struct drm_i915_private *dev_priv)
1586 {
1587         if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv))
1588                 return tgl_uy_revids;
1589         else
1590                 return tgl_revids;
1591 }
1592
1593 #define IS_TGL_DISP_REVID(p, since, until) \
1594         (IS_TIGERLAKE(p) && \
1595          tgl_revids_get(p)->disp_stepping >= (since) && \
1596          tgl_revids_get(p)->disp_stepping <= (until))
1597
1598 #define IS_TGL_UY_GT_REVID(p, since, until) \
1599         ((IS_TGL_U(p) || IS_TGL_Y(p)) && \
1600          tgl_uy_revids->gt_stepping >= (since) && \
1601          tgl_uy_revids->gt_stepping <= (until))
1602
1603 #define IS_TGL_GT_REVID(p, since, until) \
1604         (IS_TIGERLAKE(p) && \
1605          !(IS_TGL_U(p) || IS_TGL_Y(p)) && \
1606          tgl_revids->gt_stepping >= (since) && \
1607          tgl_revids->gt_stepping <= (until))
1608
1609 #define RKL_REVID_A0            0x0
1610 #define RKL_REVID_B0            0x1
1611 #define RKL_REVID_C0            0x4
1612
1613 #define IS_RKL_REVID(p, since, until) \
1614         (IS_ROCKETLAKE(p) && IS_REVID(p, since, until))
1615
1616 #define DG1_REVID_A0            0x0
1617 #define DG1_REVID_B0            0x1
1618
1619 #define IS_DG1_REVID(p, since, until) \
1620         (IS_DG1(p) && IS_REVID(p, since, until))
1621
1622 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
1623 #define IS_GEN9_LP(dev_priv)    (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
1624 #define IS_GEN9_BC(dev_priv)    (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
1625
1626 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
1627 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
1628
1629 #define ENGINE_INSTANCES_MASK(gt, first, count) ({              \
1630         unsigned int first__ = (first);                                 \
1631         unsigned int count__ = (count);                                 \
1632         ((gt)->info.engine_mask &                                               \
1633          GENMASK(first__ + count__ - 1, first__)) >> first__;           \
1634 })
1635 #define VDBOX_MASK(gt) \
1636         ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
1637 #define VEBOX_MASK(gt) \
1638         ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
1639
1640 /*
1641  * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
1642  * All later gens can run the final buffer from the ppgtt
1643  */
1644 #define CMDPARSER_USES_GGTT(dev_priv) IS_GEN(dev_priv, 7)
1645
1646 #define HAS_LLC(dev_priv)       (INTEL_INFO(dev_priv)->has_llc)
1647 #define HAS_SNOOP(dev_priv)     (INTEL_INFO(dev_priv)->has_snoop)
1648 #define HAS_EDRAM(dev_priv)     ((dev_priv)->edram_size_mb)
1649 #define HAS_SECURE_BATCHES(dev_priv) (INTEL_GEN(dev_priv) < 6)
1650 #define HAS_WT(dev_priv)        ((IS_HASWELL(dev_priv) || \
1651                                  IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
1652
1653 #define HWS_NEEDS_PHYSICAL(dev_priv)    (INTEL_INFO(dev_priv)->hws_needs_physical)
1654
1655 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
1656                 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
1657 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
1658                 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
1659 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
1660                 (INTEL_INFO(dev_priv)->has_logical_ring_preemption)
1661
1662 #define HAS_MASTER_UNIT_IRQ(dev_priv) (INTEL_INFO(dev_priv)->has_master_unit_irq)
1663
1664 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
1665
1666 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
1667 #define HAS_PPGTT(dev_priv) \
1668         (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
1669 #define HAS_FULL_PPGTT(dev_priv) \
1670         (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
1671
1672 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
1673         GEM_BUG_ON((sizes) == 0); \
1674         ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
1675 })
1676
1677 #define HAS_OVERLAY(dev_priv)            (INTEL_INFO(dev_priv)->display.has_overlay)
1678 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
1679                 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
1680
1681 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1682 #define HAS_BROKEN_CS_TLB(dev_priv)     (IS_I830(dev_priv) || IS_I845G(dev_priv))
1683
1684 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv)   \
1685         (IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9))
1686
1687 /* WaRsDisableCoarsePowerGating:skl,cnl */
1688 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv)                    \
1689         (IS_CANNONLAKE(dev_priv) ||                                     \
1690          IS_SKL_GT3(dev_priv) ||                                        \
1691          IS_SKL_GT4(dev_priv))
1692
1693 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
1694 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
1695                                         IS_GEMINILAKE(dev_priv) || \
1696                                         IS_KABYLAKE(dev_priv))
1697
1698 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1699  * rows, which changed the alignment requirements and fence programming.
1700  */
1701 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
1702                                          !(IS_I915G(dev_priv) || \
1703                                          IS_I915GM(dev_priv)))
1704 #define SUPPORTS_TV(dev_priv)           (INTEL_INFO(dev_priv)->display.supports_tv)
1705 #define I915_HAS_HOTPLUG(dev_priv)      (INTEL_INFO(dev_priv)->display.has_hotplug)
1706
1707 #define HAS_FW_BLC(dev_priv)    (INTEL_GEN(dev_priv) > 2)
1708 #define HAS_FBC(dev_priv)       (INTEL_INFO(dev_priv)->display.has_fbc)
1709 #define HAS_CUR_FBC(dev_priv)   (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)
1710
1711 #define HAS_IPS(dev_priv)       (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
1712
1713 #define HAS_DP_MST(dev_priv)    (INTEL_INFO(dev_priv)->display.has_dp_mst)
1714
1715 #define HAS_DDI(dev_priv)                (INTEL_INFO(dev_priv)->display.has_ddi)
1716 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
1717 #define HAS_PSR(dev_priv)                (INTEL_INFO(dev_priv)->display.has_psr)
1718 #define HAS_PSR_HW_TRACKING(dev_priv) \
1719         (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
1720 #define HAS_PSR2_SEL_FETCH(dev_priv)     (INTEL_GEN(dev_priv) >= 12)
1721 #define HAS_TRANSCODER(dev_priv, trans)  ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
1722
1723 #define HAS_RC6(dev_priv)                (INTEL_INFO(dev_priv)->has_rc6)
1724 #define HAS_RC6p(dev_priv)               (INTEL_INFO(dev_priv)->has_rc6p)
1725 #define HAS_RC6pp(dev_priv)              (false) /* HW was never validated */
1726
1727 #define HAS_RPS(dev_priv)       (INTEL_INFO(dev_priv)->has_rps)
1728
1729 #define HAS_CSR(dev_priv)       (INTEL_INFO(dev_priv)->display.has_csr)
1730
1731 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
1732 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
1733
1734 #define HAS_IPC(dev_priv)                (INTEL_INFO(dev_priv)->display.has_ipc)
1735
1736 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
1737 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
1738
1739 #define HAS_GT_UC(dev_priv)     (INTEL_INFO(dev_priv)->has_gt_uc)
1740
1741 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
1742
1743 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)     (INTEL_INFO(dev_priv)->has_global_mocs)
1744
1745
1746 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
1747
1748 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
1749
1750 /* DPF == dynamic parity feature */
1751 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
1752 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
1753                                  2 : HAS_L3_DPF(dev_priv))
1754
1755 #define GT_FREQUENCY_MULTIPLIER 50
1756 #define GEN9_FREQ_SCALER 3
1757
1758 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
1759
1760 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
1761
1762 /* Only valid when HAS_DISPLAY() is true */
1763 #define INTEL_DISPLAY_ENABLED(dev_priv) \
1764         (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display)
1765
1766 static inline bool intel_vtd_active(void)
1767 {
1768 #ifdef CONFIG_INTEL_IOMMU
1769         if (intel_iommu_gfx_mapped)
1770                 return true;
1771 #endif
1772         return false;
1773 }
1774
1775 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
1776 {
1777         return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
1778 }
1779
1780 static inline bool
1781 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
1782 {
1783         return IS_BROXTON(dev_priv) && intel_vtd_active();
1784 }
1785
1786 /* i915_drv.c */
1787 extern const struct dev_pm_ops i915_pm_ops;
1788
1789 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
1790 void i915_driver_remove(struct drm_i915_private *i915);
1791
1792 int i915_resume_switcheroo(struct drm_i915_private *i915);
1793 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state);
1794
1795 int i915_getparam_ioctl(struct drm_device *dev, void *data,
1796                         struct drm_file *file_priv);
1797
1798 /* i915_gem.c */
1799 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
1800 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
1801 void i915_gem_init_early(struct drm_i915_private *dev_priv);
1802 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
1803 int i915_gem_freeze(struct drm_i915_private *dev_priv);
1804 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
1805
1806 struct intel_memory_region *i915_gem_shmem_setup(struct drm_i915_private *i915);
1807
1808 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
1809 {
1810         /*
1811          * A single pass should suffice to release all the freed objects (along
1812          * most call paths) , but be a little more paranoid in that freeing
1813          * the objects does take a little amount of time, during which the rcu
1814          * callbacks could have added new objects into the freed list, and
1815          * armed the work again.
1816          */
1817         while (atomic_read(&i915->mm.free_count)) {
1818                 flush_work(&i915->mm.free_work);
1819                 rcu_barrier();
1820         }
1821 }
1822
1823 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
1824 {
1825         /*
1826          * Similar to objects above (see i915_gem_drain_freed-objects), in
1827          * general we have workers that are armed by RCU and then rearm
1828          * themselves in their callbacks. To be paranoid, we need to
1829          * drain the workqueue a second time after waiting for the RCU
1830          * grace period so that we catch work queued via RCU from the first
1831          * pass. As neither drain_workqueue() nor flush_workqueue() report
1832          * a result, we make an assumption that we only don't require more
1833          * than 3 passes to catch all _recursive_ RCU delayed work.
1834          *
1835          */
1836         int pass = 3;
1837         do {
1838                 flush_workqueue(i915->wq);
1839                 rcu_barrier();
1840                 i915_gem_drain_freed_objects(i915);
1841         } while (--pass);
1842         drain_workqueue(i915->wq);
1843 }
1844
1845 struct i915_vma * __must_check
1846 i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj,
1847                             struct i915_gem_ww_ctx *ww,
1848                             const struct i915_ggtt_view *view,
1849                             u64 size, u64 alignment, u64 flags);
1850
1851 static inline struct i915_vma * __must_check
1852 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
1853                          const struct i915_ggtt_view *view,
1854                          u64 size, u64 alignment, u64 flags)
1855 {
1856         return i915_gem_object_ggtt_pin_ww(obj, NULL, view, size, alignment, flags);
1857 }
1858
1859 int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
1860                            unsigned long flags);
1861 #define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0)
1862 #define I915_GEM_OBJECT_UNBIND_BARRIER BIT(1)
1863 #define I915_GEM_OBJECT_UNBIND_TEST BIT(2)
1864
1865 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
1866
1867 int i915_gem_dumb_create(struct drm_file *file_priv,
1868                          struct drm_device *dev,
1869                          struct drm_mode_create_dumb *args);
1870
1871 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
1872
1873 static inline u32 i915_reset_count(struct i915_gpu_error *error)
1874 {
1875         return atomic_read(&error->reset_count);
1876 }
1877
1878 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
1879                                           const struct intel_engine_cs *engine)
1880 {
1881         return atomic_read(&error->reset_engine_count[engine->uabi_class]);
1882 }
1883
1884 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
1885 void i915_gem_driver_register(struct drm_i915_private *i915);
1886 void i915_gem_driver_unregister(struct drm_i915_private *i915);
1887 void i915_gem_driver_remove(struct drm_i915_private *dev_priv);
1888 void i915_gem_driver_release(struct drm_i915_private *dev_priv);
1889 void i915_gem_suspend(struct drm_i915_private *dev_priv);
1890 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
1891 void i915_gem_resume(struct drm_i915_private *dev_priv);
1892
1893 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
1894
1895 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1896                                     enum i915_cache_level cache_level);
1897
1898 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1899                                 struct dma_buf *dma_buf);
1900
1901 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags);
1902
1903 static inline struct i915_gem_context *
1904 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
1905 {
1906         return xa_load(&file_priv->context_xa, id);
1907 }
1908
1909 static inline struct i915_gem_context *
1910 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
1911 {
1912         struct i915_gem_context *ctx;
1913
1914         rcu_read_lock();
1915         ctx = __i915_gem_context_lookup_rcu(file_priv, id);
1916         if (ctx && !kref_get_unless_zero(&ctx->ref))
1917                 ctx = NULL;
1918         rcu_read_unlock();
1919
1920         return ctx;
1921 }
1922
1923 /* i915_gem_evict.c */
1924 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
1925                                           u64 min_size, u64 alignment,
1926                                           unsigned long color,
1927                                           u64 start, u64 end,
1928                                           unsigned flags);
1929 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
1930                                          struct drm_mm_node *node,
1931                                          unsigned int flags);
1932 int i915_gem_evict_vm(struct i915_address_space *vm);
1933
1934 /* i915_gem_internal.c */
1935 struct drm_i915_gem_object *
1936 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
1937                                 phys_addr_t size);
1938
1939 /* i915_gem_tiling.c */
1940 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1941 {
1942         struct drm_i915_private *i915 = to_i915(obj->base.dev);
1943
1944         return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1945                 i915_gem_object_is_tiled(obj);
1946 }
1947
1948 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
1949                         unsigned int tiling, unsigned int stride);
1950 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
1951                              unsigned int tiling, unsigned int stride);
1952
1953 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
1954
1955 /* i915_cmd_parser.c */
1956 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
1957 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
1958 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
1959 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
1960                             struct i915_vma *batch,
1961                             u32 batch_offset,
1962                             u32 batch_length,
1963                             struct i915_vma *shadow,
1964                             bool trampoline);
1965 #define I915_CMD_PARSER_TRAMPOLINE_SIZE 8
1966
1967 /* intel_device_info.c */
1968 static inline struct intel_device_info *
1969 mkwrite_device_info(struct drm_i915_private *dev_priv)
1970 {
1971         return (struct intel_device_info *)INTEL_INFO(dev_priv);
1972 }
1973
1974 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1975                         struct drm_file *file);
1976
1977 #define __I915_REG_OP(op__, dev_priv__, ...) \
1978         intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
1979
1980 #define I915_READ(reg__)         __I915_REG_OP(read, dev_priv, (reg__))
1981 #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
1982
1983 #define POSTING_READ(reg__)     __I915_REG_OP(posting_read, dev_priv, (reg__))
1984
1985 /* These are untraced mmio-accessors that are only valid to be used inside
1986  * critical sections, such as inside IRQ handlers, where forcewake is explicitly
1987  * controlled.
1988  *
1989  * Think twice, and think again, before using these.
1990  *
1991  * As an example, these accessors can possibly be used between:
1992  *
1993  * spin_lock_irq(&dev_priv->uncore.lock);
1994  * intel_uncore_forcewake_get__locked();
1995  *
1996  * and
1997  *
1998  * intel_uncore_forcewake_put__locked();
1999  * spin_unlock_irq(&dev_priv->uncore.lock);
2000  *
2001  *
2002  * Note: some registers may not need forcewake held, so
2003  * intel_uncore_forcewake_{get,put} can be omitted, see
2004  * intel_uncore_forcewake_for_reg().
2005  *
2006  * Certain architectures will die if the same cacheline is concurrently accessed
2007  * by different clients (e.g. on Ivybridge). Access to registers should
2008  * therefore generally be serialised, by either the dev_priv->uncore.lock or
2009  * a more localised lock guarding all access to that bank of registers.
2010  */
2011 #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__))
2012 #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__))
2013
2014 /* i915_mm.c */
2015 int remap_io_mapping(struct vm_area_struct *vma,
2016                      unsigned long addr, unsigned long pfn, unsigned long size,
2017                      struct io_mapping *iomap);
2018 int remap_io_sg(struct vm_area_struct *vma,
2019                 unsigned long addr, unsigned long size,
2020                 struct scatterlist *sgl, resource_size_t iobase);
2021
2022 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
2023 {
2024         if (INTEL_GEN(i915) >= 10)
2025                 return CNL_HWS_CSB_WRITE_INDEX;
2026         else
2027                 return I915_HWS_CSB_WRITE_INDEX;
2028 }
2029
2030 static inline enum i915_map_type
2031 i915_coherent_map_type(struct drm_i915_private *i915)
2032 {
2033         return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
2034 }
2035
2036 static inline u64 i915_cs_timestamp_ns_to_ticks(struct drm_i915_private *i915, u64 val)
2037 {
2038         return DIV_ROUND_UP_ULL(val * RUNTIME_INFO(i915)->cs_timestamp_frequency_hz,
2039                                 1000000000);
2040 }
2041
2042 static inline u64 i915_cs_timestamp_ticks_to_ns(struct drm_i915_private *i915, u64 val)
2043 {
2044         return div_u64(val * 1000000000,
2045                        RUNTIME_INFO(i915)->cs_timestamp_frequency_hz);
2046 }
2047
2048 #endif