1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <asm/hypervisor.h>
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <linux/backlight.h>
42 #include <linux/hash.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/mm_types.h>
46 #include <linux/perf_event.h>
47 #include <linux/pm_qos.h>
48 #include <linux/dma-resv.h>
49 #include <linux/shmem_fs.h>
50 #include <linux/stackdepot.h>
51 #include <linux/xarray.h>
53 #include <drm/intel-gtt.h>
54 #include <drm/drm_gem.h>
55 #include <drm/drm_auth.h>
56 #include <drm/drm_cache.h>
57 #include <drm/drm_util.h>
58 #include <drm/drm_dsc.h>
59 #include <drm/drm_atomic.h>
60 #include <drm/drm_connector.h>
61 #include <drm/i915_mei_hdcp_interface.h>
62 #include <drm/ttm/ttm_device.h>
64 #include "i915_params.h"
66 #include "i915_utils.h"
68 #include "display/intel_bios.h"
69 #include "display/intel_display.h"
70 #include "display/intel_display_power.h"
71 #include "display/intel_dmc.h"
72 #include "display/intel_dpll_mgr.h"
73 #include "display/intel_dsb.h"
74 #include "display/intel_frontbuffer.h"
75 #include "display/intel_global_state.h"
76 #include "display/intel_gmbus.h"
77 #include "display/intel_opregion.h"
79 #include "gem/i915_gem_context_types.h"
80 #include "gem/i915_gem_shrinker.h"
81 #include "gem/i915_gem_stolen.h"
82 #include "gem/i915_gem_lmem.h"
84 #include "gt/intel_engine.h"
85 #include "gt/intel_gt_types.h"
86 #include "gt/intel_region_lmem.h"
87 #include "gt/intel_workarounds.h"
88 #include "gt/uc/intel_uc.h"
90 #include "intel_device_info.h"
91 #include "intel_memory_region.h"
92 #include "intel_pch.h"
93 #include "intel_runtime_pm.h"
94 #include "intel_step.h"
95 #include "intel_uncore.h"
96 #include "intel_wakeref.h"
97 #include "intel_wopcm.h"
100 #include "i915_gem_gtt.h"
101 #include "i915_gpu_error.h"
102 #include "i915_perf_types.h"
103 #include "i915_request.h"
104 #include "i915_scheduler.h"
105 #include "gt/intel_timeline.h"
106 #include "i915_vma.h"
107 #include "i915_irq.h"
110 /* General customization:
113 #define DRIVER_NAME "i915"
114 #define DRIVER_DESC "Intel Graphics"
115 #define DRIVER_DATE "20201103"
116 #define DRIVER_TIMESTAMP 1604406085
118 struct drm_i915_gem_object;
122 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
141 #define for_each_hpd_pin(__pin) \
142 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
144 /* Threshold == 5 for long IRQs, 50 for short */
145 #define HPD_STORM_DEFAULT_THRESHOLD 50
147 struct i915_hotplug {
148 struct delayed_work hotplug_work;
150 const u32 *hpd, *pch_hpd;
153 unsigned long last_jiffies;
158 HPD_MARK_DISABLED = 2
160 } stats[HPD_NUM_PINS];
163 struct delayed_work reenable_work;
167 struct work_struct dig_port_work;
169 struct work_struct poll_init_work;
172 unsigned int hpd_storm_threshold;
173 /* Whether or not to count short HPD IRQs in HPD storms */
174 u8 hpd_short_storm_enabled;
177 * if we get a HPD irq from DP and a HPD irq from non-DP
178 * the non-DP HPD could block the workqueue on a mode config
179 * mutex getting, that userspace may have taken. However
180 * userspace is waiting on the DP workqueue to run which is
181 * blocked behind the non-DP one.
183 struct workqueue_struct *dp_wq;
186 #define I915_GEM_GPU_DOMAINS \
187 (I915_GEM_DOMAIN_RENDER | \
188 I915_GEM_DOMAIN_SAMPLER | \
189 I915_GEM_DOMAIN_COMMAND | \
190 I915_GEM_DOMAIN_INSTRUCTION | \
191 I915_GEM_DOMAIN_VERTEX)
193 struct drm_i915_private;
194 struct i915_mm_struct;
195 struct i915_mmu_object;
197 struct drm_i915_file_private {
198 struct drm_i915_private *dev_priv;
201 struct drm_file *file;
205 /** @proto_context_lock: Guards all struct i915_gem_proto_context
208 * This not only guards @proto_context_xa, but is always held
209 * whenever we manipulate any struct i915_gem_proto_context,
210 * including finalizing it on first actual use of the GEM context.
212 * See i915_gem_proto_context.
214 struct mutex proto_context_lock;
216 /** @proto_context_xa: xarray of struct i915_gem_proto_context
218 * Historically, the context uAPI allowed for two methods of
219 * setting context parameters: SET_CONTEXT_PARAM and
220 * CONTEXT_CREATE_EXT_SETPARAM. The former is allowed to be called
221 * at any time while the later happens as part of
222 * GEM_CONTEXT_CREATE. Everything settable via one was settable
223 * via the other. While some params are fairly simple and setting
224 * them on a live context is harmless such as the context priority,
225 * others are far trickier such as the VM or the set of engines.
226 * In order to swap out the VM, for instance, we have to delay
227 * until all current in-flight work is complete, swap in the new
228 * VM, and then continue. This leads to a plethora of potential
229 * race conditions we'd really rather avoid.
231 * We have since disallowed setting these more complex parameters
232 * on active contexts. This works by delaying the creation of the
233 * actual context until after the client is done configuring it
234 * with SET_CONTEXT_PARAM. From the perspective of the client, it
235 * has the same u32 context ID the whole time. From the
236 * perspective of i915, however, it's a struct i915_gem_proto_context
237 * right up until the point where we attempt to do something which
238 * the proto-context can't handle. Then the struct i915_gem_context
241 * This is accomplished via a little xarray dance. When
242 * GEM_CONTEXT_CREATE is called, we create a struct
243 * i915_gem_proto_context, reserve a slot in @context_xa but leave
244 * it NULL, and place the proto-context in the corresponding slot
245 * in @proto_context_xa. Then, in i915_gem_context_lookup(), we
246 * first check @context_xa. If it's there, we return the struct
247 * i915_gem_context and we're done. If it's not, we look in
248 * @proto_context_xa and, if we find it there, we create the actual
249 * context and kill the proto-context.
251 * In order for this dance to work properly, everything which ever
252 * touches a struct i915_gem_proto_context is guarded by
253 * @proto_context_lock, including context creation. Yes, this
254 * means context creation now takes a giant global lock but it
255 * can't really be helped and that should never be on any driver's
258 struct xarray proto_context_xa;
260 /** @context_xa: xarray of fully created i915_gem_context
262 * Write access to this xarray is guarded by @proto_context_lock.
263 * Otherwise, writers may race with finalize_create_context_locked().
265 * See @proto_context_xa.
267 struct xarray context_xa;
270 unsigned int bsd_engine;
273 * Every context ban increments per client ban score. Also
274 * hangs in short succession increments ban score. If ban threshold
275 * is reached, client is considered banned and submitting more work
276 * will fail. This is a stop gap measure to limit the badly behaving
277 * clients access to gpu. Note that unbannable contexts never increment
278 * the client ban score.
280 #define I915_CLIENT_SCORE_HANG_FAST 1
281 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
282 #define I915_CLIENT_SCORE_CONTEXT_BAN 3
283 #define I915_CLIENT_SCORE_BANNED 9
284 /** ban_score: Accumulated score of all ctx bans and fast hangs. */
286 unsigned long hang_timestamp;
289 /* Interface history:
292 * 1.2: Add Power Management
293 * 1.3: Add vblank support
294 * 1.4: Fix cmdbuffer path, add heap destroy
295 * 1.5: Add vblank pipe configuration
296 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
297 * - Support vertical blank on secondary display pipe
299 #define DRIVER_MAJOR 1
300 #define DRIVER_MINOR 6
301 #define DRIVER_PATCHLEVEL 0
303 struct intel_overlay;
304 struct intel_overlay_error_state;
306 struct sdvo_device_mapping {
315 struct intel_connector;
316 struct intel_encoder;
317 struct intel_atomic_state;
318 struct intel_cdclk_config;
319 struct intel_cdclk_state;
320 struct intel_cdclk_vals;
321 struct intel_initial_plane_config;
326 struct drm_i915_display_funcs {
327 void (*get_cdclk)(struct drm_i915_private *dev_priv,
328 struct intel_cdclk_config *cdclk_config);
329 void (*set_cdclk)(struct drm_i915_private *dev_priv,
330 const struct intel_cdclk_config *cdclk_config,
332 int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
333 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
334 enum i9xx_plane_id i9xx_plane);
335 int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
336 int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
337 void (*initial_watermarks)(struct intel_atomic_state *state,
338 struct intel_crtc *crtc);
339 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
340 struct intel_crtc *crtc);
341 void (*optimize_watermarks)(struct intel_atomic_state *state,
342 struct intel_crtc *crtc);
343 int (*compute_global_watermarks)(struct intel_atomic_state *state);
344 void (*update_wm)(struct intel_crtc *crtc);
345 int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
346 u8 (*calc_voltage_level)(int cdclk);
347 /* Returns the active state of the crtc, and if the crtc is active,
348 * fills out the pipe-config with the hw state. */
349 bool (*get_pipe_config)(struct intel_crtc *,
350 struct intel_crtc_state *);
351 void (*get_initial_plane_config)(struct intel_crtc *,
352 struct intel_initial_plane_config *);
353 int (*crtc_compute_clock)(struct intel_crtc *crtc,
354 struct intel_crtc_state *crtc_state);
355 void (*crtc_enable)(struct intel_atomic_state *state,
356 struct intel_crtc *crtc);
357 void (*crtc_disable)(struct intel_atomic_state *state,
358 struct intel_crtc *crtc);
359 void (*commit_modeset_enables)(struct intel_atomic_state *state);
360 void (*commit_modeset_disables)(struct intel_atomic_state *state);
361 void (*audio_codec_enable)(struct intel_encoder *encoder,
362 const struct intel_crtc_state *crtc_state,
363 const struct drm_connector_state *conn_state);
364 void (*audio_codec_disable)(struct intel_encoder *encoder,
365 const struct intel_crtc_state *old_crtc_state,
366 const struct drm_connector_state *old_conn_state);
367 void (*fdi_link_train)(struct intel_crtc *crtc,
368 const struct intel_crtc_state *crtc_state);
369 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
370 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
371 /* clock updates for mode set */
373 /* render clock increase/decrease */
374 /* display clock increase/decrease */
375 /* pll clock increase/decrease */
377 int (*color_check)(struct intel_crtc_state *crtc_state);
379 * Program double buffered color management registers during
380 * vblank evasion. The registers should then latch during the
381 * next vblank start, alongside any other double buffered registers
382 * involved with the same commit.
384 void (*color_commit)(const struct intel_crtc_state *crtc_state);
386 * Load LUTs (and other single buffered color management
387 * registers). Will (hopefully) be called during the vblank
388 * following the latching of any double buffered registers
389 * involved with the same commit.
391 void (*load_luts)(const struct intel_crtc_state *crtc_state);
392 void (*read_luts)(struct intel_crtc_state *crtc_state);
395 enum i915_cache_level {
397 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
398 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
399 caches, eg sampler/render caches, and the
400 large Last-Level-Cache. LLC is coherent with
401 the CPU, but L3 is only visible to the GPU. */
402 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
405 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
408 /* This is always the inner lock when overlapping with struct_mutex and
409 * it's the outer lock when overlapping with stolen_lock. */
412 unsigned int possible_framebuffer_bits;
413 unsigned int busy_bits;
414 struct intel_crtc *crtc;
416 struct drm_mm_node compressed_fb;
417 struct drm_mm_node *compressed_llb;
425 bool underrun_detected;
426 struct work_struct underrun_work;
429 * Due to the atomic rules we can't access some structures without the
430 * appropriate locking, so we cache information here in order to avoid
433 struct intel_fbc_state_cache {
435 unsigned int mode_flags;
436 u32 hsw_bdw_pixel_rate;
440 unsigned int rotation;
445 * Display surface base address adjustement for
446 * pageflips. Note that on gen4+ this only adjusts up
447 * to a tile, offsets within a tile are handled in
448 * the hw itself (with the TILEOFF register).
453 u16 pixel_blend_mode;
457 const struct drm_format_info *format;
462 unsigned int fence_y_offset;
463 u16 gen9_wa_cfb_stride;
470 * This structure contains everything that's relevant to program the
471 * hardware registers. When we want to figure out if we need to disable
472 * and re-enable FBC for a new configuration we just check if there's
473 * something different in the struct. The genx_fbc_activate functions
474 * are supposed to read from it in order to program the registers.
476 struct intel_fbc_reg_params {
479 enum i9xx_plane_id i9xx_plane;
483 const struct drm_format_info *format;
489 unsigned int fence_y_offset;
490 u16 gen9_wa_cfb_stride;
496 const char *no_fbc_reason;
500 * HIGH_RR is the highest eDP panel refresh rate read from EDID
501 * LOW_RR is the lowest eDP panel refresh rate found from EDID
502 * parsing for same resolution.
504 enum drrs_refresh_rate_type {
507 DRRS_MAX_RR, /* RR count */
510 enum drrs_support_type {
511 DRRS_NOT_SUPPORTED = 0,
512 STATIC_DRRS_SUPPORT = 1,
513 SEAMLESS_DRRS_SUPPORT = 2
519 struct delayed_work work;
521 unsigned busy_frontbuffer_bits;
522 enum drrs_refresh_rate_type refresh_rate_type;
523 enum drrs_support_type type;
526 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
527 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
528 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
529 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
530 #define QUIRK_INCREASE_T12_DELAY (1<<6)
531 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
534 struct intel_fbc_work;
537 struct i2c_adapter adapter;
538 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
542 struct i2c_algo_bit_data bit_algo;
543 struct drm_i915_private *dev_priv;
546 struct i915_suspend_saved_registers {
554 struct vlv_s0ix_state;
556 #define MAX_L3_SLICES 2
557 struct intel_l3_parity {
558 u32 *remap_info[MAX_L3_SLICES];
559 struct work_struct error_work;
565 * Shortcut for the stolen region. This points to either
566 * INTEL_REGION_STOLEN_SMEM for integrated platforms, or
567 * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't
570 struct intel_memory_region *stolen_region;
571 /** Memory allocator for GTT stolen memory */
572 struct drm_mm stolen;
573 /** Protects the usage of the GTT stolen memory allocator. This is
574 * always the inner lock when overlapping with struct_mutex. */
575 struct mutex stolen_lock;
577 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
581 * List of objects which are purgeable.
583 struct list_head purge_list;
586 * List of objects which have allocated pages and are shrinkable.
588 struct list_head shrink_list;
591 * List of objects which are pending destruction.
593 struct llist_head free_list;
594 struct work_struct free_work;
596 * Count of objects pending destructions. Used to skip needlessly
597 * waiting on an RCU barrier if no objects are waiting to be freed.
602 * tmpfs instance used for shmem backed objects
604 struct vfsmount *gemfs;
606 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
608 struct notifier_block oom_notifier;
609 struct notifier_block vmap_notifier;
610 struct shrinker shrinker;
612 #ifdef CONFIG_MMU_NOTIFIER
614 * notifier_lock for mmu notifiers, memory may not be allocated
615 * while holding this lock.
617 rwlock_t notifier_lock;
620 /* shrinker accounting, also useful for userland debugging */
625 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
627 unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915,
630 static inline unsigned long
631 i915_fence_timeout(const struct drm_i915_private *i915)
633 return i915_fence_context_timeout(i915, U64_MAX);
636 /* Amount of SAGV/QGV points, BSpec precisely defines this */
637 #define I915_NUM_QGV_POINTS 8
639 #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
641 struct ddi_vbt_port_info {
642 /* Non-NULL if port present. */
643 struct intel_bios_encoder_data *devdata;
647 /* This is an index in the HDMI/DVI DDI buffer translation table. */
649 u8 hdmi_level_shift_set:1;
651 u8 alternate_aux_channel;
652 u8 alternate_ddc_pin;
654 int dp_max_link_rate; /* 0 for not limited by VBT */
657 enum psr_lines_to_wait {
658 PSR_0_LINES_TO_WAIT = 0,
664 struct intel_vbt_data {
668 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
669 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
672 unsigned int int_tv_support:1;
673 unsigned int lvds_dither:1;
674 unsigned int int_crt_support:1;
675 unsigned int lvds_use_ssc:1;
676 unsigned int int_lvds_support:1;
677 unsigned int display_clock_mode:1;
678 unsigned int fdi_rx_polarity_inverted:1;
679 unsigned int panel_type:4;
681 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
682 enum drm_panel_orientation orientation;
684 enum drrs_support_type drrs_type;
694 struct edp_power_seq pps;
701 bool require_aux_wakeup;
703 enum psr_lines_to_wait lines_to_wait;
704 int tp1_wakeup_time_us;
705 int tp2_tp3_wakeup_time_us;
706 int psr2_tp2_tp3_wakeup_time_us;
713 u8 min_brightness; /* min_brightness/255 of max */
714 u8 controller; /* brightness controller number */
715 enum intel_backlight_type type;
721 struct mipi_config *config;
722 struct mipi_pps_data *pps;
728 const u8 *sequence[MIPI_SEQ_MAX];
729 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
730 enum drm_panel_orientation orientation;
735 struct list_head display_devices;
737 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
738 struct sdvo_device_mapping sdvo_mappings[2];
741 enum intel_ddb_partitioning {
743 INTEL_DDB_PART_5_6, /* IVB+ */
746 struct ilk_wm_values {
751 enum intel_ddb_partitioning partitioning;
755 u16 plane[I915_MAX_PLANES];
765 struct vlv_wm_ddl_values {
766 u8 plane[I915_MAX_PLANES];
769 struct vlv_wm_values {
770 struct g4x_pipe_wm pipe[3];
772 struct vlv_wm_ddl_values ddl[3];
777 struct g4x_wm_values {
778 struct g4x_pipe_wm pipe[2];
780 struct g4x_sr_wm hpll;
786 struct skl_ddb_entry {
787 u16 start, end; /* in number of blocks, 'end' is exclusive */
790 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
792 return entry->end - entry->start;
795 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
796 const struct skl_ddb_entry *e2)
798 if (e1->start == e2->start && e1->end == e2->end)
804 struct i915_frontbuffer_tracking {
808 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
815 struct i915_virtual_gpu {
816 struct mutex lock; /* serialises sending of g2v_notify command pkts */
821 struct intel_cdclk_config {
822 unsigned int cdclk, vco, ref, bypass;
826 struct i915_selftest_stash {
828 struct ida mock_region_instances;
831 struct drm_i915_private {
832 struct drm_device drm;
834 /* FIXME: Device release actions should all be moved to drmm_ */
837 /* i915 device parameters */
838 struct i915_params params;
840 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
841 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
842 struct intel_driver_caps caps;
845 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
846 * end of stolen which we can optionally use to create GEM objects
847 * backed by stolen memory. Note that stolen_usable_size tells us
848 * exactly how much of this we are actually allowed to use, given that
849 * some portion of it is in fact reserved for use by hardware functions.
853 * Reseved portion of Data Stolen Memory
855 struct resource dsm_reserved;
858 * Stolen memory is segmented in hardware with different portions
859 * offlimits to certain functions.
861 * The drm_mm is initialised to the total accessible range, as found
862 * from the PCI config. On Broadwell+, this is further restricted to
863 * avoid the first page! The upper end of stolen memory is reserved for
864 * hardware functions and similarly removed from the accessible range.
866 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
868 struct intel_uncore uncore;
869 struct intel_uncore_mmio_debug mmio_debug;
871 struct i915_virtual_gpu vgpu;
873 struct intel_gvt *gvt;
875 struct intel_wopcm wopcm;
877 struct intel_dmc dmc;
879 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
881 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
882 * controller on different i2c buses. */
883 struct mutex gmbus_mutex;
886 * Base address of where the gmbus and gpio blocks are located (either
887 * on PCH or on SoC for platforms without PCH).
891 u32 hsw_psr_mmio_adjust;
893 /* MMIO base address for MIPI regs */
898 wait_queue_head_t gmbus_wait_queue;
900 struct pci_dev *bridge_dev;
902 struct rb_root uabi_engines;
904 struct resource mch_res;
906 /* protects the irq masks */
909 bool display_irqs_enabled;
911 /* Sideband mailbox protection */
912 struct mutex sb_lock;
913 struct pm_qos_request sb_qos;
915 /** Cached value of IMR to avoid reads in updating the bitfield */
918 u32 de_irq_mask[I915_MAX_PIPES];
920 u32 pipestat_irq_mask[I915_MAX_PIPES];
922 struct i915_hotplug hotplug;
923 struct intel_fbc fbc;
924 struct i915_drrs drrs;
925 struct intel_opregion opregion;
926 struct intel_vbt_data vbt;
928 bool preserve_bios_swizzle;
931 struct intel_overlay *overlay;
933 /* backlight registers and fields in struct intel_panel */
934 struct mutex backlight_lock;
936 /* protects panel power sequencer state */
937 struct mutex pps_mutex;
939 unsigned int fsb_freq, mem_freq, is_ddr3;
940 unsigned int skl_preferred_vco_freq;
941 unsigned int max_cdclk_freq;
943 unsigned int max_dotclk_freq;
944 unsigned int hpll_freq;
945 unsigned int fdi_pll_freq;
946 unsigned int czclk_freq;
949 /* The current hardware cdclk configuration */
950 struct intel_cdclk_config hw;
952 /* cdclk, divider, and ratio table from bspec */
953 const struct intel_cdclk_vals *table;
955 struct intel_global_obj obj;
959 /* The current hardware dbuf configuration */
962 struct intel_global_obj obj;
966 * wq - Driver workqueue for GEM.
968 * NOTE: Work items scheduled here are not allowed to grab any modeset
969 * locks, for otherwise the flushing done in the pageflip code will
970 * result in deadlocks.
972 struct workqueue_struct *wq;
974 /* ordered wq for modesets */
975 struct workqueue_struct *modeset_wq;
976 /* unbound hipri wq for page flips/plane updates */
977 struct workqueue_struct *flip_wq;
979 /* Display functions */
980 struct drm_i915_display_funcs display;
982 /* PCH chipset type */
983 enum intel_pch pch_type;
984 unsigned short pch_id;
986 unsigned long quirks;
988 struct drm_atomic_state *modeset_restore_state;
989 struct drm_modeset_acquire_ctx reset_ctx;
991 struct i915_ggtt ggtt; /* VM representing the global address space */
993 struct i915_gem_mm mm;
995 /* Kernel Modesetting */
997 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
998 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1001 * dpll and cdclk state is protected by connection_mutex
1002 * dpll.lock serializes intel_{prepare,enable,disable}_shared_dpll.
1003 * Must be global rather than per dpll, because on some platforms plls
1009 int num_shared_dpll;
1010 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1011 const struct intel_dpll_mgr *mgr;
1019 struct list_head global_obj_list;
1022 * For reading active_pipes holding any crtc lock is
1023 * sufficient, for writing must hold all of them.
1027 struct i915_wa_list gt_wa_list;
1029 struct i915_frontbuffer_tracking fb_tracking;
1031 struct intel_atomic_helper {
1032 struct llist_head free_list;
1033 struct work_struct free_work;
1036 bool mchbar_need_disable;
1038 struct intel_l3_parity l3_parity;
1041 * HTI (aka HDPORT) state read during initial hw readout. Most
1042 * platforms don't have HTI, so this will just stay 0. Those that do
1043 * will use this later to figure out which PLLs and PHYs are unavailable
1050 * Cannot be determined by PCIID. You must always read a register.
1054 struct i915_power_domains power_domains;
1056 struct i915_gpu_error gpu_error;
1058 struct drm_i915_gem_object *vlv_pctx;
1060 /* list of fbdev register on this device */
1061 struct intel_fbdev *fbdev;
1062 struct work_struct fbdev_suspend_work;
1064 struct drm_property *broadcast_rgb_property;
1065 struct drm_property *force_audio_property;
1067 /* hda/i915 audio component */
1068 struct i915_audio_component *audio_component;
1069 bool audio_component_registered;
1071 * av_mutex - mutex for audio/video sync
1074 struct mutex av_mutex;
1075 int audio_power_refcount;
1076 u32 audio_freq_cntrl;
1080 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1081 u32 chv_phy_control;
1083 * Shadows for CHV DPLL_MD regs to keep the state
1084 * checker somewhat working in the presence hardware
1085 * crappiness (can't read out DPLL_MD for pipes B & C).
1087 u32 chv_dpll_md[I915_MAX_PIPES];
1091 bool power_domains_suspended;
1092 struct i915_suspend_saved_registers regfile;
1093 struct vlv_s0ix_state *vlv_s0ix_state;
1096 I915_SAGV_UNKNOWN = 0,
1099 I915_SAGV_NOT_CONTROLLED
1102 u32 sagv_block_time_us;
1106 * Raw watermark latency values:
1107 * in 0.1us units for WM0,
1108 * in 0.5us units for WM1+.
1117 * Raw watermark memory latency values
1118 * for SKL for all 8 levels
1123 /* current hardware state */
1125 struct ilk_wm_values hw;
1126 struct vlv_wm_values vlv;
1127 struct g4x_wm_values g4x;
1133 * Should be held around atomic WM register writing; also
1134 * protects * intel_crtc->wm.active and
1135 * crtc_state->wm.need_postvbl_update.
1137 struct mutex wm_mutex;
1141 bool wm_lv_0_adjust_needed;
1143 bool symmetric_memory;
1144 enum intel_dram_type {
1156 struct intel_bw_info {
1157 /* for each QGV point */
1158 unsigned int deratedbw[I915_NUM_QGV_POINTS];
1163 struct intel_global_obj bw_obj;
1165 struct intel_runtime_pm runtime_pm;
1167 struct i915_perf perf;
1169 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1173 struct i915_gem_contexts {
1174 spinlock_t lock; /* locks list */
1175 struct list_head list;
1179 * We replace the local file with a global mappings as the
1180 * backing storage for the mmap is on the device and not
1181 * on the struct file, and we do not want to prolong the
1182 * lifetime of the local fd. To minimise the number of
1183 * anonymous inodes we create, we use a global singleton to
1184 * share the global mapping.
1186 struct file *mmap_singleton;
1189 u8 framestart_delay;
1191 /* Window2 specifies time required to program DSB (Window2) in number of scan lines */
1196 /* For i915gm/i945gm vblank irq workaround */
1199 /* perform PHY state sanity checks? */
1200 bool chv_phy_assert[2];
1204 /* Used to save the pipe-to-encoder mapping for audio */
1205 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
1207 /* necessary resource sharing with HDMI LPE audio driver. */
1209 struct platform_device *platdev;
1213 struct i915_pmu pmu;
1215 struct i915_hdcp_comp_master *hdcp_master;
1216 bool hdcp_comp_added;
1218 /* Mutex to protect the above hdcp component related values. */
1219 struct mutex hdcp_comp_mutex;
1221 /* The TTM device structure. */
1222 struct ttm_device bdev;
1224 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
1227 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1228 * will be rejected. Instead look for a better place.
1232 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1234 return container_of(dev, struct drm_i915_private, drm);
1237 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
1239 return dev_get_drvdata(kdev);
1242 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
1244 return pci_get_drvdata(pdev);
1247 /* Simple iterator over all initialised engines */
1248 #define for_each_engine(engine__, dev_priv__, id__) \
1250 (id__) < I915_NUM_ENGINES; \
1252 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
1254 /* Iterator over subset of engines selected by mask */
1255 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
1256 for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
1258 ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
1261 #define rb_to_uabi_engine(rb) \
1262 rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
1264 #define for_each_uabi_engine(engine__, i915__) \
1265 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
1267 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
1269 #define for_each_uabi_class_engine(engine__, class__, i915__) \
1270 for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \
1271 (engine__) && (engine__)->uabi_class == (class__); \
1272 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
1274 #define I915_GTT_OFFSET_NONE ((u32)-1)
1277 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1278 * considered to be the frontbuffer for the given plane interface-wise. This
1279 * doesn't mean that the hw necessarily already scans it out, but that any
1280 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1282 * We have one bit per pipe and per scanout plane type.
1284 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
1285 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
1286 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
1287 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
1288 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
1290 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1291 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1292 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1293 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
1294 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1296 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info)
1297 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
1298 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
1300 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
1303 * Deprecated: this will be replaced by individual IP checks:
1304 * GRAPHICS_VER(), MEDIA_VER() and DISPLAY_VER()
1306 #define INTEL_GEN(dev_priv) GRAPHICS_VER(dev_priv)
1308 * Deprecated: use IS_GRAPHICS_VER(), IS_MEDIA_VER() and IS_DISPLAY_VER() as
1311 #define IS_GEN_RANGE(dev_priv, s, e) IS_GRAPHICS_VER(dev_priv, (s), (e))
1313 * Deprecated: use GRAPHICS_VER(), MEDIA_VER() and DISPLAY_VER() as appropriate.
1315 #define IS_GEN(dev_priv, n) (GRAPHICS_VER(dev_priv) == (n))
1317 #define IP_VER(ver, rel) ((ver) << 8 | (rel))
1319 #define GRAPHICS_VER(i915) (INTEL_INFO(i915)->graphics_ver)
1320 #define GRAPHICS_VER_FULL(i915) IP_VER(INTEL_INFO(i915)->graphics_ver, \
1321 INTEL_INFO(i915)->graphics_rel)
1322 #define IS_GRAPHICS_VER(i915, from, until) \
1323 (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
1325 #define MEDIA_VER(i915) (INTEL_INFO(i915)->media_ver)
1326 #define MEDIA_VER_FULL(i915) IP_VER(INTEL_INFO(i915)->media_ver, \
1327 INTEL_INFO(i915)->media_rel)
1328 #define IS_MEDIA_VER(i915, from, until) \
1329 (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
1331 #define DISPLAY_VER(i915) (INTEL_INFO(i915)->display.ver)
1332 #define IS_DISPLAY_VER(i915, from, until) \
1333 (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
1335 #define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision)
1337 #define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb)
1339 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
1340 #define INTEL_GT_STEP(__i915) (RUNTIME_INFO(__i915)->step.gt_step)
1342 #define IS_DISPLAY_STEP(__i915, since, until) \
1343 (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
1344 INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) <= (until))
1346 #define IS_GT_STEP(__i915, since, until) \
1347 (drm_WARN_ON(&(__i915)->drm, INTEL_GT_STEP(__i915) == STEP_NONE), \
1348 INTEL_GT_STEP(__i915) >= (since) && INTEL_GT_STEP(__i915) < (until))
1350 static __always_inline unsigned int
1351 __platform_mask_index(const struct intel_runtime_info *info,
1352 enum intel_platform p)
1354 const unsigned int pbits =
1355 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1357 /* Expand the platform_mask array if this fails. */
1358 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
1359 pbits * ARRAY_SIZE(info->platform_mask));
1364 static __always_inline unsigned int
1365 __platform_mask_bit(const struct intel_runtime_info *info,
1366 enum intel_platform p)
1368 const unsigned int pbits =
1369 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1371 return p % pbits + INTEL_SUBPLATFORM_BITS;
1375 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
1377 const unsigned int pi = __platform_mask_index(info, p);
1379 return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK;
1382 static __always_inline bool
1383 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
1385 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1386 const unsigned int pi = __platform_mask_index(info, p);
1387 const unsigned int pb = __platform_mask_bit(info, p);
1389 BUILD_BUG_ON(!__builtin_constant_p(p));
1391 return info->platform_mask[pi] & BIT(pb);
1394 static __always_inline bool
1395 IS_SUBPLATFORM(const struct drm_i915_private *i915,
1396 enum intel_platform p, unsigned int s)
1398 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1399 const unsigned int pi = __platform_mask_index(info, p);
1400 const unsigned int pb = __platform_mask_bit(info, p);
1401 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
1402 const u32 mask = info->platform_mask[pi];
1404 BUILD_BUG_ON(!__builtin_constant_p(p));
1405 BUILD_BUG_ON(!__builtin_constant_p(s));
1406 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
1408 /* Shift and test on the MSB position so sign flag can be used. */
1409 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
1412 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
1413 #define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx)
1415 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
1416 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
1417 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
1418 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
1419 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
1420 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
1421 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
1422 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
1423 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
1424 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
1425 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
1426 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
1427 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
1428 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
1429 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
1430 #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
1431 #define IS_IRONLAKE_M(dev_priv) \
1432 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
1433 #define IS_SANDYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE)
1434 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
1435 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
1436 INTEL_INFO(dev_priv)->gt == 1)
1437 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
1438 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
1439 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
1440 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
1441 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
1442 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
1443 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
1444 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
1445 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
1446 #define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
1447 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
1448 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
1449 #define IS_JSL_EHL(dev_priv) (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \
1450 IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
1451 #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
1452 #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
1453 #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1)
1454 #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
1455 #define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
1456 #define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV)
1457 #define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG2)
1458 #define IS_DG2_G10(dev_priv) \
1459 IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
1460 #define IS_DG2_G11(dev_priv) \
1461 IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
1462 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
1463 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
1464 #define IS_BDW_ULT(dev_priv) \
1465 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
1466 #define IS_BDW_ULX(dev_priv) \
1467 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
1468 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
1469 INTEL_INFO(dev_priv)->gt == 3)
1470 #define IS_HSW_ULT(dev_priv) \
1471 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
1472 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
1473 INTEL_INFO(dev_priv)->gt == 3)
1474 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \
1475 INTEL_INFO(dev_priv)->gt == 1)
1476 /* ULX machines are also considered ULT. */
1477 #define IS_HSW_ULX(dev_priv) \
1478 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
1479 #define IS_SKL_ULT(dev_priv) \
1480 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
1481 #define IS_SKL_ULX(dev_priv) \
1482 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
1483 #define IS_KBL_ULT(dev_priv) \
1484 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
1485 #define IS_KBL_ULX(dev_priv) \
1486 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
1487 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
1488 INTEL_INFO(dev_priv)->gt == 2)
1489 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
1490 INTEL_INFO(dev_priv)->gt == 3)
1491 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
1492 INTEL_INFO(dev_priv)->gt == 4)
1493 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
1494 INTEL_INFO(dev_priv)->gt == 2)
1495 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
1496 INTEL_INFO(dev_priv)->gt == 3)
1497 #define IS_CFL_ULT(dev_priv) \
1498 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
1499 #define IS_CFL_ULX(dev_priv) \
1500 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
1501 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
1502 INTEL_INFO(dev_priv)->gt == 2)
1503 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
1504 INTEL_INFO(dev_priv)->gt == 3)
1506 #define IS_CML_ULT(dev_priv) \
1507 IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
1508 #define IS_CML_ULX(dev_priv) \
1509 IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
1510 #define IS_CML_GT2(dev_priv) (IS_COMETLAKE(dev_priv) && \
1511 INTEL_INFO(dev_priv)->gt == 2)
1513 #define IS_CNL_WITH_PORT_F(dev_priv) \
1514 IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
1515 #define IS_ICL_WITH_PORT_F(dev_priv) \
1516 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
1518 #define IS_TGL_U(dev_priv) \
1519 IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULT)
1521 #define IS_TGL_Y(dev_priv) \
1522 IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULX)
1524 #define IS_SKL_GT_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GT_STEP(p, since, until))
1526 #define IS_KBL_GT_STEP(dev_priv, since, until) \
1527 (IS_KABYLAKE(dev_priv) && IS_GT_STEP(dev_priv, since, until))
1528 #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
1529 (IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until))
1531 #define IS_JSL_EHL_GT_STEP(p, since, until) \
1532 (IS_JSL_EHL(p) && IS_GT_STEP(p, since, until))
1533 #define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
1534 (IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))
1536 #define IS_TGL_DISPLAY_STEP(__i915, since, until) \
1537 (IS_TIGERLAKE(__i915) && \
1538 IS_DISPLAY_STEP(__i915, since, until))
1540 #define IS_TGL_UY_GT_STEP(__i915, since, until) \
1541 ((IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \
1542 IS_GT_STEP(__i915, since, until))
1544 #define IS_TGL_GT_STEP(__i915, since, until) \
1545 (IS_TIGERLAKE(__i915) && !(IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \
1546 IS_GT_STEP(__i915, since, until))
1548 #define IS_RKL_DISPLAY_STEP(p, since, until) \
1549 (IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
1551 #define IS_DG1_GT_STEP(p, since, until) \
1552 (IS_DG1(p) && IS_GT_STEP(p, since, until))
1553 #define IS_DG1_DISPLAY_STEP(p, since, until) \
1554 (IS_DG1(p) && IS_DISPLAY_STEP(p, since, until))
1556 #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
1557 (IS_ALDERLAKE_S(__i915) && \
1558 IS_DISPLAY_STEP(__i915, since, until))
1560 #define IS_ADLS_GT_STEP(__i915, since, until) \
1561 (IS_ALDERLAKE_S(__i915) && \
1562 IS_GT_STEP(__i915, since, until))
1564 #define IS_ADLP_DISPLAY_STEP(__i915, since, until) \
1565 (IS_ALDERLAKE_P(__i915) && \
1566 IS_DISPLAY_STEP(__i915, since, until))
1568 #define IS_ADLP_GT_STEP(__i915, since, until) \
1569 (IS_ALDERLAKE_P(__i915) && \
1570 IS_GT_STEP(__i915, since, until))
1572 #define IS_XEHPSDV_GT_STEP(p, since, until) \
1573 (IS_XEHPSDV(p) && IS_GT_STEP(__i915, since, until))
1576 * DG2 hardware steppings are a bit unusual. The hardware design was forked
1577 * to create two variants (G10 and G11) which have distinct workaround sets.
1578 * The G11 fork of the DG2 design resets the GT stepping back to "A0" for its
1579 * first iteration, even though it's more similar to a G10 B0 stepping in terms
1580 * of functionality and workarounds. However the display stepping does not
1581 * reset in the same manner --- a specific stepping like "B0" has a consistent
1582 * meaning regardless of whether it belongs to a G10 or G11 DG2.
1584 * TLDR: All GT workarounds and stepping-specific logic must be applied in
1585 * relation to a specific subplatform (G10 or G11), whereas display workarounds
1586 * and stepping-specific logic will be applied with a general DG2-wide stepping
1589 #define IS_DG2_GT_STEP(__i915, variant, since, until) \
1590 (IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \
1591 IS_GT_STEP(__i915, since, until))
1593 #define IS_DG2_DISP_STEP(__i915, since, until) \
1594 (IS_DG2(__i915) && \
1595 IS_DISPLAY_STEP(__i915, since, until))
1597 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
1598 #define IS_GEN9_LP(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv))
1599 #define IS_GEN9_BC(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv))
1601 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
1602 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
1604 #define ENGINE_INSTANCES_MASK(gt, first, count) ({ \
1605 unsigned int first__ = (first); \
1606 unsigned int count__ = (count); \
1607 ((gt)->info.engine_mask & \
1608 GENMASK(first__ + count__ - 1, first__)) >> first__; \
1610 #define VDBOX_MASK(gt) \
1611 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
1612 #define VEBOX_MASK(gt) \
1613 ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
1616 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
1617 * All later gens can run the final buffer from the ppgtt
1619 #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
1621 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
1622 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
1623 #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
1624 #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
1625 #define HAS_WT(dev_priv) HAS_EDRAM(dev_priv)
1627 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)
1629 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
1630 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
1631 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
1632 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
1634 #define HAS_MASTER_UNIT_IRQ(dev_priv) (INTEL_INFO(dev_priv)->has_master_unit_irq)
1636 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
1638 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
1639 #define HAS_PPGTT(dev_priv) \
1640 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
1641 #define HAS_FULL_PPGTT(dev_priv) \
1642 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
1644 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
1645 GEM_BUG_ON((sizes) == 0); \
1646 ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
1649 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay)
1650 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
1651 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
1653 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1654 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
1656 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \
1657 (IS_BROADWELL(dev_priv) || GRAPHICS_VER(dev_priv) == 9)
1659 /* WaRsDisableCoarsePowerGating:skl,cnl */
1660 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
1661 (IS_CANNONLAKE(dev_priv) || \
1662 IS_SKL_GT3(dev_priv) || \
1663 IS_SKL_GT4(dev_priv))
1665 #define HAS_GMBUS_IRQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 4)
1666 #define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 10 || \
1667 IS_GEMINILAKE(dev_priv) || \
1668 IS_KABYLAKE(dev_priv))
1670 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1671 * rows, which changed the alignment requirements and fence programming.
1673 #define HAS_128_BYTE_Y_TILING(dev_priv) (GRAPHICS_VER(dev_priv) != 2 && \
1674 !(IS_I915G(dev_priv) || IS_I915GM(dev_priv)))
1675 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv)
1676 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
1678 #define HAS_FW_BLC(dev_priv) (GRAPHICS_VER(dev_priv) > 2)
1679 #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc)
1680 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && GRAPHICS_VER(dev_priv) >= 7)
1682 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
1684 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst)
1686 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
1687 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
1688 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
1689 #define HAS_PSR_HW_TRACKING(dev_priv) \
1690 (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
1691 #define HAS_PSR2_SEL_FETCH(dev_priv) (GRAPHICS_VER(dev_priv) >= 12)
1692 #define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
1694 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
1695 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
1696 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
1698 #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps)
1700 #define HAS_DMC(dev_priv) (INTEL_INFO(dev_priv)->display.has_dmc)
1702 #define HAS_MSO(i915) (GRAPHICS_VER(i915) >= 12)
1704 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
1705 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
1707 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
1709 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
1710 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
1712 #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc)
1714 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
1716 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs)
1719 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
1721 #define HAS_LSPCON(dev_priv) (IS_GRAPHICS_VER(dev_priv, 9, 10))
1723 /* DPF == dynamic parity feature */
1724 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
1725 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
1726 2 : HAS_L3_DPF(dev_priv))
1728 #define GT_FREQUENCY_MULTIPLIER 50
1729 #define GEN9_FREQ_SCALER 3
1731 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
1733 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
1735 #define HAS_VRR(i915) (GRAPHICS_VER(i915) >= 12)
1737 /* Only valid when HAS_DISPLAY() is true */
1738 #define INTEL_DISPLAY_ENABLED(dev_priv) \
1739 (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display)
1741 static inline bool run_as_guest(void)
1743 return !hypervisor_is_type(X86_HYPER_NATIVE);
1746 #define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
1747 IS_ALDERLAKE_S(dev_priv))
1749 static inline bool intel_vtd_active(void)
1751 #ifdef CONFIG_INTEL_IOMMU
1752 if (intel_iommu_gfx_mapped)
1756 /* Running as a guest, we assume the host is enforcing VT'd */
1757 return run_as_guest();
1760 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
1762 return GRAPHICS_VER(dev_priv) >= 6 && intel_vtd_active();
1766 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *i915)
1768 return IS_BROXTON(i915) && intel_vtd_active();
1772 intel_vm_no_concurrent_access_wa(struct drm_i915_private *i915)
1774 return IS_CHERRYVIEW(i915) || intel_ggtt_update_needs_vtd_wa(i915);
1778 extern const struct dev_pm_ops i915_pm_ops;
1780 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
1781 void i915_driver_remove(struct drm_i915_private *i915);
1782 void i915_driver_shutdown(struct drm_i915_private *i915);
1784 int i915_resume_switcheroo(struct drm_i915_private *i915);
1785 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state);
1787 int i915_getparam_ioctl(struct drm_device *dev, void *data,
1788 struct drm_file *file_priv);
1791 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
1792 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
1793 void i915_gem_init_early(struct drm_i915_private *dev_priv);
1794 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
1796 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
1799 * A single pass should suffice to release all the freed objects (along
1800 * most call paths) , but be a little more paranoid in that freeing
1801 * the objects does take a little amount of time, during which the rcu
1802 * callbacks could have added new objects into the freed list, and
1803 * armed the work again.
1805 while (atomic_read(&i915->mm.free_count)) {
1806 flush_work(&i915->mm.free_work);
1811 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
1814 * Similar to objects above (see i915_gem_drain_freed-objects), in
1815 * general we have workers that are armed by RCU and then rearm
1816 * themselves in their callbacks. To be paranoid, we need to
1817 * drain the workqueue a second time after waiting for the RCU
1818 * grace period so that we catch work queued via RCU from the first
1819 * pass. As neither drain_workqueue() nor flush_workqueue() report
1820 * a result, we make an assumption that we only don't require more
1821 * than 3 passes to catch all _recursive_ RCU delayed work.
1826 flush_workqueue(i915->wq);
1828 i915_gem_drain_freed_objects(i915);
1830 drain_workqueue(i915->wq);
1833 struct i915_vma * __must_check
1834 i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj,
1835 struct i915_gem_ww_ctx *ww,
1836 const struct i915_ggtt_view *view,
1837 u64 size, u64 alignment, u64 flags);
1839 static inline struct i915_vma * __must_check
1840 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
1841 const struct i915_ggtt_view *view,
1842 u64 size, u64 alignment, u64 flags)
1844 return i915_gem_object_ggtt_pin_ww(obj, NULL, view, size, alignment, flags);
1847 int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
1848 unsigned long flags);
1849 #define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0)
1850 #define I915_GEM_OBJECT_UNBIND_BARRIER BIT(1)
1851 #define I915_GEM_OBJECT_UNBIND_TEST BIT(2)
1852 #define I915_GEM_OBJECT_UNBIND_VM_TRYLOCK BIT(3)
1854 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
1856 int i915_gem_dumb_create(struct drm_file *file_priv,
1857 struct drm_device *dev,
1858 struct drm_mode_create_dumb *args);
1860 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
1862 static inline u32 i915_reset_count(struct i915_gpu_error *error)
1864 return atomic_read(&error->reset_count);
1867 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
1868 const struct intel_engine_cs *engine)
1870 return atomic_read(&error->reset_engine_count[engine->uabi_class]);
1873 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
1874 void i915_gem_driver_register(struct drm_i915_private *i915);
1875 void i915_gem_driver_unregister(struct drm_i915_private *i915);
1876 void i915_gem_driver_remove(struct drm_i915_private *dev_priv);
1877 void i915_gem_driver_release(struct drm_i915_private *dev_priv);
1878 void i915_gem_suspend(struct drm_i915_private *dev_priv);
1879 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
1880 void i915_gem_resume(struct drm_i915_private *dev_priv);
1882 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
1884 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1885 enum i915_cache_level cache_level);
1887 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1888 struct dma_buf *dma_buf);
1890 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags);
1892 static inline struct i915_address_space *
1893 i915_gem_vm_lookup(struct drm_i915_file_private *file_priv, u32 id)
1895 struct i915_address_space *vm;
1898 vm = xa_load(&file_priv->vm_xa, id);
1899 if (vm && !kref_get_unless_zero(&vm->ref))
1906 /* i915_gem_evict.c */
1907 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
1908 u64 min_size, u64 alignment,
1909 unsigned long color,
1912 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
1913 struct drm_mm_node *node,
1914 unsigned int flags);
1915 int i915_gem_evict_vm(struct i915_address_space *vm);
1917 /* i915_gem_internal.c */
1918 struct drm_i915_gem_object *
1919 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
1922 /* i915_gem_tiling.c */
1923 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1925 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1927 return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1928 i915_gem_object_is_tiled(obj);
1931 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
1932 unsigned int tiling, unsigned int stride);
1933 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
1934 unsigned int tiling, unsigned int stride);
1936 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
1938 /* i915_cmd_parser.c */
1939 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
1940 int intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
1941 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
1942 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
1943 struct i915_vma *batch,
1944 unsigned long batch_offset,
1945 unsigned long batch_length,
1946 struct i915_vma *shadow,
1948 #define I915_CMD_PARSER_TRAMPOLINE_SIZE 8
1950 /* intel_device_info.c */
1951 static inline struct intel_device_info *
1952 mkwrite_device_info(struct drm_i915_private *dev_priv)
1954 return (struct intel_device_info *)INTEL_INFO(dev_priv);
1957 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1958 struct drm_file *file);
1961 int remap_io_mapping(struct vm_area_struct *vma,
1962 unsigned long addr, unsigned long pfn, unsigned long size,
1963 struct io_mapping *iomap);
1964 int remap_io_sg(struct vm_area_struct *vma,
1965 unsigned long addr, unsigned long size,
1966 struct scatterlist *sgl, resource_size_t iobase);
1968 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
1970 if (GRAPHICS_VER(i915) >= 10)
1971 return CNL_HWS_CSB_WRITE_INDEX;
1973 return I915_HWS_CSB_WRITE_INDEX;
1976 static inline enum i915_map_type
1977 i915_coherent_map_type(struct drm_i915_private *i915,
1978 struct drm_i915_gem_object *obj, bool always_coherent)
1980 if (i915_gem_object_is_lmem(obj))
1982 if (HAS_LLC(i915) || always_coherent)