1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <asm/hypervisor.h>
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <linux/backlight.h>
42 #include <linux/hash.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/mm_types.h>
46 #include <linux/perf_event.h>
47 #include <linux/pm_qos.h>
48 #include <linux/dma-resv.h>
49 #include <linux/shmem_fs.h>
50 #include <linux/stackdepot.h>
51 #include <linux/xarray.h>
53 #include <drm/intel-gtt.h>
54 #include <drm/drm_gem.h>
55 #include <drm/drm_auth.h>
56 #include <drm/drm_cache.h>
57 #include <drm/drm_util.h>
58 #include <drm/drm_dsc.h>
59 #include <drm/drm_atomic.h>
60 #include <drm/drm_connector.h>
61 #include <drm/i915_mei_hdcp_interface.h>
62 #include <drm/ttm/ttm_device.h>
64 #include "i915_params.h"
66 #include "i915_utils.h"
68 #include "display/intel_bios.h"
69 #include "display/intel_display.h"
70 #include "display/intel_display_power.h"
71 #include "display/intel_dmc.h"
72 #include "display/intel_dpll_mgr.h"
73 #include "display/intel_dsb.h"
74 #include "display/intel_frontbuffer.h"
75 #include "display/intel_global_state.h"
76 #include "display/intel_gmbus.h"
77 #include "display/intel_opregion.h"
79 #include "gem/i915_gem_context_types.h"
80 #include "gem/i915_gem_shrinker.h"
81 #include "gem/i915_gem_stolen.h"
82 #include "gem/i915_gem_lmem.h"
84 #include "gt/intel_engine.h"
85 #include "gt/intel_gt_types.h"
86 #include "gt/intel_region_lmem.h"
87 #include "gt/intel_workarounds.h"
88 #include "gt/uc/intel_uc.h"
90 #include "intel_device_info.h"
91 #include "intel_memory_region.h"
92 #include "intel_pch.h"
93 #include "intel_runtime_pm.h"
94 #include "intel_step.h"
95 #include "intel_uncore.h"
96 #include "intel_wakeref.h"
97 #include "intel_wopcm.h"
100 #include "i915_gem_gtt.h"
101 #include "i915_gpu_error.h"
102 #include "i915_perf_types.h"
103 #include "i915_request.h"
104 #include "i915_scheduler.h"
105 #include "gt/intel_timeline.h"
106 #include "i915_vma.h"
107 #include "i915_irq.h"
110 /* General customization:
113 #define DRIVER_NAME "i915"
114 #define DRIVER_DESC "Intel Graphics"
115 #define DRIVER_DATE "20201103"
116 #define DRIVER_TIMESTAMP 1604406085
118 struct drm_i915_gem_object;
122 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
141 #define for_each_hpd_pin(__pin) \
142 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
144 /* Threshold == 5 for long IRQs, 50 for short */
145 #define HPD_STORM_DEFAULT_THRESHOLD 50
147 struct i915_hotplug {
148 struct delayed_work hotplug_work;
150 const u32 *hpd, *pch_hpd;
153 unsigned long last_jiffies;
158 HPD_MARK_DISABLED = 2
160 } stats[HPD_NUM_PINS];
163 struct delayed_work reenable_work;
167 struct work_struct dig_port_work;
169 struct work_struct poll_init_work;
172 unsigned int hpd_storm_threshold;
173 /* Whether or not to count short HPD IRQs in HPD storms */
174 u8 hpd_short_storm_enabled;
177 * if we get a HPD irq from DP and a HPD irq from non-DP
178 * the non-DP HPD could block the workqueue on a mode config
179 * mutex getting, that userspace may have taken. However
180 * userspace is waiting on the DP workqueue to run which is
181 * blocked behind the non-DP one.
183 struct workqueue_struct *dp_wq;
186 #define I915_GEM_GPU_DOMAINS \
187 (I915_GEM_DOMAIN_RENDER | \
188 I915_GEM_DOMAIN_SAMPLER | \
189 I915_GEM_DOMAIN_COMMAND | \
190 I915_GEM_DOMAIN_INSTRUCTION | \
191 I915_GEM_DOMAIN_VERTEX)
193 struct drm_i915_private;
194 struct i915_mm_struct;
195 struct i915_mmu_object;
197 struct drm_i915_file_private {
198 struct drm_i915_private *dev_priv;
201 struct drm_file *file;
205 /** @proto_context_lock: Guards all struct i915_gem_proto_context
208 * This not only guards @proto_context_xa, but is always held
209 * whenever we manipulate any struct i915_gem_proto_context,
210 * including finalizing it on first actual use of the GEM context.
212 * See i915_gem_proto_context.
214 struct mutex proto_context_lock;
216 /** @proto_context_xa: xarray of struct i915_gem_proto_context
218 * Historically, the context uAPI allowed for two methods of
219 * setting context parameters: SET_CONTEXT_PARAM and
220 * CONTEXT_CREATE_EXT_SETPARAM. The former is allowed to be called
221 * at any time while the later happens as part of
222 * GEM_CONTEXT_CREATE. Everything settable via one was settable
223 * via the other. While some params are fairly simple and setting
224 * them on a live context is harmless such as the context priority,
225 * others are far trickier such as the VM or the set of engines.
226 * In order to swap out the VM, for instance, we have to delay
227 * until all current in-flight work is complete, swap in the new
228 * VM, and then continue. This leads to a plethora of potential
229 * race conditions we'd really rather avoid.
231 * We have since disallowed setting these more complex parameters
232 * on active contexts. This works by delaying the creation of the
233 * actual context until after the client is done configuring it
234 * with SET_CONTEXT_PARAM. From the perspective of the client, it
235 * has the same u32 context ID the whole time. From the
236 * perspective of i915, however, it's a struct i915_gem_proto_context
237 * right up until the point where we attempt to do something which
238 * the proto-context can't handle. Then the struct i915_gem_context
241 * This is accomplished via a little xarray dance. When
242 * GEM_CONTEXT_CREATE is called, we create a struct
243 * i915_gem_proto_context, reserve a slot in @context_xa but leave
244 * it NULL, and place the proto-context in the corresponding slot
245 * in @proto_context_xa. Then, in i915_gem_context_lookup(), we
246 * first check @context_xa. If it's there, we return the struct
247 * i915_gem_context and we're done. If it's not, we look in
248 * @proto_context_xa and, if we find it there, we create the actual
249 * context and kill the proto-context.
251 * In order for this dance to work properly, everything which ever
252 * touches a struct i915_gem_proto_context is guarded by
253 * @proto_context_lock, including context creation. Yes, this
254 * means context creation now takes a giant global lock but it
255 * can't really be helped and that should never be on any driver's
258 struct xarray proto_context_xa;
260 /** @context_xa: xarray of fully created i915_gem_context
262 * Write access to this xarray is guarded by @proto_context_lock.
263 * Otherwise, writers may race with finalize_create_context_locked().
265 * See @proto_context_xa.
267 struct xarray context_xa;
270 unsigned int bsd_engine;
273 * Every context ban increments per client ban score. Also
274 * hangs in short succession increments ban score. If ban threshold
275 * is reached, client is considered banned and submitting more work
276 * will fail. This is a stop gap measure to limit the badly behaving
277 * clients access to gpu. Note that unbannable contexts never increment
278 * the client ban score.
280 #define I915_CLIENT_SCORE_HANG_FAST 1
281 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
282 #define I915_CLIENT_SCORE_CONTEXT_BAN 3
283 #define I915_CLIENT_SCORE_BANNED 9
284 /** ban_score: Accumulated score of all ctx bans and fast hangs. */
286 unsigned long hang_timestamp;
289 /* Interface history:
292 * 1.2: Add Power Management
293 * 1.3: Add vblank support
294 * 1.4: Fix cmdbuffer path, add heap destroy
295 * 1.5: Add vblank pipe configuration
296 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
297 * - Support vertical blank on secondary display pipe
299 #define DRIVER_MAJOR 1
300 #define DRIVER_MINOR 6
301 #define DRIVER_PATCHLEVEL 0
303 struct intel_overlay;
304 struct intel_overlay_error_state;
306 struct sdvo_device_mapping {
315 struct intel_connector;
316 struct intel_encoder;
317 struct intel_atomic_state;
318 struct intel_cdclk_config;
319 struct intel_cdclk_state;
320 struct intel_cdclk_vals;
321 struct intel_initial_plane_config;
326 struct drm_i915_display_funcs {
327 void (*get_cdclk)(struct drm_i915_private *dev_priv,
328 struct intel_cdclk_config *cdclk_config);
329 void (*set_cdclk)(struct drm_i915_private *dev_priv,
330 const struct intel_cdclk_config *cdclk_config,
332 int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
333 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
334 enum i9xx_plane_id i9xx_plane);
335 int (*compute_pipe_wm)(struct intel_atomic_state *state,
336 struct intel_crtc *crtc);
337 int (*compute_intermediate_wm)(struct intel_atomic_state *state,
338 struct intel_crtc *crtc);
339 void (*initial_watermarks)(struct intel_atomic_state *state,
340 struct intel_crtc *crtc);
341 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
342 struct intel_crtc *crtc);
343 void (*optimize_watermarks)(struct intel_atomic_state *state,
344 struct intel_crtc *crtc);
345 int (*compute_global_watermarks)(struct intel_atomic_state *state);
346 void (*update_wm)(struct intel_crtc *crtc);
347 int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
348 u8 (*calc_voltage_level)(int cdclk);
349 /* Returns the active state of the crtc, and if the crtc is active,
350 * fills out the pipe-config with the hw state. */
351 bool (*get_pipe_config)(struct intel_crtc *,
352 struct intel_crtc_state *);
353 void (*get_initial_plane_config)(struct intel_crtc *,
354 struct intel_initial_plane_config *);
355 int (*crtc_compute_clock)(struct intel_crtc *crtc,
356 struct intel_crtc_state *crtc_state);
357 void (*crtc_enable)(struct intel_atomic_state *state,
358 struct intel_crtc *crtc);
359 void (*crtc_disable)(struct intel_atomic_state *state,
360 struct intel_crtc *crtc);
361 void (*commit_modeset_enables)(struct intel_atomic_state *state);
362 void (*commit_modeset_disables)(struct intel_atomic_state *state);
363 void (*audio_codec_enable)(struct intel_encoder *encoder,
364 const struct intel_crtc_state *crtc_state,
365 const struct drm_connector_state *conn_state);
366 void (*audio_codec_disable)(struct intel_encoder *encoder,
367 const struct intel_crtc_state *old_crtc_state,
368 const struct drm_connector_state *old_conn_state);
369 void (*fdi_link_train)(struct intel_crtc *crtc,
370 const struct intel_crtc_state *crtc_state);
371 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
372 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
373 /* clock updates for mode set */
375 /* render clock increase/decrease */
376 /* display clock increase/decrease */
377 /* pll clock increase/decrease */
379 int (*color_check)(struct intel_crtc_state *crtc_state);
381 * Program double buffered color management registers during
382 * vblank evasion. The registers should then latch during the
383 * next vblank start, alongside any other double buffered registers
384 * involved with the same commit.
386 void (*color_commit)(const struct intel_crtc_state *crtc_state);
388 * Load LUTs (and other single buffered color management
389 * registers). Will (hopefully) be called during the vblank
390 * following the latching of any double buffered registers
391 * involved with the same commit.
393 void (*load_luts)(const struct intel_crtc_state *crtc_state);
394 void (*read_luts)(struct intel_crtc_state *crtc_state);
398 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
401 /* This is always the inner lock when overlapping with struct_mutex and
402 * it's the outer lock when overlapping with stolen_lock. */
404 unsigned int possible_framebuffer_bits;
405 unsigned int busy_bits;
406 struct intel_crtc *crtc;
408 struct drm_mm_node compressed_fb;
409 struct drm_mm_node compressed_llb;
419 bool underrun_detected;
420 struct work_struct underrun_work;
423 * Due to the atomic rules we can't access some structures without the
424 * appropriate locking, so we cache information here in order to avoid
427 struct intel_fbc_state_cache {
429 unsigned int mode_flags;
430 u32 hsw_bdw_pixel_rate;
434 unsigned int rotation;
439 * Display surface base address adjustement for
440 * pageflips. Note that on gen4+ this only adjusts up
441 * to a tile, offsets within a tile are handled in
442 * the hw itself (with the TILEOFF register).
447 u16 pixel_blend_mode;
451 const struct drm_format_info *format;
456 unsigned int fence_y_offset;
457 u16 gen9_wa_cfb_stride;
464 * This structure contains everything that's relevant to program the
465 * hardware registers. When we want to figure out if we need to disable
466 * and re-enable FBC for a new configuration we just check if there's
467 * something different in the struct. The genx_fbc_activate functions
468 * are supposed to read from it in order to program the registers.
470 struct intel_fbc_reg_params {
473 enum i9xx_plane_id i9xx_plane;
477 const struct drm_format_info *format;
483 unsigned int fence_y_offset;
484 u16 gen9_wa_cfb_stride;
490 const char *no_fbc_reason;
494 * HIGH_RR is the highest eDP panel refresh rate read from EDID
495 * LOW_RR is the lowest eDP panel refresh rate found from EDID
496 * parsing for same resolution.
498 enum drrs_refresh_rate_type {
501 DRRS_MAX_RR, /* RR count */
504 enum drrs_support_type {
505 DRRS_NOT_SUPPORTED = 0,
506 STATIC_DRRS_SUPPORT = 1,
507 SEAMLESS_DRRS_SUPPORT = 2
513 struct delayed_work work;
515 unsigned busy_frontbuffer_bits;
516 enum drrs_refresh_rate_type refresh_rate_type;
517 enum drrs_support_type type;
520 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
521 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
522 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
523 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
524 #define QUIRK_INCREASE_T12_DELAY (1<<6)
525 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
526 #define QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK (1<<8)
529 struct intel_fbc_work;
532 struct i2c_adapter adapter;
533 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
537 struct i2c_algo_bit_data bit_algo;
538 struct drm_i915_private *dev_priv;
541 struct i915_suspend_saved_registers {
549 struct vlv_s0ix_state;
551 #define MAX_L3_SLICES 2
552 struct intel_l3_parity {
553 u32 *remap_info[MAX_L3_SLICES];
554 struct work_struct error_work;
560 * Shortcut for the stolen region. This points to either
561 * INTEL_REGION_STOLEN_SMEM for integrated platforms, or
562 * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't
565 struct intel_memory_region *stolen_region;
566 /** Memory allocator for GTT stolen memory */
567 struct drm_mm stolen;
568 /** Protects the usage of the GTT stolen memory allocator. This is
569 * always the inner lock when overlapping with struct_mutex. */
570 struct mutex stolen_lock;
572 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
576 * List of objects which are purgeable.
578 struct list_head purge_list;
581 * List of objects which have allocated pages and are shrinkable.
583 struct list_head shrink_list;
586 * List of objects which are pending destruction.
588 struct llist_head free_list;
589 struct work_struct free_work;
591 * Count of objects pending destructions. Used to skip needlessly
592 * waiting on an RCU barrier if no objects are waiting to be freed.
597 * tmpfs instance used for shmem backed objects
599 struct vfsmount *gemfs;
601 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
603 struct notifier_block oom_notifier;
604 struct notifier_block vmap_notifier;
605 struct shrinker shrinker;
607 #ifdef CONFIG_MMU_NOTIFIER
609 * notifier_lock for mmu notifiers, memory may not be allocated
610 * while holding this lock.
612 rwlock_t notifier_lock;
615 /* shrinker accounting, also useful for userland debugging */
620 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
622 unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915,
625 static inline unsigned long
626 i915_fence_timeout(const struct drm_i915_private *i915)
628 return i915_fence_context_timeout(i915, U64_MAX);
631 /* Amount of SAGV/QGV points, BSpec precisely defines this */
632 #define I915_NUM_QGV_POINTS 8
634 #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
636 struct ddi_vbt_port_info {
637 /* Non-NULL if port present. */
638 struct intel_bios_encoder_data *devdata;
642 /* This is an index in the HDMI/DVI DDI buffer translation table. */
644 u8 hdmi_level_shift_set:1;
646 u8 alternate_aux_channel;
647 u8 alternate_ddc_pin;
649 int dp_max_link_rate; /* 0 for not limited by VBT */
652 enum psr_lines_to_wait {
653 PSR_0_LINES_TO_WAIT = 0,
659 struct intel_vbt_data {
663 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
664 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
667 unsigned int int_tv_support:1;
668 unsigned int lvds_dither:1;
669 unsigned int int_crt_support:1;
670 unsigned int lvds_use_ssc:1;
671 unsigned int int_lvds_support:1;
672 unsigned int display_clock_mode:1;
673 unsigned int fdi_rx_polarity_inverted:1;
674 unsigned int panel_type:4;
676 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
677 enum drm_panel_orientation orientation;
679 enum drrs_support_type drrs_type;
689 struct edp_power_seq pps;
696 bool require_aux_wakeup;
698 enum psr_lines_to_wait lines_to_wait;
699 int tp1_wakeup_time_us;
700 int tp2_tp3_wakeup_time_us;
701 int psr2_tp2_tp3_wakeup_time_us;
708 u8 min_brightness; /* min_brightness/255 of max */
709 u8 controller; /* brightness controller number */
710 enum intel_backlight_type type;
716 struct mipi_config *config;
717 struct mipi_pps_data *pps;
723 const u8 *sequence[MIPI_SEQ_MAX];
724 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
725 enum drm_panel_orientation orientation;
730 struct list_head display_devices;
732 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
733 struct sdvo_device_mapping sdvo_mappings[2];
736 enum intel_ddb_partitioning {
738 INTEL_DDB_PART_5_6, /* IVB+ */
741 struct ilk_wm_values {
746 enum intel_ddb_partitioning partitioning;
750 u16 plane[I915_MAX_PLANES];
760 struct vlv_wm_ddl_values {
761 u8 plane[I915_MAX_PLANES];
764 struct vlv_wm_values {
765 struct g4x_pipe_wm pipe[3];
767 struct vlv_wm_ddl_values ddl[3];
772 struct g4x_wm_values {
773 struct g4x_pipe_wm pipe[2];
775 struct g4x_sr_wm hpll;
781 struct skl_ddb_entry {
782 u16 start, end; /* in number of blocks, 'end' is exclusive */
785 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
787 return entry->end - entry->start;
790 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
791 const struct skl_ddb_entry *e2)
793 if (e1->start == e2->start && e1->end == e2->end)
799 struct i915_frontbuffer_tracking {
803 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
810 struct i915_virtual_gpu {
811 struct mutex lock; /* serialises sending of g2v_notify command pkts */
816 struct intel_cdclk_config {
817 unsigned int cdclk, vco, ref, bypass;
821 struct i915_selftest_stash {
823 struct ida mock_region_instances;
826 struct drm_i915_private {
827 struct drm_device drm;
829 /* FIXME: Device release actions should all be moved to drmm_ */
832 /* i915 device parameters */
833 struct i915_params params;
835 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
836 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
837 struct intel_driver_caps caps;
840 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
841 * end of stolen which we can optionally use to create GEM objects
842 * backed by stolen memory. Note that stolen_usable_size tells us
843 * exactly how much of this we are actually allowed to use, given that
844 * some portion of it is in fact reserved for use by hardware functions.
848 * Reseved portion of Data Stolen Memory
850 struct resource dsm_reserved;
853 * Stolen memory is segmented in hardware with different portions
854 * offlimits to certain functions.
856 * The drm_mm is initialised to the total accessible range, as found
857 * from the PCI config. On Broadwell+, this is further restricted to
858 * avoid the first page! The upper end of stolen memory is reserved for
859 * hardware functions and similarly removed from the accessible range.
861 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
863 struct intel_uncore uncore;
864 struct intel_uncore_mmio_debug mmio_debug;
866 struct i915_virtual_gpu vgpu;
868 struct intel_gvt *gvt;
870 struct intel_wopcm wopcm;
872 struct intel_dmc dmc;
874 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
876 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
877 * controller on different i2c buses. */
878 struct mutex gmbus_mutex;
881 * Base address of where the gmbus and gpio blocks are located (either
882 * on PCH or on SoC for platforms without PCH).
886 u32 hsw_psr_mmio_adjust;
888 /* MMIO base address for MIPI regs */
893 wait_queue_head_t gmbus_wait_queue;
895 struct pci_dev *bridge_dev;
897 struct rb_root uabi_engines;
899 struct resource mch_res;
901 /* protects the irq masks */
904 bool display_irqs_enabled;
906 /* Sideband mailbox protection */
907 struct mutex sb_lock;
908 struct pm_qos_request sb_qos;
910 /** Cached value of IMR to avoid reads in updating the bitfield */
913 u32 de_irq_mask[I915_MAX_PIPES];
915 u32 pipestat_irq_mask[I915_MAX_PIPES];
917 struct i915_hotplug hotplug;
918 struct intel_fbc fbc;
919 struct i915_drrs drrs;
920 struct intel_opregion opregion;
921 struct intel_vbt_data vbt;
923 bool preserve_bios_swizzle;
926 struct intel_overlay *overlay;
928 /* backlight registers and fields in struct intel_panel */
929 struct mutex backlight_lock;
931 /* protects panel power sequencer state */
932 struct mutex pps_mutex;
934 unsigned int fsb_freq, mem_freq, is_ddr3;
935 unsigned int skl_preferred_vco_freq;
936 unsigned int max_cdclk_freq;
938 unsigned int max_dotclk_freq;
939 unsigned int hpll_freq;
940 unsigned int fdi_pll_freq;
941 unsigned int czclk_freq;
944 /* The current hardware cdclk configuration */
945 struct intel_cdclk_config hw;
947 /* cdclk, divider, and ratio table from bspec */
948 const struct intel_cdclk_vals *table;
950 struct intel_global_obj obj;
954 /* The current hardware dbuf configuration */
957 struct intel_global_obj obj;
961 * wq - Driver workqueue for GEM.
963 * NOTE: Work items scheduled here are not allowed to grab any modeset
964 * locks, for otherwise the flushing done in the pageflip code will
965 * result in deadlocks.
967 struct workqueue_struct *wq;
969 /* ordered wq for modesets */
970 struct workqueue_struct *modeset_wq;
971 /* unbound hipri wq for page flips/plane updates */
972 struct workqueue_struct *flip_wq;
974 /* Display functions */
975 struct drm_i915_display_funcs display;
977 /* PCH chipset type */
978 enum intel_pch pch_type;
979 unsigned short pch_id;
981 unsigned long quirks;
983 struct drm_atomic_state *modeset_restore_state;
984 struct drm_modeset_acquire_ctx reset_ctx;
986 struct i915_ggtt ggtt; /* VM representing the global address space */
988 struct i915_gem_mm mm;
990 /* Kernel Modesetting */
992 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
993 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
996 * dpll and cdclk state is protected by connection_mutex
997 * dpll.lock serializes intel_{prepare,enable,disable}_shared_dpll.
998 * Must be global rather than per dpll, because on some platforms plls
1004 int num_shared_dpll;
1005 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1006 const struct intel_dpll_mgr *mgr;
1014 struct list_head global_obj_list;
1017 * For reading active_pipes holding any crtc lock is
1018 * sufficient, for writing must hold all of them.
1022 struct i915_wa_list gt_wa_list;
1024 struct i915_frontbuffer_tracking fb_tracking;
1026 struct intel_atomic_helper {
1027 struct llist_head free_list;
1028 struct work_struct free_work;
1031 bool mchbar_need_disable;
1033 struct intel_l3_parity l3_parity;
1036 * HTI (aka HDPORT) state read during initial hw readout. Most
1037 * platforms don't have HTI, so this will just stay 0. Those that do
1038 * will use this later to figure out which PLLs and PHYs are unavailable
1045 * Cannot be determined by PCIID. You must always read a register.
1049 struct i915_power_domains power_domains;
1051 struct i915_gpu_error gpu_error;
1053 struct drm_i915_gem_object *vlv_pctx;
1055 /* list of fbdev register on this device */
1056 struct intel_fbdev *fbdev;
1057 struct work_struct fbdev_suspend_work;
1059 struct drm_property *broadcast_rgb_property;
1060 struct drm_property *force_audio_property;
1062 /* hda/i915 audio component */
1063 struct i915_audio_component *audio_component;
1064 bool audio_component_registered;
1066 * av_mutex - mutex for audio/video sync
1069 struct mutex av_mutex;
1070 int audio_power_refcount;
1071 u32 audio_freq_cntrl;
1075 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1076 u32 chv_phy_control;
1078 * Shadows for CHV DPLL_MD regs to keep the state
1079 * checker somewhat working in the presence hardware
1080 * crappiness (can't read out DPLL_MD for pipes B & C).
1082 u32 chv_dpll_md[I915_MAX_PIPES];
1086 bool power_domains_suspended;
1087 struct i915_suspend_saved_registers regfile;
1088 struct vlv_s0ix_state *vlv_s0ix_state;
1091 I915_SAGV_UNKNOWN = 0,
1094 I915_SAGV_NOT_CONTROLLED
1097 u32 sagv_block_time_us;
1101 * Raw watermark latency values:
1102 * in 0.1us units for WM0,
1103 * in 0.5us units for WM1+.
1112 * Raw watermark memory latency values
1113 * for SKL for all 8 levels
1118 /* current hardware state */
1120 struct ilk_wm_values hw;
1121 struct vlv_wm_values vlv;
1122 struct g4x_wm_values g4x;
1128 * Should be held around atomic WM register writing; also
1129 * protects * intel_crtc->wm.active and
1130 * crtc_state->wm.need_postvbl_update.
1132 struct mutex wm_mutex;
1136 bool wm_lv_0_adjust_needed;
1138 bool symmetric_memory;
1139 enum intel_dram_type {
1151 struct intel_bw_info {
1152 /* for each QGV point */
1153 unsigned int deratedbw[I915_NUM_QGV_POINTS];
1158 struct intel_global_obj bw_obj;
1160 struct intel_runtime_pm runtime_pm;
1162 struct i915_perf perf;
1164 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1168 struct i915_gem_contexts {
1169 spinlock_t lock; /* locks list */
1170 struct list_head list;
1174 * We replace the local file with a global mappings as the
1175 * backing storage for the mmap is on the device and not
1176 * on the struct file, and we do not want to prolong the
1177 * lifetime of the local fd. To minimise the number of
1178 * anonymous inodes we create, we use a global singleton to
1179 * share the global mapping.
1181 struct file *mmap_singleton;
1184 u8 framestart_delay;
1186 /* Window2 specifies time required to program DSB (Window2) in number of scan lines */
1191 /* For i915gm/i945gm vblank irq workaround */
1196 /* perform PHY state sanity checks? */
1197 bool chv_phy_assert[2];
1201 /* Used to save the pipe-to-encoder mapping for audio */
1202 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
1204 /* necessary resource sharing with HDMI LPE audio driver. */
1206 struct platform_device *platdev;
1210 struct i915_pmu pmu;
1212 struct i915_hdcp_comp_master *hdcp_master;
1213 bool hdcp_comp_added;
1215 /* Mutex to protect the above hdcp component related values. */
1216 struct mutex hdcp_comp_mutex;
1218 /* The TTM device structure. */
1219 struct ttm_device bdev;
1221 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
1224 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1225 * will be rejected. Instead look for a better place.
1229 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1231 return container_of(dev, struct drm_i915_private, drm);
1234 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
1236 return dev_get_drvdata(kdev);
1239 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
1241 return pci_get_drvdata(pdev);
1244 /* Simple iterator over all initialised engines */
1245 #define for_each_engine(engine__, dev_priv__, id__) \
1247 (id__) < I915_NUM_ENGINES; \
1249 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
1251 /* Iterator over subset of engines selected by mask */
1252 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
1253 for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
1255 ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
1258 #define rb_to_uabi_engine(rb) \
1259 rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
1261 #define for_each_uabi_engine(engine__, i915__) \
1262 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
1264 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
1266 #define for_each_uabi_class_engine(engine__, class__, i915__) \
1267 for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \
1268 (engine__) && (engine__)->uabi_class == (class__); \
1269 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
1271 #define I915_GTT_OFFSET_NONE ((u32)-1)
1274 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1275 * considered to be the frontbuffer for the given plane interface-wise. This
1276 * doesn't mean that the hw necessarily already scans it out, but that any
1277 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1279 * We have one bit per pipe and per scanout plane type.
1281 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
1282 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
1283 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
1284 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
1285 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
1287 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1288 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1289 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1290 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
1291 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1293 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info)
1294 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
1295 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
1297 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
1299 #define IP_VER(ver, rel) ((ver) << 8 | (rel))
1301 #define GRAPHICS_VER(i915) (INTEL_INFO(i915)->graphics_ver)
1302 #define GRAPHICS_VER_FULL(i915) IP_VER(INTEL_INFO(i915)->graphics_ver, \
1303 INTEL_INFO(i915)->graphics_rel)
1304 #define IS_GRAPHICS_VER(i915, from, until) \
1305 (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
1307 #define MEDIA_VER(i915) (INTEL_INFO(i915)->media_ver)
1308 #define MEDIA_VER_FULL(i915) IP_VER(INTEL_INFO(i915)->media_ver, \
1309 INTEL_INFO(i915)->media_rel)
1310 #define IS_MEDIA_VER(i915, from, until) \
1311 (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
1313 #define DISPLAY_VER(i915) (INTEL_INFO(i915)->display.ver)
1314 #define IS_DISPLAY_VER(i915, from, until) \
1315 (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
1317 #define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision)
1319 #define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb)
1321 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
1322 #define INTEL_GT_STEP(__i915) (RUNTIME_INFO(__i915)->step.gt_step)
1324 #define IS_DISPLAY_STEP(__i915, since, until) \
1325 (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
1326 INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) <= (until))
1328 #define IS_GT_STEP(__i915, since, until) \
1329 (drm_WARN_ON(&(__i915)->drm, INTEL_GT_STEP(__i915) == STEP_NONE), \
1330 INTEL_GT_STEP(__i915) >= (since) && INTEL_GT_STEP(__i915) < (until))
1332 static __always_inline unsigned int
1333 __platform_mask_index(const struct intel_runtime_info *info,
1334 enum intel_platform p)
1336 const unsigned int pbits =
1337 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1339 /* Expand the platform_mask array if this fails. */
1340 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
1341 pbits * ARRAY_SIZE(info->platform_mask));
1346 static __always_inline unsigned int
1347 __platform_mask_bit(const struct intel_runtime_info *info,
1348 enum intel_platform p)
1350 const unsigned int pbits =
1351 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1353 return p % pbits + INTEL_SUBPLATFORM_BITS;
1357 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
1359 const unsigned int pi = __platform_mask_index(info, p);
1361 return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK;
1364 static __always_inline bool
1365 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
1367 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1368 const unsigned int pi = __platform_mask_index(info, p);
1369 const unsigned int pb = __platform_mask_bit(info, p);
1371 BUILD_BUG_ON(!__builtin_constant_p(p));
1373 return info->platform_mask[pi] & BIT(pb);
1376 static __always_inline bool
1377 IS_SUBPLATFORM(const struct drm_i915_private *i915,
1378 enum intel_platform p, unsigned int s)
1380 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1381 const unsigned int pi = __platform_mask_index(info, p);
1382 const unsigned int pb = __platform_mask_bit(info, p);
1383 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
1384 const u32 mask = info->platform_mask[pi];
1386 BUILD_BUG_ON(!__builtin_constant_p(p));
1387 BUILD_BUG_ON(!__builtin_constant_p(s));
1388 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
1390 /* Shift and test on the MSB position so sign flag can be used. */
1391 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
1394 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
1395 #define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx)
1397 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
1398 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
1399 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
1400 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
1401 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
1402 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
1403 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
1404 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
1405 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
1406 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
1407 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
1408 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
1409 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
1410 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
1411 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
1412 #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
1413 #define IS_IRONLAKE_M(dev_priv) \
1414 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
1415 #define IS_SANDYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE)
1416 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
1417 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
1418 INTEL_INFO(dev_priv)->gt == 1)
1419 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
1420 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
1421 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
1422 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
1423 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
1424 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
1425 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
1426 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
1427 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
1428 #define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
1429 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
1430 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
1431 #define IS_JSL_EHL(dev_priv) (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \
1432 IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
1433 #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
1434 #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
1435 #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1)
1436 #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
1437 #define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
1438 #define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV)
1439 #define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG2)
1440 #define IS_DG2_G10(dev_priv) \
1441 IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
1442 #define IS_DG2_G11(dev_priv) \
1443 IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
1444 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
1445 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
1446 #define IS_BDW_ULT(dev_priv) \
1447 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
1448 #define IS_BDW_ULX(dev_priv) \
1449 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
1450 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
1451 INTEL_INFO(dev_priv)->gt == 3)
1452 #define IS_HSW_ULT(dev_priv) \
1453 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
1454 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
1455 INTEL_INFO(dev_priv)->gt == 3)
1456 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \
1457 INTEL_INFO(dev_priv)->gt == 1)
1458 /* ULX machines are also considered ULT. */
1459 #define IS_HSW_ULX(dev_priv) \
1460 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
1461 #define IS_SKL_ULT(dev_priv) \
1462 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
1463 #define IS_SKL_ULX(dev_priv) \
1464 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
1465 #define IS_KBL_ULT(dev_priv) \
1466 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
1467 #define IS_KBL_ULX(dev_priv) \
1468 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
1469 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
1470 INTEL_INFO(dev_priv)->gt == 2)
1471 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
1472 INTEL_INFO(dev_priv)->gt == 3)
1473 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
1474 INTEL_INFO(dev_priv)->gt == 4)
1475 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
1476 INTEL_INFO(dev_priv)->gt == 2)
1477 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
1478 INTEL_INFO(dev_priv)->gt == 3)
1479 #define IS_CFL_ULT(dev_priv) \
1480 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
1481 #define IS_CFL_ULX(dev_priv) \
1482 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
1483 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
1484 INTEL_INFO(dev_priv)->gt == 2)
1485 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
1486 INTEL_INFO(dev_priv)->gt == 3)
1488 #define IS_CML_ULT(dev_priv) \
1489 IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
1490 #define IS_CML_ULX(dev_priv) \
1491 IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
1492 #define IS_CML_GT2(dev_priv) (IS_COMETLAKE(dev_priv) && \
1493 INTEL_INFO(dev_priv)->gt == 2)
1495 #define IS_CNL_WITH_PORT_F(dev_priv) \
1496 IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
1497 #define IS_ICL_WITH_PORT_F(dev_priv) \
1498 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
1500 #define IS_TGL_U(dev_priv) \
1501 IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULT)
1503 #define IS_TGL_Y(dev_priv) \
1504 IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULX)
1506 #define IS_SKL_GT_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GT_STEP(p, since, until))
1508 #define IS_KBL_GT_STEP(dev_priv, since, until) \
1509 (IS_KABYLAKE(dev_priv) && IS_GT_STEP(dev_priv, since, until))
1510 #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
1511 (IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until))
1513 #define IS_JSL_EHL_GT_STEP(p, since, until) \
1514 (IS_JSL_EHL(p) && IS_GT_STEP(p, since, until))
1515 #define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
1516 (IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))
1518 #define IS_TGL_DISPLAY_STEP(__i915, since, until) \
1519 (IS_TIGERLAKE(__i915) && \
1520 IS_DISPLAY_STEP(__i915, since, until))
1522 #define IS_TGL_UY_GT_STEP(__i915, since, until) \
1523 ((IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \
1524 IS_GT_STEP(__i915, since, until))
1526 #define IS_TGL_GT_STEP(__i915, since, until) \
1527 (IS_TIGERLAKE(__i915) && !(IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \
1528 IS_GT_STEP(__i915, since, until))
1530 #define IS_RKL_DISPLAY_STEP(p, since, until) \
1531 (IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
1533 #define IS_DG1_GT_STEP(p, since, until) \
1534 (IS_DG1(p) && IS_GT_STEP(p, since, until))
1535 #define IS_DG1_DISPLAY_STEP(p, since, until) \
1536 (IS_DG1(p) && IS_DISPLAY_STEP(p, since, until))
1538 #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
1539 (IS_ALDERLAKE_S(__i915) && \
1540 IS_DISPLAY_STEP(__i915, since, until))
1542 #define IS_ADLS_GT_STEP(__i915, since, until) \
1543 (IS_ALDERLAKE_S(__i915) && \
1544 IS_GT_STEP(__i915, since, until))
1546 #define IS_ADLP_DISPLAY_STEP(__i915, since, until) \
1547 (IS_ALDERLAKE_P(__i915) && \
1548 IS_DISPLAY_STEP(__i915, since, until))
1550 #define IS_ADLP_GT_STEP(__i915, since, until) \
1551 (IS_ALDERLAKE_P(__i915) && \
1552 IS_GT_STEP(__i915, since, until))
1554 #define IS_XEHPSDV_GT_STEP(__i915, since, until) \
1555 (IS_XEHPSDV(__i915) && IS_GT_STEP(__i915, since, until))
1558 * DG2 hardware steppings are a bit unusual. The hardware design was forked
1559 * to create two variants (G10 and G11) which have distinct workaround sets.
1560 * The G11 fork of the DG2 design resets the GT stepping back to "A0" for its
1561 * first iteration, even though it's more similar to a G10 B0 stepping in terms
1562 * of functionality and workarounds. However the display stepping does not
1563 * reset in the same manner --- a specific stepping like "B0" has a consistent
1564 * meaning regardless of whether it belongs to a G10 or G11 DG2.
1566 * TLDR: All GT workarounds and stepping-specific logic must be applied in
1567 * relation to a specific subplatform (G10 or G11), whereas display workarounds
1568 * and stepping-specific logic will be applied with a general DG2-wide stepping
1571 #define IS_DG2_GT_STEP(__i915, variant, since, until) \
1572 (IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \
1573 IS_GT_STEP(__i915, since, until))
1575 #define IS_DG2_DISP_STEP(__i915, since, until) \
1576 (IS_DG2(__i915) && \
1577 IS_DISPLAY_STEP(__i915, since, until))
1579 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
1580 #define IS_GEN9_LP(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv))
1581 #define IS_GEN9_BC(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv))
1583 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
1584 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
1586 #define ENGINE_INSTANCES_MASK(gt, first, count) ({ \
1587 unsigned int first__ = (first); \
1588 unsigned int count__ = (count); \
1589 ((gt)->info.engine_mask & \
1590 GENMASK(first__ + count__ - 1, first__)) >> first__; \
1592 #define VDBOX_MASK(gt) \
1593 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
1594 #define VEBOX_MASK(gt) \
1595 ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
1598 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
1599 * All later gens can run the final buffer from the ppgtt
1601 #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
1603 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
1604 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
1605 #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
1606 #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
1607 #define HAS_WT(dev_priv) HAS_EDRAM(dev_priv)
1609 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)
1611 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
1612 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
1613 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
1614 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
1616 #define HAS_MASTER_UNIT_IRQ(dev_priv) (INTEL_INFO(dev_priv)->has_master_unit_irq)
1618 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
1620 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
1621 #define HAS_PPGTT(dev_priv) \
1622 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
1623 #define HAS_FULL_PPGTT(dev_priv) \
1624 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
1626 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
1627 GEM_BUG_ON((sizes) == 0); \
1628 ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
1631 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay)
1632 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
1633 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
1635 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1636 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
1638 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \
1639 (IS_BROADWELL(dev_priv) || GRAPHICS_VER(dev_priv) == 9)
1641 /* WaRsDisableCoarsePowerGating:skl,cnl */
1642 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
1643 (IS_CANNONLAKE(dev_priv) || \
1644 IS_SKL_GT3(dev_priv) || \
1645 IS_SKL_GT4(dev_priv))
1647 #define HAS_GMBUS_IRQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 4)
1648 #define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 10 || \
1649 IS_GEMINILAKE(dev_priv) || \
1650 IS_KABYLAKE(dev_priv))
1652 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1653 * rows, which changed the alignment requirements and fence programming.
1655 #define HAS_128_BYTE_Y_TILING(dev_priv) (GRAPHICS_VER(dev_priv) != 2 && \
1656 !(IS_I915G(dev_priv) || IS_I915GM(dev_priv)))
1657 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv)
1658 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
1660 #define HAS_FW_BLC(dev_priv) (GRAPHICS_VER(dev_priv) > 2)
1661 #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc)
1662 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && GRAPHICS_VER(dev_priv) >= 7)
1664 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
1666 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst)
1668 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
1669 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
1670 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
1671 #define HAS_PSR_HW_TRACKING(dev_priv) \
1672 (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
1673 #define HAS_PSR2_SEL_FETCH(dev_priv) (GRAPHICS_VER(dev_priv) >= 12)
1674 #define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
1676 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
1677 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
1678 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
1680 #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps)
1682 #define HAS_DMC(dev_priv) (INTEL_INFO(dev_priv)->display.has_dmc)
1684 #define HAS_MSO(i915) (GRAPHICS_VER(i915) >= 12)
1686 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
1687 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
1689 #define HAS_MSLICES(dev_priv) \
1690 (INTEL_INFO(dev_priv)->has_mslices)
1692 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
1694 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
1695 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
1697 #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc)
1699 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
1701 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs)
1704 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
1706 #define HAS_LSPCON(dev_priv) (IS_GRAPHICS_VER(dev_priv, 9, 10))
1708 /* DPF == dynamic parity feature */
1709 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
1710 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
1711 2 : HAS_L3_DPF(dev_priv))
1713 #define GT_FREQUENCY_MULTIPLIER 50
1714 #define GEN9_FREQ_SCALER 3
1716 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
1718 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
1720 #define HAS_VRR(i915) (GRAPHICS_VER(i915) >= 12)
1722 /* Only valid when HAS_DISPLAY() is true */
1723 #define INTEL_DISPLAY_ENABLED(dev_priv) \
1724 (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display)
1726 static inline bool run_as_guest(void)
1728 return !hypervisor_is_type(X86_HYPER_NATIVE);
1731 #define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
1732 IS_ALDERLAKE_S(dev_priv))
1734 static inline bool intel_vtd_active(void)
1736 #ifdef CONFIG_INTEL_IOMMU
1737 if (intel_iommu_gfx_mapped)
1741 /* Running as a guest, we assume the host is enforcing VT'd */
1742 return run_as_guest();
1745 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
1747 return GRAPHICS_VER(dev_priv) >= 6 && intel_vtd_active();
1751 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *i915)
1753 return IS_BROXTON(i915) && intel_vtd_active();
1757 intel_vm_no_concurrent_access_wa(struct drm_i915_private *i915)
1759 return IS_CHERRYVIEW(i915) || intel_ggtt_update_needs_vtd_wa(i915);
1763 extern const struct dev_pm_ops i915_pm_ops;
1765 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
1766 void i915_driver_remove(struct drm_i915_private *i915);
1767 void i915_driver_shutdown(struct drm_i915_private *i915);
1769 int i915_resume_switcheroo(struct drm_i915_private *i915);
1770 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state);
1772 int i915_getparam_ioctl(struct drm_device *dev, void *data,
1773 struct drm_file *file_priv);
1776 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
1777 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
1778 void i915_gem_init_early(struct drm_i915_private *dev_priv);
1779 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
1781 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
1784 * A single pass should suffice to release all the freed objects (along
1785 * most call paths) , but be a little more paranoid in that freeing
1786 * the objects does take a little amount of time, during which the rcu
1787 * callbacks could have added new objects into the freed list, and
1788 * armed the work again.
1790 while (atomic_read(&i915->mm.free_count)) {
1791 flush_work(&i915->mm.free_work);
1796 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
1799 * Similar to objects above (see i915_gem_drain_freed-objects), in
1800 * general we have workers that are armed by RCU and then rearm
1801 * themselves in their callbacks. To be paranoid, we need to
1802 * drain the workqueue a second time after waiting for the RCU
1803 * grace period so that we catch work queued via RCU from the first
1804 * pass. As neither drain_workqueue() nor flush_workqueue() report
1805 * a result, we make an assumption that we only don't require more
1806 * than 3 passes to catch all _recursive_ RCU delayed work.
1811 flush_workqueue(i915->wq);
1813 i915_gem_drain_freed_objects(i915);
1815 drain_workqueue(i915->wq);
1818 struct i915_vma * __must_check
1819 i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj,
1820 struct i915_gem_ww_ctx *ww,
1821 const struct i915_ggtt_view *view,
1822 u64 size, u64 alignment, u64 flags);
1824 static inline struct i915_vma * __must_check
1825 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
1826 const struct i915_ggtt_view *view,
1827 u64 size, u64 alignment, u64 flags)
1829 return i915_gem_object_ggtt_pin_ww(obj, NULL, view, size, alignment, flags);
1832 int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
1833 unsigned long flags);
1834 #define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0)
1835 #define I915_GEM_OBJECT_UNBIND_BARRIER BIT(1)
1836 #define I915_GEM_OBJECT_UNBIND_TEST BIT(2)
1837 #define I915_GEM_OBJECT_UNBIND_VM_TRYLOCK BIT(3)
1839 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
1841 int i915_gem_dumb_create(struct drm_file *file_priv,
1842 struct drm_device *dev,
1843 struct drm_mode_create_dumb *args);
1845 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
1847 static inline u32 i915_reset_count(struct i915_gpu_error *error)
1849 return atomic_read(&error->reset_count);
1852 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
1853 const struct intel_engine_cs *engine)
1855 return atomic_read(&error->reset_engine_count[engine->uabi_class]);
1858 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
1859 void i915_gem_driver_register(struct drm_i915_private *i915);
1860 void i915_gem_driver_unregister(struct drm_i915_private *i915);
1861 void i915_gem_driver_remove(struct drm_i915_private *dev_priv);
1862 void i915_gem_driver_release(struct drm_i915_private *dev_priv);
1863 void i915_gem_suspend(struct drm_i915_private *dev_priv);
1864 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
1865 void i915_gem_resume(struct drm_i915_private *dev_priv);
1867 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
1869 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1870 enum i915_cache_level cache_level);
1872 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1873 struct dma_buf *dma_buf);
1875 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags);
1877 static inline struct i915_address_space *
1878 i915_gem_vm_lookup(struct drm_i915_file_private *file_priv, u32 id)
1880 struct i915_address_space *vm;
1883 vm = xa_load(&file_priv->vm_xa, id);
1884 if (vm && !kref_get_unless_zero(&vm->ref))
1891 /* i915_gem_evict.c */
1892 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
1893 u64 min_size, u64 alignment,
1894 unsigned long color,
1897 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
1898 struct drm_mm_node *node,
1899 unsigned int flags);
1900 int i915_gem_evict_vm(struct i915_address_space *vm);
1902 /* i915_gem_internal.c */
1903 struct drm_i915_gem_object *
1904 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
1907 /* i915_gem_tiling.c */
1908 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1910 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1912 return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1913 i915_gem_object_is_tiled(obj);
1916 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
1917 unsigned int tiling, unsigned int stride);
1918 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
1919 unsigned int tiling, unsigned int stride);
1921 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
1923 /* i915_cmd_parser.c */
1924 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
1925 int intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
1926 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
1927 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
1928 struct i915_vma *batch,
1929 unsigned long batch_offset,
1930 unsigned long batch_length,
1931 struct i915_vma *shadow,
1933 #define I915_CMD_PARSER_TRAMPOLINE_SIZE 8
1935 /* intel_device_info.c */
1936 static inline struct intel_device_info *
1937 mkwrite_device_info(struct drm_i915_private *dev_priv)
1939 return (struct intel_device_info *)INTEL_INFO(dev_priv);
1942 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1943 struct drm_file *file);
1946 int remap_io_mapping(struct vm_area_struct *vma,
1947 unsigned long addr, unsigned long pfn, unsigned long size,
1948 struct io_mapping *iomap);
1949 int remap_io_sg(struct vm_area_struct *vma,
1950 unsigned long addr, unsigned long size,
1951 struct scatterlist *sgl, resource_size_t iobase);
1953 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
1955 if (GRAPHICS_VER(i915) >= 11)
1956 return ICL_HWS_CSB_WRITE_INDEX;
1958 return I915_HWS_CSB_WRITE_INDEX;
1961 static inline enum i915_map_type
1962 i915_coherent_map_type(struct drm_i915_private *i915,
1963 struct drm_i915_gem_object *obj, bool always_coherent)
1965 if (i915_gem_object_is_lmem(obj))
1967 if (HAS_LLC(i915) || always_coherent)