drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vga_switcheroo.h>
  40 #include <linux/vt.h>
  41
  42 #include <drm/drm_atomic_helper.h>
  43 #include <drm/drm_ioctl.h>
  44 #include <drm/drm_irq.h>
  45 #include <drm/drm_managed.h>
  46 #include <drm/drm_probe_helper.h>
  47
  48 #include "display/intel_acpi.h"
  49 #include "display/intel_bw.h"
  50 #include "display/intel_cdclk.h"
  51 #include "display/intel_csr.h"
  52 #include "display/intel_display_types.h"
  53 #include "display/intel_dp.h"
  54 #include "display/intel_fbdev.h"
  55 #include "display/intel_hotplug.h"
  56 #include "display/intel_overlay.h"
  57 #include "display/intel_pipe_crc.h"
  58 #include "display/intel_pps.h"
  59 #include "display/intel_sprite.h"
  60 #include "display/intel_vga.h"
  61
  62 #include "gem/i915_gem_context.h"
  63 #include "gem/i915_gem_ioctls.h"
  64 #include "gem/i915_gem_mman.h"
  65 #include "gem/i915_gem_pm.h"
  66 #include "gt/intel_gt.h"
  67 #include "gt/intel_gt_pm.h"
  68 #include "gt/intel_rc6.h"
  69
  70 #include "i915_debugfs.h"
  71 #include "i915_drv.h"
  72 #include "i915_ioc32.h"
  73 #include "i915_irq.h"
  74 #include "i915_memcpy.h"
  75 #include "i915_perf.h"
  76 #include "i915_query.h"
  77 #include "i915_suspend.h"
  78 #include "i915_switcheroo.h"
  79 #include "i915_sysfs.h"
  80 #include "i915_trace.h"
  81 #include "i915_vgpu.h"
  82 #include "intel_dram.h"
  83 #include "intel_gvt.h"
  84 #include "intel_memory_region.h"
  85 #include "intel_pm.h"
  86 #include "intel_sideband.h"
  87 #include "vlv_suspend.h"
  88
  89 static const struct drm_driver driver;
  90
  91 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
  92 {
  93         int domain = pci_domain_nr(to_pci_dev(dev_priv->drm.dev)->bus);
  94
  95         dev_priv->bridge_dev =
  96                 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
  97         if (!dev_priv->bridge_dev) {
  98                 drm_err(&dev_priv->drm, "bridge device not found\n");
  99                 return -1;
 100         }
 101         return 0;
 102 }
 103
 104 /* Allocate space for the MCH regs if needed, return nonzero on error */
 105 static int
 106 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 107 {
 108         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 109         u32 temp_lo, temp_hi = 0;
 110         u64 mchbar_addr;
 111         int ret;
 112
 113         if (INTEL_GEN(dev_priv) >= 4)
 114                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 115         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 116         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 117
 118         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 119 #ifdef CONFIG_PNP
 120         if (mchbar_addr &&
 121             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 122                 return 0;
 123 #endif
 124
 125         /* Get some space for it */
 126         dev_priv->mch_res.name = "i915 MCHBAR";
 127         dev_priv->mch_res.flags = IORESOURCE_MEM;
 128         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 129                                      &dev_priv->mch_res,
 130                                      MCHBAR_SIZE, MCHBAR_SIZE,
 131                                      PCIBIOS_MIN_MEM,
 132                                      0, pcibios_align_resource,
 133                                      dev_priv->bridge_dev);
 134         if (ret) {
 135                 drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret);
 136                 dev_priv->mch_res.start = 0;
 137                 return ret;
 138         }
 139
 140         if (INTEL_GEN(dev_priv) >= 4)
 141                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 142                                        upper_32_bits(dev_priv->mch_res.start));
 143
 144         pci_write_config_dword(dev_priv->bridge_dev, reg,
 145                                lower_32_bits(dev_priv->mch_res.start));
 146         return 0;
 147 }
 148
 149 /* Setup MCHBAR if possible, return true if we should disable it again */
 150 static void
 151 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 152 {
 153         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 154         u32 temp;
 155         bool enabled;
 156
 157         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 158                 return;
 159
 160         dev_priv->mchbar_need_disable = false;
 161
 162         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 163                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 164                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 165         } else {
 166                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 167                 enabled = temp & 1;
 168         }
 169
 170         /* If it's already enabled, don't have to do anything */
 171         if (enabled)
 172                 return;
 173
 174         if (intel_alloc_mchbar_resource(dev_priv))
 175                 return;
 176
 177         dev_priv->mchbar_need_disable = true;
 178
 179         /* Space is allocated or reserved, so enable it. */
 180         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 181                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 182                                        temp | DEVEN_MCHBAR_EN);
 183         } else {
 184                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 185                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 186         }
 187 }
 188
 189 static void
 190 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 191 {
 192         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 193
 194         if (dev_priv->mchbar_need_disable) {
 195                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 196                         u32 deven_val;
 197
 198                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 199                                               &deven_val);
 200                         deven_val &= ~DEVEN_MCHBAR_EN;
 201                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 202                                                deven_val);
 203                 } else {
 204                         u32 mchbar_val;
 205
 206                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 207                                               &mchbar_val);
 208                         mchbar_val &= ~1;
 209                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 210                                                mchbar_val);
 211                 }
 212         }
 213
 214         if (dev_priv->mch_res.start)
 215                 release_resource(&dev_priv->mch_res);
 216 }
 217
 218 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 219 {
 220         /*
 221          * The i915 workqueue is primarily used for batched retirement of
 222          * requests (and thus managing bo) once the task has been completed
 223          * by the GPU. i915_retire_requests() is called directly when we
 224          * need high-priority retirement, such as waiting for an explicit
 225          * bo.
 226          *
 227          * It is also used for periodic low-priority events, such as
 228          * idle-timers and recording error state.
 229          *
 230          * All tasks on the workqueue are expected to acquire the dev mutex
 231          * so there is no point in running more than one instance of the
 232          * workqueue at any time.  Use an ordered one.
 233          */
 234         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 235         if (dev_priv->wq == NULL)
 236                 goto out_err;
 237
 238         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 239         if (dev_priv->hotplug.dp_wq == NULL)
 240                 goto out_free_wq;
 241
 242         return 0;
 243
 244 out_free_wq:
 245         destroy_workqueue(dev_priv->wq);
 246 out_err:
 247         drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n");
 248
 249         return -ENOMEM;
 250 }
 251
 252 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 253 {
 254         destroy_workqueue(dev_priv->hotplug.dp_wq);
 255         destroy_workqueue(dev_priv->wq);
 256 }
 257
 258 /*
 259  * We don't keep the workarounds for pre-production hardware, so we expect our
 260  * driver to fail on these machines in one way or another. A little warning on
 261  * dmesg may help both the user and the bug triagers.
 262  *
 263  * Our policy for removing pre-production workarounds is to keep the
 264  * current gen workarounds as a guide to the bring-up of the next gen
 265  * (workarounds have a habit of persisting!). Anything older than that
 266  * should be removed along with the complications they introduce.
 267  */
 268 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 269 {
 270         bool pre = false;
 271
 272         pre |= IS_HSW_EARLY_SDV(dev_priv);
 273         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 274         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 275         pre |= IS_KBL_GT_REVID(dev_priv, 0, KBL_REVID_A0);
 276         pre |= IS_GLK_REVID(dev_priv, 0, GLK_REVID_A2);
 277
 278         if (pre) {
 279                 drm_err(&dev_priv->drm, "This is a pre-production stepping. "
 280                           "It may not be fully functional.\n");
 281                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 282         }
 283 }
 284
 285 static void sanitize_gpu(struct drm_i915_private *i915)
 286 {
 287         if (!INTEL_INFO(i915)->gpu_reset_clobbers_display)
 288                 __intel_gt_reset(&i915->gt, ALL_ENGINES);
 289 }
 290
 291 /**
 292  * i915_driver_early_probe - setup state not requiring device access
 293  * @dev_priv: device private
 294  *
 295  * Initialize everything that is a "SW-only" state, that is state not
 296  * requiring accessing the device or exposing the driver via kernel internal
 297  * or userspace interfaces. Example steps belonging here: lock initialization,
 298  * system memory allocation, setting up device specific attributes and
 299  * function hooks not requiring accessing the device.
 300  */
 301 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
 302 {
 303         int ret = 0;
 304
 305         if (i915_inject_probe_failure(dev_priv))
 306                 return -ENODEV;
 307
 308         intel_device_info_subplatform_init(dev_priv);
 309
 310         intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
 311         intel_uncore_init_early(&dev_priv->uncore, dev_priv);
 312
 313         spin_lock_init(&dev_priv->irq_lock);
 314         spin_lock_init(&dev_priv->gpu_error.lock);
 315         mutex_init(&dev_priv->backlight_lock);
 316
 317         mutex_init(&dev_priv->sb_lock);
 318         cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
 319
 320         mutex_init(&dev_priv->av_mutex);
 321         mutex_init(&dev_priv->wm.wm_mutex);
 322         mutex_init(&dev_priv->pps_mutex);
 323         mutex_init(&dev_priv->hdcp_comp_mutex);
 324
 325         i915_memcpy_init_early(dev_priv);
 326         intel_runtime_pm_init_early(&dev_priv->runtime_pm);
 327
 328         ret = i915_workqueues_init(dev_priv);
 329         if (ret < 0)
 330                 return ret;
 331
 332         ret = vlv_suspend_init(dev_priv);
 333         if (ret < 0)
 334                 goto err_workqueues;
 335
 336         intel_wopcm_init_early(&dev_priv->wopcm);
 337
 338         intel_gt_init_early(&dev_priv->gt, dev_priv);
 339
 340         i915_gem_init_early(dev_priv);
 341
 342         /* This must be called before any calls to HAS_PCH_* */
 343         intel_detect_pch(dev_priv);
 344
 345         intel_pm_setup(dev_priv);
 346         ret = intel_power_domains_init(dev_priv);
 347         if (ret < 0)
 348                 goto err_gem;
 349         intel_irq_init(dev_priv);
 350         intel_init_display_hooks(dev_priv);
 351         intel_init_clock_gating_hooks(dev_priv);
 352
 353         intel_detect_preproduction_hw(dev_priv);
 354
 355         return 0;
 356
 357 err_gem:
 358         i915_gem_cleanup_early(dev_priv);
 359         intel_gt_driver_late_release(&dev_priv->gt);
 360         vlv_suspend_cleanup(dev_priv);
 361 err_workqueues:
 362         i915_workqueues_cleanup(dev_priv);
 363         return ret;
 364 }
 365
 366 /**
 367  * i915_driver_late_release - cleanup the setup done in
 368  *                             i915_driver_early_probe()
 369  * @dev_priv: device private
 370  */
 371 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
 372 {
 373         intel_irq_fini(dev_priv);
 374         intel_power_domains_cleanup(dev_priv);
 375         i915_gem_cleanup_early(dev_priv);
 376         intel_gt_driver_late_release(&dev_priv->gt);
 377         vlv_suspend_cleanup(dev_priv);
 378         i915_workqueues_cleanup(dev_priv);
 379
 380         cpu_latency_qos_remove_request(&dev_priv->sb_qos);
 381         mutex_destroy(&dev_priv->sb_lock);
 382
 383         i915_params_free(&dev_priv->params);
 384 }
 385
 386 /**
 387  * i915_driver_mmio_probe - setup device MMIO
 388  * @dev_priv: device private
 389  *
 390  * Setup minimal device state necessary for MMIO accesses later in the
 391  * initialization sequence. The setup here should avoid any other device-wide
 392  * side effects or exposing the driver via kernel internal or user space
 393  * interfaces.
 394  */
 395 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
 396 {
 397         int ret;
 398
 399         if (i915_inject_probe_failure(dev_priv))
 400                 return -ENODEV;
 401
 402         if (i915_get_bridge_dev(dev_priv))
 403                 return -EIO;
 404
 405         ret = intel_uncore_init_mmio(&dev_priv->uncore);
 406         if (ret < 0)
 407                 goto err_bridge;
 408
 409         /* Try to make sure MCHBAR is enabled before poking at it */
 410         intel_setup_mchbar(dev_priv);
 411         intel_device_info_runtime_init(dev_priv);
 412
 413         ret = intel_gt_init_mmio(&dev_priv->gt);
 414         if (ret)
 415                 goto err_uncore;
 416
 417         /* As early as possible, scrub existing GPU state before clobbering */
 418         sanitize_gpu(dev_priv);
 419
 420         return 0;
 421
 422 err_uncore:
 423         intel_teardown_mchbar(dev_priv);
 424         intel_uncore_fini_mmio(&dev_priv->uncore);
 425 err_bridge:
 426         pci_dev_put(dev_priv->bridge_dev);
 427
 428         return ret;
 429 }
 430
 431 /**
 432  * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
 433  * @dev_priv: device private
 434  */
 435 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
 436 {
 437         intel_teardown_mchbar(dev_priv);
 438         intel_uncore_fini_mmio(&dev_priv->uncore);
 439         pci_dev_put(dev_priv->bridge_dev);
 440 }
 441
 442 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 443 {
 444         intel_gvt_sanitize_options(dev_priv);
 445 }
 446
 447 /**
 448  * i915_set_dma_info - set all relevant PCI dma info as configured for the
 449  * platform
 450  * @i915: valid i915 instance
 451  *
 452  * Set the dma max segment size, device and coherent masks.  The dma mask set
 453  * needs to occur before i915_ggtt_probe_hw.
 454  *
 455  * A couple of platforms have special needs.  Address them as well.
 456  *
 457  */
 458 static int i915_set_dma_info(struct drm_i915_private *i915)
 459 {
 460         unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size;
 461         int ret;
 462
 463         GEM_BUG_ON(!mask_size);
 464
 465         /*
 466          * We don't have a max segment size, so set it to the max so sg's
 467          * debugging layer doesn't complain
 468          */
 469         dma_set_max_seg_size(i915->drm.dev, UINT_MAX);
 470
 471         ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
 472         if (ret)
 473                 goto mask_err;
 474
 475         /* overlay on gen2 is broken and can't address above 1G */
 476         if (IS_GEN(i915, 2))
 477                 mask_size = 30;
 478
 479         /*
 480          * 965GM sometimes incorrectly writes to hardware status page (HWS)
 481          * using 32bit addressing, overwriting memory if HWS is located
 482          * above 4GB.
 483          *
 484          * The documentation also mentions an issue with undefined
 485          * behaviour if any general state is accessed within a page above 4GB,
 486          * which also needs to be handled carefully.
 487          */
 488         if (IS_I965G(i915) || IS_I965GM(i915))
 489                 mask_size = 32;
 490
 491         ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
 492         if (ret)
 493                 goto mask_err;
 494
 495         return 0;
 496
 497 mask_err:
 498         drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret);
 499         return ret;
 500 }
 501
 502 /**
 503  * i915_driver_hw_probe - setup state requiring device access
 504  * @dev_priv: device private
 505  *
 506  * Setup state that requires accessing the device, but doesn't require
 507  * exposing the driver via kernel internal or userspace interfaces.
 508  */
 509 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
 510 {
 511         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 512         int ret;
 513
 514         if (i915_inject_probe_failure(dev_priv))
 515                 return -ENODEV;
 516
 517         if (HAS_PPGTT(dev_priv)) {
 518                 if (intel_vgpu_active(dev_priv) &&
 519                     !intel_vgpu_has_full_ppgtt(dev_priv)) {
 520                         i915_report_error(dev_priv,
 521                                           "incompatible vGPU found, support for isolated ppGTT required\n");
 522                         return -ENXIO;
 523                 }
 524         }
 525
 526         if (HAS_EXECLISTS(dev_priv)) {
 527                 /*
 528                  * Older GVT emulation depends upon intercepting CSB mmio,
 529                  * which we no longer use, preferring to use the HWSP cache
 530                  * instead.
 531                  */
 532                 if (intel_vgpu_active(dev_priv) &&
 533                     !intel_vgpu_has_hwsp_emulation(dev_priv)) {
 534                         i915_report_error(dev_priv,
 535                                           "old vGPU host found, support for HWSP emulation required\n");
 536                         return -ENXIO;
 537                 }
 538         }
 539
 540         intel_sanitize_options(dev_priv);
 541
 542         /* needs to be done before ggtt probe */
 543         intel_dram_edram_detect(dev_priv);
 544
 545         ret = i915_set_dma_info(dev_priv);
 546         if (ret)
 547                 return ret;
 548
 549         i915_perf_init(dev_priv);
 550
 551         ret = i915_ggtt_probe_hw(dev_priv);
 552         if (ret)
 553                 goto err_perf;
 554
 555         ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "inteldrmfb");
 556         if (ret)
 557                 goto err_ggtt;
 558
 559         ret = i915_ggtt_init_hw(dev_priv);
 560         if (ret)
 561                 goto err_ggtt;
 562
 563         ret = intel_memory_regions_hw_probe(dev_priv);
 564         if (ret)
 565                 goto err_ggtt;
 566
 567         intel_gt_init_hw_early(&dev_priv->gt, &dev_priv->ggtt);
 568
 569         ret = i915_ggtt_enable_hw(dev_priv);
 570         if (ret) {
 571                 drm_err(&dev_priv->drm, "failed to enable GGTT\n");
 572                 goto err_mem_regions;
 573         }
 574
 575         pci_set_master(pdev);
 576
 577         intel_gt_init_workarounds(dev_priv);
 578
 579         /* On the 945G/GM, the chipset reports the MSI capability on the
 580          * integrated graphics even though the support isn't actually there
 581          * according to the published specs.  It doesn't appear to function
 582          * correctly in testing on 945G.
 583          * This may be a side effect of MSI having been made available for PEG
 584          * and the registers being closely associated.
 585          *
 586          * According to chipset errata, on the 965GM, MSI interrupts may
 587          * be lost or delayed, and was defeatured. MSI interrupts seem to
 588          * get lost on g4x as well, and interrupt delivery seems to stay
 589          * properly dead afterwards. So we'll just disable them for all
 590          * pre-gen5 chipsets.
 591          *
 592          * dp aux and gmbus irq on gen4 seems to be able to generate legacy
 593          * interrupts even when in MSI mode. This results in spurious
 594          * interrupt warnings if the legacy irq no. is shared with another
 595          * device. The kernel then disables that interrupt source and so
 596          * prevents the other device from working properly.
 597          */
 598         if (INTEL_GEN(dev_priv) >= 5) {
 599                 if (pci_enable_msi(pdev) < 0)
 600                         drm_dbg(&dev_priv->drm, "can't enable MSI");
 601         }
 602
 603         ret = intel_gvt_init(dev_priv);
 604         if (ret)
 605                 goto err_msi;
 606
 607         intel_opregion_setup(dev_priv);
 608
 609         intel_pcode_init(dev_priv);
 610
 611         /*
 612          * Fill the dram structure to get the system dram info. This will be
 613          * used for memory latency calculation.
 614          */
 615         intel_dram_detect(dev_priv);
 616
 617         intel_bw_init_hw(dev_priv);
 618
 619         return 0;
 620
 621 err_msi:
 622         if (pdev->msi_enabled)
 623                 pci_disable_msi(pdev);
 624 err_mem_regions:
 625         intel_memory_regions_driver_release(dev_priv);
 626 err_ggtt:
 627         i915_ggtt_driver_release(dev_priv);
 628 err_perf:
 629         i915_perf_fini(dev_priv);
 630         return ret;
 631 }
 632
 633 /**
 634  * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
 635  * @dev_priv: device private
 636  */
 637 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
 638 {
 639         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 640
 641         i915_perf_fini(dev_priv);
 642
 643         if (pdev->msi_enabled)
 644                 pci_disable_msi(pdev);
 645 }
 646
 647 /**
 648  * i915_driver_register - register the driver with the rest of the system
 649  * @dev_priv: device private
 650  *
 651  * Perform any steps necessary to make the driver available via kernel
 652  * internal or userspace interfaces.
 653  */
 654 static void i915_driver_register(struct drm_i915_private *dev_priv)
 655 {
 656         struct drm_device *dev = &dev_priv->drm;
 657
 658         i915_gem_driver_register(dev_priv);
 659         i915_pmu_register(dev_priv);
 660
 661         intel_vgpu_register(dev_priv);
 662
 663         /* Reveal our presence to userspace */
 664         if (drm_dev_register(dev, 0)) {
 665                 drm_err(&dev_priv->drm,
 666                         "Failed to register driver for userspace access!\n");
 667                 return;
 668         }
 669
 670         i915_debugfs_register(dev_priv);
 671         i915_setup_sysfs(dev_priv);
 672
 673         /* Depends on sysfs having been initialized */
 674         i915_perf_register(dev_priv);
 675
 676         intel_gt_driver_register(&dev_priv->gt);
 677
 678         intel_display_driver_register(dev_priv);
 679
 680         intel_power_domains_enable(dev_priv);
 681         intel_runtime_pm_enable(&dev_priv->runtime_pm);
 682
 683         intel_register_dsm_handler();
 684
 685         if (i915_switcheroo_register(dev_priv))
 686                 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n");
 687 }
 688
 689 /**
 690  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
 691  * @dev_priv: device private
 692  */
 693 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
 694 {
 695         i915_switcheroo_unregister(dev_priv);
 696
 697         intel_unregister_dsm_handler();
 698
 699         intel_runtime_pm_disable(&dev_priv->runtime_pm);
 700         intel_power_domains_disable(dev_priv);
 701
 702         intel_display_driver_unregister(dev_priv);
 703
 704         intel_gt_driver_unregister(&dev_priv->gt);
 705
 706         i915_perf_unregister(dev_priv);
 707         i915_pmu_unregister(dev_priv);
 708
 709         i915_teardown_sysfs(dev_priv);
 710         drm_dev_unplug(&dev_priv->drm);
 711
 712         i915_gem_driver_unregister(dev_priv);
 713 }
 714
 715 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
 716 {
 717         if (drm_debug_enabled(DRM_UT_DRIVER)) {
 718                 struct drm_printer p = drm_debug_printer("i915 device info:");
 719
 720                 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
 721                            INTEL_DEVID(dev_priv),
 722                            INTEL_REVID(dev_priv),
 723                            intel_platform_name(INTEL_INFO(dev_priv)->platform),
 724                            intel_subplatform(RUNTIME_INFO(dev_priv),
 725                                              INTEL_INFO(dev_priv)->platform),
 726                            INTEL_GEN(dev_priv));
 727
 728                 intel_device_info_print_static(INTEL_INFO(dev_priv), &p);
 729                 intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p);
 730                 intel_gt_info_print(&dev_priv->gt.info, &p);
 731         }
 732
 733         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
 734                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n");
 735         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
 736                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n");
 737         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
 738                 drm_info(&dev_priv->drm,
 739                          "DRM_I915_DEBUG_RUNTIME_PM enabled\n");
 740 }
 741
 742 static struct drm_i915_private *
 743 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
 744 {
 745         const struct intel_device_info *match_info =
 746                 (struct intel_device_info *)ent->driver_data;
 747         struct intel_device_info *device_info;
 748         struct drm_i915_private *i915;
 749
 750         i915 = devm_drm_dev_alloc(&pdev->dev, &driver,
 751                                   struct drm_i915_private, drm);
 752         if (IS_ERR(i915))
 753                 return i915;
 754
 755         i915->drm.pdev = pdev;
 756         pci_set_drvdata(pdev, i915);
 757
 758         /* Device parameters start as a copy of module parameters. */
 759         i915_params_copy(&i915->params, &i915_modparams);
 760
 761         /* Setup the write-once "constant" device info */
 762         device_info = mkwrite_device_info(i915);
 763         memcpy(device_info, match_info, sizeof(*device_info));
 764         RUNTIME_INFO(i915)->device_id = pdev->device;
 765
 766         BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
 767
 768         return i915;
 769 }
 770
 771 /**
 772  * i915_driver_probe - setup chip and create an initial config
 773  * @pdev: PCI device
 774  * @ent: matching PCI ID entry
 775  *
 776  * The driver probe routine has to do several things:
 777  *   - drive output discovery via intel_modeset_init()
 778  *   - initialize the memory manager
 779  *   - allocate initial config memory
 780  *   - setup the DRM framebuffer with the allocated memory
 781  */
 782 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 783 {
 784         const struct intel_device_info *match_info =
 785                 (struct intel_device_info *)ent->driver_data;
 786         struct drm_i915_private *i915;
 787         int ret;
 788
 789         i915 = i915_driver_create(pdev, ent);
 790         if (IS_ERR(i915))
 791                 return PTR_ERR(i915);
 792
 793         /* Disable nuclear pageflip by default on pre-ILK */
 794         if (!i915->params.nuclear_pageflip && match_info->gen < 5)
 795                 i915->drm.driver_features &= ~DRIVER_ATOMIC;
 796
 797         /*
 798          * Check if we support fake LMEM -- for now we only unleash this for
 799          * the live selftests(test-and-exit).
 800          */
 801 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 802         if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)) {
 803                 if (INTEL_GEN(i915) >= 9 && i915_selftest.live < 0 &&
 804                     i915->params.fake_lmem_start) {
 805                         mkwrite_device_info(i915)->memory_regions =
 806                                 REGION_SMEM | REGION_LMEM | REGION_STOLEN;
 807                         GEM_BUG_ON(!HAS_LMEM(i915));
 808                 }
 809         }
 810 #endif
 811
 812         ret = pci_enable_device(pdev);
 813         if (ret)
 814                 goto out_fini;
 815
 816         ret = i915_driver_early_probe(i915);
 817         if (ret < 0)
 818                 goto out_pci_disable;
 819
 820         disable_rpm_wakeref_asserts(&i915->runtime_pm);
 821
 822         intel_vgpu_detect(i915);
 823
 824         ret = i915_driver_mmio_probe(i915);
 825         if (ret < 0)
 826                 goto out_runtime_pm_put;
 827
 828         ret = i915_driver_hw_probe(i915);
 829         if (ret < 0)
 830                 goto out_cleanup_mmio;
 831
 832         ret = intel_modeset_init_noirq(i915);
 833         if (ret < 0)
 834                 goto out_cleanup_hw;
 835
 836         ret = intel_irq_install(i915);
 837         if (ret)
 838                 goto out_cleanup_modeset;
 839
 840         ret = intel_modeset_init_nogem(i915);
 841         if (ret)
 842                 goto out_cleanup_irq;
 843
 844         ret = i915_gem_init(i915);
 845         if (ret)
 846                 goto out_cleanup_modeset2;
 847
 848         ret = intel_modeset_init(i915);
 849         if (ret)
 850                 goto out_cleanup_gem;
 851
 852         i915_driver_register(i915);
 853
 854         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 855
 856         i915_welcome_messages(i915);
 857
 858         i915->do_release = true;
 859
 860         return 0;
 861
 862 out_cleanup_gem:
 863         i915_gem_suspend(i915);
 864         i915_gem_driver_remove(i915);
 865         i915_gem_driver_release(i915);
 866 out_cleanup_modeset2:
 867         /* FIXME clean up the error path */
 868         intel_modeset_driver_remove(i915);
 869         intel_irq_uninstall(i915);
 870         intel_modeset_driver_remove_noirq(i915);
 871         goto out_cleanup_modeset;
 872 out_cleanup_irq:
 873         intel_irq_uninstall(i915);
 874 out_cleanup_modeset:
 875         intel_modeset_driver_remove_nogem(i915);
 876 out_cleanup_hw:
 877         i915_driver_hw_remove(i915);
 878         intel_memory_regions_driver_release(i915);
 879         i915_ggtt_driver_release(i915);
 880 out_cleanup_mmio:
 881         i915_driver_mmio_release(i915);
 882 out_runtime_pm_put:
 883         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 884         i915_driver_late_release(i915);
 885 out_pci_disable:
 886         pci_disable_device(pdev);
 887 out_fini:
 888         i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
 889         return ret;
 890 }
 891
 892 void i915_driver_remove(struct drm_i915_private *i915)
 893 {
 894         disable_rpm_wakeref_asserts(&i915->runtime_pm);
 895
 896         i915_driver_unregister(i915);
 897
 898         /* Flush any external code that still may be under the RCU lock */
 899         synchronize_rcu();
 900
 901         i915_gem_suspend(i915);
 902
 903         intel_gvt_driver_remove(i915);
 904
 905         intel_modeset_driver_remove(i915);
 906
 907         intel_irq_uninstall(i915);
 908
 909         intel_modeset_driver_remove_noirq(i915);
 910
 911         i915_reset_error_state(i915);
 912         i915_gem_driver_remove(i915);
 913
 914         intel_modeset_driver_remove_nogem(i915);
 915
 916         i915_driver_hw_remove(i915);
 917
 918         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 919 }
 920
 921 static void i915_driver_release(struct drm_device *dev)
 922 {
 923         struct drm_i915_private *dev_priv = to_i915(dev);
 924         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
 925
 926         if (!dev_priv->do_release)
 927                 return;
 928
 929         disable_rpm_wakeref_asserts(rpm);
 930
 931         i915_gem_driver_release(dev_priv);
 932
 933         intel_memory_regions_driver_release(dev_priv);
 934         i915_ggtt_driver_release(dev_priv);
 935         i915_gem_drain_freed_objects(dev_priv);
 936
 937         i915_driver_mmio_release(dev_priv);
 938
 939         enable_rpm_wakeref_asserts(rpm);
 940         intel_runtime_pm_driver_release(rpm);
 941
 942         i915_driver_late_release(dev_priv);
 943 }
 944
 945 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
 946 {
 947         struct drm_i915_private *i915 = to_i915(dev);
 948         int ret;
 949
 950         ret = i915_gem_open(i915, file);
 951         if (ret)
 952                 return ret;
 953
 954         return 0;
 955 }
 956
 957 /**
 958  * i915_driver_lastclose - clean up after all DRM clients have exited
 959  * @dev: DRM device
 960  *
 961  * Take care of cleaning up after all DRM clients have exited.  In the
 962  * mode setting case, we want to restore the kernel's initial mode (just
 963  * in case the last client left us in a bad state).
 964  *
 965  * Additionally, in the non-mode setting case, we'll tear down the GTT
 966  * and DMA structures, since the kernel won't be using them, and clea
 967  * up any GEM state.
 968  */
 969 static void i915_driver_lastclose(struct drm_device *dev)
 970 {
 971         intel_fbdev_restore_mode(dev);
 972         vga_switcheroo_process_delayed_switch();
 973 }
 974
 975 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
 976 {
 977         struct drm_i915_file_private *file_priv = file->driver_priv;
 978
 979         i915_gem_context_close(file);
 980
 981         kfree_rcu(file_priv, rcu);
 982
 983         /* Catch up with all the deferred frees from "this" client */
 984         i915_gem_flush_free_objects(to_i915(dev));
 985 }
 986
 987 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
 988 {
 989         struct drm_device *dev = &dev_priv->drm;
 990         struct intel_encoder *encoder;
 991
 992         drm_modeset_lock_all(dev);
 993         for_each_intel_encoder(dev, encoder)
 994                 if (encoder->suspend)
 995                         encoder->suspend(encoder);
 996         drm_modeset_unlock_all(dev);
 997 }
 998
 999 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv)
1000 {
1001         struct drm_device *dev = &dev_priv->drm;
1002         struct intel_encoder *encoder;
1003
1004         drm_modeset_lock_all(dev);
1005         for_each_intel_encoder(dev, encoder)
1006                 if (encoder->shutdown)
1007                         encoder->shutdown(encoder);
1008         drm_modeset_unlock_all(dev);
1009 }
1010
1011 void i915_driver_shutdown(struct drm_i915_private *i915)
1012 {
1013         disable_rpm_wakeref_asserts(&i915->runtime_pm);
1014         intel_runtime_pm_disable(&i915->runtime_pm);
1015         intel_power_domains_disable(i915);
1016
1017         i915_gem_suspend(i915);
1018
1019         drm_kms_helper_poll_disable(&i915->drm);
1020
1021         drm_atomic_helper_shutdown(&i915->drm);
1022
1023         intel_dp_mst_suspend(i915);
1024
1025         intel_runtime_pm_disable_interrupts(i915);
1026         intel_hpd_cancel_work(i915);
1027
1028         intel_suspend_encoders(i915);
1029         intel_shutdown_encoders(i915);
1030
1031         /*
1032          * The only requirement is to reboot with display DC states disabled,
1033          * for now leaving all display power wells in the INIT power domain
1034          * enabled matching the driver reload sequence.
1035          */
1036         intel_power_domains_driver_remove(i915);
1037         enable_rpm_wakeref_asserts(&i915->runtime_pm);
1038
1039         intel_runtime_pm_driver_release(&i915->runtime_pm);
1040 }
1041
1042 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1043 {
1044 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1045         if (acpi_target_system_state() < ACPI_STATE_S3)
1046                 return true;
1047 #endif
1048         return false;
1049 }
1050
1051 static int i915_drm_prepare(struct drm_device *dev)
1052 {
1053         struct drm_i915_private *i915 = to_i915(dev);
1054
1055         /*
1056          * NB intel_display_suspend() may issue new requests after we've
1057          * ostensibly marked the GPU as ready-to-sleep here. We need to
1058          * split out that work and pull it forward so that after point,
1059          * the GPU is not woken again.
1060          */
1061         i915_gem_suspend(i915);
1062
1063         return 0;
1064 }
1065
1066 static int i915_drm_suspend(struct drm_device *dev)
1067 {
1068         struct drm_i915_private *dev_priv = to_i915(dev);
1069         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1070         pci_power_t opregion_target_state;
1071
1072         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1073
1074         /* We do a lot of poking in a lot of registers, make sure they work
1075          * properly. */
1076         intel_power_domains_disable(dev_priv);
1077
1078         drm_kms_helper_poll_disable(dev);
1079
1080         pci_save_state(pdev);
1081
1082         intel_display_suspend(dev);
1083
1084         intel_dp_mst_suspend(dev_priv);
1085
1086         intel_runtime_pm_disable_interrupts(dev_priv);
1087         intel_hpd_cancel_work(dev_priv);
1088
1089         intel_suspend_encoders(dev_priv);
1090
1091         intel_suspend_hw(dev_priv);
1092
1093         i915_ggtt_suspend(&dev_priv->ggtt);
1094
1095         i915_save_display(dev_priv);
1096
1097         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1098         intel_opregion_suspend(dev_priv, opregion_target_state);
1099
1100         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1101
1102         dev_priv->suspend_count++;
1103
1104         intel_csr_ucode_suspend(dev_priv);
1105
1106         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1107
1108         return 0;
1109 }
1110
1111 static enum i915_drm_suspend_mode
1112 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1113 {
1114         if (hibernate)
1115                 return I915_DRM_SUSPEND_HIBERNATE;
1116
1117         if (suspend_to_idle(dev_priv))
1118                 return I915_DRM_SUSPEND_IDLE;
1119
1120         return I915_DRM_SUSPEND_MEM;
1121 }
1122
1123 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1124 {
1125         struct drm_i915_private *dev_priv = to_i915(dev);
1126         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1127         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1128         int ret;
1129
1130         disable_rpm_wakeref_asserts(rpm);
1131
1132         i915_gem_suspend_late(dev_priv);
1133
1134         intel_uncore_suspend(&dev_priv->uncore);
1135
1136         intel_power_domains_suspend(dev_priv,
1137                                     get_suspend_mode(dev_priv, hibernation));
1138
1139         intel_display_power_suspend_late(dev_priv);
1140
1141         ret = vlv_suspend_complete(dev_priv);
1142         if (ret) {
1143                 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);
1144                 intel_power_domains_resume(dev_priv);
1145
1146                 goto out;
1147         }
1148
1149         pci_disable_device(pdev);
1150         /*
1151          * During hibernation on some platforms the BIOS may try to access
1152          * the device even though it's already in D3 and hang the machine. So
1153          * leave the device in D0 on those platforms and hope the BIOS will
1154          * power down the device properly. The issue was seen on multiple old
1155          * GENs with different BIOS vendors, so having an explicit blacklist
1156          * is inpractical; apply the workaround on everything pre GEN6. The
1157          * platforms where the issue was seen:
1158          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1159          * Fujitsu FSC S7110
1160          * Acer Aspire 1830T
1161          */
1162         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1163                 pci_set_power_state(pdev, PCI_D3hot);
1164
1165 out:
1166         enable_rpm_wakeref_asserts(rpm);
1167         if (!dev_priv->uncore.user_forcewake_count)
1168                 intel_runtime_pm_driver_release(rpm);
1169
1170         return ret;
1171 }
1172
1173 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state)
1174 {
1175         int error;
1176
1177         if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&
1178                              state.event != PM_EVENT_FREEZE))
1179                 return -EINVAL;
1180
1181         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1182                 return 0;
1183
1184         error = i915_drm_suspend(&i915->drm);
1185         if (error)
1186                 return error;
1187
1188         return i915_drm_suspend_late(&i915->drm, false);
1189 }
1190
1191 static int i915_drm_resume(struct drm_device *dev)
1192 {
1193         struct drm_i915_private *dev_priv = to_i915(dev);
1194         int ret;
1195
1196         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1197
1198         sanitize_gpu(dev_priv);
1199
1200         ret = i915_ggtt_enable_hw(dev_priv);
1201         if (ret)
1202                 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
1203
1204         i915_ggtt_resume(&dev_priv->ggtt);
1205
1206         intel_csr_ucode_resume(dev_priv);
1207
1208         i915_restore_display(dev_priv);
1209         intel_pps_unlock_regs_wa(dev_priv);
1210
1211         intel_init_pch_refclk(dev_priv);
1212
1213         /*
1214          * Interrupts have to be enabled before any batches are run. If not the
1215          * GPU will hang. i915_gem_init_hw() will initiate batches to
1216          * update/restore the context.
1217          *
1218          * drm_mode_config_reset() needs AUX interrupts.
1219          *
1220          * Modeset enabling in intel_modeset_init_hw() also needs working
1221          * interrupts.
1222          */
1223         intel_runtime_pm_enable_interrupts(dev_priv);
1224
1225         drm_mode_config_reset(dev);
1226
1227         i915_gem_resume(dev_priv);
1228
1229         intel_modeset_init_hw(dev_priv);
1230         intel_init_clock_gating(dev_priv);
1231         intel_hpd_init(dev_priv);
1232
1233         /* MST sideband requires HPD interrupts enabled */
1234         intel_dp_mst_resume(dev_priv);
1235         intel_display_resume(dev);
1236
1237         intel_hpd_poll_disable(dev_priv);
1238         drm_kms_helper_poll_enable(dev);
1239
1240         intel_opregion_resume(dev_priv);
1241
1242         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1243
1244         intel_power_domains_enable(dev_priv);
1245
1246         intel_gvt_resume(dev_priv);
1247
1248         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1249
1250         return 0;
1251 }
1252
1253 static int i915_drm_resume_early(struct drm_device *dev)
1254 {
1255         struct drm_i915_private *dev_priv = to_i915(dev);
1256         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1257         int ret;
1258
1259         /*
1260          * We have a resume ordering issue with the snd-hda driver also
1261          * requiring our device to be power up. Due to the lack of a
1262          * parent/child relationship we currently solve this with an early
1263          * resume hook.
1264          *
1265          * FIXME: This should be solved with a special hdmi sink device or
1266          * similar so that power domains can be employed.
1267          */
1268
1269         /*
1270          * Note that we need to set the power state explicitly, since we
1271          * powered off the device during freeze and the PCI core won't power
1272          * it back up for us during thaw. Powering off the device during
1273          * freeze is not a hard requirement though, and during the
1274          * suspend/resume phases the PCI core makes sure we get here with the
1275          * device powered on. So in case we change our freeze logic and keep
1276          * the device powered we can also remove the following set power state
1277          * call.
1278          */
1279         ret = pci_set_power_state(pdev, PCI_D0);
1280         if (ret) {
1281                 drm_err(&dev_priv->drm,
1282                         "failed to set PCI D0 power state (%d)\n", ret);
1283                 return ret;
1284         }
1285
1286         /*
1287          * Note that pci_enable_device() first enables any parent bridge
1288          * device and only then sets the power state for this device. The
1289          * bridge enabling is a nop though, since bridge devices are resumed
1290          * first. The order of enabling power and enabling the device is
1291          * imposed by the PCI core as described above, so here we preserve the
1292          * same order for the freeze/thaw phases.
1293          *
1294          * TODO: eventually we should remove pci_disable_device() /
1295          * pci_enable_enable_device() from suspend/resume. Due to how they
1296          * depend on the device enable refcount we can't anyway depend on them
1297          * disabling/enabling the device.
1298          */
1299         if (pci_enable_device(pdev))
1300                 return -EIO;
1301
1302         pci_set_master(pdev);
1303
1304         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1305
1306         ret = vlv_resume_prepare(dev_priv, false);
1307         if (ret)
1308                 drm_err(&dev_priv->drm,
1309                         "Resume prepare failed: %d, continuing anyway\n", ret);
1310
1311         intel_uncore_resume_early(&dev_priv->uncore);
1312
1313         intel_gt_check_and_clear_faults(&dev_priv->gt);
1314
1315         intel_display_power_resume_early(dev_priv);
1316
1317         intel_power_domains_resume(dev_priv);
1318
1319         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1320
1321         return ret;
1322 }
1323
1324 int i915_resume_switcheroo(struct drm_i915_private *i915)
1325 {
1326         int ret;
1327
1328         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1329                 return 0;
1330
1331         ret = i915_drm_resume_early(&i915->drm);
1332         if (ret)
1333                 return ret;
1334
1335         return i915_drm_resume(&i915->drm);
1336 }
1337
1338 static int i915_pm_prepare(struct device *kdev)
1339 {
1340         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1341
1342         if (!i915) {
1343                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1344                 return -ENODEV;
1345         }
1346
1347         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1348                 return 0;
1349
1350         return i915_drm_prepare(&i915->drm);
1351 }
1352
1353 static int i915_pm_suspend(struct device *kdev)
1354 {
1355         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1356
1357         if (!i915) {
1358                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1359                 return -ENODEV;
1360         }
1361
1362         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1363                 return 0;
1364
1365         return i915_drm_suspend(&i915->drm);
1366 }
1367
1368 static int i915_pm_suspend_late(struct device *kdev)
1369 {
1370         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1371
1372         /*
1373          * We have a suspend ordering issue with the snd-hda driver also
1374          * requiring our device to be power up. Due to the lack of a
1375          * parent/child relationship we currently solve this with an late
1376          * suspend hook.
1377          *
1378          * FIXME: This should be solved with a special hdmi sink device or
1379          * similar so that power domains can be employed.
1380          */
1381         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1382                 return 0;
1383
1384         return i915_drm_suspend_late(&i915->drm, false);
1385 }
1386
1387 static int i915_pm_poweroff_late(struct device *kdev)
1388 {
1389         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1390
1391         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1392                 return 0;
1393
1394         return i915_drm_suspend_late(&i915->drm, true);
1395 }
1396
1397 static int i915_pm_resume_early(struct device *kdev)
1398 {
1399         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1400
1401         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1402                 return 0;
1403
1404         return i915_drm_resume_early(&i915->drm);
1405 }
1406
1407 static int i915_pm_resume(struct device *kdev)
1408 {
1409         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1410
1411         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1412                 return 0;
1413
1414         return i915_drm_resume(&i915->drm);
1415 }
1416
1417 /* freeze: before creating the hibernation_image */
1418 static int i915_pm_freeze(struct device *kdev)
1419 {
1420         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1421         int ret;
1422
1423         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1424                 ret = i915_drm_suspend(&i915->drm);
1425                 if (ret)
1426                         return ret;
1427         }
1428
1429         ret = i915_gem_freeze(i915);
1430         if (ret)
1431                 return ret;
1432
1433         return 0;
1434 }
1435
1436 static int i915_pm_freeze_late(struct device *kdev)
1437 {
1438         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1439         int ret;
1440
1441         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1442                 ret = i915_drm_suspend_late(&i915->drm, true);
1443                 if (ret)
1444                         return ret;
1445         }
1446
1447         ret = i915_gem_freeze_late(i915);
1448         if (ret)
1449                 return ret;
1450
1451         return 0;
1452 }
1453
1454 /* thaw: called after creating the hibernation image, but before turning off. */
1455 static int i915_pm_thaw_early(struct device *kdev)
1456 {
1457         return i915_pm_resume_early(kdev);
1458 }
1459
1460 static int i915_pm_thaw(struct device *kdev)
1461 {
1462         return i915_pm_resume(kdev);
1463 }
1464
1465 /* restore: called after loading the hibernation image. */
1466 static int i915_pm_restore_early(struct device *kdev)
1467 {
1468         return i915_pm_resume_early(kdev);
1469 }
1470
1471 static int i915_pm_restore(struct device *kdev)
1472 {
1473         return i915_pm_resume(kdev);
1474 }
1475
1476 static int intel_runtime_suspend(struct device *kdev)
1477 {
1478         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1479         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1480         int ret;
1481
1482         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1483                 return -ENODEV;
1484
1485         drm_dbg_kms(&dev_priv->drm, "Suspending device\n");
1486
1487         disable_rpm_wakeref_asserts(rpm);
1488
1489         /*
1490          * We are safe here against re-faults, since the fault handler takes
1491          * an RPM reference.
1492          */
1493         i915_gem_runtime_suspend(dev_priv);
1494
1495         intel_gt_runtime_suspend(&dev_priv->gt);
1496
1497         intel_runtime_pm_disable_interrupts(dev_priv);
1498
1499         intel_uncore_suspend(&dev_priv->uncore);
1500
1501         intel_display_power_suspend(dev_priv);
1502
1503         ret = vlv_suspend_complete(dev_priv);
1504         if (ret) {
1505                 drm_err(&dev_priv->drm,
1506                         "Runtime suspend failed, disabling it (%d)\n", ret);
1507                 intel_uncore_runtime_resume(&dev_priv->uncore);
1508
1509                 intel_runtime_pm_enable_interrupts(dev_priv);
1510
1511                 intel_gt_runtime_resume(&dev_priv->gt);
1512
1513                 enable_rpm_wakeref_asserts(rpm);
1514
1515                 return ret;
1516         }
1517
1518         enable_rpm_wakeref_asserts(rpm);
1519         intel_runtime_pm_driver_release(rpm);
1520
1521         if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
1522                 drm_err(&dev_priv->drm,
1523                         "Unclaimed access detected prior to suspending\n");
1524
1525         rpm->suspended = true;
1526
1527         /*
1528          * FIXME: We really should find a document that references the arguments
1529          * used below!
1530          */
1531         if (IS_BROADWELL(dev_priv)) {
1532                 /*
1533                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1534                  * being detected, and the call we do at intel_runtime_resume()
1535                  * won't be able to restore them. Since PCI_D3hot matches the
1536                  * actual specification and appears to be working, use it.
1537                  */
1538                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
1539         } else {
1540                 /*
1541                  * current versions of firmware which depend on this opregion
1542                  * notification have repurposed the D1 definition to mean
1543                  * "runtime suspended" vs. what you would normally expect (D3)
1544                  * to distinguish it from notifications that might be sent via
1545                  * the suspend path.
1546                  */
1547                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
1548         }
1549
1550         assert_forcewakes_inactive(&dev_priv->uncore);
1551
1552         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1553                 intel_hpd_poll_enable(dev_priv);
1554
1555         drm_dbg_kms(&dev_priv->drm, "Device suspended\n");
1556         return 0;
1557 }
1558
1559 static int intel_runtime_resume(struct device *kdev)
1560 {
1561         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1562         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1563         int ret;
1564
1565         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1566                 return -ENODEV;
1567
1568         drm_dbg_kms(&dev_priv->drm, "Resuming device\n");
1569
1570         drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
1571         disable_rpm_wakeref_asserts(rpm);
1572
1573         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1574         rpm->suspended = false;
1575         if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
1576                 drm_dbg(&dev_priv->drm,
1577                         "Unclaimed access during suspend, bios?\n");
1578
1579         intel_display_power_resume(dev_priv);
1580
1581         ret = vlv_resume_prepare(dev_priv, true);
1582
1583         intel_uncore_runtime_resume(&dev_priv->uncore);
1584
1585         intel_runtime_pm_enable_interrupts(dev_priv);
1586
1587         /*
1588          * No point of rolling back things in case of an error, as the best
1589          * we can do is to hope that things will still work (and disable RPM).
1590          */
1591         intel_gt_runtime_resume(&dev_priv->gt);
1592
1593         /*
1594          * On VLV/CHV display interrupts are part of the display
1595          * power well, so hpd is reinitialized from there. For
1596          * everyone else do it here.
1597          */
1598         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
1599                 intel_hpd_init(dev_priv);
1600                 intel_hpd_poll_disable(dev_priv);
1601         }
1602
1603         intel_enable_ipc(dev_priv);
1604
1605         enable_rpm_wakeref_asserts(rpm);
1606
1607         if (ret)
1608                 drm_err(&dev_priv->drm,
1609                         "Runtime resume failed, disabling it (%d)\n", ret);
1610         else
1611                 drm_dbg_kms(&dev_priv->drm, "Device resumed\n");
1612
1613         return ret;
1614 }
1615
1616 const struct dev_pm_ops i915_pm_ops = {
1617         /*
1618          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1619          * PMSG_RESUME]
1620          */
1621         .prepare = i915_pm_prepare,
1622         .suspend = i915_pm_suspend,
1623         .suspend_late = i915_pm_suspend_late,
1624         .resume_early = i915_pm_resume_early,
1625         .resume = i915_pm_resume,
1626
1627         /*
1628          * S4 event handlers
1629          * @freeze, @freeze_late    : called (1) before creating the
1630          *                            hibernation image [PMSG_FREEZE] and
1631          *                            (2) after rebooting, before restoring
1632          *                            the image [PMSG_QUIESCE]
1633          * @thaw, @thaw_early       : called (1) after creating the hibernation
1634          *                            image, before writing it [PMSG_THAW]
1635          *                            and (2) after failing to create or
1636          *                            restore the image [PMSG_RECOVER]
1637          * @poweroff, @poweroff_late: called after writing the hibernation
1638          *                            image, before rebooting [PMSG_HIBERNATE]
1639          * @restore, @restore_early : called after rebooting and restoring the
1640          *                            hibernation image [PMSG_RESTORE]
1641          */
1642         .freeze = i915_pm_freeze,
1643         .freeze_late = i915_pm_freeze_late,
1644         .thaw_early = i915_pm_thaw_early,
1645         .thaw = i915_pm_thaw,
1646         .poweroff = i915_pm_suspend,
1647         .poweroff_late = i915_pm_poweroff_late,
1648         .restore_early = i915_pm_restore_early,
1649         .restore = i915_pm_restore,
1650
1651         /* S0ix (via runtime suspend) event handlers */
1652         .runtime_suspend = intel_runtime_suspend,
1653         .runtime_resume = intel_runtime_resume,
1654 };
1655
1656 static const struct file_operations i915_driver_fops = {
1657         .owner = THIS_MODULE,
1658         .open = drm_open,
1659         .release = drm_release_noglobal,
1660         .unlocked_ioctl = drm_ioctl,
1661         .mmap = i915_gem_mmap,
1662         .poll = drm_poll,
1663         .read = drm_read,
1664         .compat_ioctl = i915_ioc32_compat_ioctl,
1665         .llseek = noop_llseek,
1666 };
1667
1668 static int
1669 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1670                           struct drm_file *file)
1671 {
1672         return -ENODEV;
1673 }
1674
1675 static const struct drm_ioctl_desc i915_ioctls[] = {
1676         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1677         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1678         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1679         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1680         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1681         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1682         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
1683         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1684         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1685         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1686         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1687         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1688         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1689         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1690         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
1691         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1692         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1693         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1694         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH),
1695         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
1696         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1697         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1698         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
1699         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1700         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1701         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
1702         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1703         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1704         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1705         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1706         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1707         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1708         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
1709         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1710         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1711         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
1712         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
1713         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1714         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
1715         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1716         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
1717         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
1718         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
1719         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
1720         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
1721         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1722         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1723         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1724         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
1725         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1726         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1727         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1728         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
1729         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
1730         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
1731         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
1732         DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
1733         DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
1734 };
1735
1736 static const struct drm_driver driver = {
1737         /* Don't use MTRRs here; the Xserver or userspace app should
1738          * deal with them for Intel hardware.
1739          */
1740         .driver_features =
1741             DRIVER_GEM |
1742             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ |
1743             DRIVER_SYNCOBJ_TIMELINE,
1744         .release = i915_driver_release,
1745         .open = i915_driver_open,
1746         .lastclose = i915_driver_lastclose,
1747         .postclose = i915_driver_postclose,
1748
1749         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1750         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1751         .gem_prime_import = i915_gem_prime_import,
1752
1753         .dumb_create = i915_gem_dumb_create,
1754         .dumb_map_offset = i915_gem_dumb_mmap_offset,
1755
1756         .ioctls = i915_ioctls,
1757         .num_ioctls = ARRAY_SIZE(i915_ioctls),
1758         .fops = &i915_driver_fops,
1759         .name = DRIVER_NAME,
1760         .desc = DRIVER_DESC,
1761         .date = DRIVER_DATE,
1762         .major = DRIVER_MAJOR,
1763         .minor = DRIVER_MINOR,
1764         .patchlevel = DRIVER_PATCHLEVEL,
1765 };