drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vga_switcheroo.h>
  40 #include <linux/vt.h>
  41 #include <acpi/video.h>
  42
  43 #include <drm/drm_atomic_helper.h>
  44 #include <drm/drm_ioctl.h>
  45 #include <drm/drm_irq.h>
  46 #include <drm/drm_managed.h>
  47 #include <drm/drm_probe_helper.h>
  48
  49 #include "display/intel_acpi.h"
  50 #include "display/intel_audio.h"
  51 #include "display/intel_bw.h"
  52 #include "display/intel_cdclk.h"
  53 #include "display/intel_csr.h"
  54 #include "display/intel_display_debugfs.h"
  55 #include "display/intel_display_types.h"
  56 #include "display/intel_dp.h"
  57 #include "display/intel_fbdev.h"
  58 #include "display/intel_hotplug.h"
  59 #include "display/intel_overlay.h"
  60 #include "display/intel_pipe_crc.h"
  61 #include "display/intel_pps.h"
  62 #include "display/intel_sprite.h"
  63 #include "display/intel_vga.h"
  64
  65 #include "gem/i915_gem_context.h"
  66 #include "gem/i915_gem_ioctls.h"
  67 #include "gem/i915_gem_mman.h"
  68 #include "gem/i915_gem_pm.h"
  69 #include "gt/intel_gt.h"
  70 #include "gt/intel_gt_pm.h"
  71 #include "gt/intel_rc6.h"
  72
  73 #include "i915_debugfs.h"
  74 #include "i915_drv.h"
  75 #include "i915_ioc32.h"
  76 #include "i915_irq.h"
  77 #include "i915_memcpy.h"
  78 #include "i915_perf.h"
  79 #include "i915_query.h"
  80 #include "i915_suspend.h"
  81 #include "i915_switcheroo.h"
  82 #include "i915_sysfs.h"
  83 #include "i915_trace.h"
  84 #include "i915_vgpu.h"
  85 #include "intel_dram.h"
  86 #include "intel_gvt.h"
  87 #include "intel_memory_region.h"
  88 #include "intel_pm.h"
  89 #include "intel_sideband.h"
  90 #include "vlv_suspend.h"
  91
  92 static const struct drm_driver driver;
  93
  94 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
  95 {
  96         int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
  97
  98         dev_priv->bridge_dev =
  99                 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
 100         if (!dev_priv->bridge_dev) {
 101                 drm_err(&dev_priv->drm, "bridge device not found\n");
 102                 return -1;
 103         }
 104         return 0;
 105 }
 106
 107 /* Allocate space for the MCH regs if needed, return nonzero on error */
 108 static int
 109 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 110 {
 111         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 112         u32 temp_lo, temp_hi = 0;
 113         u64 mchbar_addr;
 114         int ret;
 115
 116         if (INTEL_GEN(dev_priv) >= 4)
 117                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 118         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 119         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 120
 121         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 122 #ifdef CONFIG_PNP
 123         if (mchbar_addr &&
 124             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 125                 return 0;
 126 #endif
 127
 128         /* Get some space for it */
 129         dev_priv->mch_res.name = "i915 MCHBAR";
 130         dev_priv->mch_res.flags = IORESOURCE_MEM;
 131         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 132                                      &dev_priv->mch_res,
 133                                      MCHBAR_SIZE, MCHBAR_SIZE,
 134                                      PCIBIOS_MIN_MEM,
 135                                      0, pcibios_align_resource,
 136                                      dev_priv->bridge_dev);
 137         if (ret) {
 138                 drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret);
 139                 dev_priv->mch_res.start = 0;
 140                 return ret;
 141         }
 142
 143         if (INTEL_GEN(dev_priv) >= 4)
 144                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 145                                        upper_32_bits(dev_priv->mch_res.start));
 146
 147         pci_write_config_dword(dev_priv->bridge_dev, reg,
 148                                lower_32_bits(dev_priv->mch_res.start));
 149         return 0;
 150 }
 151
 152 /* Setup MCHBAR if possible, return true if we should disable it again */
 153 static void
 154 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 155 {
 156         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 157         u32 temp;
 158         bool enabled;
 159
 160         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 161                 return;
 162
 163         dev_priv->mchbar_need_disable = false;
 164
 165         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 166                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 167                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 168         } else {
 169                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 170                 enabled = temp & 1;
 171         }
 172
 173         /* If it's already enabled, don't have to do anything */
 174         if (enabled)
 175                 return;
 176
 177         if (intel_alloc_mchbar_resource(dev_priv))
 178                 return;
 179
 180         dev_priv->mchbar_need_disable = true;
 181
 182         /* Space is allocated or reserved, so enable it. */
 183         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 184                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 185                                        temp | DEVEN_MCHBAR_EN);
 186         } else {
 187                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 188                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 189         }
 190 }
 191
 192 static void
 193 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 194 {
 195         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 196
 197         if (dev_priv->mchbar_need_disable) {
 198                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 199                         u32 deven_val;
 200
 201                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 202                                               &deven_val);
 203                         deven_val &= ~DEVEN_MCHBAR_EN;
 204                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 205                                                deven_val);
 206                 } else {
 207                         u32 mchbar_val;
 208
 209                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 210                                               &mchbar_val);
 211                         mchbar_val &= ~1;
 212                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 213                                                mchbar_val);
 214                 }
 215         }
 216
 217         if (dev_priv->mch_res.start)
 218                 release_resource(&dev_priv->mch_res);
 219 }
 220
 221 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 222 {
 223         /*
 224          * The i915 workqueue is primarily used for batched retirement of
 225          * requests (and thus managing bo) once the task has been completed
 226          * by the GPU. i915_retire_requests() is called directly when we
 227          * need high-priority retirement, such as waiting for an explicit
 228          * bo.
 229          *
 230          * It is also used for periodic low-priority events, such as
 231          * idle-timers and recording error state.
 232          *
 233          * All tasks on the workqueue are expected to acquire the dev mutex
 234          * so there is no point in running more than one instance of the
 235          * workqueue at any time.  Use an ordered one.
 236          */
 237         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 238         if (dev_priv->wq == NULL)
 239                 goto out_err;
 240
 241         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 242         if (dev_priv->hotplug.dp_wq == NULL)
 243                 goto out_free_wq;
 244
 245         return 0;
 246
 247 out_free_wq:
 248         destroy_workqueue(dev_priv->wq);
 249 out_err:
 250         drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n");
 251
 252         return -ENOMEM;
 253 }
 254
 255 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 256 {
 257         destroy_workqueue(dev_priv->hotplug.dp_wq);
 258         destroy_workqueue(dev_priv->wq);
 259 }
 260
 261 /*
 262  * We don't keep the workarounds for pre-production hardware, so we expect our
 263  * driver to fail on these machines in one way or another. A little warning on
 264  * dmesg may help both the user and the bug triagers.
 265  *
 266  * Our policy for removing pre-production workarounds is to keep the
 267  * current gen workarounds as a guide to the bring-up of the next gen
 268  * (workarounds have a habit of persisting!). Anything older than that
 269  * should be removed along with the complications they introduce.
 270  */
 271 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 272 {
 273         bool pre = false;
 274
 275         pre |= IS_HSW_EARLY_SDV(dev_priv);
 276         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 277         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 278         pre |= IS_KBL_GT_REVID(dev_priv, 0, KBL_REVID_A0);
 279         pre |= IS_GLK_REVID(dev_priv, 0, GLK_REVID_A2);
 280
 281         if (pre) {
 282                 drm_err(&dev_priv->drm, "This is a pre-production stepping. "
 283                           "It may not be fully functional.\n");
 284                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 285         }
 286 }
 287
 288 static void sanitize_gpu(struct drm_i915_private *i915)
 289 {
 290         if (!INTEL_INFO(i915)->gpu_reset_clobbers_display)
 291                 __intel_gt_reset(&i915->gt, ALL_ENGINES);
 292 }
 293
 294 /**
 295  * i915_driver_early_probe - setup state not requiring device access
 296  * @dev_priv: device private
 297  *
 298  * Initialize everything that is a "SW-only" state, that is state not
 299  * requiring accessing the device or exposing the driver via kernel internal
 300  * or userspace interfaces. Example steps belonging here: lock initialization,
 301  * system memory allocation, setting up device specific attributes and
 302  * function hooks not requiring accessing the device.
 303  */
 304 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
 305 {
 306         int ret = 0;
 307
 308         if (i915_inject_probe_failure(dev_priv))
 309                 return -ENODEV;
 310
 311         intel_device_info_subplatform_init(dev_priv);
 312
 313         intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
 314         intel_uncore_init_early(&dev_priv->uncore, dev_priv);
 315
 316         spin_lock_init(&dev_priv->irq_lock);
 317         spin_lock_init(&dev_priv->gpu_error.lock);
 318         mutex_init(&dev_priv->backlight_lock);
 319
 320         mutex_init(&dev_priv->sb_lock);
 321         cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
 322
 323         mutex_init(&dev_priv->av_mutex);
 324         mutex_init(&dev_priv->wm.wm_mutex);
 325         mutex_init(&dev_priv->pps_mutex);
 326         mutex_init(&dev_priv->hdcp_comp_mutex);
 327
 328         i915_memcpy_init_early(dev_priv);
 329         intel_runtime_pm_init_early(&dev_priv->runtime_pm);
 330
 331         ret = i915_workqueues_init(dev_priv);
 332         if (ret < 0)
 333                 return ret;
 334
 335         ret = vlv_suspend_init(dev_priv);
 336         if (ret < 0)
 337                 goto err_workqueues;
 338
 339         intel_wopcm_init_early(&dev_priv->wopcm);
 340
 341         intel_gt_init_early(&dev_priv->gt, dev_priv);
 342
 343         i915_gem_init_early(dev_priv);
 344
 345         /* This must be called before any calls to HAS_PCH_* */
 346         intel_detect_pch(dev_priv);
 347
 348         intel_pm_setup(dev_priv);
 349         ret = intel_power_domains_init(dev_priv);
 350         if (ret < 0)
 351                 goto err_gem;
 352         intel_irq_init(dev_priv);
 353         intel_init_display_hooks(dev_priv);
 354         intel_init_clock_gating_hooks(dev_priv);
 355         intel_init_audio_hooks(dev_priv);
 356
 357         intel_detect_preproduction_hw(dev_priv);
 358
 359         return 0;
 360
 361 err_gem:
 362         i915_gem_cleanup_early(dev_priv);
 363         intel_gt_driver_late_release(&dev_priv->gt);
 364         vlv_suspend_cleanup(dev_priv);
 365 err_workqueues:
 366         i915_workqueues_cleanup(dev_priv);
 367         return ret;
 368 }
 369
 370 /**
 371  * i915_driver_late_release - cleanup the setup done in
 372  *                             i915_driver_early_probe()
 373  * @dev_priv: device private
 374  */
 375 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
 376 {
 377         intel_irq_fini(dev_priv);
 378         intel_power_domains_cleanup(dev_priv);
 379         i915_gem_cleanup_early(dev_priv);
 380         intel_gt_driver_late_release(&dev_priv->gt);
 381         vlv_suspend_cleanup(dev_priv);
 382         i915_workqueues_cleanup(dev_priv);
 383
 384         cpu_latency_qos_remove_request(&dev_priv->sb_qos);
 385         mutex_destroy(&dev_priv->sb_lock);
 386
 387         i915_params_free(&dev_priv->params);
 388 }
 389
 390 /**
 391  * i915_driver_mmio_probe - setup device MMIO
 392  * @dev_priv: device private
 393  *
 394  * Setup minimal device state necessary for MMIO accesses later in the
 395  * initialization sequence. The setup here should avoid any other device-wide
 396  * side effects or exposing the driver via kernel internal or user space
 397  * interfaces.
 398  */
 399 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
 400 {
 401         int ret;
 402
 403         if (i915_inject_probe_failure(dev_priv))
 404                 return -ENODEV;
 405
 406         if (i915_get_bridge_dev(dev_priv))
 407                 return -EIO;
 408
 409         ret = intel_uncore_init_mmio(&dev_priv->uncore);
 410         if (ret < 0)
 411                 goto err_bridge;
 412
 413         /* Try to make sure MCHBAR is enabled before poking at it */
 414         intel_setup_mchbar(dev_priv);
 415         intel_device_info_runtime_init(dev_priv);
 416
 417         ret = intel_gt_init_mmio(&dev_priv->gt);
 418         if (ret)
 419                 goto err_uncore;
 420
 421         /* As early as possible, scrub existing GPU state before clobbering */
 422         sanitize_gpu(dev_priv);
 423
 424         return 0;
 425
 426 err_uncore:
 427         intel_teardown_mchbar(dev_priv);
 428         intel_uncore_fini_mmio(&dev_priv->uncore);
 429 err_bridge:
 430         pci_dev_put(dev_priv->bridge_dev);
 431
 432         return ret;
 433 }
 434
 435 /**
 436  * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
 437  * @dev_priv: device private
 438  */
 439 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
 440 {
 441         intel_teardown_mchbar(dev_priv);
 442         intel_uncore_fini_mmio(&dev_priv->uncore);
 443         pci_dev_put(dev_priv->bridge_dev);
 444 }
 445
 446 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 447 {
 448         intel_gvt_sanitize_options(dev_priv);
 449 }
 450
 451 /**
 452  * i915_set_dma_info - set all relevant PCI dma info as configured for the
 453  * platform
 454  * @i915: valid i915 instance
 455  *
 456  * Set the dma max segment size, device and coherent masks.  The dma mask set
 457  * needs to occur before i915_ggtt_probe_hw.
 458  *
 459  * A couple of platforms have special needs.  Address them as well.
 460  *
 461  */
 462 static int i915_set_dma_info(struct drm_i915_private *i915)
 463 {
 464         struct pci_dev *pdev = i915->drm.pdev;
 465         unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size;
 466         int ret;
 467
 468         GEM_BUG_ON(!mask_size);
 469
 470         /*
 471          * We don't have a max segment size, so set it to the max so sg's
 472          * debugging layer doesn't complain
 473          */
 474         dma_set_max_seg_size(&pdev->dev, UINT_MAX);
 475
 476         ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(mask_size));
 477         if (ret)
 478                 goto mask_err;
 479
 480         /* overlay on gen2 is broken and can't address above 1G */
 481         if (IS_GEN(i915, 2))
 482                 mask_size = 30;
 483
 484         /*
 485          * 965GM sometimes incorrectly writes to hardware status page (HWS)
 486          * using 32bit addressing, overwriting memory if HWS is located
 487          * above 4GB.
 488          *
 489          * The documentation also mentions an issue with undefined
 490          * behaviour if any general state is accessed within a page above 4GB,
 491          * which also needs to be handled carefully.
 492          */
 493         if (IS_I965G(i915) || IS_I965GM(i915))
 494                 mask_size = 32;
 495
 496         ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(mask_size));
 497         if (ret)
 498                 goto mask_err;
 499
 500         return 0;
 501
 502 mask_err:
 503         drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret);
 504         return ret;
 505 }
 506
 507 /**
 508  * i915_driver_hw_probe - setup state requiring device access
 509  * @dev_priv: device private
 510  *
 511  * Setup state that requires accessing the device, but doesn't require
 512  * exposing the driver via kernel internal or userspace interfaces.
 513  */
 514 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
 515 {
 516         struct pci_dev *pdev = dev_priv->drm.pdev;
 517         int ret;
 518
 519         if (i915_inject_probe_failure(dev_priv))
 520                 return -ENODEV;
 521
 522         if (HAS_PPGTT(dev_priv)) {
 523                 if (intel_vgpu_active(dev_priv) &&
 524                     !intel_vgpu_has_full_ppgtt(dev_priv)) {
 525                         i915_report_error(dev_priv,
 526                                           "incompatible vGPU found, support for isolated ppGTT required\n");
 527                         return -ENXIO;
 528                 }
 529         }
 530
 531         if (HAS_EXECLISTS(dev_priv)) {
 532                 /*
 533                  * Older GVT emulation depends upon intercepting CSB mmio,
 534                  * which we no longer use, preferring to use the HWSP cache
 535                  * instead.
 536                  */
 537                 if (intel_vgpu_active(dev_priv) &&
 538                     !intel_vgpu_has_hwsp_emulation(dev_priv)) {
 539                         i915_report_error(dev_priv,
 540                                           "old vGPU host found, support for HWSP emulation required\n");
 541                         return -ENXIO;
 542                 }
 543         }
 544
 545         intel_sanitize_options(dev_priv);
 546
 547         /* needs to be done before ggtt probe */
 548         intel_dram_edram_detect(dev_priv);
 549
 550         ret = i915_set_dma_info(dev_priv);
 551         if (ret)
 552                 return ret;
 553
 554         i915_perf_init(dev_priv);
 555
 556         ret = i915_ggtt_probe_hw(dev_priv);
 557         if (ret)
 558                 goto err_perf;
 559
 560         ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "inteldrmfb");
 561         if (ret)
 562                 goto err_ggtt;
 563
 564         ret = i915_ggtt_init_hw(dev_priv);
 565         if (ret)
 566                 goto err_ggtt;
 567
 568         ret = intel_memory_regions_hw_probe(dev_priv);
 569         if (ret)
 570                 goto err_ggtt;
 571
 572         intel_gt_init_hw_early(&dev_priv->gt, &dev_priv->ggtt);
 573
 574         ret = i915_ggtt_enable_hw(dev_priv);
 575         if (ret) {
 576                 drm_err(&dev_priv->drm, "failed to enable GGTT\n");
 577                 goto err_mem_regions;
 578         }
 579
 580         pci_set_master(pdev);
 581
 582         intel_gt_init_workarounds(dev_priv);
 583
 584         /* On the 945G/GM, the chipset reports the MSI capability on the
 585          * integrated graphics even though the support isn't actually there
 586          * according to the published specs.  It doesn't appear to function
 587          * correctly in testing on 945G.
 588          * This may be a side effect of MSI having been made available for PEG
 589          * and the registers being closely associated.
 590          *
 591          * According to chipset errata, on the 965GM, MSI interrupts may
 592          * be lost or delayed, and was defeatured. MSI interrupts seem to
 593          * get lost on g4x as well, and interrupt delivery seems to stay
 594          * properly dead afterwards. So we'll just disable them for all
 595          * pre-gen5 chipsets.
 596          *
 597          * dp aux and gmbus irq on gen4 seems to be able to generate legacy
 598          * interrupts even when in MSI mode. This results in spurious
 599          * interrupt warnings if the legacy irq no. is shared with another
 600          * device. The kernel then disables that interrupt source and so
 601          * prevents the other device from working properly.
 602          */
 603         if (INTEL_GEN(dev_priv) >= 5) {
 604                 if (pci_enable_msi(pdev) < 0)
 605                         drm_dbg(&dev_priv->drm, "can't enable MSI");
 606         }
 607
 608         ret = intel_gvt_init(dev_priv);
 609         if (ret)
 610                 goto err_msi;
 611
 612         intel_opregion_setup(dev_priv);
 613
 614         intel_pcode_init(dev_priv);
 615
 616         /*
 617          * Fill the dram structure to get the system dram info. This will be
 618          * used for memory latency calculation.
 619          */
 620         intel_dram_detect(dev_priv);
 621
 622         intel_bw_init_hw(dev_priv);
 623
 624         return 0;
 625
 626 err_msi:
 627         if (pdev->msi_enabled)
 628                 pci_disable_msi(pdev);
 629 err_mem_regions:
 630         intel_memory_regions_driver_release(dev_priv);
 631 err_ggtt:
 632         i915_ggtt_driver_release(dev_priv);
 633 err_perf:
 634         i915_perf_fini(dev_priv);
 635         return ret;
 636 }
 637
 638 /**
 639  * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
 640  * @dev_priv: device private
 641  */
 642 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
 643 {
 644         struct pci_dev *pdev = dev_priv->drm.pdev;
 645
 646         i915_perf_fini(dev_priv);
 647
 648         if (pdev->msi_enabled)
 649                 pci_disable_msi(pdev);
 650 }
 651
 652 /**
 653  * i915_driver_register - register the driver with the rest of the system
 654  * @dev_priv: device private
 655  *
 656  * Perform any steps necessary to make the driver available via kernel
 657  * internal or userspace interfaces.
 658  */
 659 static void i915_driver_register(struct drm_i915_private *dev_priv)
 660 {
 661         struct drm_device *dev = &dev_priv->drm;
 662
 663         i915_gem_driver_register(dev_priv);
 664         i915_pmu_register(dev_priv);
 665
 666         intel_vgpu_register(dev_priv);
 667
 668         /* Reveal our presence to userspace */
 669         if (drm_dev_register(dev, 0) == 0) {
 670                 i915_debugfs_register(dev_priv);
 671                 if (HAS_DISPLAY(dev_priv))
 672                         intel_display_debugfs_register(dev_priv);
 673                 i915_setup_sysfs(dev_priv);
 674
 675                 /* Depends on sysfs having been initialized */
 676                 i915_perf_register(dev_priv);
 677         } else
 678                 drm_err(&dev_priv->drm,
 679                         "Failed to register driver for userspace access!\n");
 680
 681         if (HAS_DISPLAY(dev_priv)) {
 682                 /* Must be done after probing outputs */
 683                 intel_opregion_register(dev_priv);
 684                 acpi_video_register();
 685         }
 686
 687         intel_gt_driver_register(&dev_priv->gt);
 688
 689         intel_audio_init(dev_priv);
 690
 691         /*
 692          * Some ports require correctly set-up hpd registers for detection to
 693          * work properly (leading to ghost connected connector status), e.g. VGA
 694          * on gm45.  Hence we can only set up the initial fbdev config after hpd
 695          * irqs are fully enabled. We do it last so that the async config
 696          * cannot run before the connectors are registered.
 697          */
 698         intel_fbdev_initial_config_async(dev);
 699
 700         /*
 701          * We need to coordinate the hotplugs with the asynchronous fbdev
 702          * configuration, for which we use the fbdev->async_cookie.
 703          */
 704         if (HAS_DISPLAY(dev_priv))
 705                 drm_kms_helper_poll_init(dev);
 706
 707         intel_power_domains_enable(dev_priv);
 708         intel_runtime_pm_enable(&dev_priv->runtime_pm);
 709
 710         intel_register_dsm_handler();
 711
 712         if (i915_switcheroo_register(dev_priv))
 713                 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n");
 714 }
 715
 716 /**
 717  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
 718  * @dev_priv: device private
 719  */
 720 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
 721 {
 722         i915_switcheroo_unregister(dev_priv);
 723
 724         intel_unregister_dsm_handler();
 725
 726         intel_runtime_pm_disable(&dev_priv->runtime_pm);
 727         intel_power_domains_disable(dev_priv);
 728
 729         intel_fbdev_unregister(dev_priv);
 730         intel_audio_deinit(dev_priv);
 731
 732         /*
 733          * After flushing the fbdev (incl. a late async config which will
 734          * have delayed queuing of a hotplug event), then flush the hotplug
 735          * events.
 736          */
 737         drm_kms_helper_poll_fini(&dev_priv->drm);
 738         drm_atomic_helper_shutdown(&dev_priv->drm);
 739
 740         intel_gt_driver_unregister(&dev_priv->gt);
 741         acpi_video_unregister();
 742         intel_opregion_unregister(dev_priv);
 743
 744         i915_perf_unregister(dev_priv);
 745         i915_pmu_unregister(dev_priv);
 746
 747         i915_teardown_sysfs(dev_priv);
 748         drm_dev_unplug(&dev_priv->drm);
 749
 750         i915_gem_driver_unregister(dev_priv);
 751 }
 752
 753 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
 754 {
 755         if (drm_debug_enabled(DRM_UT_DRIVER)) {
 756                 struct drm_printer p = drm_debug_printer("i915 device info:");
 757
 758                 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
 759                            INTEL_DEVID(dev_priv),
 760                            INTEL_REVID(dev_priv),
 761                            intel_platform_name(INTEL_INFO(dev_priv)->platform),
 762                            intel_subplatform(RUNTIME_INFO(dev_priv),
 763                                              INTEL_INFO(dev_priv)->platform),
 764                            INTEL_GEN(dev_priv));
 765
 766                 intel_device_info_print_static(INTEL_INFO(dev_priv), &p);
 767                 intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p);
 768                 intel_gt_info_print(&dev_priv->gt.info, &p);
 769         }
 770
 771         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
 772                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n");
 773         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
 774                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n");
 775         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
 776                 drm_info(&dev_priv->drm,
 777                          "DRM_I915_DEBUG_RUNTIME_PM enabled\n");
 778 }
 779
 780 static struct drm_i915_private *
 781 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
 782 {
 783         const struct intel_device_info *match_info =
 784                 (struct intel_device_info *)ent->driver_data;
 785         struct intel_device_info *device_info;
 786         struct drm_i915_private *i915;
 787
 788         i915 = devm_drm_dev_alloc(&pdev->dev, &driver,
 789                                   struct drm_i915_private, drm);
 790         if (IS_ERR(i915))
 791                 return i915;
 792
 793         i915->drm.pdev = pdev;
 794         pci_set_drvdata(pdev, i915);
 795
 796         /* Device parameters start as a copy of module parameters. */
 797         i915_params_copy(&i915->params, &i915_modparams);
 798
 799         /* Setup the write-once "constant" device info */
 800         device_info = mkwrite_device_info(i915);
 801         memcpy(device_info, match_info, sizeof(*device_info));
 802         RUNTIME_INFO(i915)->device_id = pdev->device;
 803
 804         BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
 805
 806         return i915;
 807 }
 808
 809 /**
 810  * i915_driver_probe - setup chip and create an initial config
 811  * @pdev: PCI device
 812  * @ent: matching PCI ID entry
 813  *
 814  * The driver probe routine has to do several things:
 815  *   - drive output discovery via intel_modeset_init()
 816  *   - initialize the memory manager
 817  *   - allocate initial config memory
 818  *   - setup the DRM framebuffer with the allocated memory
 819  */
 820 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 821 {
 822         const struct intel_device_info *match_info =
 823                 (struct intel_device_info *)ent->driver_data;
 824         struct drm_i915_private *i915;
 825         int ret;
 826
 827         i915 = i915_driver_create(pdev, ent);
 828         if (IS_ERR(i915))
 829                 return PTR_ERR(i915);
 830
 831         /* Disable nuclear pageflip by default on pre-ILK */
 832         if (!i915->params.nuclear_pageflip && match_info->gen < 5)
 833                 i915->drm.driver_features &= ~DRIVER_ATOMIC;
 834
 835         /*
 836          * Check if we support fake LMEM -- for now we only unleash this for
 837          * the live selftests(test-and-exit).
 838          */
 839 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 840         if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)) {
 841                 if (INTEL_GEN(i915) >= 9 && i915_selftest.live < 0 &&
 842                     i915->params.fake_lmem_start) {
 843                         mkwrite_device_info(i915)->memory_regions =
 844                                 REGION_SMEM | REGION_LMEM | REGION_STOLEN;
 845                         GEM_BUG_ON(!HAS_LMEM(i915));
 846                 }
 847         }
 848 #endif
 849
 850         ret = pci_enable_device(pdev);
 851         if (ret)
 852                 goto out_fini;
 853
 854         ret = i915_driver_early_probe(i915);
 855         if (ret < 0)
 856                 goto out_pci_disable;
 857
 858         disable_rpm_wakeref_asserts(&i915->runtime_pm);
 859
 860         intel_vgpu_detect(i915);
 861
 862         ret = i915_driver_mmio_probe(i915);
 863         if (ret < 0)
 864                 goto out_runtime_pm_put;
 865
 866         ret = i915_driver_hw_probe(i915);
 867         if (ret < 0)
 868                 goto out_cleanup_mmio;
 869
 870         ret = intel_modeset_init_noirq(i915);
 871         if (ret < 0)
 872                 goto out_cleanup_hw;
 873
 874         ret = intel_irq_install(i915);
 875         if (ret)
 876                 goto out_cleanup_modeset;
 877
 878         ret = intel_modeset_init_nogem(i915);
 879         if (ret)
 880                 goto out_cleanup_irq;
 881
 882         ret = i915_gem_init(i915);
 883         if (ret)
 884                 goto out_cleanup_modeset2;
 885
 886         ret = intel_modeset_init(i915);
 887         if (ret)
 888                 goto out_cleanup_gem;
 889
 890         i915_driver_register(i915);
 891
 892         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 893
 894         i915_welcome_messages(i915);
 895
 896         i915->do_release = true;
 897
 898         return 0;
 899
 900 out_cleanup_gem:
 901         i915_gem_suspend(i915);
 902         i915_gem_driver_remove(i915);
 903         i915_gem_driver_release(i915);
 904 out_cleanup_modeset2:
 905         /* FIXME clean up the error path */
 906         intel_modeset_driver_remove(i915);
 907         intel_irq_uninstall(i915);
 908         intel_modeset_driver_remove_noirq(i915);
 909         goto out_cleanup_modeset;
 910 out_cleanup_irq:
 911         intel_irq_uninstall(i915);
 912 out_cleanup_modeset:
 913         intel_modeset_driver_remove_nogem(i915);
 914 out_cleanup_hw:
 915         i915_driver_hw_remove(i915);
 916         intel_memory_regions_driver_release(i915);
 917         i915_ggtt_driver_release(i915);
 918 out_cleanup_mmio:
 919         i915_driver_mmio_release(i915);
 920 out_runtime_pm_put:
 921         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 922         i915_driver_late_release(i915);
 923 out_pci_disable:
 924         pci_disable_device(pdev);
 925 out_fini:
 926         i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
 927         return ret;
 928 }
 929
 930 void i915_driver_remove(struct drm_i915_private *i915)
 931 {
 932         disable_rpm_wakeref_asserts(&i915->runtime_pm);
 933
 934         i915_driver_unregister(i915);
 935
 936         /* Flush any external code that still may be under the RCU lock */
 937         synchronize_rcu();
 938
 939         i915_gem_suspend(i915);
 940
 941         intel_gvt_driver_remove(i915);
 942
 943         intel_modeset_driver_remove(i915);
 944
 945         intel_irq_uninstall(i915);
 946
 947         intel_modeset_driver_remove_noirq(i915);
 948
 949         i915_reset_error_state(i915);
 950         i915_gem_driver_remove(i915);
 951
 952         intel_modeset_driver_remove_nogem(i915);
 953
 954         i915_driver_hw_remove(i915);
 955
 956         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 957 }
 958
 959 static void i915_driver_release(struct drm_device *dev)
 960 {
 961         struct drm_i915_private *dev_priv = to_i915(dev);
 962         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
 963
 964         if (!dev_priv->do_release)
 965                 return;
 966
 967         disable_rpm_wakeref_asserts(rpm);
 968
 969         i915_gem_driver_release(dev_priv);
 970
 971         intel_memory_regions_driver_release(dev_priv);
 972         i915_ggtt_driver_release(dev_priv);
 973         i915_gem_drain_freed_objects(dev_priv);
 974
 975         i915_driver_mmio_release(dev_priv);
 976
 977         enable_rpm_wakeref_asserts(rpm);
 978         intel_runtime_pm_driver_release(rpm);
 979
 980         i915_driver_late_release(dev_priv);
 981 }
 982
 983 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
 984 {
 985         struct drm_i915_private *i915 = to_i915(dev);
 986         int ret;
 987
 988         ret = i915_gem_open(i915, file);
 989         if (ret)
 990                 return ret;
 991
 992         return 0;
 993 }
 994
 995 /**
 996  * i915_driver_lastclose - clean up after all DRM clients have exited
 997  * @dev: DRM device
 998  *
 999  * Take care of cleaning up after all DRM clients have exited.  In the
1000  * mode setting case, we want to restore the kernel's initial mode (just
1001  * in case the last client left us in a bad state).
1002  *
1003  * Additionally, in the non-mode setting case, we'll tear down the GTT
1004  * and DMA structures, since the kernel won't be using them, and clea
1005  * up any GEM state.
1006  */
1007 static void i915_driver_lastclose(struct drm_device *dev)
1008 {
1009         intel_fbdev_restore_mode(dev);
1010         vga_switcheroo_process_delayed_switch();
1011 }
1012
1013 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1014 {
1015         struct drm_i915_file_private *file_priv = file->driver_priv;
1016
1017         i915_gem_context_close(file);
1018
1019         kfree_rcu(file_priv, rcu);
1020
1021         /* Catch up with all the deferred frees from "this" client */
1022         i915_gem_flush_free_objects(to_i915(dev));
1023 }
1024
1025 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1026 {
1027         struct drm_device *dev = &dev_priv->drm;
1028         struct intel_encoder *encoder;
1029
1030         drm_modeset_lock_all(dev);
1031         for_each_intel_encoder(dev, encoder)
1032                 if (encoder->suspend)
1033                         encoder->suspend(encoder);
1034         drm_modeset_unlock_all(dev);
1035 }
1036
1037 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv)
1038 {
1039         struct drm_device *dev = &dev_priv->drm;
1040         struct intel_encoder *encoder;
1041
1042         drm_modeset_lock_all(dev);
1043         for_each_intel_encoder(dev, encoder)
1044                 if (encoder->shutdown)
1045                         encoder->shutdown(encoder);
1046         drm_modeset_unlock_all(dev);
1047 }
1048
1049 void i915_driver_shutdown(struct drm_i915_private *i915)
1050 {
1051         disable_rpm_wakeref_asserts(&i915->runtime_pm);
1052
1053         i915_gem_suspend(i915);
1054
1055         drm_kms_helper_poll_disable(&i915->drm);
1056
1057         drm_atomic_helper_shutdown(&i915->drm);
1058
1059         intel_dp_mst_suspend(i915);
1060
1061         intel_runtime_pm_disable_interrupts(i915);
1062         intel_hpd_cancel_work(i915);
1063
1064         intel_suspend_encoders(i915);
1065         intel_shutdown_encoders(i915);
1066
1067         enable_rpm_wakeref_asserts(&i915->runtime_pm);
1068 }
1069
1070 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1071 {
1072 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1073         if (acpi_target_system_state() < ACPI_STATE_S3)
1074                 return true;
1075 #endif
1076         return false;
1077 }
1078
1079 static int i915_drm_prepare(struct drm_device *dev)
1080 {
1081         struct drm_i915_private *i915 = to_i915(dev);
1082
1083         /*
1084          * NB intel_display_suspend() may issue new requests after we've
1085          * ostensibly marked the GPU as ready-to-sleep here. We need to
1086          * split out that work and pull it forward so that after point,
1087          * the GPU is not woken again.
1088          */
1089         i915_gem_suspend(i915);
1090
1091         return 0;
1092 }
1093
1094 static int i915_drm_suspend(struct drm_device *dev)
1095 {
1096         struct drm_i915_private *dev_priv = to_i915(dev);
1097         struct pci_dev *pdev = dev_priv->drm.pdev;
1098         pci_power_t opregion_target_state;
1099
1100         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1101
1102         /* We do a lot of poking in a lot of registers, make sure they work
1103          * properly. */
1104         intel_power_domains_disable(dev_priv);
1105
1106         drm_kms_helper_poll_disable(dev);
1107
1108         pci_save_state(pdev);
1109
1110         intel_display_suspend(dev);
1111
1112         intel_dp_mst_suspend(dev_priv);
1113
1114         intel_runtime_pm_disable_interrupts(dev_priv);
1115         intel_hpd_cancel_work(dev_priv);
1116
1117         intel_suspend_encoders(dev_priv);
1118
1119         intel_suspend_hw(dev_priv);
1120
1121         i915_ggtt_suspend(&dev_priv->ggtt);
1122
1123         i915_save_display(dev_priv);
1124
1125         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1126         intel_opregion_suspend(dev_priv, opregion_target_state);
1127
1128         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1129
1130         dev_priv->suspend_count++;
1131
1132         intel_csr_ucode_suspend(dev_priv);
1133
1134         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1135
1136         return 0;
1137 }
1138
1139 static enum i915_drm_suspend_mode
1140 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1141 {
1142         if (hibernate)
1143                 return I915_DRM_SUSPEND_HIBERNATE;
1144
1145         if (suspend_to_idle(dev_priv))
1146                 return I915_DRM_SUSPEND_IDLE;
1147
1148         return I915_DRM_SUSPEND_MEM;
1149 }
1150
1151 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1152 {
1153         struct drm_i915_private *dev_priv = to_i915(dev);
1154         struct pci_dev *pdev = dev_priv->drm.pdev;
1155         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1156         int ret;
1157
1158         disable_rpm_wakeref_asserts(rpm);
1159
1160         i915_gem_suspend_late(dev_priv);
1161
1162         intel_uncore_suspend(&dev_priv->uncore);
1163
1164         intel_power_domains_suspend(dev_priv,
1165                                     get_suspend_mode(dev_priv, hibernation));
1166
1167         intel_display_power_suspend_late(dev_priv);
1168
1169         ret = vlv_suspend_complete(dev_priv);
1170         if (ret) {
1171                 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);
1172                 intel_power_domains_resume(dev_priv);
1173
1174                 goto out;
1175         }
1176
1177         pci_disable_device(pdev);
1178         /*
1179          * During hibernation on some platforms the BIOS may try to access
1180          * the device even though it's already in D3 and hang the machine. So
1181          * leave the device in D0 on those platforms and hope the BIOS will
1182          * power down the device properly. The issue was seen on multiple old
1183          * GENs with different BIOS vendors, so having an explicit blacklist
1184          * is inpractical; apply the workaround on everything pre GEN6. The
1185          * platforms where the issue was seen:
1186          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1187          * Fujitsu FSC S7110
1188          * Acer Aspire 1830T
1189          */
1190         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1191                 pci_set_power_state(pdev, PCI_D3hot);
1192
1193 out:
1194         enable_rpm_wakeref_asserts(rpm);
1195         if (!dev_priv->uncore.user_forcewake_count)
1196                 intel_runtime_pm_driver_release(rpm);
1197
1198         return ret;
1199 }
1200
1201 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state)
1202 {
1203         int error;
1204
1205         if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&
1206                              state.event != PM_EVENT_FREEZE))
1207                 return -EINVAL;
1208
1209         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1210                 return 0;
1211
1212         error = i915_drm_suspend(&i915->drm);
1213         if (error)
1214                 return error;
1215
1216         return i915_drm_suspend_late(&i915->drm, false);
1217 }
1218
1219 static int i915_drm_resume(struct drm_device *dev)
1220 {
1221         struct drm_i915_private *dev_priv = to_i915(dev);
1222         int ret;
1223
1224         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1225
1226         sanitize_gpu(dev_priv);
1227
1228         ret = i915_ggtt_enable_hw(dev_priv);
1229         if (ret)
1230                 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
1231
1232         i915_ggtt_resume(&dev_priv->ggtt);
1233
1234         intel_csr_ucode_resume(dev_priv);
1235
1236         i915_restore_display(dev_priv);
1237         intel_pps_unlock_regs_wa(dev_priv);
1238
1239         intel_init_pch_refclk(dev_priv);
1240
1241         /*
1242          * Interrupts have to be enabled before any batches are run. If not the
1243          * GPU will hang. i915_gem_init_hw() will initiate batches to
1244          * update/restore the context.
1245          *
1246          * drm_mode_config_reset() needs AUX interrupts.
1247          *
1248          * Modeset enabling in intel_modeset_init_hw() also needs working
1249          * interrupts.
1250          */
1251         intel_runtime_pm_enable_interrupts(dev_priv);
1252
1253         drm_mode_config_reset(dev);
1254
1255         i915_gem_resume(dev_priv);
1256
1257         intel_modeset_init_hw(dev_priv);
1258         intel_init_clock_gating(dev_priv);
1259         intel_hpd_init(dev_priv);
1260
1261         /* MST sideband requires HPD interrupts enabled */
1262         intel_dp_mst_resume(dev_priv);
1263         intel_display_resume(dev);
1264
1265         intel_hpd_poll_disable(dev_priv);
1266         drm_kms_helper_poll_enable(dev);
1267
1268         intel_opregion_resume(dev_priv);
1269
1270         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1271
1272         intel_power_domains_enable(dev_priv);
1273
1274         intel_gvt_resume(dev_priv);
1275
1276         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1277
1278         return 0;
1279 }
1280
1281 static int i915_drm_resume_early(struct drm_device *dev)
1282 {
1283         struct drm_i915_private *dev_priv = to_i915(dev);
1284         struct pci_dev *pdev = dev_priv->drm.pdev;
1285         int ret;
1286
1287         /*
1288          * We have a resume ordering issue with the snd-hda driver also
1289          * requiring our device to be power up. Due to the lack of a
1290          * parent/child relationship we currently solve this with an early
1291          * resume hook.
1292          *
1293          * FIXME: This should be solved with a special hdmi sink device or
1294          * similar so that power domains can be employed.
1295          */
1296
1297         /*
1298          * Note that we need to set the power state explicitly, since we
1299          * powered off the device during freeze and the PCI core won't power
1300          * it back up for us during thaw. Powering off the device during
1301          * freeze is not a hard requirement though, and during the
1302          * suspend/resume phases the PCI core makes sure we get here with the
1303          * device powered on. So in case we change our freeze logic and keep
1304          * the device powered we can also remove the following set power state
1305          * call.
1306          */
1307         ret = pci_set_power_state(pdev, PCI_D0);
1308         if (ret) {
1309                 drm_err(&dev_priv->drm,
1310                         "failed to set PCI D0 power state (%d)\n", ret);
1311                 return ret;
1312         }
1313
1314         /*
1315          * Note that pci_enable_device() first enables any parent bridge
1316          * device and only then sets the power state for this device. The
1317          * bridge enabling is a nop though, since bridge devices are resumed
1318          * first. The order of enabling power and enabling the device is
1319          * imposed by the PCI core as described above, so here we preserve the
1320          * same order for the freeze/thaw phases.
1321          *
1322          * TODO: eventually we should remove pci_disable_device() /
1323          * pci_enable_enable_device() from suspend/resume. Due to how they
1324          * depend on the device enable refcount we can't anyway depend on them
1325          * disabling/enabling the device.
1326          */
1327         if (pci_enable_device(pdev))
1328                 return -EIO;
1329
1330         pci_set_master(pdev);
1331
1332         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1333
1334         ret = vlv_resume_prepare(dev_priv, false);
1335         if (ret)
1336                 drm_err(&dev_priv->drm,
1337                         "Resume prepare failed: %d, continuing anyway\n", ret);
1338
1339         intel_uncore_resume_early(&dev_priv->uncore);
1340
1341         intel_gt_check_and_clear_faults(&dev_priv->gt);
1342
1343         intel_display_power_resume_early(dev_priv);
1344
1345         intel_power_domains_resume(dev_priv);
1346
1347         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1348
1349         return ret;
1350 }
1351
1352 int i915_resume_switcheroo(struct drm_i915_private *i915)
1353 {
1354         int ret;
1355
1356         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1357                 return 0;
1358
1359         ret = i915_drm_resume_early(&i915->drm);
1360         if (ret)
1361                 return ret;
1362
1363         return i915_drm_resume(&i915->drm);
1364 }
1365
1366 static int i915_pm_prepare(struct device *kdev)
1367 {
1368         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1369
1370         if (!i915) {
1371                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1372                 return -ENODEV;
1373         }
1374
1375         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1376                 return 0;
1377
1378         return i915_drm_prepare(&i915->drm);
1379 }
1380
1381 static int i915_pm_suspend(struct device *kdev)
1382 {
1383         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1384
1385         if (!i915) {
1386                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1387                 return -ENODEV;
1388         }
1389
1390         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1391                 return 0;
1392
1393         return i915_drm_suspend(&i915->drm);
1394 }
1395
1396 static int i915_pm_suspend_late(struct device *kdev)
1397 {
1398         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1399
1400         /*
1401          * We have a suspend ordering issue with the snd-hda driver also
1402          * requiring our device to be power up. Due to the lack of a
1403          * parent/child relationship we currently solve this with an late
1404          * suspend hook.
1405          *
1406          * FIXME: This should be solved with a special hdmi sink device or
1407          * similar so that power domains can be employed.
1408          */
1409         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1410                 return 0;
1411
1412         return i915_drm_suspend_late(&i915->drm, false);
1413 }
1414
1415 static int i915_pm_poweroff_late(struct device *kdev)
1416 {
1417         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1418
1419         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1420                 return 0;
1421
1422         return i915_drm_suspend_late(&i915->drm, true);
1423 }
1424
1425 static int i915_pm_resume_early(struct device *kdev)
1426 {
1427         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1428
1429         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1430                 return 0;
1431
1432         return i915_drm_resume_early(&i915->drm);
1433 }
1434
1435 static int i915_pm_resume(struct device *kdev)
1436 {
1437         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1438
1439         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1440                 return 0;
1441
1442         return i915_drm_resume(&i915->drm);
1443 }
1444
1445 /* freeze: before creating the hibernation_image */
1446 static int i915_pm_freeze(struct device *kdev)
1447 {
1448         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1449         int ret;
1450
1451         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1452                 ret = i915_drm_suspend(&i915->drm);
1453                 if (ret)
1454                         return ret;
1455         }
1456
1457         ret = i915_gem_freeze(i915);
1458         if (ret)
1459                 return ret;
1460
1461         return 0;
1462 }
1463
1464 static int i915_pm_freeze_late(struct device *kdev)
1465 {
1466         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1467         int ret;
1468
1469         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1470                 ret = i915_drm_suspend_late(&i915->drm, true);
1471                 if (ret)
1472                         return ret;
1473         }
1474
1475         ret = i915_gem_freeze_late(i915);
1476         if (ret)
1477                 return ret;
1478
1479         return 0;
1480 }
1481
1482 /* thaw: called after creating the hibernation image, but before turning off. */
1483 static int i915_pm_thaw_early(struct device *kdev)
1484 {
1485         return i915_pm_resume_early(kdev);
1486 }
1487
1488 static int i915_pm_thaw(struct device *kdev)
1489 {
1490         return i915_pm_resume(kdev);
1491 }
1492
1493 /* restore: called after loading the hibernation image. */
1494 static int i915_pm_restore_early(struct device *kdev)
1495 {
1496         return i915_pm_resume_early(kdev);
1497 }
1498
1499 static int i915_pm_restore(struct device *kdev)
1500 {
1501         return i915_pm_resume(kdev);
1502 }
1503
1504 static int intel_runtime_suspend(struct device *kdev)
1505 {
1506         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1507         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1508         int ret;
1509
1510         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1511                 return -ENODEV;
1512
1513         drm_dbg_kms(&dev_priv->drm, "Suspending device\n");
1514
1515         disable_rpm_wakeref_asserts(rpm);
1516
1517         /*
1518          * We are safe here against re-faults, since the fault handler takes
1519          * an RPM reference.
1520          */
1521         i915_gem_runtime_suspend(dev_priv);
1522
1523         intel_gt_runtime_suspend(&dev_priv->gt);
1524
1525         intel_runtime_pm_disable_interrupts(dev_priv);
1526
1527         intel_uncore_suspend(&dev_priv->uncore);
1528
1529         intel_display_power_suspend(dev_priv);
1530
1531         ret = vlv_suspend_complete(dev_priv);
1532         if (ret) {
1533                 drm_err(&dev_priv->drm,
1534                         "Runtime suspend failed, disabling it (%d)\n", ret);
1535                 intel_uncore_runtime_resume(&dev_priv->uncore);
1536
1537                 intel_runtime_pm_enable_interrupts(dev_priv);
1538
1539                 intel_gt_runtime_resume(&dev_priv->gt);
1540
1541                 enable_rpm_wakeref_asserts(rpm);
1542
1543                 return ret;
1544         }
1545
1546         enable_rpm_wakeref_asserts(rpm);
1547         intel_runtime_pm_driver_release(rpm);
1548
1549         if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
1550                 drm_err(&dev_priv->drm,
1551                         "Unclaimed access detected prior to suspending\n");
1552
1553         rpm->suspended = true;
1554
1555         /*
1556          * FIXME: We really should find a document that references the arguments
1557          * used below!
1558          */
1559         if (IS_BROADWELL(dev_priv)) {
1560                 /*
1561                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1562                  * being detected, and the call we do at intel_runtime_resume()
1563                  * won't be able to restore them. Since PCI_D3hot matches the
1564                  * actual specification and appears to be working, use it.
1565                  */
1566                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
1567         } else {
1568                 /*
1569                  * current versions of firmware which depend on this opregion
1570                  * notification have repurposed the D1 definition to mean
1571                  * "runtime suspended" vs. what you would normally expect (D3)
1572                  * to distinguish it from notifications that might be sent via
1573                  * the suspend path.
1574                  */
1575                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
1576         }
1577
1578         assert_forcewakes_inactive(&dev_priv->uncore);
1579
1580         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1581                 intel_hpd_poll_enable(dev_priv);
1582
1583         drm_dbg_kms(&dev_priv->drm, "Device suspended\n");
1584         return 0;
1585 }
1586
1587 static int intel_runtime_resume(struct device *kdev)
1588 {
1589         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1590         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1591         int ret;
1592
1593         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1594                 return -ENODEV;
1595
1596         drm_dbg_kms(&dev_priv->drm, "Resuming device\n");
1597
1598         drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
1599         disable_rpm_wakeref_asserts(rpm);
1600
1601         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1602         rpm->suspended = false;
1603         if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
1604                 drm_dbg(&dev_priv->drm,
1605                         "Unclaimed access during suspend, bios?\n");
1606
1607         intel_display_power_resume(dev_priv);
1608
1609         ret = vlv_resume_prepare(dev_priv, true);
1610
1611         intel_uncore_runtime_resume(&dev_priv->uncore);
1612
1613         intel_runtime_pm_enable_interrupts(dev_priv);
1614
1615         /*
1616          * No point of rolling back things in case of an error, as the best
1617          * we can do is to hope that things will still work (and disable RPM).
1618          */
1619         intel_gt_runtime_resume(&dev_priv->gt);
1620
1621         /*
1622          * On VLV/CHV display interrupts are part of the display
1623          * power well, so hpd is reinitialized from there. For
1624          * everyone else do it here.
1625          */
1626         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
1627                 intel_hpd_init(dev_priv);
1628                 intel_hpd_poll_disable(dev_priv);
1629         }
1630
1631         intel_enable_ipc(dev_priv);
1632
1633         enable_rpm_wakeref_asserts(rpm);
1634
1635         if (ret)
1636                 drm_err(&dev_priv->drm,
1637                         "Runtime resume failed, disabling it (%d)\n", ret);
1638         else
1639                 drm_dbg_kms(&dev_priv->drm, "Device resumed\n");
1640
1641         return ret;
1642 }
1643
1644 const struct dev_pm_ops i915_pm_ops = {
1645         /*
1646          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1647          * PMSG_RESUME]
1648          */
1649         .prepare = i915_pm_prepare,
1650         .suspend = i915_pm_suspend,
1651         .suspend_late = i915_pm_suspend_late,
1652         .resume_early = i915_pm_resume_early,
1653         .resume = i915_pm_resume,
1654
1655         /*
1656          * S4 event handlers
1657          * @freeze, @freeze_late    : called (1) before creating the
1658          *                            hibernation image [PMSG_FREEZE] and
1659          *                            (2) after rebooting, before restoring
1660          *                            the image [PMSG_QUIESCE]
1661          * @thaw, @thaw_early       : called (1) after creating the hibernation
1662          *                            image, before writing it [PMSG_THAW]
1663          *                            and (2) after failing to create or
1664          *                            restore the image [PMSG_RECOVER]
1665          * @poweroff, @poweroff_late: called after writing the hibernation
1666          *                            image, before rebooting [PMSG_HIBERNATE]
1667          * @restore, @restore_early : called after rebooting and restoring the
1668          *                            hibernation image [PMSG_RESTORE]
1669          */
1670         .freeze = i915_pm_freeze,
1671         .freeze_late = i915_pm_freeze_late,
1672         .thaw_early = i915_pm_thaw_early,
1673         .thaw = i915_pm_thaw,
1674         .poweroff = i915_pm_suspend,
1675         .poweroff_late = i915_pm_poweroff_late,
1676         .restore_early = i915_pm_restore_early,
1677         .restore = i915_pm_restore,
1678
1679         /* S0ix (via runtime suspend) event handlers */
1680         .runtime_suspend = intel_runtime_suspend,
1681         .runtime_resume = intel_runtime_resume,
1682 };
1683
1684 static const struct file_operations i915_driver_fops = {
1685         .owner = THIS_MODULE,
1686         .open = drm_open,
1687         .release = drm_release_noglobal,
1688         .unlocked_ioctl = drm_ioctl,
1689         .mmap = i915_gem_mmap,
1690         .poll = drm_poll,
1691         .read = drm_read,
1692         .compat_ioctl = i915_ioc32_compat_ioctl,
1693         .llseek = noop_llseek,
1694 };
1695
1696 static int
1697 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1698                           struct drm_file *file)
1699 {
1700         return -ENODEV;
1701 }
1702
1703 static const struct drm_ioctl_desc i915_ioctls[] = {
1704         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1705         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1706         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1707         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1708         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1709         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1710         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
1711         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1712         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1713         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1714         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1715         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1716         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1717         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1718         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
1719         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1720         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1721         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1722         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
1723         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
1724         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1725         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1726         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
1727         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1728         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1729         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
1730         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1731         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1732         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1733         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1734         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1735         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1736         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
1737         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1738         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1739         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
1740         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
1741         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1742         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
1743         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1744         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
1745         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
1746         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
1747         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
1748         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
1749         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1750         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1751         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1752         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
1753         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1754         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1755         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1756         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
1757         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
1758         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
1759         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
1760         DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
1761         DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
1762 };
1763
1764 static const struct drm_driver driver = {
1765         /* Don't use MTRRs here; the Xserver or userspace app should
1766          * deal with them for Intel hardware.
1767          */
1768         .driver_features =
1769             DRIVER_GEM |
1770             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ |
1771             DRIVER_SYNCOBJ_TIMELINE,
1772         .release = i915_driver_release,
1773         .open = i915_driver_open,
1774         .lastclose = i915_driver_lastclose,
1775         .postclose = i915_driver_postclose,
1776
1777         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1778         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1779         .gem_prime_import = i915_gem_prime_import,
1780
1781         .dumb_create = i915_gem_dumb_create,
1782         .dumb_map_offset = i915_gem_dumb_mmap_offset,
1783
1784         .ioctls = i915_ioctls,
1785         .num_ioctls = ARRAY_SIZE(i915_ioctls),
1786         .fops = &i915_driver_fops,
1787         .name = DRIVER_NAME,
1788         .desc = DRIVER_DESC,
1789         .date = DRIVER_DATE,
1790         .major = DRIVER_MAJOR,
1791         .minor = DRIVER_MINOR,
1792         .patchlevel = DRIVER_PATCHLEVEL,
1793 };