drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vga_switcheroo.h>
  40 #include <linux/vt.h>
  41
  42 #include <drm/drm_aperture.h>
  43 #include <drm/drm_atomic_helper.h>
  44 #include <drm/drm_ioctl.h>
  45 #include <drm/drm_irq.h>
  46 #include <drm/drm_managed.h>
  47 #include <drm/drm_probe_helper.h>
  48
  49 #include "display/intel_acpi.h"
  50 #include "display/intel_bw.h"
  51 #include "display/intel_cdclk.h"
  52 #include "display/intel_csr.h"
  53 #include "display/intel_display_types.h"
  54 #include "display/intel_dp.h"
  55 #include "display/intel_fbdev.h"
  56 #include "display/intel_hotplug.h"
  57 #include "display/intel_overlay.h"
  58 #include "display/intel_pipe_crc.h"
  59 #include "display/intel_pps.h"
  60 #include "display/intel_sprite.h"
  61 #include "display/intel_vga.h"
  62
  63 #include "gem/i915_gem_context.h"
  64 #include "gem/i915_gem_ioctls.h"
  65 #include "gem/i915_gem_mman.h"
  66 #include "gem/i915_gem_pm.h"
  67 #include "gt/intel_gt.h"
  68 #include "gt/intel_gt_pm.h"
  69 #include "gt/intel_rc6.h"
  70
  71 #include "i915_debugfs.h"
  72 #include "i915_drv.h"
  73 #include "i915_ioc32.h"
  74 #include "i915_irq.h"
  75 #include "i915_memcpy.h"
  76 #include "i915_perf.h"
  77 #include "i915_query.h"
  78 #include "i915_suspend.h"
  79 #include "i915_switcheroo.h"
  80 #include "i915_sysfs.h"
  81 #include "i915_trace.h"
  82 #include "i915_vgpu.h"
  83 #include "intel_dram.h"
  84 #include "intel_gvt.h"
  85 #include "intel_memory_region.h"
  86 #include "intel_pm.h"
  87 #include "intel_sideband.h"
  88 #include "vlv_suspend.h"
  89
  90 static const struct drm_driver driver;
  91
  92 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
  93 {
  94         int domain = pci_domain_nr(to_pci_dev(dev_priv->drm.dev)->bus);
  95
  96         dev_priv->bridge_dev =
  97                 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
  98         if (!dev_priv->bridge_dev) {
  99                 drm_err(&dev_priv->drm, "bridge device not found\n");
 100                 return -1;
 101         }
 102         return 0;
 103 }
 104
 105 /* Allocate space for the MCH regs if needed, return nonzero on error */
 106 static int
 107 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 108 {
 109         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 110         u32 temp_lo, temp_hi = 0;
 111         u64 mchbar_addr;
 112         int ret;
 113
 114         if (INTEL_GEN(dev_priv) >= 4)
 115                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 116         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 117         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 118
 119         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 120 #ifdef CONFIG_PNP
 121         if (mchbar_addr &&
 122             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 123                 return 0;
 124 #endif
 125
 126         /* Get some space for it */
 127         dev_priv->mch_res.name = "i915 MCHBAR";
 128         dev_priv->mch_res.flags = IORESOURCE_MEM;
 129         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 130                                      &dev_priv->mch_res,
 131                                      MCHBAR_SIZE, MCHBAR_SIZE,
 132                                      PCIBIOS_MIN_MEM,
 133                                      0, pcibios_align_resource,
 134                                      dev_priv->bridge_dev);
 135         if (ret) {
 136                 drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret);
 137                 dev_priv->mch_res.start = 0;
 138                 return ret;
 139         }
 140
 141         if (INTEL_GEN(dev_priv) >= 4)
 142                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 143                                        upper_32_bits(dev_priv->mch_res.start));
 144
 145         pci_write_config_dword(dev_priv->bridge_dev, reg,
 146                                lower_32_bits(dev_priv->mch_res.start));
 147         return 0;
 148 }
 149
 150 /* Setup MCHBAR if possible, return true if we should disable it again */
 151 static void
 152 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 153 {
 154         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 155         u32 temp;
 156         bool enabled;
 157
 158         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 159                 return;
 160
 161         dev_priv->mchbar_need_disable = false;
 162
 163         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 164                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 165                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 166         } else {
 167                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 168                 enabled = temp & 1;
 169         }
 170
 171         /* If it's already enabled, don't have to do anything */
 172         if (enabled)
 173                 return;
 174
 175         if (intel_alloc_mchbar_resource(dev_priv))
 176                 return;
 177
 178         dev_priv->mchbar_need_disable = true;
 179
 180         /* Space is allocated or reserved, so enable it. */
 181         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 182                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 183                                        temp | DEVEN_MCHBAR_EN);
 184         } else {
 185                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 186                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 187         }
 188 }
 189
 190 static void
 191 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 192 {
 193         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 194
 195         if (dev_priv->mchbar_need_disable) {
 196                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 197                         u32 deven_val;
 198
 199                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 200                                               &deven_val);
 201                         deven_val &= ~DEVEN_MCHBAR_EN;
 202                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 203                                                deven_val);
 204                 } else {
 205                         u32 mchbar_val;
 206
 207                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 208                                               &mchbar_val);
 209                         mchbar_val &= ~1;
 210                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 211                                                mchbar_val);
 212                 }
 213         }
 214
 215         if (dev_priv->mch_res.start)
 216                 release_resource(&dev_priv->mch_res);
 217 }
 218
 219 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 220 {
 221         /*
 222          * The i915 workqueue is primarily used for batched retirement of
 223          * requests (and thus managing bo) once the task has been completed
 224          * by the GPU. i915_retire_requests() is called directly when we
 225          * need high-priority retirement, such as waiting for an explicit
 226          * bo.
 227          *
 228          * It is also used for periodic low-priority events, such as
 229          * idle-timers and recording error state.
 230          *
 231          * All tasks on the workqueue are expected to acquire the dev mutex
 232          * so there is no point in running more than one instance of the
 233          * workqueue at any time.  Use an ordered one.
 234          */
 235         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 236         if (dev_priv->wq == NULL)
 237                 goto out_err;
 238
 239         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 240         if (dev_priv->hotplug.dp_wq == NULL)
 241                 goto out_free_wq;
 242
 243         return 0;
 244
 245 out_free_wq:
 246         destroy_workqueue(dev_priv->wq);
 247 out_err:
 248         drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n");
 249
 250         return -ENOMEM;
 251 }
 252
 253 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 254 {
 255         destroy_workqueue(dev_priv->hotplug.dp_wq);
 256         destroy_workqueue(dev_priv->wq);
 257 }
 258
 259 /*
 260  * We don't keep the workarounds for pre-production hardware, so we expect our
 261  * driver to fail on these machines in one way or another. A little warning on
 262  * dmesg may help both the user and the bug triagers.
 263  *
 264  * Our policy for removing pre-production workarounds is to keep the
 265  * current gen workarounds as a guide to the bring-up of the next gen
 266  * (workarounds have a habit of persisting!). Anything older than that
 267  * should be removed along with the complications they introduce.
 268  */
 269 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 270 {
 271         bool pre = false;
 272
 273         pre |= IS_HSW_EARLY_SDV(dev_priv);
 274         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 275         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 276         pre |= IS_KBL_GT_STEP(dev_priv, 0, STEP_A0);
 277         pre |= IS_GLK_REVID(dev_priv, 0, GLK_REVID_A2);
 278
 279         if (pre) {
 280                 drm_err(&dev_priv->drm, "This is a pre-production stepping. "
 281                           "It may not be fully functional.\n");
 282                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 283         }
 284 }
 285
 286 static void sanitize_gpu(struct drm_i915_private *i915)
 287 {
 288         if (!INTEL_INFO(i915)->gpu_reset_clobbers_display)
 289                 __intel_gt_reset(&i915->gt, ALL_ENGINES);
 290 }
 291
 292 /**
 293  * i915_driver_early_probe - setup state not requiring device access
 294  * @dev_priv: device private
 295  *
 296  * Initialize everything that is a "SW-only" state, that is state not
 297  * requiring accessing the device or exposing the driver via kernel internal
 298  * or userspace interfaces. Example steps belonging here: lock initialization,
 299  * system memory allocation, setting up device specific attributes and
 300  * function hooks not requiring accessing the device.
 301  */
 302 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
 303 {
 304         int ret = 0;
 305
 306         if (i915_inject_probe_failure(dev_priv))
 307                 return -ENODEV;
 308
 309         intel_device_info_subplatform_init(dev_priv);
 310         intel_step_init(dev_priv);
 311
 312         intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
 313         intel_uncore_init_early(&dev_priv->uncore, dev_priv);
 314
 315         spin_lock_init(&dev_priv->irq_lock);
 316         spin_lock_init(&dev_priv->gpu_error.lock);
 317         mutex_init(&dev_priv->backlight_lock);
 318
 319         mutex_init(&dev_priv->sb_lock);
 320         cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
 321
 322         mutex_init(&dev_priv->av_mutex);
 323         mutex_init(&dev_priv->wm.wm_mutex);
 324         mutex_init(&dev_priv->pps_mutex);
 325         mutex_init(&dev_priv->hdcp_comp_mutex);
 326
 327         i915_memcpy_init_early(dev_priv);
 328         intel_runtime_pm_init_early(&dev_priv->runtime_pm);
 329
 330         ret = i915_workqueues_init(dev_priv);
 331         if (ret < 0)
 332                 return ret;
 333
 334         ret = vlv_suspend_init(dev_priv);
 335         if (ret < 0)
 336                 goto err_workqueues;
 337
 338         intel_wopcm_init_early(&dev_priv->wopcm);
 339
 340         intel_gt_init_early(&dev_priv->gt, dev_priv);
 341
 342         i915_gem_init_early(dev_priv);
 343
 344         /* This must be called before any calls to HAS_PCH_* */
 345         intel_detect_pch(dev_priv);
 346
 347         intel_pm_setup(dev_priv);
 348         ret = intel_power_domains_init(dev_priv);
 349         if (ret < 0)
 350                 goto err_gem;
 351         intel_irq_init(dev_priv);
 352         intel_init_display_hooks(dev_priv);
 353         intel_init_clock_gating_hooks(dev_priv);
 354
 355         intel_detect_preproduction_hw(dev_priv);
 356
 357         return 0;
 358
 359 err_gem:
 360         i915_gem_cleanup_early(dev_priv);
 361         intel_gt_driver_late_release(&dev_priv->gt);
 362         vlv_suspend_cleanup(dev_priv);
 363 err_workqueues:
 364         i915_workqueues_cleanup(dev_priv);
 365         return ret;
 366 }
 367
 368 /**
 369  * i915_driver_late_release - cleanup the setup done in
 370  *                             i915_driver_early_probe()
 371  * @dev_priv: device private
 372  */
 373 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
 374 {
 375         intel_irq_fini(dev_priv);
 376         intel_power_domains_cleanup(dev_priv);
 377         i915_gem_cleanup_early(dev_priv);
 378         intel_gt_driver_late_release(&dev_priv->gt);
 379         vlv_suspend_cleanup(dev_priv);
 380         i915_workqueues_cleanup(dev_priv);
 381
 382         cpu_latency_qos_remove_request(&dev_priv->sb_qos);
 383         mutex_destroy(&dev_priv->sb_lock);
 384
 385         i915_params_free(&dev_priv->params);
 386 }
 387
 388 /**
 389  * i915_driver_mmio_probe - setup device MMIO
 390  * @dev_priv: device private
 391  *
 392  * Setup minimal device state necessary for MMIO accesses later in the
 393  * initialization sequence. The setup here should avoid any other device-wide
 394  * side effects or exposing the driver via kernel internal or user space
 395  * interfaces.
 396  */
 397 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
 398 {
 399         int ret;
 400
 401         if (i915_inject_probe_failure(dev_priv))
 402                 return -ENODEV;
 403
 404         if (i915_get_bridge_dev(dev_priv))
 405                 return -EIO;
 406
 407         ret = intel_uncore_init_mmio(&dev_priv->uncore);
 408         if (ret < 0)
 409                 goto err_bridge;
 410
 411         /* Try to make sure MCHBAR is enabled before poking at it */
 412         intel_setup_mchbar(dev_priv);
 413         intel_device_info_runtime_init(dev_priv);
 414
 415         ret = intel_gt_init_mmio(&dev_priv->gt);
 416         if (ret)
 417                 goto err_uncore;
 418
 419         /* As early as possible, scrub existing GPU state before clobbering */
 420         sanitize_gpu(dev_priv);
 421
 422         return 0;
 423
 424 err_uncore:
 425         intel_teardown_mchbar(dev_priv);
 426         intel_uncore_fini_mmio(&dev_priv->uncore);
 427 err_bridge:
 428         pci_dev_put(dev_priv->bridge_dev);
 429
 430         return ret;
 431 }
 432
 433 /**
 434  * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
 435  * @dev_priv: device private
 436  */
 437 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
 438 {
 439         intel_teardown_mchbar(dev_priv);
 440         intel_uncore_fini_mmio(&dev_priv->uncore);
 441         pci_dev_put(dev_priv->bridge_dev);
 442 }
 443
 444 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 445 {
 446         intel_gvt_sanitize_options(dev_priv);
 447 }
 448
 449 /**
 450  * i915_set_dma_info - set all relevant PCI dma info as configured for the
 451  * platform
 452  * @i915: valid i915 instance
 453  *
 454  * Set the dma max segment size, device and coherent masks.  The dma mask set
 455  * needs to occur before i915_ggtt_probe_hw.
 456  *
 457  * A couple of platforms have special needs.  Address them as well.
 458  *
 459  */
 460 static int i915_set_dma_info(struct drm_i915_private *i915)
 461 {
 462         unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size;
 463         int ret;
 464
 465         GEM_BUG_ON(!mask_size);
 466
 467         /*
 468          * We don't have a max segment size, so set it to the max so sg's
 469          * debugging layer doesn't complain
 470          */
 471         dma_set_max_seg_size(i915->drm.dev, UINT_MAX);
 472
 473         ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
 474         if (ret)
 475                 goto mask_err;
 476
 477         /* overlay on gen2 is broken and can't address above 1G */
 478         if (IS_GEN(i915, 2))
 479                 mask_size = 30;
 480
 481         /*
 482          * 965GM sometimes incorrectly writes to hardware status page (HWS)
 483          * using 32bit addressing, overwriting memory if HWS is located
 484          * above 4GB.
 485          *
 486          * The documentation also mentions an issue with undefined
 487          * behaviour if any general state is accessed within a page above 4GB,
 488          * which also needs to be handled carefully.
 489          */
 490         if (IS_I965G(i915) || IS_I965GM(i915))
 491                 mask_size = 32;
 492
 493         ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
 494         if (ret)
 495                 goto mask_err;
 496
 497         return 0;
 498
 499 mask_err:
 500         drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret);
 501         return ret;
 502 }
 503
 504 /**
 505  * i915_driver_hw_probe - setup state requiring device access
 506  * @dev_priv: device private
 507  *
 508  * Setup state that requires accessing the device, but doesn't require
 509  * exposing the driver via kernel internal or userspace interfaces.
 510  */
 511 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
 512 {
 513         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 514         int ret;
 515
 516         if (i915_inject_probe_failure(dev_priv))
 517                 return -ENODEV;
 518
 519         if (HAS_PPGTT(dev_priv)) {
 520                 if (intel_vgpu_active(dev_priv) &&
 521                     !intel_vgpu_has_full_ppgtt(dev_priv)) {
 522                         i915_report_error(dev_priv,
 523                                           "incompatible vGPU found, support for isolated ppGTT required\n");
 524                         return -ENXIO;
 525                 }
 526         }
 527
 528         if (HAS_EXECLISTS(dev_priv)) {
 529                 /*
 530                  * Older GVT emulation depends upon intercepting CSB mmio,
 531                  * which we no longer use, preferring to use the HWSP cache
 532                  * instead.
 533                  */
 534                 if (intel_vgpu_active(dev_priv) &&
 535                     !intel_vgpu_has_hwsp_emulation(dev_priv)) {
 536                         i915_report_error(dev_priv,
 537                                           "old vGPU host found, support for HWSP emulation required\n");
 538                         return -ENXIO;
 539                 }
 540         }
 541
 542         intel_sanitize_options(dev_priv);
 543
 544         /* needs to be done before ggtt probe */
 545         intel_dram_edram_detect(dev_priv);
 546
 547         ret = i915_set_dma_info(dev_priv);
 548         if (ret)
 549                 return ret;
 550
 551         i915_perf_init(dev_priv);
 552
 553         ret = i915_ggtt_probe_hw(dev_priv);
 554         if (ret)
 555                 goto err_perf;
 556
 557         ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, "inteldrmfb");
 558         if (ret)
 559                 goto err_ggtt;
 560
 561         ret = i915_ggtt_init_hw(dev_priv);
 562         if (ret)
 563                 goto err_ggtt;
 564
 565         ret = intel_memory_regions_hw_probe(dev_priv);
 566         if (ret)
 567                 goto err_ggtt;
 568
 569         intel_gt_init_hw_early(&dev_priv->gt, &dev_priv->ggtt);
 570
 571         ret = intel_gt_probe_lmem(&dev_priv->gt);
 572         if (ret)
 573                 goto err_mem_regions;
 574
 575         ret = i915_ggtt_enable_hw(dev_priv);
 576         if (ret) {
 577                 drm_err(&dev_priv->drm, "failed to enable GGTT\n");
 578                 goto err_mem_regions;
 579         }
 580
 581         pci_set_master(pdev);
 582
 583         intel_gt_init_workarounds(dev_priv);
 584
 585         /* On the 945G/GM, the chipset reports the MSI capability on the
 586          * integrated graphics even though the support isn't actually there
 587          * according to the published specs.  It doesn't appear to function
 588          * correctly in testing on 945G.
 589          * This may be a side effect of MSI having been made available for PEG
 590          * and the registers being closely associated.
 591          *
 592          * According to chipset errata, on the 965GM, MSI interrupts may
 593          * be lost or delayed, and was defeatured. MSI interrupts seem to
 594          * get lost on g4x as well, and interrupt delivery seems to stay
 595          * properly dead afterwards. So we'll just disable them for all
 596          * pre-gen5 chipsets.
 597          *
 598          * dp aux and gmbus irq on gen4 seems to be able to generate legacy
 599          * interrupts even when in MSI mode. This results in spurious
 600          * interrupt warnings if the legacy irq no. is shared with another
 601          * device. The kernel then disables that interrupt source and so
 602          * prevents the other device from working properly.
 603          */
 604         if (INTEL_GEN(dev_priv) >= 5) {
 605                 if (pci_enable_msi(pdev) < 0)
 606                         drm_dbg(&dev_priv->drm, "can't enable MSI");
 607         }
 608
 609         ret = intel_gvt_init(dev_priv);
 610         if (ret)
 611                 goto err_msi;
 612
 613         intel_opregion_setup(dev_priv);
 614
 615         intel_pcode_init(dev_priv);
 616
 617         /*
 618          * Fill the dram structure to get the system dram info. This will be
 619          * used for memory latency calculation.
 620          */
 621         intel_dram_detect(dev_priv);
 622
 623         intel_bw_init_hw(dev_priv);
 624
 625         return 0;
 626
 627 err_msi:
 628         if (pdev->msi_enabled)
 629                 pci_disable_msi(pdev);
 630 err_mem_regions:
 631         intel_memory_regions_driver_release(dev_priv);
 632 err_ggtt:
 633         i915_ggtt_driver_release(dev_priv);
 634 err_perf:
 635         i915_perf_fini(dev_priv);
 636         return ret;
 637 }
 638
 639 /**
 640  * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
 641  * @dev_priv: device private
 642  */
 643 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
 644 {
 645         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 646
 647         i915_perf_fini(dev_priv);
 648
 649         if (pdev->msi_enabled)
 650                 pci_disable_msi(pdev);
 651 }
 652
 653 /**
 654  * i915_driver_register - register the driver with the rest of the system
 655  * @dev_priv: device private
 656  *
 657  * Perform any steps necessary to make the driver available via kernel
 658  * internal or userspace interfaces.
 659  */
 660 static void i915_driver_register(struct drm_i915_private *dev_priv)
 661 {
 662         struct drm_device *dev = &dev_priv->drm;
 663
 664         i915_gem_driver_register(dev_priv);
 665         i915_pmu_register(dev_priv);
 666
 667         intel_vgpu_register(dev_priv);
 668
 669         /* Reveal our presence to userspace */
 670         if (drm_dev_register(dev, 0)) {
 671                 drm_err(&dev_priv->drm,
 672                         "Failed to register driver for userspace access!\n");
 673                 return;
 674         }
 675
 676         i915_debugfs_register(dev_priv);
 677         i915_setup_sysfs(dev_priv);
 678
 679         /* Depends on sysfs having been initialized */
 680         i915_perf_register(dev_priv);
 681
 682         intel_gt_driver_register(&dev_priv->gt);
 683
 684         intel_display_driver_register(dev_priv);
 685
 686         intel_power_domains_enable(dev_priv);
 687         intel_runtime_pm_enable(&dev_priv->runtime_pm);
 688
 689         intel_register_dsm_handler();
 690
 691         if (i915_switcheroo_register(dev_priv))
 692                 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n");
 693 }
 694
 695 /**
 696  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
 697  * @dev_priv: device private
 698  */
 699 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
 700 {
 701         i915_switcheroo_unregister(dev_priv);
 702
 703         intel_unregister_dsm_handler();
 704
 705         intel_runtime_pm_disable(&dev_priv->runtime_pm);
 706         intel_power_domains_disable(dev_priv);
 707
 708         intel_display_driver_unregister(dev_priv);
 709
 710         intel_gt_driver_unregister(&dev_priv->gt);
 711
 712         i915_perf_unregister(dev_priv);
 713         i915_pmu_unregister(dev_priv);
 714
 715         i915_teardown_sysfs(dev_priv);
 716         drm_dev_unplug(&dev_priv->drm);
 717
 718         i915_gem_driver_unregister(dev_priv);
 719 }
 720
 721 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
 722 {
 723         if (drm_debug_enabled(DRM_UT_DRIVER)) {
 724                 struct drm_printer p = drm_debug_printer("i915 device info:");
 725
 726                 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
 727                            INTEL_DEVID(dev_priv),
 728                            INTEL_REVID(dev_priv),
 729                            intel_platform_name(INTEL_INFO(dev_priv)->platform),
 730                            intel_subplatform(RUNTIME_INFO(dev_priv),
 731                                              INTEL_INFO(dev_priv)->platform),
 732                            INTEL_GEN(dev_priv));
 733
 734                 intel_device_info_print_static(INTEL_INFO(dev_priv), &p);
 735                 intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p);
 736                 intel_gt_info_print(&dev_priv->gt.info, &p);
 737         }
 738
 739         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
 740                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n");
 741         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
 742                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n");
 743         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
 744                 drm_info(&dev_priv->drm,
 745                          "DRM_I915_DEBUG_RUNTIME_PM enabled\n");
 746 }
 747
 748 static struct drm_i915_private *
 749 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
 750 {
 751         const struct intel_device_info *match_info =
 752                 (struct intel_device_info *)ent->driver_data;
 753         struct intel_device_info *device_info;
 754         struct drm_i915_private *i915;
 755
 756         i915 = devm_drm_dev_alloc(&pdev->dev, &driver,
 757                                   struct drm_i915_private, drm);
 758         if (IS_ERR(i915))
 759                 return i915;
 760
 761         pci_set_drvdata(pdev, i915);
 762
 763         /* Device parameters start as a copy of module parameters. */
 764         i915_params_copy(&i915->params, &i915_modparams);
 765
 766         /* Setup the write-once "constant" device info */
 767         device_info = mkwrite_device_info(i915);
 768         memcpy(device_info, match_info, sizeof(*device_info));
 769         RUNTIME_INFO(i915)->device_id = pdev->device;
 770
 771         return i915;
 772 }
 773
 774 /**
 775  * i915_driver_probe - setup chip and create an initial config
 776  * @pdev: PCI device
 777  * @ent: matching PCI ID entry
 778  *
 779  * The driver probe routine has to do several things:
 780  *   - drive output discovery via intel_modeset_init()
 781  *   - initialize the memory manager
 782  *   - allocate initial config memory
 783  *   - setup the DRM framebuffer with the allocated memory
 784  */
 785 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 786 {
 787         const struct intel_device_info *match_info =
 788                 (struct intel_device_info *)ent->driver_data;
 789         struct drm_i915_private *i915;
 790         int ret;
 791
 792         i915 = i915_driver_create(pdev, ent);
 793         if (IS_ERR(i915))
 794                 return PTR_ERR(i915);
 795
 796         /* Disable nuclear pageflip by default on pre-ILK */
 797         if (!i915->params.nuclear_pageflip && match_info->graphics_ver < 5)
 798                 i915->drm.driver_features &= ~DRIVER_ATOMIC;
 799
 800         /*
 801          * Check if we support fake LMEM -- for now we only unleash this for
 802          * the live selftests(test-and-exit).
 803          */
 804 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 805         if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)) {
 806                 if (INTEL_GEN(i915) >= 9 && i915_selftest.live < 0 &&
 807                     i915->params.fake_lmem_start) {
 808                         mkwrite_device_info(i915)->memory_regions =
 809                                 REGION_SMEM | REGION_LMEM | REGION_STOLEN_SMEM;
 810                         GEM_BUG_ON(!HAS_LMEM(i915));
 811                 }
 812         }
 813 #endif
 814
 815         ret = pci_enable_device(pdev);
 816         if (ret)
 817                 goto out_fini;
 818
 819         ret = i915_driver_early_probe(i915);
 820         if (ret < 0)
 821                 goto out_pci_disable;
 822
 823         disable_rpm_wakeref_asserts(&i915->runtime_pm);
 824
 825         intel_vgpu_detect(i915);
 826
 827         ret = i915_driver_mmio_probe(i915);
 828         if (ret < 0)
 829                 goto out_runtime_pm_put;
 830
 831         ret = i915_driver_hw_probe(i915);
 832         if (ret < 0)
 833                 goto out_cleanup_mmio;
 834
 835         ret = intel_modeset_init_noirq(i915);
 836         if (ret < 0)
 837                 goto out_cleanup_hw;
 838
 839         ret = intel_irq_install(i915);
 840         if (ret)
 841                 goto out_cleanup_modeset;
 842
 843         ret = intel_modeset_init_nogem(i915);
 844         if (ret)
 845                 goto out_cleanup_irq;
 846
 847         ret = i915_gem_init(i915);
 848         if (ret)
 849                 goto out_cleanup_modeset2;
 850
 851         ret = intel_modeset_init(i915);
 852         if (ret)
 853                 goto out_cleanup_gem;
 854
 855         i915_driver_register(i915);
 856
 857         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 858
 859         i915_welcome_messages(i915);
 860
 861         i915->do_release = true;
 862
 863         return 0;
 864
 865 out_cleanup_gem:
 866         i915_gem_suspend(i915);
 867         i915_gem_driver_remove(i915);
 868         i915_gem_driver_release(i915);
 869 out_cleanup_modeset2:
 870         /* FIXME clean up the error path */
 871         intel_modeset_driver_remove(i915);
 872         intel_irq_uninstall(i915);
 873         intel_modeset_driver_remove_noirq(i915);
 874         goto out_cleanup_modeset;
 875 out_cleanup_irq:
 876         intel_irq_uninstall(i915);
 877 out_cleanup_modeset:
 878         intel_modeset_driver_remove_nogem(i915);
 879 out_cleanup_hw:
 880         i915_driver_hw_remove(i915);
 881         intel_memory_regions_driver_release(i915);
 882         i915_ggtt_driver_release(i915);
 883 out_cleanup_mmio:
 884         i915_driver_mmio_release(i915);
 885 out_runtime_pm_put:
 886         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 887         i915_driver_late_release(i915);
 888 out_pci_disable:
 889         pci_disable_device(pdev);
 890 out_fini:
 891         i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
 892         return ret;
 893 }
 894
 895 void i915_driver_remove(struct drm_i915_private *i915)
 896 {
 897         disable_rpm_wakeref_asserts(&i915->runtime_pm);
 898
 899         i915_driver_unregister(i915);
 900
 901         /* Flush any external code that still may be under the RCU lock */
 902         synchronize_rcu();
 903
 904         i915_gem_suspend(i915);
 905
 906         intel_gvt_driver_remove(i915);
 907
 908         intel_modeset_driver_remove(i915);
 909
 910         intel_irq_uninstall(i915);
 911
 912         intel_modeset_driver_remove_noirq(i915);
 913
 914         i915_reset_error_state(i915);
 915         i915_gem_driver_remove(i915);
 916
 917         intel_modeset_driver_remove_nogem(i915);
 918
 919         i915_driver_hw_remove(i915);
 920
 921         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 922 }
 923
 924 static void i915_driver_release(struct drm_device *dev)
 925 {
 926         struct drm_i915_private *dev_priv = to_i915(dev);
 927         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
 928
 929         if (!dev_priv->do_release)
 930                 return;
 931
 932         disable_rpm_wakeref_asserts(rpm);
 933
 934         i915_gem_driver_release(dev_priv);
 935
 936         intel_memory_regions_driver_release(dev_priv);
 937         i915_ggtt_driver_release(dev_priv);
 938         i915_gem_drain_freed_objects(dev_priv);
 939
 940         i915_driver_mmio_release(dev_priv);
 941
 942         enable_rpm_wakeref_asserts(rpm);
 943         intel_runtime_pm_driver_release(rpm);
 944
 945         i915_driver_late_release(dev_priv);
 946 }
 947
 948 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
 949 {
 950         struct drm_i915_private *i915 = to_i915(dev);
 951         int ret;
 952
 953         ret = i915_gem_open(i915, file);
 954         if (ret)
 955                 return ret;
 956
 957         return 0;
 958 }
 959
 960 /**
 961  * i915_driver_lastclose - clean up after all DRM clients have exited
 962  * @dev: DRM device
 963  *
 964  * Take care of cleaning up after all DRM clients have exited.  In the
 965  * mode setting case, we want to restore the kernel's initial mode (just
 966  * in case the last client left us in a bad state).
 967  *
 968  * Additionally, in the non-mode setting case, we'll tear down the GTT
 969  * and DMA structures, since the kernel won't be using them, and clea
 970  * up any GEM state.
 971  */
 972 static void i915_driver_lastclose(struct drm_device *dev)
 973 {
 974         struct drm_i915_private *i915 = to_i915(dev);
 975
 976         intel_fbdev_restore_mode(dev);
 977
 978         if (HAS_DISPLAY(i915))
 979                 vga_switcheroo_process_delayed_switch();
 980 }
 981
 982 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
 983 {
 984         struct drm_i915_file_private *file_priv = file->driver_priv;
 985
 986         i915_gem_context_close(file);
 987
 988         kfree_rcu(file_priv, rcu);
 989
 990         /* Catch up with all the deferred frees from "this" client */
 991         i915_gem_flush_free_objects(to_i915(dev));
 992 }
 993
 994 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
 995 {
 996         struct drm_device *dev = &dev_priv->drm;
 997         struct intel_encoder *encoder;
 998
 999         if (!HAS_DISPLAY(dev_priv))
1000                 return;
1001
1002         drm_modeset_lock_all(dev);
1003         for_each_intel_encoder(dev, encoder)
1004                 if (encoder->suspend)
1005                         encoder->suspend(encoder);
1006         drm_modeset_unlock_all(dev);
1007 }
1008
1009 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv)
1010 {
1011         struct drm_device *dev = &dev_priv->drm;
1012         struct intel_encoder *encoder;
1013
1014         if (!HAS_DISPLAY(dev_priv))
1015                 return;
1016
1017         drm_modeset_lock_all(dev);
1018         for_each_intel_encoder(dev, encoder)
1019                 if (encoder->shutdown)
1020                         encoder->shutdown(encoder);
1021         drm_modeset_unlock_all(dev);
1022 }
1023
1024 void i915_driver_shutdown(struct drm_i915_private *i915)
1025 {
1026         disable_rpm_wakeref_asserts(&i915->runtime_pm);
1027         intel_runtime_pm_disable(&i915->runtime_pm);
1028         intel_power_domains_disable(i915);
1029
1030         i915_gem_suspend(i915);
1031
1032         if (HAS_DISPLAY(i915)) {
1033                 drm_kms_helper_poll_disable(&i915->drm);
1034
1035                 drm_atomic_helper_shutdown(&i915->drm);
1036         }
1037
1038         intel_dp_mst_suspend(i915);
1039
1040         intel_runtime_pm_disable_interrupts(i915);
1041         intel_hpd_cancel_work(i915);
1042
1043         intel_suspend_encoders(i915);
1044         intel_shutdown_encoders(i915);
1045
1046         intel_csr_ucode_suspend(i915);
1047
1048         /*
1049          * The only requirement is to reboot with display DC states disabled,
1050          * for now leaving all display power wells in the INIT power domain
1051          * enabled.
1052          *
1053          * TODO:
1054          * - unify the pci_driver::shutdown sequence here with the
1055          *   pci_driver.driver.pm.poweroff,poweroff_late sequence.
1056          * - unify the driver remove and system/runtime suspend sequences with
1057          *   the above unified shutdown/poweroff sequence.
1058          */
1059         intel_power_domains_driver_remove(i915);
1060         enable_rpm_wakeref_asserts(&i915->runtime_pm);
1061
1062         intel_runtime_pm_driver_release(&i915->runtime_pm);
1063 }
1064
1065 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1066 {
1067 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1068         if (acpi_target_system_state() < ACPI_STATE_S3)
1069                 return true;
1070 #endif
1071         return false;
1072 }
1073
1074 static int i915_drm_prepare(struct drm_device *dev)
1075 {
1076         struct drm_i915_private *i915 = to_i915(dev);
1077
1078         /*
1079          * NB intel_display_suspend() may issue new requests after we've
1080          * ostensibly marked the GPU as ready-to-sleep here. We need to
1081          * split out that work and pull it forward so that after point,
1082          * the GPU is not woken again.
1083          */
1084         i915_gem_suspend(i915);
1085
1086         return 0;
1087 }
1088
1089 static int i915_drm_suspend(struct drm_device *dev)
1090 {
1091         struct drm_i915_private *dev_priv = to_i915(dev);
1092         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1093         pci_power_t opregion_target_state;
1094
1095         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1096
1097         /* We do a lot of poking in a lot of registers, make sure they work
1098          * properly. */
1099         intel_power_domains_disable(dev_priv);
1100         if (HAS_DISPLAY(dev_priv))
1101                 drm_kms_helper_poll_disable(dev);
1102
1103         pci_save_state(pdev);
1104
1105         intel_display_suspend(dev);
1106
1107         intel_dp_mst_suspend(dev_priv);
1108
1109         intel_runtime_pm_disable_interrupts(dev_priv);
1110         intel_hpd_cancel_work(dev_priv);
1111
1112         intel_suspend_encoders(dev_priv);
1113
1114         intel_suspend_hw(dev_priv);
1115
1116         i915_ggtt_suspend(&dev_priv->ggtt);
1117
1118         i915_save_display(dev_priv);
1119
1120         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1121         intel_opregion_suspend(dev_priv, opregion_target_state);
1122
1123         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1124
1125         dev_priv->suspend_count++;
1126
1127         intel_csr_ucode_suspend(dev_priv);
1128
1129         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1130
1131         return 0;
1132 }
1133
1134 static enum i915_drm_suspend_mode
1135 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1136 {
1137         if (hibernate)
1138                 return I915_DRM_SUSPEND_HIBERNATE;
1139
1140         if (suspend_to_idle(dev_priv))
1141                 return I915_DRM_SUSPEND_IDLE;
1142
1143         return I915_DRM_SUSPEND_MEM;
1144 }
1145
1146 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1147 {
1148         struct drm_i915_private *dev_priv = to_i915(dev);
1149         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1150         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1151         int ret;
1152
1153         disable_rpm_wakeref_asserts(rpm);
1154
1155         i915_gem_suspend_late(dev_priv);
1156
1157         intel_uncore_suspend(&dev_priv->uncore);
1158
1159         intel_power_domains_suspend(dev_priv,
1160                                     get_suspend_mode(dev_priv, hibernation));
1161
1162         intel_display_power_suspend_late(dev_priv);
1163
1164         ret = vlv_suspend_complete(dev_priv);
1165         if (ret) {
1166                 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);
1167                 intel_power_domains_resume(dev_priv);
1168
1169                 goto out;
1170         }
1171
1172         pci_disable_device(pdev);
1173         /*
1174          * During hibernation on some platforms the BIOS may try to access
1175          * the device even though it's already in D3 and hang the machine. So
1176          * leave the device in D0 on those platforms and hope the BIOS will
1177          * power down the device properly. The issue was seen on multiple old
1178          * GENs with different BIOS vendors, so having an explicit blacklist
1179          * is inpractical; apply the workaround on everything pre GEN6. The
1180          * platforms where the issue was seen:
1181          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1182          * Fujitsu FSC S7110
1183          * Acer Aspire 1830T
1184          */
1185         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1186                 pci_set_power_state(pdev, PCI_D3hot);
1187
1188 out:
1189         enable_rpm_wakeref_asserts(rpm);
1190         if (!dev_priv->uncore.user_forcewake_count)
1191                 intel_runtime_pm_driver_release(rpm);
1192
1193         return ret;
1194 }
1195
1196 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state)
1197 {
1198         int error;
1199
1200         if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&
1201                              state.event != PM_EVENT_FREEZE))
1202                 return -EINVAL;
1203
1204         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1205                 return 0;
1206
1207         error = i915_drm_suspend(&i915->drm);
1208         if (error)
1209                 return error;
1210
1211         return i915_drm_suspend_late(&i915->drm, false);
1212 }
1213
1214 static int i915_drm_resume(struct drm_device *dev)
1215 {
1216         struct drm_i915_private *dev_priv = to_i915(dev);
1217         int ret;
1218
1219         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1220
1221         sanitize_gpu(dev_priv);
1222
1223         ret = i915_ggtt_enable_hw(dev_priv);
1224         if (ret)
1225                 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
1226
1227         i915_ggtt_resume(&dev_priv->ggtt);
1228
1229         intel_csr_ucode_resume(dev_priv);
1230
1231         i915_restore_display(dev_priv);
1232         intel_pps_unlock_regs_wa(dev_priv);
1233
1234         intel_init_pch_refclk(dev_priv);
1235
1236         /*
1237          * Interrupts have to be enabled before any batches are run. If not the
1238          * GPU will hang. i915_gem_init_hw() will initiate batches to
1239          * update/restore the context.
1240          *
1241          * drm_mode_config_reset() needs AUX interrupts.
1242          *
1243          * Modeset enabling in intel_modeset_init_hw() also needs working
1244          * interrupts.
1245          */
1246         intel_runtime_pm_enable_interrupts(dev_priv);
1247
1248         if (HAS_DISPLAY(dev_priv))
1249                 drm_mode_config_reset(dev);
1250
1251         i915_gem_resume(dev_priv);
1252
1253         intel_modeset_init_hw(dev_priv);
1254         intel_init_clock_gating(dev_priv);
1255         intel_hpd_init(dev_priv);
1256
1257         /* MST sideband requires HPD interrupts enabled */
1258         intel_dp_mst_resume(dev_priv);
1259         intel_display_resume(dev);
1260
1261         intel_hpd_poll_disable(dev_priv);
1262         if (HAS_DISPLAY(dev_priv))
1263                 drm_kms_helper_poll_enable(dev);
1264
1265         intel_opregion_resume(dev_priv);
1266
1267         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1268
1269         intel_power_domains_enable(dev_priv);
1270
1271         intel_gvt_resume(dev_priv);
1272
1273         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1274
1275         return 0;
1276 }
1277
1278 static int i915_drm_resume_early(struct drm_device *dev)
1279 {
1280         struct drm_i915_private *dev_priv = to_i915(dev);
1281         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1282         int ret;
1283
1284         /*
1285          * We have a resume ordering issue with the snd-hda driver also
1286          * requiring our device to be power up. Due to the lack of a
1287          * parent/child relationship we currently solve this with an early
1288          * resume hook.
1289          *
1290          * FIXME: This should be solved with a special hdmi sink device or
1291          * similar so that power domains can be employed.
1292          */
1293
1294         /*
1295          * Note that we need to set the power state explicitly, since we
1296          * powered off the device during freeze and the PCI core won't power
1297          * it back up for us during thaw. Powering off the device during
1298          * freeze is not a hard requirement though, and during the
1299          * suspend/resume phases the PCI core makes sure we get here with the
1300          * device powered on. So in case we change our freeze logic and keep
1301          * the device powered we can also remove the following set power state
1302          * call.
1303          */
1304         ret = pci_set_power_state(pdev, PCI_D0);
1305         if (ret) {
1306                 drm_err(&dev_priv->drm,
1307                         "failed to set PCI D0 power state (%d)\n", ret);
1308                 return ret;
1309         }
1310
1311         /*
1312          * Note that pci_enable_device() first enables any parent bridge
1313          * device and only then sets the power state for this device. The
1314          * bridge enabling is a nop though, since bridge devices are resumed
1315          * first. The order of enabling power and enabling the device is
1316          * imposed by the PCI core as described above, so here we preserve the
1317          * same order for the freeze/thaw phases.
1318          *
1319          * TODO: eventually we should remove pci_disable_device() /
1320          * pci_enable_enable_device() from suspend/resume. Due to how they
1321          * depend on the device enable refcount we can't anyway depend on them
1322          * disabling/enabling the device.
1323          */
1324         if (pci_enable_device(pdev))
1325                 return -EIO;
1326
1327         pci_set_master(pdev);
1328
1329         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1330
1331         ret = vlv_resume_prepare(dev_priv, false);
1332         if (ret)
1333                 drm_err(&dev_priv->drm,
1334                         "Resume prepare failed: %d, continuing anyway\n", ret);
1335
1336         intel_uncore_resume_early(&dev_priv->uncore);
1337
1338         intel_gt_check_and_clear_faults(&dev_priv->gt);
1339
1340         intel_display_power_resume_early(dev_priv);
1341
1342         intel_power_domains_resume(dev_priv);
1343
1344         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1345
1346         return ret;
1347 }
1348
1349 int i915_resume_switcheroo(struct drm_i915_private *i915)
1350 {
1351         int ret;
1352
1353         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1354                 return 0;
1355
1356         ret = i915_drm_resume_early(&i915->drm);
1357         if (ret)
1358                 return ret;
1359
1360         return i915_drm_resume(&i915->drm);
1361 }
1362
1363 static int i915_pm_prepare(struct device *kdev)
1364 {
1365         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1366
1367         if (!i915) {
1368                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1369                 return -ENODEV;
1370         }
1371
1372         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1373                 return 0;
1374
1375         return i915_drm_prepare(&i915->drm);
1376 }
1377
1378 static int i915_pm_suspend(struct device *kdev)
1379 {
1380         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1381
1382         if (!i915) {
1383                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1384                 return -ENODEV;
1385         }
1386
1387         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1388                 return 0;
1389
1390         return i915_drm_suspend(&i915->drm);
1391 }
1392
1393 static int i915_pm_suspend_late(struct device *kdev)
1394 {
1395         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1396
1397         /*
1398          * We have a suspend ordering issue with the snd-hda driver also
1399          * requiring our device to be power up. Due to the lack of a
1400          * parent/child relationship we currently solve this with an late
1401          * suspend hook.
1402          *
1403          * FIXME: This should be solved with a special hdmi sink device or
1404          * similar so that power domains can be employed.
1405          */
1406         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1407                 return 0;
1408
1409         return i915_drm_suspend_late(&i915->drm, false);
1410 }
1411
1412 static int i915_pm_poweroff_late(struct device *kdev)
1413 {
1414         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1415
1416         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1417                 return 0;
1418
1419         return i915_drm_suspend_late(&i915->drm, true);
1420 }
1421
1422 static int i915_pm_resume_early(struct device *kdev)
1423 {
1424         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1425
1426         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1427                 return 0;
1428
1429         return i915_drm_resume_early(&i915->drm);
1430 }
1431
1432 static int i915_pm_resume(struct device *kdev)
1433 {
1434         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1435
1436         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1437                 return 0;
1438
1439         return i915_drm_resume(&i915->drm);
1440 }
1441
1442 /* freeze: before creating the hibernation_image */
1443 static int i915_pm_freeze(struct device *kdev)
1444 {
1445         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1446         int ret;
1447
1448         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1449                 ret = i915_drm_suspend(&i915->drm);
1450                 if (ret)
1451                         return ret;
1452         }
1453
1454         ret = i915_gem_freeze(i915);
1455         if (ret)
1456                 return ret;
1457
1458         return 0;
1459 }
1460
1461 static int i915_pm_freeze_late(struct device *kdev)
1462 {
1463         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1464         int ret;
1465
1466         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1467                 ret = i915_drm_suspend_late(&i915->drm, true);
1468                 if (ret)
1469                         return ret;
1470         }
1471
1472         ret = i915_gem_freeze_late(i915);
1473         if (ret)
1474                 return ret;
1475
1476         return 0;
1477 }
1478
1479 /* thaw: called after creating the hibernation image, but before turning off. */
1480 static int i915_pm_thaw_early(struct device *kdev)
1481 {
1482         return i915_pm_resume_early(kdev);
1483 }
1484
1485 static int i915_pm_thaw(struct device *kdev)
1486 {
1487         return i915_pm_resume(kdev);
1488 }
1489
1490 /* restore: called after loading the hibernation image. */
1491 static int i915_pm_restore_early(struct device *kdev)
1492 {
1493         return i915_pm_resume_early(kdev);
1494 }
1495
1496 static int i915_pm_restore(struct device *kdev)
1497 {
1498         return i915_pm_resume(kdev);
1499 }
1500
1501 static int intel_runtime_suspend(struct device *kdev)
1502 {
1503         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1504         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1505         int ret;
1506
1507         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1508                 return -ENODEV;
1509
1510         drm_dbg_kms(&dev_priv->drm, "Suspending device\n");
1511
1512         disable_rpm_wakeref_asserts(rpm);
1513
1514         /*
1515          * We are safe here against re-faults, since the fault handler takes
1516          * an RPM reference.
1517          */
1518         i915_gem_runtime_suspend(dev_priv);
1519
1520         intel_gt_runtime_suspend(&dev_priv->gt);
1521
1522         intel_runtime_pm_disable_interrupts(dev_priv);
1523
1524         intel_uncore_suspend(&dev_priv->uncore);
1525
1526         intel_display_power_suspend(dev_priv);
1527
1528         ret = vlv_suspend_complete(dev_priv);
1529         if (ret) {
1530                 drm_err(&dev_priv->drm,
1531                         "Runtime suspend failed, disabling it (%d)\n", ret);
1532                 intel_uncore_runtime_resume(&dev_priv->uncore);
1533
1534                 intel_runtime_pm_enable_interrupts(dev_priv);
1535
1536                 intel_gt_runtime_resume(&dev_priv->gt);
1537
1538                 enable_rpm_wakeref_asserts(rpm);
1539
1540                 return ret;
1541         }
1542
1543         enable_rpm_wakeref_asserts(rpm);
1544         intel_runtime_pm_driver_release(rpm);
1545
1546         if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
1547                 drm_err(&dev_priv->drm,
1548                         "Unclaimed access detected prior to suspending\n");
1549
1550         rpm->suspended = true;
1551
1552         /*
1553          * FIXME: We really should find a document that references the arguments
1554          * used below!
1555          */
1556         if (IS_BROADWELL(dev_priv)) {
1557                 /*
1558                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1559                  * being detected, and the call we do at intel_runtime_resume()
1560                  * won't be able to restore them. Since PCI_D3hot matches the
1561                  * actual specification and appears to be working, use it.
1562                  */
1563                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
1564         } else {
1565                 /*
1566                  * current versions of firmware which depend on this opregion
1567                  * notification have repurposed the D1 definition to mean
1568                  * "runtime suspended" vs. what you would normally expect (D3)
1569                  * to distinguish it from notifications that might be sent via
1570                  * the suspend path.
1571                  */
1572                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
1573         }
1574
1575         assert_forcewakes_inactive(&dev_priv->uncore);
1576
1577         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1578                 intel_hpd_poll_enable(dev_priv);
1579
1580         drm_dbg_kms(&dev_priv->drm, "Device suspended\n");
1581         return 0;
1582 }
1583
1584 static int intel_runtime_resume(struct device *kdev)
1585 {
1586         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1587         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1588         int ret;
1589
1590         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1591                 return -ENODEV;
1592
1593         drm_dbg_kms(&dev_priv->drm, "Resuming device\n");
1594
1595         drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
1596         disable_rpm_wakeref_asserts(rpm);
1597
1598         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1599         rpm->suspended = false;
1600         if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
1601                 drm_dbg(&dev_priv->drm,
1602                         "Unclaimed access during suspend, bios?\n");
1603
1604         intel_display_power_resume(dev_priv);
1605
1606         ret = vlv_resume_prepare(dev_priv, true);
1607
1608         intel_uncore_runtime_resume(&dev_priv->uncore);
1609
1610         intel_runtime_pm_enable_interrupts(dev_priv);
1611
1612         /*
1613          * No point of rolling back things in case of an error, as the best
1614          * we can do is to hope that things will still work (and disable RPM).
1615          */
1616         intel_gt_runtime_resume(&dev_priv->gt);
1617
1618         /*
1619          * On VLV/CHV display interrupts are part of the display
1620          * power well, so hpd is reinitialized from there. For
1621          * everyone else do it here.
1622          */
1623         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
1624                 intel_hpd_init(dev_priv);
1625                 intel_hpd_poll_disable(dev_priv);
1626         }
1627
1628         intel_enable_ipc(dev_priv);
1629
1630         enable_rpm_wakeref_asserts(rpm);
1631
1632         if (ret)
1633                 drm_err(&dev_priv->drm,
1634                         "Runtime resume failed, disabling it (%d)\n", ret);
1635         else
1636                 drm_dbg_kms(&dev_priv->drm, "Device resumed\n");
1637
1638         return ret;
1639 }
1640
1641 const struct dev_pm_ops i915_pm_ops = {
1642         /*
1643          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1644          * PMSG_RESUME]
1645          */
1646         .prepare = i915_pm_prepare,
1647         .suspend = i915_pm_suspend,
1648         .suspend_late = i915_pm_suspend_late,
1649         .resume_early = i915_pm_resume_early,
1650         .resume = i915_pm_resume,
1651
1652         /*
1653          * S4 event handlers
1654          * @freeze, @freeze_late    : called (1) before creating the
1655          *                            hibernation image [PMSG_FREEZE] and
1656          *                            (2) after rebooting, before restoring
1657          *                            the image [PMSG_QUIESCE]
1658          * @thaw, @thaw_early       : called (1) after creating the hibernation
1659          *                            image, before writing it [PMSG_THAW]
1660          *                            and (2) after failing to create or
1661          *                            restore the image [PMSG_RECOVER]
1662          * @poweroff, @poweroff_late: called after writing the hibernation
1663          *                            image, before rebooting [PMSG_HIBERNATE]
1664          * @restore, @restore_early : called after rebooting and restoring the
1665          *                            hibernation image [PMSG_RESTORE]
1666          */
1667         .freeze = i915_pm_freeze,
1668         .freeze_late = i915_pm_freeze_late,
1669         .thaw_early = i915_pm_thaw_early,
1670         .thaw = i915_pm_thaw,
1671         .poweroff = i915_pm_suspend,
1672         .poweroff_late = i915_pm_poweroff_late,
1673         .restore_early = i915_pm_restore_early,
1674         .restore = i915_pm_restore,
1675
1676         /* S0ix (via runtime suspend) event handlers */
1677         .runtime_suspend = intel_runtime_suspend,
1678         .runtime_resume = intel_runtime_resume,
1679 };
1680
1681 static const struct file_operations i915_driver_fops = {
1682         .owner = THIS_MODULE,
1683         .open = drm_open,
1684         .release = drm_release_noglobal,
1685         .unlocked_ioctl = drm_ioctl,
1686         .mmap = i915_gem_mmap,
1687         .poll = drm_poll,
1688         .read = drm_read,
1689         .compat_ioctl = i915_ioc32_compat_ioctl,
1690         .llseek = noop_llseek,
1691 };
1692
1693 static int
1694 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1695                           struct drm_file *file)
1696 {
1697         return -ENODEV;
1698 }
1699
1700 static const struct drm_ioctl_desc i915_ioctls[] = {
1701         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1702         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1703         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1704         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1705         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1706         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1707         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
1708         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1709         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1710         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1711         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1712         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1713         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1714         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1715         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
1716         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1717         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1718         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1719         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH),
1720         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
1721         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1722         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1723         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
1724         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1725         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1726         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
1727         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1728         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1729         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1730         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1731         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1732         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1733         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
1734         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1735         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1736         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
1737         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
1738         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1739         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
1740         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1741         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
1742         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
1743         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
1744         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
1745         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
1746         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1747         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1748         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1749         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
1750         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1751         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1752         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1753         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
1754         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
1755         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
1756         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
1757         DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
1758         DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
1759 };
1760
1761 static const struct drm_driver driver = {
1762         /* Don't use MTRRs here; the Xserver or userspace app should
1763          * deal with them for Intel hardware.
1764          */
1765         .driver_features =
1766             DRIVER_GEM |
1767             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ |
1768             DRIVER_SYNCOBJ_TIMELINE,
1769         .release = i915_driver_release,
1770         .open = i915_driver_open,
1771         .lastclose = i915_driver_lastclose,
1772         .postclose = i915_driver_postclose,
1773
1774         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1775         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1776         .gem_prime_import = i915_gem_prime_import,
1777
1778         .dumb_create = i915_gem_dumb_create,
1779         .dumb_map_offset = i915_gem_dumb_mmap_offset,
1780
1781         .ioctls = i915_ioctls,
1782         .num_ioctls = ARRAY_SIZE(i915_ioctls),
1783         .fops = &i915_driver_fops,
1784         .name = DRIVER_NAME,
1785         .desc = DRIVER_DESC,
1786         .date = DRIVER_DATE,
1787         .major = DRIVER_MAJOR,
1788         .minor = DRIVER_MINOR,
1789         .patchlevel = DRIVER_PATCHLEVEL,
1790 };