drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vga_switcheroo.h>
  40 #include <linux/vt.h>
  41 #include <acpi/video.h>
  42
  43 #include <drm/drm_atomic_helper.h>
  44 #include <drm/drm_ioctl.h>
  45 #include <drm/drm_irq.h>
  46 #include <drm/drm_managed.h>
  47 #include <drm/drm_probe_helper.h>
  48
  49 #include "display/intel_acpi.h"
  50 #include "display/intel_audio.h"
  51 #include "display/intel_bw.h"
  52 #include "display/intel_cdclk.h"
  53 #include "display/intel_csr.h"
  54 #include "display/intel_display_debugfs.h"
  55 #include "display/intel_display_types.h"
  56 #include "display/intel_dp.h"
  57 #include "display/intel_fbdev.h"
  58 #include "display/intel_hotplug.h"
  59 #include "display/intel_overlay.h"
  60 #include "display/intel_pipe_crc.h"
  61 #include "display/intel_sprite.h"
  62 #include "display/intel_vga.h"
  63
  64 #include "gem/i915_gem_context.h"
  65 #include "gem/i915_gem_ioctls.h"
  66 #include "gem/i915_gem_mman.h"
  67 #include "gt/intel_gt.h"
  68 #include "gt/intel_gt_pm.h"
  69 #include "gt/intel_rc6.h"
  70
  71 #include "i915_debugfs.h"
  72 #include "i915_drv.h"
  73 #include "i915_ioc32.h"
  74 #include "i915_irq.h"
  75 #include "i915_memcpy.h"
  76 #include "i915_perf.h"
  77 #include "i915_query.h"
  78 #include "i915_suspend.h"
  79 #include "i915_switcheroo.h"
  80 #include "i915_sysfs.h"
  81 #include "i915_trace.h"
  82 #include "i915_vgpu.h"
  83 #include "intel_dram.h"
  84 #include "intel_gvt.h"
  85 #include "intel_memory_region.h"
  86 #include "intel_pm.h"
  87 #include "vlv_suspend.h"
  88
  89 static struct drm_driver driver;
  90
  91 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
  92 {
  93         int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
  94
  95         dev_priv->bridge_dev =
  96                 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
  97         if (!dev_priv->bridge_dev) {
  98                 drm_err(&dev_priv->drm, "bridge device not found\n");
  99                 return -1;
 100         }
 101         return 0;
 102 }
 103
 104 /* Allocate space for the MCH regs if needed, return nonzero on error */
 105 static int
 106 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 107 {
 108         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 109         u32 temp_lo, temp_hi = 0;
 110         u64 mchbar_addr;
 111         int ret;
 112
 113         if (INTEL_GEN(dev_priv) >= 4)
 114                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 115         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 116         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 117
 118         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 119 #ifdef CONFIG_PNP
 120         if (mchbar_addr &&
 121             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 122                 return 0;
 123 #endif
 124
 125         /* Get some space for it */
 126         dev_priv->mch_res.name = "i915 MCHBAR";
 127         dev_priv->mch_res.flags = IORESOURCE_MEM;
 128         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 129                                      &dev_priv->mch_res,
 130                                      MCHBAR_SIZE, MCHBAR_SIZE,
 131                                      PCIBIOS_MIN_MEM,
 132                                      0, pcibios_align_resource,
 133                                      dev_priv->bridge_dev);
 134         if (ret) {
 135                 drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret);
 136                 dev_priv->mch_res.start = 0;
 137                 return ret;
 138         }
 139
 140         if (INTEL_GEN(dev_priv) >= 4)
 141                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 142                                        upper_32_bits(dev_priv->mch_res.start));
 143
 144         pci_write_config_dword(dev_priv->bridge_dev, reg,
 145                                lower_32_bits(dev_priv->mch_res.start));
 146         return 0;
 147 }
 148
 149 /* Setup MCHBAR if possible, return true if we should disable it again */
 150 static void
 151 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 152 {
 153         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 154         u32 temp;
 155         bool enabled;
 156
 157         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 158                 return;
 159
 160         dev_priv->mchbar_need_disable = false;
 161
 162         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 163                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 164                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 165         } else {
 166                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 167                 enabled = temp & 1;
 168         }
 169
 170         /* If it's already enabled, don't have to do anything */
 171         if (enabled)
 172                 return;
 173
 174         if (intel_alloc_mchbar_resource(dev_priv))
 175                 return;
 176
 177         dev_priv->mchbar_need_disable = true;
 178
 179         /* Space is allocated or reserved, so enable it. */
 180         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 181                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 182                                        temp | DEVEN_MCHBAR_EN);
 183         } else {
 184                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 185                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 186         }
 187 }
 188
 189 static void
 190 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 191 {
 192         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 193
 194         if (dev_priv->mchbar_need_disable) {
 195                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 196                         u32 deven_val;
 197
 198                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 199                                               &deven_val);
 200                         deven_val &= ~DEVEN_MCHBAR_EN;
 201                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 202                                                deven_val);
 203                 } else {
 204                         u32 mchbar_val;
 205
 206                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 207                                               &mchbar_val);
 208                         mchbar_val &= ~1;
 209                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 210                                                mchbar_val);
 211                 }
 212         }
 213
 214         if (dev_priv->mch_res.start)
 215                 release_resource(&dev_priv->mch_res);
 216 }
 217
 218 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 219 {
 220         /*
 221          * The i915 workqueue is primarily used for batched retirement of
 222          * requests (and thus managing bo) once the task has been completed
 223          * by the GPU. i915_retire_requests() is called directly when we
 224          * need high-priority retirement, such as waiting for an explicit
 225          * bo.
 226          *
 227          * It is also used for periodic low-priority events, such as
 228          * idle-timers and recording error state.
 229          *
 230          * All tasks on the workqueue are expected to acquire the dev mutex
 231          * so there is no point in running more than one instance of the
 232          * workqueue at any time.  Use an ordered one.
 233          */
 234         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 235         if (dev_priv->wq == NULL)
 236                 goto out_err;
 237
 238         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 239         if (dev_priv->hotplug.dp_wq == NULL)
 240                 goto out_free_wq;
 241
 242         return 0;
 243
 244 out_free_wq:
 245         destroy_workqueue(dev_priv->wq);
 246 out_err:
 247         drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n");
 248
 249         return -ENOMEM;
 250 }
 251
 252 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 253 {
 254         destroy_workqueue(dev_priv->hotplug.dp_wq);
 255         destroy_workqueue(dev_priv->wq);
 256 }
 257
 258 /*
 259  * We don't keep the workarounds for pre-production hardware, so we expect our
 260  * driver to fail on these machines in one way or another. A little warning on
 261  * dmesg may help both the user and the bug triagers.
 262  *
 263  * Our policy for removing pre-production workarounds is to keep the
 264  * current gen workarounds as a guide to the bring-up of the next gen
 265  * (workarounds have a habit of persisting!). Anything older than that
 266  * should be removed along with the complications they introduce.
 267  */
 268 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 269 {
 270         bool pre = false;
 271
 272         pre |= IS_HSW_EARLY_SDV(dev_priv);
 273         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 274         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 275         pre |= IS_KBL_GT_REVID(dev_priv, 0, KBL_REVID_A0);
 276         pre |= IS_GLK_REVID(dev_priv, 0, GLK_REVID_A2);
 277
 278         if (pre) {
 279                 drm_err(&dev_priv->drm, "This is a pre-production stepping. "
 280                           "It may not be fully functional.\n");
 281                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 282         }
 283 }
 284
 285 static void sanitize_gpu(struct drm_i915_private *i915)
 286 {
 287         if (!INTEL_INFO(i915)->gpu_reset_clobbers_display)
 288                 __intel_gt_reset(&i915->gt, ALL_ENGINES);
 289 }
 290
 291 /**
 292  * i915_driver_early_probe - setup state not requiring device access
 293  * @dev_priv: device private
 294  *
 295  * Initialize everything that is a "SW-only" state, that is state not
 296  * requiring accessing the device or exposing the driver via kernel internal
 297  * or userspace interfaces. Example steps belonging here: lock initialization,
 298  * system memory allocation, setting up device specific attributes and
 299  * function hooks not requiring accessing the device.
 300  */
 301 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
 302 {
 303         int ret = 0;
 304
 305         if (i915_inject_probe_failure(dev_priv))
 306                 return -ENODEV;
 307
 308         intel_device_info_subplatform_init(dev_priv);
 309
 310         intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
 311         intel_uncore_init_early(&dev_priv->uncore, dev_priv);
 312
 313         spin_lock_init(&dev_priv->irq_lock);
 314         spin_lock_init(&dev_priv->gpu_error.lock);
 315         mutex_init(&dev_priv->backlight_lock);
 316
 317         mutex_init(&dev_priv->sb_lock);
 318         cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
 319
 320         mutex_init(&dev_priv->av_mutex);
 321         mutex_init(&dev_priv->wm.wm_mutex);
 322         mutex_init(&dev_priv->pps_mutex);
 323         mutex_init(&dev_priv->hdcp_comp_mutex);
 324
 325         i915_memcpy_init_early(dev_priv);
 326         intel_runtime_pm_init_early(&dev_priv->runtime_pm);
 327
 328         ret = i915_workqueues_init(dev_priv);
 329         if (ret < 0)
 330                 return ret;
 331
 332         ret = vlv_suspend_init(dev_priv);
 333         if (ret < 0)
 334                 goto err_workqueues;
 335
 336         intel_wopcm_init_early(&dev_priv->wopcm);
 337
 338         intel_gt_init_early(&dev_priv->gt, dev_priv);
 339
 340         i915_gem_init_early(dev_priv);
 341
 342         /* This must be called before any calls to HAS_PCH_* */
 343         intel_detect_pch(dev_priv);
 344
 345         intel_pm_setup(dev_priv);
 346         ret = intel_power_domains_init(dev_priv);
 347         if (ret < 0)
 348                 goto err_gem;
 349         intel_irq_init(dev_priv);
 350         intel_init_display_hooks(dev_priv);
 351         intel_init_clock_gating_hooks(dev_priv);
 352         intel_init_audio_hooks(dev_priv);
 353
 354         intel_detect_preproduction_hw(dev_priv);
 355
 356         return 0;
 357
 358 err_gem:
 359         i915_gem_cleanup_early(dev_priv);
 360         intel_gt_driver_late_release(&dev_priv->gt);
 361         vlv_suspend_cleanup(dev_priv);
 362 err_workqueues:
 363         i915_workqueues_cleanup(dev_priv);
 364         return ret;
 365 }
 366
 367 /**
 368  * i915_driver_late_release - cleanup the setup done in
 369  *                             i915_driver_early_probe()
 370  * @dev_priv: device private
 371  */
 372 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
 373 {
 374         intel_irq_fini(dev_priv);
 375         intel_power_domains_cleanup(dev_priv);
 376         i915_gem_cleanup_early(dev_priv);
 377         intel_gt_driver_late_release(&dev_priv->gt);
 378         vlv_suspend_cleanup(dev_priv);
 379         i915_workqueues_cleanup(dev_priv);
 380
 381         cpu_latency_qos_remove_request(&dev_priv->sb_qos);
 382         mutex_destroy(&dev_priv->sb_lock);
 383
 384         i915_params_free(&dev_priv->params);
 385 }
 386
 387 /**
 388  * i915_driver_mmio_probe - setup device MMIO
 389  * @dev_priv: device private
 390  *
 391  * Setup minimal device state necessary for MMIO accesses later in the
 392  * initialization sequence. The setup here should avoid any other device-wide
 393  * side effects or exposing the driver via kernel internal or user space
 394  * interfaces.
 395  */
 396 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
 397 {
 398         int ret;
 399
 400         if (i915_inject_probe_failure(dev_priv))
 401                 return -ENODEV;
 402
 403         if (i915_get_bridge_dev(dev_priv))
 404                 return -EIO;
 405
 406         ret = intel_uncore_init_mmio(&dev_priv->uncore);
 407         if (ret < 0)
 408                 goto err_bridge;
 409
 410         /* Try to make sure MCHBAR is enabled before poking at it */
 411         intel_setup_mchbar(dev_priv);
 412
 413         ret = intel_gt_init_mmio(&dev_priv->gt);
 414         if (ret)
 415                 goto err_uncore;
 416
 417         /* As early as possible, scrub existing GPU state before clobbering */
 418         sanitize_gpu(dev_priv);
 419
 420         return 0;
 421
 422 err_uncore:
 423         intel_teardown_mchbar(dev_priv);
 424         intel_uncore_fini_mmio(&dev_priv->uncore);
 425 err_bridge:
 426         pci_dev_put(dev_priv->bridge_dev);
 427
 428         return ret;
 429 }
 430
 431 /**
 432  * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
 433  * @dev_priv: device private
 434  */
 435 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
 436 {
 437         intel_teardown_mchbar(dev_priv);
 438         intel_uncore_fini_mmio(&dev_priv->uncore);
 439         pci_dev_put(dev_priv->bridge_dev);
 440 }
 441
 442 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 443 {
 444         intel_gvt_sanitize_options(dev_priv);
 445 }
 446
 447 /**
 448  * i915_set_dma_info - set all relevant PCI dma info as configured for the
 449  * platform
 450  * @i915: valid i915 instance
 451  *
 452  * Set the dma max segment size, device and coherent masks.  The dma mask set
 453  * needs to occur before i915_ggtt_probe_hw.
 454  *
 455  * A couple of platforms have special needs.  Address them as well.
 456  *
 457  */
 458 static int i915_set_dma_info(struct drm_i915_private *i915)
 459 {
 460         struct pci_dev *pdev = i915->drm.pdev;
 461         unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size;
 462         int ret;
 463
 464         GEM_BUG_ON(!mask_size);
 465
 466         /*
 467          * We don't have a max segment size, so set it to the max so sg's
 468          * debugging layer doesn't complain
 469          */
 470         dma_set_max_seg_size(&pdev->dev, UINT_MAX);
 471
 472         ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(mask_size));
 473         if (ret)
 474                 goto mask_err;
 475
 476         /* overlay on gen2 is broken and can't address above 1G */
 477         if (IS_GEN(i915, 2))
 478                 mask_size = 30;
 479
 480         /*
 481          * 965GM sometimes incorrectly writes to hardware status page (HWS)
 482          * using 32bit addressing, overwriting memory if HWS is located
 483          * above 4GB.
 484          *
 485          * The documentation also mentions an issue with undefined
 486          * behaviour if any general state is accessed within a page above 4GB,
 487          * which also needs to be handled carefully.
 488          */
 489         if (IS_I965G(i915) || IS_I965GM(i915))
 490                 mask_size = 32;
 491
 492         ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(mask_size));
 493         if (ret)
 494                 goto mask_err;
 495
 496         return 0;
 497
 498 mask_err:
 499         drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret);
 500         return ret;
 501 }
 502
 503 /**
 504  * i915_driver_hw_probe - setup state requiring device access
 505  * @dev_priv: device private
 506  *
 507  * Setup state that requires accessing the device, but doesn't require
 508  * exposing the driver via kernel internal or userspace interfaces.
 509  */
 510 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
 511 {
 512         struct pci_dev *pdev = dev_priv->drm.pdev;
 513         int ret;
 514
 515         if (i915_inject_probe_failure(dev_priv))
 516                 return -ENODEV;
 517
 518         intel_device_info_runtime_init(dev_priv);
 519
 520         if (HAS_PPGTT(dev_priv)) {
 521                 if (intel_vgpu_active(dev_priv) &&
 522                     !intel_vgpu_has_full_ppgtt(dev_priv)) {
 523                         i915_report_error(dev_priv,
 524                                           "incompatible vGPU found, support for isolated ppGTT required\n");
 525                         return -ENXIO;
 526                 }
 527         }
 528
 529         if (HAS_EXECLISTS(dev_priv)) {
 530                 /*
 531                  * Older GVT emulation depends upon intercepting CSB mmio,
 532                  * which we no longer use, preferring to use the HWSP cache
 533                  * instead.
 534                  */
 535                 if (intel_vgpu_active(dev_priv) &&
 536                     !intel_vgpu_has_hwsp_emulation(dev_priv)) {
 537                         i915_report_error(dev_priv,
 538                                           "old vGPU host found, support for HWSP emulation required\n");
 539                         return -ENXIO;
 540                 }
 541         }
 542
 543         intel_sanitize_options(dev_priv);
 544
 545         /* needs to be done before ggtt probe */
 546         intel_dram_edram_detect(dev_priv);
 547
 548         ret = i915_set_dma_info(dev_priv);
 549         if (ret)
 550                 return ret;
 551
 552         i915_perf_init(dev_priv);
 553
 554         ret = i915_ggtt_probe_hw(dev_priv);
 555         if (ret)
 556                 goto err_perf;
 557
 558         ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "inteldrmfb");
 559         if (ret)
 560                 goto err_ggtt;
 561
 562         ret = i915_ggtt_init_hw(dev_priv);
 563         if (ret)
 564                 goto err_ggtt;
 565
 566         ret = intel_memory_regions_hw_probe(dev_priv);
 567         if (ret)
 568                 goto err_ggtt;
 569
 570         intel_gt_init_hw_early(&dev_priv->gt, &dev_priv->ggtt);
 571
 572         ret = i915_ggtt_enable_hw(dev_priv);
 573         if (ret) {
 574                 drm_err(&dev_priv->drm, "failed to enable GGTT\n");
 575                 goto err_mem_regions;
 576         }
 577
 578         pci_set_master(pdev);
 579
 580         cpu_latency_qos_add_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 581
 582         intel_gt_init_workarounds(dev_priv);
 583
 584         /* On the 945G/GM, the chipset reports the MSI capability on the
 585          * integrated graphics even though the support isn't actually there
 586          * according to the published specs.  It doesn't appear to function
 587          * correctly in testing on 945G.
 588          * This may be a side effect of MSI having been made available for PEG
 589          * and the registers being closely associated.
 590          *
 591          * According to chipset errata, on the 965GM, MSI interrupts may
 592          * be lost or delayed, and was defeatured. MSI interrupts seem to
 593          * get lost on g4x as well, and interrupt delivery seems to stay
 594          * properly dead afterwards. So we'll just disable them for all
 595          * pre-gen5 chipsets.
 596          *
 597          * dp aux and gmbus irq on gen4 seems to be able to generate legacy
 598          * interrupts even when in MSI mode. This results in spurious
 599          * interrupt warnings if the legacy irq no. is shared with another
 600          * device. The kernel then disables that interrupt source and so
 601          * prevents the other device from working properly.
 602          */
 603         if (INTEL_GEN(dev_priv) >= 5) {
 604                 if (pci_enable_msi(pdev) < 0)
 605                         drm_dbg(&dev_priv->drm, "can't enable MSI");
 606         }
 607
 608         ret = intel_gvt_init(dev_priv);
 609         if (ret)
 610                 goto err_msi;
 611
 612         intel_opregion_setup(dev_priv);
 613         /*
 614          * Fill the dram structure to get the system raw bandwidth and
 615          * dram info. This will be used for memory latency calculation.
 616          */
 617         intel_dram_detect(dev_priv);
 618
 619         intel_bw_init_hw(dev_priv);
 620
 621         return 0;
 622
 623 err_msi:
 624         if (pdev->msi_enabled)
 625                 pci_disable_msi(pdev);
 626         cpu_latency_qos_remove_request(&dev_priv->pm_qos);
 627 err_mem_regions:
 628         intel_memory_regions_driver_release(dev_priv);
 629 err_ggtt:
 630         i915_ggtt_driver_release(dev_priv);
 631 err_perf:
 632         i915_perf_fini(dev_priv);
 633         return ret;
 634 }
 635
 636 /**
 637  * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
 638  * @dev_priv: device private
 639  */
 640 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
 641 {
 642         struct pci_dev *pdev = dev_priv->drm.pdev;
 643
 644         i915_perf_fini(dev_priv);
 645
 646         if (pdev->msi_enabled)
 647                 pci_disable_msi(pdev);
 648
 649         cpu_latency_qos_remove_request(&dev_priv->pm_qos);
 650 }
 651
 652 /**
 653  * i915_driver_register - register the driver with the rest of the system
 654  * @dev_priv: device private
 655  *
 656  * Perform any steps necessary to make the driver available via kernel
 657  * internal or userspace interfaces.
 658  */
 659 static void i915_driver_register(struct drm_i915_private *dev_priv)
 660 {
 661         struct drm_device *dev = &dev_priv->drm;
 662
 663         i915_gem_driver_register(dev_priv);
 664         i915_pmu_register(dev_priv);
 665
 666         intel_vgpu_register(dev_priv);
 667
 668         /* Reveal our presence to userspace */
 669         if (drm_dev_register(dev, 0) == 0) {
 670                 i915_debugfs_register(dev_priv);
 671                 intel_display_debugfs_register(dev_priv);
 672                 i915_setup_sysfs(dev_priv);
 673
 674                 /* Depends on sysfs having been initialized */
 675                 i915_perf_register(dev_priv);
 676         } else
 677                 drm_err(&dev_priv->drm,
 678                         "Failed to register driver for userspace access!\n");
 679
 680         if (HAS_DISPLAY(dev_priv) && INTEL_DISPLAY_ENABLED(dev_priv)) {
 681                 /* Must be done after probing outputs */
 682                 intel_opregion_register(dev_priv);
 683                 acpi_video_register();
 684         }
 685
 686         intel_gt_driver_register(&dev_priv->gt);
 687
 688         intel_audio_init(dev_priv);
 689
 690         /*
 691          * Some ports require correctly set-up hpd registers for detection to
 692          * work properly (leading to ghost connected connector status), e.g. VGA
 693          * on gm45.  Hence we can only set up the initial fbdev config after hpd
 694          * irqs are fully enabled. We do it last so that the async config
 695          * cannot run before the connectors are registered.
 696          */
 697         intel_fbdev_initial_config_async(dev);
 698
 699         /*
 700          * We need to coordinate the hotplugs with the asynchronous fbdev
 701          * configuration, for which we use the fbdev->async_cookie.
 702          */
 703         if (HAS_DISPLAY(dev_priv) && INTEL_DISPLAY_ENABLED(dev_priv))
 704                 drm_kms_helper_poll_init(dev);
 705
 706         intel_power_domains_enable(dev_priv);
 707         intel_runtime_pm_enable(&dev_priv->runtime_pm);
 708
 709         intel_register_dsm_handler();
 710
 711         if (i915_switcheroo_register(dev_priv))
 712                 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n");
 713 }
 714
 715 /**
 716  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
 717  * @dev_priv: device private
 718  */
 719 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
 720 {
 721         i915_switcheroo_unregister(dev_priv);
 722
 723         intel_unregister_dsm_handler();
 724
 725         intel_runtime_pm_disable(&dev_priv->runtime_pm);
 726         intel_power_domains_disable(dev_priv);
 727
 728         intel_fbdev_unregister(dev_priv);
 729         intel_audio_deinit(dev_priv);
 730
 731         /*
 732          * After flushing the fbdev (incl. a late async config which will
 733          * have delayed queuing of a hotplug event), then flush the hotplug
 734          * events.
 735          */
 736         drm_kms_helper_poll_fini(&dev_priv->drm);
 737
 738         intel_gt_driver_unregister(&dev_priv->gt);
 739         acpi_video_unregister();
 740         intel_opregion_unregister(dev_priv);
 741
 742         i915_perf_unregister(dev_priv);
 743         i915_pmu_unregister(dev_priv);
 744
 745         i915_teardown_sysfs(dev_priv);
 746         drm_dev_unplug(&dev_priv->drm);
 747
 748         i915_gem_driver_unregister(dev_priv);
 749 }
 750
 751 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
 752 {
 753         if (drm_debug_enabled(DRM_UT_DRIVER)) {
 754                 struct drm_printer p = drm_debug_printer("i915 device info:");
 755
 756                 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
 757                            INTEL_DEVID(dev_priv),
 758                            INTEL_REVID(dev_priv),
 759                            intel_platform_name(INTEL_INFO(dev_priv)->platform),
 760                            intel_subplatform(RUNTIME_INFO(dev_priv),
 761                                              INTEL_INFO(dev_priv)->platform),
 762                            INTEL_GEN(dev_priv));
 763
 764                 intel_device_info_print_static(INTEL_INFO(dev_priv), &p);
 765                 intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p);
 766                 intel_gt_info_print(&dev_priv->gt.info, &p);
 767         }
 768
 769         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
 770                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n");
 771         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
 772                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n");
 773         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
 774                 drm_info(&dev_priv->drm,
 775                          "DRM_I915_DEBUG_RUNTIME_PM enabled\n");
 776 }
 777
 778 static struct drm_i915_private *
 779 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
 780 {
 781         const struct intel_device_info *match_info =
 782                 (struct intel_device_info *)ent->driver_data;
 783         struct intel_device_info *device_info;
 784         struct drm_i915_private *i915;
 785
 786         i915 = devm_drm_dev_alloc(&pdev->dev, &driver,
 787                                   struct drm_i915_private, drm);
 788         if (IS_ERR(i915))
 789                 return i915;
 790
 791         i915->drm.pdev = pdev;
 792         pci_set_drvdata(pdev, i915);
 793
 794         /* Device parameters start as a copy of module parameters. */
 795         i915_params_copy(&i915->params, &i915_modparams);
 796
 797         /* Setup the write-once "constant" device info */
 798         device_info = mkwrite_device_info(i915);
 799         memcpy(device_info, match_info, sizeof(*device_info));
 800         RUNTIME_INFO(i915)->device_id = pdev->device;
 801
 802         BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
 803
 804         return i915;
 805 }
 806
 807 /**
 808  * i915_driver_probe - setup chip and create an initial config
 809  * @pdev: PCI device
 810  * @ent: matching PCI ID entry
 811  *
 812  * The driver probe routine has to do several things:
 813  *   - drive output discovery via intel_modeset_init()
 814  *   - initialize the memory manager
 815  *   - allocate initial config memory
 816  *   - setup the DRM framebuffer with the allocated memory
 817  */
 818 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 819 {
 820         const struct intel_device_info *match_info =
 821                 (struct intel_device_info *)ent->driver_data;
 822         struct drm_i915_private *i915;
 823         int ret;
 824
 825         i915 = i915_driver_create(pdev, ent);
 826         if (IS_ERR(i915))
 827                 return PTR_ERR(i915);
 828
 829         /* Disable nuclear pageflip by default on pre-ILK */
 830         if (!i915->params.nuclear_pageflip && match_info->gen < 5)
 831                 i915->drm.driver_features &= ~DRIVER_ATOMIC;
 832
 833         /*
 834          * Check if we support fake LMEM -- for now we only unleash this for
 835          * the live selftests(test-and-exit).
 836          */
 837 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 838         if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)) {
 839                 if (INTEL_GEN(i915) >= 9 && i915_selftest.live < 0 &&
 840                     i915->params.fake_lmem_start) {
 841                         mkwrite_device_info(i915)->memory_regions =
 842                                 REGION_SMEM | REGION_LMEM | REGION_STOLEN;
 843                         mkwrite_device_info(i915)->is_dgfx = true;
 844                         GEM_BUG_ON(!HAS_LMEM(i915));
 845                         GEM_BUG_ON(!IS_DGFX(i915));
 846                 }
 847         }
 848 #endif
 849
 850         ret = pci_enable_device(pdev);
 851         if (ret)
 852                 goto out_fini;
 853
 854         ret = i915_driver_early_probe(i915);
 855         if (ret < 0)
 856                 goto out_pci_disable;
 857
 858         disable_rpm_wakeref_asserts(&i915->runtime_pm);
 859
 860         intel_vgpu_detect(i915);
 861
 862         ret = i915_driver_mmio_probe(i915);
 863         if (ret < 0)
 864                 goto out_runtime_pm_put;
 865
 866         ret = i915_driver_hw_probe(i915);
 867         if (ret < 0)
 868                 goto out_cleanup_mmio;
 869
 870         ret = intel_modeset_init_noirq(i915);
 871         if (ret < 0)
 872                 goto out_cleanup_hw;
 873
 874         ret = intel_irq_install(i915);
 875         if (ret)
 876                 goto out_cleanup_modeset;
 877
 878         ret = intel_modeset_init_nogem(i915);
 879         if (ret)
 880                 goto out_cleanup_irq;
 881
 882         ret = i915_gem_init(i915);
 883         if (ret)
 884                 goto out_cleanup_modeset2;
 885
 886         ret = intel_modeset_init(i915);
 887         if (ret)
 888                 goto out_cleanup_gem;
 889
 890         i915_driver_register(i915);
 891
 892         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 893
 894         i915_welcome_messages(i915);
 895
 896         i915->do_release = true;
 897
 898         return 0;
 899
 900 out_cleanup_gem:
 901         i915_gem_suspend(i915);
 902         i915_gem_driver_remove(i915);
 903         i915_gem_driver_release(i915);
 904 out_cleanup_modeset2:
 905         /* FIXME clean up the error path */
 906         intel_modeset_driver_remove(i915);
 907         intel_irq_uninstall(i915);
 908         intel_modeset_driver_remove_noirq(i915);
 909         goto out_cleanup_modeset;
 910 out_cleanup_irq:
 911         intel_irq_uninstall(i915);
 912 out_cleanup_modeset:
 913         intel_modeset_driver_remove_nogem(i915);
 914 out_cleanup_hw:
 915         i915_driver_hw_remove(i915);
 916         intel_memory_regions_driver_release(i915);
 917         i915_ggtt_driver_release(i915);
 918 out_cleanup_mmio:
 919         i915_driver_mmio_release(i915);
 920 out_runtime_pm_put:
 921         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 922         i915_driver_late_release(i915);
 923 out_pci_disable:
 924         pci_disable_device(pdev);
 925 out_fini:
 926         i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
 927         return ret;
 928 }
 929
 930 void i915_driver_remove(struct drm_i915_private *i915)
 931 {
 932         disable_rpm_wakeref_asserts(&i915->runtime_pm);
 933
 934         i915_driver_unregister(i915);
 935
 936         /* Flush any external code that still may be under the RCU lock */
 937         synchronize_rcu();
 938
 939         i915_gem_suspend(i915);
 940
 941         drm_atomic_helper_shutdown(&i915->drm);
 942
 943         intel_gvt_driver_remove(i915);
 944
 945         intel_modeset_driver_remove(i915);
 946
 947         intel_irq_uninstall(i915);
 948
 949         intel_modeset_driver_remove_noirq(i915);
 950
 951         i915_reset_error_state(i915);
 952         i915_gem_driver_remove(i915);
 953
 954         intel_modeset_driver_remove_nogem(i915);
 955
 956         i915_driver_hw_remove(i915);
 957
 958         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 959 }
 960
 961 static void i915_driver_release(struct drm_device *dev)
 962 {
 963         struct drm_i915_private *dev_priv = to_i915(dev);
 964         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
 965
 966         if (!dev_priv->do_release)
 967                 return;
 968
 969         disable_rpm_wakeref_asserts(rpm);
 970
 971         i915_gem_driver_release(dev_priv);
 972
 973         intel_memory_regions_driver_release(dev_priv);
 974         i915_ggtt_driver_release(dev_priv);
 975         i915_gem_drain_freed_objects(dev_priv);
 976
 977         i915_driver_mmio_release(dev_priv);
 978
 979         enable_rpm_wakeref_asserts(rpm);
 980         intel_runtime_pm_driver_release(rpm);
 981
 982         i915_driver_late_release(dev_priv);
 983 }
 984
 985 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
 986 {
 987         struct drm_i915_private *i915 = to_i915(dev);
 988         int ret;
 989
 990         ret = i915_gem_open(i915, file);
 991         if (ret)
 992                 return ret;
 993
 994         return 0;
 995 }
 996
 997 /**
 998  * i915_driver_lastclose - clean up after all DRM clients have exited
 999  * @dev: DRM device
1000  *
1001  * Take care of cleaning up after all DRM clients have exited.  In the
1002  * mode setting case, we want to restore the kernel's initial mode (just
1003  * in case the last client left us in a bad state).
1004  *
1005  * Additionally, in the non-mode setting case, we'll tear down the GTT
1006  * and DMA structures, since the kernel won't be using them, and clea
1007  * up any GEM state.
1008  */
1009 static void i915_driver_lastclose(struct drm_device *dev)
1010 {
1011         intel_fbdev_restore_mode(dev);
1012         vga_switcheroo_process_delayed_switch();
1013 }
1014
1015 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1016 {
1017         struct drm_i915_file_private *file_priv = file->driver_priv;
1018
1019         i915_gem_context_close(file);
1020
1021         kfree_rcu(file_priv, rcu);
1022
1023         /* Catch up with all the deferred frees from "this" client */
1024         i915_gem_flush_free_objects(to_i915(dev));
1025 }
1026
1027 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1028 {
1029         struct drm_device *dev = &dev_priv->drm;
1030         struct intel_encoder *encoder;
1031
1032         drm_modeset_lock_all(dev);
1033         for_each_intel_encoder(dev, encoder)
1034                 if (encoder->suspend)
1035                         encoder->suspend(encoder);
1036         drm_modeset_unlock_all(dev);
1037 }
1038
1039 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1040 {
1041 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1042         if (acpi_target_system_state() < ACPI_STATE_S3)
1043                 return true;
1044 #endif
1045         return false;
1046 }
1047
1048 static int i915_drm_prepare(struct drm_device *dev)
1049 {
1050         struct drm_i915_private *i915 = to_i915(dev);
1051
1052         /*
1053          * NB intel_display_suspend() may issue new requests after we've
1054          * ostensibly marked the GPU as ready-to-sleep here. We need to
1055          * split out that work and pull it forward so that after point,
1056          * the GPU is not woken again.
1057          */
1058         i915_gem_suspend(i915);
1059
1060         return 0;
1061 }
1062
1063 static int i915_drm_suspend(struct drm_device *dev)
1064 {
1065         struct drm_i915_private *dev_priv = to_i915(dev);
1066         struct pci_dev *pdev = dev_priv->drm.pdev;
1067         pci_power_t opregion_target_state;
1068
1069         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1070
1071         /* We do a lot of poking in a lot of registers, make sure they work
1072          * properly. */
1073         intel_power_domains_disable(dev_priv);
1074
1075         drm_kms_helper_poll_disable(dev);
1076
1077         pci_save_state(pdev);
1078
1079         intel_display_suspend(dev);
1080
1081         intel_dp_mst_suspend(dev_priv);
1082
1083         intel_runtime_pm_disable_interrupts(dev_priv);
1084         intel_hpd_cancel_work(dev_priv);
1085
1086         intel_suspend_encoders(dev_priv);
1087
1088         intel_suspend_hw(dev_priv);
1089
1090         i915_ggtt_suspend(&dev_priv->ggtt);
1091
1092         i915_save_state(dev_priv);
1093
1094         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1095         intel_opregion_suspend(dev_priv, opregion_target_state);
1096
1097         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1098
1099         dev_priv->suspend_count++;
1100
1101         intel_csr_ucode_suspend(dev_priv);
1102
1103         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1104
1105         return 0;
1106 }
1107
1108 static enum i915_drm_suspend_mode
1109 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1110 {
1111         if (hibernate)
1112                 return I915_DRM_SUSPEND_HIBERNATE;
1113
1114         if (suspend_to_idle(dev_priv))
1115                 return I915_DRM_SUSPEND_IDLE;
1116
1117         return I915_DRM_SUSPEND_MEM;
1118 }
1119
1120 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1121 {
1122         struct drm_i915_private *dev_priv = to_i915(dev);
1123         struct pci_dev *pdev = dev_priv->drm.pdev;
1124         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1125         int ret;
1126
1127         disable_rpm_wakeref_asserts(rpm);
1128
1129         i915_gem_suspend_late(dev_priv);
1130
1131         intel_uncore_suspend(&dev_priv->uncore);
1132
1133         intel_power_domains_suspend(dev_priv,
1134                                     get_suspend_mode(dev_priv, hibernation));
1135
1136         intel_display_power_suspend_late(dev_priv);
1137
1138         ret = vlv_suspend_complete(dev_priv);
1139         if (ret) {
1140                 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);
1141                 intel_power_domains_resume(dev_priv);
1142
1143                 goto out;
1144         }
1145
1146         pci_disable_device(pdev);
1147         /*
1148          * During hibernation on some platforms the BIOS may try to access
1149          * the device even though it's already in D3 and hang the machine. So
1150          * leave the device in D0 on those platforms and hope the BIOS will
1151          * power down the device properly. The issue was seen on multiple old
1152          * GENs with different BIOS vendors, so having an explicit blacklist
1153          * is inpractical; apply the workaround on everything pre GEN6. The
1154          * platforms where the issue was seen:
1155          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1156          * Fujitsu FSC S7110
1157          * Acer Aspire 1830T
1158          */
1159         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1160                 pci_set_power_state(pdev, PCI_D3hot);
1161
1162 out:
1163         enable_rpm_wakeref_asserts(rpm);
1164         if (!dev_priv->uncore.user_forcewake_count)
1165                 intel_runtime_pm_driver_release(rpm);
1166
1167         return ret;
1168 }
1169
1170 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state)
1171 {
1172         int error;
1173
1174         if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&
1175                              state.event != PM_EVENT_FREEZE))
1176                 return -EINVAL;
1177
1178         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1179                 return 0;
1180
1181         error = i915_drm_suspend(&i915->drm);
1182         if (error)
1183                 return error;
1184
1185         return i915_drm_suspend_late(&i915->drm, false);
1186 }
1187
1188 static int i915_drm_resume(struct drm_device *dev)
1189 {
1190         struct drm_i915_private *dev_priv = to_i915(dev);
1191         int ret;
1192
1193         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1194
1195         sanitize_gpu(dev_priv);
1196
1197         ret = i915_ggtt_enable_hw(dev_priv);
1198         if (ret)
1199                 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
1200
1201         i915_ggtt_resume(&dev_priv->ggtt);
1202
1203         intel_csr_ucode_resume(dev_priv);
1204
1205         i915_restore_state(dev_priv);
1206         intel_pps_unlock_regs_wa(dev_priv);
1207
1208         intel_init_pch_refclk(dev_priv);
1209
1210         /*
1211          * Interrupts have to be enabled before any batches are run. If not the
1212          * GPU will hang. i915_gem_init_hw() will initiate batches to
1213          * update/restore the context.
1214          *
1215          * drm_mode_config_reset() needs AUX interrupts.
1216          *
1217          * Modeset enabling in intel_modeset_init_hw() also needs working
1218          * interrupts.
1219          */
1220         intel_runtime_pm_enable_interrupts(dev_priv);
1221
1222         drm_mode_config_reset(dev);
1223
1224         i915_gem_resume(dev_priv);
1225
1226         intel_modeset_init_hw(dev_priv);
1227         intel_init_clock_gating(dev_priv);
1228
1229         spin_lock_irq(&dev_priv->irq_lock);
1230         if (dev_priv->display.hpd_irq_setup)
1231                 dev_priv->display.hpd_irq_setup(dev_priv);
1232         spin_unlock_irq(&dev_priv->irq_lock);
1233
1234         intel_dp_mst_resume(dev_priv);
1235
1236         intel_display_resume(dev);
1237
1238         drm_kms_helper_poll_enable(dev);
1239
1240         /*
1241          * ... but also need to make sure that hotplug processing
1242          * doesn't cause havoc. Like in the driver load code we don't
1243          * bother with the tiny race here where we might lose hotplug
1244          * notifications.
1245          * */
1246         intel_hpd_init(dev_priv);
1247
1248         intel_opregion_resume(dev_priv);
1249
1250         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1251
1252         intel_power_domains_enable(dev_priv);
1253
1254         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1255
1256         return 0;
1257 }
1258
1259 static int i915_drm_resume_early(struct drm_device *dev)
1260 {
1261         struct drm_i915_private *dev_priv = to_i915(dev);
1262         struct pci_dev *pdev = dev_priv->drm.pdev;
1263         int ret;
1264
1265         /*
1266          * We have a resume ordering issue with the snd-hda driver also
1267          * requiring our device to be power up. Due to the lack of a
1268          * parent/child relationship we currently solve this with an early
1269          * resume hook.
1270          *
1271          * FIXME: This should be solved with a special hdmi sink device or
1272          * similar so that power domains can be employed.
1273          */
1274
1275         /*
1276          * Note that we need to set the power state explicitly, since we
1277          * powered off the device during freeze and the PCI core won't power
1278          * it back up for us during thaw. Powering off the device during
1279          * freeze is not a hard requirement though, and during the
1280          * suspend/resume phases the PCI core makes sure we get here with the
1281          * device powered on. So in case we change our freeze logic and keep
1282          * the device powered we can also remove the following set power state
1283          * call.
1284          */
1285         ret = pci_set_power_state(pdev, PCI_D0);
1286         if (ret) {
1287                 drm_err(&dev_priv->drm,
1288                         "failed to set PCI D0 power state (%d)\n", ret);
1289                 return ret;
1290         }
1291
1292         /*
1293          * Note that pci_enable_device() first enables any parent bridge
1294          * device and only then sets the power state for this device. The
1295          * bridge enabling is a nop though, since bridge devices are resumed
1296          * first. The order of enabling power and enabling the device is
1297          * imposed by the PCI core as described above, so here we preserve the
1298          * same order for the freeze/thaw phases.
1299          *
1300          * TODO: eventually we should remove pci_disable_device() /
1301          * pci_enable_enable_device() from suspend/resume. Due to how they
1302          * depend on the device enable refcount we can't anyway depend on them
1303          * disabling/enabling the device.
1304          */
1305         if (pci_enable_device(pdev))
1306                 return -EIO;
1307
1308         pci_set_master(pdev);
1309
1310         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1311
1312         ret = vlv_resume_prepare(dev_priv, false);
1313         if (ret)
1314                 drm_err(&dev_priv->drm,
1315                         "Resume prepare failed: %d, continuing anyway\n", ret);
1316
1317         intel_uncore_resume_early(&dev_priv->uncore);
1318
1319         intel_gt_check_and_clear_faults(&dev_priv->gt);
1320
1321         intel_display_power_resume_early(dev_priv);
1322
1323         intel_power_domains_resume(dev_priv);
1324
1325         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1326
1327         return ret;
1328 }
1329
1330 int i915_resume_switcheroo(struct drm_i915_private *i915)
1331 {
1332         int ret;
1333
1334         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1335                 return 0;
1336
1337         ret = i915_drm_resume_early(&i915->drm);
1338         if (ret)
1339                 return ret;
1340
1341         return i915_drm_resume(&i915->drm);
1342 }
1343
1344 static int i915_pm_prepare(struct device *kdev)
1345 {
1346         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1347
1348         if (!i915) {
1349                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1350                 return -ENODEV;
1351         }
1352
1353         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1354                 return 0;
1355
1356         return i915_drm_prepare(&i915->drm);
1357 }
1358
1359 static int i915_pm_suspend(struct device *kdev)
1360 {
1361         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1362
1363         if (!i915) {
1364                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1365                 return -ENODEV;
1366         }
1367
1368         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1369                 return 0;
1370
1371         return i915_drm_suspend(&i915->drm);
1372 }
1373
1374 static int i915_pm_suspend_late(struct device *kdev)
1375 {
1376         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1377
1378         /*
1379          * We have a suspend ordering issue with the snd-hda driver also
1380          * requiring our device to be power up. Due to the lack of a
1381          * parent/child relationship we currently solve this with an late
1382          * suspend hook.
1383          *
1384          * FIXME: This should be solved with a special hdmi sink device or
1385          * similar so that power domains can be employed.
1386          */
1387         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1388                 return 0;
1389
1390         return i915_drm_suspend_late(&i915->drm, false);
1391 }
1392
1393 static int i915_pm_poweroff_late(struct device *kdev)
1394 {
1395         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1396
1397         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1398                 return 0;
1399
1400         return i915_drm_suspend_late(&i915->drm, true);
1401 }
1402
1403 static int i915_pm_resume_early(struct device *kdev)
1404 {
1405         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1406
1407         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1408                 return 0;
1409
1410         return i915_drm_resume_early(&i915->drm);
1411 }
1412
1413 static int i915_pm_resume(struct device *kdev)
1414 {
1415         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1416
1417         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1418                 return 0;
1419
1420         return i915_drm_resume(&i915->drm);
1421 }
1422
1423 /* freeze: before creating the hibernation_image */
1424 static int i915_pm_freeze(struct device *kdev)
1425 {
1426         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1427         int ret;
1428
1429         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1430                 ret = i915_drm_suspend(&i915->drm);
1431                 if (ret)
1432                         return ret;
1433         }
1434
1435         ret = i915_gem_freeze(i915);
1436         if (ret)
1437                 return ret;
1438
1439         return 0;
1440 }
1441
1442 static int i915_pm_freeze_late(struct device *kdev)
1443 {
1444         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1445         int ret;
1446
1447         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1448                 ret = i915_drm_suspend_late(&i915->drm, true);
1449                 if (ret)
1450                         return ret;
1451         }
1452
1453         ret = i915_gem_freeze_late(i915);
1454         if (ret)
1455                 return ret;
1456
1457         return 0;
1458 }
1459
1460 /* thaw: called after creating the hibernation image, but before turning off. */
1461 static int i915_pm_thaw_early(struct device *kdev)
1462 {
1463         return i915_pm_resume_early(kdev);
1464 }
1465
1466 static int i915_pm_thaw(struct device *kdev)
1467 {
1468         return i915_pm_resume(kdev);
1469 }
1470
1471 /* restore: called after loading the hibernation image. */
1472 static int i915_pm_restore_early(struct device *kdev)
1473 {
1474         return i915_pm_resume_early(kdev);
1475 }
1476
1477 static int i915_pm_restore(struct device *kdev)
1478 {
1479         return i915_pm_resume(kdev);
1480 }
1481
1482 static int intel_runtime_suspend(struct device *kdev)
1483 {
1484         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1485         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1486         int ret;
1487
1488         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1489                 return -ENODEV;
1490
1491         drm_dbg_kms(&dev_priv->drm, "Suspending device\n");
1492
1493         disable_rpm_wakeref_asserts(rpm);
1494
1495         /*
1496          * We are safe here against re-faults, since the fault handler takes
1497          * an RPM reference.
1498          */
1499         i915_gem_runtime_suspend(dev_priv);
1500
1501         intel_gt_runtime_suspend(&dev_priv->gt);
1502
1503         intel_runtime_pm_disable_interrupts(dev_priv);
1504
1505         intel_uncore_suspend(&dev_priv->uncore);
1506
1507         intel_display_power_suspend(dev_priv);
1508
1509         ret = vlv_suspend_complete(dev_priv);
1510         if (ret) {
1511                 drm_err(&dev_priv->drm,
1512                         "Runtime suspend failed, disabling it (%d)\n", ret);
1513                 intel_uncore_runtime_resume(&dev_priv->uncore);
1514
1515                 intel_runtime_pm_enable_interrupts(dev_priv);
1516
1517                 intel_gt_runtime_resume(&dev_priv->gt);
1518
1519                 enable_rpm_wakeref_asserts(rpm);
1520
1521                 return ret;
1522         }
1523
1524         enable_rpm_wakeref_asserts(rpm);
1525         intel_runtime_pm_driver_release(rpm);
1526
1527         if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
1528                 drm_err(&dev_priv->drm,
1529                         "Unclaimed access detected prior to suspending\n");
1530
1531         rpm->suspended = true;
1532
1533         /*
1534          * FIXME: We really should find a document that references the arguments
1535          * used below!
1536          */
1537         if (IS_BROADWELL(dev_priv)) {
1538                 /*
1539                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1540                  * being detected, and the call we do at intel_runtime_resume()
1541                  * won't be able to restore them. Since PCI_D3hot matches the
1542                  * actual specification and appears to be working, use it.
1543                  */
1544                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
1545         } else {
1546                 /*
1547                  * current versions of firmware which depend on this opregion
1548                  * notification have repurposed the D1 definition to mean
1549                  * "runtime suspended" vs. what you would normally expect (D3)
1550                  * to distinguish it from notifications that might be sent via
1551                  * the suspend path.
1552                  */
1553                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
1554         }
1555
1556         assert_forcewakes_inactive(&dev_priv->uncore);
1557
1558         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1559                 intel_hpd_poll_init(dev_priv);
1560
1561         drm_dbg_kms(&dev_priv->drm, "Device suspended\n");
1562         return 0;
1563 }
1564
1565 static int intel_runtime_resume(struct device *kdev)
1566 {
1567         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1568         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1569         int ret;
1570
1571         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1572                 return -ENODEV;
1573
1574         drm_dbg_kms(&dev_priv->drm, "Resuming device\n");
1575
1576         drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
1577         disable_rpm_wakeref_asserts(rpm);
1578
1579         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1580         rpm->suspended = false;
1581         if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
1582                 drm_dbg(&dev_priv->drm,
1583                         "Unclaimed access during suspend, bios?\n");
1584
1585         intel_display_power_resume(dev_priv);
1586
1587         ret = vlv_resume_prepare(dev_priv, true);
1588
1589         intel_uncore_runtime_resume(&dev_priv->uncore);
1590
1591         intel_runtime_pm_enable_interrupts(dev_priv);
1592
1593         /*
1594          * No point of rolling back things in case of an error, as the best
1595          * we can do is to hope that things will still work (and disable RPM).
1596          */
1597         intel_gt_runtime_resume(&dev_priv->gt);
1598
1599         /*
1600          * On VLV/CHV display interrupts are part of the display
1601          * power well, so hpd is reinitialized from there. For
1602          * everyone else do it here.
1603          */
1604         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1605                 intel_hpd_init(dev_priv);
1606
1607         intel_enable_ipc(dev_priv);
1608
1609         enable_rpm_wakeref_asserts(rpm);
1610
1611         if (ret)
1612                 drm_err(&dev_priv->drm,
1613                         "Runtime resume failed, disabling it (%d)\n", ret);
1614         else
1615                 drm_dbg_kms(&dev_priv->drm, "Device resumed\n");
1616
1617         return ret;
1618 }
1619
1620 const struct dev_pm_ops i915_pm_ops = {
1621         /*
1622          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1623          * PMSG_RESUME]
1624          */
1625         .prepare = i915_pm_prepare,
1626         .suspend = i915_pm_suspend,
1627         .suspend_late = i915_pm_suspend_late,
1628         .resume_early = i915_pm_resume_early,
1629         .resume = i915_pm_resume,
1630
1631         /*
1632          * S4 event handlers
1633          * @freeze, @freeze_late    : called (1) before creating the
1634          *                            hibernation image [PMSG_FREEZE] and
1635          *                            (2) after rebooting, before restoring
1636          *                            the image [PMSG_QUIESCE]
1637          * @thaw, @thaw_early       : called (1) after creating the hibernation
1638          *                            image, before writing it [PMSG_THAW]
1639          *                            and (2) after failing to create or
1640          *                            restore the image [PMSG_RECOVER]
1641          * @poweroff, @poweroff_late: called after writing the hibernation
1642          *                            image, before rebooting [PMSG_HIBERNATE]
1643          * @restore, @restore_early : called after rebooting and restoring the
1644          *                            hibernation image [PMSG_RESTORE]
1645          */
1646         .freeze = i915_pm_freeze,
1647         .freeze_late = i915_pm_freeze_late,
1648         .thaw_early = i915_pm_thaw_early,
1649         .thaw = i915_pm_thaw,
1650         .poweroff = i915_pm_suspend,
1651         .poweroff_late = i915_pm_poweroff_late,
1652         .restore_early = i915_pm_restore_early,
1653         .restore = i915_pm_restore,
1654
1655         /* S0ix (via runtime suspend) event handlers */
1656         .runtime_suspend = intel_runtime_suspend,
1657         .runtime_resume = intel_runtime_resume,
1658 };
1659
1660 static const struct file_operations i915_driver_fops = {
1661         .owner = THIS_MODULE,
1662         .open = drm_open,
1663         .release = drm_release_noglobal,
1664         .unlocked_ioctl = drm_ioctl,
1665         .mmap = i915_gem_mmap,
1666         .poll = drm_poll,
1667         .read = drm_read,
1668         .compat_ioctl = i915_ioc32_compat_ioctl,
1669         .llseek = noop_llseek,
1670 };
1671
1672 static int
1673 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1674                           struct drm_file *file)
1675 {
1676         return -ENODEV;
1677 }
1678
1679 static const struct drm_ioctl_desc i915_ioctls[] = {
1680         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1681         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1682         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1683         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1684         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1685         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1686         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
1687         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1688         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1689         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1690         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1691         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1692         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1693         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1694         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
1695         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1696         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1697         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1698         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
1699         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
1700         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1701         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1702         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
1703         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1704         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1705         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
1706         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1707         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1708         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1709         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1710         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1711         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1712         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
1713         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1714         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1715         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
1716         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
1717         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1718         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
1719         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1720         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
1721         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
1722         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
1723         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
1724         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
1725         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1726         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1727         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1728         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
1729         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1730         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1731         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1732         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
1733         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
1734         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
1735         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
1736         DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
1737         DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
1738 };
1739
1740 static struct drm_driver driver = {
1741         /* Don't use MTRRs here; the Xserver or userspace app should
1742          * deal with them for Intel hardware.
1743          */
1744         .driver_features =
1745             DRIVER_GEM |
1746             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ |
1747             DRIVER_SYNCOBJ_TIMELINE,
1748         .release = i915_driver_release,
1749         .open = i915_driver_open,
1750         .lastclose = i915_driver_lastclose,
1751         .postclose = i915_driver_postclose,
1752
1753         .gem_close_object = i915_gem_close_object,
1754         .gem_free_object_unlocked = i915_gem_free_object,
1755
1756         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1757         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1758         .gem_prime_export = i915_gem_prime_export,
1759         .gem_prime_import = i915_gem_prime_import,
1760
1761         .dumb_create = i915_gem_dumb_create,
1762         .dumb_map_offset = i915_gem_dumb_mmap_offset,
1763
1764         .ioctls = i915_ioctls,
1765         .num_ioctls = ARRAY_SIZE(i915_ioctls),
1766         .fops = &i915_driver_fops,
1767         .name = DRIVER_NAME,
1768         .desc = DRIVER_DESC,
1769         .date = DRIVER_DATE,
1770         .major = DRIVER_MAJOR,
1771         .minor = DRIVER_MINOR,
1772         .patchlevel = DRIVER_PATCHLEVEL,
1773 };