drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drm_atomic_helper.h>
  45 #include <drm/drm_ioctl.h>
  46 #include <drm/drm_irq.h>
  47 #include <drm/drm_probe_helper.h>
  48 #include <drm/i915_drm.h>
  49
  50 #include "display/intel_acpi.h"
  51 #include "display/intel_audio.h"
  52 #include "display/intel_bw.h"
  53 #include "display/intel_cdclk.h"
  54 #include "display/intel_display_types.h"
  55 #include "display/intel_dp.h"
  56 #include "display/intel_fbdev.h"
  57 #include "display/intel_gmbus.h"
  58 #include "display/intel_hotplug.h"
  59 #include "display/intel_overlay.h"
  60 #include "display/intel_pipe_crc.h"
  61 #include "display/intel_sprite.h"
  62
  63 #include "gem/i915_gem_context.h"
  64 #include "gem/i915_gem_ioctls.h"
  65 #include "gt/intel_gt.h"
  66 #include "gt/intel_gt_pm.h"
  67
  68 #include "i915_debugfs.h"
  69 #include "i915_drv.h"
  70 #include "i915_irq.h"
  71 #include "i915_memcpy.h"
  72 #include "i915_perf.h"
  73 #include "i915_query.h"
  74 #include "i915_suspend.h"
  75 #include "i915_sysfs.h"
  76 #include "i915_trace.h"
  77 #include "i915_vgpu.h"
  78 #include "intel_csr.h"
  79 #include "intel_pm.h"
  80
  81 static struct drm_driver driver;
  82
  83 struct vlv_s0ix_state {
  84         /* GAM */
  85         u32 wr_watermark;
  86         u32 gfx_prio_ctrl;
  87         u32 arb_mode;
  88         u32 gfx_pend_tlb0;
  89         u32 gfx_pend_tlb1;
  90         u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
  91         u32 media_max_req_count;
  92         u32 gfx_max_req_count;
  93         u32 render_hwsp;
  94         u32 ecochk;
  95         u32 bsd_hwsp;
  96         u32 blt_hwsp;
  97         u32 tlb_rd_addr;
  98
  99         /* MBC */
 100         u32 g3dctl;
 101         u32 gsckgctl;
 102         u32 mbctl;
 103
 104         /* GCP */
 105         u32 ucgctl1;
 106         u32 ucgctl3;
 107         u32 rcgctl1;
 108         u32 rcgctl2;
 109         u32 rstctl;
 110         u32 misccpctl;
 111
 112         /* GPM */
 113         u32 gfxpause;
 114         u32 rpdeuhwtc;
 115         u32 rpdeuc;
 116         u32 ecobus;
 117         u32 pwrdwnupctl;
 118         u32 rp_down_timeout;
 119         u32 rp_deucsw;
 120         u32 rcubmabdtmr;
 121         u32 rcedata;
 122         u32 spare2gh;
 123
 124         /* Display 1 CZ domain */
 125         u32 gt_imr;
 126         u32 gt_ier;
 127         u32 pm_imr;
 128         u32 pm_ier;
 129         u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
 130
 131         /* GT SA CZ domain */
 132         u32 tilectl;
 133         u32 gt_fifoctl;
 134         u32 gtlc_wake_ctrl;
 135         u32 gtlc_survive;
 136         u32 pmwgicz;
 137
 138         /* Display 2 CZ domain */
 139         u32 gu_ctl0;
 140         u32 gu_ctl1;
 141         u32 pcbr;
 142         u32 clock_gate_dis2;
 143 };
 144
 145 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 146 {
 147         int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
 148
 149         dev_priv->bridge_dev =
 150                 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
 151         if (!dev_priv->bridge_dev) {
 152                 DRM_ERROR("bridge device not found\n");
 153                 return -1;
 154         }
 155         return 0;
 156 }
 157
 158 /* Allocate space for the MCH regs if needed, return nonzero on error */
 159 static int
 160 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 161 {
 162         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 163         u32 temp_lo, temp_hi = 0;
 164         u64 mchbar_addr;
 165         int ret;
 166
 167         if (INTEL_GEN(dev_priv) >= 4)
 168                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 169         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 170         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 171
 172         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 173 #ifdef CONFIG_PNP
 174         if (mchbar_addr &&
 175             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 176                 return 0;
 177 #endif
 178
 179         /* Get some space for it */
 180         dev_priv->mch_res.name = "i915 MCHBAR";
 181         dev_priv->mch_res.flags = IORESOURCE_MEM;
 182         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 183                                      &dev_priv->mch_res,
 184                                      MCHBAR_SIZE, MCHBAR_SIZE,
 185                                      PCIBIOS_MIN_MEM,
 186                                      0, pcibios_align_resource,
 187                                      dev_priv->bridge_dev);
 188         if (ret) {
 189                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 190                 dev_priv->mch_res.start = 0;
 191                 return ret;
 192         }
 193
 194         if (INTEL_GEN(dev_priv) >= 4)
 195                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 196                                        upper_32_bits(dev_priv->mch_res.start));
 197
 198         pci_write_config_dword(dev_priv->bridge_dev, reg,
 199                                lower_32_bits(dev_priv->mch_res.start));
 200         return 0;
 201 }
 202
 203 /* Setup MCHBAR if possible, return true if we should disable it again */
 204 static void
 205 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 206 {
 207         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 208         u32 temp;
 209         bool enabled;
 210
 211         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 212                 return;
 213
 214         dev_priv->mchbar_need_disable = false;
 215
 216         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 217                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 218                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 219         } else {
 220                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 221                 enabled = temp & 1;
 222         }
 223
 224         /* If it's already enabled, don't have to do anything */
 225         if (enabled)
 226                 return;
 227
 228         if (intel_alloc_mchbar_resource(dev_priv))
 229                 return;
 230
 231         dev_priv->mchbar_need_disable = true;
 232
 233         /* Space is allocated or reserved, so enable it. */
 234         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 235                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 236                                        temp | DEVEN_MCHBAR_EN);
 237         } else {
 238                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 239                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 240         }
 241 }
 242
 243 static void
 244 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 245 {
 246         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 247
 248         if (dev_priv->mchbar_need_disable) {
 249                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 250                         u32 deven_val;
 251
 252                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 253                                               &deven_val);
 254                         deven_val &= ~DEVEN_MCHBAR_EN;
 255                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 256                                                deven_val);
 257                 } else {
 258                         u32 mchbar_val;
 259
 260                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 261                                               &mchbar_val);
 262                         mchbar_val &= ~1;
 263                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 264                                                mchbar_val);
 265                 }
 266         }
 267
 268         if (dev_priv->mch_res.start)
 269                 release_resource(&dev_priv->mch_res);
 270 }
 271
 272 /* true = enable decode, false = disable decoder */
 273 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 274 {
 275         struct drm_i915_private *dev_priv = cookie;
 276
 277         intel_modeset_vga_set_state(dev_priv, state);
 278         if (state)
 279                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 280                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 281         else
 282                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 283 }
 284
 285 static int i915_resume_switcheroo(struct drm_i915_private *i915);
 286 static int i915_suspend_switcheroo(struct drm_i915_private *i915,
 287                                    pm_message_t state);
 288
 289 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 290 {
 291         struct drm_i915_private *i915 = pdev_to_i915(pdev);
 292         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 293
 294         if (!i915) {
 295                 dev_err(&pdev->dev, "DRM not initialized, aborting switch.\n");
 296                 return;
 297         }
 298
 299         if (state == VGA_SWITCHEROO_ON) {
 300                 pr_info("switched on\n");
 301                 i915->drm.switch_power_state = DRM_SWITCH_POWER_CHANGING;
 302                 /* i915 resume handler doesn't set to D0 */
 303                 pci_set_power_state(pdev, PCI_D0);
 304                 i915_resume_switcheroo(i915);
 305                 i915->drm.switch_power_state = DRM_SWITCH_POWER_ON;
 306         } else {
 307                 pr_info("switched off\n");
 308                 i915->drm.switch_power_state = DRM_SWITCH_POWER_CHANGING;
 309                 i915_suspend_switcheroo(i915, pmm);
 310                 i915->drm.switch_power_state = DRM_SWITCH_POWER_OFF;
 311         }
 312 }
 313
 314 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 315 {
 316         struct drm_i915_private *i915 = pdev_to_i915(pdev);
 317
 318         /*
 319          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 320          * locking inversion with the driver load path. And the access here is
 321          * completely racy anyway. So don't bother with locking for now.
 322          */
 323         return i915 && i915->drm.open_count == 0;
 324 }
 325
 326 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 327         .set_gpu_state = i915_switcheroo_set_state,
 328         .reprobe = NULL,
 329         .can_switch = i915_switcheroo_can_switch,
 330 };
 331
 332 static int i915_driver_modeset_probe(struct drm_device *dev)
 333 {
 334         struct drm_i915_private *dev_priv = to_i915(dev);
 335         struct pci_dev *pdev = dev_priv->drm.pdev;
 336         int ret;
 337
 338         if (i915_inject_probe_failure(dev_priv))
 339                 return -ENODEV;
 340
 341         if (HAS_DISPLAY(dev_priv)) {
 342                 ret = drm_vblank_init(&dev_priv->drm,
 343                                       INTEL_INFO(dev_priv)->num_pipes);
 344                 if (ret)
 345                         goto out;
 346         }
 347
 348         intel_bios_init(dev_priv);
 349
 350         /* If we have > 1 VGA cards, then we need to arbitrate access
 351          * to the common VGA resources.
 352          *
 353          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 354          * then we do not take part in VGA arbitration and the
 355          * vga_client_register() fails with -ENODEV.
 356          */
 357         ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
 358         if (ret && ret != -ENODEV)
 359                 goto out;
 360
 361         intel_register_dsm_handler();
 362
 363         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 364         if (ret)
 365                 goto cleanup_vga_client;
 366
 367         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 368         intel_update_rawclk(dev_priv);
 369
 370         intel_power_domains_init_hw(dev_priv, false);
 371
 372         intel_csr_ucode_init(dev_priv);
 373
 374         ret = intel_irq_install(dev_priv);
 375         if (ret)
 376                 goto cleanup_csr;
 377
 378         intel_gmbus_setup(dev_priv);
 379
 380         /* Important: The output setup functions called by modeset_init need
 381          * working irqs for e.g. gmbus and dp aux transfers. */
 382         ret = intel_modeset_init(dev);
 383         if (ret)
 384                 goto cleanup_irq;
 385
 386         ret = i915_gem_init(dev_priv);
 387         if (ret)
 388                 goto cleanup_modeset;
 389
 390         intel_overlay_setup(dev_priv);
 391
 392         if (!HAS_DISPLAY(dev_priv))
 393                 return 0;
 394
 395         ret = intel_fbdev_init(dev);
 396         if (ret)
 397                 goto cleanup_gem;
 398
 399         /* Only enable hotplug handling once the fbdev is fully set up. */
 400         intel_hpd_init(dev_priv);
 401
 402         intel_init_ipc(dev_priv);
 403
 404         return 0;
 405
 406 cleanup_gem:
 407         i915_gem_suspend(dev_priv);
 408         i915_gem_driver_remove(dev_priv);
 409         i915_gem_driver_release(dev_priv);
 410 cleanup_modeset:
 411         intel_modeset_driver_remove(dev);
 412 cleanup_irq:
 413         intel_irq_uninstall(dev_priv);
 414         intel_gmbus_teardown(dev_priv);
 415 cleanup_csr:
 416         intel_csr_ucode_fini(dev_priv);
 417         intel_power_domains_driver_remove(dev_priv);
 418         vga_switcheroo_unregister_client(pdev);
 419 cleanup_vga_client:
 420         vga_client_register(pdev, NULL, NULL, NULL);
 421 out:
 422         return ret;
 423 }
 424
 425 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 426 {
 427         /*
 428          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 429          * CHV x1 PHY (DP/HDMI D)
 430          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 431          */
 432         if (IS_CHERRYVIEW(dev_priv)) {
 433                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 434                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 435         } else if (IS_VALLEYVIEW(dev_priv)) {
 436                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 437         }
 438 }
 439
 440 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 441 {
 442         /*
 443          * The i915 workqueue is primarily used for batched retirement of
 444          * requests (and thus managing bo) once the task has been completed
 445          * by the GPU. i915_retire_requests() is called directly when we
 446          * need high-priority retirement, such as waiting for an explicit
 447          * bo.
 448          *
 449          * It is also used for periodic low-priority events, such as
 450          * idle-timers and recording error state.
 451          *
 452          * All tasks on the workqueue are expected to acquire the dev mutex
 453          * so there is no point in running more than one instance of the
 454          * workqueue at any time.  Use an ordered one.
 455          */
 456         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 457         if (dev_priv->wq == NULL)
 458                 goto out_err;
 459
 460         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 461         if (dev_priv->hotplug.dp_wq == NULL)
 462                 goto out_free_wq;
 463
 464         return 0;
 465
 466 out_free_wq:
 467         destroy_workqueue(dev_priv->wq);
 468 out_err:
 469         DRM_ERROR("Failed to allocate workqueues.\n");
 470
 471         return -ENOMEM;
 472 }
 473
 474 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 475 {
 476         destroy_workqueue(dev_priv->hotplug.dp_wq);
 477         destroy_workqueue(dev_priv->wq);
 478 }
 479
 480 /*
 481  * We don't keep the workarounds for pre-production hardware, so we expect our
 482  * driver to fail on these machines in one way or another. A little warning on
 483  * dmesg may help both the user and the bug triagers.
 484  *
 485  * Our policy for removing pre-production workarounds is to keep the
 486  * current gen workarounds as a guide to the bring-up of the next gen
 487  * (workarounds have a habit of persisting!). Anything older than that
 488  * should be removed along with the complications they introduce.
 489  */
 490 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 491 {
 492         bool pre = false;
 493
 494         pre |= IS_HSW_EARLY_SDV(dev_priv);
 495         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 496         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 497         pre |= IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0);
 498
 499         if (pre) {
 500                 DRM_ERROR("This is a pre-production stepping. "
 501                           "It may not be fully functional.\n");
 502                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 503         }
 504 }
 505
 506 static int vlv_alloc_s0ix_state(struct drm_i915_private *i915)
 507 {
 508         if (!IS_VALLEYVIEW(i915))
 509                 return 0;
 510
 511         /* we write all the values in the struct, so no need to zero it out */
 512         i915->vlv_s0ix_state = kmalloc(sizeof(*i915->vlv_s0ix_state),
 513                                        GFP_KERNEL);
 514         if (!i915->vlv_s0ix_state)
 515                 return -ENOMEM;
 516
 517         return 0;
 518 }
 519
 520 static void vlv_free_s0ix_state(struct drm_i915_private *i915)
 521 {
 522         if (!i915->vlv_s0ix_state)
 523                 return;
 524
 525         kfree(i915->vlv_s0ix_state);
 526         i915->vlv_s0ix_state = NULL;
 527 }
 528
 529 /**
 530  * i915_driver_early_probe - setup state not requiring device access
 531  * @dev_priv: device private
 532  *
 533  * Initialize everything that is a "SW-only" state, that is state not
 534  * requiring accessing the device or exposing the driver via kernel internal
 535  * or userspace interfaces. Example steps belonging here: lock initialization,
 536  * system memory allocation, setting up device specific attributes and
 537  * function hooks not requiring accessing the device.
 538  */
 539 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
 540 {
 541         int ret = 0;
 542
 543         if (i915_inject_probe_failure(dev_priv))
 544                 return -ENODEV;
 545
 546         intel_device_info_subplatform_init(dev_priv);
 547
 548         intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
 549         intel_uncore_init_early(&dev_priv->uncore, dev_priv);
 550
 551         spin_lock_init(&dev_priv->irq_lock);
 552         spin_lock_init(&dev_priv->gpu_error.lock);
 553         mutex_init(&dev_priv->backlight_lock);
 554
 555         mutex_init(&dev_priv->sb_lock);
 556         pm_qos_add_request(&dev_priv->sb_qos,
 557                            PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
 558
 559         mutex_init(&dev_priv->av_mutex);
 560         mutex_init(&dev_priv->wm.wm_mutex);
 561         mutex_init(&dev_priv->pps_mutex);
 562         mutex_init(&dev_priv->hdcp_comp_mutex);
 563
 564         i915_memcpy_init_early(dev_priv);
 565         intel_runtime_pm_init_early(&dev_priv->runtime_pm);
 566
 567         ret = i915_workqueues_init(dev_priv);
 568         if (ret < 0)
 569                 return ret;
 570
 571         ret = vlv_alloc_s0ix_state(dev_priv);
 572         if (ret < 0)
 573                 goto err_workqueues;
 574
 575         intel_wopcm_init_early(&dev_priv->wopcm);
 576
 577         intel_gt_init_early(&dev_priv->gt, dev_priv);
 578
 579         ret = i915_gem_init_early(dev_priv);
 580         if (ret < 0)
 581                 goto err_gt;
 582
 583         /* This must be called before any calls to HAS_PCH_* */
 584         intel_detect_pch(dev_priv);
 585
 586         intel_pm_setup(dev_priv);
 587         intel_init_dpio(dev_priv);
 588         ret = intel_power_domains_init(dev_priv);
 589         if (ret < 0)
 590                 goto err_gem;
 591         intel_irq_init(dev_priv);
 592         intel_init_display_hooks(dev_priv);
 593         intel_init_clock_gating_hooks(dev_priv);
 594         intel_init_audio_hooks(dev_priv);
 595         intel_display_crc_init(dev_priv);
 596
 597         intel_detect_preproduction_hw(dev_priv);
 598
 599         return 0;
 600
 601 err_gem:
 602         i915_gem_cleanup_early(dev_priv);
 603 err_gt:
 604         intel_gt_driver_late_release(&dev_priv->gt);
 605         vlv_free_s0ix_state(dev_priv);
 606 err_workqueues:
 607         i915_workqueues_cleanup(dev_priv);
 608         return ret;
 609 }
 610
 611 /**
 612  * i915_driver_late_release - cleanup the setup done in
 613  *                             i915_driver_early_probe()
 614  * @dev_priv: device private
 615  */
 616 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
 617 {
 618         intel_irq_fini(dev_priv);
 619         intel_power_domains_cleanup(dev_priv);
 620         i915_gem_cleanup_early(dev_priv);
 621         intel_gt_driver_late_release(&dev_priv->gt);
 622         vlv_free_s0ix_state(dev_priv);
 623         i915_workqueues_cleanup(dev_priv);
 624
 625         pm_qos_remove_request(&dev_priv->sb_qos);
 626         mutex_destroy(&dev_priv->sb_lock);
 627 }
 628
 629 /**
 630  * i915_driver_mmio_probe - setup device MMIO
 631  * @dev_priv: device private
 632  *
 633  * Setup minimal device state necessary for MMIO accesses later in the
 634  * initialization sequence. The setup here should avoid any other device-wide
 635  * side effects or exposing the driver via kernel internal or user space
 636  * interfaces.
 637  */
 638 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
 639 {
 640         int ret;
 641
 642         if (i915_inject_probe_failure(dev_priv))
 643                 return -ENODEV;
 644
 645         if (i915_get_bridge_dev(dev_priv))
 646                 return -EIO;
 647
 648         ret = intel_uncore_init_mmio(&dev_priv->uncore);
 649         if (ret < 0)
 650                 goto err_bridge;
 651
 652         /* Try to make sure MCHBAR is enabled before poking at it */
 653         intel_setup_mchbar(dev_priv);
 654
 655         intel_device_info_init_mmio(dev_priv);
 656
 657         intel_uncore_prune_mmio_domains(&dev_priv->uncore);
 658
 659         intel_uc_init_mmio(&dev_priv->gt.uc);
 660
 661         ret = intel_engines_init_mmio(dev_priv);
 662         if (ret)
 663                 goto err_uncore;
 664
 665         i915_gem_init_mmio(dev_priv);
 666
 667         return 0;
 668
 669 err_uncore:
 670         intel_teardown_mchbar(dev_priv);
 671         intel_uncore_fini_mmio(&dev_priv->uncore);
 672 err_bridge:
 673         pci_dev_put(dev_priv->bridge_dev);
 674
 675         return ret;
 676 }
 677
 678 /**
 679  * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
 680  * @dev_priv: device private
 681  */
 682 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
 683 {
 684         intel_engines_cleanup(dev_priv);
 685         intel_teardown_mchbar(dev_priv);
 686         intel_uncore_fini_mmio(&dev_priv->uncore);
 687         pci_dev_put(dev_priv->bridge_dev);
 688 }
 689
 690 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 691 {
 692         intel_gvt_sanitize_options(dev_priv);
 693 }
 694
 695 #define DRAM_TYPE_STR(type) [INTEL_DRAM_ ## type] = #type
 696
 697 static const char *intel_dram_type_str(enum intel_dram_type type)
 698 {
 699         static const char * const str[] = {
 700                 DRAM_TYPE_STR(UNKNOWN),
 701                 DRAM_TYPE_STR(DDR3),
 702                 DRAM_TYPE_STR(DDR4),
 703                 DRAM_TYPE_STR(LPDDR3),
 704                 DRAM_TYPE_STR(LPDDR4),
 705         };
 706
 707         if (type >= ARRAY_SIZE(str))
 708                 type = INTEL_DRAM_UNKNOWN;
 709
 710         return str[type];
 711 }
 712
 713 #undef DRAM_TYPE_STR
 714
 715 static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
 716 {
 717         return dimm->ranks * 64 / (dimm->width ?: 1);
 718 }
 719
 720 /* Returns total GB for the whole DIMM */
 721 static int skl_get_dimm_size(u16 val)
 722 {
 723         return val & SKL_DRAM_SIZE_MASK;
 724 }
 725
 726 static int skl_get_dimm_width(u16 val)
 727 {
 728         if (skl_get_dimm_size(val) == 0)
 729                 return 0;
 730
 731         switch (val & SKL_DRAM_WIDTH_MASK) {
 732         case SKL_DRAM_WIDTH_X8:
 733         case SKL_DRAM_WIDTH_X16:
 734         case SKL_DRAM_WIDTH_X32:
 735                 val = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
 736                 return 8 << val;
 737         default:
 738                 MISSING_CASE(val);
 739                 return 0;
 740         }
 741 }
 742
 743 static int skl_get_dimm_ranks(u16 val)
 744 {
 745         if (skl_get_dimm_size(val) == 0)
 746                 return 0;
 747
 748         val = (val & SKL_DRAM_RANK_MASK) >> SKL_DRAM_RANK_SHIFT;
 749
 750         return val + 1;
 751 }
 752
 753 /* Returns total GB for the whole DIMM */
 754 static int cnl_get_dimm_size(u16 val)
 755 {
 756         return (val & CNL_DRAM_SIZE_MASK) / 2;
 757 }
 758
 759 static int cnl_get_dimm_width(u16 val)
 760 {
 761         if (cnl_get_dimm_size(val) == 0)
 762                 return 0;
 763
 764         switch (val & CNL_DRAM_WIDTH_MASK) {
 765         case CNL_DRAM_WIDTH_X8:
 766         case CNL_DRAM_WIDTH_X16:
 767         case CNL_DRAM_WIDTH_X32:
 768                 val = (val & CNL_DRAM_WIDTH_MASK) >> CNL_DRAM_WIDTH_SHIFT;
 769                 return 8 << val;
 770         default:
 771                 MISSING_CASE(val);
 772                 return 0;
 773         }
 774 }
 775
 776 static int cnl_get_dimm_ranks(u16 val)
 777 {
 778         if (cnl_get_dimm_size(val) == 0)
 779                 return 0;
 780
 781         val = (val & CNL_DRAM_RANK_MASK) >> CNL_DRAM_RANK_SHIFT;
 782
 783         return val + 1;
 784 }
 785
 786 static bool
 787 skl_is_16gb_dimm(const struct dram_dimm_info *dimm)
 788 {
 789         /* Convert total GB to Gb per DRAM device */
 790         return 8 * dimm->size / (intel_dimm_num_devices(dimm) ?: 1) == 16;
 791 }
 792
 793 static void
 794 skl_dram_get_dimm_info(struct drm_i915_private *dev_priv,
 795                        struct dram_dimm_info *dimm,
 796                        int channel, char dimm_name, u16 val)
 797 {
 798         if (INTEL_GEN(dev_priv) >= 10) {
 799                 dimm->size = cnl_get_dimm_size(val);
 800                 dimm->width = cnl_get_dimm_width(val);
 801                 dimm->ranks = cnl_get_dimm_ranks(val);
 802         } else {
 803                 dimm->size = skl_get_dimm_size(val);
 804                 dimm->width = skl_get_dimm_width(val);
 805                 dimm->ranks = skl_get_dimm_ranks(val);
 806         }
 807
 808         DRM_DEBUG_KMS("CH%u DIMM %c size: %u GB, width: X%u, ranks: %u, 16Gb DIMMs: %s\n",
 809                       channel, dimm_name, dimm->size, dimm->width, dimm->ranks,
 810                       yesno(skl_is_16gb_dimm(dimm)));
 811 }
 812
 813 static int
 814 skl_dram_get_channel_info(struct drm_i915_private *dev_priv,
 815                           struct dram_channel_info *ch,
 816                           int channel, u32 val)
 817 {
 818         skl_dram_get_dimm_info(dev_priv, &ch->dimm_l,
 819                                channel, 'L', val & 0xffff);
 820         skl_dram_get_dimm_info(dev_priv, &ch->dimm_s,
 821                                channel, 'S', val >> 16);
 822
 823         if (ch->dimm_l.size == 0 && ch->dimm_s.size == 0) {
 824                 DRM_DEBUG_KMS("CH%u not populated\n", channel);
 825                 return -EINVAL;
 826         }
 827
 828         if (ch->dimm_l.ranks == 2 || ch->dimm_s.ranks == 2)
 829                 ch->ranks = 2;
 830         else if (ch->dimm_l.ranks == 1 && ch->dimm_s.ranks == 1)
 831                 ch->ranks = 2;
 832         else
 833                 ch->ranks = 1;
 834
 835         ch->is_16gb_dimm =
 836                 skl_is_16gb_dimm(&ch->dimm_l) ||
 837                 skl_is_16gb_dimm(&ch->dimm_s);
 838
 839         DRM_DEBUG_KMS("CH%u ranks: %u, 16Gb DIMMs: %s\n",
 840                       channel, ch->ranks, yesno(ch->is_16gb_dimm));
 841
 842         return 0;
 843 }
 844
 845 static bool
 846 intel_is_dram_symmetric(const struct dram_channel_info *ch0,
 847                         const struct dram_channel_info *ch1)
 848 {
 849         return !memcmp(ch0, ch1, sizeof(*ch0)) &&
 850                 (ch0->dimm_s.size == 0 ||
 851                  !memcmp(&ch0->dimm_l, &ch0->dimm_s, sizeof(ch0->dimm_l)));
 852 }
 853
 854 static int
 855 skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
 856 {
 857         struct dram_info *dram_info = &dev_priv->dram_info;
 858         struct dram_channel_info ch0 = {}, ch1 = {};
 859         u32 val;
 860         int ret;
 861
 862         val = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
 863         ret = skl_dram_get_channel_info(dev_priv, &ch0, 0, val);
 864         if (ret == 0)
 865                 dram_info->num_channels++;
 866
 867         val = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
 868         ret = skl_dram_get_channel_info(dev_priv, &ch1, 1, val);
 869         if (ret == 0)
 870                 dram_info->num_channels++;
 871
 872         if (dram_info->num_channels == 0) {
 873                 DRM_INFO("Number of memory channels is zero\n");
 874                 return -EINVAL;
 875         }
 876
 877         /*
 878          * If any of the channel is single rank channel, worst case output
 879          * will be same as if single rank memory, so consider single rank
 880          * memory.
 881          */
 882         if (ch0.ranks == 1 || ch1.ranks == 1)
 883                 dram_info->ranks = 1;
 884         else
 885                 dram_info->ranks = max(ch0.ranks, ch1.ranks);
 886
 887         if (dram_info->ranks == 0) {
 888                 DRM_INFO("couldn't get memory rank information\n");
 889                 return -EINVAL;
 890         }
 891
 892         dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
 893
 894         dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1);
 895
 896         DRM_DEBUG_KMS("Memory configuration is symmetric? %s\n",
 897                       yesno(dram_info->symmetric_memory));
 898         return 0;
 899 }
 900
 901 static enum intel_dram_type
 902 skl_get_dram_type(struct drm_i915_private *dev_priv)
 903 {
 904         u32 val;
 905
 906         val = I915_READ(SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
 907
 908         switch (val & SKL_DRAM_DDR_TYPE_MASK) {
 909         case SKL_DRAM_DDR_TYPE_DDR3:
 910                 return INTEL_DRAM_DDR3;
 911         case SKL_DRAM_DDR_TYPE_DDR4:
 912                 return INTEL_DRAM_DDR4;
 913         case SKL_DRAM_DDR_TYPE_LPDDR3:
 914                 return INTEL_DRAM_LPDDR3;
 915         case SKL_DRAM_DDR_TYPE_LPDDR4:
 916                 return INTEL_DRAM_LPDDR4;
 917         default:
 918                 MISSING_CASE(val);
 919                 return INTEL_DRAM_UNKNOWN;
 920         }
 921 }
 922
 923 static int
 924 skl_get_dram_info(struct drm_i915_private *dev_priv)
 925 {
 926         struct dram_info *dram_info = &dev_priv->dram_info;
 927         u32 mem_freq_khz, val;
 928         int ret;
 929
 930         dram_info->type = skl_get_dram_type(dev_priv);
 931         DRM_DEBUG_KMS("DRAM type: %s\n", intel_dram_type_str(dram_info->type));
 932
 933         ret = skl_dram_get_channels_info(dev_priv);
 934         if (ret)
 935                 return ret;
 936
 937         val = I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
 938         mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
 939                                     SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
 940
 941         dram_info->bandwidth_kbps = dram_info->num_channels *
 942                                                         mem_freq_khz * 8;
 943
 944         if (dram_info->bandwidth_kbps == 0) {
 945                 DRM_INFO("Couldn't get system memory bandwidth\n");
 946                 return -EINVAL;
 947         }
 948
 949         dram_info->valid = true;
 950         return 0;
 951 }
 952
 953 /* Returns Gb per DRAM device */
 954 static int bxt_get_dimm_size(u32 val)
 955 {
 956         switch (val & BXT_DRAM_SIZE_MASK) {
 957         case BXT_DRAM_SIZE_4GBIT:
 958                 return 4;
 959         case BXT_DRAM_SIZE_6GBIT:
 960                 return 6;
 961         case BXT_DRAM_SIZE_8GBIT:
 962                 return 8;
 963         case BXT_DRAM_SIZE_12GBIT:
 964                 return 12;
 965         case BXT_DRAM_SIZE_16GBIT:
 966                 return 16;
 967         default:
 968                 MISSING_CASE(val);
 969                 return 0;
 970         }
 971 }
 972
 973 static int bxt_get_dimm_width(u32 val)
 974 {
 975         if (!bxt_get_dimm_size(val))
 976                 return 0;
 977
 978         val = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
 979
 980         return 8 << val;
 981 }
 982
 983 static int bxt_get_dimm_ranks(u32 val)
 984 {
 985         if (!bxt_get_dimm_size(val))
 986                 return 0;
 987
 988         switch (val & BXT_DRAM_RANK_MASK) {
 989         case BXT_DRAM_RANK_SINGLE:
 990                 return 1;
 991         case BXT_DRAM_RANK_DUAL:
 992                 return 2;
 993         default:
 994                 MISSING_CASE(val);
 995                 return 0;
 996         }
 997 }
 998
 999 static enum intel_dram_type bxt_get_dimm_type(u32 val)
1000 {
1001         if (!bxt_get_dimm_size(val))
1002                 return INTEL_DRAM_UNKNOWN;
1003
1004         switch (val & BXT_DRAM_TYPE_MASK) {
1005         case BXT_DRAM_TYPE_DDR3:
1006                 return INTEL_DRAM_DDR3;
1007         case BXT_DRAM_TYPE_LPDDR3:
1008                 return INTEL_DRAM_LPDDR3;
1009         case BXT_DRAM_TYPE_DDR4:
1010                 return INTEL_DRAM_DDR4;
1011         case BXT_DRAM_TYPE_LPDDR4:
1012                 return INTEL_DRAM_LPDDR4;
1013         default:
1014                 MISSING_CASE(val);
1015                 return INTEL_DRAM_UNKNOWN;
1016         }
1017 }
1018
1019 static void bxt_get_dimm_info(struct dram_dimm_info *dimm,
1020                               u32 val)
1021 {
1022         dimm->width = bxt_get_dimm_width(val);
1023         dimm->ranks = bxt_get_dimm_ranks(val);
1024
1025         /*
1026          * Size in register is Gb per DRAM device. Convert to total
1027          * GB to match the way we report this for non-LP platforms.
1028          */
1029         dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm) / 8;
1030 }
1031
1032 static int
1033 bxt_get_dram_info(struct drm_i915_private *dev_priv)
1034 {
1035         struct dram_info *dram_info = &dev_priv->dram_info;
1036         u32 dram_channels;
1037         u32 mem_freq_khz, val;
1038         u8 num_active_channels;
1039         int i;
1040
1041         val = I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0);
1042         mem_freq_khz = DIV_ROUND_UP((val & BXT_REQ_DATA_MASK) *
1043                                     BXT_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
1044
1045         dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;
1046         num_active_channels = hweight32(dram_channels);
1047
1048         /* Each active bit represents 4-byte channel */
1049         dram_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4);
1050
1051         if (dram_info->bandwidth_kbps == 0) {
1052                 DRM_INFO("Couldn't get system memory bandwidth\n");
1053                 return -EINVAL;
1054         }
1055
1056         /*
1057          * Now read each DUNIT8/9/10/11 to check the rank of each dimms.
1058          */
1059         for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) {
1060                 struct dram_dimm_info dimm;
1061                 enum intel_dram_type type;
1062
1063                 val = I915_READ(BXT_D_CR_DRP0_DUNIT(i));
1064                 if (val == 0xFFFFFFFF)
1065                         continue;
1066
1067                 dram_info->num_channels++;
1068
1069                 bxt_get_dimm_info(&dimm, val);
1070                 type = bxt_get_dimm_type(val);
1071
1072                 WARN_ON(type != INTEL_DRAM_UNKNOWN &&
1073                         dram_info->type != INTEL_DRAM_UNKNOWN &&
1074                         dram_info->type != type);
1075
1076                 DRM_DEBUG_KMS("CH%u DIMM size: %u GB, width: X%u, ranks: %u, type: %s\n",
1077                               i - BXT_D_CR_DRP0_DUNIT_START,
1078                               dimm.size, dimm.width, dimm.ranks,
1079                               intel_dram_type_str(type));
1080
1081                 /*
1082                  * If any of the channel is single rank channel,
1083                  * worst case output will be same as if single rank
1084                  * memory, so consider single rank memory.
1085                  */
1086                 if (dram_info->ranks == 0)
1087                         dram_info->ranks = dimm.ranks;
1088                 else if (dimm.ranks == 1)
1089                         dram_info->ranks = 1;
1090
1091                 if (type != INTEL_DRAM_UNKNOWN)
1092                         dram_info->type = type;
1093         }
1094
1095         if (dram_info->type == INTEL_DRAM_UNKNOWN ||
1096             dram_info->ranks == 0) {
1097                 DRM_INFO("couldn't get memory information\n");
1098                 return -EINVAL;
1099         }
1100
1101         dram_info->valid = true;
1102         return 0;
1103 }
1104
1105 static void
1106 intel_get_dram_info(struct drm_i915_private *dev_priv)
1107 {
1108         struct dram_info *dram_info = &dev_priv->dram_info;
1109         int ret;
1110
1111         /*
1112          * Assume 16Gb DIMMs are present until proven otherwise.
1113          * This is only used for the level 0 watermark latency
1114          * w/a which does not apply to bxt/glk.
1115          */
1116         dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv);
1117
1118         if (INTEL_GEN(dev_priv) < 9)
1119                 return;
1120
1121         if (IS_GEN9_LP(dev_priv))
1122                 ret = bxt_get_dram_info(dev_priv);
1123         else
1124                 ret = skl_get_dram_info(dev_priv);
1125         if (ret)
1126                 return;
1127
1128         DRM_DEBUG_KMS("DRAM bandwidth: %u kBps, channels: %u\n",
1129                       dram_info->bandwidth_kbps,
1130                       dram_info->num_channels);
1131
1132         DRM_DEBUG_KMS("DRAM ranks: %u, 16Gb DIMMs: %s\n",
1133                       dram_info->ranks, yesno(dram_info->is_16gb_dimm));
1134 }
1135
1136 static u32 gen9_edram_size_mb(struct drm_i915_private *dev_priv, u32 cap)
1137 {
1138         const unsigned int ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
1139         const unsigned int sets[4] = { 1, 1, 2, 2 };
1140
1141         return EDRAM_NUM_BANKS(cap) *
1142                 ways[EDRAM_WAYS_IDX(cap)] *
1143                 sets[EDRAM_SETS_IDX(cap)];
1144 }
1145
1146 static void edram_detect(struct drm_i915_private *dev_priv)
1147 {
1148         u32 edram_cap = 0;
1149
1150         if (!(IS_HASWELL(dev_priv) ||
1151               IS_BROADWELL(dev_priv) ||
1152               INTEL_GEN(dev_priv) >= 9))
1153                 return;
1154
1155         edram_cap = __raw_uncore_read32(&dev_priv->uncore, HSW_EDRAM_CAP);
1156
1157         /* NB: We can't write IDICR yet because we don't have gt funcs set up */
1158
1159         if (!(edram_cap & EDRAM_ENABLED))
1160                 return;
1161
1162         /*
1163          * The needed capability bits for size calculation are not there with
1164          * pre gen9 so return 128MB always.
1165          */
1166         if (INTEL_GEN(dev_priv) < 9)
1167                 dev_priv->edram_size_mb = 128;
1168         else
1169                 dev_priv->edram_size_mb =
1170                         gen9_edram_size_mb(dev_priv, edram_cap);
1171
1172         dev_info(dev_priv->drm.dev,
1173                  "Found %uMB of eDRAM\n", dev_priv->edram_size_mb);
1174 }
1175
1176 /**
1177  * i915_driver_hw_probe - setup state requiring device access
1178  * @dev_priv: device private
1179  *
1180  * Setup state that requires accessing the device, but doesn't require
1181  * exposing the driver via kernel internal or userspace interfaces.
1182  */
1183 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
1184 {
1185         struct pci_dev *pdev = dev_priv->drm.pdev;
1186         int ret;
1187
1188         if (i915_inject_probe_failure(dev_priv))
1189                 return -ENODEV;
1190
1191         intel_device_info_runtime_init(dev_priv);
1192
1193         if (HAS_PPGTT(dev_priv)) {
1194                 if (intel_vgpu_active(dev_priv) &&
1195                     !intel_vgpu_has_full_ppgtt(dev_priv)) {
1196                         i915_report_error(dev_priv,
1197                                           "incompatible vGPU found, support for isolated ppGTT required\n");
1198                         return -ENXIO;
1199                 }
1200         }
1201
1202         if (HAS_EXECLISTS(dev_priv)) {
1203                 /*
1204                  * Older GVT emulation depends upon intercepting CSB mmio,
1205                  * which we no longer use, preferring to use the HWSP cache
1206                  * instead.
1207                  */
1208                 if (intel_vgpu_active(dev_priv) &&
1209                     !intel_vgpu_has_hwsp_emulation(dev_priv)) {
1210                         i915_report_error(dev_priv,
1211                                           "old vGPU host found, support for HWSP emulation required\n");
1212                         return -ENXIO;
1213                 }
1214         }
1215
1216         intel_sanitize_options(dev_priv);
1217
1218         /* needs to be done before ggtt probe */
1219         edram_detect(dev_priv);
1220
1221         i915_perf_init(dev_priv);
1222
1223         ret = i915_ggtt_probe_hw(dev_priv);
1224         if (ret)
1225                 goto err_perf;
1226
1227         ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "inteldrmfb");
1228         if (ret)
1229                 goto err_ggtt;
1230
1231         ret = i915_ggtt_init_hw(dev_priv);
1232         if (ret)
1233                 goto err_ggtt;
1234
1235         intel_gt_init_hw(dev_priv);
1236
1237         ret = i915_ggtt_enable_hw(dev_priv);
1238         if (ret) {
1239                 DRM_ERROR("failed to enable GGTT\n");
1240                 goto err_ggtt;
1241         }
1242
1243         pci_set_master(pdev);
1244
1245         /*
1246          * We don't have a max segment size, so set it to the max so sg's
1247          * debugging layer doesn't complain
1248          */
1249         dma_set_max_seg_size(&pdev->dev, UINT_MAX);
1250
1251         /* overlay on gen2 is broken and can't address above 1G */
1252         if (IS_GEN(dev_priv, 2)) {
1253                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1254                 if (ret) {
1255                         DRM_ERROR("failed to set DMA mask\n");
1256
1257                         goto err_ggtt;
1258                 }
1259         }
1260
1261         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1262          * using 32bit addressing, overwriting memory if HWS is located
1263          * above 4GB.
1264          *
1265          * The documentation also mentions an issue with undefined
1266          * behaviour if any general state is accessed within a page above 4GB,
1267          * which also needs to be handled carefully.
1268          */
1269         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1270                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1271
1272                 if (ret) {
1273                         DRM_ERROR("failed to set DMA mask\n");
1274
1275                         goto err_ggtt;
1276                 }
1277         }
1278
1279         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1280                            PM_QOS_DEFAULT_VALUE);
1281
1282         /* BIOS often leaves RC6 enabled, but disable it for hw init */
1283         intel_sanitize_gt_powersave(dev_priv);
1284
1285         intel_gt_init_workarounds(dev_priv);
1286
1287         /* On the 945G/GM, the chipset reports the MSI capability on the
1288          * integrated graphics even though the support isn't actually there
1289          * according to the published specs.  It doesn't appear to function
1290          * correctly in testing on 945G.
1291          * This may be a side effect of MSI having been made available for PEG
1292          * and the registers being closely associated.
1293          *
1294          * According to chipset errata, on the 965GM, MSI interrupts may
1295          * be lost or delayed, and was defeatured. MSI interrupts seem to
1296          * get lost on g4x as well, and interrupt delivery seems to stay
1297          * properly dead afterwards. So we'll just disable them for all
1298          * pre-gen5 chipsets.
1299          *
1300          * dp aux and gmbus irq on gen4 seems to be able to generate legacy
1301          * interrupts even when in MSI mode. This results in spurious
1302          * interrupt warnings if the legacy irq no. is shared with another
1303          * device. The kernel then disables that interrupt source and so
1304          * prevents the other device from working properly.
1305          */
1306         if (INTEL_GEN(dev_priv) >= 5) {
1307                 if (pci_enable_msi(pdev) < 0)
1308                         DRM_DEBUG_DRIVER("can't enable MSI");
1309         }
1310
1311         ret = intel_gvt_init(dev_priv);
1312         if (ret)
1313                 goto err_msi;
1314
1315         intel_opregion_setup(dev_priv);
1316         /*
1317          * Fill the dram structure to get the system raw bandwidth and
1318          * dram info. This will be used for memory latency calculation.
1319          */
1320         intel_get_dram_info(dev_priv);
1321
1322         intel_bw_init_hw(dev_priv);
1323
1324         return 0;
1325
1326 err_msi:
1327         if (pdev->msi_enabled)
1328                 pci_disable_msi(pdev);
1329         pm_qos_remove_request(&dev_priv->pm_qos);
1330 err_ggtt:
1331         i915_ggtt_driver_release(dev_priv);
1332 err_perf:
1333         i915_perf_fini(dev_priv);
1334         return ret;
1335 }
1336
1337 /**
1338  * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
1339  * @dev_priv: device private
1340  */
1341 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
1342 {
1343         struct pci_dev *pdev = dev_priv->drm.pdev;
1344
1345         i915_perf_fini(dev_priv);
1346
1347         if (pdev->msi_enabled)
1348                 pci_disable_msi(pdev);
1349
1350         pm_qos_remove_request(&dev_priv->pm_qos);
1351 }
1352
1353 /**
1354  * i915_driver_register - register the driver with the rest of the system
1355  * @dev_priv: device private
1356  *
1357  * Perform any steps necessary to make the driver available via kernel
1358  * internal or userspace interfaces.
1359  */
1360 static void i915_driver_register(struct drm_i915_private *dev_priv)
1361 {
1362         struct drm_device *dev = &dev_priv->drm;
1363
1364         i915_gem_driver_register(dev_priv);
1365         i915_pmu_register(dev_priv);
1366
1367         /*
1368          * Notify a valid surface after modesetting,
1369          * when running inside a VM.
1370          */
1371         if (intel_vgpu_active(dev_priv))
1372                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1373
1374         /* Reveal our presence to userspace */
1375         if (drm_dev_register(dev, 0) == 0) {
1376                 i915_debugfs_register(dev_priv);
1377                 i915_setup_sysfs(dev_priv);
1378
1379                 /* Depends on sysfs having been initialized */
1380                 i915_perf_register(dev_priv);
1381         } else
1382                 DRM_ERROR("Failed to register driver for userspace access!\n");
1383
1384         if (HAS_DISPLAY(dev_priv)) {
1385                 /* Must be done after probing outputs */
1386                 intel_opregion_register(dev_priv);
1387                 acpi_video_register();
1388         }
1389
1390         if (IS_GEN(dev_priv, 5))
1391                 intel_gpu_ips_init(dev_priv);
1392
1393         intel_audio_init(dev_priv);
1394
1395         /*
1396          * Some ports require correctly set-up hpd registers for detection to
1397          * work properly (leading to ghost connected connector status), e.g. VGA
1398          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1399          * irqs are fully enabled. We do it last so that the async config
1400          * cannot run before the connectors are registered.
1401          */
1402         intel_fbdev_initial_config_async(dev);
1403
1404         /*
1405          * We need to coordinate the hotplugs with the asynchronous fbdev
1406          * configuration, for which we use the fbdev->async_cookie.
1407          */
1408         if (HAS_DISPLAY(dev_priv))
1409                 drm_kms_helper_poll_init(dev);
1410
1411         intel_power_domains_enable(dev_priv);
1412         intel_runtime_pm_enable(&dev_priv->runtime_pm);
1413 }
1414
1415 /**
1416  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1417  * @dev_priv: device private
1418  */
1419 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1420 {
1421         intel_runtime_pm_disable(&dev_priv->runtime_pm);
1422         intel_power_domains_disable(dev_priv);
1423
1424         intel_fbdev_unregister(dev_priv);
1425         intel_audio_deinit(dev_priv);
1426
1427         /*
1428          * After flushing the fbdev (incl. a late async config which will
1429          * have delayed queuing of a hotplug event), then flush the hotplug
1430          * events.
1431          */
1432         drm_kms_helper_poll_fini(&dev_priv->drm);
1433
1434         intel_gpu_ips_teardown();
1435         acpi_video_unregister();
1436         intel_opregion_unregister(dev_priv);
1437
1438         i915_perf_unregister(dev_priv);
1439         i915_pmu_unregister(dev_priv);
1440
1441         i915_teardown_sysfs(dev_priv);
1442         drm_dev_unplug(&dev_priv->drm);
1443
1444         i915_gem_driver_unregister(dev_priv);
1445 }
1446
1447 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
1448 {
1449         if (drm_debug & DRM_UT_DRIVER) {
1450                 struct drm_printer p = drm_debug_printer("i915 device info:");
1451
1452                 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
1453                            INTEL_DEVID(dev_priv),
1454                            INTEL_REVID(dev_priv),
1455                            intel_platform_name(INTEL_INFO(dev_priv)->platform),
1456                            intel_subplatform(RUNTIME_INFO(dev_priv),
1457                                              INTEL_INFO(dev_priv)->platform),
1458                            INTEL_GEN(dev_priv));
1459
1460                 intel_device_info_dump_flags(INTEL_INFO(dev_priv), &p);
1461                 intel_device_info_dump_runtime(RUNTIME_INFO(dev_priv), &p);
1462         }
1463
1464         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1465                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1466         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1467                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1468         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
1469                 DRM_INFO("DRM_I915_DEBUG_RUNTIME_PM enabled\n");
1470 }
1471
1472 static struct drm_i915_private *
1473 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
1474 {
1475         const struct intel_device_info *match_info =
1476                 (struct intel_device_info *)ent->driver_data;
1477         struct intel_device_info *device_info;
1478         struct drm_i915_private *i915;
1479         int err;
1480
1481         i915 = kzalloc(sizeof(*i915), GFP_KERNEL);
1482         if (!i915)
1483                 return ERR_PTR(-ENOMEM);
1484
1485         err = drm_dev_init(&i915->drm, &driver, &pdev->dev);
1486         if (err) {
1487                 kfree(i915);
1488                 return ERR_PTR(err);
1489         }
1490
1491         i915->drm.dev_private = i915;
1492
1493         i915->drm.pdev = pdev;
1494         pci_set_drvdata(pdev, i915);
1495
1496         /* Setup the write-once "constant" device info */
1497         device_info = mkwrite_device_info(i915);
1498         memcpy(device_info, match_info, sizeof(*device_info));
1499         RUNTIME_INFO(i915)->device_id = pdev->device;
1500
1501         BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
1502
1503         return i915;
1504 }
1505
1506 static void i915_driver_destroy(struct drm_i915_private *i915)
1507 {
1508         struct pci_dev *pdev = i915->drm.pdev;
1509
1510         drm_dev_fini(&i915->drm);
1511         kfree(i915);
1512
1513         /* And make sure we never chase our dangling pointer from pci_dev */
1514         pci_set_drvdata(pdev, NULL);
1515 }
1516
1517 /**
1518  * i915_driver_probe - setup chip and create an initial config
1519  * @pdev: PCI device
1520  * @ent: matching PCI ID entry
1521  *
1522  * The driver probe routine has to do several things:
1523  *   - drive output discovery via intel_modeset_init()
1524  *   - initialize the memory manager
1525  *   - allocate initial config memory
1526  *   - setup the DRM framebuffer with the allocated memory
1527  */
1528 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1529 {
1530         const struct intel_device_info *match_info =
1531                 (struct intel_device_info *)ent->driver_data;
1532         struct drm_i915_private *dev_priv;
1533         int ret;
1534
1535         dev_priv = i915_driver_create(pdev, ent);
1536         if (IS_ERR(dev_priv))
1537                 return PTR_ERR(dev_priv);
1538
1539         /* Disable nuclear pageflip by default on pre-ILK */
1540         if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1541                 dev_priv->drm.driver_features &= ~DRIVER_ATOMIC;
1542
1543         ret = pci_enable_device(pdev);
1544         if (ret)
1545                 goto out_fini;
1546
1547         ret = i915_driver_early_probe(dev_priv);
1548         if (ret < 0)
1549                 goto out_pci_disable;
1550
1551         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1552
1553         i915_detect_vgpu(dev_priv);
1554
1555         ret = i915_driver_mmio_probe(dev_priv);
1556         if (ret < 0)
1557                 goto out_runtime_pm_put;
1558
1559         ret = i915_driver_hw_probe(dev_priv);
1560         if (ret < 0)
1561                 goto out_cleanup_mmio;
1562
1563         ret = i915_driver_modeset_probe(&dev_priv->drm);
1564         if (ret < 0)
1565                 goto out_cleanup_hw;
1566
1567         i915_driver_register(dev_priv);
1568
1569         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1570
1571         i915_welcome_messages(dev_priv);
1572
1573         return 0;
1574
1575 out_cleanup_hw:
1576         i915_driver_hw_remove(dev_priv);
1577         i915_ggtt_driver_release(dev_priv);
1578
1579         /* Paranoia: make sure we have disabled everything before we exit. */
1580         intel_sanitize_gt_powersave(dev_priv);
1581 out_cleanup_mmio:
1582         i915_driver_mmio_release(dev_priv);
1583 out_runtime_pm_put:
1584         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1585         i915_driver_late_release(dev_priv);
1586 out_pci_disable:
1587         pci_disable_device(pdev);
1588 out_fini:
1589         i915_probe_error(dev_priv, "Device initialization failed (%d)\n", ret);
1590         i915_driver_destroy(dev_priv);
1591         return ret;
1592 }
1593
1594 void i915_driver_remove(struct drm_i915_private *i915)
1595 {
1596         struct pci_dev *pdev = i915->drm.pdev;
1597
1598         disable_rpm_wakeref_asserts(&i915->runtime_pm);
1599
1600         i915_driver_unregister(i915);
1601
1602         /*
1603          * After unregistering the device to prevent any new users, cancel
1604          * all in-flight requests so that we can quickly unbind the active
1605          * resources.
1606          */
1607         intel_gt_set_wedged(&i915->gt);
1608
1609         /* Flush any external code that still may be under the RCU lock */
1610         synchronize_rcu();
1611
1612         i915_gem_suspend(i915);
1613
1614         drm_atomic_helper_shutdown(&i915->drm);
1615
1616         intel_gvt_driver_remove(i915);
1617
1618         intel_modeset_driver_remove(&i915->drm);
1619
1620         intel_bios_driver_remove(i915);
1621
1622         vga_switcheroo_unregister_client(pdev);
1623         vga_client_register(pdev, NULL, NULL, NULL);
1624
1625         intel_csr_ucode_fini(i915);
1626
1627         /* Free error state after interrupts are fully disabled. */
1628         cancel_delayed_work_sync(&i915->gt.hangcheck.work);
1629         i915_reset_error_state(i915);
1630
1631         i915_gem_driver_remove(i915);
1632
1633         intel_power_domains_driver_remove(i915);
1634
1635         i915_driver_hw_remove(i915);
1636
1637         enable_rpm_wakeref_asserts(&i915->runtime_pm);
1638 }
1639
1640 static void i915_driver_release(struct drm_device *dev)
1641 {
1642         struct drm_i915_private *dev_priv = to_i915(dev);
1643         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1644
1645         disable_rpm_wakeref_asserts(rpm);
1646
1647         i915_gem_driver_release(dev_priv);
1648
1649         i915_ggtt_driver_release(dev_priv);
1650
1651         /* Paranoia: make sure we have disabled everything before we exit. */
1652         intel_sanitize_gt_powersave(dev_priv);
1653
1654         i915_driver_mmio_release(dev_priv);
1655
1656         enable_rpm_wakeref_asserts(rpm);
1657         intel_runtime_pm_driver_release(rpm);
1658
1659         i915_driver_late_release(dev_priv);
1660         i915_driver_destroy(dev_priv);
1661 }
1662
1663 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1664 {
1665         struct drm_i915_private *i915 = to_i915(dev);
1666         int ret;
1667
1668         ret = i915_gem_open(i915, file);
1669         if (ret)
1670                 return ret;
1671
1672         return 0;
1673 }
1674
1675 /**
1676  * i915_driver_lastclose - clean up after all DRM clients have exited
1677  * @dev: DRM device
1678  *
1679  * Take care of cleaning up after all DRM clients have exited.  In the
1680  * mode setting case, we want to restore the kernel's initial mode (just
1681  * in case the last client left us in a bad state).
1682  *
1683  * Additionally, in the non-mode setting case, we'll tear down the GTT
1684  * and DMA structures, since the kernel won't be using them, and clea
1685  * up any GEM state.
1686  */
1687 static void i915_driver_lastclose(struct drm_device *dev)
1688 {
1689         intel_fbdev_restore_mode(dev);
1690         vga_switcheroo_process_delayed_switch();
1691 }
1692
1693 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1694 {
1695         struct drm_i915_file_private *file_priv = file->driver_priv;
1696
1697         mutex_lock(&dev->struct_mutex);
1698         i915_gem_context_close(file);
1699         i915_gem_release(dev, file);
1700         mutex_unlock(&dev->struct_mutex);
1701
1702         kfree(file_priv);
1703
1704         /* Catch up with all the deferred frees from "this" client */
1705         i915_gem_flush_free_objects(to_i915(dev));
1706 }
1707
1708 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1709 {
1710         struct drm_device *dev = &dev_priv->drm;
1711         struct intel_encoder *encoder;
1712
1713         drm_modeset_lock_all(dev);
1714         for_each_intel_encoder(dev, encoder)
1715                 if (encoder->suspend)
1716                         encoder->suspend(encoder);
1717         drm_modeset_unlock_all(dev);
1718 }
1719
1720 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1721                               bool rpm_resume);
1722 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1723
1724 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1725 {
1726 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1727         if (acpi_target_system_state() < ACPI_STATE_S3)
1728                 return true;
1729 #endif
1730         return false;
1731 }
1732
1733 static int i915_drm_prepare(struct drm_device *dev)
1734 {
1735         struct drm_i915_private *i915 = to_i915(dev);
1736
1737         /*
1738          * NB intel_display_suspend() may issue new requests after we've
1739          * ostensibly marked the GPU as ready-to-sleep here. We need to
1740          * split out that work and pull it forward so that after point,
1741          * the GPU is not woken again.
1742          */
1743         i915_gem_suspend(i915);
1744
1745         return 0;
1746 }
1747
1748 static int i915_drm_suspend(struct drm_device *dev)
1749 {
1750         struct drm_i915_private *dev_priv = to_i915(dev);
1751         struct pci_dev *pdev = dev_priv->drm.pdev;
1752         pci_power_t opregion_target_state;
1753
1754         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1755
1756         /* We do a lot of poking in a lot of registers, make sure they work
1757          * properly. */
1758         intel_power_domains_disable(dev_priv);
1759
1760         drm_kms_helper_poll_disable(dev);
1761
1762         pci_save_state(pdev);
1763
1764         intel_display_suspend(dev);
1765
1766         intel_dp_mst_suspend(dev_priv);
1767
1768         intel_runtime_pm_disable_interrupts(dev_priv);
1769         intel_hpd_cancel_work(dev_priv);
1770
1771         intel_suspend_encoders(dev_priv);
1772
1773         intel_suspend_hw(dev_priv);
1774
1775         i915_gem_suspend_gtt_mappings(dev_priv);
1776
1777         i915_save_state(dev_priv);
1778
1779         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1780         intel_opregion_suspend(dev_priv, opregion_target_state);
1781
1782         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1783
1784         dev_priv->suspend_count++;
1785
1786         intel_csr_ucode_suspend(dev_priv);
1787
1788         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1789
1790         return 0;
1791 }
1792
1793 static enum i915_drm_suspend_mode
1794 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1795 {
1796         if (hibernate)
1797                 return I915_DRM_SUSPEND_HIBERNATE;
1798
1799         if (suspend_to_idle(dev_priv))
1800                 return I915_DRM_SUSPEND_IDLE;
1801
1802         return I915_DRM_SUSPEND_MEM;
1803 }
1804
1805 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1806 {
1807         struct drm_i915_private *dev_priv = to_i915(dev);
1808         struct pci_dev *pdev = dev_priv->drm.pdev;
1809         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1810         int ret = 0;
1811
1812         disable_rpm_wakeref_asserts(rpm);
1813
1814         i915_gem_suspend_late(dev_priv);
1815
1816         intel_uncore_suspend(&dev_priv->uncore);
1817
1818         intel_power_domains_suspend(dev_priv,
1819                                     get_suspend_mode(dev_priv, hibernation));
1820
1821         intel_display_power_suspend_late(dev_priv);
1822
1823         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1824                 ret = vlv_suspend_complete(dev_priv);
1825
1826         if (ret) {
1827                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1828                 intel_power_domains_resume(dev_priv);
1829
1830                 goto out;
1831         }
1832
1833         pci_disable_device(pdev);
1834         /*
1835          * During hibernation on some platforms the BIOS may try to access
1836          * the device even though it's already in D3 and hang the machine. So
1837          * leave the device in D0 on those platforms and hope the BIOS will
1838          * power down the device properly. The issue was seen on multiple old
1839          * GENs with different BIOS vendors, so having an explicit blacklist
1840          * is inpractical; apply the workaround on everything pre GEN6. The
1841          * platforms where the issue was seen:
1842          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1843          * Fujitsu FSC S7110
1844          * Acer Aspire 1830T
1845          */
1846         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1847                 pci_set_power_state(pdev, PCI_D3hot);
1848
1849 out:
1850         enable_rpm_wakeref_asserts(rpm);
1851         if (!dev_priv->uncore.user_forcewake_count)
1852                 intel_runtime_pm_driver_release(rpm);
1853
1854         return ret;
1855 }
1856
1857 static int
1858 i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state)
1859 {
1860         int error;
1861
1862         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1863                          state.event != PM_EVENT_FREEZE))
1864                 return -EINVAL;
1865
1866         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1867                 return 0;
1868
1869         error = i915_drm_suspend(&i915->drm);
1870         if (error)
1871                 return error;
1872
1873         return i915_drm_suspend_late(&i915->drm, false);
1874 }
1875
1876 static int i915_drm_resume(struct drm_device *dev)
1877 {
1878         struct drm_i915_private *dev_priv = to_i915(dev);
1879         int ret;
1880
1881         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1882         intel_sanitize_gt_powersave(dev_priv);
1883
1884         i915_gem_sanitize(dev_priv);
1885
1886         ret = i915_ggtt_enable_hw(dev_priv);
1887         if (ret)
1888                 DRM_ERROR("failed to re-enable GGTT\n");
1889
1890         intel_csr_ucode_resume(dev_priv);
1891
1892         i915_restore_state(dev_priv);
1893         intel_pps_unlock_regs_wa(dev_priv);
1894
1895         intel_init_pch_refclk(dev_priv);
1896
1897         /*
1898          * Interrupts have to be enabled before any batches are run. If not the
1899          * GPU will hang. i915_gem_init_hw() will initiate batches to
1900          * update/restore the context.
1901          *
1902          * drm_mode_config_reset() needs AUX interrupts.
1903          *
1904          * Modeset enabling in intel_modeset_init_hw() also needs working
1905          * interrupts.
1906          */
1907         intel_runtime_pm_enable_interrupts(dev_priv);
1908
1909         drm_mode_config_reset(dev);
1910
1911         i915_gem_resume(dev_priv);
1912
1913         intel_modeset_init_hw(dev);
1914         intel_init_clock_gating(dev_priv);
1915
1916         spin_lock_irq(&dev_priv->irq_lock);
1917         if (dev_priv->display.hpd_irq_setup)
1918                 dev_priv->display.hpd_irq_setup(dev_priv);
1919         spin_unlock_irq(&dev_priv->irq_lock);
1920
1921         intel_dp_mst_resume(dev_priv);
1922
1923         intel_display_resume(dev);
1924
1925         drm_kms_helper_poll_enable(dev);
1926
1927         /*
1928          * ... but also need to make sure that hotplug processing
1929          * doesn't cause havoc. Like in the driver load code we don't
1930          * bother with the tiny race here where we might lose hotplug
1931          * notifications.
1932          * */
1933         intel_hpd_init(dev_priv);
1934
1935         intel_opregion_resume(dev_priv);
1936
1937         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1938
1939         intel_power_domains_enable(dev_priv);
1940
1941         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1942
1943         return 0;
1944 }
1945
1946 static int i915_drm_resume_early(struct drm_device *dev)
1947 {
1948         struct drm_i915_private *dev_priv = to_i915(dev);
1949         struct pci_dev *pdev = dev_priv->drm.pdev;
1950         int ret;
1951
1952         /*
1953          * We have a resume ordering issue with the snd-hda driver also
1954          * requiring our device to be power up. Due to the lack of a
1955          * parent/child relationship we currently solve this with an early
1956          * resume hook.
1957          *
1958          * FIXME: This should be solved with a special hdmi sink device or
1959          * similar so that power domains can be employed.
1960          */
1961
1962         /*
1963          * Note that we need to set the power state explicitly, since we
1964          * powered off the device during freeze and the PCI core won't power
1965          * it back up for us during thaw. Powering off the device during
1966          * freeze is not a hard requirement though, and during the
1967          * suspend/resume phases the PCI core makes sure we get here with the
1968          * device powered on. So in case we change our freeze logic and keep
1969          * the device powered we can also remove the following set power state
1970          * call.
1971          */
1972         ret = pci_set_power_state(pdev, PCI_D0);
1973         if (ret) {
1974                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1975                 return ret;
1976         }
1977
1978         /*
1979          * Note that pci_enable_device() first enables any parent bridge
1980          * device and only then sets the power state for this device. The
1981          * bridge enabling is a nop though, since bridge devices are resumed
1982          * first. The order of enabling power and enabling the device is
1983          * imposed by the PCI core as described above, so here we preserve the
1984          * same order for the freeze/thaw phases.
1985          *
1986          * TODO: eventually we should remove pci_disable_device() /
1987          * pci_enable_enable_device() from suspend/resume. Due to how they
1988          * depend on the device enable refcount we can't anyway depend on them
1989          * disabling/enabling the device.
1990          */
1991         if (pci_enable_device(pdev))
1992                 return -EIO;
1993
1994         pci_set_master(pdev);
1995
1996         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1997
1998         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1999                 ret = vlv_resume_prepare(dev_priv, false);
2000         if (ret)
2001                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
2002                           ret);
2003
2004         intel_uncore_resume_early(&dev_priv->uncore);
2005
2006         intel_gt_check_and_clear_faults(&dev_priv->gt);
2007
2008         intel_display_power_resume_early(dev_priv);
2009
2010         intel_sanitize_gt_powersave(dev_priv);
2011
2012         intel_power_domains_resume(dev_priv);
2013
2014         intel_gt_sanitize(&dev_priv->gt, true);
2015
2016         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2017
2018         return ret;
2019 }
2020
2021 static int i915_resume_switcheroo(struct drm_i915_private *i915)
2022 {
2023         int ret;
2024
2025         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2026                 return 0;
2027
2028         ret = i915_drm_resume_early(&i915->drm);
2029         if (ret)
2030                 return ret;
2031
2032         return i915_drm_resume(&i915->drm);
2033 }
2034
2035 static int i915_pm_prepare(struct device *kdev)
2036 {
2037         struct drm_i915_private *i915 = kdev_to_i915(kdev);
2038
2039         if (!i915) {
2040                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2041                 return -ENODEV;
2042         }
2043
2044         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2045                 return 0;
2046
2047         return i915_drm_prepare(&i915->drm);
2048 }
2049
2050 static int i915_pm_suspend(struct device *kdev)
2051 {
2052         struct drm_i915_private *i915 = kdev_to_i915(kdev);
2053
2054         if (!i915) {
2055                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2056                 return -ENODEV;
2057         }
2058
2059         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2060                 return 0;
2061
2062         return i915_drm_suspend(&i915->drm);
2063 }
2064
2065 static int i915_pm_suspend_late(struct device *kdev)
2066 {
2067         struct drm_i915_private *i915 = kdev_to_i915(kdev);
2068
2069         /*
2070          * We have a suspend ordering issue with the snd-hda driver also
2071          * requiring our device to be power up. Due to the lack of a
2072          * parent/child relationship we currently solve this with an late
2073          * suspend hook.
2074          *
2075          * FIXME: This should be solved with a special hdmi sink device or
2076          * similar so that power domains can be employed.
2077          */
2078         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2079                 return 0;
2080
2081         return i915_drm_suspend_late(&i915->drm, false);
2082 }
2083
2084 static int i915_pm_poweroff_late(struct device *kdev)
2085 {
2086         struct drm_i915_private *i915 = kdev_to_i915(kdev);
2087
2088         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2089                 return 0;
2090
2091         return i915_drm_suspend_late(&i915->drm, true);
2092 }
2093
2094 static int i915_pm_resume_early(struct device *kdev)
2095 {
2096         struct drm_i915_private *i915 = kdev_to_i915(kdev);
2097
2098         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2099                 return 0;
2100
2101         return i915_drm_resume_early(&i915->drm);
2102 }
2103
2104 static int i915_pm_resume(struct device *kdev)
2105 {
2106         struct drm_i915_private *i915 = kdev_to_i915(kdev);
2107
2108         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2109                 return 0;
2110
2111         return i915_drm_resume(&i915->drm);
2112 }
2113
2114 /* freeze: before creating the hibernation_image */
2115 static int i915_pm_freeze(struct device *kdev)
2116 {
2117         struct drm_i915_private *i915 = kdev_to_i915(kdev);
2118         int ret;
2119
2120         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
2121                 ret = i915_drm_suspend(&i915->drm);
2122                 if (ret)
2123                         return ret;
2124         }
2125
2126         ret = i915_gem_freeze(i915);
2127         if (ret)
2128                 return ret;
2129
2130         return 0;
2131 }
2132
2133 static int i915_pm_freeze_late(struct device *kdev)
2134 {
2135         struct drm_i915_private *i915 = kdev_to_i915(kdev);
2136         int ret;
2137
2138         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
2139                 ret = i915_drm_suspend_late(&i915->drm, true);
2140                 if (ret)
2141                         return ret;
2142         }
2143
2144         ret = i915_gem_freeze_late(i915);
2145         if (ret)
2146                 return ret;
2147
2148         return 0;
2149 }
2150
2151 /* thaw: called after creating the hibernation image, but before turning off. */
2152 static int i915_pm_thaw_early(struct device *kdev)
2153 {
2154         return i915_pm_resume_early(kdev);
2155 }
2156
2157 static int i915_pm_thaw(struct device *kdev)
2158 {
2159         return i915_pm_resume(kdev);
2160 }
2161
2162 /* restore: called after loading the hibernation image. */
2163 static int i915_pm_restore_early(struct device *kdev)
2164 {
2165         return i915_pm_resume_early(kdev);
2166 }
2167
2168 static int i915_pm_restore(struct device *kdev)
2169 {
2170         return i915_pm_resume(kdev);
2171 }
2172
2173 /*
2174  * Save all Gunit registers that may be lost after a D3 and a subsequent
2175  * S0i[R123] transition. The list of registers needing a save/restore is
2176  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2177  * registers in the following way:
2178  * - Driver: saved/restored by the driver
2179  * - Punit : saved/restored by the Punit firmware
2180  * - No, w/o marking: no need to save/restore, since the register is R/O or
2181  *                    used internally by the HW in a way that doesn't depend
2182  *                    keeping the content across a suspend/resume.
2183  * - Debug : used for debugging
2184  *
2185  * We save/restore all registers marked with 'Driver', with the following
2186  * exceptions:
2187  * - Registers out of use, including also registers marked with 'Debug'.
2188  *   These have no effect on the driver's operation, so we don't save/restore
2189  *   them to reduce the overhead.
2190  * - Registers that are fully setup by an initialization function called from
2191  *   the resume path. For example many clock gating and RPS/RC6 registers.
2192  * - Registers that provide the right functionality with their reset defaults.
2193  *
2194  * TODO: Except for registers that based on the above 3 criteria can be safely
2195  * ignored, we save/restore all others, practically treating the HW context as
2196  * a black-box for the driver. Further investigation is needed to reduce the
2197  * saved/restored registers even further, by following the same 3 criteria.
2198  */
2199 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2200 {
2201         struct vlv_s0ix_state *s = dev_priv->vlv_s0ix_state;
2202         int i;
2203
2204         if (!s)
2205                 return;
2206
2207         /* GAM 0x4000-0x4770 */
2208         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2209         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2210         s->arb_mode             = I915_READ(ARB_MODE);
2211         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2212         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2213
2214         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2215                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2216
2217         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2218         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2219
2220         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2221         s->ecochk               = I915_READ(GAM_ECOCHK);
2222         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2223         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2224
2225         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2226
2227         /* MBC 0x9024-0x91D0, 0x8500 */
2228         s->g3dctl               = I915_READ(VLV_G3DCTL);
2229         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2230         s->mbctl                = I915_READ(GEN6_MBCTL);
2231
2232         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2233         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2234         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2235         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2236         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2237         s->rstctl               = I915_READ(GEN6_RSTCTL);
2238         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2239
2240         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2241         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2242         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2243         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2244         s->ecobus               = I915_READ(ECOBUS);
2245         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2246         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2247         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2248         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2249         s->rcedata              = I915_READ(VLV_RCEDATA);
2250         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2251
2252         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2253         s->gt_imr               = I915_READ(GTIMR);
2254         s->gt_ier               = I915_READ(GTIER);
2255         s->pm_imr               = I915_READ(GEN6_PMIMR);
2256         s->pm_ier               = I915_READ(GEN6_PMIER);
2257
2258         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2259                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2260
2261         /* GT SA CZ domain, 0x100000-0x138124 */
2262         s->tilectl              = I915_READ(TILECTL);
2263         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2264         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2265         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2266         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2267
2268         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2269         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2270         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2271         s->pcbr                 = I915_READ(VLV_PCBR);
2272         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2273
2274         /*
2275          * Not saving any of:
2276          * DFT,         0x9800-0x9EC0
2277          * SARB,        0xB000-0xB1FC
2278          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2279          * PCI CFG
2280          */
2281 }
2282
2283 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2284 {
2285         struct vlv_s0ix_state *s = dev_priv->vlv_s0ix_state;
2286         u32 val;
2287         int i;
2288
2289         if (!s)
2290                 return;
2291
2292         /* GAM 0x4000-0x4770 */
2293         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2294         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2295         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2296         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2297         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2298
2299         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2300                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2301
2302         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2303         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2304
2305         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2306         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2307         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2308         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2309
2310         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2311
2312         /* MBC 0x9024-0x91D0, 0x8500 */
2313         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2314         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2315         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2316
2317         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2318         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2319         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2320         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2321         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2322         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2323         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2324
2325         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2326         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2327         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2328         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2329         I915_WRITE(ECOBUS,              s->ecobus);
2330         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2331         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2332         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2333         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2334         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2335         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2336
2337         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2338         I915_WRITE(GTIMR,               s->gt_imr);
2339         I915_WRITE(GTIER,               s->gt_ier);
2340         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2341         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2342
2343         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2344                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2345
2346         /* GT SA CZ domain, 0x100000-0x138124 */
2347         I915_WRITE(TILECTL,                     s->tilectl);
2348         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2349         /*
2350          * Preserve the GT allow wake and GFX force clock bit, they are not
2351          * be restored, as they are used to control the s0ix suspend/resume
2352          * sequence by the caller.
2353          */
2354         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2355         val &= VLV_GTLC_ALLOWWAKEREQ;
2356         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2357         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2358
2359         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2360         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2361         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2362         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2363
2364         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2365
2366         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2367         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2368         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2369         I915_WRITE(VLV_PCBR,                    s->pcbr);
2370         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2371 }
2372
2373 static int vlv_wait_for_pw_status(struct drm_i915_private *i915,
2374                                   u32 mask, u32 val)
2375 {
2376         i915_reg_t reg = VLV_GTLC_PW_STATUS;
2377         u32 reg_value;
2378         int ret;
2379
2380         /* The HW does not like us polling for PW_STATUS frequently, so
2381          * use the sleeping loop rather than risk the busy spin within
2382          * intel_wait_for_register().
2383          *
2384          * Transitioning between RC6 states should be at most 2ms (see
2385          * valleyview_enable_rps) so use a 3ms timeout.
2386          */
2387         ret = wait_for(((reg_value =
2388                          intel_uncore_read_notrace(&i915->uncore, reg)) & mask)
2389                        == val, 3);
2390
2391         /* just trace the final value */
2392         trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
2393
2394         return ret;
2395 }
2396
2397 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2398 {
2399         u32 val;
2400         int err;
2401
2402         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2403         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2404         if (force_on)
2405                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2406         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2407
2408         if (!force_on)
2409                 return 0;
2410
2411         err = intel_wait_for_register(&dev_priv->uncore,
2412                                       VLV_GTLC_SURVIVABILITY_REG,
2413                                       VLV_GFX_CLK_STATUS_BIT,
2414                                       VLV_GFX_CLK_STATUS_BIT,
2415                                       20);
2416         if (err)
2417                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2418                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2419
2420         return err;
2421 }
2422
2423 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2424 {
2425         u32 mask;
2426         u32 val;
2427         int err;
2428
2429         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2430         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2431         if (allow)
2432                 val |= VLV_GTLC_ALLOWWAKEREQ;
2433         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2434         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2435
2436         mask = VLV_GTLC_ALLOWWAKEACK;
2437         val = allow ? mask : 0;
2438
2439         err = vlv_wait_for_pw_status(dev_priv, mask, val);
2440         if (err)
2441                 DRM_ERROR("timeout disabling GT waking\n");
2442
2443         return err;
2444 }
2445
2446 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2447                                   bool wait_for_on)
2448 {
2449         u32 mask;
2450         u32 val;
2451
2452         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2453         val = wait_for_on ? mask : 0;
2454
2455         /*
2456          * RC6 transitioning can be delayed up to 2 msec (see
2457          * valleyview_enable_rps), use 3 msec for safety.
2458          *
2459          * This can fail to turn off the rc6 if the GPU is stuck after a failed
2460          * reset and we are trying to force the machine to sleep.
2461          */
2462         if (vlv_wait_for_pw_status(dev_priv, mask, val))
2463                 DRM_DEBUG_DRIVER("timeout waiting for GT wells to go %s\n",
2464                                  onoff(wait_for_on));
2465 }
2466
2467 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2468 {
2469         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2470                 return;
2471
2472         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2473         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2474 }
2475
2476 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2477 {
2478         u32 mask;
2479         int err;
2480
2481         /*
2482          * Bspec defines the following GT well on flags as debug only, so
2483          * don't treat them as hard failures.
2484          */
2485         vlv_wait_for_gt_wells(dev_priv, false);
2486
2487         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2488         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2489
2490         vlv_check_no_gt_access(dev_priv);
2491
2492         err = vlv_force_gfx_clock(dev_priv, true);
2493         if (err)
2494                 goto err1;
2495
2496         err = vlv_allow_gt_wake(dev_priv, false);
2497         if (err)
2498                 goto err2;
2499
2500         vlv_save_gunit_s0ix_state(dev_priv);
2501
2502         err = vlv_force_gfx_clock(dev_priv, false);
2503         if (err)
2504                 goto err2;
2505
2506         return 0;
2507
2508 err2:
2509         /* For safety always re-enable waking and disable gfx clock forcing */
2510         vlv_allow_gt_wake(dev_priv, true);
2511 err1:
2512         vlv_force_gfx_clock(dev_priv, false);
2513
2514         return err;
2515 }
2516
2517 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2518                                 bool rpm_resume)
2519 {
2520         int err;
2521         int ret;
2522
2523         /*
2524          * If any of the steps fail just try to continue, that's the best we
2525          * can do at this point. Return the first error code (which will also
2526          * leave RPM permanently disabled).
2527          */
2528         ret = vlv_force_gfx_clock(dev_priv, true);
2529
2530         vlv_restore_gunit_s0ix_state(dev_priv);
2531
2532         err = vlv_allow_gt_wake(dev_priv, true);
2533         if (!ret)
2534                 ret = err;
2535
2536         err = vlv_force_gfx_clock(dev_priv, false);
2537         if (!ret)
2538                 ret = err;
2539
2540         vlv_check_no_gt_access(dev_priv);
2541
2542         if (rpm_resume)
2543                 intel_init_clock_gating(dev_priv);
2544
2545         return ret;
2546 }
2547
2548 static int intel_runtime_suspend(struct device *kdev)
2549 {
2550         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
2551         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
2552         int ret = 0;
2553
2554         if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv))))
2555                 return -ENODEV;
2556
2557         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2558                 return -ENODEV;
2559
2560         DRM_DEBUG_KMS("Suspending device\n");
2561
2562         disable_rpm_wakeref_asserts(rpm);
2563
2564         /*
2565          * We are safe here against re-faults, since the fault handler takes
2566          * an RPM reference.
2567          */
2568         i915_gem_runtime_suspend(dev_priv);
2569
2570         intel_gt_runtime_suspend(&dev_priv->gt);
2571
2572         intel_runtime_pm_disable_interrupts(dev_priv);
2573
2574         intel_uncore_suspend(&dev_priv->uncore);
2575
2576         intel_display_power_suspend(dev_priv);
2577
2578         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2579                 ret = vlv_suspend_complete(dev_priv);
2580
2581         if (ret) {
2582                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2583                 intel_uncore_runtime_resume(&dev_priv->uncore);
2584
2585                 intel_runtime_pm_enable_interrupts(dev_priv);
2586
2587                 intel_gt_runtime_resume(&dev_priv->gt);
2588
2589                 i915_gem_restore_fences(dev_priv);
2590
2591                 enable_rpm_wakeref_asserts(rpm);
2592
2593                 return ret;
2594         }
2595
2596         enable_rpm_wakeref_asserts(rpm);
2597         intel_runtime_pm_driver_release(rpm);
2598
2599         if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
2600                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2601
2602         rpm->suspended = true;
2603
2604         /*
2605          * FIXME: We really should find a document that references the arguments
2606          * used below!
2607          */
2608         if (IS_BROADWELL(dev_priv)) {
2609                 /*
2610                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2611                  * being detected, and the call we do at intel_runtime_resume()
2612                  * won't be able to restore them. Since PCI_D3hot matches the
2613                  * actual specification and appears to be working, use it.
2614                  */
2615                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2616         } else {
2617                 /*
2618                  * current versions of firmware which depend on this opregion
2619                  * notification have repurposed the D1 definition to mean
2620                  * "runtime suspended" vs. what you would normally expect (D3)
2621                  * to distinguish it from notifications that might be sent via
2622                  * the suspend path.
2623                  */
2624                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2625         }
2626
2627         assert_forcewakes_inactive(&dev_priv->uncore);
2628
2629         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2630                 intel_hpd_poll_init(dev_priv);
2631
2632         DRM_DEBUG_KMS("Device suspended\n");
2633         return 0;
2634 }
2635
2636 static int intel_runtime_resume(struct device *kdev)
2637 {
2638         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
2639         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
2640         int ret = 0;
2641
2642         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2643                 return -ENODEV;
2644
2645         DRM_DEBUG_KMS("Resuming device\n");
2646
2647         WARN_ON_ONCE(atomic_read(&rpm->wakeref_count));
2648         disable_rpm_wakeref_asserts(rpm);
2649
2650         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2651         rpm->suspended = false;
2652         if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
2653                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2654
2655         intel_display_power_resume(dev_priv);
2656
2657         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2658                 ret = vlv_resume_prepare(dev_priv, true);
2659
2660         intel_uncore_runtime_resume(&dev_priv->uncore);
2661
2662         intel_runtime_pm_enable_interrupts(dev_priv);
2663
2664         /*
2665          * No point of rolling back things in case of an error, as the best
2666          * we can do is to hope that things will still work (and disable RPM).
2667          */
2668         intel_gt_runtime_resume(&dev_priv->gt);
2669         i915_gem_restore_fences(dev_priv);
2670
2671         /*
2672          * On VLV/CHV display interrupts are part of the display
2673          * power well, so hpd is reinitialized from there. For
2674          * everyone else do it here.
2675          */
2676         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2677                 intel_hpd_init(dev_priv);
2678
2679         intel_enable_ipc(dev_priv);
2680
2681         enable_rpm_wakeref_asserts(rpm);
2682
2683         if (ret)
2684                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2685         else
2686                 DRM_DEBUG_KMS("Device resumed\n");
2687
2688         return ret;
2689 }
2690
2691 const struct dev_pm_ops i915_pm_ops = {
2692         /*
2693          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2694          * PMSG_RESUME]
2695          */
2696         .prepare = i915_pm_prepare,
2697         .suspend = i915_pm_suspend,
2698         .suspend_late = i915_pm_suspend_late,
2699         .resume_early = i915_pm_resume_early,
2700         .resume = i915_pm_resume,
2701
2702         /*
2703          * S4 event handlers
2704          * @freeze, @freeze_late    : called (1) before creating the
2705          *                            hibernation image [PMSG_FREEZE] and
2706          *                            (2) after rebooting, before restoring
2707          *                            the image [PMSG_QUIESCE]
2708          * @thaw, @thaw_early       : called (1) after creating the hibernation
2709          *                            image, before writing it [PMSG_THAW]
2710          *                            and (2) after failing to create or
2711          *                            restore the image [PMSG_RECOVER]
2712          * @poweroff, @poweroff_late: called after writing the hibernation
2713          *                            image, before rebooting [PMSG_HIBERNATE]
2714          * @restore, @restore_early : called after rebooting and restoring the
2715          *                            hibernation image [PMSG_RESTORE]
2716          */
2717         .freeze = i915_pm_freeze,
2718         .freeze_late = i915_pm_freeze_late,
2719         .thaw_early = i915_pm_thaw_early,
2720         .thaw = i915_pm_thaw,
2721         .poweroff = i915_pm_suspend,
2722         .poweroff_late = i915_pm_poweroff_late,
2723         .restore_early = i915_pm_restore_early,
2724         .restore = i915_pm_restore,
2725
2726         /* S0ix (via runtime suspend) event handlers */
2727         .runtime_suspend = intel_runtime_suspend,
2728         .runtime_resume = intel_runtime_resume,
2729 };
2730
2731 static const struct vm_operations_struct i915_gem_vm_ops = {
2732         .fault = i915_gem_fault,
2733         .open = drm_gem_vm_open,
2734         .close = drm_gem_vm_close,
2735 };
2736
2737 static const struct file_operations i915_driver_fops = {
2738         .owner = THIS_MODULE,
2739         .open = drm_open,
2740         .release = drm_release,
2741         .unlocked_ioctl = drm_ioctl,
2742         .mmap = drm_gem_mmap,
2743         .poll = drm_poll,
2744         .read = drm_read,
2745         .compat_ioctl = i915_compat_ioctl,
2746         .llseek = noop_llseek,
2747 };
2748
2749 static int
2750 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2751                           struct drm_file *file)
2752 {
2753         return -ENODEV;
2754 }
2755
2756 static const struct drm_ioctl_desc i915_ioctls[] = {
2757         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2758         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2759         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2760         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2761         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2762         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2763         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
2764         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2765         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2766         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2767         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2768         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2769         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2770         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2771         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2772         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2773         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2774         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2775         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
2776         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
2777         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2778         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2779         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
2780         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2781         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2782         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
2783         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2784         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2785         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2786         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2787         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2788         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2789         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2790         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2791         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2792         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2793         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2794         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2795         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
2796         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2797         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
2798         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
2799         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
2800         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
2801         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
2802         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2803         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2804         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2805         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2806         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2807         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2808         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2809         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2810         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
2811         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
2812         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
2813         DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
2814         DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
2815 };
2816
2817 static struct drm_driver driver = {
2818         /* Don't use MTRRs here; the Xserver or userspace app should
2819          * deal with them for Intel hardware.
2820          */
2821         .driver_features =
2822             DRIVER_GEM |
2823             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
2824         .release = i915_driver_release,
2825         .open = i915_driver_open,
2826         .lastclose = i915_driver_lastclose,
2827         .postclose = i915_driver_postclose,
2828
2829         .gem_close_object = i915_gem_close_object,
2830         .gem_free_object_unlocked = i915_gem_free_object,
2831         .gem_vm_ops = &i915_gem_vm_ops,
2832
2833         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2834         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2835         .gem_prime_export = i915_gem_prime_export,
2836         .gem_prime_import = i915_gem_prime_import,
2837
2838         .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
2839         .get_scanout_position = i915_get_crtc_scanoutpos,
2840
2841         .dumb_create = i915_gem_dumb_create,
2842         .dumb_map_offset = i915_gem_mmap_gtt,
2843         .ioctls = i915_ioctls,
2844         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2845         .fops = &i915_driver_fops,
2846         .name = DRIVER_NAME,
2847         .desc = DRIVER_DESC,
2848         .date = DRIVER_DATE,
2849         .major = DRIVER_MAJOR,
2850         .minor = DRIVER_MINOR,
2851         .patchlevel = DRIVER_PATCHLEVEL,
2852 };
2853
2854 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2855 #include "selftests/mock_drm.c"
2856 #endif