drivers/gpu/drm/i915/i915_cmd_parser.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Brad Volkin <bradley.d.volkin@intel.com>
  25  *
  26  */
  27
  28 #include "gt/intel_engine.h"
  29
  30 #include "i915_drv.h"
  31 #include "i915_memcpy.h"
  32
  33 /**
  34  * DOC: batch buffer command parser
  35  *
  36  * Motivation:
  37  * Certain OpenGL features (e.g. transform feedback, performance monitoring)
  38  * require userspace code to submit batches containing commands such as
  39  * MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some
  40  * generations of the hardware will noop these commands in "unsecure" batches
  41  * (which includes all userspace batches submitted via i915) even though the
  42  * commands may be safe and represent the intended programming model of the
  43  * device.
  44  *
  45  * The software command parser is similar in operation to the command parsing
  46  * done in hardware for unsecure batches. However, the software parser allows
  47  * some operations that would be noop'd by hardware, if the parser determines
  48  * the operation is safe, and submits the batch as "secure" to prevent hardware
  49  * parsing.
  50  *
  51  * Threats:
  52  * At a high level, the hardware (and software) checks attempt to prevent
  53  * granting userspace undue privileges. There are three categories of privilege.
  54  *
  55  * First, commands which are explicitly defined as privileged or which should
  56  * only be used by the kernel driver. The parser rejects such commands
  57  *
  58  * Second, commands which access registers. To support correct/enhanced
  59  * userspace functionality, particularly certain OpenGL extensions, the parser
  60  * provides a whitelist of registers which userspace may safely access
  61  *
  62  * Third, commands which access privileged memory (i.e. GGTT, HWS page, etc).
  63  * The parser always rejects such commands.
  64  *
  65  * The majority of the problematic commands fall in the MI_* range, with only a
  66  * few specific commands on each engine (e.g. PIPE_CONTROL and MI_FLUSH_DW).
  67  *
  68  * Implementation:
  69  * Each engine maintains tables of commands and registers which the parser
  70  * uses in scanning batch buffers submitted to that engine.
  71  *
  72  * Since the set of commands that the parser must check for is significantly
  73  * smaller than the number of commands supported, the parser tables contain only
  74  * those commands required by the parser. This generally works because command
  75  * opcode ranges have standard command length encodings. So for commands that
  76  * the parser does not need to check, it can easily skip them. This is
  77  * implemented via a per-engine length decoding vfunc.
  78  *
  79  * Unfortunately, there are a number of commands that do not follow the standard
  80  * length encoding for their opcode range, primarily amongst the MI_* commands.
  81  * To handle this, the parser provides a way to define explicit "skip" entries
  82  * in the per-engine command tables.
  83  *
  84  * Other command table entries map fairly directly to high level categories
  85  * mentioned above: rejected, register whitelist. The parser implements a number
  86  * of checks, including the privileged memory checks, via a general bitmasking
  87  * mechanism.
  88  */
  89
  90 /*
  91  * A command that requires special handling by the command parser.
  92  */
  93 struct drm_i915_cmd_descriptor {
  94         /*
  95          * Flags describing how the command parser processes the command.
  96          *
  97          * CMD_DESC_FIXED: The command has a fixed length if this is set,
  98          *                 a length mask if not set
  99          * CMD_DESC_SKIP: The command is allowed but does not follow the
 100          *                standard length encoding for the opcode range in
 101          *                which it falls
 102          * CMD_DESC_REJECT: The command is never allowed
 103          * CMD_DESC_REGISTER: The command should be checked against the
 104          *                    register whitelist for the appropriate ring
 105          */
 106         u32 flags;
 107 #define CMD_DESC_FIXED    (1<<0)
 108 #define CMD_DESC_SKIP     (1<<1)
 109 #define CMD_DESC_REJECT   (1<<2)
 110 #define CMD_DESC_REGISTER (1<<3)
 111 #define CMD_DESC_BITMASK  (1<<4)
 112
 113         /*
 114          * The command's unique identification bits and the bitmask to get them.
 115          * This isn't strictly the opcode field as defined in the spec and may
 116          * also include type, subtype, and/or subop fields.
 117          */
 118         struct {
 119                 u32 value;
 120                 u32 mask;
 121         } cmd;
 122
 123         /*
 124          * The command's length. The command is either fixed length (i.e. does
 125          * not include a length field) or has a length field mask. The flag
 126          * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
 127          * a length mask. All command entries in a command table must include
 128          * length information.
 129          */
 130         union {
 131                 u32 fixed;
 132                 u32 mask;
 133         } length;
 134
 135         /*
 136          * Describes where to find a register address in the command to check
 137          * against the ring's register whitelist. Only valid if flags has the
 138          * CMD_DESC_REGISTER bit set.
 139          *
 140          * A non-zero step value implies that the command may access multiple
 141          * registers in sequence (e.g. LRI), in that case step gives the
 142          * distance in dwords between individual offset fields.
 143          */
 144         struct {
 145                 u32 offset;
 146                 u32 mask;
 147                 u32 step;
 148         } reg;
 149
 150 #define MAX_CMD_DESC_BITMASKS 3
 151         /*
 152          * Describes command checks where a particular dword is masked and
 153          * compared against an expected value. If the command does not match
 154          * the expected value, the parser rejects it. Only valid if flags has
 155          * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
 156          * are valid.
 157          *
 158          * If the check specifies a non-zero condition_mask then the parser
 159          * only performs the check when the bits specified by condition_mask
 160          * are non-zero.
 161          */
 162         struct {
 163                 u32 offset;
 164                 u32 mask;
 165                 u32 expected;
 166                 u32 condition_offset;
 167                 u32 condition_mask;
 168         } bits[MAX_CMD_DESC_BITMASKS];
 169 };
 170
 171 /*
 172  * A table of commands requiring special handling by the command parser.
 173  *
 174  * Each engine has an array of tables. Each table consists of an array of
 175  * command descriptors, which must be sorted with command opcodes in
 176  * ascending order.
 177  */
 178 struct drm_i915_cmd_table {
 179         const struct drm_i915_cmd_descriptor *table;
 180         int count;
 181 };
 182
 183 #define STD_MI_OPCODE_SHIFT  (32 - 9)
 184 #define STD_3D_OPCODE_SHIFT  (32 - 16)
 185 #define STD_2D_OPCODE_SHIFT  (32 - 10)
 186 #define STD_MFX_OPCODE_SHIFT (32 - 16)
 187 #define MIN_OPCODE_SHIFT 16
 188
 189 #define CMD(op, opm, f, lm, fl, ...)                            \
 190         {                                                       \
 191                 .flags = (fl) | ((f) ? CMD_DESC_FIXED : 0),     \
 192                 .cmd = { (op & ~0u << (opm)), ~0u << (opm) },   \
 193                 .length = { (lm) },                             \
 194                 __VA_ARGS__                                     \
 195         }
 196
 197 /* Convenience macros to compress the tables */
 198 #define SMI STD_MI_OPCODE_SHIFT
 199 #define S3D STD_3D_OPCODE_SHIFT
 200 #define S2D STD_2D_OPCODE_SHIFT
 201 #define SMFX STD_MFX_OPCODE_SHIFT
 202 #define F true
 203 #define S CMD_DESC_SKIP
 204 #define R CMD_DESC_REJECT
 205 #define W CMD_DESC_REGISTER
 206 #define B CMD_DESC_BITMASK
 207
 208 /*            Command                          Mask   Fixed Len   Action
 209               ---------------------------------------------------------- */
 210 static const struct drm_i915_cmd_descriptor gen7_common_cmds[] = {
 211         CMD(  MI_NOOP,                          SMI,    F,  1,      S  ),
 212         CMD(  MI_USER_INTERRUPT,                SMI,    F,  1,      R  ),
 213         CMD(  MI_WAIT_FOR_EVENT,                SMI,    F,  1,      R  ),
 214         CMD(  MI_ARB_CHECK,                     SMI,    F,  1,      S  ),
 215         CMD(  MI_REPORT_HEAD,                   SMI,    F,  1,      S  ),
 216         CMD(  MI_SUSPEND_FLUSH,                 SMI,    F,  1,      S  ),
 217         CMD(  MI_SEMAPHORE_MBOX,                SMI,   !F,  0xFF,   R  ),
 218         CMD(  MI_STORE_DWORD_INDEX,             SMI,   !F,  0xFF,   R  ),
 219         CMD(  MI_LOAD_REGISTER_IMM(1),          SMI,   !F,  0xFF,   W,
 220               .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 }    ),
 221         CMD(  MI_STORE_REGISTER_MEM,            SMI,    F,  3,     W | B,
 222               .reg = { .offset = 1, .mask = 0x007FFFFC },
 223               .bits = {{
 224                         .offset = 0,
 225                         .mask = MI_GLOBAL_GTT,
 226                         .expected = 0,
 227               }},                                                      ),
 228         CMD(  MI_LOAD_REGISTER_MEM,             SMI,    F,  3,     W | B,
 229               .reg = { .offset = 1, .mask = 0x007FFFFC },
 230               .bits = {{
 231                         .offset = 0,
 232                         .mask = MI_GLOBAL_GTT,
 233                         .expected = 0,
 234               }},                                                      ),
 235         /*
 236          * MI_BATCH_BUFFER_START requires some special handling. It's not
 237          * really a 'skip' action but it doesn't seem like it's worth adding
 238          * a new action. See intel_engine_cmd_parser().
 239          */
 240         CMD(  MI_BATCH_BUFFER_START,            SMI,   !F,  0xFF,   S  ),
 241 };
 242
 243 static const struct drm_i915_cmd_descriptor gen7_render_cmds[] = {
 244         CMD(  MI_FLUSH,                         SMI,    F,  1,      S  ),
 245         CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),
 246         CMD(  MI_PREDICATE,                     SMI,    F,  1,      S  ),
 247         CMD(  MI_TOPOLOGY_FILTER,               SMI,    F,  1,      S  ),
 248         CMD(  MI_SET_APPID,                     SMI,    F,  1,      S  ),
 249         CMD(  MI_DISPLAY_FLIP,                  SMI,   !F,  0xFF,   R  ),
 250         CMD(  MI_SET_CONTEXT,                   SMI,   !F,  0xFF,   R  ),
 251         CMD(  MI_URB_CLEAR,                     SMI,   !F,  0xFF,   S  ),
 252         CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0x3F,   B,
 253               .bits = {{
 254                         .offset = 0,
 255                         .mask = MI_GLOBAL_GTT,
 256                         .expected = 0,
 257               }},                                                      ),
 258         CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0xFF,   R  ),
 259         CMD(  MI_CLFLUSH,                       SMI,   !F,  0x3FF,  B,
 260               .bits = {{
 261                         .offset = 0,
 262                         .mask = MI_GLOBAL_GTT,
 263                         .expected = 0,
 264               }},                                                      ),
 265         CMD(  MI_REPORT_PERF_COUNT,             SMI,   !F,  0x3F,   B,
 266               .bits = {{
 267                         .offset = 1,
 268                         .mask = MI_REPORT_PERF_COUNT_GGTT,
 269                         .expected = 0,
 270               }},                                                      ),
 271         CMD(  MI_CONDITIONAL_BATCH_BUFFER_END,  SMI,   !F,  0xFF,   B,
 272               .bits = {{
 273                         .offset = 0,
 274                         .mask = MI_GLOBAL_GTT,
 275                         .expected = 0,
 276               }},                                                      ),
 277         CMD(  GFX_OP_3DSTATE_VF_STATISTICS,     S3D,    F,  1,      S  ),
 278         CMD(  PIPELINE_SELECT,                  S3D,    F,  1,      S  ),
 279         CMD(  MEDIA_VFE_STATE,                  S3D,   !F,  0xFFFF, B,
 280               .bits = {{
 281                         .offset = 2,
 282                         .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK,
 283                         .expected = 0,
 284               }},                                                      ),
 285         CMD(  GPGPU_OBJECT,                     S3D,   !F,  0xFF,   S  ),
 286         CMD(  GPGPU_WALKER,                     S3D,   !F,  0xFF,   S  ),
 287         CMD(  GFX_OP_3DSTATE_SO_DECL_LIST,      S3D,   !F,  0x1FF,  S  ),
 288         CMD(  GFX_OP_PIPE_CONTROL(5),           S3D,   !F,  0xFF,   B,
 289               .bits = {{
 290                         .offset = 1,
 291                         .mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY),
 292                         .expected = 0,
 293               },
 294               {
 295                         .offset = 1,
 296                         .mask = (PIPE_CONTROL_GLOBAL_GTT_IVB |
 297                                  PIPE_CONTROL_STORE_DATA_INDEX),
 298                         .expected = 0,
 299                         .condition_offset = 1,
 300                         .condition_mask = PIPE_CONTROL_POST_SYNC_OP_MASK,
 301               }},                                                      ),
 302 };
 303
 304 static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
 305         CMD(  MI_SET_PREDICATE,                 SMI,    F,  1,      S  ),
 306         CMD(  MI_RS_CONTROL,                    SMI,    F,  1,      S  ),
 307         CMD(  MI_URB_ATOMIC_ALLOC,              SMI,    F,  1,      S  ),
 308         CMD(  MI_SET_APPID,                     SMI,    F,  1,      S  ),
 309         CMD(  MI_RS_CONTEXT,                    SMI,    F,  1,      S  ),
 310         CMD(  MI_LOAD_SCAN_LINES_INCL,          SMI,   !F,  0x3F,   R  ),
 311         CMD(  MI_LOAD_SCAN_LINES_EXCL,          SMI,   !F,  0x3F,   R  ),
 312         CMD(  MI_LOAD_REGISTER_REG,             SMI,   !F,  0xFF,   W,
 313               .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 }    ),
 314         CMD(  MI_RS_STORE_DATA_IMM,             SMI,   !F,  0xFF,   S  ),
 315         CMD(  MI_LOAD_URB_MEM,                  SMI,   !F,  0xFF,   S  ),
 316         CMD(  MI_STORE_URB_MEM,                 SMI,   !F,  0xFF,   S  ),
 317         CMD(  GFX_OP_3DSTATE_DX9_CONSTANTF_VS,  S3D,   !F,  0x7FF,  S  ),
 318         CMD(  GFX_OP_3DSTATE_DX9_CONSTANTF_PS,  S3D,   !F,  0x7FF,  S  ),
 319
 320         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS,  S3D,   !F,  0x1FF,  S  ),
 321         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS,  S3D,   !F,  0x1FF,  S  ),
 322         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS,  S3D,   !F,  0x1FF,  S  ),
 323         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS,  S3D,   !F,  0x1FF,  S  ),
 324         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS,  S3D,   !F,  0x1FF,  S  ),
 325 };
 326
 327 static const struct drm_i915_cmd_descriptor gen7_video_cmds[] = {
 328         CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),
 329         CMD(  MI_SET_APPID,                     SMI,    F,  1,      S  ),
 330         CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0xFF,   B,
 331               .bits = {{
 332                         .offset = 0,
 333                         .mask = MI_GLOBAL_GTT,
 334                         .expected = 0,
 335               }},                                                      ),
 336         CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0x3F,   R  ),
 337         CMD(  MI_FLUSH_DW,                      SMI,   !F,  0x3F,   B,
 338               .bits = {{
 339                         .offset = 0,
 340                         .mask = MI_FLUSH_DW_NOTIFY,
 341                         .expected = 0,
 342               },
 343               {
 344                         .offset = 1,
 345                         .mask = MI_FLUSH_DW_USE_GTT,
 346                         .expected = 0,
 347                         .condition_offset = 0,
 348                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 349               },
 350               {
 351                         .offset = 0,
 352                         .mask = MI_FLUSH_DW_STORE_INDEX,
 353                         .expected = 0,
 354                         .condition_offset = 0,
 355                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 356               }},                                                      ),
 357         CMD(  MI_CONDITIONAL_BATCH_BUFFER_END,  SMI,   !F,  0xFF,   B,
 358               .bits = {{
 359                         .offset = 0,
 360                         .mask = MI_GLOBAL_GTT,
 361                         .expected = 0,
 362               }},                                                      ),
 363         /*
 364          * MFX_WAIT doesn't fit the way we handle length for most commands.
 365          * It has a length field but it uses a non-standard length bias.
 366          * It is always 1 dword though, so just treat it as fixed length.
 367          */
 368         CMD(  MFX_WAIT,                         SMFX,   F,  1,      S  ),
 369 };
 370
 371 static const struct drm_i915_cmd_descriptor gen7_vecs_cmds[] = {
 372         CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),
 373         CMD(  MI_SET_APPID,                     SMI,    F,  1,      S  ),
 374         CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0xFF,   B,
 375               .bits = {{
 376                         .offset = 0,
 377                         .mask = MI_GLOBAL_GTT,
 378                         .expected = 0,
 379               }},                                                      ),
 380         CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0x3F,   R  ),
 381         CMD(  MI_FLUSH_DW,                      SMI,   !F,  0x3F,   B,
 382               .bits = {{
 383                         .offset = 0,
 384                         .mask = MI_FLUSH_DW_NOTIFY,
 385                         .expected = 0,
 386               },
 387               {
 388                         .offset = 1,
 389                         .mask = MI_FLUSH_DW_USE_GTT,
 390                         .expected = 0,
 391                         .condition_offset = 0,
 392                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 393               },
 394               {
 395                         .offset = 0,
 396                         .mask = MI_FLUSH_DW_STORE_INDEX,
 397                         .expected = 0,
 398                         .condition_offset = 0,
 399                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 400               }},                                                      ),
 401         CMD(  MI_CONDITIONAL_BATCH_BUFFER_END,  SMI,   !F,  0xFF,   B,
 402               .bits = {{
 403                         .offset = 0,
 404                         .mask = MI_GLOBAL_GTT,
 405                         .expected = 0,
 406               }},                                                      ),
 407 };
 408
 409 static const struct drm_i915_cmd_descriptor gen7_blt_cmds[] = {
 410         CMD(  MI_DISPLAY_FLIP,                  SMI,   !F,  0xFF,   R  ),
 411         CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0x3FF,  B,
 412               .bits = {{
 413                         .offset = 0,
 414                         .mask = MI_GLOBAL_GTT,
 415                         .expected = 0,
 416               }},                                                      ),
 417         CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0x3F,   R  ),
 418         CMD(  MI_FLUSH_DW,                      SMI,   !F,  0x3F,   B,
 419               .bits = {{
 420                         .offset = 0,
 421                         .mask = MI_FLUSH_DW_NOTIFY,
 422                         .expected = 0,
 423               },
 424               {
 425                         .offset = 1,
 426                         .mask = MI_FLUSH_DW_USE_GTT,
 427                         .expected = 0,
 428                         .condition_offset = 0,
 429                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 430               },
 431               {
 432                         .offset = 0,
 433                         .mask = MI_FLUSH_DW_STORE_INDEX,
 434                         .expected = 0,
 435                         .condition_offset = 0,
 436                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 437               }},                                                      ),
 438         CMD(  COLOR_BLT,                        S2D,   !F,  0x3F,   S  ),
 439         CMD(  SRC_COPY_BLT,                     S2D,   !F,  0x3F,   S  ),
 440 };
 441
 442 static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = {
 443         CMD(  MI_LOAD_SCAN_LINES_INCL,          SMI,   !F,  0x3F,   R  ),
 444         CMD(  MI_LOAD_SCAN_LINES_EXCL,          SMI,   !F,  0x3F,   R  ),
 445 };
 446
 447 /*
 448  * For Gen9 we can still rely on the h/w to enforce cmd security, and only
 449  * need to re-enforce the register access checks. We therefore only need to
 450  * teach the cmdparser how to find the end of each command, and identify
 451  * register accesses. The table doesn't need to reject any commands, and so
 452  * the only commands listed here are:
 453  *   1) Those that touch registers
 454  *   2) Those that do not have the default 8-bit length
 455  *
 456  * Note that the default MI length mask chosen for this table is 0xFF, not
 457  * the 0x3F used on older devices. This is because the vast majority of MI
 458  * cmds on Gen9 use a standard 8-bit Length field.
 459  * All the Gen9 blitter instructions are standard 0xFF length mask, and
 460  * none allow access to non-general registers, so in fact no BLT cmds are
 461  * included in the table at all.
 462  *
 463  */
 464 static const struct drm_i915_cmd_descriptor gen9_blt_cmds[] = {
 465         CMD(  MI_NOOP,                          SMI,    F,  1,      S  ),
 466         CMD(  MI_USER_INTERRUPT,                SMI,    F,  1,      S  ),
 467         CMD(  MI_WAIT_FOR_EVENT,                SMI,    F,  1,      S  ),
 468         CMD(  MI_FLUSH,                         SMI,    F,  1,      S  ),
 469         CMD(  MI_ARB_CHECK,                     SMI,    F,  1,      S  ),
 470         CMD(  MI_REPORT_HEAD,                   SMI,    F,  1,      S  ),
 471         CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      S  ),
 472         CMD(  MI_SUSPEND_FLUSH,                 SMI,    F,  1,      S  ),
 473         CMD(  MI_LOAD_SCAN_LINES_INCL,          SMI,   !F,  0x3F,   S  ),
 474         CMD(  MI_LOAD_SCAN_LINES_EXCL,          SMI,   !F,  0x3F,   S  ),
 475         CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0x3FF,  S  ),
 476         CMD(  MI_LOAD_REGISTER_IMM(1),          SMI,   !F,  0xFF,   W,
 477               .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 }    ),
 478         CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0x3FF,  S  ),
 479         CMD(  MI_STORE_REGISTER_MEM_GEN8,       SMI,    F,  4,      W,
 480               .reg = { .offset = 1, .mask = 0x007FFFFC }               ),
 481         CMD(  MI_FLUSH_DW,                      SMI,   !F,  0x3F,   S  ),
 482         CMD(  MI_LOAD_REGISTER_MEM_GEN8,        SMI,    F,  4,      W,
 483               .reg = { .offset = 1, .mask = 0x007FFFFC }               ),
 484         CMD(  MI_LOAD_REGISTER_REG,             SMI,    !F,  0xFF,  W,
 485               .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 }    ),
 486
 487         /*
 488          * We allow BB_START but apply further checks. We just sanitize the
 489          * basic fields here.
 490          */
 491 #define MI_BB_START_OPERAND_MASK   GENMASK(SMI-1, 0)
 492 #define MI_BB_START_OPERAND_EXPECT (MI_BATCH_PPGTT_HSW | 1)
 493         CMD(  MI_BATCH_BUFFER_START_GEN8,       SMI,    !F,  0xFF,  B,
 494               .bits = {{
 495                         .offset = 0,
 496                         .mask = MI_BB_START_OPERAND_MASK,
 497                         .expected = MI_BB_START_OPERAND_EXPECT,
 498               }},                                                      ),
 499 };
 500
 501 static const struct drm_i915_cmd_descriptor noop_desc =
 502         CMD(MI_NOOP, SMI, F, 1, S);
 503
 504 #undef CMD
 505 #undef SMI
 506 #undef S3D
 507 #undef S2D
 508 #undef SMFX
 509 #undef F
 510 #undef S
 511 #undef R
 512 #undef W
 513 #undef B
 514
 515 static const struct drm_i915_cmd_table gen7_render_cmd_table[] = {
 516         { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
 517         { gen7_render_cmds, ARRAY_SIZE(gen7_render_cmds) },
 518 };
 519
 520 static const struct drm_i915_cmd_table hsw_render_ring_cmd_table[] = {
 521         { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
 522         { gen7_render_cmds, ARRAY_SIZE(gen7_render_cmds) },
 523         { hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) },
 524 };
 525
 526 static const struct drm_i915_cmd_table gen7_video_cmd_table[] = {
 527         { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
 528         { gen7_video_cmds, ARRAY_SIZE(gen7_video_cmds) },
 529 };
 530
 531 static const struct drm_i915_cmd_table hsw_vebox_cmd_table[] = {
 532         { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
 533         { gen7_vecs_cmds, ARRAY_SIZE(gen7_vecs_cmds) },
 534 };
 535
 536 static const struct drm_i915_cmd_table gen7_blt_cmd_table[] = {
 537         { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
 538         { gen7_blt_cmds, ARRAY_SIZE(gen7_blt_cmds) },
 539 };
 540
 541 static const struct drm_i915_cmd_table hsw_blt_ring_cmd_table[] = {
 542         { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
 543         { gen7_blt_cmds, ARRAY_SIZE(gen7_blt_cmds) },
 544         { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) },
 545 };
 546
 547 static const struct drm_i915_cmd_table gen9_blt_cmd_table[] = {
 548         { gen9_blt_cmds, ARRAY_SIZE(gen9_blt_cmds) },
 549 };
 550
 551
 552 /*
 553  * Register whitelists, sorted by increasing register offset.
 554  */
 555
 556 /*
 557  * An individual whitelist entry granting access to register addr.  If
 558  * mask is non-zero the argument of immediate register writes will be
 559  * AND-ed with mask, and the command will be rejected if the result
 560  * doesn't match value.
 561  *
 562  * Registers with non-zero mask are only allowed to be written using
 563  * LRI.
 564  */
 565 struct drm_i915_reg_descriptor {
 566         i915_reg_t addr;
 567         u32 mask;
 568         u32 value;
 569 };
 570
 571 /* Convenience macro for adding 32-bit registers. */
 572 #define REG32(_reg, ...) \
 573         { .addr = (_reg), __VA_ARGS__ }
 574
 575 /*
 576  * Convenience macro for adding 64-bit registers.
 577  *
 578  * Some registers that userspace accesses are 64 bits. The register
 579  * access commands only allow 32-bit accesses. Hence, we have to include
 580  * entries for both halves of the 64-bit registers.
 581  */
 582 #define REG64(_reg) \
 583         { .addr = _reg }, \
 584         { .addr = _reg ## _UDW }
 585
 586 #define REG64_IDX(_reg, idx) \
 587         { .addr = _reg(idx) }, \
 588         { .addr = _reg ## _UDW(idx) }
 589
 590 static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
 591         REG64(GPGPU_THREADS_DISPATCHED),
 592         REG64(HS_INVOCATION_COUNT),
 593         REG64(DS_INVOCATION_COUNT),
 594         REG64(IA_VERTICES_COUNT),
 595         REG64(IA_PRIMITIVES_COUNT),
 596         REG64(VS_INVOCATION_COUNT),
 597         REG64(GS_INVOCATION_COUNT),
 598         REG64(GS_PRIMITIVES_COUNT),
 599         REG64(CL_INVOCATION_COUNT),
 600         REG64(CL_PRIMITIVES_COUNT),
 601         REG64(PS_INVOCATION_COUNT),
 602         REG64(PS_DEPTH_COUNT),
 603         REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
 604         REG64(MI_PREDICATE_SRC0),
 605         REG64(MI_PREDICATE_SRC1),
 606         REG32(GEN7_3DPRIM_END_OFFSET),
 607         REG32(GEN7_3DPRIM_START_VERTEX),
 608         REG32(GEN7_3DPRIM_VERTEX_COUNT),
 609         REG32(GEN7_3DPRIM_INSTANCE_COUNT),
 610         REG32(GEN7_3DPRIM_START_INSTANCE),
 611         REG32(GEN7_3DPRIM_BASE_VERTEX),
 612         REG32(GEN7_GPGPU_DISPATCHDIMX),
 613         REG32(GEN7_GPGPU_DISPATCHDIMY),
 614         REG32(GEN7_GPGPU_DISPATCHDIMZ),
 615         REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE),
 616         REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 0),
 617         REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 1),
 618         REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 2),
 619         REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 3),
 620         REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 0),
 621         REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 1),
 622         REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 2),
 623         REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 3),
 624         REG32(GEN7_SO_WRITE_OFFSET(0)),
 625         REG32(GEN7_SO_WRITE_OFFSET(1)),
 626         REG32(GEN7_SO_WRITE_OFFSET(2)),
 627         REG32(GEN7_SO_WRITE_OFFSET(3)),
 628         REG32(GEN7_L3SQCREG1),
 629         REG32(GEN7_L3CNTLREG2),
 630         REG32(GEN7_L3CNTLREG3),
 631         REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
 632 };
 633
 634 static const struct drm_i915_reg_descriptor hsw_render_regs[] = {
 635         REG64_IDX(HSW_CS_GPR, 0),
 636         REG64_IDX(HSW_CS_GPR, 1),
 637         REG64_IDX(HSW_CS_GPR, 2),
 638         REG64_IDX(HSW_CS_GPR, 3),
 639         REG64_IDX(HSW_CS_GPR, 4),
 640         REG64_IDX(HSW_CS_GPR, 5),
 641         REG64_IDX(HSW_CS_GPR, 6),
 642         REG64_IDX(HSW_CS_GPR, 7),
 643         REG64_IDX(HSW_CS_GPR, 8),
 644         REG64_IDX(HSW_CS_GPR, 9),
 645         REG64_IDX(HSW_CS_GPR, 10),
 646         REG64_IDX(HSW_CS_GPR, 11),
 647         REG64_IDX(HSW_CS_GPR, 12),
 648         REG64_IDX(HSW_CS_GPR, 13),
 649         REG64_IDX(HSW_CS_GPR, 14),
 650         REG64_IDX(HSW_CS_GPR, 15),
 651         REG32(HSW_SCRATCH1,
 652               .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE,
 653               .value = 0),
 654         REG32(HSW_ROW_CHICKEN3,
 655               .mask = ~(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE << 16 |
 656                         HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),
 657               .value = 0),
 658 };
 659
 660 static const struct drm_i915_reg_descriptor gen7_blt_regs[] = {
 661         REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
 662         REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE),
 663         REG32(BCS_SWCTRL),
 664         REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
 665 };
 666
 667 static const struct drm_i915_reg_descriptor gen9_blt_regs[] = {
 668         REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
 669         REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE),
 670         REG32(BCS_SWCTRL),
 671         REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
 672         REG64_IDX(BCS_GPR, 0),
 673         REG64_IDX(BCS_GPR, 1),
 674         REG64_IDX(BCS_GPR, 2),
 675         REG64_IDX(BCS_GPR, 3),
 676         REG64_IDX(BCS_GPR, 4),
 677         REG64_IDX(BCS_GPR, 5),
 678         REG64_IDX(BCS_GPR, 6),
 679         REG64_IDX(BCS_GPR, 7),
 680         REG64_IDX(BCS_GPR, 8),
 681         REG64_IDX(BCS_GPR, 9),
 682         REG64_IDX(BCS_GPR, 10),
 683         REG64_IDX(BCS_GPR, 11),
 684         REG64_IDX(BCS_GPR, 12),
 685         REG64_IDX(BCS_GPR, 13),
 686         REG64_IDX(BCS_GPR, 14),
 687         REG64_IDX(BCS_GPR, 15),
 688 };
 689
 690 #undef REG64
 691 #undef REG32
 692
 693 struct drm_i915_reg_table {
 694         const struct drm_i915_reg_descriptor *regs;
 695         int num_regs;
 696 };
 697
 698 static const struct drm_i915_reg_table ivb_render_reg_tables[] = {
 699         { gen7_render_regs, ARRAY_SIZE(gen7_render_regs) },
 700 };
 701
 702 static const struct drm_i915_reg_table ivb_blt_reg_tables[] = {
 703         { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs) },
 704 };
 705
 706 static const struct drm_i915_reg_table hsw_render_reg_tables[] = {
 707         { gen7_render_regs, ARRAY_SIZE(gen7_render_regs) },
 708         { hsw_render_regs, ARRAY_SIZE(hsw_render_regs) },
 709 };
 710
 711 static const struct drm_i915_reg_table hsw_blt_reg_tables[] = {
 712         { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs) },
 713 };
 714
 715 static const struct drm_i915_reg_table gen9_blt_reg_tables[] = {
 716         { gen9_blt_regs, ARRAY_SIZE(gen9_blt_regs) },
 717 };
 718
 719 static u32 gen7_render_get_cmd_length_mask(u32 cmd_header)
 720 {
 721         u32 client = cmd_header >> INSTR_CLIENT_SHIFT;
 722         u32 subclient =
 723                 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
 724
 725         if (client == INSTR_MI_CLIENT)
 726                 return 0x3F;
 727         else if (client == INSTR_RC_CLIENT) {
 728                 if (subclient == INSTR_MEDIA_SUBCLIENT)
 729                         return 0xFFFF;
 730                 else
 731                         return 0xFF;
 732         }
 733
 734         DRM_DEBUG("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header);
 735         return 0;
 736 }
 737
 738 static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header)
 739 {
 740         u32 client = cmd_header >> INSTR_CLIENT_SHIFT;
 741         u32 subclient =
 742                 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
 743         u32 op = (cmd_header & INSTR_26_TO_24_MASK) >> INSTR_26_TO_24_SHIFT;
 744
 745         if (client == INSTR_MI_CLIENT)
 746                 return 0x3F;
 747         else if (client == INSTR_RC_CLIENT) {
 748                 if (subclient == INSTR_MEDIA_SUBCLIENT) {
 749                         if (op == 6)
 750                                 return 0xFFFF;
 751                         else
 752                                 return 0xFFF;
 753                 } else
 754                         return 0xFF;
 755         }
 756
 757         DRM_DEBUG("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header);
 758         return 0;
 759 }
 760
 761 static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header)
 762 {
 763         u32 client = cmd_header >> INSTR_CLIENT_SHIFT;
 764
 765         if (client == INSTR_MI_CLIENT)
 766                 return 0x3F;
 767         else if (client == INSTR_BC_CLIENT)
 768                 return 0xFF;
 769
 770         DRM_DEBUG("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header);
 771         return 0;
 772 }
 773
 774 static u32 gen9_blt_get_cmd_length_mask(u32 cmd_header)
 775 {
 776         u32 client = cmd_header >> INSTR_CLIENT_SHIFT;
 777
 778         if (client == INSTR_MI_CLIENT || client == INSTR_BC_CLIENT)
 779                 return 0xFF;
 780
 781         DRM_DEBUG("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header);
 782         return 0;
 783 }
 784
 785 static bool validate_cmds_sorted(const struct intel_engine_cs *engine,
 786                                  const struct drm_i915_cmd_table *cmd_tables,
 787                                  int cmd_table_count)
 788 {
 789         int i;
 790         bool ret = true;
 791
 792         if (!cmd_tables || cmd_table_count == 0)
 793                 return true;
 794
 795         for (i = 0; i < cmd_table_count; i++) {
 796                 const struct drm_i915_cmd_table *table = &cmd_tables[i];
 797                 u32 previous = 0;
 798                 int j;
 799
 800                 for (j = 0; j < table->count; j++) {
 801                         const struct drm_i915_cmd_descriptor *desc =
 802                                 &table->table[j];
 803                         u32 curr = desc->cmd.value & desc->cmd.mask;
 804
 805                         if (curr < previous) {
 806                                 drm_err(&engine->i915->drm,
 807                                         "CMD: %s [%d] command table not sorted: "
 808                                         "table=%d entry=%d cmd=0x%08X prev=0x%08X\n",
 809                                         engine->name, engine->id,
 810                                         i, j, curr, previous);
 811                                 ret = false;
 812                         }
 813
 814                         previous = curr;
 815                 }
 816         }
 817
 818         return ret;
 819 }
 820
 821 static bool check_sorted(const struct intel_engine_cs *engine,
 822                          const struct drm_i915_reg_descriptor *reg_table,
 823                          int reg_count)
 824 {
 825         int i;
 826         u32 previous = 0;
 827         bool ret = true;
 828
 829         for (i = 0; i < reg_count; i++) {
 830                 u32 curr = i915_mmio_reg_offset(reg_table[i].addr);
 831
 832                 if (curr < previous) {
 833                         drm_err(&engine->i915->drm,
 834                                 "CMD: %s [%d] register table not sorted: "
 835                                 "entry=%d reg=0x%08X prev=0x%08X\n",
 836                                 engine->name, engine->id,
 837                                 i, curr, previous);
 838                         ret = false;
 839                 }
 840
 841                 previous = curr;
 842         }
 843
 844         return ret;
 845 }
 846
 847 static bool validate_regs_sorted(struct intel_engine_cs *engine)
 848 {
 849         int i;
 850         const struct drm_i915_reg_table *table;
 851
 852         for (i = 0; i < engine->reg_table_count; i++) {
 853                 table = &engine->reg_tables[i];
 854                 if (!check_sorted(engine, table->regs, table->num_regs))
 855                         return false;
 856         }
 857
 858         return true;
 859 }
 860
 861 struct cmd_node {
 862         const struct drm_i915_cmd_descriptor *desc;
 863         struct hlist_node node;
 864 };
 865
 866 /*
 867  * Different command ranges have different numbers of bits for the opcode. For
 868  * example, MI commands use bits 31:23 while 3D commands use bits 31:16. The
 869  * problem is that, for example, MI commands use bits 22:16 for other fields
 870  * such as GGTT vs PPGTT bits. If we include those bits in the mask then when
 871  * we mask a command from a batch it could hash to the wrong bucket due to
 872  * non-opcode bits being set. But if we don't include those bits, some 3D
 873  * commands may hash to the same bucket due to not including opcode bits that
 874  * make the command unique. For now, we will risk hashing to the same bucket.
 875  */
 876 static inline u32 cmd_header_key(u32 x)
 877 {
 878         switch (x >> INSTR_CLIENT_SHIFT) {
 879         default:
 880         case INSTR_MI_CLIENT:
 881                 return x >> STD_MI_OPCODE_SHIFT;
 882         case INSTR_RC_CLIENT:
 883                 return x >> STD_3D_OPCODE_SHIFT;
 884         case INSTR_BC_CLIENT:
 885                 return x >> STD_2D_OPCODE_SHIFT;
 886         }
 887 }
 888
 889 static int init_hash_table(struct intel_engine_cs *engine,
 890                            const struct drm_i915_cmd_table *cmd_tables,
 891                            int cmd_table_count)
 892 {
 893         int i, j;
 894
 895         hash_init(engine->cmd_hash);
 896
 897         for (i = 0; i < cmd_table_count; i++) {
 898                 const struct drm_i915_cmd_table *table = &cmd_tables[i];
 899
 900                 for (j = 0; j < table->count; j++) {
 901                         const struct drm_i915_cmd_descriptor *desc =
 902                                 &table->table[j];
 903                         struct cmd_node *desc_node =
 904                                 kmalloc(sizeof(*desc_node), GFP_KERNEL);
 905
 906                         if (!desc_node)
 907                                 return -ENOMEM;
 908
 909                         desc_node->desc = desc;
 910                         hash_add(engine->cmd_hash, &desc_node->node,
 911                                  cmd_header_key(desc->cmd.value));
 912                 }
 913         }
 914
 915         return 0;
 916 }
 917
 918 static void fini_hash_table(struct intel_engine_cs *engine)
 919 {
 920         struct hlist_node *tmp;
 921         struct cmd_node *desc_node;
 922         int i;
 923
 924         hash_for_each_safe(engine->cmd_hash, i, tmp, desc_node, node) {
 925                 hash_del(&desc_node->node);
 926                 kfree(desc_node);
 927         }
 928 }
 929
 930 /**
 931  * intel_engine_init_cmd_parser() - set cmd parser related fields for an engine
 932  * @engine: the engine to initialize
 933  *
 934  * Optionally initializes fields related to batch buffer command parsing in the
 935  * struct intel_engine_cs based on whether the platform requires software
 936  * command parsing.
 937  */
 938 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine)
 939 {
 940         const struct drm_i915_cmd_table *cmd_tables;
 941         int cmd_table_count;
 942         int ret;
 943
 944         if (!IS_GEN(engine->i915, 7) && !(IS_GEN(engine->i915, 9) &&
 945                                           engine->class == COPY_ENGINE_CLASS))
 946                 return;
 947
 948         switch (engine->class) {
 949         case RENDER_CLASS:
 950                 if (IS_HASWELL(engine->i915)) {
 951                         cmd_tables = hsw_render_ring_cmd_table;
 952                         cmd_table_count =
 953                                 ARRAY_SIZE(hsw_render_ring_cmd_table);
 954                 } else {
 955                         cmd_tables = gen7_render_cmd_table;
 956                         cmd_table_count = ARRAY_SIZE(gen7_render_cmd_table);
 957                 }
 958
 959                 if (IS_HASWELL(engine->i915)) {
 960                         engine->reg_tables = hsw_render_reg_tables;
 961                         engine->reg_table_count = ARRAY_SIZE(hsw_render_reg_tables);
 962                 } else {
 963                         engine->reg_tables = ivb_render_reg_tables;
 964                         engine->reg_table_count = ARRAY_SIZE(ivb_render_reg_tables);
 965                 }
 966                 engine->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
 967                 break;
 968         case VIDEO_DECODE_CLASS:
 969                 cmd_tables = gen7_video_cmd_table;
 970                 cmd_table_count = ARRAY_SIZE(gen7_video_cmd_table);
 971                 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
 972                 break;
 973         case COPY_ENGINE_CLASS:
 974                 engine->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
 975                 if (IS_GEN(engine->i915, 9)) {
 976                         cmd_tables = gen9_blt_cmd_table;
 977                         cmd_table_count = ARRAY_SIZE(gen9_blt_cmd_table);
 978                         engine->get_cmd_length_mask =
 979                                 gen9_blt_get_cmd_length_mask;
 980
 981                         /* BCS Engine unsafe without parser */
 982                         engine->flags |= I915_ENGINE_REQUIRES_CMD_PARSER;
 983                 } else if (IS_HASWELL(engine->i915)) {
 984                         cmd_tables = hsw_blt_ring_cmd_table;
 985                         cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmd_table);
 986                 } else {
 987                         cmd_tables = gen7_blt_cmd_table;
 988                         cmd_table_count = ARRAY_SIZE(gen7_blt_cmd_table);
 989                 }
 990
 991                 if (IS_GEN(engine->i915, 9)) {
 992                         engine->reg_tables = gen9_blt_reg_tables;
 993                         engine->reg_table_count =
 994                                 ARRAY_SIZE(gen9_blt_reg_tables);
 995                 } else if (IS_HASWELL(engine->i915)) {
 996                         engine->reg_tables = hsw_blt_reg_tables;
 997                         engine->reg_table_count = ARRAY_SIZE(hsw_blt_reg_tables);
 998                 } else {
 999                         engine->reg_tables = ivb_blt_reg_tables;
1000                         engine->reg_table_count = ARRAY_SIZE(ivb_blt_reg_tables);
1001                 }
1002                 break;
1003         case VIDEO_ENHANCEMENT_CLASS:
1004                 cmd_tables = hsw_vebox_cmd_table;
1005                 cmd_table_count = ARRAY_SIZE(hsw_vebox_cmd_table);
1006                 /* VECS can use the same length_mask function as VCS */
1007                 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
1008                 break;
1009         default:
1010                 MISSING_CASE(engine->class);
1011                 return;
1012         }
1013
1014         if (!validate_cmds_sorted(engine, cmd_tables, cmd_table_count)) {
1015                 drm_err(&engine->i915->drm,
1016                         "%s: command descriptions are not sorted\n",
1017                         engine->name);
1018                 return;
1019         }
1020         if (!validate_regs_sorted(engine)) {
1021                 drm_err(&engine->i915->drm,
1022                         "%s: registers are not sorted\n", engine->name);
1023                 return;
1024         }
1025
1026         ret = init_hash_table(engine, cmd_tables, cmd_table_count);
1027         if (ret) {
1028                 drm_err(&engine->i915->drm,
1029                         "%s: initialised failed!\n", engine->name);
1030                 fini_hash_table(engine);
1031                 return;
1032         }
1033
1034         engine->flags |= I915_ENGINE_USING_CMD_PARSER;
1035 }
1036
1037 /**
1038  * intel_engine_cleanup_cmd_parser() - clean up cmd parser related fields
1039  * @engine: the engine to clean up
1040  *
1041  * Releases any resources related to command parsing that may have been
1042  * initialized for the specified engine.
1043  */
1044 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine)
1045 {
1046         if (!intel_engine_using_cmd_parser(engine))
1047                 return;
1048
1049         fini_hash_table(engine);
1050 }
1051
1052 static const struct drm_i915_cmd_descriptor*
1053 find_cmd_in_table(struct intel_engine_cs *engine,
1054                   u32 cmd_header)
1055 {
1056         struct cmd_node *desc_node;
1057
1058         hash_for_each_possible(engine->cmd_hash, desc_node, node,
1059                                cmd_header_key(cmd_header)) {
1060                 const struct drm_i915_cmd_descriptor *desc = desc_node->desc;
1061                 if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0)
1062                         return desc;
1063         }
1064
1065         return NULL;
1066 }
1067
1068 /*
1069  * Returns a pointer to a descriptor for the command specified by cmd_header.
1070  *
1071  * The caller must supply space for a default descriptor via the default_desc
1072  * parameter. If no descriptor for the specified command exists in the engine's
1073  * command parser tables, this function fills in default_desc based on the
1074  * engine's default length encoding and returns default_desc.
1075  */
1076 static const struct drm_i915_cmd_descriptor*
1077 find_cmd(struct intel_engine_cs *engine,
1078          u32 cmd_header,
1079          const struct drm_i915_cmd_descriptor *desc,
1080          struct drm_i915_cmd_descriptor *default_desc)
1081 {
1082         u32 mask;
1083
1084         if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0)
1085                 return desc;
1086
1087         desc = find_cmd_in_table(engine, cmd_header);
1088         if (desc)
1089                 return desc;
1090
1091         mask = engine->get_cmd_length_mask(cmd_header);
1092         if (!mask)
1093                 return NULL;
1094
1095         default_desc->cmd.value = cmd_header;
1096         default_desc->cmd.mask = ~0u << MIN_OPCODE_SHIFT;
1097         default_desc->length.mask = mask;
1098         default_desc->flags = CMD_DESC_SKIP;
1099         return default_desc;
1100 }
1101
1102 static const struct drm_i915_reg_descriptor *
1103 __find_reg(const struct drm_i915_reg_descriptor *table, int count, u32 addr)
1104 {
1105         int start = 0, end = count;
1106         while (start < end) {
1107                 int mid = start + (end - start) / 2;
1108                 int ret = addr - i915_mmio_reg_offset(table[mid].addr);
1109                 if (ret < 0)
1110                         end = mid;
1111                 else if (ret > 0)
1112                         start = mid + 1;
1113                 else
1114                         return &table[mid];
1115         }
1116         return NULL;
1117 }
1118
1119 static const struct drm_i915_reg_descriptor *
1120 find_reg(const struct intel_engine_cs *engine, u32 addr)
1121 {
1122         const struct drm_i915_reg_table *table = engine->reg_tables;
1123         const struct drm_i915_reg_descriptor *reg = NULL;
1124         int count = engine->reg_table_count;
1125
1126         for (; !reg && (count > 0); ++table, --count)
1127                 reg = __find_reg(table->regs, table->num_regs, addr);
1128
1129         return reg;
1130 }
1131
1132 /* Returns a vmap'd pointer to dst_obj, which the caller must unmap */
1133 static u32 *copy_batch(struct drm_i915_gem_object *dst_obj,
1134                        struct drm_i915_gem_object *src_obj,
1135                        u32 offset, u32 length)
1136 {
1137         bool needs_clflush;
1138         void *dst, *src;
1139         int ret;
1140
1141         dst = i915_gem_object_pin_map(dst_obj, I915_MAP_FORCE_WB);
1142         if (IS_ERR(dst))
1143                 return dst;
1144
1145         ret = i915_gem_object_pin_pages(src_obj);
1146         if (ret) {
1147                 i915_gem_object_unpin_map(dst_obj);
1148                 return ERR_PTR(ret);
1149         }
1150
1151         needs_clflush =
1152                 !(src_obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ);
1153
1154         src = ERR_PTR(-ENODEV);
1155         if (needs_clflush && i915_has_memcpy_from_wc()) {
1156                 src = i915_gem_object_pin_map(src_obj, I915_MAP_WC);
1157                 if (!IS_ERR(src)) {
1158                         i915_unaligned_memcpy_from_wc(dst,
1159                                                       src + offset,
1160                                                       length);
1161                         i915_gem_object_unpin_map(src_obj);
1162                 }
1163         }
1164         if (IS_ERR(src)) {
1165                 void *ptr;
1166                 int x, n;
1167
1168                 /*
1169                  * We can avoid clflushing partial cachelines before the write
1170                  * if we only every write full cache-lines. Since we know that
1171                  * both the source and destination are in multiples of
1172                  * PAGE_SIZE, we can simply round up to the next cacheline.
1173                  * We don't care about copying too much here as we only
1174                  * validate up to the end of the batch.
1175                  */
1176                 if (!(dst_obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ))
1177                         length = round_up(length,
1178                                           boot_cpu_data.x86_clflush_size);
1179
1180                 ptr = dst;
1181                 x = offset_in_page(offset);
1182                 for (n = offset >> PAGE_SHIFT; length; n++) {
1183                         int len = min_t(int, length, PAGE_SIZE - x);
1184
1185                         src = kmap_atomic(i915_gem_object_get_page(src_obj, n));
1186                         if (needs_clflush)
1187                                 drm_clflush_virt_range(src + x, len);
1188                         memcpy(ptr, src + x, len);
1189                         kunmap_atomic(src);
1190
1191                         ptr += len;
1192                         length -= len;
1193                         x = 0;
1194                 }
1195         }
1196
1197         i915_gem_object_unpin_pages(src_obj);
1198
1199         /* dst_obj is returned with vmap pinned */
1200         return dst;
1201 }
1202
1203 static bool check_cmd(const struct intel_engine_cs *engine,
1204                       const struct drm_i915_cmd_descriptor *desc,
1205                       const u32 *cmd, u32 length)
1206 {
1207         if (desc->flags & CMD_DESC_SKIP)
1208                 return true;
1209
1210         if (desc->flags & CMD_DESC_REJECT) {
1211                 DRM_DEBUG("CMD: Rejected command: 0x%08X\n", *cmd);
1212                 return false;
1213         }
1214
1215         if (desc->flags & CMD_DESC_REGISTER) {
1216                 /*
1217                  * Get the distance between individual register offset
1218                  * fields if the command can perform more than one
1219                  * access at a time.
1220                  */
1221                 const u32 step = desc->reg.step ? desc->reg.step : length;
1222                 u32 offset;
1223
1224                 for (offset = desc->reg.offset; offset < length;
1225                      offset += step) {
1226                         const u32 reg_addr = cmd[offset] & desc->reg.mask;
1227                         const struct drm_i915_reg_descriptor *reg =
1228                                 find_reg(engine, reg_addr);
1229
1230                         if (!reg) {
1231                                 DRM_DEBUG("CMD: Rejected register 0x%08X in command: 0x%08X (%s)\n",
1232                                           reg_addr, *cmd, engine->name);
1233                                 return false;
1234                         }
1235
1236                         /*
1237                          * Check the value written to the register against the
1238                          * allowed mask/value pair given in the whitelist entry.
1239                          */
1240                         if (reg->mask) {
1241                                 if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
1242                                         DRM_DEBUG("CMD: Rejected LRM to masked register 0x%08X\n",
1243                                                   reg_addr);
1244                                         return false;
1245                                 }
1246
1247                                 if (desc->cmd.value == MI_LOAD_REGISTER_REG) {
1248                                         DRM_DEBUG("CMD: Rejected LRR to masked register 0x%08X\n",
1249                                                   reg_addr);
1250                                         return false;
1251                                 }
1252
1253                                 if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1) &&
1254                                     (offset + 2 > length ||
1255                                      (cmd[offset + 1] & reg->mask) != reg->value)) {
1256                                         DRM_DEBUG("CMD: Rejected LRI to masked register 0x%08X\n",
1257                                                   reg_addr);
1258                                         return false;
1259                                 }
1260                         }
1261                 }
1262         }
1263
1264         if (desc->flags & CMD_DESC_BITMASK) {
1265                 int i;
1266
1267                 for (i = 0; i < MAX_CMD_DESC_BITMASKS; i++) {
1268                         u32 dword;
1269
1270                         if (desc->bits[i].mask == 0)
1271                                 break;
1272
1273                         if (desc->bits[i].condition_mask != 0) {
1274                                 u32 offset =
1275                                         desc->bits[i].condition_offset;
1276                                 u32 condition = cmd[offset] &
1277                                         desc->bits[i].condition_mask;
1278
1279                                 if (condition == 0)
1280                                         continue;
1281                         }
1282
1283                         if (desc->bits[i].offset >= length) {
1284                                 DRM_DEBUG("CMD: Rejected command 0x%08X, too short to check bitmask (%s)\n",
1285                                           *cmd, engine->name);
1286                                 return false;
1287                         }
1288
1289                         dword = cmd[desc->bits[i].offset] &
1290                                 desc->bits[i].mask;
1291
1292                         if (dword != desc->bits[i].expected) {
1293                                 DRM_DEBUG("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (%s)\n",
1294                                           *cmd,
1295                                           desc->bits[i].mask,
1296                                           desc->bits[i].expected,
1297                                           dword, engine->name);
1298                                 return false;
1299                         }
1300                 }
1301         }
1302
1303         return true;
1304 }
1305
1306 static int check_bbstart(u32 *cmd, u32 offset, u32 length,
1307                          u32 batch_length,
1308                          u64 batch_addr,
1309                          u64 shadow_addr,
1310                          const unsigned long *jump_whitelist)
1311 {
1312         u64 jump_offset, jump_target;
1313         u32 target_cmd_offset, target_cmd_index;
1314
1315         /* For igt compatibility on older platforms */
1316         if (!jump_whitelist) {
1317                 DRM_DEBUG("CMD: Rejecting BB_START for ggtt based submission\n");
1318                 return -EACCES;
1319         }
1320
1321         if (length != 3) {
1322                 DRM_DEBUG("CMD: Recursive BB_START with bad length(%u)\n",
1323                           length);
1324                 return -EINVAL;
1325         }
1326
1327         jump_target = *(u64 *)(cmd + 1);
1328         jump_offset = jump_target - batch_addr;
1329
1330         /*
1331          * Any underflow of jump_target is guaranteed to be outside the range
1332          * of a u32, so >= test catches both too large and too small
1333          */
1334         if (jump_offset >= batch_length) {
1335                 DRM_DEBUG("CMD: BB_START to 0x%llx jumps out of BB\n",
1336                           jump_target);
1337                 return -EINVAL;
1338         }
1339
1340         /*
1341          * This cannot overflow a u32 because we already checked jump_offset
1342          * is within the BB, and the batch_length is a u32
1343          */
1344         target_cmd_offset = lower_32_bits(jump_offset);
1345         target_cmd_index = target_cmd_offset / sizeof(u32);
1346
1347         *(u64 *)(cmd + 1) = shadow_addr + target_cmd_offset;
1348
1349         if (target_cmd_index == offset)
1350                 return 0;
1351
1352         if (IS_ERR(jump_whitelist))
1353                 return PTR_ERR(jump_whitelist);
1354
1355         if (!test_bit(target_cmd_index, jump_whitelist)) {
1356                 DRM_DEBUG("CMD: BB_START to 0x%llx not a previously executed cmd\n",
1357                           jump_target);
1358                 return -EINVAL;
1359         }
1360
1361         return 0;
1362 }
1363
1364 static unsigned long *alloc_whitelist(u32 batch_length)
1365 {
1366         unsigned long *jmp;
1367
1368         /*
1369          * We expect batch_length to be less than 256KiB for known users,
1370          * i.e. we need at most an 8KiB bitmap allocation which should be
1371          * reasonably cheap due to kmalloc caches.
1372          */
1373
1374         /* Prefer to report transient allocation failure rather than hit oom */
1375         jmp = bitmap_zalloc(DIV_ROUND_UP(batch_length, sizeof(u32)),
1376                             GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
1377         if (!jmp)
1378                 return ERR_PTR(-ENOMEM);
1379
1380         return jmp;
1381 }
1382
1383 #define LENGTH_BIAS 2
1384
1385 static bool shadow_needs_clflush(struct drm_i915_gem_object *obj)
1386 {
1387         return !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE);
1388 }
1389
1390 /**
1391  * intel_engine_cmd_parser() - parse a batch buffer for privilege violations
1392  * @engine: the engine on which the batch is to execute
1393  * @batch: the batch buffer in question
1394  * @batch_offset: byte offset in the batch at which execution starts
1395  * @batch_length: length of the commands in batch_obj
1396  * @shadow: validated copy of the batch buffer in question
1397  * @trampoline: whether to emit a conditional trampoline at the end of the batch
1398  *
1399  * Parses the specified batch buffer looking for privilege violations as
1400  * described in the overview.
1401  *
1402  * Return: non-zero if the parser finds violations or otherwise fails; -EACCES
1403  * if the batch appears legal but should use hardware parsing
1404  */
1405 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
1406                             struct i915_vma *batch,
1407                             u32 batch_offset,
1408                             u32 batch_length,
1409                             struct i915_vma *shadow,
1410                             bool trampoline)
1411 {
1412         u32 *cmd, *batch_end, offset = 0;
1413         struct drm_i915_cmd_descriptor default_desc = noop_desc;
1414         const struct drm_i915_cmd_descriptor *desc = &default_desc;
1415         unsigned long *jump_whitelist;
1416         u64 batch_addr, shadow_addr;
1417         int ret = 0;
1418
1419         GEM_BUG_ON(!IS_ALIGNED(batch_offset, sizeof(*cmd)));
1420         GEM_BUG_ON(!IS_ALIGNED(batch_length, sizeof(*cmd)));
1421         GEM_BUG_ON(range_overflows_t(u64, batch_offset, batch_length,
1422                                      batch->size));
1423         GEM_BUG_ON(!batch_length);
1424
1425         cmd = copy_batch(shadow->obj, batch->obj, batch_offset, batch_length);
1426         if (IS_ERR(cmd)) {
1427                 DRM_DEBUG("CMD: Failed to copy batch\n");
1428                 return PTR_ERR(cmd);
1429         }
1430
1431         jump_whitelist = NULL;
1432         if (!trampoline)
1433                 /* Defer failure until attempted use */
1434                 jump_whitelist = alloc_whitelist(batch_length);
1435
1436         shadow_addr = gen8_canonical_addr(shadow->node.start);
1437         batch_addr = gen8_canonical_addr(batch->node.start + batch_offset);
1438
1439         /*
1440          * We use the batch length as size because the shadow object is as
1441          * large or larger and copy_batch() will write MI_NOPs to the extra
1442          * space. Parsing should be faster in some cases this way.
1443          */
1444         batch_end = cmd + batch_length / sizeof(*batch_end);
1445         do {
1446                 u32 length;
1447
1448                 if (*cmd == MI_BATCH_BUFFER_END)
1449                         break;
1450
1451                 desc = find_cmd(engine, *cmd, desc, &default_desc);
1452                 if (!desc) {
1453                         DRM_DEBUG("CMD: Unrecognized command: 0x%08X\n", *cmd);
1454                         ret = -EINVAL;
1455                         break;
1456                 }
1457
1458                 if (desc->flags & CMD_DESC_FIXED)
1459                         length = desc->length.fixed;
1460                 else
1461                         length = (*cmd & desc->length.mask) + LENGTH_BIAS;
1462
1463                 if ((batch_end - cmd) < length) {
1464                         DRM_DEBUG("CMD: Command length exceeds batch length: 0x%08X length=%u batchlen=%td\n",
1465                                   *cmd,
1466                                   length,
1467                                   batch_end - cmd);
1468                         ret = -EINVAL;
1469                         break;
1470                 }
1471
1472                 if (!check_cmd(engine, desc, cmd, length)) {
1473                         ret = -EACCES;
1474                         break;
1475                 }
1476
1477                 if (desc->cmd.value == MI_BATCH_BUFFER_START) {
1478                         ret = check_bbstart(cmd, offset, length, batch_length,
1479                                             batch_addr, shadow_addr,
1480                                             jump_whitelist);
1481                         break;
1482                 }
1483
1484                 if (!IS_ERR_OR_NULL(jump_whitelist))
1485                         __set_bit(offset, jump_whitelist);
1486
1487                 cmd += length;
1488                 offset += length;
1489                 if  (cmd >= batch_end) {
1490                         DRM_DEBUG("CMD: Got to the end of the buffer w/o a BBE cmd!\n");
1491                         ret = -EINVAL;
1492                         break;
1493                 }
1494         } while (1);
1495
1496         if (trampoline) {
1497                 /*
1498                  * With the trampoline, the shadow is executed twice.
1499                  *
1500                  *   1 - starting at offset 0, in privileged mode
1501                  *   2 - starting at offset batch_len, as non-privileged
1502                  *
1503                  * Only if the batch is valid and safe to execute, do we
1504                  * allow the first privileged execution to proceed. If not,
1505                  * we terminate the first batch and use the second batchbuffer
1506                  * entry to chain to the original unsafe non-privileged batch,
1507                  * leaving it to the HW to validate.
1508                  */
1509                 *batch_end = MI_BATCH_BUFFER_END;
1510
1511                 if (ret) {
1512                         /* Batch unsafe to execute with privileges, cancel! */
1513                         cmd = page_mask_bits(shadow->obj->mm.mapping);
1514                         *cmd = MI_BATCH_BUFFER_END;
1515
1516                         /* If batch is unsafe but valid, jump to the original */
1517                         if (ret == -EACCES) {
1518                                 unsigned int flags;
1519
1520                                 flags = MI_BATCH_NON_SECURE_I965;
1521                                 if (IS_HASWELL(engine->i915))
1522                                         flags = MI_BATCH_NON_SECURE_HSW;
1523
1524                                 GEM_BUG_ON(!IS_GEN_RANGE(engine->i915, 6, 7));
1525                                 __gen6_emit_bb_start(batch_end,
1526                                                      batch_addr,
1527                                                      flags);
1528
1529                                 ret = 0; /* allow execution */
1530                         }
1531                 }
1532
1533                 if (shadow_needs_clflush(shadow->obj))
1534                         drm_clflush_virt_range(batch_end, 8);
1535         }
1536
1537         if (shadow_needs_clflush(shadow->obj)) {
1538                 void *ptr = page_mask_bits(shadow->obj->mm.mapping);
1539
1540                 drm_clflush_virt_range(ptr, (void *)(cmd + 1) - ptr);
1541         }
1542
1543         if (!IS_ERR_OR_NULL(jump_whitelist))
1544                 kfree(jump_whitelist);
1545         i915_gem_object_unpin_map(shadow->obj);
1546         return ret;
1547 }
1548
1549 /**
1550  * i915_cmd_parser_get_version() - get the cmd parser version number
1551  * @dev_priv: i915 device private
1552  *
1553  * The cmd parser maintains a simple increasing integer version number suitable
1554  * for passing to userspace clients to determine what operations are permitted.
1555  *
1556  * Return: the current version number of the cmd parser
1557  */
1558 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv)
1559 {
1560         struct intel_engine_cs *engine;
1561         bool active = false;
1562
1563         /* If the command parser is not enabled, report 0 - unsupported */
1564         for_each_uabi_engine(engine, dev_priv) {
1565                 if (intel_engine_using_cmd_parser(engine)) {
1566                         active = true;
1567                         break;
1568                 }
1569         }
1570         if (!active)
1571                 return 0;
1572
1573         /*
1574          * Command parser version history
1575          *
1576          * 1. Initial version. Checks batches and reports violations, but leaves
1577          *    hardware parsing enabled (so does not allow new use cases).
1578          * 2. Allow access to the MI_PREDICATE_SRC0 and
1579          *    MI_PREDICATE_SRC1 registers.
1580          * 3. Allow access to the GPGPU_THREADS_DISPATCHED register.
1581          * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3.
1582          * 5. GPGPU dispatch compute indirect registers.
1583          * 6. TIMESTAMP register and Haswell CS GPR registers
1584          * 7. Allow MI_LOAD_REGISTER_REG between whitelisted registers.
1585          * 8. Don't report cmd_check() failures as EINVAL errors to userspace;
1586          *    rely on the HW to NOOP disallowed commands as it would without
1587          *    the parser enabled.
1588          * 9. Don't whitelist or handle oacontrol specially, as ownership
1589          *    for oacontrol state is moving to i915-perf.
1590          * 10. Support for Gen9 BCS Parsing
1591          */
1592         return 10;
1593 }