drivers/gpu/drm/i915/gvt/scheduler.c

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Zhi Wang <zhi.a.wang@intel.com>
  25  *
  26  * Contributors:
  27  *    Ping Gao <ping.a.gao@intel.com>
  28  *    Tina Zhang <tina.zhang@intel.com>
  29  *    Chanbin Du <changbin.du@intel.com>
  30  *    Min He <min.he@intel.com>
  31  *    Bing Niu <bing.niu@intel.com>
  32  *    Zhenyu Wang <zhenyuw@linux.intel.com>
  33  *
  34  */
  35
  36 #include <linux/kthread.h>
  37
  38 #include "gem/i915_gem_pm.h"
  39 #include "gt/intel_context.h"
  40 #include "gt/intel_ring.h"
  41
  42 #include "i915_drv.h"
  43 #include "i915_gem_gtt.h"
  44 #include "gvt.h"
  45
  46 #define RING_CTX_OFF(x) \
  47         offsetof(struct execlist_ring_context, x)
  48
  49 static void set_context_pdp_root_pointer(
  50                 struct execlist_ring_context *ring_context,
  51                 u32 pdp[8])
  52 {
  53         int i;
  54
  55         for (i = 0; i < 8; i++)
  56                 ring_context->pdps[i].val = pdp[7 - i];
  57 }
  58
  59 static void update_shadow_pdps(struct intel_vgpu_workload *workload)
  60 {
  61         struct drm_i915_gem_object *ctx_obj =
  62                 workload->req->context->state->obj;
  63         struct execlist_ring_context *shadow_ring_context;
  64         struct page *page;
  65
  66         if (WARN_ON(!workload->shadow_mm))
  67                 return;
  68
  69         if (WARN_ON(!atomic_read(&workload->shadow_mm->pincount)))
  70                 return;
  71
  72         page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
  73         shadow_ring_context = kmap(page);
  74         set_context_pdp_root_pointer(shadow_ring_context,
  75                         (void *)workload->shadow_mm->ppgtt_mm.shadow_pdps);
  76         kunmap(page);
  77 }
  78
  79 /*
  80  * when populating shadow ctx from guest, we should not overrride oa related
  81  * registers, so that they will not be overlapped by guest oa configs. Thus
  82  * made it possible to capture oa data from host for both host and guests.
  83  */
  84 static void sr_oa_regs(struct intel_vgpu_workload *workload,
  85                 u32 *reg_state, bool save)
  86 {
  87         struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv;
  88         u32 ctx_oactxctrl = dev_priv->perf.ctx_oactxctrl_offset;
  89         u32 ctx_flexeu0 = dev_priv->perf.ctx_flexeu0_offset;
  90         int i = 0;
  91         u32 flex_mmio[] = {
  92                 i915_mmio_reg_offset(EU_PERF_CNTL0),
  93                 i915_mmio_reg_offset(EU_PERF_CNTL1),
  94                 i915_mmio_reg_offset(EU_PERF_CNTL2),
  95                 i915_mmio_reg_offset(EU_PERF_CNTL3),
  96                 i915_mmio_reg_offset(EU_PERF_CNTL4),
  97                 i915_mmio_reg_offset(EU_PERF_CNTL5),
  98                 i915_mmio_reg_offset(EU_PERF_CNTL6),
  99         };
 100
 101         if (workload->ring_id != RCS0)
 102                 return;
 103
 104         if (save) {
 105                 workload->oactxctrl = reg_state[ctx_oactxctrl + 1];
 106
 107                 for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) {
 108                         u32 state_offset = ctx_flexeu0 + i * 2;
 109
 110                         workload->flex_mmio[i] = reg_state[state_offset + 1];
 111                 }
 112         } else {
 113                 reg_state[ctx_oactxctrl] =
 114                         i915_mmio_reg_offset(GEN8_OACTXCONTROL);
 115                 reg_state[ctx_oactxctrl + 1] = workload->oactxctrl;
 116
 117                 for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) {
 118                         u32 state_offset = ctx_flexeu0 + i * 2;
 119                         u32 mmio = flex_mmio[i];
 120
 121                         reg_state[state_offset] = mmio;
 122                         reg_state[state_offset + 1] = workload->flex_mmio[i];
 123                 }
 124         }
 125 }
 126
 127 static int populate_shadow_context(struct intel_vgpu_workload *workload)
 128 {
 129         struct intel_vgpu *vgpu = workload->vgpu;
 130         struct intel_gvt *gvt = vgpu->gvt;
 131         int ring_id = workload->ring_id;
 132         struct drm_i915_gem_object *ctx_obj =
 133                 workload->req->context->state->obj;
 134         struct execlist_ring_context *shadow_ring_context;
 135         struct page *page;
 136         void *dst;
 137         unsigned long context_gpa, context_page_num;
 138         int i;
 139
 140         page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
 141         shadow_ring_context = kmap(page);
 142
 143         sr_oa_regs(workload, (u32 *)shadow_ring_context, true);
 144 #define COPY_REG(name) \
 145         intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
 146                 + RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
 147 #define COPY_REG_MASKED(name) {\
 148                 intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
 149                                               + RING_CTX_OFF(name.val),\
 150                                               &shadow_ring_context->name.val, 4);\
 151                 shadow_ring_context->name.val |= 0xffff << 16;\
 152         }
 153
 154         COPY_REG_MASKED(ctx_ctrl);
 155         COPY_REG(ctx_timestamp);
 156
 157         if (ring_id == RCS0) {
 158                 COPY_REG(bb_per_ctx_ptr);
 159                 COPY_REG(rcs_indirect_ctx);
 160                 COPY_REG(rcs_indirect_ctx_offset);
 161         }
 162 #undef COPY_REG
 163 #undef COPY_REG_MASKED
 164
 165         intel_gvt_hypervisor_read_gpa(vgpu,
 166                         workload->ring_context_gpa +
 167                         sizeof(*shadow_ring_context),
 168                         (void *)shadow_ring_context +
 169                         sizeof(*shadow_ring_context),
 170                         I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
 171
 172         sr_oa_regs(workload, (u32 *)shadow_ring_context, false);
 173         kunmap(page);
 174
 175         if (IS_RESTORE_INHIBIT(shadow_ring_context->ctx_ctrl.val))
 176                 return 0;
 177
 178         gvt_dbg_sched("ring id %d workload lrca %x", ring_id,
 179                         workload->ctx_desc.lrca);
 180
 181         context_page_num = gvt->dev_priv->engine[ring_id]->context_size;
 182
 183         context_page_num = context_page_num >> PAGE_SHIFT;
 184
 185         if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS0)
 186                 context_page_num = 19;
 187
 188         i = 2;
 189         while (i < context_page_num) {
 190                 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
 191                                 (u32)((workload->ctx_desc.lrca + i) <<
 192                                 I915_GTT_PAGE_SHIFT));
 193                 if (context_gpa == INTEL_GVT_INVALID_ADDR) {
 194                         gvt_vgpu_err("Invalid guest context descriptor\n");
 195                         return -EFAULT;
 196                 }
 197
 198                 page = i915_gem_object_get_page(ctx_obj, i);
 199                 dst = kmap(page);
 200                 intel_gvt_hypervisor_read_gpa(vgpu, context_gpa, dst,
 201                                 I915_GTT_PAGE_SIZE);
 202                 kunmap(page);
 203                 i++;
 204         }
 205         return 0;
 206 }
 207
 208 static inline bool is_gvt_request(struct i915_request *rq)
 209 {
 210         return intel_context_force_single_submission(rq->context);
 211 }
 212
 213 static void save_ring_hw_state(struct intel_vgpu *vgpu, int ring_id)
 214 {
 215         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 216         u32 ring_base = dev_priv->engine[ring_id]->mmio_base;
 217         i915_reg_t reg;
 218
 219         reg = RING_INSTDONE(ring_base);
 220         vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
 221         reg = RING_ACTHD(ring_base);
 222         vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
 223         reg = RING_ACTHD_UDW(ring_base);
 224         vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
 225 }
 226
 227 static int shadow_context_status_change(struct notifier_block *nb,
 228                 unsigned long action, void *data)
 229 {
 230         struct i915_request *req = data;
 231         struct intel_gvt *gvt = container_of(nb, struct intel_gvt,
 232                                 shadow_ctx_notifier_block[req->engine->id]);
 233         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 234         enum intel_engine_id ring_id = req->engine->id;
 235         struct intel_vgpu_workload *workload;
 236         unsigned long flags;
 237
 238         if (!is_gvt_request(req)) {
 239                 spin_lock_irqsave(&scheduler->mmio_context_lock, flags);
 240                 if (action == INTEL_CONTEXT_SCHEDULE_IN &&
 241                     scheduler->engine_owner[ring_id]) {
 242                         /* Switch ring from vGPU to host. */
 243                         intel_gvt_switch_mmio(scheduler->engine_owner[ring_id],
 244                                               NULL, ring_id);
 245                         scheduler->engine_owner[ring_id] = NULL;
 246                 }
 247                 spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags);
 248
 249                 return NOTIFY_OK;
 250         }
 251
 252         workload = scheduler->current_workload[ring_id];
 253         if (unlikely(!workload))
 254                 return NOTIFY_OK;
 255
 256         switch (action) {
 257         case INTEL_CONTEXT_SCHEDULE_IN:
 258                 spin_lock_irqsave(&scheduler->mmio_context_lock, flags);
 259                 if (workload->vgpu != scheduler->engine_owner[ring_id]) {
 260                         /* Switch ring from host to vGPU or vGPU to vGPU. */
 261                         intel_gvt_switch_mmio(scheduler->engine_owner[ring_id],
 262                                               workload->vgpu, ring_id);
 263                         scheduler->engine_owner[ring_id] = workload->vgpu;
 264                 } else
 265                         gvt_dbg_sched("skip ring %d mmio switch for vgpu%d\n",
 266                                       ring_id, workload->vgpu->id);
 267                 spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags);
 268                 atomic_set(&workload->shadow_ctx_active, 1);
 269                 break;
 270         case INTEL_CONTEXT_SCHEDULE_OUT:
 271                 save_ring_hw_state(workload->vgpu, ring_id);
 272                 atomic_set(&workload->shadow_ctx_active, 0);
 273                 break;
 274         case INTEL_CONTEXT_SCHEDULE_PREEMPTED:
 275                 save_ring_hw_state(workload->vgpu, ring_id);
 276                 break;
 277         default:
 278                 WARN_ON(1);
 279                 return NOTIFY_OK;
 280         }
 281         wake_up(&workload->shadow_ctx_status_wq);
 282         return NOTIFY_OK;
 283 }
 284
 285 static void
 286 shadow_context_descriptor_update(struct intel_context *ce,
 287                                  struct intel_vgpu_workload *workload)
 288 {
 289         u64 desc = ce->lrc_desc;
 290
 291         /*
 292          * Update bits 0-11 of the context descriptor which includes flags
 293          * like GEN8_CTX_* cached in desc_template
 294          */
 295         desc &= ~(0x3 << GEN8_CTX_ADDRESSING_MODE_SHIFT);
 296         desc |= workload->ctx_desc.addressing_mode <<
 297                 GEN8_CTX_ADDRESSING_MODE_SHIFT;
 298
 299         ce->lrc_desc = desc;
 300 }
 301
 302 static int copy_workload_to_ring_buffer(struct intel_vgpu_workload *workload)
 303 {
 304         struct intel_vgpu *vgpu = workload->vgpu;
 305         struct i915_request *req = workload->req;
 306         void *shadow_ring_buffer_va;
 307         u32 *cs;
 308         int err;
 309
 310         if (IS_GEN(req->i915, 9) && is_inhibit_context(req->context))
 311                 intel_vgpu_restore_inhibit_context(vgpu, req);
 312
 313         /*
 314          * To track whether a request has started on HW, we can emit a
 315          * breadcrumb at the beginning of the request and check its
 316          * timeline's HWSP to see if the breadcrumb has advanced past the
 317          * start of this request. Actually, the request must have the
 318          * init_breadcrumb if its timeline set has_init_bread_crumb, or the
 319          * scheduler might get a wrong state of it during reset. Since the
 320          * requests from gvt always set the has_init_breadcrumb flag, here
 321          * need to do the emit_init_breadcrumb for all the requests.
 322          */
 323         if (req->engine->emit_init_breadcrumb) {
 324                 err = req->engine->emit_init_breadcrumb(req);
 325                 if (err) {
 326                         gvt_vgpu_err("fail to emit init breadcrumb\n");
 327                         return err;
 328                 }
 329         }
 330
 331         /* allocate shadow ring buffer */
 332         cs = intel_ring_begin(workload->req, workload->rb_len / sizeof(u32));
 333         if (IS_ERR(cs)) {
 334                 gvt_vgpu_err("fail to alloc size =%ld shadow  ring buffer\n",
 335                         workload->rb_len);
 336                 return PTR_ERR(cs);
 337         }
 338
 339         shadow_ring_buffer_va = workload->shadow_ring_buffer_va;
 340
 341         /* get shadow ring buffer va */
 342         workload->shadow_ring_buffer_va = cs;
 343
 344         memcpy(cs, shadow_ring_buffer_va,
 345                         workload->rb_len);
 346
 347         cs += workload->rb_len / sizeof(u32);
 348         intel_ring_advance(workload->req, cs);
 349
 350         return 0;
 351 }
 352
 353 static void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
 354 {
 355         if (!wa_ctx->indirect_ctx.obj)
 356                 return;
 357
 358         i915_gem_object_unpin_map(wa_ctx->indirect_ctx.obj);
 359         i915_gem_object_put(wa_ctx->indirect_ctx.obj);
 360
 361         wa_ctx->indirect_ctx.obj = NULL;
 362         wa_ctx->indirect_ctx.shadow_va = NULL;
 363 }
 364
 365 static void set_context_ppgtt_from_shadow(struct intel_vgpu_workload *workload,
 366                                           struct intel_context *ce)
 367 {
 368         struct intel_vgpu_mm *mm = workload->shadow_mm;
 369         struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(ce->vm);
 370         int i = 0;
 371
 372         if (mm->ppgtt_mm.root_entry_type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
 373                 px_dma(ppgtt->pd) = mm->ppgtt_mm.shadow_pdps[0];
 374         } else {
 375                 for (i = 0; i < GVT_RING_CTX_NR_PDPS; i++) {
 376                         struct i915_page_directory * const pd =
 377                                 i915_pd_entry(ppgtt->pd, i);
 378
 379                         px_dma(pd) = mm->ppgtt_mm.shadow_pdps[i];
 380                 }
 381         }
 382 }
 383
 384 static int
 385 intel_gvt_workload_req_alloc(struct intel_vgpu_workload *workload)
 386 {
 387         struct intel_vgpu *vgpu = workload->vgpu;
 388         struct intel_vgpu_submission *s = &vgpu->submission;
 389         struct i915_request *rq;
 390
 391         if (workload->req)
 392                 return 0;
 393
 394         rq = i915_request_create(s->shadow[workload->ring_id]);
 395         if (IS_ERR(rq)) {
 396                 gvt_vgpu_err("fail to allocate gem request\n");
 397                 return PTR_ERR(rq);
 398         }
 399
 400         workload->req = i915_request_get(rq);
 401         return 0;
 402 }
 403
 404 /**
 405  * intel_gvt_scan_and_shadow_workload - audit the workload by scanning and
 406  * shadow it as well, include ringbuffer,wa_ctx and ctx.
 407  * @workload: an abstract entity for each execlist submission.
 408  *
 409  * This function is called before the workload submitting to i915, to make
 410  * sure the content of the workload is valid.
 411  */
 412 int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload)
 413 {
 414         struct intel_vgpu *vgpu = workload->vgpu;
 415         struct intel_vgpu_submission *s = &vgpu->submission;
 416         int ret;
 417
 418         lockdep_assert_held(&vgpu->vgpu_lock);
 419
 420         if (workload->shadow)
 421                 return 0;
 422
 423         if (!test_and_set_bit(workload->ring_id, s->shadow_ctx_desc_updated))
 424                 shadow_context_descriptor_update(s->shadow[workload->ring_id],
 425                                                  workload);
 426
 427         ret = intel_gvt_scan_and_shadow_ringbuffer(workload);
 428         if (ret)
 429                 return ret;
 430
 431         if (workload->ring_id == RCS0 && workload->wa_ctx.indirect_ctx.size) {
 432                 ret = intel_gvt_scan_and_shadow_wa_ctx(&workload->wa_ctx);
 433                 if (ret)
 434                         goto err_shadow;
 435         }
 436
 437         workload->shadow = true;
 438         return 0;
 439 err_shadow:
 440         release_shadow_wa_ctx(&workload->wa_ctx);
 441         return ret;
 442 }
 443
 444 static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload);
 445
 446 static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload)
 447 {
 448         struct intel_gvt *gvt = workload->vgpu->gvt;
 449         const int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
 450         struct intel_vgpu_shadow_bb *bb;
 451         int ret;
 452
 453         list_for_each_entry(bb, &workload->shadow_bb, list) {
 454                 /* For privilge batch buffer and not wa_ctx, the bb_start_cmd_va
 455                  * is only updated into ring_scan_buffer, not real ring address
 456                  * allocated in later copy_workload_to_ring_buffer. pls be noted
 457                  * shadow_ring_buffer_va is now pointed to real ring buffer va
 458                  * in copy_workload_to_ring_buffer.
 459                  */
 460
 461                 if (bb->bb_offset)
 462                         bb->bb_start_cmd_va = workload->shadow_ring_buffer_va
 463                                 + bb->bb_offset;
 464
 465                 if (bb->ppgtt) {
 466                         /* for non-priv bb, scan&shadow is only for
 467                          * debugging purpose, so the content of shadow bb
 468                          * is the same as original bb. Therefore,
 469                          * here, rather than switch to shadow bb's gma
 470                          * address, we directly use original batch buffer's
 471                          * gma address, and send original bb to hardware
 472                          * directly
 473                          */
 474                         if (bb->clflush & CLFLUSH_AFTER) {
 475                                 drm_clflush_virt_range(bb->va,
 476                                                 bb->obj->base.size);
 477                                 bb->clflush &= ~CLFLUSH_AFTER;
 478                         }
 479                         i915_gem_object_finish_access(bb->obj);
 480                         bb->accessing = false;
 481
 482                 } else {
 483                         bb->vma = i915_gem_object_ggtt_pin(bb->obj,
 484                                         NULL, 0, 0, 0);
 485                         if (IS_ERR(bb->vma)) {
 486                                 ret = PTR_ERR(bb->vma);
 487                                 goto err;
 488                         }
 489
 490                         /* relocate shadow batch buffer */
 491                         bb->bb_start_cmd_va[1] = i915_ggtt_offset(bb->vma);
 492                         if (gmadr_bytes == 8)
 493                                 bb->bb_start_cmd_va[2] = 0;
 494
 495                         /* No one is going to touch shadow bb from now on. */
 496                         if (bb->clflush & CLFLUSH_AFTER) {
 497                                 drm_clflush_virt_range(bb->va,
 498                                                 bb->obj->base.size);
 499                                 bb->clflush &= ~CLFLUSH_AFTER;
 500                         }
 501
 502                         ret = i915_gem_object_set_to_gtt_domain(bb->obj,
 503                                                                 false);
 504                         if (ret)
 505                                 goto err;
 506
 507                         ret = i915_vma_move_to_active(bb->vma,
 508                                                       workload->req,
 509                                                       0);
 510                         if (ret)
 511                                 goto err;
 512
 513                         i915_gem_object_finish_access(bb->obj);
 514                         bb->accessing = false;
 515                 }
 516         }
 517         return 0;
 518 err:
 519         release_shadow_batch_buffer(workload);
 520         return ret;
 521 }
 522
 523 static void update_wa_ctx_2_shadow_ctx(struct intel_shadow_wa_ctx *wa_ctx)
 524 {
 525         struct intel_vgpu_workload *workload =
 526                 container_of(wa_ctx, struct intel_vgpu_workload, wa_ctx);
 527         struct i915_request *rq = workload->req;
 528         struct execlist_ring_context *shadow_ring_context =
 529                 (struct execlist_ring_context *)rq->context->lrc_reg_state;
 530
 531         shadow_ring_context->bb_per_ctx_ptr.val =
 532                 (shadow_ring_context->bb_per_ctx_ptr.val &
 533                 (~PER_CTX_ADDR_MASK)) | wa_ctx->per_ctx.shadow_gma;
 534         shadow_ring_context->rcs_indirect_ctx.val =
 535                 (shadow_ring_context->rcs_indirect_ctx.val &
 536                 (~INDIRECT_CTX_ADDR_MASK)) | wa_ctx->indirect_ctx.shadow_gma;
 537 }
 538
 539 static int prepare_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
 540 {
 541         struct i915_vma *vma;
 542         unsigned char *per_ctx_va =
 543                 (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
 544                 wa_ctx->indirect_ctx.size;
 545
 546         if (wa_ctx->indirect_ctx.size == 0)
 547                 return 0;
 548
 549         vma = i915_gem_object_ggtt_pin(wa_ctx->indirect_ctx.obj, NULL,
 550                                        0, CACHELINE_BYTES, 0);
 551         if (IS_ERR(vma))
 552                 return PTR_ERR(vma);
 553
 554         /* FIXME: we are not tracking our pinned VMA leaving it
 555          * up to the core to fix up the stray pin_count upon
 556          * free.
 557          */
 558
 559         wa_ctx->indirect_ctx.shadow_gma = i915_ggtt_offset(vma);
 560
 561         wa_ctx->per_ctx.shadow_gma = *((unsigned int *)per_ctx_va + 1);
 562         memset(per_ctx_va, 0, CACHELINE_BYTES);
 563
 564         update_wa_ctx_2_shadow_ctx(wa_ctx);
 565         return 0;
 566 }
 567
 568 static void update_vreg_in_ctx(struct intel_vgpu_workload *workload)
 569 {
 570         struct intel_vgpu *vgpu = workload->vgpu;
 571         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 572         u32 ring_base;
 573
 574         ring_base = dev_priv->engine[workload->ring_id]->mmio_base;
 575         vgpu_vreg_t(vgpu, RING_START(ring_base)) = workload->rb_start;
 576 }
 577
 578 static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload)
 579 {
 580         struct intel_vgpu_shadow_bb *bb, *pos;
 581
 582         if (list_empty(&workload->shadow_bb))
 583                 return;
 584
 585         bb = list_first_entry(&workload->shadow_bb,
 586                         struct intel_vgpu_shadow_bb, list);
 587
 588         list_for_each_entry_safe(bb, pos, &workload->shadow_bb, list) {
 589                 if (bb->obj) {
 590                         if (bb->accessing)
 591                                 i915_gem_object_finish_access(bb->obj);
 592
 593                         if (bb->va && !IS_ERR(bb->va))
 594                                 i915_gem_object_unpin_map(bb->obj);
 595
 596                         if (bb->vma && !IS_ERR(bb->vma)) {
 597                                 i915_vma_unpin(bb->vma);
 598                                 i915_vma_close(bb->vma);
 599                         }
 600                         i915_gem_object_put(bb->obj);
 601                 }
 602                 list_del(&bb->list);
 603                 kfree(bb);
 604         }
 605 }
 606
 607 static int prepare_workload(struct intel_vgpu_workload *workload)
 608 {
 609         struct intel_vgpu *vgpu = workload->vgpu;
 610         struct intel_vgpu_submission *s = &vgpu->submission;
 611         int ring = workload->ring_id;
 612         int ret = 0;
 613
 614         ret = intel_vgpu_pin_mm(workload->shadow_mm);
 615         if (ret) {
 616                 gvt_vgpu_err("fail to vgpu pin mm\n");
 617                 return ret;
 618         }
 619
 620         if (workload->shadow_mm->type != INTEL_GVT_MM_PPGTT ||
 621             !workload->shadow_mm->ppgtt_mm.shadowed) {
 622                 gvt_vgpu_err("workload shadow ppgtt isn't ready\n");
 623                 return -EINVAL;
 624         }
 625
 626         update_shadow_pdps(workload);
 627
 628         set_context_ppgtt_from_shadow(workload, s->shadow[ring]);
 629
 630         ret = intel_vgpu_sync_oos_pages(workload->vgpu);
 631         if (ret) {
 632                 gvt_vgpu_err("fail to vgpu sync oos pages\n");
 633                 goto err_unpin_mm;
 634         }
 635
 636         ret = intel_vgpu_flush_post_shadow(workload->vgpu);
 637         if (ret) {
 638                 gvt_vgpu_err("fail to flush post shadow\n");
 639                 goto err_unpin_mm;
 640         }
 641
 642         ret = copy_workload_to_ring_buffer(workload);
 643         if (ret) {
 644                 gvt_vgpu_err("fail to generate request\n");
 645                 goto err_unpin_mm;
 646         }
 647
 648         ret = prepare_shadow_batch_buffer(workload);
 649         if (ret) {
 650                 gvt_vgpu_err("fail to prepare_shadow_batch_buffer\n");
 651                 goto err_unpin_mm;
 652         }
 653
 654         ret = prepare_shadow_wa_ctx(&workload->wa_ctx);
 655         if (ret) {
 656                 gvt_vgpu_err("fail to prepare_shadow_wa_ctx\n");
 657                 goto err_shadow_batch;
 658         }
 659
 660         if (workload->prepare) {
 661                 ret = workload->prepare(workload);
 662                 if (ret)
 663                         goto err_shadow_wa_ctx;
 664         }
 665
 666         return 0;
 667 err_shadow_wa_ctx:
 668         release_shadow_wa_ctx(&workload->wa_ctx);
 669 err_shadow_batch:
 670         release_shadow_batch_buffer(workload);
 671 err_unpin_mm:
 672         intel_vgpu_unpin_mm(workload->shadow_mm);
 673         return ret;
 674 }
 675
 676 static int dispatch_workload(struct intel_vgpu_workload *workload)
 677 {
 678         struct intel_vgpu *vgpu = workload->vgpu;
 679         struct i915_request *rq;
 680         int ring_id = workload->ring_id;
 681         int ret;
 682
 683         gvt_dbg_sched("ring id %d prepare to dispatch workload %p\n",
 684                 ring_id, workload);
 685
 686         mutex_lock(&vgpu->vgpu_lock);
 687
 688         ret = intel_gvt_workload_req_alloc(workload);
 689         if (ret)
 690                 goto err_req;
 691
 692         ret = intel_gvt_scan_and_shadow_workload(workload);
 693         if (ret)
 694                 goto out;
 695
 696         ret = populate_shadow_context(workload);
 697         if (ret) {
 698                 release_shadow_wa_ctx(&workload->wa_ctx);
 699                 goto out;
 700         }
 701
 702         ret = prepare_workload(workload);
 703 out:
 704         if (ret) {
 705                 /* We might still need to add request with
 706                  * clean ctx to retire it properly..
 707                  */
 708                 rq = fetch_and_zero(&workload->req);
 709                 i915_request_put(rq);
 710         }
 711
 712         if (!IS_ERR_OR_NULL(workload->req)) {
 713                 gvt_dbg_sched("ring id %d submit workload to i915 %p\n",
 714                                 ring_id, workload->req);
 715                 i915_request_add(workload->req);
 716                 workload->dispatched = true;
 717         }
 718 err_req:
 719         if (ret)
 720                 workload->status = ret;
 721         mutex_unlock(&vgpu->vgpu_lock);
 722         return ret;
 723 }
 724
 725 static struct intel_vgpu_workload *pick_next_workload(
 726                 struct intel_gvt *gvt, int ring_id)
 727 {
 728         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 729         struct intel_vgpu_workload *workload = NULL;
 730
 731         mutex_lock(&gvt->sched_lock);
 732
 733         /*
 734          * no current vgpu / will be scheduled out / no workload
 735          * bail out
 736          */
 737         if (!scheduler->current_vgpu) {
 738                 gvt_dbg_sched("ring id %d stop - no current vgpu\n", ring_id);
 739                 goto out;
 740         }
 741
 742         if (scheduler->need_reschedule) {
 743                 gvt_dbg_sched("ring id %d stop - will reschedule\n", ring_id);
 744                 goto out;
 745         }
 746
 747         if (!scheduler->current_vgpu->active ||
 748             list_empty(workload_q_head(scheduler->current_vgpu, ring_id)))
 749                 goto out;
 750
 751         /*
 752          * still have current workload, maybe the workload disptacher
 753          * fail to submit it for some reason, resubmit it.
 754          */
 755         if (scheduler->current_workload[ring_id]) {
 756                 workload = scheduler->current_workload[ring_id];
 757                 gvt_dbg_sched("ring id %d still have current workload %p\n",
 758                                 ring_id, workload);
 759                 goto out;
 760         }
 761
 762         /*
 763          * pick a workload as current workload
 764          * once current workload is set, schedule policy routines
 765          * will wait the current workload is finished when trying to
 766          * schedule out a vgpu.
 767          */
 768         scheduler->current_workload[ring_id] = container_of(
 769                         workload_q_head(scheduler->current_vgpu, ring_id)->next,
 770                         struct intel_vgpu_workload, list);
 771
 772         workload = scheduler->current_workload[ring_id];
 773
 774         gvt_dbg_sched("ring id %d pick new workload %p\n", ring_id, workload);
 775
 776         atomic_inc(&workload->vgpu->submission.running_workload_num);
 777 out:
 778         mutex_unlock(&gvt->sched_lock);
 779         return workload;
 780 }
 781
 782 static void update_guest_context(struct intel_vgpu_workload *workload)
 783 {
 784         struct i915_request *rq = workload->req;
 785         struct intel_vgpu *vgpu = workload->vgpu;
 786         struct intel_gvt *gvt = vgpu->gvt;
 787         struct drm_i915_gem_object *ctx_obj = rq->context->state->obj;
 788         struct execlist_ring_context *shadow_ring_context;
 789         struct page *page;
 790         void *src;
 791         unsigned long context_gpa, context_page_num;
 792         int i;
 793         struct drm_i915_private *dev_priv = gvt->dev_priv;
 794         u32 ring_base;
 795         u32 head, tail;
 796         u16 wrap_count;
 797
 798         gvt_dbg_sched("ring id %d workload lrca %x\n", rq->engine->id,
 799                       workload->ctx_desc.lrca);
 800
 801         head = workload->rb_head;
 802         tail = workload->rb_tail;
 803         wrap_count = workload->guest_rb_head >> RB_HEAD_WRAP_CNT_OFF;
 804
 805         if (tail < head) {
 806                 if (wrap_count == RB_HEAD_WRAP_CNT_MAX)
 807                         wrap_count = 0;
 808                 else
 809                         wrap_count += 1;
 810         }
 811
 812         head = (wrap_count << RB_HEAD_WRAP_CNT_OFF) | tail;
 813
 814         ring_base = dev_priv->engine[workload->ring_id]->mmio_base;
 815         vgpu_vreg_t(vgpu, RING_TAIL(ring_base)) = tail;
 816         vgpu_vreg_t(vgpu, RING_HEAD(ring_base)) = head;
 817
 818         context_page_num = rq->engine->context_size;
 819         context_page_num = context_page_num >> PAGE_SHIFT;
 820
 821         if (IS_BROADWELL(gvt->dev_priv) && rq->engine->id == RCS0)
 822                 context_page_num = 19;
 823
 824         i = 2;
 825
 826         while (i < context_page_num) {
 827                 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
 828                                 (u32)((workload->ctx_desc.lrca + i) <<
 829                                         I915_GTT_PAGE_SHIFT));
 830                 if (context_gpa == INTEL_GVT_INVALID_ADDR) {
 831                         gvt_vgpu_err("invalid guest context descriptor\n");
 832                         return;
 833                 }
 834
 835                 page = i915_gem_object_get_page(ctx_obj, i);
 836                 src = kmap(page);
 837                 intel_gvt_hypervisor_write_gpa(vgpu, context_gpa, src,
 838                                 I915_GTT_PAGE_SIZE);
 839                 kunmap(page);
 840                 i++;
 841         }
 842
 843         intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa +
 844                 RING_CTX_OFF(ring_header.val), &workload->rb_tail, 4);
 845
 846         page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
 847         shadow_ring_context = kmap(page);
 848
 849 #define COPY_REG(name) \
 850         intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + \
 851                 RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
 852
 853         COPY_REG(ctx_ctrl);
 854         COPY_REG(ctx_timestamp);
 855
 856 #undef COPY_REG
 857
 858         intel_gvt_hypervisor_write_gpa(vgpu,
 859                         workload->ring_context_gpa +
 860                         sizeof(*shadow_ring_context),
 861                         (void *)shadow_ring_context +
 862                         sizeof(*shadow_ring_context),
 863                         I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
 864
 865         kunmap(page);
 866 }
 867
 868 void intel_vgpu_clean_workloads(struct intel_vgpu *vgpu,
 869                                 intel_engine_mask_t engine_mask)
 870 {
 871         struct intel_vgpu_submission *s = &vgpu->submission;
 872         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 873         struct intel_engine_cs *engine;
 874         struct intel_vgpu_workload *pos, *n;
 875         intel_engine_mask_t tmp;
 876
 877         /* free the unsubmited workloads in the queues. */
 878         for_each_engine_masked(engine, &dev_priv->gt, engine_mask, tmp) {
 879                 list_for_each_entry_safe(pos, n,
 880                         &s->workload_q_head[engine->id], list) {
 881                         list_del_init(&pos->list);
 882                         intel_vgpu_destroy_workload(pos);
 883                 }
 884                 clear_bit(engine->id, s->shadow_ctx_desc_updated);
 885         }
 886 }
 887
 888 static void complete_current_workload(struct intel_gvt *gvt, int ring_id)
 889 {
 890         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 891         struct intel_vgpu_workload *workload =
 892                 scheduler->current_workload[ring_id];
 893         struct intel_vgpu *vgpu = workload->vgpu;
 894         struct intel_vgpu_submission *s = &vgpu->submission;
 895         struct i915_request *rq = workload->req;
 896         int event;
 897
 898         mutex_lock(&vgpu->vgpu_lock);
 899         mutex_lock(&gvt->sched_lock);
 900
 901         /* For the workload w/ request, needs to wait for the context
 902          * switch to make sure request is completed.
 903          * For the workload w/o request, directly complete the workload.
 904          */
 905         if (rq) {
 906                 wait_event(workload->shadow_ctx_status_wq,
 907                            !atomic_read(&workload->shadow_ctx_active));
 908
 909                 /* If this request caused GPU hang, req->fence.error will
 910                  * be set to -EIO. Use -EIO to set workload status so
 911                  * that when this request caused GPU hang, didn't trigger
 912                  * context switch interrupt to guest.
 913                  */
 914                 if (likely(workload->status == -EINPROGRESS)) {
 915                         if (workload->req->fence.error == -EIO)
 916                                 workload->status = -EIO;
 917                         else
 918                                 workload->status = 0;
 919                 }
 920
 921                 if (!workload->status &&
 922                     !(vgpu->resetting_eng & BIT(ring_id))) {
 923                         update_guest_context(workload);
 924
 925                         for_each_set_bit(event, workload->pending_events,
 926                                          INTEL_GVT_EVENT_MAX)
 927                                 intel_vgpu_trigger_virtual_event(vgpu, event);
 928                 }
 929
 930                 i915_request_put(fetch_and_zero(&workload->req));
 931         }
 932
 933         gvt_dbg_sched("ring id %d complete workload %p status %d\n",
 934                         ring_id, workload, workload->status);
 935
 936         scheduler->current_workload[ring_id] = NULL;
 937
 938         list_del_init(&workload->list);
 939
 940         if (workload->status || vgpu->resetting_eng & BIT(ring_id)) {
 941                 /* if workload->status is not successful means HW GPU
 942                  * has occurred GPU hang or something wrong with i915/GVT,
 943                  * and GVT won't inject context switch interrupt to guest.
 944                  * So this error is a vGPU hang actually to the guest.
 945                  * According to this we should emunlate a vGPU hang. If
 946                  * there are pending workloads which are already submitted
 947                  * from guest, we should clean them up like HW GPU does.
 948                  *
 949                  * if it is in middle of engine resetting, the pending
 950                  * workloads won't be submitted to HW GPU and will be
 951                  * cleaned up during the resetting process later, so doing
 952                  * the workload clean up here doesn't have any impact.
 953                  **/
 954                 intel_vgpu_clean_workloads(vgpu, BIT(ring_id));
 955         }
 956
 957         workload->complete(workload);
 958
 959         atomic_dec(&s->running_workload_num);
 960         wake_up(&scheduler->workload_complete_wq);
 961
 962         if (gvt->scheduler.need_reschedule)
 963                 intel_gvt_request_service(gvt, INTEL_GVT_REQUEST_EVENT_SCHED);
 964
 965         mutex_unlock(&gvt->sched_lock);
 966         mutex_unlock(&vgpu->vgpu_lock);
 967 }
 968
 969 struct workload_thread_param {
 970         struct intel_gvt *gvt;
 971         int ring_id;
 972 };
 973
 974 static int workload_thread(void *priv)
 975 {
 976         struct workload_thread_param *p = (struct workload_thread_param *)priv;
 977         struct intel_gvt *gvt = p->gvt;
 978         int ring_id = p->ring_id;
 979         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 980         struct intel_vgpu_workload *workload = NULL;
 981         struct intel_vgpu *vgpu = NULL;
 982         int ret;
 983         bool need_force_wake = (INTEL_GEN(gvt->dev_priv) >= 9);
 984         DEFINE_WAIT_FUNC(wait, woken_wake_function);
 985         struct intel_runtime_pm *rpm = &gvt->dev_priv->runtime_pm;
 986
 987         kfree(p);
 988
 989         gvt_dbg_core("workload thread for ring %d started\n", ring_id);
 990
 991         while (!kthread_should_stop()) {
 992                 add_wait_queue(&scheduler->waitq[ring_id], &wait);
 993                 do {
 994                         workload = pick_next_workload(gvt, ring_id);
 995                         if (workload)
 996                                 break;
 997                         wait_woken(&wait, TASK_INTERRUPTIBLE,
 998                                    MAX_SCHEDULE_TIMEOUT);
 999                 } while (!kthread_should_stop());
1000                 remove_wait_queue(&scheduler->waitq[ring_id], &wait);
1001
1002                 if (!workload)
1003                         break;
1004
1005                 gvt_dbg_sched("ring id %d next workload %p vgpu %d\n",
1006                                 workload->ring_id, workload,
1007                                 workload->vgpu->id);
1008
1009                 intel_runtime_pm_get(rpm);
1010
1011                 gvt_dbg_sched("ring id %d will dispatch workload %p\n",
1012                                 workload->ring_id, workload);
1013
1014                 if (need_force_wake)
1015                         intel_uncore_forcewake_get(&gvt->dev_priv->uncore,
1016                                         FORCEWAKE_ALL);
1017                 /*
1018                  * Update the vReg of the vGPU which submitted this
1019                  * workload. The vGPU may use these registers for checking
1020                  * the context state. The value comes from GPU commands
1021                  * in this workload.
1022                  */
1023                 update_vreg_in_ctx(workload);
1024
1025                 ret = dispatch_workload(workload);
1026
1027                 if (ret) {
1028                         vgpu = workload->vgpu;
1029                         gvt_vgpu_err("fail to dispatch workload, skip\n");
1030                         goto complete;
1031                 }
1032
1033                 gvt_dbg_sched("ring id %d wait workload %p\n",
1034                                 workload->ring_id, workload);
1035                 i915_request_wait(workload->req, 0, MAX_SCHEDULE_TIMEOUT);
1036
1037 complete:
1038                 gvt_dbg_sched("will complete workload %p, status: %d\n",
1039                                 workload, workload->status);
1040
1041                 complete_current_workload(gvt, ring_id);
1042
1043                 if (need_force_wake)
1044                         intel_uncore_forcewake_put(&gvt->dev_priv->uncore,
1045                                         FORCEWAKE_ALL);
1046
1047                 intel_runtime_pm_put_unchecked(rpm);
1048                 if (ret && (vgpu_is_vm_unhealthy(ret)))
1049                         enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR);
1050         }
1051         return 0;
1052 }
1053
1054 void intel_gvt_wait_vgpu_idle(struct intel_vgpu *vgpu)
1055 {
1056         struct intel_vgpu_submission *s = &vgpu->submission;
1057         struct intel_gvt *gvt = vgpu->gvt;
1058         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1059
1060         if (atomic_read(&s->running_workload_num)) {
1061                 gvt_dbg_sched("wait vgpu idle\n");
1062
1063                 wait_event(scheduler->workload_complete_wq,
1064                                 !atomic_read(&s->running_workload_num));
1065         }
1066 }
1067
1068 void intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt)
1069 {
1070         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1071         struct intel_engine_cs *engine;
1072         enum intel_engine_id i;
1073
1074         gvt_dbg_core("clean workload scheduler\n");
1075
1076         for_each_engine(engine, gvt->dev_priv, i) {
1077                 atomic_notifier_chain_unregister(
1078                                         &engine->context_status_notifier,
1079                                         &gvt->shadow_ctx_notifier_block[i]);
1080                 kthread_stop(scheduler->thread[i]);
1081         }
1082 }
1083
1084 int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt)
1085 {
1086         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1087         struct workload_thread_param *param = NULL;
1088         struct intel_engine_cs *engine;
1089         enum intel_engine_id i;
1090         int ret;
1091
1092         gvt_dbg_core("init workload scheduler\n");
1093
1094         init_waitqueue_head(&scheduler->workload_complete_wq);
1095
1096         for_each_engine(engine, gvt->dev_priv, i) {
1097                 init_waitqueue_head(&scheduler->waitq[i]);
1098
1099                 param = kzalloc(sizeof(*param), GFP_KERNEL);
1100                 if (!param) {
1101                         ret = -ENOMEM;
1102                         goto err;
1103                 }
1104
1105                 param->gvt = gvt;
1106                 param->ring_id = i;
1107
1108                 scheduler->thread[i] = kthread_run(workload_thread, param,
1109                         "gvt workload %d", i);
1110                 if (IS_ERR(scheduler->thread[i])) {
1111                         gvt_err("fail to create workload thread\n");
1112                         ret = PTR_ERR(scheduler->thread[i]);
1113                         goto err;
1114                 }
1115
1116                 gvt->shadow_ctx_notifier_block[i].notifier_call =
1117                                         shadow_context_status_change;
1118                 atomic_notifier_chain_register(&engine->context_status_notifier,
1119                                         &gvt->shadow_ctx_notifier_block[i]);
1120         }
1121         return 0;
1122 err:
1123         intel_gvt_clean_workload_scheduler(gvt);
1124         kfree(param);
1125         param = NULL;
1126         return ret;
1127 }
1128
1129 static void
1130 i915_context_ppgtt_root_restore(struct intel_vgpu_submission *s,
1131                                 struct i915_ppgtt *ppgtt)
1132 {
1133         int i;
1134
1135         if (i915_vm_is_4lvl(&ppgtt->vm)) {
1136                 px_dma(ppgtt->pd) = s->i915_context_pml4;
1137         } else {
1138                 for (i = 0; i < GEN8_3LVL_PDPES; i++) {
1139                         struct i915_page_directory * const pd =
1140                                 i915_pd_entry(ppgtt->pd, i);
1141
1142                         px_dma(pd) = s->i915_context_pdps[i];
1143                 }
1144         }
1145 }
1146
1147 /**
1148  * intel_vgpu_clean_submission - free submission-related resource for vGPU
1149  * @vgpu: a vGPU
1150  *
1151  * This function is called when a vGPU is being destroyed.
1152  *
1153  */
1154 void intel_vgpu_clean_submission(struct intel_vgpu *vgpu)
1155 {
1156         struct intel_vgpu_submission *s = &vgpu->submission;
1157         struct intel_engine_cs *engine;
1158         enum intel_engine_id id;
1159
1160         intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0);
1161
1162         i915_context_ppgtt_root_restore(s, i915_vm_to_ppgtt(s->shadow[0]->vm));
1163         for_each_engine(engine, vgpu->gvt->dev_priv, id)
1164                 intel_context_unpin(s->shadow[id]);
1165
1166         kmem_cache_destroy(s->workloads);
1167 }
1168
1169
1170 /**
1171  * intel_vgpu_reset_submission - reset submission-related resource for vGPU
1172  * @vgpu: a vGPU
1173  * @engine_mask: engines expected to be reset
1174  *
1175  * This function is called when a vGPU is being destroyed.
1176  *
1177  */
1178 void intel_vgpu_reset_submission(struct intel_vgpu *vgpu,
1179                                  intel_engine_mask_t engine_mask)
1180 {
1181         struct intel_vgpu_submission *s = &vgpu->submission;
1182
1183         if (!s->active)
1184                 return;
1185
1186         intel_vgpu_clean_workloads(vgpu, engine_mask);
1187         s->ops->reset(vgpu, engine_mask);
1188 }
1189
1190 static void
1191 i915_context_ppgtt_root_save(struct intel_vgpu_submission *s,
1192                              struct i915_ppgtt *ppgtt)
1193 {
1194         int i;
1195
1196         if (i915_vm_is_4lvl(&ppgtt->vm)) {
1197                 s->i915_context_pml4 = px_dma(ppgtt->pd);
1198         } else {
1199                 for (i = 0; i < GEN8_3LVL_PDPES; i++) {
1200                         struct i915_page_directory * const pd =
1201                                 i915_pd_entry(ppgtt->pd, i);
1202
1203                         s->i915_context_pdps[i] = px_dma(pd);
1204                 }
1205         }
1206 }
1207
1208 /**
1209  * intel_vgpu_setup_submission - setup submission-related resource for vGPU
1210  * @vgpu: a vGPU
1211  *
1212  * This function is called when a vGPU is being created.
1213  *
1214  * Returns:
1215  * Zero on success, negative error code if failed.
1216  *
1217  */
1218 int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
1219 {
1220         struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
1221         struct intel_vgpu_submission *s = &vgpu->submission;
1222         struct intel_engine_cs *engine;
1223         struct i915_ppgtt *ppgtt;
1224         enum intel_engine_id i;
1225         int ret;
1226
1227         ppgtt = i915_ppgtt_create(&i915->gt);
1228         if (IS_ERR(ppgtt))
1229                 return PTR_ERR(ppgtt);
1230
1231         i915_context_ppgtt_root_save(s, ppgtt);
1232
1233         for_each_engine(engine, i915, i) {
1234                 struct intel_context *ce;
1235
1236                 INIT_LIST_HEAD(&s->workload_q_head[i]);
1237                 s->shadow[i] = ERR_PTR(-EINVAL);
1238
1239                 ce = intel_context_create(engine);
1240                 if (IS_ERR(ce)) {
1241                         ret = PTR_ERR(ce);
1242                         goto out_shadow_ctx;
1243                 }
1244
1245                 i915_vm_put(ce->vm);
1246                 ce->vm = i915_vm_get(&ppgtt->vm);
1247                 intel_context_set_single_submission(ce);
1248
1249                 if (!USES_GUC_SUBMISSION(i915)) { /* Max ring buffer size */
1250                         const unsigned int ring_size = 512 * SZ_4K;
1251
1252                         ce->ring = __intel_context_ring_size(ring_size);
1253                 }
1254
1255                 ret = intel_context_pin(ce);
1256                 intel_context_put(ce);
1257                 if (ret)
1258                         goto out_shadow_ctx;
1259
1260                 s->shadow[i] = ce;
1261         }
1262
1263         bitmap_zero(s->shadow_ctx_desc_updated, I915_NUM_ENGINES);
1264
1265         s->workloads = kmem_cache_create_usercopy("gvt-g_vgpu_workload",
1266                                                   sizeof(struct intel_vgpu_workload), 0,
1267                                                   SLAB_HWCACHE_ALIGN,
1268                                                   offsetof(struct intel_vgpu_workload, rb_tail),
1269                                                   sizeof_field(struct intel_vgpu_workload, rb_tail),
1270                                                   NULL);
1271
1272         if (!s->workloads) {
1273                 ret = -ENOMEM;
1274                 goto out_shadow_ctx;
1275         }
1276
1277         atomic_set(&s->running_workload_num, 0);
1278         bitmap_zero(s->tlb_handle_pending, I915_NUM_ENGINES);
1279
1280         i915_vm_put(&ppgtt->vm);
1281         return 0;
1282
1283 out_shadow_ctx:
1284         i915_context_ppgtt_root_restore(s, ppgtt);
1285         for_each_engine(engine, i915, i) {
1286                 if (IS_ERR(s->shadow[i]))
1287                         break;
1288
1289                 intel_context_unpin(s->shadow[i]);
1290                 intel_context_put(s->shadow[i]);
1291         }
1292         i915_vm_put(&ppgtt->vm);
1293         return ret;
1294 }
1295
1296 /**
1297  * intel_vgpu_select_submission_ops - select virtual submission interface
1298  * @vgpu: a vGPU
1299  * @engine_mask: either ALL_ENGINES or target engine mask
1300  * @interface: expected vGPU virtual submission interface
1301  *
1302  * This function is called when guest configures submission interface.
1303  *
1304  * Returns:
1305  * Zero on success, negative error code if failed.
1306  *
1307  */
1308 int intel_vgpu_select_submission_ops(struct intel_vgpu *vgpu,
1309                                      intel_engine_mask_t engine_mask,
1310                                      unsigned int interface)
1311 {
1312         struct intel_vgpu_submission *s = &vgpu->submission;
1313         const struct intel_vgpu_submission_ops *ops[] = {
1314                 [INTEL_VGPU_EXECLIST_SUBMISSION] =
1315                         &intel_vgpu_execlist_submission_ops,
1316         };
1317         int ret;
1318
1319         if (WARN_ON(interface >= ARRAY_SIZE(ops)))
1320                 return -EINVAL;
1321
1322         if (WARN_ON(interface == 0 && engine_mask != ALL_ENGINES))
1323                 return -EINVAL;
1324
1325         if (s->active)
1326                 s->ops->clean(vgpu, engine_mask);
1327
1328         if (interface == 0) {
1329                 s->ops = NULL;
1330                 s->virtual_submission_interface = 0;
1331                 s->active = false;
1332                 gvt_dbg_core("vgpu%d: remove submission ops\n", vgpu->id);
1333                 return 0;
1334         }
1335
1336         ret = ops[interface]->init(vgpu, engine_mask);
1337         if (ret)
1338                 return ret;
1339
1340         s->ops = ops[interface];
1341         s->virtual_submission_interface = interface;
1342         s->active = true;
1343
1344         gvt_dbg_core("vgpu%d: activate ops [ %s ]\n",
1345                         vgpu->id, s->ops->name);
1346
1347         return 0;
1348 }
1349
1350 /**
1351  * intel_vgpu_destroy_workload - destroy a vGPU workload
1352  * @workload: workload to destroy
1353  *
1354  * This function is called when destroy a vGPU workload.
1355  *
1356  */
1357 void intel_vgpu_destroy_workload(struct intel_vgpu_workload *workload)
1358 {
1359         struct intel_vgpu_submission *s = &workload->vgpu->submission;
1360
1361         release_shadow_batch_buffer(workload);
1362         release_shadow_wa_ctx(&workload->wa_ctx);
1363
1364         if (workload->shadow_mm)
1365                 intel_vgpu_mm_put(workload->shadow_mm);
1366
1367         kmem_cache_free(s->workloads, workload);
1368 }
1369
1370 static struct intel_vgpu_workload *
1371 alloc_workload(struct intel_vgpu *vgpu)
1372 {
1373         struct intel_vgpu_submission *s = &vgpu->submission;
1374         struct intel_vgpu_workload *workload;
1375
1376         workload = kmem_cache_zalloc(s->workloads, GFP_KERNEL);
1377         if (!workload)
1378                 return ERR_PTR(-ENOMEM);
1379
1380         INIT_LIST_HEAD(&workload->list);
1381         INIT_LIST_HEAD(&workload->shadow_bb);
1382
1383         init_waitqueue_head(&workload->shadow_ctx_status_wq);
1384         atomic_set(&workload->shadow_ctx_active, 0);
1385
1386         workload->status = -EINPROGRESS;
1387         workload->vgpu = vgpu;
1388
1389         return workload;
1390 }
1391
1392 #define RING_CTX_OFF(x) \
1393         offsetof(struct execlist_ring_context, x)
1394
1395 static void read_guest_pdps(struct intel_vgpu *vgpu,
1396                 u64 ring_context_gpa, u32 pdp[8])
1397 {
1398         u64 gpa;
1399         int i;
1400
1401         gpa = ring_context_gpa + RING_CTX_OFF(pdps[0].val);
1402
1403         for (i = 0; i < 8; i++)
1404                 intel_gvt_hypervisor_read_gpa(vgpu,
1405                                 gpa + i * 8, &pdp[7 - i], 4);
1406 }
1407
1408 static int prepare_mm(struct intel_vgpu_workload *workload)
1409 {
1410         struct execlist_ctx_descriptor_format *desc = &workload->ctx_desc;
1411         struct intel_vgpu_mm *mm;
1412         struct intel_vgpu *vgpu = workload->vgpu;
1413         enum intel_gvt_gtt_type root_entry_type;
1414         u64 pdps[GVT_RING_CTX_NR_PDPS];
1415
1416         switch (desc->addressing_mode) {
1417         case 1: /* legacy 32-bit */
1418                 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY;
1419                 break;
1420         case 3: /* legacy 64-bit */
1421                 root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
1422                 break;
1423         default:
1424                 gvt_vgpu_err("Advanced Context mode(SVM) is not supported!\n");
1425                 return -EINVAL;
1426         }
1427
1428         read_guest_pdps(workload->vgpu, workload->ring_context_gpa, (void *)pdps);
1429
1430         mm = intel_vgpu_get_ppgtt_mm(workload->vgpu, root_entry_type, pdps);
1431         if (IS_ERR(mm))
1432                 return PTR_ERR(mm);
1433
1434         workload->shadow_mm = mm;
1435         return 0;
1436 }
1437
1438 #define same_context(a, b) (((a)->context_id == (b)->context_id) && \
1439                 ((a)->lrca == (b)->lrca))
1440
1441 /**
1442  * intel_vgpu_create_workload - create a vGPU workload
1443  * @vgpu: a vGPU
1444  * @ring_id: ring index
1445  * @desc: a guest context descriptor
1446  *
1447  * This function is called when creating a vGPU workload.
1448  *
1449  * Returns:
1450  * struct intel_vgpu_workload * on success, negative error code in
1451  * pointer if failed.
1452  *
1453  */
1454 struct intel_vgpu_workload *
1455 intel_vgpu_create_workload(struct intel_vgpu *vgpu, int ring_id,
1456                            struct execlist_ctx_descriptor_format *desc)
1457 {
1458         struct intel_vgpu_submission *s = &vgpu->submission;
1459         struct list_head *q = workload_q_head(vgpu, ring_id);
1460         struct intel_vgpu_workload *last_workload = NULL;
1461         struct intel_vgpu_workload *workload = NULL;
1462         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1463         u64 ring_context_gpa;
1464         u32 head, tail, start, ctl, ctx_ctl, per_ctx, indirect_ctx;
1465         u32 guest_head;
1466         int ret;
1467
1468         ring_context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
1469                         (u32)((desc->lrca + 1) << I915_GTT_PAGE_SHIFT));
1470         if (ring_context_gpa == INTEL_GVT_INVALID_ADDR) {
1471                 gvt_vgpu_err("invalid guest context LRCA: %x\n", desc->lrca);
1472                 return ERR_PTR(-EINVAL);
1473         }
1474
1475         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1476                         RING_CTX_OFF(ring_header.val), &head, 4);
1477
1478         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1479                         RING_CTX_OFF(ring_tail.val), &tail, 4);
1480
1481         guest_head = head;
1482
1483         head &= RB_HEAD_OFF_MASK;
1484         tail &= RB_TAIL_OFF_MASK;
1485
1486         list_for_each_entry_reverse(last_workload, q, list) {
1487
1488                 if (same_context(&last_workload->ctx_desc, desc)) {
1489                         gvt_dbg_el("ring id %d cur workload == last\n",
1490                                         ring_id);
1491                         gvt_dbg_el("ctx head %x real head %lx\n", head,
1492                                         last_workload->rb_tail);
1493                         /*
1494                          * cannot use guest context head pointer here,
1495                          * as it might not be updated at this time
1496                          */
1497                         head = last_workload->rb_tail;
1498                         break;
1499                 }
1500         }
1501
1502         gvt_dbg_el("ring id %d begin a new workload\n", ring_id);
1503
1504         /* record some ring buffer register values for scan and shadow */
1505         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1506                         RING_CTX_OFF(rb_start.val), &start, 4);
1507         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1508                         RING_CTX_OFF(rb_ctrl.val), &ctl, 4);
1509         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1510                         RING_CTX_OFF(ctx_ctrl.val), &ctx_ctl, 4);
1511
1512         if (!intel_gvt_ggtt_validate_range(vgpu, start,
1513                                 _RING_CTL_BUF_SIZE(ctl))) {
1514                 gvt_vgpu_err("context contain invalid rb at: 0x%x\n", start);
1515                 return ERR_PTR(-EINVAL);
1516         }
1517
1518         workload = alloc_workload(vgpu);
1519         if (IS_ERR(workload))
1520                 return workload;
1521
1522         workload->ring_id = ring_id;
1523         workload->ctx_desc = *desc;
1524         workload->ring_context_gpa = ring_context_gpa;
1525         workload->rb_head = head;
1526         workload->guest_rb_head = guest_head;
1527         workload->rb_tail = tail;
1528         workload->rb_start = start;
1529         workload->rb_ctl = ctl;
1530
1531         if (ring_id == RCS0) {
1532                 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1533                         RING_CTX_OFF(bb_per_ctx_ptr.val), &per_ctx, 4);
1534                 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1535                         RING_CTX_OFF(rcs_indirect_ctx.val), &indirect_ctx, 4);
1536
1537                 workload->wa_ctx.indirect_ctx.guest_gma =
1538                         indirect_ctx & INDIRECT_CTX_ADDR_MASK;
1539                 workload->wa_ctx.indirect_ctx.size =
1540                         (indirect_ctx & INDIRECT_CTX_SIZE_MASK) *
1541                         CACHELINE_BYTES;
1542
1543                 if (workload->wa_ctx.indirect_ctx.size != 0) {
1544                         if (!intel_gvt_ggtt_validate_range(vgpu,
1545                                 workload->wa_ctx.indirect_ctx.guest_gma,
1546                                 workload->wa_ctx.indirect_ctx.size)) {
1547                                 gvt_vgpu_err("invalid wa_ctx at: 0x%lx\n",
1548                                     workload->wa_ctx.indirect_ctx.guest_gma);
1549                                 kmem_cache_free(s->workloads, workload);
1550                                 return ERR_PTR(-EINVAL);
1551                         }
1552                 }
1553
1554                 workload->wa_ctx.per_ctx.guest_gma =
1555                         per_ctx & PER_CTX_ADDR_MASK;
1556                 workload->wa_ctx.per_ctx.valid = per_ctx & 1;
1557                 if (workload->wa_ctx.per_ctx.valid) {
1558                         if (!intel_gvt_ggtt_validate_range(vgpu,
1559                                 workload->wa_ctx.per_ctx.guest_gma,
1560                                 CACHELINE_BYTES)) {
1561                                 gvt_vgpu_err("invalid per_ctx at: 0x%lx\n",
1562                                         workload->wa_ctx.per_ctx.guest_gma);
1563                                 kmem_cache_free(s->workloads, workload);
1564                                 return ERR_PTR(-EINVAL);
1565                         }
1566                 }
1567         }
1568
1569         gvt_dbg_el("workload %p ring id %d head %x tail %x start %x ctl %x\n",
1570                         workload, ring_id, head, tail, start, ctl);
1571
1572         ret = prepare_mm(workload);
1573         if (ret) {
1574                 kmem_cache_free(s->workloads, workload);
1575                 return ERR_PTR(ret);
1576         }
1577
1578         /* Only scan and shadow the first workload in the queue
1579          * as there is only one pre-allocated buf-obj for shadow.
1580          */
1581         if (list_empty(workload_q_head(vgpu, ring_id))) {
1582                 intel_runtime_pm_get(&dev_priv->runtime_pm);
1583                 ret = intel_gvt_scan_and_shadow_workload(workload);
1584                 intel_runtime_pm_put_unchecked(&dev_priv->runtime_pm);
1585         }
1586
1587         if (ret) {
1588                 if (vgpu_is_vm_unhealthy(ret))
1589                         enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR);
1590                 intel_vgpu_destroy_workload(workload);
1591                 return ERR_PTR(ret);
1592         }
1593
1594         return workload;
1595 }
1596
1597 /**
1598  * intel_vgpu_queue_workload - Qeue a vGPU workload
1599  * @workload: the workload to queue in
1600  */
1601 void intel_vgpu_queue_workload(struct intel_vgpu_workload *workload)
1602 {
1603         list_add_tail(&workload->list,
1604                 workload_q_head(workload->vgpu, workload->ring_id));
1605         intel_gvt_kick_schedule(workload->vgpu->gvt);
1606         wake_up(&workload->vgpu->gvt->scheduler.waitq[workload->ring_id]);
1607 }