drivers/gpu/drm/i915/gt/intel_engine.h

   1 /* SPDX-License-Identifier: MIT */
   2 #ifndef _INTEL_RINGBUFFER_H_
   3 #define _INTEL_RINGBUFFER_H_
   4
   5 #include <drm/drm_util.h>
   6
   7 #include <linux/hashtable.h>
   8 #include <linux/irq_work.h>
   9 #include <linux/random.h>
  10 #include <linux/seqlock.h>
  11
  12 #include "i915_pmu.h"
  13 #include "i915_reg.h"
  14 #include "i915_request.h"
  15 #include "i915_selftest.h"
  16 #include "intel_engine_types.h"
  17 #include "intel_gt_types.h"
  18 #include "intel_timeline.h"
  19 #include "intel_workarounds.h"
  20
  21 struct drm_printer;
  22 struct intel_context;
  23 struct intel_gt;
  24 struct lock_class_key;
  25
  26 /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
  27  * but keeps the logic simple. Indeed, the whole purpose of this macro is just
  28  * to give some inclination as to some of the magic values used in the various
  29  * workarounds!
  30  */
  31 #define CACHELINE_BYTES 64
  32 #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(u32))
  33
  34 #define ENGINE_TRACE(e, fmt, ...) do {                                  \
  35         const struct intel_engine_cs *e__ __maybe_unused = (e);         \
  36         GEM_TRACE("%s %s: " fmt,                                        \
  37                   dev_name(e__->i915->drm.dev), e__->name,              \
  38                   ##__VA_ARGS__);                                       \
  39 } while (0)
  40
  41 /*
  42  * The register defines to be used with the following macros need to accept a
  43  * base param, e.g:
  44  *
  45  * REG_FOO(base) _MMIO((base) + <relative offset>)
  46  * ENGINE_READ(engine, REG_FOO);
  47  *
  48  * register arrays are to be defined and accessed as follows:
  49  *
  50  * REG_BAR(base, i) _MMIO((base) + <relative offset> + (i) * <shift>)
  51  * ENGINE_READ_IDX(engine, REG_BAR, i)
  52  */
  53
  54 #define __ENGINE_REG_OP(op__, engine__, ...) \
  55         intel_uncore_##op__((engine__)->uncore, __VA_ARGS__)
  56
  57 #define __ENGINE_READ_OP(op__, engine__, reg__) \
  58         __ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base))
  59
  60 #define ENGINE_READ16(...)      __ENGINE_READ_OP(read16, __VA_ARGS__)
  61 #define ENGINE_READ(...)        __ENGINE_READ_OP(read, __VA_ARGS__)
  62 #define ENGINE_READ_FW(...)     __ENGINE_READ_OP(read_fw, __VA_ARGS__)
  63 #define ENGINE_POSTING_READ(...) __ENGINE_READ_OP(posting_read_fw, __VA_ARGS__)
  64 #define ENGINE_POSTING_READ16(...) __ENGINE_READ_OP(posting_read16, __VA_ARGS__)
  65
  66 #define ENGINE_READ64(engine__, lower_reg__, upper_reg__) \
  67         __ENGINE_REG_OP(read64_2x32, (engine__), \
  68                         lower_reg__((engine__)->mmio_base), \
  69                         upper_reg__((engine__)->mmio_base))
  70
  71 #define ENGINE_READ_IDX(engine__, reg__, idx__) \
  72         __ENGINE_REG_OP(read, (engine__), reg__((engine__)->mmio_base, (idx__)))
  73
  74 #define __ENGINE_WRITE_OP(op__, engine__, reg__, val__) \
  75         __ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base), (val__))
  76
  77 #define ENGINE_WRITE16(...)     __ENGINE_WRITE_OP(write16, __VA_ARGS__)
  78 #define ENGINE_WRITE(...)       __ENGINE_WRITE_OP(write, __VA_ARGS__)
  79 #define ENGINE_WRITE_FW(...)    __ENGINE_WRITE_OP(write_fw, __VA_ARGS__)
  80
  81 #define GEN6_RING_FAULT_REG_READ(engine__) \
  82         intel_uncore_read((engine__)->uncore, RING_FAULT_REG(engine__))
  83
  84 #define GEN6_RING_FAULT_REG_POSTING_READ(engine__) \
  85         intel_uncore_posting_read((engine__)->uncore, RING_FAULT_REG(engine__))
  86
  87 #define GEN6_RING_FAULT_REG_RMW(engine__, clear__, set__) \
  88 ({ \
  89         u32 __val; \
  90 \
  91         __val = intel_uncore_read((engine__)->uncore, \
  92                                   RING_FAULT_REG(engine__)); \
  93         __val &= ~(clear__); \
  94         __val |= (set__); \
  95         intel_uncore_write((engine__)->uncore, RING_FAULT_REG(engine__), \
  96                            __val); \
  97 })
  98
  99 /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
 100  * do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
 101  */
 102
 103 static inline unsigned int
 104 execlists_num_ports(const struct intel_engine_execlists * const execlists)
 105 {
 106         return execlists->port_mask + 1;
 107 }
 108
 109 static inline struct i915_request *
 110 execlists_active(const struct intel_engine_execlists *execlists)
 111 {
 112         struct i915_request * const *cur, * const *old, *active;
 113
 114         cur = READ_ONCE(execlists->active);
 115         smp_rmb(); /* pairs with overwrite protection in process_csb() */
 116         do {
 117                 old = cur;
 118
 119                 active = READ_ONCE(*cur);
 120                 cur = READ_ONCE(execlists->active);
 121
 122                 smp_rmb(); /* and complete the seqlock retry */
 123         } while (unlikely(cur != old));
 124
 125         return active;
 126 }
 127
 128 static inline void
 129 execlists_active_lock_bh(struct intel_engine_execlists *execlists)
 130 {
 131         local_bh_disable(); /* prevent local softirq and lock recursion */
 132         tasklet_lock(&execlists->tasklet);
 133 }
 134
 135 static inline void
 136 execlists_active_unlock_bh(struct intel_engine_execlists *execlists)
 137 {
 138         tasklet_unlock(&execlists->tasklet);
 139         local_bh_enable(); /* restore softirq, and kick ksoftirqd! */
 140 }
 141
 142 struct i915_request *
 143 execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists);
 144
 145 static inline u32
 146 intel_read_status_page(const struct intel_engine_cs *engine, int reg)
 147 {
 148         /* Ensure that the compiler doesn't optimize away the load. */
 149         return READ_ONCE(engine->status_page.addr[reg]);
 150 }
 151
 152 static inline void
 153 intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
 154 {
 155         /* Writing into the status page should be done sparingly. Since
 156          * we do when we are uncertain of the device state, we take a bit
 157          * of extra paranoia to try and ensure that the HWS takes the value
 158          * we give and that it doesn't end up trapped inside the CPU!
 159          */
 160         if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
 161                 mb();
 162                 clflush(&engine->status_page.addr[reg]);
 163                 engine->status_page.addr[reg] = value;
 164                 clflush(&engine->status_page.addr[reg]);
 165                 mb();
 166         } else {
 167                 WRITE_ONCE(engine->status_page.addr[reg], value);
 168         }
 169 }
 170
 171 /*
 172  * Reads a dword out of the status page, which is written to from the command
 173  * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
 174  * MI_STORE_DATA_IMM.
 175  *
 176  * The following dwords have a reserved meaning:
 177  * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
 178  * 0x04: ring 0 head pointer
 179  * 0x05: ring 1 head pointer (915-class)
 180  * 0x06: ring 2 head pointer (915-class)
 181  * 0x10-0x1b: Context status DWords (GM45)
 182  * 0x1f: Last written status offset. (GM45)
 183  * 0x20-0x2f: Reserved (Gen6+)
 184  *
 185  * The area from dword 0x30 to 0x3ff is available for driver usage.
 186  */
 187 #define I915_GEM_HWS_PREEMPT            0x32
 188 #define I915_GEM_HWS_PREEMPT_ADDR       (I915_GEM_HWS_PREEMPT * sizeof(u32))
 189 #define I915_GEM_HWS_SEQNO              0x40
 190 #define I915_GEM_HWS_SEQNO_ADDR         (I915_GEM_HWS_SEQNO * sizeof(u32))
 191 #define I915_GEM_HWS_SCRATCH            0x80
 192
 193 #define I915_HWS_CSB_BUF0_INDEX         0x10
 194 #define I915_HWS_CSB_WRITE_INDEX        0x1f
 195 #define CNL_HWS_CSB_WRITE_INDEX         0x2f
 196
 197 void intel_engine_stop(struct intel_engine_cs *engine);
 198 void intel_engine_cleanup(struct intel_engine_cs *engine);
 199
 200 int intel_engines_init_mmio(struct intel_gt *gt);
 201 int intel_engines_init(struct intel_gt *gt);
 202
 203 void intel_engine_free_request_pool(struct intel_engine_cs *engine);
 204
 205 void intel_engines_release(struct intel_gt *gt);
 206 void intel_engines_free(struct intel_gt *gt);
 207
 208 int intel_engine_init_common(struct intel_engine_cs *engine);
 209 void intel_engine_cleanup_common(struct intel_engine_cs *engine);
 210
 211 int intel_engine_resume(struct intel_engine_cs *engine);
 212
 213 int intel_ring_submission_setup(struct intel_engine_cs *engine);
 214
 215 int intel_engine_stop_cs(struct intel_engine_cs *engine);
 216 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine);
 217
 218 void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask);
 219
 220 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine);
 221 u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine);
 222
 223 void intel_engine_get_instdone(const struct intel_engine_cs *engine,
 224                                struct intel_instdone *instdone);
 225
 226 void intel_engine_init_execlists(struct intel_engine_cs *engine);
 227
 228 static inline void __intel_engine_reset(struct intel_engine_cs *engine,
 229                                         bool stalled)
 230 {
 231         if (engine->reset.rewind)
 232                 engine->reset.rewind(engine, stalled);
 233         engine->serial++; /* contexts lost */
 234 }
 235
 236 bool intel_engines_are_idle(struct intel_gt *gt);
 237 bool intel_engine_is_idle(struct intel_engine_cs *engine);
 238
 239 void __intel_engine_flush_submission(struct intel_engine_cs *engine, bool sync);
 240 static inline void intel_engine_flush_submission(struct intel_engine_cs *engine)
 241 {
 242         __intel_engine_flush_submission(engine, true);
 243 }
 244
 245 void intel_engines_reset_default_submission(struct intel_gt *gt);
 246
 247 bool intel_engine_can_store_dword(struct intel_engine_cs *engine);
 248
 249 __printf(3, 4)
 250 void intel_engine_dump(struct intel_engine_cs *engine,
 251                        struct drm_printer *m,
 252                        const char *header, ...);
 253
 254 ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine,
 255                                    ktime_t *now);
 256
 257 struct i915_request *
 258 intel_engine_find_active_request(struct intel_engine_cs *engine);
 259
 260 u32 intel_engine_context_size(struct intel_gt *gt, u8 class);
 261 struct intel_context *
 262 intel_engine_create_pinned_context(struct intel_engine_cs *engine,
 263                                    struct i915_address_space *vm,
 264                                    unsigned int ring_size,
 265                                    unsigned int hwsp,
 266                                    struct lock_class_key *key,
 267                                    const char *name);
 268
 269 void intel_engine_destroy_pinned_context(struct intel_context *ce);
 270
 271 void intel_engine_init_active(struct intel_engine_cs *engine,
 272                               unsigned int subclass);
 273 #define ENGINE_PHYSICAL 0
 274 #define ENGINE_MOCK     1
 275 #define ENGINE_VIRTUAL  2
 276
 277 static inline bool intel_engine_uses_guc(const struct intel_engine_cs *engine)
 278 {
 279         return engine->gt->submission_method >= INTEL_SUBMISSION_GUC;
 280 }
 281
 282 static inline bool
 283 intel_engine_has_preempt_reset(const struct intel_engine_cs *engine)
 284 {
 285         if (!IS_ACTIVE(CONFIG_DRM_I915_PREEMPT_TIMEOUT))
 286                 return false;
 287
 288         return intel_engine_has_preemption(engine);
 289 }
 290
 291 static inline bool
 292 intel_engine_has_heartbeat(const struct intel_engine_cs *engine)
 293 {
 294         if (!IS_ACTIVE(CONFIG_DRM_I915_HEARTBEAT_INTERVAL))
 295                 return false;
 296
 297         return READ_ONCE(engine->props.heartbeat_interval_ms);
 298 }
 299
 300 #endif /* _INTEL_RINGBUFFER_H_ */