drivers/gpu/drm/i915/display/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/delay.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/i2c.h>
  32 #include <linux/slab.h>
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_edid.h>
  37 #include <drm/drm_hdcp.h>
  38 #include <drm/drm_scdc_helper.h>
  39 #include <drm/intel_lpe_audio.h>
  40
  41 #include "i915_debugfs.h"
  42 #include "i915_drv.h"
  43 #include "intel_atomic.h"
  44 #include "intel_connector.h"
  45 #include "intel_ddi.h"
  46 #include "intel_display_types.h"
  47 #include "intel_dp.h"
  48 #include "intel_gmbus.h"
  49 #include "intel_hdcp.h"
  50 #include "intel_hdmi.h"
  51 #include "intel_lspcon.h"
  52 #include "intel_panel.h"
  53
  54 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  55 {
  56         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  57 }
  58
  59 static void
  60 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  61 {
  62         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  63         struct drm_i915_private *dev_priv = to_i915(dev);
  64         u32 enabled_bits;
  65
  66         enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  67
  68         drm_WARN(dev,
  69                  intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits,
  70                  "HDMI port enabled, expecting disabled\n");
  71 }
  72
  73 static void
  74 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
  75                                      enum transcoder cpu_transcoder)
  76 {
  77         drm_WARN(&dev_priv->drm,
  78                  intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
  79                  TRANS_DDI_FUNC_ENABLE,
  80                  "HDMI transcoder function enabled, expecting disabled\n");
  81 }
  82
  83 static u32 g4x_infoframe_index(unsigned int type)
  84 {
  85         switch (type) {
  86         case HDMI_PACKET_TYPE_GAMUT_METADATA:
  87                 return VIDEO_DIP_SELECT_GAMUT;
  88         case HDMI_INFOFRAME_TYPE_AVI:
  89                 return VIDEO_DIP_SELECT_AVI;
  90         case HDMI_INFOFRAME_TYPE_SPD:
  91                 return VIDEO_DIP_SELECT_SPD;
  92         case HDMI_INFOFRAME_TYPE_VENDOR:
  93                 return VIDEO_DIP_SELECT_VENDOR;
  94         default:
  95                 MISSING_CASE(type);
  96                 return 0;
  97         }
  98 }
  99
 100 static u32 g4x_infoframe_enable(unsigned int type)
 101 {
 102         switch (type) {
 103         case HDMI_PACKET_TYPE_GENERAL_CONTROL:
 104                 return VIDEO_DIP_ENABLE_GCP;
 105         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 106                 return VIDEO_DIP_ENABLE_GAMUT;
 107         case DP_SDP_VSC:
 108                 return 0;
 109         case HDMI_INFOFRAME_TYPE_AVI:
 110                 return VIDEO_DIP_ENABLE_AVI;
 111         case HDMI_INFOFRAME_TYPE_SPD:
 112                 return VIDEO_DIP_ENABLE_SPD;
 113         case HDMI_INFOFRAME_TYPE_VENDOR:
 114                 return VIDEO_DIP_ENABLE_VENDOR;
 115         case HDMI_INFOFRAME_TYPE_DRM:
 116                 return 0;
 117         default:
 118                 MISSING_CASE(type);
 119                 return 0;
 120         }
 121 }
 122
 123 static u32 hsw_infoframe_enable(unsigned int type)
 124 {
 125         switch (type) {
 126         case HDMI_PACKET_TYPE_GENERAL_CONTROL:
 127                 return VIDEO_DIP_ENABLE_GCP_HSW;
 128         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 129                 return VIDEO_DIP_ENABLE_GMP_HSW;
 130         case DP_SDP_VSC:
 131                 return VIDEO_DIP_ENABLE_VSC_HSW;
 132         case DP_SDP_PPS:
 133                 return VDIP_ENABLE_PPS;
 134         case HDMI_INFOFRAME_TYPE_AVI:
 135                 return VIDEO_DIP_ENABLE_AVI_HSW;
 136         case HDMI_INFOFRAME_TYPE_SPD:
 137                 return VIDEO_DIP_ENABLE_SPD_HSW;
 138         case HDMI_INFOFRAME_TYPE_VENDOR:
 139                 return VIDEO_DIP_ENABLE_VS_HSW;
 140         case HDMI_INFOFRAME_TYPE_DRM:
 141                 return VIDEO_DIP_ENABLE_DRM_GLK;
 142         default:
 143                 MISSING_CASE(type);
 144                 return 0;
 145         }
 146 }
 147
 148 static i915_reg_t
 149 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 150                  enum transcoder cpu_transcoder,
 151                  unsigned int type,
 152                  int i)
 153 {
 154         switch (type) {
 155         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 156                 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
 157         case DP_SDP_VSC:
 158                 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
 159         case DP_SDP_PPS:
 160                 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
 161         case HDMI_INFOFRAME_TYPE_AVI:
 162                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
 163         case HDMI_INFOFRAME_TYPE_SPD:
 164                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
 165         case HDMI_INFOFRAME_TYPE_VENDOR:
 166                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
 167         case HDMI_INFOFRAME_TYPE_DRM:
 168                 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
 169         default:
 170                 MISSING_CASE(type);
 171                 return INVALID_MMIO_REG;
 172         }
 173 }
 174
 175 static int hsw_dip_data_size(struct drm_i915_private *dev_priv,
 176                              unsigned int type)
 177 {
 178         switch (type) {
 179         case DP_SDP_VSC:
 180                 return VIDEO_DIP_VSC_DATA_SIZE;
 181         case DP_SDP_PPS:
 182                 return VIDEO_DIP_PPS_DATA_SIZE;
 183         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 184                 if (DISPLAY_VER(dev_priv) >= 11)
 185                         return VIDEO_DIP_GMP_DATA_SIZE;
 186                 else
 187                         return VIDEO_DIP_DATA_SIZE;
 188         default:
 189                 return VIDEO_DIP_DATA_SIZE;
 190         }
 191 }
 192
 193 static void g4x_write_infoframe(struct intel_encoder *encoder,
 194                                 const struct intel_crtc_state *crtc_state,
 195                                 unsigned int type,
 196                                 const void *frame, ssize_t len)
 197 {
 198         const u32 *data = frame;
 199         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 200         u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
 201         int i;
 202
 203         drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
 204                  "Writing DIP with CTL reg disabled\n");
 205
 206         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 207         val |= g4x_infoframe_index(type);
 208
 209         val &= ~g4x_infoframe_enable(type);
 210
 211         intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
 212
 213         for (i = 0; i < len; i += 4) {
 214                 intel_de_write(dev_priv, VIDEO_DIP_DATA, *data);
 215                 data++;
 216         }
 217         /* Write every possible data byte to force correct ECC calculation. */
 218         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 219                 intel_de_write(dev_priv, VIDEO_DIP_DATA, 0);
 220
 221         val |= g4x_infoframe_enable(type);
 222         val &= ~VIDEO_DIP_FREQ_MASK;
 223         val |= VIDEO_DIP_FREQ_VSYNC;
 224
 225         intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
 226         intel_de_posting_read(dev_priv, VIDEO_DIP_CTL);
 227 }
 228
 229 static void g4x_read_infoframe(struct intel_encoder *encoder,
 230                                const struct intel_crtc_state *crtc_state,
 231                                unsigned int type,
 232                                void *frame, ssize_t len)
 233 {
 234         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 235         u32 val, *data = frame;
 236         int i;
 237
 238         val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
 239
 240         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 241         val |= g4x_infoframe_index(type);
 242
 243         intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
 244
 245         for (i = 0; i < len; i += 4)
 246                 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA);
 247 }
 248
 249 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
 250                                   const struct intel_crtc_state *pipe_config)
 251 {
 252         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 253         u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
 254
 255         if ((val & VIDEO_DIP_ENABLE) == 0)
 256                 return 0;
 257
 258         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 259                 return 0;
 260
 261         return val & (VIDEO_DIP_ENABLE_AVI |
 262                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 263 }
 264
 265 static void ibx_write_infoframe(struct intel_encoder *encoder,
 266                                 const struct intel_crtc_state *crtc_state,
 267                                 unsigned int type,
 268                                 const void *frame, ssize_t len)
 269 {
 270         const u32 *data = frame;
 271         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 272         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
 273         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 274         u32 val = intel_de_read(dev_priv, reg);
 275         int i;
 276
 277         drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
 278                  "Writing DIP with CTL reg disabled\n");
 279
 280         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 281         val |= g4x_infoframe_index(type);
 282
 283         val &= ~g4x_infoframe_enable(type);
 284
 285         intel_de_write(dev_priv, reg, val);
 286
 287         for (i = 0; i < len; i += 4) {
 288                 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe),
 289                                *data);
 290                 data++;
 291         }
 292         /* Write every possible data byte to force correct ECC calculation. */
 293         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 294                 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 295
 296         val |= g4x_infoframe_enable(type);
 297         val &= ~VIDEO_DIP_FREQ_MASK;
 298         val |= VIDEO_DIP_FREQ_VSYNC;
 299
 300         intel_de_write(dev_priv, reg, val);
 301         intel_de_posting_read(dev_priv, reg);
 302 }
 303
 304 static void ibx_read_infoframe(struct intel_encoder *encoder,
 305                                const struct intel_crtc_state *crtc_state,
 306                                unsigned int type,
 307                                void *frame, ssize_t len)
 308 {
 309         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 310         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 311         u32 val, *data = frame;
 312         int i;
 313
 314         val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));
 315
 316         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 317         val |= g4x_infoframe_index(type);
 318
 319         intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);
 320
 321         for (i = 0; i < len; i += 4)
 322                 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
 323 }
 324
 325 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
 326                                   const struct intel_crtc_state *pipe_config)
 327 {
 328         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 329         enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
 330         i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
 331         u32 val = intel_de_read(dev_priv, reg);
 332
 333         if ((val & VIDEO_DIP_ENABLE) == 0)
 334                 return 0;
 335
 336         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 337                 return 0;
 338
 339         return val & (VIDEO_DIP_ENABLE_AVI |
 340                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 341                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 342 }
 343
 344 static void cpt_write_infoframe(struct intel_encoder *encoder,
 345                                 const struct intel_crtc_state *crtc_state,
 346                                 unsigned int type,
 347                                 const void *frame, ssize_t len)
 348 {
 349         const u32 *data = frame;
 350         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 351         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
 352         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 353         u32 val = intel_de_read(dev_priv, reg);
 354         int i;
 355
 356         drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
 357                  "Writing DIP with CTL reg disabled\n");
 358
 359         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 360         val |= g4x_infoframe_index(type);
 361
 362         /* The DIP control register spec says that we need to update the AVI
 363          * infoframe without clearing its enable bit */
 364         if (type != HDMI_INFOFRAME_TYPE_AVI)
 365                 val &= ~g4x_infoframe_enable(type);
 366
 367         intel_de_write(dev_priv, reg, val);
 368
 369         for (i = 0; i < len; i += 4) {
 370                 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe),
 371                                *data);
 372                 data++;
 373         }
 374         /* Write every possible data byte to force correct ECC calculation. */
 375         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 376                 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 377
 378         val |= g4x_infoframe_enable(type);
 379         val &= ~VIDEO_DIP_FREQ_MASK;
 380         val |= VIDEO_DIP_FREQ_VSYNC;
 381
 382         intel_de_write(dev_priv, reg, val);
 383         intel_de_posting_read(dev_priv, reg);
 384 }
 385
 386 static void cpt_read_infoframe(struct intel_encoder *encoder,
 387                                const struct intel_crtc_state *crtc_state,
 388                                unsigned int type,
 389                                void *frame, ssize_t len)
 390 {
 391         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 392         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 393         u32 val, *data = frame;
 394         int i;
 395
 396         val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));
 397
 398         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 399         val |= g4x_infoframe_index(type);
 400
 401         intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);
 402
 403         for (i = 0; i < len; i += 4)
 404                 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
 405 }
 406
 407 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
 408                                   const struct intel_crtc_state *pipe_config)
 409 {
 410         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 411         enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
 412         u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe));
 413
 414         if ((val & VIDEO_DIP_ENABLE) == 0)
 415                 return 0;
 416
 417         return val & (VIDEO_DIP_ENABLE_AVI |
 418                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 419                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 420 }
 421
 422 static void vlv_write_infoframe(struct intel_encoder *encoder,
 423                                 const struct intel_crtc_state *crtc_state,
 424                                 unsigned int type,
 425                                 const void *frame, ssize_t len)
 426 {
 427         const u32 *data = frame;
 428         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 429         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
 430         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 431         u32 val = intel_de_read(dev_priv, reg);
 432         int i;
 433
 434         drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
 435                  "Writing DIP with CTL reg disabled\n");
 436
 437         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 438         val |= g4x_infoframe_index(type);
 439
 440         val &= ~g4x_infoframe_enable(type);
 441
 442         intel_de_write(dev_priv, reg, val);
 443
 444         for (i = 0; i < len; i += 4) {
 445                 intel_de_write(dev_priv,
 446                                VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 447                 data++;
 448         }
 449         /* Write every possible data byte to force correct ECC calculation. */
 450         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 451                 intel_de_write(dev_priv,
 452                                VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 453
 454         val |= g4x_infoframe_enable(type);
 455         val &= ~VIDEO_DIP_FREQ_MASK;
 456         val |= VIDEO_DIP_FREQ_VSYNC;
 457
 458         intel_de_write(dev_priv, reg, val);
 459         intel_de_posting_read(dev_priv, reg);
 460 }
 461
 462 static void vlv_read_infoframe(struct intel_encoder *encoder,
 463                                const struct intel_crtc_state *crtc_state,
 464                                unsigned int type,
 465                                void *frame, ssize_t len)
 466 {
 467         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 468         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 469         u32 val, *data = frame;
 470         int i;
 471
 472         val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe));
 473
 474         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 475         val |= g4x_infoframe_index(type);
 476
 477         intel_de_write(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe), val);
 478
 479         for (i = 0; i < len; i += 4)
 480                 *data++ = intel_de_read(dev_priv,
 481                                         VLV_TVIDEO_DIP_DATA(crtc->pipe));
 482 }
 483
 484 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
 485                                   const struct intel_crtc_state *pipe_config)
 486 {
 487         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 488         enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
 489         u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe));
 490
 491         if ((val & VIDEO_DIP_ENABLE) == 0)
 492                 return 0;
 493
 494         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 495                 return 0;
 496
 497         return val & (VIDEO_DIP_ENABLE_AVI |
 498                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 499                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 500 }
 501
 502 void hsw_write_infoframe(struct intel_encoder *encoder,
 503                          const struct intel_crtc_state *crtc_state,
 504                          unsigned int type,
 505                          const void *frame, ssize_t len)
 506 {
 507         const u32 *data = frame;
 508         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 509         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 510         i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
 511         int data_size;
 512         int i;
 513         u32 val = intel_de_read(dev_priv, ctl_reg);
 514
 515         data_size = hsw_dip_data_size(dev_priv, type);
 516
 517         drm_WARN_ON(&dev_priv->drm, len > data_size);
 518
 519         val &= ~hsw_infoframe_enable(type);
 520         intel_de_write(dev_priv, ctl_reg, val);
 521
 522         for (i = 0; i < len; i += 4) {
 523                 intel_de_write(dev_priv,
 524                                hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
 525                                *data);
 526                 data++;
 527         }
 528         /* Write every possible data byte to force correct ECC calculation. */
 529         for (; i < data_size; i += 4)
 530                 intel_de_write(dev_priv,
 531                                hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
 532                                0);
 533
 534         val |= hsw_infoframe_enable(type);
 535         intel_de_write(dev_priv, ctl_reg, val);
 536         intel_de_posting_read(dev_priv, ctl_reg);
 537 }
 538
 539 void hsw_read_infoframe(struct intel_encoder *encoder,
 540                         const struct intel_crtc_state *crtc_state,
 541                         unsigned int type, void *frame, ssize_t len)
 542 {
 543         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 544         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 545         u32 val, *data = frame;
 546         int i;
 547
 548         val = intel_de_read(dev_priv, HSW_TVIDEO_DIP_CTL(cpu_transcoder));
 549
 550         for (i = 0; i < len; i += 4)
 551                 *data++ = intel_de_read(dev_priv,
 552                                         hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2));
 553 }
 554
 555 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
 556                                   const struct intel_crtc_state *pipe_config)
 557 {
 558         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 559         u32 val = intel_de_read(dev_priv,
 560                                 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
 561         u32 mask;
 562
 563         mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 564                 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 565                 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 566
 567         if (DISPLAY_VER(dev_priv) >= 10)
 568                 mask |= VIDEO_DIP_ENABLE_DRM_GLK;
 569
 570         return val & mask;
 571 }
 572
 573 static const u8 infoframe_type_to_idx[] = {
 574         HDMI_PACKET_TYPE_GENERAL_CONTROL,
 575         HDMI_PACKET_TYPE_GAMUT_METADATA,
 576         DP_SDP_VSC,
 577         HDMI_INFOFRAME_TYPE_AVI,
 578         HDMI_INFOFRAME_TYPE_SPD,
 579         HDMI_INFOFRAME_TYPE_VENDOR,
 580         HDMI_INFOFRAME_TYPE_DRM,
 581 };
 582
 583 u32 intel_hdmi_infoframe_enable(unsigned int type)
 584 {
 585         int i;
 586
 587         for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
 588                 if (infoframe_type_to_idx[i] == type)
 589                         return BIT(i);
 590         }
 591
 592         return 0;
 593 }
 594
 595 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
 596                                   const struct intel_crtc_state *crtc_state)
 597 {
 598         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 599         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 600         u32 val, ret = 0;
 601         int i;
 602
 603         val = dig_port->infoframes_enabled(encoder, crtc_state);
 604
 605         /* map from hardware bits to dip idx */
 606         for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
 607                 unsigned int type = infoframe_type_to_idx[i];
 608
 609                 if (HAS_DDI(dev_priv)) {
 610                         if (val & hsw_infoframe_enable(type))
 611                                 ret |= BIT(i);
 612                 } else {
 613                         if (val & g4x_infoframe_enable(type))
 614                                 ret |= BIT(i);
 615                 }
 616         }
 617
 618         return ret;
 619 }
 620
 621 /*
 622  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 623  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 624  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 625  * used for both technologies.
 626  *
 627  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 628  * DW1:       DB3       | DB2 | DB1 | DB0
 629  * DW2:       DB7       | DB6 | DB5 | DB4
 630  * DW3: ...
 631  *
 632  * (HB is Header Byte, DB is Data Byte)
 633  *
 634  * The hdmi pack() functions don't know about that hardware specific hole so we
 635  * trick them by giving an offset into the buffer and moving back the header
 636  * bytes by one.
 637  */
 638 static void intel_write_infoframe(struct intel_encoder *encoder,
 639                                   const struct intel_crtc_state *crtc_state,
 640                                   enum hdmi_infoframe_type type,
 641                                   const union hdmi_infoframe *frame)
 642 {
 643         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 644         u8 buffer[VIDEO_DIP_DATA_SIZE];
 645         ssize_t len;
 646
 647         if ((crtc_state->infoframes.enable &
 648              intel_hdmi_infoframe_enable(type)) == 0)
 649                 return;
 650
 651         if (drm_WARN_ON(encoder->base.dev, frame->any.type != type))
 652                 return;
 653
 654         /* see comment above for the reason for this offset */
 655         len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
 656         if (drm_WARN_ON(encoder->base.dev, len < 0))
 657                 return;
 658
 659         /* Insert the 'hole' (see big comment above) at position 3 */
 660         memmove(&buffer[0], &buffer[1], 3);
 661         buffer[3] = 0;
 662         len++;
 663
 664         dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
 665 }
 666
 667 void intel_read_infoframe(struct intel_encoder *encoder,
 668                           const struct intel_crtc_state *crtc_state,
 669                           enum hdmi_infoframe_type type,
 670                           union hdmi_infoframe *frame)
 671 {
 672         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 673         u8 buffer[VIDEO_DIP_DATA_SIZE];
 674         int ret;
 675
 676         if ((crtc_state->infoframes.enable &
 677              intel_hdmi_infoframe_enable(type)) == 0)
 678                 return;
 679
 680         dig_port->read_infoframe(encoder, crtc_state,
 681                                        type, buffer, sizeof(buffer));
 682
 683         /* Fill the 'hole' (see big comment above) at position 3 */
 684         memmove(&buffer[1], &buffer[0], 3);
 685
 686         /* see comment above for the reason for this offset */
 687         ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
 688         if (ret) {
 689                 drm_dbg_kms(encoder->base.dev,
 690                             "Failed to unpack infoframe type 0x%02x\n", type);
 691                 return;
 692         }
 693
 694         if (frame->any.type != type)
 695                 drm_dbg_kms(encoder->base.dev,
 696                             "Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
 697                             frame->any.type, type);
 698 }
 699
 700 static bool
 701 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
 702                                  struct intel_crtc_state *crtc_state,
 703                                  struct drm_connector_state *conn_state)
 704 {
 705         struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
 706         const struct drm_display_mode *adjusted_mode =
 707                 &crtc_state->hw.adjusted_mode;
 708         struct drm_connector *connector = conn_state->connector;
 709         int ret;
 710
 711         if (!crtc_state->has_infoframe)
 712                 return true;
 713
 714         crtc_state->infoframes.enable |=
 715                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
 716
 717         ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector,
 718                                                        adjusted_mode);
 719         if (ret)
 720                 return false;
 721
 722         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 723                 frame->colorspace = HDMI_COLORSPACE_YUV420;
 724         else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 725                 frame->colorspace = HDMI_COLORSPACE_YUV444;
 726         else
 727                 frame->colorspace = HDMI_COLORSPACE_RGB;
 728
 729         drm_hdmi_avi_infoframe_colorspace(frame, conn_state);
 730
 731         /* nonsense combination */
 732         drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range &&
 733                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
 734
 735         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
 736                 drm_hdmi_avi_infoframe_quant_range(frame, connector,
 737                                                    adjusted_mode,
 738                                                    crtc_state->limited_color_range ?
 739                                                    HDMI_QUANTIZATION_RANGE_LIMITED :
 740                                                    HDMI_QUANTIZATION_RANGE_FULL);
 741         } else {
 742                 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
 743                 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
 744         }
 745
 746         drm_hdmi_avi_infoframe_content_type(frame, conn_state);
 747
 748         /* TODO: handle pixel repetition for YCBCR420 outputs */
 749
 750         ret = hdmi_avi_infoframe_check(frame);
 751         if (drm_WARN_ON(encoder->base.dev, ret))
 752                 return false;
 753
 754         return true;
 755 }
 756
 757 static bool
 758 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
 759                                  struct intel_crtc_state *crtc_state,
 760                                  struct drm_connector_state *conn_state)
 761 {
 762         struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
 763         int ret;
 764
 765         if (!crtc_state->has_infoframe)
 766                 return true;
 767
 768         crtc_state->infoframes.enable |=
 769                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
 770
 771         ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
 772         if (drm_WARN_ON(encoder->base.dev, ret))
 773                 return false;
 774
 775         frame->sdi = HDMI_SPD_SDI_PC;
 776
 777         ret = hdmi_spd_infoframe_check(frame);
 778         if (drm_WARN_ON(encoder->base.dev, ret))
 779                 return false;
 780
 781         return true;
 782 }
 783
 784 static bool
 785 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
 786                                   struct intel_crtc_state *crtc_state,
 787                                   struct drm_connector_state *conn_state)
 788 {
 789         struct hdmi_vendor_infoframe *frame =
 790                 &crtc_state->infoframes.hdmi.vendor.hdmi;
 791         const struct drm_display_info *info =
 792                 &conn_state->connector->display_info;
 793         int ret;
 794
 795         if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
 796                 return true;
 797
 798         crtc_state->infoframes.enable |=
 799                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);
 800
 801         ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
 802                                                           conn_state->connector,
 803                                                           &crtc_state->hw.adjusted_mode);
 804         if (drm_WARN_ON(encoder->base.dev, ret))
 805                 return false;
 806
 807         ret = hdmi_vendor_infoframe_check(frame);
 808         if (drm_WARN_ON(encoder->base.dev, ret))
 809                 return false;
 810
 811         return true;
 812 }
 813
 814 static bool
 815 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
 816                                  struct intel_crtc_state *crtc_state,
 817                                  struct drm_connector_state *conn_state)
 818 {
 819         struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
 820         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 821         int ret;
 822
 823         if (DISPLAY_VER(dev_priv) < 10)
 824                 return true;
 825
 826         if (!crtc_state->has_infoframe)
 827                 return true;
 828
 829         if (!conn_state->hdr_output_metadata)
 830                 return true;
 831
 832         crtc_state->infoframes.enable |=
 833                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);
 834
 835         ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state);
 836         if (ret < 0) {
 837                 drm_dbg_kms(&dev_priv->drm,
 838                             "couldn't set HDR metadata in infoframe\n");
 839                 return false;
 840         }
 841
 842         ret = hdmi_drm_infoframe_check(frame);
 843         if (drm_WARN_ON(&dev_priv->drm, ret))
 844                 return false;
 845
 846         return true;
 847 }
 848
 849 static void g4x_set_infoframes(struct intel_encoder *encoder,
 850                                bool enable,
 851                                const struct intel_crtc_state *crtc_state,
 852                                const struct drm_connector_state *conn_state)
 853 {
 854         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 855         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 856         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
 857         i915_reg_t reg = VIDEO_DIP_CTL;
 858         u32 val = intel_de_read(dev_priv, reg);
 859         u32 port = VIDEO_DIP_PORT(encoder->port);
 860
 861         assert_hdmi_port_disabled(intel_hdmi);
 862
 863         /* If the registers were not initialized yet, they might be zeroes,
 864          * which means we're selecting the AVI DIP and we're setting its
 865          * frequency to once. This seems to really confuse the HW and make
 866          * things stop working (the register spec says the AVI always needs to
 867          * be sent every VSync). So here we avoid writing to the register more
 868          * than we need and also explicitly select the AVI DIP and explicitly
 869          * set its frequency to every VSync. Avoiding to write it twice seems to
 870          * be enough to solve the problem, but being defensive shouldn't hurt us
 871          * either. */
 872         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 873
 874         if (!enable) {
 875                 if (!(val & VIDEO_DIP_ENABLE))
 876                         return;
 877                 if (port != (val & VIDEO_DIP_PORT_MASK)) {
 878                         drm_dbg_kms(&dev_priv->drm,
 879                                     "video DIP still enabled on port %c\n",
 880                                     (val & VIDEO_DIP_PORT_MASK) >> 29);
 881                         return;
 882                 }
 883                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 884                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 885                 intel_de_write(dev_priv, reg, val);
 886                 intel_de_posting_read(dev_priv, reg);
 887                 return;
 888         }
 889
 890         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 891                 if (val & VIDEO_DIP_ENABLE) {
 892                         drm_dbg_kms(&dev_priv->drm,
 893                                     "video DIP already enabled on port %c\n",
 894                                     (val & VIDEO_DIP_PORT_MASK) >> 29);
 895                         return;
 896                 }
 897                 val &= ~VIDEO_DIP_PORT_MASK;
 898                 val |= port;
 899         }
 900
 901         val |= VIDEO_DIP_ENABLE;
 902         val &= ~(VIDEO_DIP_ENABLE_AVI |
 903                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 904
 905         intel_de_write(dev_priv, reg, val);
 906         intel_de_posting_read(dev_priv, reg);
 907
 908         intel_write_infoframe(encoder, crtc_state,
 909                               HDMI_INFOFRAME_TYPE_AVI,
 910                               &crtc_state->infoframes.avi);
 911         intel_write_infoframe(encoder, crtc_state,
 912                               HDMI_INFOFRAME_TYPE_SPD,
 913                               &crtc_state->infoframes.spd);
 914         intel_write_infoframe(encoder, crtc_state,
 915                               HDMI_INFOFRAME_TYPE_VENDOR,
 916                               &crtc_state->infoframes.hdmi);
 917 }
 918
 919 /*
 920  * Determine if default_phase=1 can be indicated in the GCP infoframe.
 921  *
 922  * From HDMI specification 1.4a:
 923  * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
 924  * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
 925  * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
 926  * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
 927  *   phase of 0
 928  */
 929 static bool gcp_default_phase_possible(int pipe_bpp,
 930                                        const struct drm_display_mode *mode)
 931 {
 932         unsigned int pixels_per_group;
 933
 934         switch (pipe_bpp) {
 935         case 30:
 936                 /* 4 pixels in 5 clocks */
 937                 pixels_per_group = 4;
 938                 break;
 939         case 36:
 940                 /* 2 pixels in 3 clocks */
 941                 pixels_per_group = 2;
 942                 break;
 943         case 48:
 944                 /* 1 pixel in 2 clocks */
 945                 pixels_per_group = 1;
 946                 break;
 947         default:
 948                 /* phase information not relevant for 8bpc */
 949                 return false;
 950         }
 951
 952         return mode->crtc_hdisplay % pixels_per_group == 0 &&
 953                 mode->crtc_htotal % pixels_per_group == 0 &&
 954                 mode->crtc_hblank_start % pixels_per_group == 0 &&
 955                 mode->crtc_hblank_end % pixels_per_group == 0 &&
 956                 mode->crtc_hsync_start % pixels_per_group == 0 &&
 957                 mode->crtc_hsync_end % pixels_per_group == 0 &&
 958                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
 959                  mode->crtc_htotal/2 % pixels_per_group == 0);
 960 }
 961
 962 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
 963                                          const struct intel_crtc_state *crtc_state,
 964                                          const struct drm_connector_state *conn_state)
 965 {
 966         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 967         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 968         i915_reg_t reg;
 969
 970         if ((crtc_state->infoframes.enable &
 971              intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
 972                 return false;
 973
 974         if (HAS_DDI(dev_priv))
 975                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
 976         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 977                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 978         else if (HAS_PCH_SPLIT(dev_priv))
 979                 reg = TVIDEO_DIP_GCP(crtc->pipe);
 980         else
 981                 return false;
 982
 983         intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp);
 984
 985         return true;
 986 }
 987
 988 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
 989                                    struct intel_crtc_state *crtc_state)
 990 {
 991         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 992         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 993         i915_reg_t reg;
 994
 995         if ((crtc_state->infoframes.enable &
 996              intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
 997                 return;
 998
 999         if (HAS_DDI(dev_priv))
1000                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
1001         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1002                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
1003         else if (HAS_PCH_SPLIT(dev_priv))
1004                 reg = TVIDEO_DIP_GCP(crtc->pipe);
1005         else
1006                 return;
1007
1008         crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg);
1009 }
1010
1011 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
1012                                              struct intel_crtc_state *crtc_state,
1013                                              struct drm_connector_state *conn_state)
1014 {
1015         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1016
1017         if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
1018                 return;
1019
1020         crtc_state->infoframes.enable |=
1021                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
1022
1023         /* Indicate color indication for deep color mode */
1024         if (crtc_state->pipe_bpp > 24)
1025                 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
1026
1027         /* Enable default_phase whenever the display mode is suitably aligned */
1028         if (gcp_default_phase_possible(crtc_state->pipe_bpp,
1029                                        &crtc_state->hw.adjusted_mode))
1030                 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
1031 }
1032
1033 static void ibx_set_infoframes(struct intel_encoder *encoder,
1034                                bool enable,
1035                                const struct intel_crtc_state *crtc_state,
1036                                const struct drm_connector_state *conn_state)
1037 {
1038         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1039         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
1040         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1041         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
1042         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
1043         u32 val = intel_de_read(dev_priv, reg);
1044         u32 port = VIDEO_DIP_PORT(encoder->port);
1045
1046         assert_hdmi_port_disabled(intel_hdmi);
1047
1048         /* See the big comment in g4x_set_infoframes() */
1049         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1050
1051         if (!enable) {
1052                 if (!(val & VIDEO_DIP_ENABLE))
1053                         return;
1054                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1055                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1056                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1057                 intel_de_write(dev_priv, reg, val);
1058                 intel_de_posting_read(dev_priv, reg);
1059                 return;
1060         }
1061
1062         if (port != (val & VIDEO_DIP_PORT_MASK)) {
1063                 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1064                          "DIP already enabled on port %c\n",
1065                          (val & VIDEO_DIP_PORT_MASK) >> 29);
1066                 val &= ~VIDEO_DIP_PORT_MASK;
1067                 val |= port;
1068         }
1069
1070         val |= VIDEO_DIP_ENABLE;
1071         val &= ~(VIDEO_DIP_ENABLE_AVI |
1072                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1073                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1074
1075         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1076                 val |= VIDEO_DIP_ENABLE_GCP;
1077
1078         intel_de_write(dev_priv, reg, val);
1079         intel_de_posting_read(dev_priv, reg);
1080
1081         intel_write_infoframe(encoder, crtc_state,
1082                               HDMI_INFOFRAME_TYPE_AVI,
1083                               &crtc_state->infoframes.avi);
1084         intel_write_infoframe(encoder, crtc_state,
1085                               HDMI_INFOFRAME_TYPE_SPD,
1086                               &crtc_state->infoframes.spd);
1087         intel_write_infoframe(encoder, crtc_state,
1088                               HDMI_INFOFRAME_TYPE_VENDOR,
1089                               &crtc_state->infoframes.hdmi);
1090 }
1091
1092 static void cpt_set_infoframes(struct intel_encoder *encoder,
1093                                bool enable,
1094                                const struct intel_crtc_state *crtc_state,
1095                                const struct drm_connector_state *conn_state)
1096 {
1097         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1098         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
1099         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1100         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
1101         u32 val = intel_de_read(dev_priv, reg);
1102
1103         assert_hdmi_port_disabled(intel_hdmi);
1104
1105         /* See the big comment in g4x_set_infoframes() */
1106         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1107
1108         if (!enable) {
1109                 if (!(val & VIDEO_DIP_ENABLE))
1110                         return;
1111                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1112                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1113                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1114                 intel_de_write(dev_priv, reg, val);
1115                 intel_de_posting_read(dev_priv, reg);
1116                 return;
1117         }
1118
1119         /* Set both together, unset both together: see the spec. */
1120         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
1121         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1122                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1123
1124         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1125                 val |= VIDEO_DIP_ENABLE_GCP;
1126
1127         intel_de_write(dev_priv, reg, val);
1128         intel_de_posting_read(dev_priv, reg);
1129
1130         intel_write_infoframe(encoder, crtc_state,
1131                               HDMI_INFOFRAME_TYPE_AVI,
1132                               &crtc_state->infoframes.avi);
1133         intel_write_infoframe(encoder, crtc_state,
1134                               HDMI_INFOFRAME_TYPE_SPD,
1135                               &crtc_state->infoframes.spd);
1136         intel_write_infoframe(encoder, crtc_state,
1137                               HDMI_INFOFRAME_TYPE_VENDOR,
1138                               &crtc_state->infoframes.hdmi);
1139 }
1140
1141 static void vlv_set_infoframes(struct intel_encoder *encoder,
1142                                bool enable,
1143                                const struct intel_crtc_state *crtc_state,
1144                                const struct drm_connector_state *conn_state)
1145 {
1146         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1147         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
1148         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1149         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
1150         u32 val = intel_de_read(dev_priv, reg);
1151         u32 port = VIDEO_DIP_PORT(encoder->port);
1152
1153         assert_hdmi_port_disabled(intel_hdmi);
1154
1155         /* See the big comment in g4x_set_infoframes() */
1156         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1157
1158         if (!enable) {
1159                 if (!(val & VIDEO_DIP_ENABLE))
1160                         return;
1161                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1162                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1163                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1164                 intel_de_write(dev_priv, reg, val);
1165                 intel_de_posting_read(dev_priv, reg);
1166                 return;
1167         }
1168
1169         if (port != (val & VIDEO_DIP_PORT_MASK)) {
1170                 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1171                          "DIP already enabled on port %c\n",
1172                          (val & VIDEO_DIP_PORT_MASK) >> 29);
1173                 val &= ~VIDEO_DIP_PORT_MASK;
1174                 val |= port;
1175         }
1176
1177         val |= VIDEO_DIP_ENABLE;
1178         val &= ~(VIDEO_DIP_ENABLE_AVI |
1179                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1180                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1181
1182         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1183                 val |= VIDEO_DIP_ENABLE_GCP;
1184
1185         intel_de_write(dev_priv, reg, val);
1186         intel_de_posting_read(dev_priv, reg);
1187
1188         intel_write_infoframe(encoder, crtc_state,
1189                               HDMI_INFOFRAME_TYPE_AVI,
1190                               &crtc_state->infoframes.avi);
1191         intel_write_infoframe(encoder, crtc_state,
1192                               HDMI_INFOFRAME_TYPE_SPD,
1193                               &crtc_state->infoframes.spd);
1194         intel_write_infoframe(encoder, crtc_state,
1195                               HDMI_INFOFRAME_TYPE_VENDOR,
1196                               &crtc_state->infoframes.hdmi);
1197 }
1198
1199 static void hsw_set_infoframes(struct intel_encoder *encoder,
1200                                bool enable,
1201                                const struct intel_crtc_state *crtc_state,
1202                                const struct drm_connector_state *conn_state)
1203 {
1204         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1205         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
1206         u32 val = intel_de_read(dev_priv, reg);
1207
1208         assert_hdmi_transcoder_func_disabled(dev_priv,
1209                                              crtc_state->cpu_transcoder);
1210
1211         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
1212                  VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
1213                  VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
1214                  VIDEO_DIP_ENABLE_DRM_GLK);
1215
1216         if (!enable) {
1217                 intel_de_write(dev_priv, reg, val);
1218                 intel_de_posting_read(dev_priv, reg);
1219                 return;
1220         }
1221
1222         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1223                 val |= VIDEO_DIP_ENABLE_GCP_HSW;
1224
1225         intel_de_write(dev_priv, reg, val);
1226         intel_de_posting_read(dev_priv, reg);
1227
1228         intel_write_infoframe(encoder, crtc_state,
1229                               HDMI_INFOFRAME_TYPE_AVI,
1230                               &crtc_state->infoframes.avi);
1231         intel_write_infoframe(encoder, crtc_state,
1232                               HDMI_INFOFRAME_TYPE_SPD,
1233                               &crtc_state->infoframes.spd);
1234         intel_write_infoframe(encoder, crtc_state,
1235                               HDMI_INFOFRAME_TYPE_VENDOR,
1236                               &crtc_state->infoframes.hdmi);
1237         intel_write_infoframe(encoder, crtc_state,
1238                               HDMI_INFOFRAME_TYPE_DRM,
1239                               &crtc_state->infoframes.drm);
1240 }
1241
1242 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
1243 {
1244         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1245         struct i2c_adapter *adapter =
1246                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1247
1248         if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
1249                 return;
1250
1251         drm_dbg_kms(&dev_priv->drm, "%s DP dual mode adaptor TMDS output\n",
1252                     enable ? "Enabling" : "Disabling");
1253
1254         drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
1255                                          adapter, enable);
1256 }
1257
1258 static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port,
1259                                 unsigned int offset, void *buffer, size_t size)
1260 {
1261         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1262         struct intel_hdmi *hdmi = &dig_port->hdmi;
1263         struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1264                                                               hdmi->ddc_bus);
1265         int ret;
1266         u8 start = offset & 0xff;
1267         struct i2c_msg msgs[] = {
1268                 {
1269                         .addr = DRM_HDCP_DDC_ADDR,
1270                         .flags = 0,
1271                         .len = 1,
1272                         .buf = &start,
1273                 },
1274                 {
1275                         .addr = DRM_HDCP_DDC_ADDR,
1276                         .flags = I2C_M_RD,
1277                         .len = size,
1278                         .buf = buffer
1279                 }
1280         };
1281         ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
1282         if (ret == ARRAY_SIZE(msgs))
1283                 return 0;
1284         return ret >= 0 ? -EIO : ret;
1285 }
1286
1287 static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port,
1288                                  unsigned int offset, void *buffer, size_t size)
1289 {
1290         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1291         struct intel_hdmi *hdmi = &dig_port->hdmi;
1292         struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1293                                                               hdmi->ddc_bus);
1294         int ret;
1295         u8 *write_buf;
1296         struct i2c_msg msg;
1297
1298         write_buf = kzalloc(size + 1, GFP_KERNEL);
1299         if (!write_buf)
1300                 return -ENOMEM;
1301
1302         write_buf[0] = offset & 0xff;
1303         memcpy(&write_buf[1], buffer, size);
1304
1305         msg.addr = DRM_HDCP_DDC_ADDR;
1306         msg.flags = 0,
1307         msg.len = size + 1,
1308         msg.buf = write_buf;
1309
1310         ret = i2c_transfer(adapter, &msg, 1);
1311         if (ret == 1)
1312                 ret = 0;
1313         else if (ret >= 0)
1314                 ret = -EIO;
1315
1316         kfree(write_buf);
1317         return ret;
1318 }
1319
1320 static
1321 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
1322                                   u8 *an)
1323 {
1324         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1325         struct intel_hdmi *hdmi = &dig_port->hdmi;
1326         struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1327                                                               hdmi->ddc_bus);
1328         int ret;
1329
1330         ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an,
1331                                     DRM_HDCP_AN_LEN);
1332         if (ret) {
1333                 drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n",
1334                             ret);
1335                 return ret;
1336         }
1337
1338         ret = intel_gmbus_output_aksv(adapter);
1339         if (ret < 0) {
1340                 drm_dbg_kms(&i915->drm, "Failed to output aksv (%d)\n", ret);
1341                 return ret;
1342         }
1343         return 0;
1344 }
1345
1346 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port,
1347                                      u8 *bksv)
1348 {
1349         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1350
1351         int ret;
1352         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv,
1353                                    DRM_HDCP_KSV_LEN);
1354         if (ret)
1355                 drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n",
1356                             ret);
1357         return ret;
1358 }
1359
1360 static
1361 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port,
1362                                  u8 *bstatus)
1363 {
1364         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1365
1366         int ret;
1367         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS,
1368                                    bstatus, DRM_HDCP_BSTATUS_LEN);
1369         if (ret)
1370                 drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n",
1371                             ret);
1372         return ret;
1373 }
1374
1375 static
1376 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port,
1377                                      bool *repeater_present)
1378 {
1379         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1380         int ret;
1381         u8 val;
1382
1383         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1384         if (ret) {
1385                 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1386                             ret);
1387                 return ret;
1388         }
1389         *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1390         return 0;
1391 }
1392
1393 static
1394 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
1395                                   u8 *ri_prime)
1396 {
1397         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1398
1399         int ret;
1400         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME,
1401                                    ri_prime, DRM_HDCP_RI_LEN);
1402         if (ret)
1403                 drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n",
1404                             ret);
1405         return ret;
1406 }
1407
1408 static
1409 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
1410                                    bool *ksv_ready)
1411 {
1412         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1413         int ret;
1414         u8 val;
1415
1416         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1417         if (ret) {
1418                 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1419                             ret);
1420                 return ret;
1421         }
1422         *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1423         return 0;
1424 }
1425
1426 static
1427 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
1428                                   int num_downstream, u8 *ksv_fifo)
1429 {
1430         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1431         int ret;
1432         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO,
1433                                    ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1434         if (ret) {
1435                 drm_dbg_kms(&i915->drm,
1436                             "Read ksv fifo over DDC failed (%d)\n", ret);
1437                 return ret;
1438         }
1439         return 0;
1440 }
1441
1442 static
1443 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
1444                                       int i, u32 *part)
1445 {
1446         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1447         int ret;
1448
1449         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1450                 return -EINVAL;
1451
1452         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i),
1453                                    part, DRM_HDCP_V_PRIME_PART_LEN);
1454         if (ret)
1455                 drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n",
1456                             i, ret);
1457         return ret;
1458 }
1459
1460 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector,
1461                                            enum transcoder cpu_transcoder)
1462 {
1463         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1464         struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1465         struct drm_crtc *crtc = connector->base.state->crtc;
1466         struct intel_crtc *intel_crtc = container_of(crtc,
1467                                                      struct intel_crtc, base);
1468         u32 scanline;
1469         int ret;
1470
1471         for (;;) {
1472                 scanline = intel_de_read(dev_priv, PIPEDSL(intel_crtc->pipe));
1473                 if (scanline > 100 && scanline < 200)
1474                         break;
1475                 usleep_range(25, 50);
1476         }
1477
1478         ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1479                                          false, TRANS_DDI_HDCP_SIGNALLING);
1480         if (ret) {
1481                 drm_err(&dev_priv->drm,
1482                         "Disable HDCP signalling failed (%d)\n", ret);
1483                 return ret;
1484         }
1485
1486         ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1487                                          true, TRANS_DDI_HDCP_SIGNALLING);
1488         if (ret) {
1489                 drm_err(&dev_priv->drm,
1490                         "Enable HDCP signalling failed (%d)\n", ret);
1491                 return ret;
1492         }
1493
1494         return 0;
1495 }
1496
1497 static
1498 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
1499                                       enum transcoder cpu_transcoder,
1500                                       bool enable)
1501 {
1502         struct intel_hdmi *hdmi = &dig_port->hdmi;
1503         struct intel_connector *connector = hdmi->attached_connector;
1504         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1505         int ret;
1506
1507         if (!enable)
1508                 usleep_range(6, 60); /* Bspec says >= 6us */
1509
1510         ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
1511                                          cpu_transcoder, enable,
1512                                          TRANS_DDI_HDCP_SIGNALLING);
1513         if (ret) {
1514                 drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n",
1515                         enable ? "Enable" : "Disable", ret);
1516                 return ret;
1517         }
1518
1519         /*
1520          * WA: To fix incorrect positioning of the window of
1521          * opportunity and enc_en signalling in KABYLAKE.
1522          */
1523         if (IS_KABYLAKE(dev_priv) && enable)
1524                 return kbl_repositioning_enc_en_signal(connector,
1525                                                        cpu_transcoder);
1526
1527         return 0;
1528 }
1529
1530 static
1531 bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port,
1532                                      struct intel_connector *connector)
1533 {
1534         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1535         enum port port = dig_port->base.port;
1536         enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
1537         int ret;
1538         union {
1539                 u32 reg;
1540                 u8 shim[DRM_HDCP_RI_LEN];
1541         } ri;
1542
1543         ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim);
1544         if (ret)
1545                 return false;
1546
1547         intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg);
1548
1549         /* Wait for Ri prime match */
1550         if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) &
1551                       (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) ==
1552                      (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1553                 drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n",
1554                         intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder,
1555                                                         port)));
1556                 return false;
1557         }
1558         return true;
1559 }
1560
1561 static
1562 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port,
1563                                 struct intel_connector *connector)
1564 {
1565         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1566         int retry;
1567
1568         for (retry = 0; retry < 3; retry++)
1569                 if (intel_hdmi_hdcp_check_link_once(dig_port, connector))
1570                         return true;
1571
1572         drm_err(&i915->drm, "Link check failed\n");
1573         return false;
1574 }
1575
1576 struct hdcp2_hdmi_msg_timeout {
1577         u8 msg_id;
1578         u16 timeout;
1579 };
1580
1581 static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = {
1582         { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, },
1583         { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, },
1584         { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, },
1585         { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, },
1586         { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, },
1587 };
1588
1589 static
1590 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port,
1591                                     u8 *rx_status)
1592 {
1593         return intel_hdmi_hdcp_read(dig_port,
1594                                     HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
1595                                     rx_status,
1596                                     HDCP_2_2_HDMI_RXSTATUS_LEN);
1597 }
1598
1599 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
1600 {
1601         int i;
1602
1603         if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) {
1604                 if (is_paired)
1605                         return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS;
1606                 else
1607                         return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS;
1608         }
1609
1610         for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) {
1611                 if (hdcp2_msg_timeout[i].msg_id == msg_id)
1612                         return hdcp2_msg_timeout[i].timeout;
1613         }
1614
1615         return -EINVAL;
1616 }
1617
1618 static int
1619 hdcp2_detect_msg_availability(struct intel_digital_port *dig_port,
1620                               u8 msg_id, bool *msg_ready,
1621                               ssize_t *msg_sz)
1622 {
1623         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1624         u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1625         int ret;
1626
1627         ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1628         if (ret < 0) {
1629                 drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n",
1630                             ret);
1631                 return ret;
1632         }
1633
1634         *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
1635                   rx_status[0]);
1636
1637         if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
1638                 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
1639                              *msg_sz);
1640         else
1641                 *msg_ready = *msg_sz;
1642
1643         return 0;
1644 }
1645
1646 static ssize_t
1647 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port,
1648                               u8 msg_id, bool paired)
1649 {
1650         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1651         bool msg_ready = false;
1652         int timeout, ret;
1653         ssize_t msg_sz = 0;
1654
1655         timeout = get_hdcp2_msg_timeout(msg_id, paired);
1656         if (timeout < 0)
1657                 return timeout;
1658
1659         ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port,
1660                                                              msg_id, &msg_ready,
1661                                                              &msg_sz),
1662                          !ret && msg_ready && msg_sz, timeout * 1000,
1663                          1000, 5 * 1000);
1664         if (ret)
1665                 drm_dbg_kms(&i915->drm, "msg_id: %d, ret: %d, timeout: %d\n",
1666                             msg_id, ret, timeout);
1667
1668         return ret ? ret : msg_sz;
1669 }
1670
1671 static
1672 int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *dig_port,
1673                                void *buf, size_t size)
1674 {
1675         unsigned int offset;
1676
1677         offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
1678         return intel_hdmi_hdcp_write(dig_port, offset, buf, size);
1679 }
1680
1681 static
1682 int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port,
1683                               u8 msg_id, void *buf, size_t size)
1684 {
1685         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1686         struct intel_hdmi *hdmi = &dig_port->hdmi;
1687         struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
1688         unsigned int offset;
1689         ssize_t ret;
1690
1691         ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id,
1692                                             hdcp->is_paired);
1693         if (ret < 0)
1694                 return ret;
1695
1696         /*
1697          * Available msg size should be equal to or lesser than the
1698          * available buffer.
1699          */
1700         if (ret > size) {
1701                 drm_dbg_kms(&i915->drm,
1702                             "msg_sz(%zd) is more than exp size(%zu)\n",
1703                             ret, size);
1704                 return -1;
1705         }
1706
1707         offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
1708         ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret);
1709         if (ret)
1710                 drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n",
1711                             msg_id, ret);
1712
1713         return ret;
1714 }
1715
1716 static
1717 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port,
1718                                 struct intel_connector *connector)
1719 {
1720         u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1721         int ret;
1722
1723         ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1724         if (ret)
1725                 return ret;
1726
1727         /*
1728          * Re-auth request and Link Integrity Failures are represented by
1729          * same bit. i.e reauth_req.
1730          */
1731         if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
1732                 ret = HDCP_REAUTH_REQUEST;
1733         else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
1734                 ret = HDCP_TOPOLOGY_CHANGE;
1735
1736         return ret;
1737 }
1738
1739 static
1740 int intel_hdmi_hdcp2_capable(struct intel_digital_port *dig_port,
1741                              bool *capable)
1742 {
1743         u8 hdcp2_version;
1744         int ret;
1745
1746         *capable = false;
1747         ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
1748                                    &hdcp2_version, sizeof(hdcp2_version));
1749         if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
1750                 *capable = true;
1751
1752         return ret;
1753 }
1754
1755 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1756         .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1757         .read_bksv = intel_hdmi_hdcp_read_bksv,
1758         .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1759         .repeater_present = intel_hdmi_hdcp_repeater_present,
1760         .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1761         .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1762         .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1763         .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1764         .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1765         .check_link = intel_hdmi_hdcp_check_link,
1766         .write_2_2_msg = intel_hdmi_hdcp2_write_msg,
1767         .read_2_2_msg = intel_hdmi_hdcp2_read_msg,
1768         .check_2_2_link = intel_hdmi_hdcp2_check_link,
1769         .hdcp_2_2_capable = intel_hdmi_hdcp2_capable,
1770         .protocol = HDCP_PROTOCOL_HDMI,
1771 };
1772
1773 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
1774 {
1775         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1776         int max_tmds_clock, vbt_max_tmds_clock;
1777
1778         if (DISPLAY_VER(dev_priv) >= 10)
1779                 max_tmds_clock = 594000;
1780         else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv))
1781                 max_tmds_clock = 300000;
1782         else if (DISPLAY_VER(dev_priv) >= 5)
1783                 max_tmds_clock = 225000;
1784         else
1785                 max_tmds_clock = 165000;
1786
1787         vbt_max_tmds_clock = intel_bios_max_tmds_clock(encoder);
1788         if (vbt_max_tmds_clock)
1789                 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock);
1790
1791         return max_tmds_clock;
1792 }
1793
1794 static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi,
1795                                 const struct drm_connector_state *conn_state)
1796 {
1797         return hdmi->has_hdmi_sink &&
1798                 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI;
1799 }
1800
1801 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1802                                  bool respect_downstream_limits,
1803                                  bool has_hdmi_sink)
1804 {
1805         struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1806         int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
1807
1808         if (respect_downstream_limits) {
1809                 struct intel_connector *connector = hdmi->attached_connector;
1810                 const struct drm_display_info *info = &connector->base.display_info;
1811
1812                 if (hdmi->dp_dual_mode.max_tmds_clock)
1813                         max_tmds_clock = min(max_tmds_clock,
1814                                              hdmi->dp_dual_mode.max_tmds_clock);
1815
1816                 if (info->max_tmds_clock)
1817                         max_tmds_clock = min(max_tmds_clock,
1818                                              info->max_tmds_clock);
1819                 else if (!has_hdmi_sink)
1820                         max_tmds_clock = min(max_tmds_clock, 165000);
1821         }
1822
1823         return max_tmds_clock;
1824 }
1825
1826 static enum drm_mode_status
1827 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1828                       int clock, bool respect_downstream_limits,
1829                       bool has_hdmi_sink)
1830 {
1831         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1832
1833         if (clock < 25000)
1834                 return MODE_CLOCK_LOW;
1835         if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits,
1836                                           has_hdmi_sink))
1837                 return MODE_CLOCK_HIGH;
1838
1839         /* GLK DPLL can't generate 446-480 MHz */
1840         if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000)
1841                 return MODE_CLOCK_RANGE;
1842
1843         /* BXT/GLK DPLL can't generate 223-240 MHz */
1844         if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
1845                 return MODE_CLOCK_RANGE;
1846
1847         /* CHV DPLL can't generate 216-240 MHz */
1848         if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1849                 return MODE_CLOCK_RANGE;
1850
1851         return MODE_OK;
1852 }
1853
1854 static int intel_hdmi_port_clock(int clock, int bpc)
1855 {
1856         /*
1857          * Need to adjust the port link by:
1858          *  1.5x for 12bpc
1859          *  1.25x for 10bpc
1860          */
1861         return clock * bpc / 8;
1862 }
1863
1864 static enum drm_mode_status
1865 intel_hdmi_mode_valid(struct drm_connector *connector,
1866                       struct drm_display_mode *mode)
1867 {
1868         struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
1869         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1870         struct drm_i915_private *dev_priv = to_i915(dev);
1871         enum drm_mode_status status;
1872         int clock = mode->clock;
1873         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1874         bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state);
1875
1876         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1877                 return MODE_NO_DBLESCAN;
1878
1879         if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1880                 clock *= 2;
1881
1882         if (clock > max_dotclk)
1883                 return MODE_CLOCK_HIGH;
1884
1885         if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1886                 if (!has_hdmi_sink)
1887                         return MODE_CLOCK_LOW;
1888                 clock *= 2;
1889         }
1890
1891         if (drm_mode_is_420_only(&connector->display_info, mode))
1892                 clock /= 2;
1893
1894         /* check if we can do 8bpc */
1895         status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 8),
1896                                        true, has_hdmi_sink);
1897
1898         if (has_hdmi_sink) {
1899                 /* if we can't do 8bpc we may still be able to do 12bpc */
1900                 if (status != MODE_OK && !HAS_GMCH(dev_priv))
1901                         status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 12),
1902                                                        true, has_hdmi_sink);
1903
1904                 /* if we can't do 8,12bpc we may still be able to do 10bpc */
1905                 if (status != MODE_OK && DISPLAY_VER(dev_priv) >= 11)
1906                         status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 10),
1907                                                        true, has_hdmi_sink);
1908         }
1909         if (status != MODE_OK)
1910                 return status;
1911
1912         return intel_mode_valid_max_plane_size(dev_priv, mode, false);
1913 }
1914
1915 bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
1916                                     int bpc, bool has_hdmi_sink, bool ycbcr420_output)
1917 {
1918         struct drm_atomic_state *state = crtc_state->uapi.state;
1919         struct drm_connector_state *connector_state;
1920         struct drm_connector *connector;
1921         int i;
1922
1923         if (crtc_state->pipe_bpp < bpc * 3)
1924                 return false;
1925
1926         if (!has_hdmi_sink)
1927                 return false;
1928
1929         for_each_new_connector_in_state(state, connector, connector_state, i) {
1930                 const struct drm_display_info *info = &connector->display_info;
1931
1932                 if (connector_state->crtc != crtc_state->uapi.crtc)
1933                         continue;
1934
1935                 if (ycbcr420_output) {
1936                         const struct drm_hdmi_info *hdmi = &info->hdmi;
1937
1938                         if (bpc == 12 && !(hdmi->y420_dc_modes &
1939                                            DRM_EDID_YCBCR420_DC_36))
1940                                 return false;
1941                         else if (bpc == 10 && !(hdmi->y420_dc_modes &
1942                                                 DRM_EDID_YCBCR420_DC_30))
1943                                 return false;
1944                 } else {
1945                         if (bpc == 12 && !(info->edid_hdmi_dc_modes &
1946                                            DRM_EDID_HDMI_DC_36))
1947                                 return false;
1948                         else if (bpc == 10 && !(info->edid_hdmi_dc_modes &
1949                                                 DRM_EDID_HDMI_DC_30))
1950                                 return false;
1951                 }
1952         }
1953
1954         return true;
1955 }
1956
1957 static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
1958                                      int bpc)
1959 {
1960         struct drm_i915_private *dev_priv =
1961                 to_i915(crtc_state->uapi.crtc->dev);
1962         const struct drm_display_mode *adjusted_mode =
1963                 &crtc_state->hw.adjusted_mode;
1964
1965         if (HAS_GMCH(dev_priv))
1966                 return false;
1967
1968         if (bpc == 10 && DISPLAY_VER(dev_priv) < 11)
1969                 return false;
1970
1971         /*
1972          * HDMI deep color affects the clocks, so it's only possible
1973          * when not cloning with other encoder types.
1974          */
1975         if (crtc_state->output_types != BIT(INTEL_OUTPUT_HDMI))
1976                 return false;
1977
1978         /* Display Wa_1405510057:icl,ehl */
1979         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
1980             bpc == 10 && IS_DISPLAY_VER(dev_priv, 11) &&
1981             (adjusted_mode->crtc_hblank_end -
1982              adjusted_mode->crtc_hblank_start) % 8 == 2)
1983                 return false;
1984
1985         return intel_hdmi_deep_color_possible(crtc_state, bpc,
1986                                               crtc_state->has_hdmi_sink,
1987                                               crtc_state->output_format ==
1988                                               INTEL_OUTPUT_FORMAT_YCBCR420);
1989 }
1990
1991 static int
1992 intel_hdmi_ycbcr420_config(struct intel_crtc_state *crtc_state,
1993                            const struct drm_connector_state *conn_state)
1994 {
1995         struct drm_connector *connector = conn_state->connector;
1996         struct drm_i915_private *i915 = to_i915(connector->dev);
1997         const struct drm_display_mode *adjusted_mode =
1998                 &crtc_state->hw.adjusted_mode;
1999
2000         if (!drm_mode_is_420_only(&connector->display_info, adjusted_mode))
2001                 return 0;
2002
2003         if (!connector->ycbcr_420_allowed) {
2004                 drm_err(&i915->drm,
2005                         "Platform doesn't support YCBCR420 output\n");
2006                 return -EINVAL;
2007         }
2008
2009         crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2010
2011         return intel_pch_panel_fitting(crtc_state, conn_state);
2012 }
2013
2014 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
2015                                   struct intel_crtc_state *crtc_state,
2016                                   int clock)
2017 {
2018         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2019         int bpc;
2020
2021         for (bpc = 12; bpc >= 10; bpc -= 2) {
2022                 if (hdmi_deep_color_possible(crtc_state, bpc) &&
2023                     hdmi_port_clock_valid(intel_hdmi,
2024                                           intel_hdmi_port_clock(clock, bpc),
2025                                           true, crtc_state->has_hdmi_sink) == MODE_OK)
2026                         return bpc;
2027         }
2028
2029         return 8;
2030 }
2031
2032 static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
2033                                     struct intel_crtc_state *crtc_state)
2034 {
2035         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2036         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2037         const struct drm_display_mode *adjusted_mode =
2038                 &crtc_state->hw.adjusted_mode;
2039         int bpc, clock = adjusted_mode->crtc_clock;
2040
2041         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2042                 clock *= 2;
2043
2044         /* YCBCR420 TMDS rate requirement is half the pixel clock */
2045         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2046                 clock /= 2;
2047
2048         bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock);
2049
2050         crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc);
2051
2052         /*
2053          * pipe_bpp could already be below 8bpc due to
2054          * FDI bandwidth constraints. We shouldn't bump it
2055          * back up to 8bpc in that case.
2056          */
2057         if (crtc_state->pipe_bpp > bpc * 3)
2058                 crtc_state->pipe_bpp = bpc * 3;
2059
2060         drm_dbg_kms(&i915->drm,
2061                     "picking %d bpc for HDMI output (pipe bpp: %d)\n",
2062                     bpc, crtc_state->pipe_bpp);
2063
2064         if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock,
2065                                   false, crtc_state->has_hdmi_sink) != MODE_OK) {
2066                 drm_dbg_kms(&i915->drm,
2067                             "unsupported HDMI clock (%d kHz), rejecting mode\n",
2068                             crtc_state->port_clock);
2069                 return -EINVAL;
2070         }
2071
2072         return 0;
2073 }
2074
2075 bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
2076                                     const struct drm_connector_state *conn_state)
2077 {
2078         const struct intel_digital_connector_state *intel_conn_state =
2079                 to_intel_digital_connector_state(conn_state);
2080         const struct drm_display_mode *adjusted_mode =
2081                 &crtc_state->hw.adjusted_mode;
2082
2083         /*
2084          * Our YCbCr output is always limited range.
2085          * crtc_state->limited_color_range only applies to RGB,
2086          * and it must never be set for YCbCr or we risk setting
2087          * some conflicting bits in PIPECONF which will mess up
2088          * the colors on the monitor.
2089          */
2090         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2091                 return false;
2092
2093         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2094                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
2095                 return crtc_state->has_hdmi_sink &&
2096                         drm_default_rgb_quant_range(adjusted_mode) ==
2097                         HDMI_QUANTIZATION_RANGE_LIMITED;
2098         } else {
2099                 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2100         }
2101 }
2102
2103 static bool intel_hdmi_has_audio(struct intel_encoder *encoder,
2104                                  const struct intel_crtc_state *crtc_state,
2105                                  const struct drm_connector_state *conn_state)
2106 {
2107         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2108         const struct intel_digital_connector_state *intel_conn_state =
2109                 to_intel_digital_connector_state(conn_state);
2110
2111         if (!crtc_state->has_hdmi_sink)
2112                 return false;
2113
2114         if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2115                 return intel_hdmi->has_audio;
2116         else
2117                 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2118 }
2119
2120 int intel_hdmi_compute_config(struct intel_encoder *encoder,
2121                               struct intel_crtc_state *pipe_config,
2122                               struct drm_connector_state *conn_state)
2123 {
2124         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2125         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2126         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2127         struct drm_connector *connector = conn_state->connector;
2128         struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
2129         int ret;
2130
2131         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2132                 return -EINVAL;
2133
2134         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2135         pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_hdmi,
2136                                                          conn_state);
2137
2138         if (pipe_config->has_hdmi_sink)
2139                 pipe_config->has_infoframe = true;
2140
2141         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2142                 pipe_config->pixel_multiplier = 2;
2143
2144         ret = intel_hdmi_ycbcr420_config(pipe_config, conn_state);
2145         if (ret)
2146                 return ret;
2147
2148         pipe_config->limited_color_range =
2149                 intel_hdmi_limited_color_range(pipe_config, conn_state);
2150
2151         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
2152                 pipe_config->has_pch_encoder = true;
2153
2154         pipe_config->has_audio =
2155                 intel_hdmi_has_audio(encoder, pipe_config, conn_state);
2156
2157         ret = intel_hdmi_compute_clock(encoder, pipe_config);
2158         if (ret)
2159                 return ret;
2160
2161         if (conn_state->picture_aspect_ratio)
2162                 adjusted_mode->picture_aspect_ratio =
2163                         conn_state->picture_aspect_ratio;
2164
2165         pipe_config->lane_count = 4;
2166
2167         if (scdc->scrambling.supported && DISPLAY_VER(dev_priv) >= 10) {
2168                 if (scdc->scrambling.low_rates)
2169                         pipe_config->hdmi_scrambling = true;
2170
2171                 if (pipe_config->port_clock > 340000) {
2172                         pipe_config->hdmi_scrambling = true;
2173                         pipe_config->hdmi_high_tmds_clock_ratio = true;
2174                 }
2175         }
2176
2177         intel_hdmi_compute_gcp_infoframe(encoder, pipe_config,
2178                                          conn_state);
2179
2180         if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
2181                 drm_dbg_kms(&dev_priv->drm, "bad AVI infoframe\n");
2182                 return -EINVAL;
2183         }
2184
2185         if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
2186                 drm_dbg_kms(&dev_priv->drm, "bad SPD infoframe\n");
2187                 return -EINVAL;
2188         }
2189
2190         if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
2191                 drm_dbg_kms(&dev_priv->drm, "bad HDMI infoframe\n");
2192                 return -EINVAL;
2193         }
2194
2195         if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) {
2196                 drm_dbg_kms(&dev_priv->drm, "bad DRM infoframe\n");
2197                 return -EINVAL;
2198         }
2199
2200         return 0;
2201 }
2202
2203 static void
2204 intel_hdmi_unset_edid(struct drm_connector *connector)
2205 {
2206         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2207
2208         intel_hdmi->has_hdmi_sink = false;
2209         intel_hdmi->has_audio = false;
2210
2211         intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
2212         intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
2213
2214         kfree(to_intel_connector(connector)->detect_edid);
2215         to_intel_connector(connector)->detect_edid = NULL;
2216 }
2217
2218 static void
2219 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
2220 {
2221         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2222         struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
2223         enum port port = hdmi_to_dig_port(hdmi)->base.port;
2224         struct i2c_adapter *adapter =
2225                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
2226         enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
2227
2228         /*
2229          * Type 1 DVI adaptors are not required to implement any
2230          * registers, so we can't always detect their presence.
2231          * Ideally we should be able to check the state of the
2232          * CONFIG1 pin, but no such luck on our hardware.
2233          *
2234          * The only method left to us is to check the VBT to see
2235          * if the port is a dual mode capable DP port. But let's
2236          * only do that when we sucesfully read the EDID, to avoid
2237          * confusing log messages about DP dual mode adaptors when
2238          * there's nothing connected to the port.
2239          */
2240         if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
2241                 /* An overridden EDID imply that we want this port for testing.
2242                  * Make sure not to set limits for that port.
2243                  */
2244                 if (has_edid && !connector->override_edid &&
2245                     intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2246                         drm_dbg_kms(&dev_priv->drm,
2247                                     "Assuming DP dual mode adaptor presence based on VBT\n");
2248                         type = DRM_DP_DUAL_MODE_TYPE1_DVI;
2249                 } else {
2250                         type = DRM_DP_DUAL_MODE_NONE;
2251                 }
2252         }
2253
2254         if (type == DRM_DP_DUAL_MODE_NONE)
2255                 return;
2256
2257         hdmi->dp_dual_mode.type = type;
2258         hdmi->dp_dual_mode.max_tmds_clock =
2259                 drm_dp_dual_mode_max_tmds_clock(type, adapter);
2260
2261         drm_dbg_kms(&dev_priv->drm,
2262                     "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2263                     drm_dp_get_dual_mode_type_name(type),
2264                     hdmi->dp_dual_mode.max_tmds_clock);
2265 }
2266
2267 static bool
2268 intel_hdmi_set_edid(struct drm_connector *connector)
2269 {
2270         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2271         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2272         intel_wakeref_t wakeref;
2273         struct edid *edid;
2274         bool connected = false;
2275         struct i2c_adapter *i2c;
2276
2277         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2278
2279         i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2280
2281         edid = drm_get_edid(connector, i2c);
2282
2283         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
2284                 drm_dbg_kms(&dev_priv->drm,
2285                             "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2286                 intel_gmbus_force_bit(i2c, true);
2287                 edid = drm_get_edid(connector, i2c);
2288                 intel_gmbus_force_bit(i2c, false);
2289         }
2290
2291         intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
2292
2293         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2294
2295         to_intel_connector(connector)->detect_edid = edid;
2296         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
2297                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
2298                 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
2299
2300                 connected = true;
2301         }
2302
2303         cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
2304
2305         return connected;
2306 }
2307
2308 static enum drm_connector_status
2309 intel_hdmi_detect(struct drm_connector *connector, bool force)
2310 {
2311         enum drm_connector_status status = connector_status_disconnected;
2312         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2313         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2314         struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2315         intel_wakeref_t wakeref;
2316
2317         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
2318                     connector->base.id, connector->name);
2319
2320         if (!INTEL_DISPLAY_ENABLED(dev_priv))
2321                 return connector_status_disconnected;
2322
2323         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2324
2325         if (DISPLAY_VER(dev_priv) >= 11 &&
2326             !intel_digital_port_connected(encoder))
2327                 goto out;
2328
2329         intel_hdmi_unset_edid(connector);
2330
2331         if (intel_hdmi_set_edid(connector))
2332                 status = connector_status_connected;
2333
2334 out:
2335         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2336
2337         if (status != connector_status_connected)
2338                 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
2339
2340         /*
2341          * Make sure the refs for power wells enabled during detect are
2342          * dropped to avoid a new detect cycle triggered by HPD polling.
2343          */
2344         intel_display_power_flush_work(dev_priv);
2345
2346         return status;
2347 }
2348
2349 static void
2350 intel_hdmi_force(struct drm_connector *connector)
2351 {
2352         struct drm_i915_private *i915 = to_i915(connector->dev);
2353
2354         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
2355                     connector->base.id, connector->name);
2356
2357         intel_hdmi_unset_edid(connector);
2358
2359         if (connector->status != connector_status_connected)
2360                 return;
2361
2362         intel_hdmi_set_edid(connector);
2363 }
2364
2365 static int intel_hdmi_get_modes(struct drm_connector *connector)
2366 {
2367         struct edid *edid;
2368
2369         edid = to_intel_connector(connector)->detect_edid;
2370         if (edid == NULL)
2371                 return 0;
2372
2373         return intel_connector_update_modes(connector, edid);
2374 }
2375
2376 static struct i2c_adapter *
2377 intel_hdmi_get_i2c_adapter(struct drm_connector *connector)
2378 {
2379         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2380         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2381
2382         return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2383 }
2384
2385 static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector)
2386 {
2387         struct drm_i915_private *i915 = to_i915(connector->dev);
2388         struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2389         struct kobject *i2c_kobj = &adapter->dev.kobj;
2390         struct kobject *connector_kobj = &connector->kdev->kobj;
2391         int ret;
2392
2393         ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name);
2394         if (ret)
2395                 drm_err(&i915->drm, "Failed to create i2c symlink (%d)\n", ret);
2396 }
2397
2398 static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector)
2399 {
2400         struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2401         struct kobject *i2c_kobj = &adapter->dev.kobj;
2402         struct kobject *connector_kobj = &connector->kdev->kobj;
2403
2404         sysfs_remove_link(connector_kobj, i2c_kobj->name);
2405 }
2406
2407 static int
2408 intel_hdmi_connector_register(struct drm_connector *connector)
2409 {
2410         int ret;
2411
2412         ret = intel_connector_register(connector);
2413         if (ret)
2414                 return ret;
2415
2416         intel_hdmi_create_i2c_symlink(connector);
2417
2418         return ret;
2419 }
2420
2421 static void intel_hdmi_connector_unregister(struct drm_connector *connector)
2422 {
2423         struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier;
2424
2425         cec_notifier_conn_unregister(n);
2426
2427         intel_hdmi_remove_i2c_symlink(connector);
2428         intel_connector_unregister(connector);
2429 }
2430
2431 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2432         .detect = intel_hdmi_detect,
2433         .force = intel_hdmi_force,
2434         .fill_modes = drm_helper_probe_single_connector_modes,
2435         .atomic_get_property = intel_digital_connector_atomic_get_property,
2436         .atomic_set_property = intel_digital_connector_atomic_set_property,
2437         .late_register = intel_hdmi_connector_register,
2438         .early_unregister = intel_hdmi_connector_unregister,
2439         .destroy = intel_connector_destroy,
2440         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2441         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2442 };
2443
2444 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2445         .get_modes = intel_hdmi_get_modes,
2446         .mode_valid = intel_hdmi_mode_valid,
2447         .atomic_check = intel_digital_connector_atomic_check,
2448 };
2449
2450 static void
2451 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2452 {
2453         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2454
2455         intel_attach_force_audio_property(connector);
2456         intel_attach_broadcast_rgb_property(connector);
2457         intel_attach_aspect_ratio_property(connector);
2458
2459         intel_attach_hdmi_colorspace_property(connector);
2460         drm_connector_attach_content_type_property(connector);
2461
2462         if (DISPLAY_VER(dev_priv) >= 10)
2463                 drm_object_attach_property(&connector->base,
2464                         connector->dev->mode_config.hdr_output_metadata_property, 0);
2465
2466         if (!HAS_GMCH(dev_priv))
2467                 drm_connector_attach_max_bpc_property(connector, 8, 12);
2468 }
2469
2470 /*
2471  * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2472  * @encoder: intel_encoder
2473  * @connector: drm_connector
2474  * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2475  *  or reset the high tmds clock ratio for scrambling
2476  * @scrambling: bool to Indicate if the function needs to set or reset
2477  *  sink scrambling
2478  *
2479  * This function handles scrambling on HDMI 2.0 capable sinks.
2480  * If required clock rate is > 340 Mhz && scrambling is supported by sink
2481  * it enables scrambling. This should be called before enabling the HDMI
2482  * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2483  * detect a scrambled clock within 100 ms.
2484  *
2485  * Returns:
2486  * True on success, false on failure.
2487  */
2488 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2489                                        struct drm_connector *connector,
2490                                        bool high_tmds_clock_ratio,
2491                                        bool scrambling)
2492 {
2493         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2494         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2495         struct drm_scrambling *sink_scrambling =
2496                 &connector->display_info.hdmi.scdc.scrambling;
2497         struct i2c_adapter *adapter =
2498                 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2499
2500         if (!sink_scrambling->supported)
2501                 return true;
2502
2503         drm_dbg_kms(&dev_priv->drm,
2504                     "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2505                     connector->base.id, connector->name,
2506                     yesno(scrambling), high_tmds_clock_ratio ? 40 : 10);
2507
2508         /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2509         return drm_scdc_set_high_tmds_clock_ratio(adapter,
2510                                                   high_tmds_clock_ratio) &&
2511                 drm_scdc_set_scrambling(adapter, scrambling);
2512 }
2513
2514 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2515 {
2516         u8 ddc_pin;
2517
2518         switch (port) {
2519         case PORT_B:
2520                 ddc_pin = GMBUS_PIN_DPB;
2521                 break;
2522         case PORT_C:
2523                 ddc_pin = GMBUS_PIN_DPC;
2524                 break;
2525         case PORT_D:
2526                 ddc_pin = GMBUS_PIN_DPD_CHV;
2527                 break;
2528         default:
2529                 MISSING_CASE(port);
2530                 ddc_pin = GMBUS_PIN_DPB;
2531                 break;
2532         }
2533         return ddc_pin;
2534 }
2535
2536 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2537 {
2538         u8 ddc_pin;
2539
2540         switch (port) {
2541         case PORT_B:
2542                 ddc_pin = GMBUS_PIN_1_BXT;
2543                 break;
2544         case PORT_C:
2545                 ddc_pin = GMBUS_PIN_2_BXT;
2546                 break;
2547         default:
2548                 MISSING_CASE(port);
2549                 ddc_pin = GMBUS_PIN_1_BXT;
2550                 break;
2551         }
2552         return ddc_pin;
2553 }
2554
2555 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2556                               enum port port)
2557 {
2558         u8 ddc_pin;
2559
2560         switch (port) {
2561         case PORT_B:
2562                 ddc_pin = GMBUS_PIN_1_BXT;
2563                 break;
2564         case PORT_C:
2565                 ddc_pin = GMBUS_PIN_2_BXT;
2566                 break;
2567         case PORT_D:
2568                 ddc_pin = GMBUS_PIN_4_CNP;
2569                 break;
2570         case PORT_F:
2571                 ddc_pin = GMBUS_PIN_3_BXT;
2572                 break;
2573         default:
2574                 MISSING_CASE(port);
2575                 ddc_pin = GMBUS_PIN_1_BXT;
2576                 break;
2577         }
2578         return ddc_pin;
2579 }
2580
2581 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2582 {
2583         enum phy phy = intel_port_to_phy(dev_priv, port);
2584
2585         if (intel_phy_is_combo(dev_priv, phy))
2586                 return GMBUS_PIN_1_BXT + port;
2587         else if (intel_phy_is_tc(dev_priv, phy))
2588                 return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
2589
2590         drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port));
2591         return GMBUS_PIN_2_BXT;
2592 }
2593
2594 static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2595 {
2596         enum phy phy = intel_port_to_phy(dev_priv, port);
2597         u8 ddc_pin;
2598
2599         switch (phy) {
2600         case PHY_A:
2601                 ddc_pin = GMBUS_PIN_1_BXT;
2602                 break;
2603         case PHY_B:
2604                 ddc_pin = GMBUS_PIN_2_BXT;
2605                 break;
2606         case PHY_C:
2607                 ddc_pin = GMBUS_PIN_9_TC1_ICP;
2608                 break;
2609         default:
2610                 MISSING_CASE(phy);
2611                 ddc_pin = GMBUS_PIN_1_BXT;
2612                 break;
2613         }
2614         return ddc_pin;
2615 }
2616
2617 static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2618 {
2619         enum phy phy = intel_port_to_phy(dev_priv, port);
2620
2621         WARN_ON(port == PORT_C);
2622
2623         /*
2624          * Pin mapping for RKL depends on which PCH is present.  With TGP, the
2625          * final two outputs use type-c pins, even though they're actually
2626          * combo outputs.  With CMP, the traditional DDI A-D pins are used for
2627          * all outputs.
2628          */
2629         if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C)
2630                 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2631
2632         return GMBUS_PIN_1_BXT + phy;
2633 }
2634
2635 static u8 gen9bc_tgp_port_to_ddc_pin(struct drm_i915_private *i915, enum port port)
2636 {
2637         enum phy phy = intel_port_to_phy(i915, port);
2638
2639         drm_WARN_ON(&i915->drm, port == PORT_A);
2640
2641         /*
2642          * Pin mapping for GEN9 BC depends on which PCH is present.  With TGP,
2643          * final two outputs use type-c pins, even though they're actually
2644          * combo outputs.  With CMP, the traditional DDI A-D pins are used for
2645          * all outputs.
2646          */
2647         if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C)
2648                 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2649
2650         return GMBUS_PIN_1_BXT + phy;
2651 }
2652
2653 static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2654 {
2655         return intel_port_to_phy(dev_priv, port) + 1;
2656 }
2657
2658 static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2659 {
2660         enum phy phy = intel_port_to_phy(dev_priv, port);
2661
2662         WARN_ON(port == PORT_B || port == PORT_C);
2663
2664         /*
2665          * Pin mapping for ADL-S requires TC pins for all combo phy outputs
2666          * except first combo output.
2667          */
2668         if (phy == PHY_A)
2669                 return GMBUS_PIN_1_BXT;
2670
2671         return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;
2672 }
2673
2674 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2675                               enum port port)
2676 {
2677         u8 ddc_pin;
2678
2679         switch (port) {
2680         case PORT_B:
2681                 ddc_pin = GMBUS_PIN_DPB;
2682                 break;
2683         case PORT_C:
2684                 ddc_pin = GMBUS_PIN_DPC;
2685                 break;
2686         case PORT_D:
2687                 ddc_pin = GMBUS_PIN_DPD;
2688                 break;
2689         default:
2690                 MISSING_CASE(port);
2691                 ddc_pin = GMBUS_PIN_DPB;
2692                 break;
2693         }
2694         return ddc_pin;
2695 }
2696
2697 static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
2698 {
2699         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2700         enum port port = encoder->port;
2701         u8 ddc_pin;
2702
2703         ddc_pin = intel_bios_alternate_ddc_pin(encoder);
2704         if (ddc_pin) {
2705                 drm_dbg_kms(&dev_priv->drm,
2706                             "Using DDC pin 0x%x for port %c (VBT)\n",
2707                             ddc_pin, port_name(port));
2708                 return ddc_pin;
2709         }
2710
2711         if (HAS_PCH_ADP(dev_priv))
2712                 ddc_pin = adls_port_to_ddc_pin(dev_priv, port);
2713         else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
2714                 ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
2715         else if (IS_ROCKETLAKE(dev_priv))
2716                 ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
2717         else if (IS_GEN9_BC(dev_priv) && HAS_PCH_TGP(dev_priv))
2718                 ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port);
2719         else if (HAS_PCH_MCC(dev_priv))
2720                 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
2721         else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2722                 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
2723         else if (HAS_PCH_CNP(dev_priv))
2724                 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
2725         else if (IS_GEN9_LP(dev_priv))
2726                 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
2727         else if (IS_CHERRYVIEW(dev_priv))
2728                 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
2729         else
2730                 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
2731
2732         drm_dbg_kms(&dev_priv->drm,
2733                     "Using DDC pin 0x%x for port %c (platform default)\n",
2734                     ddc_pin, port_name(port));
2735
2736         return ddc_pin;
2737 }
2738
2739 void intel_infoframe_init(struct intel_digital_port *dig_port)
2740 {
2741         struct drm_i915_private *dev_priv =
2742                 to_i915(dig_port->base.base.dev);
2743
2744         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2745                 dig_port->write_infoframe = vlv_write_infoframe;
2746                 dig_port->read_infoframe = vlv_read_infoframe;
2747                 dig_port->set_infoframes = vlv_set_infoframes;
2748                 dig_port->infoframes_enabled = vlv_infoframes_enabled;
2749         } else if (IS_G4X(dev_priv)) {
2750                 dig_port->write_infoframe = g4x_write_infoframe;
2751                 dig_port->read_infoframe = g4x_read_infoframe;
2752                 dig_port->set_infoframes = g4x_set_infoframes;
2753                 dig_port->infoframes_enabled = g4x_infoframes_enabled;
2754         } else if (HAS_DDI(dev_priv)) {
2755                 if (intel_bios_is_lspcon_present(dev_priv, dig_port->base.port)) {
2756                         dig_port->write_infoframe = lspcon_write_infoframe;
2757                         dig_port->read_infoframe = lspcon_read_infoframe;
2758                         dig_port->set_infoframes = lspcon_set_infoframes;
2759                         dig_port->infoframes_enabled = lspcon_infoframes_enabled;
2760                 } else {
2761                         dig_port->write_infoframe = hsw_write_infoframe;
2762                         dig_port->read_infoframe = hsw_read_infoframe;
2763                         dig_port->set_infoframes = hsw_set_infoframes;
2764                         dig_port->infoframes_enabled = hsw_infoframes_enabled;
2765                 }
2766         } else if (HAS_PCH_IBX(dev_priv)) {
2767                 dig_port->write_infoframe = ibx_write_infoframe;
2768                 dig_port->read_infoframe = ibx_read_infoframe;
2769                 dig_port->set_infoframes = ibx_set_infoframes;
2770                 dig_port->infoframes_enabled = ibx_infoframes_enabled;
2771         } else {
2772                 dig_port->write_infoframe = cpt_write_infoframe;
2773                 dig_port->read_infoframe = cpt_read_infoframe;
2774                 dig_port->set_infoframes = cpt_set_infoframes;
2775                 dig_port->infoframes_enabled = cpt_infoframes_enabled;
2776         }
2777 }
2778
2779 void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
2780                                struct intel_connector *intel_connector)
2781 {
2782         struct drm_connector *connector = &intel_connector->base;
2783         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2784         struct intel_encoder *intel_encoder = &dig_port->base;
2785         struct drm_device *dev = intel_encoder->base.dev;
2786         struct drm_i915_private *dev_priv = to_i915(dev);
2787         struct i2c_adapter *ddc;
2788         enum port port = intel_encoder->port;
2789         struct cec_connector_info conn_info;
2790
2791         drm_dbg_kms(&dev_priv->drm,
2792                     "Adding HDMI connector on [ENCODER:%d:%s]\n",
2793                     intel_encoder->base.base.id, intel_encoder->base.name);
2794
2795         if (DISPLAY_VER(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A))
2796                 return;
2797
2798         if (drm_WARN(dev, dig_port->max_lanes < 4,
2799                      "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n",
2800                      dig_port->max_lanes, intel_encoder->base.base.id,
2801                      intel_encoder->base.name))
2802                 return;
2803
2804         intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(intel_encoder);
2805         ddc = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2806
2807         drm_connector_init_with_ddc(dev, connector,
2808                                     &intel_hdmi_connector_funcs,
2809                                     DRM_MODE_CONNECTOR_HDMIA,
2810                                     ddc);
2811         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2812
2813         connector->interlace_allowed = 1;
2814         connector->doublescan_allowed = 0;
2815         connector->stereo_allowed = 1;
2816
2817         if (DISPLAY_VER(dev_priv) >= 10)
2818                 connector->ycbcr_420_allowed = true;
2819
2820         intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
2821
2822         if (HAS_DDI(dev_priv))
2823                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2824         else
2825                 intel_connector->get_hw_state = intel_connector_get_hw_state;
2826
2827         intel_hdmi_add_properties(intel_hdmi, connector);
2828
2829         intel_connector_attach_encoder(intel_connector, intel_encoder);
2830         intel_hdmi->attached_connector = intel_connector;
2831
2832         if (is_hdcp_supported(dev_priv, port)) {
2833                 int ret = intel_hdcp_init(intel_connector, dig_port,
2834                                           &intel_hdmi_hdcp_shim);
2835                 if (ret)
2836                         drm_dbg_kms(&dev_priv->drm,
2837                                     "HDCP init failed, skipping.\n");
2838         }
2839
2840         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2841          * 0xd.  Failure to do so will result in spurious interrupts being
2842          * generated on the port when a cable is not attached.
2843          */
2844         if (IS_G45(dev_priv)) {
2845                 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
2846                 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
2847                                (temp & ~0xf) | 0xd);
2848         }
2849
2850         cec_fill_conn_info_from_drm(&conn_info, connector);
2851
2852         intel_hdmi->cec_notifier =
2853                 cec_notifier_conn_register(dev->dev, port_identifier(port),
2854                                            &conn_info);
2855         if (!intel_hdmi->cec_notifier)
2856                 drm_dbg_kms(&dev_priv->drm, "CEC notifier get failed\n");
2857 }
2858
2859 /*
2860  * intel_hdmi_dsc_get_slice_height - get the dsc slice_height
2861  * @vactive: Vactive of a display mode
2862  *
2863  * @return: appropriate dsc slice height for a given mode.
2864  */
2865 int intel_hdmi_dsc_get_slice_height(int vactive)
2866 {
2867         int slice_height;
2868
2869         /*
2870          * Slice Height determination : HDMI2.1 Section 7.7.5.2
2871          * Select smallest slice height >=96, that results in a valid PPS and
2872          * requires minimum padding lines required for final slice.
2873          *
2874          * Assumption : Vactive is even.
2875          */
2876         for (slice_height = 96; slice_height <= vactive; slice_height += 2)
2877                 if (vactive % slice_height == 0)
2878                         return slice_height;
2879
2880         return 0;
2881 }
2882
2883 /*
2884  * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder
2885  * and dsc decoder capabilities
2886  *
2887  * @crtc_state: intel crtc_state
2888  * @src_max_slices: maximum slices supported by the DSC encoder
2889  * @src_max_slice_width: maximum slice width supported by DSC encoder
2890  * @hdmi_max_slices: maximum slices supported by sink DSC decoder
2891  * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink
2892  *
2893  * @return: num of dsc slices that can be supported by the dsc encoder
2894  * and decoder.
2895  */
2896 int
2897 intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state,
2898                               int src_max_slices, int src_max_slice_width,
2899                               int hdmi_max_slices, int hdmi_throughput)
2900 {
2901 /* Pixel rates in KPixels/sec */
2902 #define HDMI_DSC_PEAK_PIXEL_RATE                2720000
2903 /*
2904  * Rates at which the source and sink are required to process pixels in each
2905  * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz.
2906  */
2907 #define HDMI_DSC_MAX_ENC_THROUGHPUT_0           340000
2908 #define HDMI_DSC_MAX_ENC_THROUGHPUT_1           400000
2909
2910 /* Spec limits the slice width to 2720 pixels */
2911 #define MAX_HDMI_SLICE_WIDTH                    2720
2912         int kslice_adjust;
2913         int adjusted_clk_khz;
2914         int min_slices;
2915         int target_slices;
2916         int max_throughput; /* max clock freq. in khz per slice */
2917         int max_slice_width;
2918         int slice_width;
2919         int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock;
2920
2921         if (!hdmi_throughput)
2922                 return 0;
2923
2924         /*
2925          * Slice Width determination : HDMI2.1 Section 7.7.5.1
2926          * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as
2927          * for 4:4:4 is 1.0. Multiplying these factors by 10 and later
2928          * dividing adjusted clock value by 10.
2929          */
2930         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
2931             crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
2932                 kslice_adjust = 10;
2933         else
2934                 kslice_adjust = 5;
2935
2936         /*
2937          * As per spec, the rate at which the source and the sink process
2938          * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz.
2939          * This depends upon the pixel clock rate and output formats
2940          * (kslice adjust).
2941          * If pixel clock * kslice adjust >= 2720MHz slices can be processed
2942          * at max 340MHz, otherwise they can be processed at max 400MHz.
2943          */
2944
2945         adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10);
2946
2947         if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE)
2948                 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0;
2949         else
2950                 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1;
2951
2952         /*
2953          * Taking into account the sink's capability for maximum
2954          * clock per slice (in MHz) as read from HF-VSDB.
2955          */
2956         max_throughput = min(max_throughput, hdmi_throughput * 1000);
2957
2958         min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput);
2959         max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width);
2960
2961         /*
2962          * Keep on increasing the num of slices/line, starting from min_slices
2963          * per line till we get such a number, for which the slice_width is
2964          * just less than max_slice_width. The slices/line selected should be
2965          * less than or equal to the max horizontal slices that the combination
2966          * of PCON encoder and HDMI decoder can support.
2967          */
2968         slice_width = max_slice_width;
2969
2970         do {
2971                 if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1)
2972                         target_slices = 1;
2973                 else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2)
2974                         target_slices = 2;
2975                 else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4)
2976                         target_slices = 4;
2977                 else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8)
2978                         target_slices = 8;
2979                 else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12)
2980                         target_slices = 12;
2981                 else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16)
2982                         target_slices = 16;
2983                 else
2984                         return 0;
2985
2986                 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices);
2987                 if (slice_width >= max_slice_width)
2988                         min_slices = target_slices + 1;
2989         } while (slice_width >= max_slice_width);
2990
2991         return target_slices;
2992 }
2993
2994 /*
2995  * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on
2996  * source and sink capabilities.
2997  *
2998  * @src_fraction_bpp: fractional bpp supported by the source
2999  * @slice_width: dsc slice width supported by the source and sink
3000  * @num_slices: num of slices supported by the source and sink
3001  * @output_format: video output format
3002  * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting
3003  * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink
3004  *
3005  * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel
3006  */
3007 int
3008 intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices,
3009                        int output_format, bool hdmi_all_bpp,
3010                        int hdmi_max_chunk_bytes)
3011 {
3012         int max_dsc_bpp, min_dsc_bpp;
3013         int target_bytes;
3014         bool bpp_found = false;
3015         int bpp_decrement_x16;
3016         int bpp_target;
3017         int bpp_target_x16;
3018
3019         /*
3020          * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec
3021          * Start with the max bpp and keep on decrementing with
3022          * fractional bpp, if supported by PCON DSC encoder
3023          *
3024          * for each bpp we check if no of bytes can be supported by HDMI sink
3025          */
3026
3027         /* Assuming: bpc as 8*/
3028         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3029                 min_dsc_bpp = 6;
3030                 max_dsc_bpp = 3 * 4; /* 3*bpc/2 */
3031         } else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
3032                    output_format == INTEL_OUTPUT_FORMAT_RGB) {
3033                 min_dsc_bpp = 8;
3034                 max_dsc_bpp = 3 * 8; /* 3*bpc */
3035         } else {
3036                 /* Assuming 4:2:2 encoding */
3037                 min_dsc_bpp = 7;
3038                 max_dsc_bpp = 2 * 8; /* 2*bpc */
3039         }
3040
3041         /*
3042          * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink
3043          * Section 7.7.34 : Source shall not enable compressed Video
3044          * Transport with bpp_target settings above 12 bpp unless
3045          * DSC_all_bpp is set to 1.
3046          */
3047         if (!hdmi_all_bpp)
3048                 max_dsc_bpp = min(max_dsc_bpp, 12);
3049
3050         /*
3051          * The Sink has a limit of compressed data in bytes for a scanline,
3052          * as described in max_chunk_bytes field in HFVSDB block of edid.
3053          * The no. of bytes depend on the target bits per pixel that the
3054          * source configures. So we start with the max_bpp and calculate
3055          * the target_chunk_bytes. We keep on decrementing the target_bpp,
3056          * till we get the target_chunk_bytes just less than what the sink's
3057          * max_chunk_bytes, or else till we reach the min_dsc_bpp.
3058          *
3059          * The decrement is according to the fractional support from PCON DSC
3060          * encoder. For fractional BPP we use bpp_target as a multiple of 16.
3061          *
3062          * bpp_target_x16 = bpp_target * 16
3063          * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps
3064          * {1/16, 1/8, 1/4, 1/2, 1} respectively.
3065          */
3066
3067         bpp_target = max_dsc_bpp;
3068
3069         /* src does not support fractional bpp implies decrement by 16 for bppx16 */
3070         if (!src_fractional_bpp)
3071                 src_fractional_bpp = 1;
3072         bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp);
3073         bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16;
3074
3075         while (bpp_target_x16 > (min_dsc_bpp * 16)) {
3076                 int bpp;
3077
3078                 bpp = DIV_ROUND_UP(bpp_target_x16, 16);
3079                 target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8);
3080                 if (target_bytes <= hdmi_max_chunk_bytes) {
3081                         bpp_found = true;
3082                         break;
3083                 }
3084                 bpp_target_x16 -= bpp_decrement_x16;
3085         }
3086         if (bpp_found)
3087                 return bpp_target_x16;
3088
3089         return 0;
3090 }