drivers/gpu/drm/i915/display/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/export.h>
  29 #include <linux/i2c.h>
  30 #include <linux/notifier.h>
  31 #include <linux/slab.h>
  32 #include <linux/string_helpers.h>
  33 #include <linux/timekeeping.h>
  34 #include <linux/types.h>
  35
  36 #include <asm/byteorder.h>
  37
  38 #include <drm/display/drm_dp_helper.h>
  39 #include <drm/display/drm_dsc_helper.h>
  40 #include <drm/display/drm_hdmi_helper.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_crtc.h>
  43 #include <drm/drm_edid.h>
  44 #include <drm/drm_probe_helper.h>
  45
  46 #include "g4x_dp.h"
  47 #include "i915_debugfs.h"
  48 #include "i915_drv.h"
  49 #include "intel_atomic.h"
  50 #include "intel_audio.h"
  51 #include "intel_backlight.h"
  52 #include "intel_combo_phy_regs.h"
  53 #include "intel_connector.h"
  54 #include "intel_crtc.h"
  55 #include "intel_ddi.h"
  56 #include "intel_de.h"
  57 #include "intel_display_types.h"
  58 #include "intel_dp.h"
  59 #include "intel_dp_aux.h"
  60 #include "intel_dp_hdcp.h"
  61 #include "intel_dp_link_training.h"
  62 #include "intel_dp_mst.h"
  63 #include "intel_dpio_phy.h"
  64 #include "intel_dpll.h"
  65 #include "intel_fifo_underrun.h"
  66 #include "intel_hdcp.h"
  67 #include "intel_hdmi.h"
  68 #include "intel_hotplug.h"
  69 #include "intel_lspcon.h"
  70 #include "intel_lvds.h"
  71 #include "intel_panel.h"
  72 #include "intel_pch_display.h"
  73 #include "intel_pps.h"
  74 #include "intel_psr.h"
  75 #include "intel_tc.h"
  76 #include "intel_vdsc.h"
  77 #include "intel_vrr.h"
  78
  79 /* DP DSC throughput values used for slice count calculations KPixels/s */
  80 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  81 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  82 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  83
  84 /* DP DSC FEC Overhead factor = 1/(0.972261) */
  85 #define DP_DSC_FEC_OVERHEAD_FACTOR              972261
  86
  87 /* Compliance test status bits  */
  88 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  89 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  90 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  91 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  92
  93
  94 /* Constants for DP DSC configurations */
  95 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
  96
  97 /* With Single pipe configuration, HW is capable of supporting maximum
  98  * of 4 slices per line.
  99  */
 100 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 101
 102 /**
 103  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 104  * @intel_dp: DP struct
 105  *
 106  * If a CPU or PCH DP output is attached to an eDP panel, this function
 107  * will return true, and false otherwise.
 108  *
 109  * This function is not safe to use prior to encoder type being set.
 110  */
 111 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 112 {
 113         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 114
 115         return dig_port->base.type == INTEL_OUTPUT_EDP;
 116 }
 117
 118 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 119 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
 120
 121 /* Is link rate UHBR and thus 128b/132b? */
 122 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
 123 {
 124         return crtc_state->port_clock >= 1000000;
 125 }
 126
 127 static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
 128 {
 129         intel_dp->sink_rates[0] = 162000;
 130         intel_dp->num_sink_rates = 1;
 131 }
 132
 133 /* update sink rates from dpcd */
 134 static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
 135 {
 136         static const int dp_rates[] = {
 137                 162000, 270000, 540000, 810000
 138         };
 139         int i, max_rate;
 140         int max_lttpr_rate;
 141
 142         if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
 143                 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
 144                 static const int quirk_rates[] = { 162000, 270000, 324000 };
 145
 146                 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
 147                 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
 148
 149                 return;
 150         }
 151
 152         /*
 153          * Sink rates for 8b/10b.
 154          */
 155         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 156         max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
 157         if (max_lttpr_rate)
 158                 max_rate = min(max_rate, max_lttpr_rate);
 159
 160         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 161                 if (dp_rates[i] > max_rate)
 162                         break;
 163                 intel_dp->sink_rates[i] = dp_rates[i];
 164         }
 165
 166         /*
 167          * Sink rates for 128b/132b. If set, sink should support all 8b/10b
 168          * rates and 10 Gbps.
 169          */
 170         if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) {
 171                 u8 uhbr_rates = 0;
 172
 173                 BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);
 174
 175                 drm_dp_dpcd_readb(&intel_dp->aux,
 176                                   DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates);
 177
 178                 if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) {
 179                         /* We have a repeater */
 180                         if (intel_dp->lttpr_common_caps[0] >= 0x20 &&
 181                             intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
 182                                                         DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] &
 183                             DP_PHY_REPEATER_128B132B_SUPPORTED) {
 184                                 /* Repeater supports 128b/132b, valid UHBR rates */
 185                                 uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES -
 186                                                                           DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
 187                         } else {
 188                                 /* Does not support 128b/132b */
 189                                 uhbr_rates = 0;
 190                         }
 191                 }
 192
 193                 if (uhbr_rates & DP_UHBR10)
 194                         intel_dp->sink_rates[i++] = 1000000;
 195                 if (uhbr_rates & DP_UHBR13_5)
 196                         intel_dp->sink_rates[i++] = 1350000;
 197                 if (uhbr_rates & DP_UHBR20)
 198                         intel_dp->sink_rates[i++] = 2000000;
 199         }
 200
 201         intel_dp->num_sink_rates = i;
 202 }
 203
 204 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 205 {
 206         struct intel_connector *connector = intel_dp->attached_connector;
 207         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 208         struct intel_encoder *encoder = &intel_dig_port->base;
 209
 210         intel_dp_set_dpcd_sink_rates(intel_dp);
 211
 212         if (intel_dp->num_sink_rates)
 213                 return;
 214
 215         drm_err(&dp_to_i915(intel_dp)->drm,
 216                 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n",
 217                 connector->base.base.id, connector->base.name,
 218                 encoder->base.base.id, encoder->base.name);
 219
 220         intel_dp_set_default_sink_rates(intel_dp);
 221 }
 222
 223 static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp)
 224 {
 225         intel_dp->max_sink_lane_count = 1;
 226 }
 227
 228 static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp)
 229 {
 230         struct intel_connector *connector = intel_dp->attached_connector;
 231         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 232         struct intel_encoder *encoder = &intel_dig_port->base;
 233
 234         intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 235
 236         switch (intel_dp->max_sink_lane_count) {
 237         case 1:
 238         case 2:
 239         case 4:
 240                 return;
 241         }
 242
 243         drm_err(&dp_to_i915(intel_dp)->drm,
 244                 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n",
 245                 connector->base.base.id, connector->base.name,
 246                 encoder->base.base.id, encoder->base.name,
 247                 intel_dp->max_sink_lane_count);
 248
 249         intel_dp_set_default_max_sink_lane_count(intel_dp);
 250 }
 251
 252 /* Get length of rates array potentially limited by max_rate. */
 253 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 254 {
 255         int i;
 256
 257         /* Limit results by potentially reduced max rate */
 258         for (i = 0; i < len; i++) {
 259                 if (rates[len - i - 1] <= max_rate)
 260                         return len - i;
 261         }
 262
 263         return 0;
 264 }
 265
 266 /* Get length of common rates array potentially limited by max_rate. */
 267 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 268                                           int max_rate)
 269 {
 270         return intel_dp_rate_limit_len(intel_dp->common_rates,
 271                                        intel_dp->num_common_rates, max_rate);
 272 }
 273
 274 static int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
 275 {
 276         if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
 277                         index < 0 || index >= intel_dp->num_common_rates))
 278                 return 162000;
 279
 280         return intel_dp->common_rates[index];
 281 }
 282
 283 /* Theoretical max between source and sink */
 284 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 285 {
 286         return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
 287 }
 288
 289 /* Theoretical max between source and sink */
 290 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 291 {
 292         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 293         int source_max = dig_port->max_lanes;
 294         int sink_max = intel_dp->max_sink_lane_count;
 295         int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
 296         int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
 297
 298         if (lttpr_max)
 299                 sink_max = min(sink_max, lttpr_max);
 300
 301         return min3(source_max, sink_max, fia_max);
 302 }
 303
 304 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 305 {
 306         switch (intel_dp->max_link_lane_count) {
 307         case 1:
 308         case 2:
 309         case 4:
 310                 return intel_dp->max_link_lane_count;
 311         default:
 312                 MISSING_CASE(intel_dp->max_link_lane_count);
 313                 return 1;
 314         }
 315 }
 316
 317 /*
 318  * The required data bandwidth for a mode with given pixel clock and bpp. This
 319  * is the required net bandwidth independent of the data bandwidth efficiency.
 320  */
 321 int
 322 intel_dp_link_required(int pixel_clock, int bpp)
 323 {
 324         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 325         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 326 }
 327
 328 /*
 329  * Given a link rate and lanes, get the data bandwidth.
 330  *
 331  * Data bandwidth is the actual payload rate, which depends on the data
 332  * bandwidth efficiency and the link rate.
 333  *
 334  * For 8b/10b channel encoding, SST and non-FEC, the data bandwidth efficiency
 335  * is 80%. For example, for a 1.62 Gbps link, 1.62*10^9 bps * 0.80 * (1/8) =
 336  * 162000 kBps. With 8-bit symbols, we have 162000 kHz symbol clock. Just by
 337  * coincidence, the port clock in kHz matches the data bandwidth in kBps, and
 338  * they equal the link bit rate in Gbps multiplied by 100000. (Note that this no
 339  * longer holds for data bandwidth as soon as FEC or MST is taken into account!)
 340  *
 341  * For 128b/132b channel encoding, the data bandwidth efficiency is 96.71%. For
 342  * example, for a 10 Gbps link, 10*10^9 bps * 0.9671 * (1/8) = 1208875
 343  * kBps. With 32-bit symbols, we have 312500 kHz symbol clock. The value 1000000
 344  * does not match the symbol clock, the port clock (not even if you think in
 345  * terms of a byte clock), nor the data bandwidth. It only matches the link bit
 346  * rate in units of 10000 bps.
 347  */
 348 int
 349 intel_dp_max_data_rate(int max_link_rate, int max_lanes)
 350 {
 351         if (max_link_rate >= 1000000) {
 352                 /*
 353                  * UHBR rates always use 128b/132b channel encoding, and have
 354                  * 97.71% data bandwidth efficiency. Consider max_link_rate the
 355                  * link bit rate in units of 10000 bps.
 356                  */
 357                 int max_link_rate_kbps = max_link_rate * 10;
 358
 359                 max_link_rate_kbps = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(max_link_rate_kbps, 9671), 10000);
 360                 max_link_rate = max_link_rate_kbps / 8;
 361         }
 362
 363         /*
 364          * Lower than UHBR rates always use 8b/10b channel encoding, and have
 365          * 80% data bandwidth efficiency for SST non-FEC. However, this turns
 366          * out to be a nop by coincidence, and can be skipped:
 367          *
 368          *      int max_link_rate_kbps = max_link_rate * 10;
 369          *      max_link_rate_kbps = DIV_ROUND_CLOSEST_ULL(max_link_rate_kbps * 8, 10);
 370          *      max_link_rate = max_link_rate_kbps / 8;
 371          */
 372
 373         return max_link_rate * max_lanes;
 374 }
 375
 376 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
 377 {
 378         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 379         struct intel_encoder *encoder = &intel_dig_port->base;
 380         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 381
 382         return DISPLAY_VER(dev_priv) >= 12 ||
 383                 (DISPLAY_VER(dev_priv) == 11 &&
 384                  encoder->port != PORT_A);
 385 }
 386
 387 static int dg2_max_source_rate(struct intel_dp *intel_dp)
 388 {
 389         return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
 390 }
 391
 392 static bool is_low_voltage_sku(struct drm_i915_private *i915, enum phy phy)
 393 {
 394         u32 voltage;
 395
 396         voltage = intel_de_read(i915, ICL_PORT_COMP_DW3(phy)) & VOLTAGE_INFO_MASK;
 397
 398         return voltage == VOLTAGE_INFO_0_85V;
 399 }
 400
 401 static int icl_max_source_rate(struct intel_dp *intel_dp)
 402 {
 403         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 404         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 405         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 406
 407         if (intel_phy_is_combo(dev_priv, phy) &&
 408             (is_low_voltage_sku(dev_priv, phy) || !intel_dp_is_edp(intel_dp)))
 409                 return 540000;
 410
 411         return 810000;
 412 }
 413
 414 static int ehl_max_source_rate(struct intel_dp *intel_dp)
 415 {
 416         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 417         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 418         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 419
 420         if (intel_dp_is_edp(intel_dp) || is_low_voltage_sku(dev_priv, phy))
 421                 return 540000;
 422
 423         return 810000;
 424 }
 425
 426 static int dg1_max_source_rate(struct intel_dp *intel_dp)
 427 {
 428         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 429         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 430         enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
 431
 432         if (intel_phy_is_combo(i915, phy) && is_low_voltage_sku(i915, phy))
 433                 return 540000;
 434
 435         return 810000;
 436 }
 437
 438 static int vbt_max_link_rate(struct intel_dp *intel_dp)
 439 {
 440         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 441         int max_rate;
 442
 443         max_rate = intel_bios_dp_max_link_rate(encoder);
 444
 445         if (intel_dp_is_edp(intel_dp)) {
 446                 struct intel_connector *connector = intel_dp->attached_connector;
 447                 int edp_max_rate = connector->panel.vbt.edp.max_link_rate;
 448
 449                 if (max_rate && edp_max_rate)
 450                         max_rate = min(max_rate, edp_max_rate);
 451                 else if (edp_max_rate)
 452                         max_rate = edp_max_rate;
 453         }
 454
 455         return max_rate;
 456 }
 457
 458 static void
 459 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 460 {
 461         /* The values must be in increasing order */
 462         static const int icl_rates[] = {
 463                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
 464                 1000000, 1350000,
 465         };
 466         static const int bxt_rates[] = {
 467                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 468         };
 469         static const int skl_rates[] = {
 470                 162000, 216000, 270000, 324000, 432000, 540000
 471         };
 472         static const int hsw_rates[] = {
 473                 162000, 270000, 540000
 474         };
 475         static const int g4x_rates[] = {
 476                 162000, 270000
 477         };
 478         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 479         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 480         const int *source_rates;
 481         int size, max_rate = 0, vbt_max_rate;
 482
 483         /* This should only be done once */
 484         drm_WARN_ON(&dev_priv->drm,
 485                     intel_dp->source_rates || intel_dp->num_source_rates);
 486
 487         if (DISPLAY_VER(dev_priv) >= 11) {
 488                 source_rates = icl_rates;
 489                 size = ARRAY_SIZE(icl_rates);
 490                 if (IS_DG2(dev_priv))
 491                         max_rate = dg2_max_source_rate(intel_dp);
 492                 else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
 493                          IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
 494                         max_rate = dg1_max_source_rate(intel_dp);
 495                 else if (IS_JSL_EHL(dev_priv))
 496                         max_rate = ehl_max_source_rate(intel_dp);
 497                 else
 498                         max_rate = icl_max_source_rate(intel_dp);
 499         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 500                 source_rates = bxt_rates;
 501                 size = ARRAY_SIZE(bxt_rates);
 502         } else if (DISPLAY_VER(dev_priv) == 9) {
 503                 source_rates = skl_rates;
 504                 size = ARRAY_SIZE(skl_rates);
 505         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 506                    IS_BROADWELL(dev_priv)) {
 507                 source_rates = hsw_rates;
 508                 size = ARRAY_SIZE(hsw_rates);
 509         } else {
 510                 source_rates = g4x_rates;
 511                 size = ARRAY_SIZE(g4x_rates);
 512         }
 513
 514         vbt_max_rate = vbt_max_link_rate(intel_dp);
 515         if (max_rate && vbt_max_rate)
 516                 max_rate = min(max_rate, vbt_max_rate);
 517         else if (vbt_max_rate)
 518                 max_rate = vbt_max_rate;
 519
 520         if (max_rate)
 521                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 522
 523         intel_dp->source_rates = source_rates;
 524         intel_dp->num_source_rates = size;
 525 }
 526
 527 static int intersect_rates(const int *source_rates, int source_len,
 528                            const int *sink_rates, int sink_len,
 529                            int *common_rates)
 530 {
 531         int i = 0, j = 0, k = 0;
 532
 533         while (i < source_len && j < sink_len) {
 534                 if (source_rates[i] == sink_rates[j]) {
 535                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 536                                 return k;
 537                         common_rates[k] = source_rates[i];
 538                         ++k;
 539                         ++i;
 540                         ++j;
 541                 } else if (source_rates[i] < sink_rates[j]) {
 542                         ++i;
 543                 } else {
 544                         ++j;
 545                 }
 546         }
 547         return k;
 548 }
 549
 550 /* return index of rate in rates array, or -1 if not found */
 551 static int intel_dp_rate_index(const int *rates, int len, int rate)
 552 {
 553         int i;
 554
 555         for (i = 0; i < len; i++)
 556                 if (rate == rates[i])
 557                         return i;
 558
 559         return -1;
 560 }
 561
 562 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 563 {
 564         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 565
 566         drm_WARN_ON(&i915->drm,
 567                     !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 568
 569         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 570                                                      intel_dp->num_source_rates,
 571                                                      intel_dp->sink_rates,
 572                                                      intel_dp->num_sink_rates,
 573                                                      intel_dp->common_rates);
 574
 575         /* Paranoia, there should always be something in common. */
 576         if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
 577                 intel_dp->common_rates[0] = 162000;
 578                 intel_dp->num_common_rates = 1;
 579         }
 580 }
 581
 582 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 583                                        u8 lane_count)
 584 {
 585         /*
 586          * FIXME: we need to synchronize the current link parameters with
 587          * hardware readout. Currently fast link training doesn't work on
 588          * boot-up.
 589          */
 590         if (link_rate == 0 ||
 591             link_rate > intel_dp->max_link_rate)
 592                 return false;
 593
 594         if (lane_count == 0 ||
 595             lane_count > intel_dp_max_lane_count(intel_dp))
 596                 return false;
 597
 598         return true;
 599 }
 600
 601 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 602                                                      int link_rate,
 603                                                      u8 lane_count)
 604 {
 605         /* FIXME figure out what we actually want here */
 606         const struct drm_display_mode *fixed_mode =
 607                 intel_panel_preferred_fixed_mode(intel_dp->attached_connector);
 608         int mode_rate, max_rate;
 609
 610         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 611         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 612         if (mode_rate > max_rate)
 613                 return false;
 614
 615         return true;
 616 }
 617
 618 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 619                                             int link_rate, u8 lane_count)
 620 {
 621         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 622         int index;
 623
 624         /*
 625          * TODO: Enable fallback on MST links once MST link compute can handle
 626          * the fallback params.
 627          */
 628         if (intel_dp->is_mst) {
 629                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 630                 return -1;
 631         }
 632
 633         if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
 634                 drm_dbg_kms(&i915->drm,
 635                             "Retrying Link training for eDP with max parameters\n");
 636                 intel_dp->use_max_params = true;
 637                 return 0;
 638         }
 639
 640         index = intel_dp_rate_index(intel_dp->common_rates,
 641                                     intel_dp->num_common_rates,
 642                                     link_rate);
 643         if (index > 0) {
 644                 if (intel_dp_is_edp(intel_dp) &&
 645                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 646                                                               intel_dp_common_rate(intel_dp, index - 1),
 647                                                               lane_count)) {
 648                         drm_dbg_kms(&i915->drm,
 649                                     "Retrying Link training for eDP with same parameters\n");
 650                         return 0;
 651                 }
 652                 intel_dp->max_link_rate = intel_dp_common_rate(intel_dp, index - 1);
 653                 intel_dp->max_link_lane_count = lane_count;
 654         } else if (lane_count > 1) {
 655                 if (intel_dp_is_edp(intel_dp) &&
 656                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 657                                                               intel_dp_max_common_rate(intel_dp),
 658                                                               lane_count >> 1)) {
 659                         drm_dbg_kms(&i915->drm,
 660                                     "Retrying Link training for eDP with same parameters\n");
 661                         return 0;
 662                 }
 663                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 664                 intel_dp->max_link_lane_count = lane_count >> 1;
 665         } else {
 666                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 667                 return -1;
 668         }
 669
 670         return 0;
 671 }
 672
 673 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
 674 {
 675         return div_u64(mul_u32_u32(mode_clock, 1000000U),
 676                        DP_DSC_FEC_OVERHEAD_FACTOR);
 677 }
 678
 679 static int
 680 small_joiner_ram_size_bits(struct drm_i915_private *i915)
 681 {
 682         if (DISPLAY_VER(i915) >= 13)
 683                 return 17280 * 8;
 684         else if (DISPLAY_VER(i915) >= 11)
 685                 return 7680 * 8;
 686         else
 687                 return 6144 * 8;
 688 }
 689
 690 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 691                                        u32 link_clock, u32 lane_count,
 692                                        u32 mode_clock, u32 mode_hdisplay,
 693                                        bool bigjoiner,
 694                                        u32 pipe_bpp)
 695 {
 696         u32 bits_per_pixel, max_bpp_small_joiner_ram;
 697         int i;
 698
 699         /*
 700          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
 701          * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
 702          * for SST -> TimeSlotsPerMTP is 1,
 703          * for MST -> TimeSlotsPerMTP has to be calculated
 704          */
 705         bits_per_pixel = (link_clock * lane_count * 8) /
 706                          intel_dp_mode_to_fec_clock(mode_clock);
 707
 708         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
 709         max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
 710                 mode_hdisplay;
 711
 712         if (bigjoiner)
 713                 max_bpp_small_joiner_ram *= 2;
 714
 715         /*
 716          * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
 717          * check, output bpp from small joiner RAM check)
 718          */
 719         bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
 720
 721         if (bigjoiner) {
 722                 u32 max_bpp_bigjoiner =
 723                         i915->max_cdclk_freq * 48 /
 724                         intel_dp_mode_to_fec_clock(mode_clock);
 725
 726                 bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
 727         }
 728
 729         /* Error out if the max bpp is less than smallest allowed valid bpp */
 730         if (bits_per_pixel < valid_dsc_bpp[0]) {
 731                 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
 732                             bits_per_pixel, valid_dsc_bpp[0]);
 733                 return 0;
 734         }
 735
 736         /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */
 737         if (DISPLAY_VER(i915) >= 13) {
 738                 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
 739         } else {
 740                 /* Find the nearest match in the array of known BPPs from VESA */
 741                 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
 742                         if (bits_per_pixel < valid_dsc_bpp[i + 1])
 743                                 break;
 744                 }
 745                 bits_per_pixel = valid_dsc_bpp[i];
 746         }
 747
 748         /*
 749          * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
 750          * fractional part is 0
 751          */
 752         return bits_per_pixel << 4;
 753 }
 754
 755 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 756                                        int mode_clock, int mode_hdisplay,
 757                                        bool bigjoiner)
 758 {
 759         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 760         u8 min_slice_count, i;
 761         int max_slice_width;
 762
 763         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
 764                 min_slice_count = DIV_ROUND_UP(mode_clock,
 765                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
 766         else
 767                 min_slice_count = DIV_ROUND_UP(mode_clock,
 768                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
 769
 770         max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
 771         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
 772                 drm_dbg_kms(&i915->drm,
 773                             "Unsupported slice width %d by DP DSC Sink device\n",
 774                             max_slice_width);
 775                 return 0;
 776         }
 777         /* Also take into account max slice width */
 778         min_slice_count = max_t(u8, min_slice_count,
 779                                 DIV_ROUND_UP(mode_hdisplay,
 780                                              max_slice_width));
 781
 782         /* Find the closest match to the valid slice count values */
 783         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
 784                 u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
 785
 786                 if (test_slice_count >
 787                     drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
 788                         break;
 789
 790                 /* big joiner needs small joiner to be enabled */
 791                 if (bigjoiner && test_slice_count < 4)
 792                         continue;
 793
 794                 if (min_slice_count <= test_slice_count)
 795                         return test_slice_count;
 796         }
 797
 798         drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
 799                     min_slice_count);
 800         return 0;
 801 }
 802
 803 static enum intel_output_format
 804 intel_dp_output_format(struct intel_connector *connector,
 805                        bool ycbcr_420_output)
 806 {
 807         struct intel_dp *intel_dp = intel_attached_dp(connector);
 808
 809         if (!connector->base.ycbcr_420_allowed || !ycbcr_420_output)
 810                 return INTEL_OUTPUT_FORMAT_RGB;
 811
 812         if (intel_dp->dfp.rgb_to_ycbcr &&
 813             intel_dp->dfp.ycbcr_444_to_420)
 814                 return INTEL_OUTPUT_FORMAT_RGB;
 815
 816         if (intel_dp->dfp.ycbcr_444_to_420)
 817                 return INTEL_OUTPUT_FORMAT_YCBCR444;
 818         else
 819                 return INTEL_OUTPUT_FORMAT_YCBCR420;
 820 }
 821
 822 int intel_dp_min_bpp(enum intel_output_format output_format)
 823 {
 824         if (output_format == INTEL_OUTPUT_FORMAT_RGB)
 825                 return 6 * 3;
 826         else
 827                 return 8 * 3;
 828 }
 829
 830 static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
 831 {
 832         /*
 833          * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
 834          * format of the number of bytes per pixel will be half the number
 835          * of bytes of RGB pixel.
 836          */
 837         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 838                 bpp /= 2;
 839
 840         return bpp;
 841 }
 842
 843 static int
 844 intel_dp_mode_min_output_bpp(struct intel_connector *connector,
 845                              const struct drm_display_mode *mode)
 846 {
 847         const struct drm_display_info *info = &connector->base.display_info;
 848         enum intel_output_format output_format =
 849                 intel_dp_output_format(connector, drm_mode_is_420_only(info, mode));
 850
 851         return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
 852 }
 853
 854 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
 855                                   int hdisplay)
 856 {
 857         /*
 858          * Older platforms don't like hdisplay==4096 with DP.
 859          *
 860          * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
 861          * and frame counter increment), but we don't get vblank interrupts,
 862          * and the pipe underruns immediately. The link also doesn't seem
 863          * to get trained properly.
 864          *
 865          * On CHV the vblank interrupts don't seem to disappear but
 866          * otherwise the symptoms are similar.
 867          *
 868          * TODO: confirm the behaviour on HSW+
 869          */
 870         return hdisplay == 4096 && !HAS_DDI(dev_priv);
 871 }
 872
 873 static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp)
 874 {
 875         struct intel_connector *connector = intel_dp->attached_connector;
 876         const struct drm_display_info *info = &connector->base.display_info;
 877         int max_tmds_clock = intel_dp->dfp.max_tmds_clock;
 878
 879         /* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */
 880         if (max_tmds_clock && info->max_tmds_clock)
 881                 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
 882
 883         return max_tmds_clock;
 884 }
 885
 886 static enum drm_mode_status
 887 intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
 888                           int clock, int bpc, bool ycbcr420_output,
 889                           bool respect_downstream_limits)
 890 {
 891         int tmds_clock, min_tmds_clock, max_tmds_clock;
 892
 893         if (!respect_downstream_limits)
 894                 return MODE_OK;
 895
 896         tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
 897
 898         min_tmds_clock = intel_dp->dfp.min_tmds_clock;
 899         max_tmds_clock = intel_dp_max_tmds_clock(intel_dp);
 900
 901         if (min_tmds_clock && tmds_clock < min_tmds_clock)
 902                 return MODE_CLOCK_LOW;
 903
 904         if (max_tmds_clock && tmds_clock > max_tmds_clock)
 905                 return MODE_CLOCK_HIGH;
 906
 907         return MODE_OK;
 908 }
 909
 910 static enum drm_mode_status
 911 intel_dp_mode_valid_downstream(struct intel_connector *connector,
 912                                const struct drm_display_mode *mode,
 913                                int target_clock)
 914 {
 915         struct intel_dp *intel_dp = intel_attached_dp(connector);
 916         const struct drm_display_info *info = &connector->base.display_info;
 917         enum drm_mode_status status;
 918         bool ycbcr_420_only;
 919
 920         /* If PCON supports FRL MODE, check FRL bandwidth constraints */
 921         if (intel_dp->dfp.pcon_max_frl_bw) {
 922                 int target_bw;
 923                 int max_frl_bw;
 924                 int bpp = intel_dp_mode_min_output_bpp(connector, mode);
 925
 926                 target_bw = bpp * target_clock;
 927
 928                 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
 929
 930                 /* converting bw from Gbps to Kbps*/
 931                 max_frl_bw = max_frl_bw * 1000000;
 932
 933                 if (target_bw > max_frl_bw)
 934                         return MODE_CLOCK_HIGH;
 935
 936                 return MODE_OK;
 937         }
 938
 939         if (intel_dp->dfp.max_dotclock &&
 940             target_clock > intel_dp->dfp.max_dotclock)
 941                 return MODE_CLOCK_HIGH;
 942
 943         ycbcr_420_only = drm_mode_is_420_only(info, mode);
 944
 945         /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
 946         status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
 947                                            8, ycbcr_420_only, true);
 948
 949         if (status != MODE_OK) {
 950                 if (ycbcr_420_only ||
 951                     !connector->base.ycbcr_420_allowed ||
 952                     !drm_mode_is_420_also(info, mode))
 953                         return status;
 954
 955                 status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
 956                                                    8, true, true);
 957                 if (status != MODE_OK)
 958                         return status;
 959         }
 960
 961         return MODE_OK;
 962 }
 963
 964 static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
 965                                     int hdisplay, int clock)
 966 {
 967         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 968
 969         if (!intel_dp_can_bigjoiner(intel_dp))
 970                 return false;
 971
 972         return clock > i915->max_dotclk_freq || hdisplay > 5120;
 973 }
 974
 975 static enum drm_mode_status
 976 intel_dp_mode_valid(struct drm_connector *_connector,
 977                     struct drm_display_mode *mode)
 978 {
 979         struct intel_connector *connector = to_intel_connector(_connector);
 980         struct intel_dp *intel_dp = intel_attached_dp(connector);
 981         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 982         const struct drm_display_mode *fixed_mode;
 983         int target_clock = mode->clock;
 984         int max_rate, mode_rate, max_lanes, max_link_clock;
 985         int max_dotclk = dev_priv->max_dotclk_freq;
 986         u16 dsc_max_output_bpp = 0;
 987         u8 dsc_slice_count = 0;
 988         enum drm_mode_status status;
 989         bool dsc = false, bigjoiner = false;
 990
 991         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 992                 return MODE_NO_DBLESCAN;
 993
 994         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 995                 return MODE_H_ILLEGAL;
 996
 997         fixed_mode = intel_panel_fixed_mode(connector, mode);
 998         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 999                 status = intel_panel_mode_valid(connector, mode);
1000                 if (status != MODE_OK)
1001                         return status;
1002
1003                 target_clock = fixed_mode->clock;
1004         }
1005
1006         if (mode->clock < 10000)
1007                 return MODE_CLOCK_LOW;
1008
1009         if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) {
1010                 bigjoiner = true;
1011                 max_dotclk *= 2;
1012         }
1013         if (target_clock > max_dotclk)
1014                 return MODE_CLOCK_HIGH;
1015
1016         max_link_clock = intel_dp_max_link_rate(intel_dp);
1017         max_lanes = intel_dp_max_lane_count(intel_dp);
1018
1019         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
1020         mode_rate = intel_dp_link_required(target_clock,
1021                                            intel_dp_mode_min_output_bpp(connector, mode));
1022
1023         if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
1024                 return MODE_H_ILLEGAL;
1025
1026         /*
1027          * Output bpp is stored in 6.4 format so right shift by 4 to get the
1028          * integer value since we support only integer values of bpp.
1029          */
1030         if (DISPLAY_VER(dev_priv) >= 10 &&
1031             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
1032                 /*
1033                  * TBD pass the connector BPC,
1034                  * for now U8_MAX so that max BPC on that platform would be picked
1035                  */
1036                 int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
1037
1038                 if (intel_dp_is_edp(intel_dp)) {
1039                         dsc_max_output_bpp =
1040                                 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
1041                         dsc_slice_count =
1042                                 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1043                                                                 true);
1044                 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
1045                         dsc_max_output_bpp =
1046                                 intel_dp_dsc_get_output_bpp(dev_priv,
1047                                                             max_link_clock,
1048                                                             max_lanes,
1049                                                             target_clock,
1050                                                             mode->hdisplay,
1051                                                             bigjoiner,
1052                                                             pipe_bpp) >> 4;
1053                         dsc_slice_count =
1054                                 intel_dp_dsc_get_slice_count(intel_dp,
1055                                                              target_clock,
1056                                                              mode->hdisplay,
1057                                                              bigjoiner);
1058                 }
1059
1060                 dsc = dsc_max_output_bpp && dsc_slice_count;
1061         }
1062
1063         /*
1064          * Big joiner configuration needs DSC for TGL which is not true for
1065          * XE_LPD where uncompressed joiner is supported.
1066          */
1067         if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc)
1068                 return MODE_CLOCK_HIGH;
1069
1070         if (mode_rate > max_rate && !dsc)
1071                 return MODE_CLOCK_HIGH;
1072
1073         status = intel_dp_mode_valid_downstream(connector, mode, target_clock);
1074         if (status != MODE_OK)
1075                 return status;
1076
1077         return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
1078 }
1079
1080 bool intel_dp_source_supports_tps3(struct drm_i915_private *i915)
1081 {
1082         return DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915) || IS_HASWELL(i915);
1083 }
1084
1085 bool intel_dp_source_supports_tps4(struct drm_i915_private *i915)
1086 {
1087         return DISPLAY_VER(i915) >= 10;
1088 }
1089
1090 static void snprintf_int_array(char *str, size_t len,
1091                                const int *array, int nelem)
1092 {
1093         int i;
1094
1095         str[0] = '\0';
1096
1097         for (i = 0; i < nelem; i++) {
1098                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1099                 if (r >= len)
1100                         return;
1101                 str += r;
1102                 len -= r;
1103         }
1104 }
1105
1106 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1107 {
1108         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1109         char str[128]; /* FIXME: too big for stack? */
1110
1111         if (!drm_debug_enabled(DRM_UT_KMS))
1112                 return;
1113
1114         snprintf_int_array(str, sizeof(str),
1115                            intel_dp->source_rates, intel_dp->num_source_rates);
1116         drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
1117
1118         snprintf_int_array(str, sizeof(str),
1119                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1120         drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
1121
1122         snprintf_int_array(str, sizeof(str),
1123                            intel_dp->common_rates, intel_dp->num_common_rates);
1124         drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
1125 }
1126
1127 int
1128 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1129 {
1130         int len;
1131
1132         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1133
1134         return intel_dp_common_rate(intel_dp, len - 1);
1135 }
1136
1137 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1138 {
1139         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1140         int i = intel_dp_rate_index(intel_dp->sink_rates,
1141                                     intel_dp->num_sink_rates, rate);
1142
1143         if (drm_WARN_ON(&i915->drm, i < 0))
1144                 i = 0;
1145
1146         return i;
1147 }
1148
1149 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1150                            u8 *link_bw, u8 *rate_select)
1151 {
1152         /* eDP 1.4 rate select method. */
1153         if (intel_dp->use_rate_select) {
1154                 *link_bw = 0;
1155                 *rate_select =
1156                         intel_dp_rate_select(intel_dp, port_clock);
1157         } else {
1158                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1159                 *rate_select = 0;
1160         }
1161 }
1162
1163 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1164                                          const struct intel_crtc_state *pipe_config)
1165 {
1166         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1167
1168         /* On TGL, FEC is supported on all Pipes */
1169         if (DISPLAY_VER(dev_priv) >= 12)
1170                 return true;
1171
1172         if (DISPLAY_VER(dev_priv) == 11 && pipe_config->cpu_transcoder != TRANSCODER_A)
1173                 return true;
1174
1175         return false;
1176 }
1177
1178 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1179                                   const struct intel_crtc_state *pipe_config)
1180 {
1181         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1182                 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1183 }
1184
1185 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1186                                   const struct intel_crtc_state *crtc_state)
1187 {
1188         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
1189                 return false;
1190
1191         return intel_dsc_source_support(crtc_state) &&
1192                 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1193 }
1194
1195 static bool intel_dp_is_ycbcr420(struct intel_dp *intel_dp,
1196                                  const struct intel_crtc_state *crtc_state)
1197 {
1198         return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
1199                 (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
1200                  intel_dp->dfp.ycbcr_444_to_420);
1201 }
1202
1203 static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
1204                                      const struct intel_crtc_state *crtc_state,
1205                                      int bpc, bool respect_downstream_limits)
1206 {
1207         bool ycbcr420_output = intel_dp_is_ycbcr420(intel_dp, crtc_state);
1208         int clock = crtc_state->hw.adjusted_mode.crtc_clock;
1209
1210         /*
1211          * Current bpc could already be below 8bpc due to
1212          * FDI bandwidth constraints or other limits.
1213          * HDMI minimum is 8bpc however.
1214          */
1215         bpc = max(bpc, 8);
1216
1217         /*
1218          * We will never exceed downstream TMDS clock limits while
1219          * attempting deep color. If the user insists on forcing an
1220          * out of spec mode they will have to be satisfied with 8bpc.
1221          */
1222         if (!respect_downstream_limits)
1223                 bpc = 8;
1224
1225         for (; bpc >= 8; bpc -= 2) {
1226                 if (intel_hdmi_bpc_possible(crtc_state, bpc,
1227                                             intel_dp->has_hdmi_sink, ycbcr420_output) &&
1228                     intel_dp_tmds_clock_valid(intel_dp, clock, bpc, ycbcr420_output,
1229                                               respect_downstream_limits) == MODE_OK)
1230                         return bpc;
1231         }
1232
1233         return -EINVAL;
1234 }
1235
1236 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
1237                             const struct intel_crtc_state *crtc_state,
1238                             bool respect_downstream_limits)
1239 {
1240         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1241         struct intel_connector *intel_connector = intel_dp->attached_connector;
1242         int bpp, bpc;
1243
1244         bpc = crtc_state->pipe_bpp / 3;
1245
1246         if (intel_dp->dfp.max_bpc)
1247                 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
1248
1249         if (intel_dp->dfp.min_tmds_clock) {
1250                 int max_hdmi_bpc;
1251
1252                 max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc,
1253                                                          respect_downstream_limits);
1254                 if (max_hdmi_bpc < 0)
1255                         return 0;
1256
1257                 bpc = min(bpc, max_hdmi_bpc);
1258         }
1259
1260         bpp = bpc * 3;
1261         if (intel_dp_is_edp(intel_dp)) {
1262                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1263                 if (intel_connector->base.display_info.bpc == 0 &&
1264                     intel_connector->panel.vbt.edp.bpp &&
1265                     intel_connector->panel.vbt.edp.bpp < bpp) {
1266                         drm_dbg_kms(&dev_priv->drm,
1267                                     "clamping bpp for eDP panel to BIOS-provided %i\n",
1268                                     intel_connector->panel.vbt.edp.bpp);
1269                         bpp = intel_connector->panel.vbt.edp.bpp;
1270                 }
1271         }
1272
1273         return bpp;
1274 }
1275
1276 /* Adjust link config limits based on compliance test requests. */
1277 void
1278 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1279                                   struct intel_crtc_state *pipe_config,
1280                                   struct link_config_limits *limits)
1281 {
1282         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1283
1284         /* For DP Compliance we override the computed bpp for the pipe */
1285         if (intel_dp->compliance.test_data.bpc != 0) {
1286                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1287
1288                 limits->min_bpp = limits->max_bpp = bpp;
1289                 pipe_config->dither_force_disable = bpp == 6 * 3;
1290
1291                 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
1292         }
1293
1294         /* Use values requested by Compliance Test Request */
1295         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1296                 int index;
1297
1298                 /* Validate the compliance test data since max values
1299                  * might have changed due to link train fallback.
1300                  */
1301                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1302                                                intel_dp->compliance.test_lane_count)) {
1303                         index = intel_dp_rate_index(intel_dp->common_rates,
1304                                                     intel_dp->num_common_rates,
1305                                                     intel_dp->compliance.test_link_rate);
1306                         if (index >= 0)
1307                                 limits->min_rate = limits->max_rate =
1308                                         intel_dp->compliance.test_link_rate;
1309                         limits->min_lane_count = limits->max_lane_count =
1310                                 intel_dp->compliance.test_lane_count;
1311                 }
1312         }
1313 }
1314
1315 /* Optimize link config in order: max bpp, min clock, min lanes */
1316 static int
1317 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1318                                   struct intel_crtc_state *pipe_config,
1319                                   const struct link_config_limits *limits)
1320 {
1321         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1322         int bpp, i, lane_count;
1323         int mode_rate, link_rate, link_avail;
1324
1325         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1326                 int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1327
1328                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1329                                                    output_bpp);
1330
1331                 for (i = 0; i < intel_dp->num_common_rates; i++) {
1332                         link_rate = intel_dp_common_rate(intel_dp, i);
1333                         if (link_rate < limits->min_rate ||
1334                             link_rate > limits->max_rate)
1335                                 continue;
1336
1337                         for (lane_count = limits->min_lane_count;
1338                              lane_count <= limits->max_lane_count;
1339                              lane_count <<= 1) {
1340                                 link_avail = intel_dp_max_data_rate(link_rate,
1341                                                                     lane_count);
1342
1343                                 if (mode_rate <= link_avail) {
1344                                         pipe_config->lane_count = lane_count;
1345                                         pipe_config->pipe_bpp = bpp;
1346                                         pipe_config->port_clock = link_rate;
1347
1348                                         return 0;
1349                                 }
1350                         }
1351                 }
1352         }
1353
1354         return -EINVAL;
1355 }
1356
1357 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
1358 {
1359         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1360         int i, num_bpc;
1361         u8 dsc_bpc[3] = {0};
1362         u8 dsc_max_bpc;
1363
1364         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1365         if (DISPLAY_VER(i915) >= 12)
1366                 dsc_max_bpc = min_t(u8, 12, max_req_bpc);
1367         else
1368                 dsc_max_bpc = min_t(u8, 10, max_req_bpc);
1369
1370         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
1371                                                        dsc_bpc);
1372         for (i = 0; i < num_bpc; i++) {
1373                 if (dsc_max_bpc >= dsc_bpc[i])
1374                         return dsc_bpc[i] * 3;
1375         }
1376
1377         return 0;
1378 }
1379
1380 #define DSC_SUPPORTED_VERSION_MIN               1
1381
1382 static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
1383                                        struct intel_crtc_state *crtc_state)
1384 {
1385         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1386         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1387         struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1388         u8 line_buf_depth;
1389         int ret;
1390
1391         /*
1392          * RC_MODEL_SIZE is currently a constant across all configurations.
1393          *
1394          * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
1395          * DP_DSC_RC_BUF_SIZE for this.
1396          */
1397         vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1398
1399         /*
1400          * Slice Height of 8 works for all currently available panels. So start
1401          * with that if pic_height is an integral multiple of 8. Eventually add
1402          * logic to try multiple slice heights.
1403          */
1404         if (vdsc_cfg->pic_height % 8 == 0)
1405                 vdsc_cfg->slice_height = 8;
1406         else if (vdsc_cfg->pic_height % 4 == 0)
1407                 vdsc_cfg->slice_height = 4;
1408         else
1409                 vdsc_cfg->slice_height = 2;
1410
1411         ret = intel_dsc_compute_params(crtc_state);
1412         if (ret)
1413                 return ret;
1414
1415         vdsc_cfg->dsc_version_major =
1416                 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1417                  DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1418         vdsc_cfg->dsc_version_minor =
1419                 min(DSC_SUPPORTED_VERSION_MIN,
1420                     (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1421                      DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
1422
1423         vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
1424                 DP_DSC_RGB;
1425
1426         line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
1427         if (!line_buf_depth) {
1428                 drm_dbg_kms(&i915->drm,
1429                             "DSC Sink Line Buffer Depth invalid\n");
1430                 return -EINVAL;
1431         }
1432
1433         if (vdsc_cfg->dsc_version_minor == 2)
1434                 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
1435                         DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
1436         else
1437                 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
1438                         DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
1439
1440         vdsc_cfg->block_pred_enable =
1441                 intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
1442                 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
1443
1444         return drm_dsc_compute_rc_parameters(vdsc_cfg);
1445 }
1446
1447 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
1448                                        struct intel_crtc_state *pipe_config,
1449                                        struct drm_connector_state *conn_state,
1450                                        struct link_config_limits *limits)
1451 {
1452         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1453         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1454         const struct drm_display_mode *adjusted_mode =
1455                 &pipe_config->hw.adjusted_mode;
1456         int pipe_bpp;
1457         int ret;
1458
1459         pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
1460                 intel_dp_supports_fec(intel_dp, pipe_config);
1461
1462         if (!intel_dp_supports_dsc(intel_dp, pipe_config))
1463                 return -EINVAL;
1464
1465         pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
1466
1467         /* Min Input BPC for ICL+ is 8 */
1468         if (pipe_bpp < 8 * 3) {
1469                 drm_dbg_kms(&dev_priv->drm,
1470                             "No DSC support for less than 8bpc\n");
1471                 return -EINVAL;
1472         }
1473
1474         /*
1475          * For now enable DSC for max bpp, max link rate, max lane count.
1476          * Optimize this later for the minimum possible link rate/lane count
1477          * with DSC enabled for the requested mode.
1478          */
1479         pipe_config->pipe_bpp = pipe_bpp;
1480         pipe_config->port_clock = limits->max_rate;
1481         pipe_config->lane_count = limits->max_lane_count;
1482
1483         if (intel_dp_is_edp(intel_dp)) {
1484                 pipe_config->dsc.compressed_bpp =
1485                         min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
1486                               pipe_config->pipe_bpp);
1487                 pipe_config->dsc.slice_count =
1488                         drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1489                                                         true);
1490         } else {
1491                 u16 dsc_max_output_bpp;
1492                 u8 dsc_dp_slice_count;
1493
1494                 dsc_max_output_bpp =
1495                         intel_dp_dsc_get_output_bpp(dev_priv,
1496                                                     pipe_config->port_clock,
1497                                                     pipe_config->lane_count,
1498                                                     adjusted_mode->crtc_clock,
1499                                                     adjusted_mode->crtc_hdisplay,
1500                                                     pipe_config->bigjoiner_pipes,
1501                                                     pipe_bpp);
1502                 dsc_dp_slice_count =
1503                         intel_dp_dsc_get_slice_count(intel_dp,
1504                                                      adjusted_mode->crtc_clock,
1505                                                      adjusted_mode->crtc_hdisplay,
1506                                                      pipe_config->bigjoiner_pipes);
1507                 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
1508                         drm_dbg_kms(&dev_priv->drm,
1509                                     "Compressed BPP/Slice Count not supported\n");
1510                         return -EINVAL;
1511                 }
1512                 pipe_config->dsc.compressed_bpp = min_t(u16,
1513                                                                dsc_max_output_bpp >> 4,
1514                                                                pipe_config->pipe_bpp);
1515                 pipe_config->dsc.slice_count = dsc_dp_slice_count;
1516         }
1517
1518         /* As of today we support DSC for only RGB */
1519         if (intel_dp->force_dsc_bpp) {
1520                 if (intel_dp->force_dsc_bpp >= 8 &&
1521                     intel_dp->force_dsc_bpp < pipe_bpp) {
1522                         drm_dbg_kms(&dev_priv->drm,
1523                                     "DSC BPP forced to %d",
1524                                     intel_dp->force_dsc_bpp);
1525                         pipe_config->dsc.compressed_bpp =
1526                                                 intel_dp->force_dsc_bpp;
1527                 } else {
1528                         drm_dbg_kms(&dev_priv->drm,
1529                                     "Invalid DSC BPP %d",
1530                                     intel_dp->force_dsc_bpp);
1531                 }
1532         }
1533
1534         /*
1535          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
1536          * is greater than the maximum Cdclock and if slice count is even
1537          * then we need to use 2 VDSC instances.
1538          */
1539         if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq ||
1540             pipe_config->bigjoiner_pipes) {
1541                 if (pipe_config->dsc.slice_count < 2) {
1542                         drm_dbg_kms(&dev_priv->drm,
1543                                     "Cannot split stream to use 2 VDSC instances\n");
1544                         return -EINVAL;
1545                 }
1546
1547                 pipe_config->dsc.dsc_split = true;
1548         }
1549
1550         ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
1551         if (ret < 0) {
1552                 drm_dbg_kms(&dev_priv->drm,
1553                             "Cannot compute valid DSC parameters for Input Bpp = %d "
1554                             "Compressed BPP = %d\n",
1555                             pipe_config->pipe_bpp,
1556                             pipe_config->dsc.compressed_bpp);
1557                 return ret;
1558         }
1559
1560         pipe_config->dsc.compression_enable = true;
1561         drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
1562                     "Compressed Bpp = %d Slice Count = %d\n",
1563                     pipe_config->pipe_bpp,
1564                     pipe_config->dsc.compressed_bpp,
1565                     pipe_config->dsc.slice_count);
1566
1567         return 0;
1568 }
1569
1570 static int
1571 intel_dp_compute_link_config(struct intel_encoder *encoder,
1572                              struct intel_crtc_state *pipe_config,
1573                              struct drm_connector_state *conn_state,
1574                              bool respect_downstream_limits)
1575 {
1576         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1577         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1578         const struct drm_display_mode *adjusted_mode =
1579                 &pipe_config->hw.adjusted_mode;
1580         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1581         struct link_config_limits limits;
1582         bool joiner_needs_dsc = false;
1583         int ret;
1584
1585         limits.min_rate = intel_dp_common_rate(intel_dp, 0);
1586         limits.max_rate = intel_dp_max_link_rate(intel_dp);
1587
1588         limits.min_lane_count = 1;
1589         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
1590
1591         limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
1592         limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config, respect_downstream_limits);
1593
1594         if (intel_dp->use_max_params) {
1595                 /*
1596                  * Use the maximum clock and number of lanes the eDP panel
1597                  * advertizes being capable of in case the initial fast
1598                  * optimal params failed us. The panels are generally
1599                  * designed to support only a single clock and lane
1600                  * configuration, and typically on older panels these
1601                  * values correspond to the native resolution of the panel.
1602                  */
1603                 limits.min_lane_count = limits.max_lane_count;
1604                 limits.min_rate = limits.max_rate;
1605         }
1606
1607         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
1608
1609         drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
1610                     "max rate %d max bpp %d pixel clock %iKHz\n",
1611                     limits.max_lane_count, limits.max_rate,
1612                     limits.max_bpp, adjusted_mode->crtc_clock);
1613
1614         if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
1615                                     adjusted_mode->crtc_clock))
1616                 pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
1617
1618         /*
1619          * Pipe joiner needs compression up to display 12 due to bandwidth
1620          * limitation. DG2 onwards pipe joiner can be enabled without
1621          * compression.
1622          */
1623         joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes;
1624
1625         /*
1626          * Optimize for slow and wide for everything, because there are some
1627          * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
1628          */
1629         ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
1630
1631         if (ret || joiner_needs_dsc || intel_dp->force_dsc_en) {
1632                 drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
1633                             str_yes_no(ret), str_yes_no(joiner_needs_dsc),
1634                             str_yes_no(intel_dp->force_dsc_en));
1635                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
1636                                                   conn_state, &limits);
1637                 if (ret < 0)
1638                         return ret;
1639         }
1640
1641         if (pipe_config->dsc.compression_enable) {
1642                 drm_dbg_kms(&i915->drm,
1643                             "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
1644                             pipe_config->lane_count, pipe_config->port_clock,
1645                             pipe_config->pipe_bpp,
1646                             pipe_config->dsc.compressed_bpp);
1647
1648                 drm_dbg_kms(&i915->drm,
1649                             "DP link rate required %i available %i\n",
1650                             intel_dp_link_required(adjusted_mode->crtc_clock,
1651                                                    pipe_config->dsc.compressed_bpp),
1652                             intel_dp_max_data_rate(pipe_config->port_clock,
1653                                                    pipe_config->lane_count));
1654         } else {
1655                 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
1656                             pipe_config->lane_count, pipe_config->port_clock,
1657                             pipe_config->pipe_bpp);
1658
1659                 drm_dbg_kms(&i915->drm,
1660                             "DP link rate required %i available %i\n",
1661                             intel_dp_link_required(adjusted_mode->crtc_clock,
1662                                                    pipe_config->pipe_bpp),
1663                             intel_dp_max_data_rate(pipe_config->port_clock,
1664                                                    pipe_config->lane_count));
1665         }
1666         return 0;
1667 }
1668
1669 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
1670                                   const struct drm_connector_state *conn_state)
1671 {
1672         const struct intel_digital_connector_state *intel_conn_state =
1673                 to_intel_digital_connector_state(conn_state);
1674         const struct drm_display_mode *adjusted_mode =
1675                 &crtc_state->hw.adjusted_mode;
1676
1677         /*
1678          * Our YCbCr output is always limited range.
1679          * crtc_state->limited_color_range only applies to RGB,
1680          * and it must never be set for YCbCr or we risk setting
1681          * some conflicting bits in PIPECONF which will mess up
1682          * the colors on the monitor.
1683          */
1684         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
1685                 return false;
1686
1687         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1688                 /*
1689                  * See:
1690                  * CEA-861-E - 5.1 Default Encoding Parameters
1691                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1692                  */
1693                 return crtc_state->pipe_bpp != 18 &&
1694                         drm_default_rgb_quant_range(adjusted_mode) ==
1695                         HDMI_QUANTIZATION_RANGE_LIMITED;
1696         } else {
1697                 return intel_conn_state->broadcast_rgb ==
1698                         INTEL_BROADCAST_RGB_LIMITED;
1699         }
1700 }
1701
1702 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
1703                                     enum port port)
1704 {
1705         if (IS_G4X(dev_priv))
1706                 return false;
1707         if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A)
1708                 return false;
1709
1710         return true;
1711 }
1712
1713 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
1714                                              const struct drm_connector_state *conn_state,
1715                                              struct drm_dp_vsc_sdp *vsc)
1716 {
1717         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1718         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1719
1720         /*
1721          * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1722          * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
1723          * Colorimetry Format indication.
1724          */
1725         vsc->revision = 0x5;
1726         vsc->length = 0x13;
1727
1728         /* DP 1.4a spec, Table 2-120 */
1729         switch (crtc_state->output_format) {
1730         case INTEL_OUTPUT_FORMAT_YCBCR444:
1731                 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
1732                 break;
1733         case INTEL_OUTPUT_FORMAT_YCBCR420:
1734                 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
1735                 break;
1736         case INTEL_OUTPUT_FORMAT_RGB:
1737         default:
1738                 vsc->pixelformat = DP_PIXELFORMAT_RGB;
1739         }
1740
1741         switch (conn_state->colorspace) {
1742         case DRM_MODE_COLORIMETRY_BT709_YCC:
1743                 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1744                 break;
1745         case DRM_MODE_COLORIMETRY_XVYCC_601:
1746                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
1747                 break;
1748         case DRM_MODE_COLORIMETRY_XVYCC_709:
1749                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
1750                 break;
1751         case DRM_MODE_COLORIMETRY_SYCC_601:
1752                 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
1753                 break;
1754         case DRM_MODE_COLORIMETRY_OPYCC_601:
1755                 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
1756                 break;
1757         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
1758                 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
1759                 break;
1760         case DRM_MODE_COLORIMETRY_BT2020_RGB:
1761                 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
1762                 break;
1763         case DRM_MODE_COLORIMETRY_BT2020_YCC:
1764                 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
1765                 break;
1766         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
1767         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
1768                 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
1769                 break;
1770         default:
1771                 /*
1772                  * RGB->YCBCR color conversion uses the BT.709
1773                  * color space.
1774                  */
1775                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1776                         vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1777                 else
1778                         vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
1779                 break;
1780         }
1781
1782         vsc->bpc = crtc_state->pipe_bpp / 3;
1783
1784         /* only RGB pixelformat supports 6 bpc */
1785         drm_WARN_ON(&dev_priv->drm,
1786                     vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
1787
1788         /* all YCbCr are always limited range */
1789         vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
1790         vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
1791 }
1792
1793 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
1794                                      struct intel_crtc_state *crtc_state,
1795                                      const struct drm_connector_state *conn_state)
1796 {
1797         struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
1798
1799         /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
1800         if (crtc_state->has_psr)
1801                 return;
1802
1803         if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
1804                 return;
1805
1806         crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
1807         vsc->sdp_type = DP_SDP_VSC;
1808         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
1809                                          &crtc_state->infoframes.vsc);
1810 }
1811
1812 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
1813                                   const struct intel_crtc_state *crtc_state,
1814                                   const struct drm_connector_state *conn_state,
1815                                   struct drm_dp_vsc_sdp *vsc)
1816 {
1817         vsc->sdp_type = DP_SDP_VSC;
1818
1819         if (crtc_state->has_psr2) {
1820                 if (intel_dp->psr.colorimetry_support &&
1821                     intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
1822                         /* [PSR2, +Colorimetry] */
1823                         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
1824                                                          vsc);
1825                 } else {
1826                         /*
1827                          * [PSR2, -Colorimetry]
1828                          * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
1829                          * 3D stereo + PSR/PSR2 + Y-coordinate.
1830                          */
1831                         vsc->revision = 0x4;
1832                         vsc->length = 0xe;
1833                 }
1834         } else {
1835                 /*
1836                  * [PSR1]
1837                  * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1838                  * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
1839                  * higher).
1840                  */
1841                 vsc->revision = 0x2;
1842                 vsc->length = 0x8;
1843         }
1844 }
1845
1846 static void
1847 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
1848                                             struct intel_crtc_state *crtc_state,
1849                                             const struct drm_connector_state *conn_state)
1850 {
1851         int ret;
1852         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1853         struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
1854
1855         if (!conn_state->hdr_output_metadata)
1856                 return;
1857
1858         ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
1859
1860         if (ret) {
1861                 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
1862                 return;
1863         }
1864
1865         crtc_state->infoframes.enable |=
1866                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
1867 }
1868
1869 static bool cpu_transcoder_has_drrs(struct drm_i915_private *i915,
1870                                     enum transcoder cpu_transcoder)
1871 {
1872         /* M1/N1 is double buffered */
1873         if (DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915))
1874                 return true;
1875
1876         return intel_cpu_transcoder_has_m2_n2(i915, cpu_transcoder);
1877 }
1878
1879 static bool can_enable_drrs(struct intel_connector *connector,
1880                             const struct intel_crtc_state *pipe_config,
1881                             const struct drm_display_mode *downclock_mode)
1882 {
1883         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1884
1885         if (pipe_config->vrr.enable)
1886                 return false;
1887
1888         /*
1889          * DRRS and PSR can't be enable together, so giving preference to PSR
1890          * as it allows more power-savings by complete shutting down display,
1891          * so to guarantee this, intel_drrs_compute_config() must be called
1892          * after intel_psr_compute_config().
1893          */
1894         if (pipe_config->has_psr)
1895                 return false;
1896
1897         /* FIXME missing FDI M2/N2 etc. */
1898         if (pipe_config->has_pch_encoder)
1899                 return false;
1900
1901         if (!cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder))
1902                 return false;
1903
1904         return downclock_mode &&
1905                 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
1906 }
1907
1908 static void
1909 intel_dp_drrs_compute_config(struct intel_connector *connector,
1910                              struct intel_crtc_state *pipe_config,
1911                              int output_bpp, bool constant_n)
1912 {
1913         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1914         const struct drm_display_mode *downclock_mode =
1915                 intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);
1916         int pixel_clock;
1917
1918         if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
1919                 if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
1920                         intel_zero_m_n(&pipe_config->dp_m2_n2);
1921                 return;
1922         }
1923
1924         if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915))
1925                 pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay;
1926
1927         pipe_config->has_drrs = true;
1928
1929         pixel_clock = downclock_mode->clock;
1930         if (pipe_config->splitter.enable)
1931                 pixel_clock /= pipe_config->splitter.link_count;
1932
1933         intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
1934                                pipe_config->port_clock, &pipe_config->dp_m2_n2,
1935                                constant_n, pipe_config->fec_enable);
1936
1937         /* FIXME: abstract this better */
1938         if (pipe_config->splitter.enable)
1939                 pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
1940 }
1941
1942 static bool intel_dp_has_audio(struct intel_encoder *encoder,
1943                                const struct intel_crtc_state *crtc_state,
1944                                const struct drm_connector_state *conn_state)
1945 {
1946         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1947         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1948         const struct intel_digital_connector_state *intel_conn_state =
1949                 to_intel_digital_connector_state(conn_state);
1950
1951         if (!intel_dp_port_has_audio(i915, encoder->port))
1952                 return false;
1953
1954         if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1955                 return intel_dp->has_audio;
1956         else
1957                 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
1958 }
1959
1960 static int
1961 intel_dp_compute_output_format(struct intel_encoder *encoder,
1962                                struct intel_crtc_state *crtc_state,
1963                                struct drm_connector_state *conn_state,
1964                                bool respect_downstream_limits)
1965 {
1966         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1967         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1968         struct intel_connector *connector = intel_dp->attached_connector;
1969         const struct drm_display_info *info = &connector->base.display_info;
1970         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1971         bool ycbcr_420_only;
1972         int ret;
1973
1974         ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
1975
1976         crtc_state->output_format = intel_dp_output_format(connector, ycbcr_420_only);
1977
1978         if (ycbcr_420_only && !intel_dp_is_ycbcr420(intel_dp, crtc_state)) {
1979                 drm_dbg_kms(&i915->drm,
1980                             "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
1981                 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
1982         }
1983
1984         ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
1985                                            respect_downstream_limits);
1986         if (ret) {
1987                 if (intel_dp_is_ycbcr420(intel_dp, crtc_state) ||
1988                     !connector->base.ycbcr_420_allowed ||
1989                     !drm_mode_is_420_also(info, adjusted_mode))
1990                         return ret;
1991
1992                 crtc_state->output_format = intel_dp_output_format(connector, true);
1993                 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
1994                                                    respect_downstream_limits);
1995         }
1996
1997         return ret;
1998 }
1999
2000 int
2001 intel_dp_compute_config(struct intel_encoder *encoder,
2002                         struct intel_crtc_state *pipe_config,
2003                         struct drm_connector_state *conn_state)
2004 {
2005         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2006         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2007         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2008         const struct drm_display_mode *fixed_mode;
2009         struct intel_connector *connector = intel_dp->attached_connector;
2010         bool constant_n = drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CONSTANT_N);
2011         int ret = 0, output_bpp;
2012
2013         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
2014                 pipe_config->has_pch_encoder = true;
2015
2016         pipe_config->has_audio = intel_dp_has_audio(encoder, pipe_config, conn_state);
2017
2018         fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);
2019         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
2020                 ret = intel_panel_compute_config(connector, adjusted_mode);
2021                 if (ret)
2022                         return ret;
2023         }
2024
2025         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2026                 return -EINVAL;
2027
2028         if (HAS_GMCH(dev_priv) &&
2029             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2030                 return -EINVAL;
2031
2032         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2033                 return -EINVAL;
2034
2035         if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2036                 return -EINVAL;
2037
2038         /*
2039          * Try to respect downstream TMDS clock limits first, if
2040          * that fails assume the user might know something we don't.
2041          */
2042         ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true);
2043         if (ret)
2044                 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false);
2045         if (ret)
2046                 return ret;
2047
2048         if ((intel_dp_is_edp(intel_dp) && fixed_mode) ||
2049             pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2050                 ret = intel_panel_fitting(pipe_config, conn_state);
2051                 if (ret)
2052                         return ret;
2053         }
2054
2055         pipe_config->limited_color_range =
2056                 intel_dp_limited_color_range(pipe_config, conn_state);
2057
2058         if (pipe_config->dsc.compression_enable)
2059                 output_bpp = pipe_config->dsc.compressed_bpp;
2060         else
2061                 output_bpp = intel_dp_output_bpp(pipe_config->output_format,
2062                                                  pipe_config->pipe_bpp);
2063
2064         if (intel_dp->mso_link_count) {
2065                 int n = intel_dp->mso_link_count;
2066                 int overlap = intel_dp->mso_pixel_overlap;
2067
2068                 pipe_config->splitter.enable = true;
2069                 pipe_config->splitter.link_count = n;
2070                 pipe_config->splitter.pixel_overlap = overlap;
2071
2072                 drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n",
2073                             n, overlap);
2074
2075                 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;
2076                 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;
2077                 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;
2078                 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;
2079                 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;
2080                 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;
2081                 adjusted_mode->crtc_clock /= n;
2082         }
2083
2084         intel_link_compute_m_n(output_bpp,
2085                                pipe_config->lane_count,
2086                                adjusted_mode->crtc_clock,
2087                                pipe_config->port_clock,
2088                                &pipe_config->dp_m_n,
2089                                constant_n, pipe_config->fec_enable);
2090
2091         /* FIXME: abstract this better */
2092         if (pipe_config->splitter.enable)
2093                 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
2094
2095         if (!HAS_DDI(dev_priv))
2096                 g4x_dp_set_clock(encoder, pipe_config);
2097
2098         intel_vrr_compute_config(pipe_config, conn_state);
2099         intel_psr_compute_config(intel_dp, pipe_config, conn_state);
2100         intel_dp_drrs_compute_config(connector, pipe_config,
2101                                      output_bpp, constant_n);
2102         intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
2103         intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
2104
2105         return 0;
2106 }
2107
2108 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2109                               int link_rate, int lane_count)
2110 {
2111         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2112         intel_dp->link_trained = false;
2113         intel_dp->link_rate = link_rate;
2114         intel_dp->lane_count = lane_count;
2115 }
2116
2117 static void intel_dp_reset_max_link_params(struct intel_dp *intel_dp)
2118 {
2119         intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
2120         intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
2121 }
2122
2123 /* Enable backlight PWM and backlight PP control. */
2124 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2125                             const struct drm_connector_state *conn_state)
2126 {
2127         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
2128         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2129
2130         if (!intel_dp_is_edp(intel_dp))
2131                 return;
2132
2133         drm_dbg_kms(&i915->drm, "\n");
2134
2135         intel_backlight_enable(crtc_state, conn_state);
2136         intel_pps_backlight_on(intel_dp);
2137 }
2138
2139 /* Disable backlight PP control and backlight PWM. */
2140 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2141 {
2142         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
2143         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2144
2145         if (!intel_dp_is_edp(intel_dp))
2146                 return;
2147
2148         drm_dbg_kms(&i915->drm, "\n");
2149
2150         intel_pps_backlight_off(intel_dp);
2151         intel_backlight_disable(old_conn_state);
2152 }
2153
2154 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2155 {
2156         /*
2157          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2158          * be capable of signalling downstream hpd with a long pulse.
2159          * Whether or not that means D3 is safe to use is not clear,
2160          * but let's assume so until proven otherwise.
2161          *
2162          * FIXME should really check all downstream ports...
2163          */
2164         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2165                 drm_dp_is_branch(intel_dp->dpcd) &&
2166                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2167 }
2168
2169 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
2170                                            const struct intel_crtc_state *crtc_state,
2171                                            bool enable)
2172 {
2173         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2174         int ret;
2175
2176         if (!crtc_state->dsc.compression_enable)
2177                 return;
2178
2179         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
2180                                  enable ? DP_DECOMPRESSION_EN : 0);
2181         if (ret < 0)
2182                 drm_dbg_kms(&i915->drm,
2183                             "Failed to %s sink decompression state\n",
2184                             str_enable_disable(enable));
2185 }
2186
2187 static void
2188 intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)
2189 {
2190         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2191         u8 oui[] = { 0x00, 0xaa, 0x01 };
2192         u8 buf[3] = { 0 };
2193
2194         /*
2195          * During driver init, we want to be careful and avoid changing the source OUI if it's
2196          * already set to what we want, so as to avoid clearing any state by accident
2197          */
2198         if (careful) {
2199                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
2200                         drm_err(&i915->drm, "Failed to read source OUI\n");
2201
2202                 if (memcmp(oui, buf, sizeof(oui)) == 0)
2203                         return;
2204         }
2205
2206         if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0)
2207                 drm_err(&i915->drm, "Failed to write source OUI\n");
2208
2209         intel_dp->last_oui_write = jiffies;
2210 }
2211
2212 void intel_dp_wait_source_oui(struct intel_dp *intel_dp)
2213 {
2214         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2215
2216         drm_dbg_kms(&i915->drm, "Performing OUI wait\n");
2217         wait_remaining_ms_from_jiffies(intel_dp->last_oui_write, 30);
2218 }
2219
2220 /* If the device supports it, try to set the power state appropriately */
2221 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
2222 {
2223         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2224         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2225         int ret, i;
2226
2227         /* Should have a valid DPCD by this point */
2228         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2229                 return;
2230
2231         if (mode != DP_SET_POWER_D0) {
2232                 if (downstream_hpd_needs_d0(intel_dp))
2233                         return;
2234
2235                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
2236         } else {
2237                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2238
2239                 lspcon_resume(dp_to_dig_port(intel_dp));
2240
2241                 /* Write the source OUI as early as possible */
2242                 if (intel_dp_is_edp(intel_dp))
2243                         intel_edp_init_source_oui(intel_dp, false);
2244
2245                 /*
2246                  * When turning on, we need to retry for 1ms to give the sink
2247                  * time to wake up.
2248                  */
2249                 for (i = 0; i < 3; i++) {
2250                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
2251                         if (ret == 1)
2252                                 break;
2253                         msleep(1);
2254                 }
2255
2256                 if (ret == 1 && lspcon->active)
2257                         lspcon_wait_pcon_mode(lspcon);
2258         }
2259
2260         if (ret != 1)
2261                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
2262                             encoder->base.base.id, encoder->base.name,
2263                             mode == DP_SET_POWER_D0 ? "D0" : "D3");
2264 }
2265
2266 static bool
2267 intel_dp_get_dpcd(struct intel_dp *intel_dp);
2268
2269 /**
2270  * intel_dp_sync_state - sync the encoder state during init/resume
2271  * @encoder: intel encoder to sync
2272  * @crtc_state: state for the CRTC connected to the encoder
2273  *
2274  * Sync any state stored in the encoder wrt. HW state during driver init
2275  * and system resume.
2276  */
2277 void intel_dp_sync_state(struct intel_encoder *encoder,
2278                          const struct intel_crtc_state *crtc_state)
2279 {
2280         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2281
2282         if (!crtc_state)
2283                 return;
2284
2285         /*
2286          * Don't clobber DPCD if it's been already read out during output
2287          * setup (eDP) or detect.
2288          */
2289         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2290                 intel_dp_get_dpcd(intel_dp);
2291
2292         intel_dp_reset_max_link_params(intel_dp);
2293 }
2294
2295 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
2296                                     struct intel_crtc_state *crtc_state)
2297 {
2298         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2299         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2300
2301         /*
2302          * If BIOS has set an unsupported or non-standard link rate for some
2303          * reason force an encoder recompute and full modeset.
2304          */
2305         if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
2306                                 crtc_state->port_clock) < 0) {
2307                 drm_dbg_kms(&i915->drm, "Forcing full modeset due to unsupported link rate\n");
2308                 crtc_state->uapi.connectors_changed = true;
2309                 return false;
2310         }
2311
2312         /*
2313          * FIXME hack to force full modeset when DSC is being used.
2314          *
2315          * As long as we do not have full state readout and config comparison
2316          * of crtc_state->dsc, we have no way to ensure reliable fastset.
2317          * Remove once we have readout for DSC.
2318          */
2319         if (crtc_state->dsc.compression_enable) {
2320                 drm_dbg_kms(&i915->drm, "Forcing full modeset due to DSC being enabled\n");
2321                 crtc_state->uapi.mode_changed = true;
2322                 return false;
2323         }
2324
2325         if (CAN_PSR(intel_dp)) {
2326                 drm_dbg_kms(&i915->drm, "Forcing full modeset to compute PSR state\n");
2327                 crtc_state->uapi.mode_changed = true;
2328                 return false;
2329         }
2330
2331         return true;
2332 }
2333
2334 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
2335 {
2336         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2337
2338         /* Clear the cached register set to avoid using stale values */
2339
2340         memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
2341
2342         if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
2343                              intel_dp->pcon_dsc_dpcd,
2344                              sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
2345                 drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
2346                         DP_PCON_DSC_ENCODER);
2347
2348         drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
2349                     (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
2350 }
2351
2352 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
2353 {
2354         int bw_gbps[] = {9, 18, 24, 32, 40, 48};
2355         int i;
2356
2357         for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
2358                 if (frl_bw_mask & (1 << i))
2359                         return bw_gbps[i];
2360         }
2361         return 0;
2362 }
2363
2364 static int intel_dp_pcon_set_frl_mask(int max_frl)
2365 {
2366         switch (max_frl) {
2367         case 48:
2368                 return DP_PCON_FRL_BW_MASK_48GBPS;
2369         case 40:
2370                 return DP_PCON_FRL_BW_MASK_40GBPS;
2371         case 32:
2372                 return DP_PCON_FRL_BW_MASK_32GBPS;
2373         case 24:
2374                 return DP_PCON_FRL_BW_MASK_24GBPS;
2375         case 18:
2376                 return DP_PCON_FRL_BW_MASK_18GBPS;
2377         case 9:
2378                 return DP_PCON_FRL_BW_MASK_9GBPS;
2379         }
2380
2381         return 0;
2382 }
2383
2384 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
2385 {
2386         struct intel_connector *intel_connector = intel_dp->attached_connector;
2387         struct drm_connector *connector = &intel_connector->base;
2388         int max_frl_rate;
2389         int max_lanes, rate_per_lane;
2390         int max_dsc_lanes, dsc_rate_per_lane;
2391
2392         max_lanes = connector->display_info.hdmi.max_lanes;
2393         rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
2394         max_frl_rate = max_lanes * rate_per_lane;
2395
2396         if (connector->display_info.hdmi.dsc_cap.v_1p2) {
2397                 max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
2398                 dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
2399                 if (max_dsc_lanes && dsc_rate_per_lane)
2400                         max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
2401         }
2402
2403         return max_frl_rate;
2404 }
2405
2406 static bool
2407 intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp,
2408                              u8 max_frl_bw_mask, u8 *frl_trained_mask)
2409 {
2410         if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) &&
2411             drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL &&
2412             *frl_trained_mask >= max_frl_bw_mask)
2413                 return true;
2414
2415         return false;
2416 }
2417
2418 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
2419 {
2420 #define TIMEOUT_FRL_READY_MS 500
2421 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
2422
2423         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2424         int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
2425         u8 max_frl_bw_mask = 0, frl_trained_mask;
2426         bool is_active;
2427
2428         max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
2429         drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
2430
2431         max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
2432         drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
2433
2434         max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
2435
2436         if (max_frl_bw <= 0)
2437                 return -EINVAL;
2438
2439         max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
2440         drm_dbg(&i915->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);
2441
2442         if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask))
2443                 goto frl_trained;
2444
2445         ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
2446         if (ret < 0)
2447                 return ret;
2448         /* Wait for PCON to be FRL Ready */
2449         wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
2450
2451         if (!is_active)
2452                 return -ETIMEDOUT;
2453
2454         ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
2455                                           DP_PCON_ENABLE_SEQUENTIAL_LINK);
2456         if (ret < 0)
2457                 return ret;
2458         ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
2459                                           DP_PCON_FRL_LINK_TRAIN_NORMAL);
2460         if (ret < 0)
2461                 return ret;
2462         ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
2463         if (ret < 0)
2464                 return ret;
2465         /*
2466          * Wait for FRL to be completed
2467          * Check if the HDMI Link is up and active.
2468          */
2469         wait_for(is_active =
2470                  intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask),
2471                  TIMEOUT_HDMI_LINK_ACTIVE_MS);
2472
2473         if (!is_active)
2474                 return -ETIMEDOUT;
2475
2476 frl_trained:
2477         drm_dbg(&i915->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);
2478         intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
2479         intel_dp->frl.is_trained = true;
2480         drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
2481
2482         return 0;
2483 }
2484
2485 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
2486 {
2487         if (drm_dp_is_branch(intel_dp->dpcd) &&
2488             intel_dp->has_hdmi_sink &&
2489             intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
2490                 return true;
2491
2492         return false;
2493 }
2494
2495 static
2496 int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp)
2497 {
2498         int ret;
2499         u8 buf = 0;
2500
2501         /* Set PCON source control mode */
2502         buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE;
2503
2504         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2505         if (ret < 0)
2506                 return ret;
2507
2508         /* Set HDMI LINK ENABLE */
2509         buf |= DP_PCON_ENABLE_HDMI_LINK;
2510         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2511         if (ret < 0)
2512                 return ret;
2513
2514         return 0;
2515 }
2516
2517 void intel_dp_check_frl_training(struct intel_dp *intel_dp)
2518 {
2519         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2520
2521         /*
2522          * Always go for FRL training if:
2523          * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)
2524          * -sink is HDMI2.1
2525          */
2526         if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||
2527             !intel_dp_is_hdmi_2_1_sink(intel_dp) ||
2528             intel_dp->frl.is_trained)
2529                 return;
2530
2531         if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
2532                 int ret, mode;
2533
2534                 drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");
2535                 ret = intel_dp_pcon_set_tmds_mode(intel_dp);
2536                 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
2537
2538                 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
2539                         drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
2540         } else {
2541                 drm_dbg(&dev_priv->drm, "FRL training Completed\n");
2542         }
2543 }
2544
2545 static int
2546 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
2547 {
2548         int vactive = crtc_state->hw.adjusted_mode.vdisplay;
2549
2550         return intel_hdmi_dsc_get_slice_height(vactive);
2551 }
2552
2553 static int
2554 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
2555                              const struct intel_crtc_state *crtc_state)
2556 {
2557         struct intel_connector *intel_connector = intel_dp->attached_connector;
2558         struct drm_connector *connector = &intel_connector->base;
2559         int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;
2560         int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;
2561         int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
2562         int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
2563
2564         return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
2565                                              pcon_max_slice_width,
2566                                              hdmi_max_slices, hdmi_throughput);
2567 }
2568
2569 static int
2570 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
2571                           const struct intel_crtc_state *crtc_state,
2572                           int num_slices, int slice_width)
2573 {
2574         struct intel_connector *intel_connector = intel_dp->attached_connector;
2575         struct drm_connector *connector = &intel_connector->base;
2576         int output_format = crtc_state->output_format;
2577         bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;
2578         int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
2579         int hdmi_max_chunk_bytes =
2580                 connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;
2581
2582         return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
2583                                       num_slices, output_format, hdmi_all_bpp,
2584                                       hdmi_max_chunk_bytes);
2585 }
2586
2587 void
2588 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
2589                             const struct intel_crtc_state *crtc_state)
2590 {
2591         u8 pps_param[6];
2592         int slice_height;
2593         int slice_width;
2594         int num_slices;
2595         int bits_per_pixel;
2596         int ret;
2597         struct intel_connector *intel_connector = intel_dp->attached_connector;
2598         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2599         struct drm_connector *connector;
2600         bool hdmi_is_dsc_1_2;
2601
2602         if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
2603                 return;
2604
2605         if (!intel_connector)
2606                 return;
2607         connector = &intel_connector->base;
2608         hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
2609
2610         if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
2611             !hdmi_is_dsc_1_2)
2612                 return;
2613
2614         slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
2615         if (!slice_height)
2616                 return;
2617
2618         num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
2619         if (!num_slices)
2620                 return;
2621
2622         slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
2623                                    num_slices);
2624
2625         bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
2626                                                    num_slices, slice_width);
2627         if (!bits_per_pixel)
2628                 return;
2629
2630         pps_param[0] = slice_height & 0xFF;
2631         pps_param[1] = slice_height >> 8;
2632         pps_param[2] = slice_width & 0xFF;
2633         pps_param[3] = slice_width >> 8;
2634         pps_param[4] = bits_per_pixel & 0xFF;
2635         pps_param[5] = (bits_per_pixel >> 8) & 0x3;
2636
2637         ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
2638         if (ret < 0)
2639                 drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
2640 }
2641
2642 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
2643                                            const struct intel_crtc_state *crtc_state)
2644 {
2645         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2646         u8 tmp;
2647
2648         if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
2649                 return;
2650
2651         if (!drm_dp_is_branch(intel_dp->dpcd))
2652                 return;
2653
2654         tmp = intel_dp->has_hdmi_sink ?
2655                 DP_HDMI_DVI_OUTPUT_CONFIG : 0;
2656
2657         if (drm_dp_dpcd_writeb(&intel_dp->aux,
2658                                DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
2659                 drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
2660                             str_enable_disable(intel_dp->has_hdmi_sink));
2661
2662         tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
2663                 intel_dp->dfp.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
2664
2665         if (drm_dp_dpcd_writeb(&intel_dp->aux,
2666                                DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
2667                 drm_dbg_kms(&i915->drm,
2668                             "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
2669                             str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
2670
2671         tmp = intel_dp->dfp.rgb_to_ycbcr ?
2672                 DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
2673
2674         if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
2675                 drm_dbg_kms(&i915->drm,
2676                            "Failed to %s protocol converter RGB->YCbCr conversion mode\n",
2677                            str_enable_disable(tmp));
2678 }
2679
2680
2681 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
2682 {
2683         u8 dprx = 0;
2684
2685         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
2686                               &dprx) != 1)
2687                 return false;
2688         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
2689 }
2690
2691 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
2692 {
2693         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2694
2695         /*
2696          * Clear the cached register set to avoid using stale values
2697          * for the sinks that do not support DSC.
2698          */
2699         memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
2700
2701         /* Clear fec_capable to avoid using stale values */
2702         intel_dp->fec_capable = 0;
2703
2704         /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
2705         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
2706             intel_dp->edp_dpcd[0] >= DP_EDP_14) {
2707                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
2708                                      intel_dp->dsc_dpcd,
2709                                      sizeof(intel_dp->dsc_dpcd)) < 0)
2710                         drm_err(&i915->drm,
2711                                 "Failed to read DPCD register 0x%x\n",
2712                                 DP_DSC_SUPPORT);
2713
2714                 drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n",
2715                             (int)sizeof(intel_dp->dsc_dpcd),
2716                             intel_dp->dsc_dpcd);
2717
2718                 /* FEC is supported only on DP 1.4 */
2719                 if (!intel_dp_is_edp(intel_dp) &&
2720                     drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
2721                                       &intel_dp->fec_capable) < 0)
2722                         drm_err(&i915->drm,
2723                                 "Failed to read FEC DPCD register\n");
2724
2725                 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
2726                             intel_dp->fec_capable);
2727         }
2728 }
2729
2730 static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
2731                                      struct drm_display_mode *mode)
2732 {
2733         struct intel_dp *intel_dp = intel_attached_dp(connector);
2734         struct drm_i915_private *i915 = to_i915(connector->base.dev);
2735         int n = intel_dp->mso_link_count;
2736         int overlap = intel_dp->mso_pixel_overlap;
2737
2738         if (!mode || !n)
2739                 return;
2740
2741         mode->hdisplay = (mode->hdisplay - overlap) * n;
2742         mode->hsync_start = (mode->hsync_start - overlap) * n;
2743         mode->hsync_end = (mode->hsync_end - overlap) * n;
2744         mode->htotal = (mode->htotal - overlap) * n;
2745         mode->clock *= n;
2746
2747         drm_mode_set_name(mode);
2748
2749         drm_dbg_kms(&i915->drm,
2750                     "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n",
2751                     connector->base.base.id, connector->base.name,
2752                     DRM_MODE_ARG(mode));
2753 }
2754
2755 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp)
2756 {
2757         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2758         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2759         struct intel_connector *connector = intel_dp->attached_connector;
2760
2761         if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) {
2762                 /*
2763                  * This is a big fat ugly hack.
2764                  *
2765                  * Some machines in UEFI boot mode provide us a VBT that has 18
2766                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2767                  * unknown we fail to light up. Yet the same BIOS boots up with
2768                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2769                  * max, not what it tells us to use.
2770                  *
2771                  * Note: This will still be broken if the eDP panel is not lit
2772                  * up by the BIOS, and thus we can't get the mode at module
2773                  * load.
2774                  */
2775                 drm_dbg_kms(&dev_priv->drm,
2776                             "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2777                             pipe_bpp, connector->panel.vbt.edp.bpp);
2778                 connector->panel.vbt.edp.bpp = pipe_bpp;
2779         }
2780 }
2781
2782 static void intel_edp_mso_init(struct intel_dp *intel_dp)
2783 {
2784         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2785         struct intel_connector *connector = intel_dp->attached_connector;
2786         struct drm_display_info *info = &connector->base.display_info;
2787         u8 mso;
2788
2789         if (intel_dp->edp_dpcd[0] < DP_EDP_14)
2790                 return;
2791
2792         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {
2793                 drm_err(&i915->drm, "Failed to read MSO cap\n");
2794                 return;
2795         }
2796
2797         /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
2798         mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
2799         if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
2800                 drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso);
2801                 mso = 0;
2802         }
2803
2804         if (mso) {
2805                 drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n",
2806                             mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
2807                             info->mso_pixel_overlap);
2808                 if (!HAS_MSO(i915)) {
2809                         drm_err(&i915->drm, "No source MSO support, disabling\n");
2810                         mso = 0;
2811                 }
2812         }
2813
2814         intel_dp->mso_link_count = mso;
2815         intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;
2816 }
2817
2818 static bool
2819 intel_edp_init_dpcd(struct intel_dp *intel_dp)
2820 {
2821         struct drm_i915_private *dev_priv =
2822                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
2823
2824         /* this function is meant to be called only once */
2825         drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
2826
2827         if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
2828                 return false;
2829
2830         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
2831                          drm_dp_is_branch(intel_dp->dpcd));
2832
2833         /*
2834          * Read the eDP display control registers.
2835          *
2836          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
2837          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
2838          * set, but require eDP 1.4+ detection (e.g. for supported link rates
2839          * method). The display control registers should read zero if they're
2840          * not supported anyway.
2841          */
2842         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
2843                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
2844                              sizeof(intel_dp->edp_dpcd)) {
2845                 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
2846                             (int)sizeof(intel_dp->edp_dpcd),
2847                             intel_dp->edp_dpcd);
2848
2849                 intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;
2850         }
2851
2852         /*
2853          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
2854          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
2855          */
2856         intel_psr_init_dpcd(intel_dp);
2857
2858         /* Clear the default sink rates */
2859         intel_dp->num_sink_rates = 0;
2860
2861         /* Read the eDP 1.4+ supported link rates. */
2862         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
2863                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
2864                 int i;
2865
2866                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
2867                                 sink_rates, sizeof(sink_rates));
2868
2869                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
2870                         int val = le16_to_cpu(sink_rates[i]);
2871
2872                         if (val == 0)
2873                                 break;
2874
2875                         /* Value read multiplied by 200kHz gives the per-lane
2876                          * link rate in kHz. The source rates are, however,
2877                          * stored in terms of LS_Clk kHz. The full conversion
2878                          * back to symbols is
2879                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
2880                          */
2881                         intel_dp->sink_rates[i] = (val * 200) / 10;
2882                 }
2883                 intel_dp->num_sink_rates = i;
2884         }
2885
2886         /*
2887          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
2888          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
2889          */
2890         if (intel_dp->num_sink_rates)
2891                 intel_dp->use_rate_select = true;
2892         else
2893                 intel_dp_set_sink_rates(intel_dp);
2894         intel_dp_set_max_sink_lane_count(intel_dp);
2895
2896         /* Read the eDP DSC DPCD registers */
2897         if (DISPLAY_VER(dev_priv) >= 10)
2898                 intel_dp_get_dsc_sink_cap(intel_dp);
2899
2900         /*
2901          * If needed, program our source OUI so we can make various Intel-specific AUX services
2902          * available (such as HDR backlight controls)
2903          */
2904         intel_edp_init_source_oui(intel_dp, true);
2905
2906         return true;
2907 }
2908
2909 static bool
2910 intel_dp_has_sink_count(struct intel_dp *intel_dp)
2911 {
2912         if (!intel_dp->attached_connector)
2913                 return false;
2914
2915         return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
2916                                           intel_dp->dpcd,
2917                                           &intel_dp->desc);
2918 }
2919
2920 static bool
2921 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2922 {
2923         int ret;
2924
2925         if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)
2926                 return false;
2927
2928         /*
2929          * Don't clobber cached eDP rates. Also skip re-reading
2930          * the OUI/ID since we know it won't change.
2931          */
2932         if (!intel_dp_is_edp(intel_dp)) {
2933                 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
2934                                  drm_dp_is_branch(intel_dp->dpcd));
2935
2936                 intel_dp_set_sink_rates(intel_dp);
2937                 intel_dp_set_max_sink_lane_count(intel_dp);
2938                 intel_dp_set_common_rates(intel_dp);
2939         }
2940
2941         if (intel_dp_has_sink_count(intel_dp)) {
2942                 ret = drm_dp_read_sink_count(&intel_dp->aux);
2943                 if (ret < 0)
2944                         return false;
2945
2946                 /*
2947                  * Sink count can change between short pulse hpd hence
2948                  * a member variable in intel_dp will track any changes
2949                  * between short pulse interrupts.
2950                  */
2951                 intel_dp->sink_count = ret;
2952
2953                 /*
2954                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
2955                  * a dongle is present but no display. Unless we require to know
2956                  * if a dongle is present or not, we don't need to update
2957                  * downstream port information. So, an early return here saves
2958                  * time from performing other operations which are not required.
2959                  */
2960                 if (!intel_dp->sink_count)
2961                         return false;
2962         }
2963
2964         return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
2965                                            intel_dp->downstream_ports) == 0;
2966 }
2967
2968 static bool
2969 intel_dp_can_mst(struct intel_dp *intel_dp)
2970 {
2971         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2972
2973         return i915->params.enable_dp_mst &&
2974                 intel_dp_mst_source_support(intel_dp) &&
2975                 drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
2976 }
2977
2978 static void
2979 intel_dp_configure_mst(struct intel_dp *intel_dp)
2980 {
2981         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2982         struct intel_encoder *encoder =
2983                 &dp_to_dig_port(intel_dp)->base;
2984         bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
2985
2986         drm_dbg_kms(&i915->drm,
2987                     "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
2988                     encoder->base.base.id, encoder->base.name,
2989                     str_yes_no(intel_dp_mst_source_support(intel_dp)),
2990                     str_yes_no(sink_can_mst),
2991                     str_yes_no(i915->params.enable_dp_mst));
2992
2993         if (!intel_dp_mst_source_support(intel_dp))
2994                 return;
2995
2996         intel_dp->is_mst = sink_can_mst &&
2997                 i915->params.enable_dp_mst;
2998
2999         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3000                                         intel_dp->is_mst);
3001 }
3002
3003 static bool
3004 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi)
3005 {
3006         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4;
3007 }
3008
3009 static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4])
3010 {
3011         int retry;
3012
3013         for (retry = 0; retry < 3; retry++) {
3014                 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1,
3015                                       &esi[1], 3) == 3)
3016                         return true;
3017         }
3018
3019         return false;
3020 }
3021
3022 bool
3023 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
3024                        const struct drm_connector_state *conn_state)
3025 {
3026         /*
3027          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
3028          * of Color Encoding Format and Content Color Gamut], in order to
3029          * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
3030          */
3031         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
3032                 return true;
3033
3034         switch (conn_state->colorspace) {
3035         case DRM_MODE_COLORIMETRY_SYCC_601:
3036         case DRM_MODE_COLORIMETRY_OPYCC_601:
3037         case DRM_MODE_COLORIMETRY_BT2020_YCC:
3038         case DRM_MODE_COLORIMETRY_BT2020_RGB:
3039         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
3040                 return true;
3041         default:
3042                 break;
3043         }
3044
3045         return false;
3046 }
3047
3048 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
3049                                      struct dp_sdp *sdp, size_t size)
3050 {
3051         size_t length = sizeof(struct dp_sdp);
3052
3053         if (size < length)
3054                 return -ENOSPC;
3055
3056         memset(sdp, 0, size);
3057
3058         /*
3059          * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
3060          * VSC SDP Header Bytes
3061          */
3062         sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
3063         sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
3064         sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
3065         sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
3066
3067         /*
3068          * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
3069          * per DP 1.4a spec.
3070          */
3071         if (vsc->revision != 0x5)
3072                 goto out;
3073
3074         /* VSC SDP Payload for DB16 through DB18 */
3075         /* Pixel Encoding and Colorimetry Formats  */
3076         sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
3077         sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
3078
3079         switch (vsc->bpc) {
3080         case 6:
3081                 /* 6bpc: 0x0 */
3082                 break;
3083         case 8:
3084                 sdp->db[17] = 0x1; /* DB17[3:0] */
3085                 break;
3086         case 10:
3087                 sdp->db[17] = 0x2;
3088                 break;
3089         case 12:
3090                 sdp->db[17] = 0x3;
3091                 break;
3092         case 16:
3093                 sdp->db[17] = 0x4;
3094                 break;
3095         default:
3096                 MISSING_CASE(vsc->bpc);
3097                 break;
3098         }
3099         /* Dynamic Range and Component Bit Depth */
3100         if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
3101                 sdp->db[17] |= 0x80;  /* DB17[7] */
3102
3103         /* Content Type */
3104         sdp->db[18] = vsc->content_type & 0x7;
3105
3106 out:
3107         return length;
3108 }
3109
3110 static ssize_t
3111 intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,
3112                                          const struct hdmi_drm_infoframe *drm_infoframe,
3113                                          struct dp_sdp *sdp,
3114                                          size_t size)
3115 {
3116         size_t length = sizeof(struct dp_sdp);
3117         const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
3118         unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
3119         ssize_t len;
3120
3121         if (size < length)
3122                 return -ENOSPC;
3123
3124         memset(sdp, 0, size);
3125
3126         len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
3127         if (len < 0) {
3128                 drm_dbg_kms(&i915->drm, "buffer size is smaller than hdr metadata infoframe\n");
3129                 return -ENOSPC;
3130         }
3131
3132         if (len != infoframe_size) {
3133                 drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");
3134                 return -ENOSPC;
3135         }
3136
3137         /*
3138          * Set up the infoframe sdp packet for HDR static metadata.
3139          * Prepare VSC Header for SU as per DP 1.4a spec,
3140          * Table 2-100 and Table 2-101
3141          */
3142
3143         /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
3144         sdp->sdp_header.HB0 = 0;
3145         /*
3146          * Packet Type 80h + Non-audio INFOFRAME Type value
3147          * HDMI_INFOFRAME_TYPE_DRM: 0x87
3148          * - 80h + Non-audio INFOFRAME Type value
3149          * - InfoFrame Type: 0x07
3150          *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
3151          */
3152         sdp->sdp_header.HB1 = drm_infoframe->type;
3153         /*
3154          * Least Significant Eight Bits of (Data Byte Count – 1)
3155          * infoframe_size - 1
3156          */
3157         sdp->sdp_header.HB2 = 0x1D;
3158         /* INFOFRAME SDP Version Number */
3159         sdp->sdp_header.HB3 = (0x13 << 2);
3160         /* CTA Header Byte 2 (INFOFRAME Version Number) */
3161         sdp->db[0] = drm_infoframe->version;
3162         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
3163         sdp->db[1] = drm_infoframe->length;
3164         /*
3165          * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
3166          * HDMI_INFOFRAME_HEADER_SIZE
3167          */
3168         BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
3169         memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
3170                HDMI_DRM_INFOFRAME_SIZE);
3171
3172         /*
3173          * Size of DP infoframe sdp packet for HDR static metadata consists of
3174          * - DP SDP Header(struct dp_sdp_header): 4 bytes
3175          * - Two Data Blocks: 2 bytes
3176          *    CTA Header Byte2 (INFOFRAME Version Number)
3177          *    CTA Header Byte3 (Length of INFOFRAME)
3178          * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
3179          *
3180          * Prior to GEN11's GMP register size is identical to DP HDR static metadata
3181          * infoframe size. But GEN11+ has larger than that size, write_infoframe
3182          * will pad rest of the size.
3183          */
3184         return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
3185 }
3186
3187 static void intel_write_dp_sdp(struct intel_encoder *encoder,
3188                                const struct intel_crtc_state *crtc_state,
3189                                unsigned int type)
3190 {
3191         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3192         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3193         struct dp_sdp sdp = {};
3194         ssize_t len;
3195
3196         if ((crtc_state->infoframes.enable &
3197              intel_hdmi_infoframe_enable(type)) == 0)
3198                 return;
3199
3200         switch (type) {
3201         case DP_SDP_VSC:
3202                 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
3203                                             sizeof(sdp));
3204                 break;
3205         case HDMI_PACKET_TYPE_GAMUT_METADATA:
3206                 len = intel_dp_hdr_metadata_infoframe_sdp_pack(dev_priv,
3207                                                                &crtc_state->infoframes.drm.drm,
3208                                                                &sdp, sizeof(sdp));
3209                 break;
3210         default:
3211                 MISSING_CASE(type);
3212                 return;
3213         }
3214
3215         if (drm_WARN_ON(&dev_priv->drm, len < 0))
3216                 return;
3217
3218         dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
3219 }
3220
3221 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
3222                             const struct intel_crtc_state *crtc_state,
3223                             const struct drm_dp_vsc_sdp *vsc)
3224 {
3225         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3226         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3227         struct dp_sdp sdp = {};
3228         ssize_t len;
3229
3230         len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
3231
3232         if (drm_WARN_ON(&dev_priv->drm, len < 0))
3233                 return;
3234
3235         dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
3236                                         &sdp, len);
3237 }
3238
3239 void intel_dp_set_infoframes(struct intel_encoder *encoder,
3240                              bool enable,
3241                              const struct intel_crtc_state *crtc_state,
3242                              const struct drm_connector_state *conn_state)
3243 {
3244         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3245         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
3246         u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
3247                          VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
3248                          VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
3249         u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
3250
3251         /* TODO: Add DSC case (DIP_ENABLE_PPS) */
3252         /* When PSR is enabled, this routine doesn't disable VSC DIP */
3253         if (!crtc_state->has_psr)
3254                 val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
3255
3256         intel_de_write(dev_priv, reg, val);
3257         intel_de_posting_read(dev_priv, reg);
3258
3259         if (!enable)
3260                 return;
3261
3262         /* When PSR is enabled, VSC SDP is handled by PSR routine */
3263         if (!crtc_state->has_psr)
3264                 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
3265
3266         intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
3267 }
3268
3269 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
3270                                    const void *buffer, size_t size)
3271 {
3272         const struct dp_sdp *sdp = buffer;
3273
3274         if (size < sizeof(struct dp_sdp))
3275                 return -EINVAL;
3276
3277         memset(vsc, 0, sizeof(*vsc));
3278
3279         if (sdp->sdp_header.HB0 != 0)
3280                 return -EINVAL;
3281
3282         if (sdp->sdp_header.HB1 != DP_SDP_VSC)
3283                 return -EINVAL;
3284
3285         vsc->sdp_type = sdp->sdp_header.HB1;
3286         vsc->revision = sdp->sdp_header.HB2;
3287         vsc->length = sdp->sdp_header.HB3;
3288
3289         if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
3290             (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
3291                 /*
3292                  * - HB2 = 0x2, HB3 = 0x8
3293                  *   VSC SDP supporting 3D stereo + PSR
3294                  * - HB2 = 0x4, HB3 = 0xe
3295                  *   VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
3296                  *   first scan line of the SU region (applies to eDP v1.4b
3297                  *   and higher).
3298                  */
3299                 return 0;
3300         } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
3301                 /*
3302                  * - HB2 = 0x5, HB3 = 0x13
3303                  *   VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
3304                  *   Format.
3305                  */
3306                 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
3307                 vsc->colorimetry = sdp->db[16] & 0xf;
3308                 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
3309
3310                 switch (sdp->db[17] & 0x7) {
3311                 case 0x0:
3312                         vsc->bpc = 6;
3313                         break;
3314                 case 0x1:
3315                         vsc->bpc = 8;
3316                         break;
3317                 case 0x2:
3318                         vsc->bpc = 10;
3319                         break;
3320                 case 0x3:
3321                         vsc->bpc = 12;
3322                         break;
3323                 case 0x4:
3324                         vsc->bpc = 16;
3325                         break;
3326                 default:
3327                         MISSING_CASE(sdp->db[17] & 0x7);
3328                         return -EINVAL;
3329                 }
3330
3331                 vsc->content_type = sdp->db[18] & 0x7;
3332         } else {
3333                 return -EINVAL;
3334         }
3335
3336         return 0;
3337 }
3338
3339 static int
3340 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
3341                                            const void *buffer, size_t size)
3342 {
3343         int ret;
3344
3345         const struct dp_sdp *sdp = buffer;
3346
3347         if (size < sizeof(struct dp_sdp))
3348                 return -EINVAL;
3349
3350         if (sdp->sdp_header.HB0 != 0)
3351                 return -EINVAL;
3352
3353         if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
3354                 return -EINVAL;
3355
3356         /*
3357          * Least Significant Eight Bits of (Data Byte Count – 1)
3358          * 1Dh (i.e., Data Byte Count = 30 bytes).
3359          */
3360         if (sdp->sdp_header.HB2 != 0x1D)
3361                 return -EINVAL;
3362
3363         /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
3364         if ((sdp->sdp_header.HB3 & 0x3) != 0)
3365                 return -EINVAL;
3366
3367         /* INFOFRAME SDP Version Number */
3368         if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
3369                 return -EINVAL;
3370
3371         /* CTA Header Byte 2 (INFOFRAME Version Number) */
3372         if (sdp->db[0] != 1)
3373                 return -EINVAL;
3374
3375         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
3376         if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
3377                 return -EINVAL;
3378
3379         ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
3380                                              HDMI_DRM_INFOFRAME_SIZE);
3381
3382         return ret;
3383 }
3384
3385 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
3386                                   struct intel_crtc_state *crtc_state,
3387                                   struct drm_dp_vsc_sdp *vsc)
3388 {
3389         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3390         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3391         unsigned int type = DP_SDP_VSC;
3392         struct dp_sdp sdp = {};
3393         int ret;
3394
3395         /* When PSR is enabled, VSC SDP is handled by PSR routine */
3396         if (crtc_state->has_psr)
3397                 return;
3398
3399         if ((crtc_state->infoframes.enable &
3400              intel_hdmi_infoframe_enable(type)) == 0)
3401                 return;
3402
3403         dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
3404
3405         ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
3406
3407         if (ret)
3408                 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
3409 }
3410
3411 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
3412                                                      struct intel_crtc_state *crtc_state,
3413                                                      struct hdmi_drm_infoframe *drm_infoframe)
3414 {
3415         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3416         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3417         unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
3418         struct dp_sdp sdp = {};
3419         int ret;
3420
3421         if ((crtc_state->infoframes.enable &
3422             intel_hdmi_infoframe_enable(type)) == 0)
3423                 return;
3424
3425         dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
3426                                  sizeof(sdp));
3427
3428         ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
3429                                                          sizeof(sdp));
3430
3431         if (ret)
3432                 drm_dbg_kms(&dev_priv->drm,
3433                             "Failed to unpack DP HDR Metadata Infoframe SDP\n");
3434 }
3435
3436 void intel_read_dp_sdp(struct intel_encoder *encoder,
3437                        struct intel_crtc_state *crtc_state,
3438                        unsigned int type)
3439 {
3440         switch (type) {
3441         case DP_SDP_VSC:
3442                 intel_read_dp_vsc_sdp(encoder, crtc_state,
3443                                       &crtc_state->infoframes.vsc);
3444                 break;
3445         case HDMI_PACKET_TYPE_GAMUT_METADATA:
3446                 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
3447                                                          &crtc_state->infoframes.drm.drm);
3448                 break;
3449         default:
3450                 MISSING_CASE(type);
3451                 break;
3452         }
3453 }
3454
3455 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3456 {
3457         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3458         int status = 0;
3459         int test_link_rate;
3460         u8 test_lane_count, test_link_bw;
3461         /* (DP CTS 1.2)
3462          * 4.3.1.11
3463          */
3464         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
3465         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
3466                                    &test_lane_count);
3467
3468         if (status <= 0) {
3469                 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
3470                 return DP_TEST_NAK;
3471         }
3472         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
3473
3474         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
3475                                    &test_link_bw);
3476         if (status <= 0) {
3477                 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
3478                 return DP_TEST_NAK;
3479         }
3480         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
3481
3482         /* Validate the requested link rate and lane count */
3483         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
3484                                         test_lane_count))
3485                 return DP_TEST_NAK;
3486
3487         intel_dp->compliance.test_lane_count = test_lane_count;
3488         intel_dp->compliance.test_link_rate = test_link_rate;
3489
3490         return DP_TEST_ACK;
3491 }
3492
3493 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3494 {
3495         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3496         u8 test_pattern;
3497         u8 test_misc;
3498         __be16 h_width, v_height;
3499         int status = 0;
3500
3501         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
3502         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
3503                                    &test_pattern);
3504         if (status <= 0) {
3505                 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
3506                 return DP_TEST_NAK;
3507         }
3508         if (test_pattern != DP_COLOR_RAMP)
3509                 return DP_TEST_NAK;
3510
3511         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
3512                                   &h_width, 2);
3513         if (status <= 0) {
3514                 drm_dbg_kms(&i915->drm, "H Width read failed\n");
3515                 return DP_TEST_NAK;
3516         }
3517
3518         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
3519                                   &v_height, 2);
3520         if (status <= 0) {
3521                 drm_dbg_kms(&i915->drm, "V Height read failed\n");
3522                 return DP_TEST_NAK;
3523         }
3524
3525         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
3526                                    &test_misc);
3527         if (status <= 0) {
3528                 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
3529                 return DP_TEST_NAK;
3530         }
3531         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
3532                 return DP_TEST_NAK;
3533         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
3534                 return DP_TEST_NAK;
3535         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
3536         case DP_TEST_BIT_DEPTH_6:
3537                 intel_dp->compliance.test_data.bpc = 6;
3538                 break;
3539         case DP_TEST_BIT_DEPTH_8:
3540                 intel_dp->compliance.test_data.bpc = 8;
3541                 break;
3542         default:
3543                 return DP_TEST_NAK;
3544         }
3545
3546         intel_dp->compliance.test_data.video_pattern = test_pattern;
3547         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
3548         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
3549         /* Set test active flag here so userspace doesn't interrupt things */
3550         intel_dp->compliance.test_active = true;
3551
3552         return DP_TEST_ACK;
3553 }
3554
3555 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
3556 {
3557         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3558         u8 test_result = DP_TEST_ACK;
3559         struct intel_connector *intel_connector = intel_dp->attached_connector;
3560         struct drm_connector *connector = &intel_connector->base;
3561
3562         if (intel_connector->detect_edid == NULL ||
3563             connector->edid_corrupt ||
3564             intel_dp->aux.i2c_defer_count > 6) {
3565                 /* Check EDID read for NACKs, DEFERs and corruption
3566                  * (DP CTS 1.2 Core r1.1)
3567                  *    4.2.2.4 : Failed EDID read, I2C_NAK
3568                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
3569                  *    4.2.2.6 : EDID corruption detected
3570                  * Use failsafe mode for all cases
3571                  */
3572                 if (intel_dp->aux.i2c_nack_count > 0 ||
3573                         intel_dp->aux.i2c_defer_count > 0)
3574                         drm_dbg_kms(&i915->drm,
3575                                     "EDID read had %d NACKs, %d DEFERs\n",
3576                                     intel_dp->aux.i2c_nack_count,
3577                                     intel_dp->aux.i2c_defer_count);
3578                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
3579         } else {
3580                 struct edid *block = intel_connector->detect_edid;
3581
3582                 /* We have to write the checksum
3583                  * of the last block read
3584                  */
3585                 block += intel_connector->detect_edid->extensions;
3586
3587                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
3588                                        block->checksum) <= 0)
3589                         drm_dbg_kms(&i915->drm,
3590                                     "Failed to write EDID checksum\n");
3591
3592                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3593                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
3594         }
3595
3596         /* Set test active flag here so userspace doesn't interrupt things */
3597         intel_dp->compliance.test_active = true;
3598
3599         return test_result;
3600 }
3601
3602 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
3603                                         const struct intel_crtc_state *crtc_state)
3604 {
3605         struct drm_i915_private *dev_priv =
3606                         to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3607         struct drm_dp_phy_test_params *data =
3608                         &intel_dp->compliance.test_data.phytest;
3609         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3610         enum pipe pipe = crtc->pipe;
3611         u32 pattern_val;
3612
3613         switch (data->phy_pattern) {
3614         case DP_PHY_TEST_PATTERN_NONE:
3615                 drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n");
3616                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
3617                 break;
3618         case DP_PHY_TEST_PATTERN_D10_2:
3619                 drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n");
3620                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3621                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
3622                 break;
3623         case DP_PHY_TEST_PATTERN_ERROR_COUNT:
3624                 drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n");
3625                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3626                                DDI_DP_COMP_CTL_ENABLE |
3627                                DDI_DP_COMP_CTL_SCRAMBLED_0);
3628                 break;
3629         case DP_PHY_TEST_PATTERN_PRBS7:
3630                 drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n");
3631                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3632                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
3633                 break;
3634         case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
3635                 /*
3636                  * FIXME: Ideally pattern should come from DPCD 0x250. As
3637                  * current firmware of DPR-100 could not set it, so hardcoding
3638                  * now for complaince test.
3639                  */
3640                 drm_dbg_kms(&dev_priv->drm,
3641                             "Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
3642                 pattern_val = 0x3e0f83e0;
3643                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
3644                 pattern_val = 0x0f83e0f8;
3645                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
3646                 pattern_val = 0x0000f83e;
3647                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
3648                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3649                                DDI_DP_COMP_CTL_ENABLE |
3650                                DDI_DP_COMP_CTL_CUSTOM80);
3651                 break;
3652         case DP_PHY_TEST_PATTERN_CP2520:
3653                 /*
3654                  * FIXME: Ideally pattern should come from DPCD 0x24A. As
3655                  * current firmware of DPR-100 could not set it, so hardcoding
3656                  * now for complaince test.
3657                  */
3658                 drm_dbg_kms(&dev_priv->drm, "Set HBR2 compliance Phy Test Pattern\n");
3659                 pattern_val = 0xFB;
3660                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3661                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
3662                                pattern_val);
3663                 break;
3664         default:
3665                 WARN(1, "Invalid Phy Test Pattern\n");
3666         }
3667 }
3668
3669 static void
3670 intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp,
3671                                   const struct intel_crtc_state *crtc_state)
3672 {
3673         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3674         struct drm_device *dev = dig_port->base.base.dev;
3675         struct drm_i915_private *dev_priv = to_i915(dev);
3676         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
3677         enum pipe pipe = crtc->pipe;
3678         u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
3679
3680         trans_ddi_func_ctl_value = intel_de_read(dev_priv,
3681                                                  TRANS_DDI_FUNC_CTL(pipe));
3682         trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
3683         dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
3684
3685         trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
3686                                       TGL_TRANS_DDI_PORT_MASK);
3687         trans_conf_value &= ~PIPECONF_ENABLE;
3688         dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
3689
3690         intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
3691         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
3692                        trans_ddi_func_ctl_value);
3693         intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
3694 }
3695
3696 static void
3697 intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp,
3698                                  const struct intel_crtc_state *crtc_state)
3699 {
3700         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3701         struct drm_device *dev = dig_port->base.base.dev;
3702         struct drm_i915_private *dev_priv = to_i915(dev);
3703         enum port port = dig_port->base.port;
3704         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
3705         enum pipe pipe = crtc->pipe;
3706         u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
3707
3708         trans_ddi_func_ctl_value = intel_de_read(dev_priv,
3709                                                  TRANS_DDI_FUNC_CTL(pipe));
3710         trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
3711         dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
3712
3713         trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
3714                                     TGL_TRANS_DDI_SELECT_PORT(port);
3715         trans_conf_value |= PIPECONF_ENABLE;
3716         dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
3717
3718         intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
3719         intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
3720         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
3721                        trans_ddi_func_ctl_value);
3722 }
3723
3724 static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
3725                                          const struct intel_crtc_state *crtc_state)
3726 {
3727         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3728         struct drm_dp_phy_test_params *data =
3729                 &intel_dp->compliance.test_data.phytest;
3730         u8 link_status[DP_LINK_STATUS_SIZE];
3731
3732         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
3733                                              link_status) < 0) {
3734                 drm_dbg_kms(&i915->drm, "failed to get link status\n");
3735                 return;
3736         }
3737
3738         /* retrieve vswing & pre-emphasis setting */
3739         intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
3740                                   link_status);
3741
3742         intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
3743
3744         intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
3745
3746         intel_dp_phy_pattern_update(intel_dp, crtc_state);
3747
3748         intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state);
3749
3750         drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3751                           intel_dp->train_set, crtc_state->lane_count);
3752
3753         drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
3754                                     link_status[DP_DPCD_REV]);
3755 }
3756
3757 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
3758 {
3759         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3760         struct drm_dp_phy_test_params *data =
3761                 &intel_dp->compliance.test_data.phytest;
3762
3763         if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
3764                 drm_dbg_kms(&i915->drm, "DP Phy Test pattern AUX read failure\n");
3765                 return DP_TEST_NAK;
3766         }
3767
3768         /* Set test active flag here so userspace doesn't interrupt things */
3769         intel_dp->compliance.test_active = true;
3770
3771         return DP_TEST_ACK;
3772 }
3773
3774 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3775 {
3776         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3777         u8 response = DP_TEST_NAK;
3778         u8 request = 0;
3779         int status;
3780
3781         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
3782         if (status <= 0) {
3783                 drm_dbg_kms(&i915->drm,
3784                             "Could not read test request from sink\n");
3785                 goto update_status;
3786         }
3787
3788         switch (request) {
3789         case DP_TEST_LINK_TRAINING:
3790                 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
3791                 response = intel_dp_autotest_link_training(intel_dp);
3792                 break;
3793         case DP_TEST_LINK_VIDEO_PATTERN:
3794                 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
3795                 response = intel_dp_autotest_video_pattern(intel_dp);
3796                 break;
3797         case DP_TEST_LINK_EDID_READ:
3798                 drm_dbg_kms(&i915->drm, "EDID test requested\n");
3799                 response = intel_dp_autotest_edid(intel_dp);
3800                 break;
3801         case DP_TEST_LINK_PHY_TEST_PATTERN:
3802                 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
3803                 response = intel_dp_autotest_phy_pattern(intel_dp);
3804                 break;
3805         default:
3806                 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
3807                             request);
3808                 break;
3809         }
3810
3811         if (response & DP_TEST_ACK)
3812                 intel_dp->compliance.test_type = request;
3813
3814 update_status:
3815         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
3816         if (status <= 0)
3817                 drm_dbg_kms(&i915->drm,
3818                             "Could not write test response to sink\n");
3819 }
3820
3821 static bool intel_dp_link_ok(struct intel_dp *intel_dp,
3822                              u8 link_status[DP_LINK_STATUS_SIZE])
3823 {
3824         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3825         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3826         bool uhbr = intel_dp->link_rate >= 1000000;
3827         bool ok;
3828
3829         if (uhbr)
3830                 ok = drm_dp_128b132b_lane_channel_eq_done(link_status,
3831                                                           intel_dp->lane_count);
3832         else
3833                 ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
3834
3835         if (ok)
3836                 return true;
3837
3838         intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
3839         drm_dbg_kms(&i915->drm,
3840                     "[ENCODER:%d:%s] %s link not ok, retraining\n",
3841                     encoder->base.base.id, encoder->base.name,
3842                     uhbr ? "128b/132b" : "8b/10b");
3843
3844         return false;
3845 }
3846
3847 static void
3848 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)
3849 {
3850         bool handled = false;
3851
3852         drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3853         if (handled)
3854                 ack[1] |= esi[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY);
3855
3856         if (esi[1] & DP_CP_IRQ) {
3857                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
3858                 ack[1] |= DP_CP_IRQ;
3859         }
3860 }
3861
3862 static bool intel_dp_mst_link_status(struct intel_dp *intel_dp)
3863 {
3864         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3865         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3866         u8 link_status[DP_LINK_STATUS_SIZE] = {};
3867         const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;
3868
3869         if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status,
3870                              esi_link_status_size) != esi_link_status_size) {
3871                 drm_err(&i915->drm,
3872                         "[ENCODER:%d:%s] Failed to read link status\n",
3873                         encoder->base.base.id, encoder->base.name);
3874                 return false;
3875         }
3876
3877         return intel_dp_link_ok(intel_dp, link_status);
3878 }
3879
3880 /**
3881  * intel_dp_check_mst_status - service any pending MST interrupts, check link status
3882  * @intel_dp: Intel DP struct
3883  *
3884  * Read any pending MST interrupts, call MST core to handle these and ack the
3885  * interrupts. Check if the main and AUX link state is ok.
3886  *
3887  * Returns:
3888  * - %true if pending interrupts were serviced (or no interrupts were
3889  *   pending) w/o detecting an error condition.
3890  * - %false if an error condition - like AUX failure or a loss of link - is
3891  *   detected, which needs servicing from the hotplug work.
3892  */
3893 static bool
3894 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3895 {
3896         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3897         bool link_ok = true;
3898
3899         drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
3900
3901         for (;;) {
3902                 u8 esi[4] = {};
3903                 u8 ack[4] = {};
3904
3905                 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
3906                         drm_dbg_kms(&i915->drm,
3907                                     "failed to get ESI - device may have failed\n");
3908                         link_ok = false;
3909
3910                         break;
3911                 }
3912
3913                 drm_dbg_kms(&i915->drm, "DPRX ESI: %4ph\n", esi);
3914
3915                 if (intel_dp->active_mst_links > 0 && link_ok &&
3916                     esi[3] & LINK_STATUS_CHANGED) {
3917                         if (!intel_dp_mst_link_status(intel_dp))
3918                                 link_ok = false;
3919                         ack[3] |= LINK_STATUS_CHANGED;
3920                 }
3921
3922                 intel_dp_mst_hpd_irq(intel_dp, esi, ack);
3923
3924                 if (!memchr_inv(ack, 0, sizeof(ack)))
3925                         break;
3926
3927                 if (!intel_dp_ack_sink_irq_esi(intel_dp, ack))
3928                         drm_dbg_kms(&i915->drm, "Failed to ack ESI\n");
3929         }
3930
3931         return link_ok;
3932 }
3933
3934 static void
3935 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
3936 {
3937         bool is_active;
3938         u8 buf = 0;
3939
3940         is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
3941         if (intel_dp->frl.is_trained && !is_active) {
3942                 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
3943                         return;
3944
3945                 buf &=  ~DP_PCON_ENABLE_HDMI_LINK;
3946                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
3947                         return;
3948
3949                 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
3950
3951                 /* Restart FRL training or fall back to TMDS mode */
3952                 intel_dp_check_frl_training(intel_dp);
3953         }
3954 }
3955
3956 static bool
3957 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
3958 {
3959         u8 link_status[DP_LINK_STATUS_SIZE];
3960
3961         if (!intel_dp->link_trained)
3962                 return false;
3963
3964         /*
3965          * While PSR source HW is enabled, it will control main-link sending
3966          * frames, enabling and disabling it so trying to do a retrain will fail
3967          * as the link would or not be on or it could mix training patterns
3968          * and frame data at the same time causing retrain to fail.
3969          * Also when exiting PSR, HW will retrain the link anyways fixing
3970          * any link status error.
3971          */
3972         if (intel_psr_enabled(intel_dp))
3973                 return false;
3974
3975         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
3976                                              link_status) < 0)
3977                 return false;
3978
3979         /*
3980          * Validate the cached values of intel_dp->link_rate and
3981          * intel_dp->lane_count before attempting to retrain.
3982          *
3983          * FIXME would be nice to user the crtc state here, but since
3984          * we need to call this from the short HPD handler that seems
3985          * a bit hard.
3986          */
3987         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
3988                                         intel_dp->lane_count))
3989                 return false;
3990
3991         /* Retrain if link not ok */
3992         return !intel_dp_link_ok(intel_dp, link_status);
3993 }
3994
3995 static bool intel_dp_has_connector(struct intel_dp *intel_dp,
3996                                    const struct drm_connector_state *conn_state)
3997 {
3998         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3999         struct intel_encoder *encoder;
4000         enum pipe pipe;
4001
4002         if (!conn_state->best_encoder)
4003                 return false;
4004
4005         /* SST */
4006         encoder = &dp_to_dig_port(intel_dp)->base;
4007         if (conn_state->best_encoder == &encoder->base)
4008                 return true;
4009
4010         /* MST */
4011         for_each_pipe(i915, pipe) {
4012                 encoder = &intel_dp->mst_encoders[pipe]->base;
4013                 if (conn_state->best_encoder == &encoder->base)
4014                         return true;
4015         }
4016
4017         return false;
4018 }
4019
4020 static int intel_dp_prep_link_retrain(struct intel_dp *intel_dp,
4021                                       struct drm_modeset_acquire_ctx *ctx,
4022                                       u8 *pipe_mask)
4023 {
4024         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4025         struct drm_connector_list_iter conn_iter;
4026         struct intel_connector *connector;
4027         int ret = 0;
4028
4029         *pipe_mask = 0;
4030
4031         if (!intel_dp_needs_link_retrain(intel_dp))
4032                 return 0;
4033
4034         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
4035         for_each_intel_connector_iter(connector, &conn_iter) {
4036                 struct drm_connector_state *conn_state =
4037                         connector->base.state;
4038                 struct intel_crtc_state *crtc_state;
4039                 struct intel_crtc *crtc;
4040
4041                 if (!intel_dp_has_connector(intel_dp, conn_state))
4042                         continue;
4043
4044                 crtc = to_intel_crtc(conn_state->crtc);
4045                 if (!crtc)
4046                         continue;
4047
4048                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4049                 if (ret)
4050                         break;
4051
4052                 crtc_state = to_intel_crtc_state(crtc->base.state);
4053
4054                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
4055
4056                 if (!crtc_state->hw.active)
4057                         continue;
4058
4059                 if (conn_state->commit &&
4060                     !try_wait_for_completion(&conn_state->commit->hw_done))
4061                         continue;
4062
4063                 *pipe_mask |= BIT(crtc->pipe);
4064         }
4065         drm_connector_list_iter_end(&conn_iter);
4066
4067         if (!intel_dp_needs_link_retrain(intel_dp))
4068                 *pipe_mask = 0;
4069
4070         return ret;
4071 }
4072
4073 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
4074 {
4075         struct intel_connector *connector = intel_dp->attached_connector;
4076
4077         return connector->base.status == connector_status_connected ||
4078                 intel_dp->is_mst;
4079 }
4080
4081 int intel_dp_retrain_link(struct intel_encoder *encoder,
4082                           struct drm_modeset_acquire_ctx *ctx)
4083 {
4084         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4085         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4086         struct intel_crtc *crtc;
4087         u8 pipe_mask;
4088         int ret;
4089
4090         if (!intel_dp_is_connected(intel_dp))
4091                 return 0;
4092
4093         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4094                                ctx);
4095         if (ret)
4096                 return ret;
4097
4098         ret = intel_dp_prep_link_retrain(intel_dp, ctx, &pipe_mask);
4099         if (ret)
4100                 return ret;
4101
4102         if (pipe_mask == 0)
4103                 return 0;
4104
4105         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
4106                     encoder->base.base.id, encoder->base.name);
4107
4108         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4109                 const struct intel_crtc_state *crtc_state =
4110                         to_intel_crtc_state(crtc->base.state);
4111
4112                 /* Suppress underruns caused by re-training */
4113                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4114                 if (crtc_state->has_pch_encoder)
4115                         intel_set_pch_fifo_underrun_reporting(dev_priv,
4116                                                               intel_crtc_pch_transcoder(crtc), false);
4117         }
4118
4119         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4120                 const struct intel_crtc_state *crtc_state =
4121                         to_intel_crtc_state(crtc->base.state);
4122
4123                 /* retrain on the MST master transcoder */
4124                 if (DISPLAY_VER(dev_priv) >= 12 &&
4125                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
4126                     !intel_dp_mst_is_master_trans(crtc_state))
4127                         continue;
4128
4129                 intel_dp_check_frl_training(intel_dp);
4130                 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
4131                 intel_dp_start_link_train(intel_dp, crtc_state);
4132                 intel_dp_stop_link_train(intel_dp, crtc_state);
4133                 break;
4134         }
4135
4136         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4137                 const struct intel_crtc_state *crtc_state =
4138                         to_intel_crtc_state(crtc->base.state);
4139
4140                 /* Keep underrun reporting disabled until things are stable */
4141                 intel_crtc_wait_for_next_vblank(crtc);
4142
4143                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4144                 if (crtc_state->has_pch_encoder)
4145                         intel_set_pch_fifo_underrun_reporting(dev_priv,
4146                                                               intel_crtc_pch_transcoder(crtc), true);
4147         }
4148
4149         return 0;
4150 }
4151
4152 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
4153                                   struct drm_modeset_acquire_ctx *ctx,
4154                                   u8 *pipe_mask)
4155 {
4156         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4157         struct drm_connector_list_iter conn_iter;
4158         struct intel_connector *connector;
4159         int ret = 0;
4160
4161         *pipe_mask = 0;
4162
4163         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
4164         for_each_intel_connector_iter(connector, &conn_iter) {
4165                 struct drm_connector_state *conn_state =
4166                         connector->base.state;
4167                 struct intel_crtc_state *crtc_state;
4168                 struct intel_crtc *crtc;
4169
4170                 if (!intel_dp_has_connector(intel_dp, conn_state))
4171                         continue;
4172
4173                 crtc = to_intel_crtc(conn_state->crtc);
4174                 if (!crtc)
4175                         continue;
4176
4177                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4178                 if (ret)
4179                         break;
4180
4181                 crtc_state = to_intel_crtc_state(crtc->base.state);
4182
4183                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
4184
4185                 if (!crtc_state->hw.active)
4186                         continue;
4187
4188                 if (conn_state->commit &&
4189                     !try_wait_for_completion(&conn_state->commit->hw_done))
4190                         continue;
4191
4192                 *pipe_mask |= BIT(crtc->pipe);
4193         }
4194         drm_connector_list_iter_end(&conn_iter);
4195
4196         return ret;
4197 }
4198
4199 static int intel_dp_do_phy_test(struct intel_encoder *encoder,
4200                                 struct drm_modeset_acquire_ctx *ctx)
4201 {
4202         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4203         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4204         struct intel_crtc *crtc;
4205         u8 pipe_mask;
4206         int ret;
4207
4208         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4209                                ctx);
4210         if (ret)
4211                 return ret;
4212
4213         ret = intel_dp_prep_phy_test(intel_dp, ctx, &pipe_mask);
4214         if (ret)
4215                 return ret;
4216
4217         if (pipe_mask == 0)
4218                 return 0;
4219
4220         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
4221                     encoder->base.base.id, encoder->base.name);
4222
4223         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4224                 const struct intel_crtc_state *crtc_state =
4225                         to_intel_crtc_state(crtc->base.state);
4226
4227                 /* test on the MST master transcoder */
4228                 if (DISPLAY_VER(dev_priv) >= 12 &&
4229                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
4230                     !intel_dp_mst_is_master_trans(crtc_state))
4231                         continue;
4232
4233                 intel_dp_process_phy_request(intel_dp, crtc_state);
4234                 break;
4235         }
4236
4237         return 0;
4238 }
4239
4240 void intel_dp_phy_test(struct intel_encoder *encoder)
4241 {
4242         struct drm_modeset_acquire_ctx ctx;
4243         int ret;
4244
4245         drm_modeset_acquire_init(&ctx, 0);
4246
4247         for (;;) {
4248                 ret = intel_dp_do_phy_test(encoder, &ctx);
4249
4250                 if (ret == -EDEADLK) {
4251                         drm_modeset_backoff(&ctx);
4252                         continue;
4253                 }
4254
4255                 break;
4256         }
4257
4258         drm_modeset_drop_locks(&ctx);
4259         drm_modeset_acquire_fini(&ctx);
4260         drm_WARN(encoder->base.dev, ret,
4261                  "Acquiring modeset locks failed with %i\n", ret);
4262 }
4263
4264 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
4265 {
4266         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4267         u8 val;
4268
4269         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4270                 return;
4271
4272         if (drm_dp_dpcd_readb(&intel_dp->aux,
4273                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
4274                 return;
4275
4276         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
4277
4278         if (val & DP_AUTOMATED_TEST_REQUEST)
4279                 intel_dp_handle_test_request(intel_dp);
4280
4281         if (val & DP_CP_IRQ)
4282                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4283
4284         if (val & DP_SINK_SPECIFIC_IRQ)
4285                 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
4286 }
4287
4288 static void intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
4289 {
4290         u8 val;
4291
4292         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4293                 return;
4294
4295         if (drm_dp_dpcd_readb(&intel_dp->aux,
4296                               DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val)
4297                 return;
4298
4299         if (drm_dp_dpcd_writeb(&intel_dp->aux,
4300                                DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1)
4301                 return;
4302
4303         if (val & HDMI_LINK_STATUS_CHANGED)
4304                 intel_dp_handle_hdmi_link_status_change(intel_dp);
4305 }
4306
4307 /*
4308  * According to DP spec
4309  * 5.1.2:
4310  *  1. Read DPCD
4311  *  2. Configure link according to Receiver Capabilities
4312  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4313  *  4. Check link status on receipt of hot-plug interrupt
4314  *
4315  * intel_dp_short_pulse -  handles short pulse interrupts
4316  * when full detection is not required.
4317  * Returns %true if short pulse is handled and full detection
4318  * is NOT required and %false otherwise.
4319  */
4320 static bool
4321 intel_dp_short_pulse(struct intel_dp *intel_dp)
4322 {
4323         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4324         u8 old_sink_count = intel_dp->sink_count;
4325         bool ret;
4326
4327         /*
4328          * Clearing compliance test variables to allow capturing
4329          * of values for next automated test request.
4330          */
4331         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4332
4333         /*
4334          * Now read the DPCD to see if it's actually running
4335          * If the current value of sink count doesn't match with
4336          * the value that was stored earlier or dpcd read failed
4337          * we need to do full detection
4338          */
4339         ret = intel_dp_get_dpcd(intel_dp);
4340
4341         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4342                 /* No need to proceed if we are going to do full detect */
4343                 return false;
4344         }
4345
4346         intel_dp_check_device_service_irq(intel_dp);
4347         intel_dp_check_link_service_irq(intel_dp);
4348
4349         /* Handle CEC interrupts, if any */
4350         drm_dp_cec_irq(&intel_dp->aux);
4351
4352         /* defer to the hotplug work for link retraining if needed */
4353         if (intel_dp_needs_link_retrain(intel_dp))
4354                 return false;
4355
4356         intel_psr_short_pulse(intel_dp);
4357
4358         switch (intel_dp->compliance.test_type) {
4359         case DP_TEST_LINK_TRAINING:
4360                 drm_dbg_kms(&dev_priv->drm,
4361                             "Link Training Compliance Test requested\n");
4362                 /* Send a Hotplug Uevent to userspace to start modeset */
4363                 drm_kms_helper_hotplug_event(&dev_priv->drm);
4364                 break;
4365         case DP_TEST_LINK_PHY_TEST_PATTERN:
4366                 drm_dbg_kms(&dev_priv->drm,
4367                             "PHY test pattern Compliance Test requested\n");
4368                 /*
4369                  * Schedule long hpd to do the test
4370                  *
4371                  * FIXME get rid of the ad-hoc phy test modeset code
4372                  * and properly incorporate it into the normal modeset.
4373                  */
4374                 return false;
4375         }
4376
4377         return true;
4378 }
4379
4380 /* XXX this is probably wrong for multiple downstream ports */
4381 static enum drm_connector_status
4382 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4383 {
4384         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4385         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4386         u8 *dpcd = intel_dp->dpcd;
4387         u8 type;
4388
4389         if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
4390                 return connector_status_connected;
4391
4392         lspcon_resume(dig_port);
4393
4394         if (!intel_dp_get_dpcd(intel_dp))
4395                 return connector_status_disconnected;
4396
4397         /* if there's no downstream port, we're done */
4398         if (!drm_dp_is_branch(dpcd))
4399                 return connector_status_connected;
4400
4401         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4402         if (intel_dp_has_sink_count(intel_dp) &&
4403             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4404                 return intel_dp->sink_count ?
4405                 connector_status_connected : connector_status_disconnected;
4406         }
4407
4408         if (intel_dp_can_mst(intel_dp))
4409                 return connector_status_connected;
4410
4411         /* If no HPD, poke DDC gently */
4412         if (drm_probe_ddc(&intel_dp->aux.ddc))
4413                 return connector_status_connected;
4414
4415         /* Well we tried, say unknown for unreliable port types */
4416         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4417                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4418                 if (type == DP_DS_PORT_TYPE_VGA ||
4419                     type == DP_DS_PORT_TYPE_NON_EDID)
4420                         return connector_status_unknown;
4421         } else {
4422                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4423                         DP_DWN_STRM_PORT_TYPE_MASK;
4424                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4425                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4426                         return connector_status_unknown;
4427         }
4428
4429         /* Anything else is out of spec, warn and ignore */
4430         drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
4431         return connector_status_disconnected;
4432 }
4433
4434 static enum drm_connector_status
4435 edp_detect(struct intel_dp *intel_dp)
4436 {
4437         return connector_status_connected;
4438 }
4439
4440 /*
4441  * intel_digital_port_connected - is the specified port connected?
4442  * @encoder: intel_encoder
4443  *
4444  * In cases where there's a connector physically connected but it can't be used
4445  * by our hardware we also return false, since the rest of the driver should
4446  * pretty much treat the port as disconnected. This is relevant for type-C
4447  * (starting on ICL) where there's ownership involved.
4448  *
4449  * Return %true if port is connected, %false otherwise.
4450  */
4451 bool intel_digital_port_connected(struct intel_encoder *encoder)
4452 {
4453         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4454         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4455         bool is_connected = false;
4456         intel_wakeref_t wakeref;
4457
4458         with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
4459                 is_connected = dig_port->connected(encoder);
4460
4461         return is_connected;
4462 }
4463
4464 static struct edid *
4465 intel_dp_get_edid(struct intel_dp *intel_dp)
4466 {
4467         struct intel_connector *intel_connector = intel_dp->attached_connector;
4468
4469         /* use cached edid if we have one */
4470         if (intel_connector->edid) {
4471                 /* invalid edid */
4472                 if (IS_ERR(intel_connector->edid))
4473                         return NULL;
4474
4475                 return drm_edid_duplicate(intel_connector->edid);
4476         } else
4477                 return drm_get_edid(&intel_connector->base,
4478                                     &intel_dp->aux.ddc);
4479 }
4480
4481 static void
4482 intel_dp_update_dfp(struct intel_dp *intel_dp,
4483                     const struct edid *edid)
4484 {
4485         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4486         struct intel_connector *connector = intel_dp->attached_connector;
4487
4488         intel_dp->dfp.max_bpc =
4489                 drm_dp_downstream_max_bpc(intel_dp->dpcd,
4490                                           intel_dp->downstream_ports, edid);
4491
4492         intel_dp->dfp.max_dotclock =
4493                 drm_dp_downstream_max_dotclock(intel_dp->dpcd,
4494                                                intel_dp->downstream_ports);
4495
4496         intel_dp->dfp.min_tmds_clock =
4497                 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
4498                                                  intel_dp->downstream_ports,
4499                                                  edid);
4500         intel_dp->dfp.max_tmds_clock =
4501                 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
4502                                                  intel_dp->downstream_ports,
4503                                                  edid);
4504
4505         intel_dp->dfp.pcon_max_frl_bw =
4506                 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
4507                                            intel_dp->downstream_ports);
4508
4509         drm_dbg_kms(&i915->drm,
4510                     "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
4511                     connector->base.base.id, connector->base.name,
4512                     intel_dp->dfp.max_bpc,
4513                     intel_dp->dfp.max_dotclock,
4514                     intel_dp->dfp.min_tmds_clock,
4515                     intel_dp->dfp.max_tmds_clock,
4516                     intel_dp->dfp.pcon_max_frl_bw);
4517
4518         intel_dp_get_pcon_dsc_cap(intel_dp);
4519 }
4520
4521 static void
4522 intel_dp_update_420(struct intel_dp *intel_dp)
4523 {
4524         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4525         struct intel_connector *connector = intel_dp->attached_connector;
4526         bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420, rgb_to_ycbcr;
4527
4528         /* No YCbCr output support on gmch platforms */
4529         if (HAS_GMCH(i915))
4530                 return;
4531
4532         /*
4533          * ILK doesn't seem capable of DP YCbCr output. The
4534          * displayed image is severly corrupted. SNB+ is fine.
4535          */
4536         if (IS_IRONLAKE(i915))
4537                 return;
4538
4539         is_branch = drm_dp_is_branch(intel_dp->dpcd);
4540         ycbcr_420_passthrough =
4541                 drm_dp_downstream_420_passthrough(intel_dp->dpcd,
4542                                                   intel_dp->downstream_ports);
4543         /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
4544         ycbcr_444_to_420 =
4545                 dp_to_dig_port(intel_dp)->lspcon.active ||
4546                 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
4547                                                         intel_dp->downstream_ports);
4548         rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
4549                                                                  intel_dp->downstream_ports,
4550                                                                  DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
4551
4552         if (DISPLAY_VER(i915) >= 11) {
4553                 /* Let PCON convert from RGB->YCbCr if possible */
4554                 if (is_branch && rgb_to_ycbcr && ycbcr_444_to_420) {
4555                         intel_dp->dfp.rgb_to_ycbcr = true;
4556                         intel_dp->dfp.ycbcr_444_to_420 = true;
4557                         connector->base.ycbcr_420_allowed = true;
4558                 } else {
4559                 /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */
4560                         intel_dp->dfp.ycbcr_444_to_420 =
4561                                 ycbcr_444_to_420 && !ycbcr_420_passthrough;
4562
4563                         connector->base.ycbcr_420_allowed =
4564                                 !is_branch || ycbcr_444_to_420 || ycbcr_420_passthrough;
4565                 }
4566         } else {
4567                 /* 4:4:4->4:2:0 conversion is the only way */
4568                 intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420;
4569
4570                 connector->base.ycbcr_420_allowed = ycbcr_444_to_420;
4571         }
4572
4573         drm_dbg_kms(&i915->drm,
4574                     "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
4575                     connector->base.base.id, connector->base.name,
4576                     str_yes_no(intel_dp->dfp.rgb_to_ycbcr),
4577                     str_yes_no(connector->base.ycbcr_420_allowed),
4578                     str_yes_no(intel_dp->dfp.ycbcr_444_to_420));
4579 }
4580
4581 static void
4582 intel_dp_set_edid(struct intel_dp *intel_dp)
4583 {
4584         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4585         struct intel_connector *connector = intel_dp->attached_connector;
4586         struct edid *edid;
4587         bool vrr_capable;
4588
4589         intel_dp_unset_edid(intel_dp);
4590         edid = intel_dp_get_edid(intel_dp);
4591         connector->detect_edid = edid;
4592
4593         vrr_capable = intel_vrr_is_capable(connector);
4594         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
4595                     connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));
4596         drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
4597
4598         intel_dp_update_dfp(intel_dp, edid);
4599         intel_dp_update_420(intel_dp);
4600
4601         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
4602                 intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
4603                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4604         }
4605
4606         drm_dp_cec_set_edid(&intel_dp->aux, edid);
4607 }
4608
4609 static void
4610 intel_dp_unset_edid(struct intel_dp *intel_dp)
4611 {
4612         struct intel_connector *connector = intel_dp->attached_connector;
4613
4614         drm_dp_cec_unset_edid(&intel_dp->aux);
4615         kfree(connector->detect_edid);
4616         connector->detect_edid = NULL;
4617
4618         intel_dp->has_hdmi_sink = false;
4619         intel_dp->has_audio = false;
4620
4621         intel_dp->dfp.max_bpc = 0;
4622         intel_dp->dfp.max_dotclock = 0;
4623         intel_dp->dfp.min_tmds_clock = 0;
4624         intel_dp->dfp.max_tmds_clock = 0;
4625
4626         intel_dp->dfp.pcon_max_frl_bw = 0;
4627
4628         intel_dp->dfp.ycbcr_444_to_420 = false;
4629         connector->base.ycbcr_420_allowed = false;
4630
4631         drm_connector_set_vrr_capable_property(&connector->base,
4632                                                false);
4633 }
4634
4635 static int
4636 intel_dp_detect(struct drm_connector *connector,
4637                 struct drm_modeset_acquire_ctx *ctx,
4638                 bool force)
4639 {
4640         struct drm_i915_private *dev_priv = to_i915(connector->dev);
4641         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4642         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4643         struct intel_encoder *encoder = &dig_port->base;
4644         enum drm_connector_status status;
4645
4646         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4647                     connector->base.id, connector->name);
4648         drm_WARN_ON(&dev_priv->drm,
4649                     !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
4650
4651         if (!INTEL_DISPLAY_ENABLED(dev_priv))
4652                 return connector_status_disconnected;
4653
4654         /* Can't disconnect eDP */
4655         if (intel_dp_is_edp(intel_dp))
4656                 status = edp_detect(intel_dp);
4657         else if (intel_digital_port_connected(encoder))
4658                 status = intel_dp_detect_dpcd(intel_dp);
4659         else
4660                 status = connector_status_disconnected;
4661
4662         if (status == connector_status_disconnected) {
4663                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4664                 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4665
4666                 if (intel_dp->is_mst) {
4667                         drm_dbg_kms(&dev_priv->drm,
4668                                     "MST device may have disappeared %d vs %d\n",
4669                                     intel_dp->is_mst,
4670                                     intel_dp->mst_mgr.mst_state);
4671                         intel_dp->is_mst = false;
4672                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4673                                                         intel_dp->is_mst);
4674                 }
4675
4676                 goto out;
4677         }
4678
4679         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
4680         if (DISPLAY_VER(dev_priv) >= 11)
4681                 intel_dp_get_dsc_sink_cap(intel_dp);
4682
4683         intel_dp_configure_mst(intel_dp);
4684
4685         /*
4686          * TODO: Reset link params when switching to MST mode, until MST
4687          * supports link training fallback params.
4688          */
4689         if (intel_dp->reset_link_params || intel_dp->is_mst) {
4690                 intel_dp_reset_max_link_params(intel_dp);
4691                 intel_dp->reset_link_params = false;
4692         }
4693
4694         intel_dp_print_rates(intel_dp);
4695
4696         if (intel_dp->is_mst) {
4697                 /*
4698                  * If we are in MST mode then this connector
4699                  * won't appear connected or have anything
4700                  * with EDID on it
4701                  */
4702                 status = connector_status_disconnected;
4703                 goto out;
4704         }
4705
4706         /*
4707          * Some external monitors do not signal loss of link synchronization
4708          * with an IRQ_HPD, so force a link status check.
4709          */
4710         if (!intel_dp_is_edp(intel_dp)) {
4711                 int ret;
4712
4713                 ret = intel_dp_retrain_link(encoder, ctx);
4714                 if (ret)
4715                         return ret;
4716         }
4717
4718         /*
4719          * Clearing NACK and defer counts to get their exact values
4720          * while reading EDID which are required by Compliance tests
4721          * 4.2.2.4 and 4.2.2.5
4722          */
4723         intel_dp->aux.i2c_nack_count = 0;
4724         intel_dp->aux.i2c_defer_count = 0;
4725
4726         intel_dp_set_edid(intel_dp);
4727         if (intel_dp_is_edp(intel_dp) ||
4728             to_intel_connector(connector)->detect_edid)
4729                 status = connector_status_connected;
4730
4731         intel_dp_check_device_service_irq(intel_dp);
4732
4733 out:
4734         if (status != connector_status_connected && !intel_dp->is_mst)
4735                 intel_dp_unset_edid(intel_dp);
4736
4737         /*
4738          * Make sure the refs for power wells enabled during detect are
4739          * dropped to avoid a new detect cycle triggered by HPD polling.
4740          */
4741         intel_display_power_flush_work(dev_priv);
4742
4743         if (!intel_dp_is_edp(intel_dp))
4744                 drm_dp_set_subconnector_property(connector,
4745                                                  status,
4746                                                  intel_dp->dpcd,
4747                                                  intel_dp->downstream_ports);
4748         return status;
4749 }
4750
4751 static void
4752 intel_dp_force(struct drm_connector *connector)
4753 {
4754         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4755         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4756         struct intel_encoder *intel_encoder = &dig_port->base;
4757         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4758         enum intel_display_power_domain aux_domain =
4759                 intel_aux_power_domain(dig_port);
4760         intel_wakeref_t wakeref;
4761
4762         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4763                     connector->base.id, connector->name);
4764         intel_dp_unset_edid(intel_dp);
4765
4766         if (connector->status != connector_status_connected)
4767                 return;
4768
4769         wakeref = intel_display_power_get(dev_priv, aux_domain);
4770
4771         intel_dp_set_edid(intel_dp);
4772
4773         intel_display_power_put(dev_priv, aux_domain, wakeref);
4774 }
4775
4776 static int intel_dp_get_modes(struct drm_connector *connector)
4777 {
4778         struct intel_connector *intel_connector = to_intel_connector(connector);
4779         struct edid *edid;
4780         int num_modes = 0;
4781
4782         edid = intel_connector->detect_edid;
4783         if (edid)
4784                 num_modes = intel_connector_update_modes(connector, edid);
4785
4786         /* Also add fixed mode, which may or may not be present in EDID */
4787         if (intel_dp_is_edp(intel_attached_dp(intel_connector)))
4788                 num_modes += intel_panel_get_modes(intel_connector);
4789
4790         if (num_modes)
4791                 return num_modes;
4792
4793         if (!edid) {
4794                 struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
4795                 struct drm_display_mode *mode;
4796
4797                 mode = drm_dp_downstream_mode(connector->dev,
4798                                               intel_dp->dpcd,
4799                                               intel_dp->downstream_ports);
4800                 if (mode) {
4801                         drm_mode_probed_add(connector, mode);
4802                         num_modes++;
4803                 }
4804         }
4805
4806         return num_modes;
4807 }
4808
4809 static int
4810 intel_dp_connector_register(struct drm_connector *connector)
4811 {
4812         struct drm_i915_private *i915 = to_i915(connector->dev);
4813         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4814         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4815         struct intel_lspcon *lspcon = &dig_port->lspcon;
4816         int ret;
4817
4818         ret = intel_connector_register(connector);
4819         if (ret)
4820                 return ret;
4821
4822         drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
4823                     intel_dp->aux.name, connector->kdev->kobj.name);
4824
4825         intel_dp->aux.dev = connector->kdev;
4826         ret = drm_dp_aux_register(&intel_dp->aux);
4827         if (!ret)
4828                 drm_dp_cec_register_connector(&intel_dp->aux, connector);
4829
4830         if (!intel_bios_is_lspcon_present(i915, dig_port->base.port))
4831                 return ret;
4832
4833         /*
4834          * ToDo: Clean this up to handle lspcon init and resume more
4835          * efficiently and streamlined.
4836          */
4837         if (lspcon_init(dig_port)) {
4838                 lspcon_detect_hdr_capability(lspcon);
4839                 if (lspcon->hdr_supported)
4840                         drm_connector_attach_hdr_output_metadata_property(connector);
4841         }
4842
4843         return ret;
4844 }
4845
4846 static void
4847 intel_dp_connector_unregister(struct drm_connector *connector)
4848 {
4849         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4850
4851         drm_dp_cec_unregister_connector(&intel_dp->aux);
4852         drm_dp_aux_unregister(&intel_dp->aux);
4853         intel_connector_unregister(connector);
4854 }
4855
4856 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
4857 {
4858         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4859         struct intel_dp *intel_dp = &dig_port->dp;
4860
4861         intel_dp_mst_encoder_cleanup(dig_port);
4862
4863         intel_pps_vdd_off_sync(intel_dp);
4864
4865         intel_dp_aux_fini(intel_dp);
4866 }
4867
4868 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4869 {
4870         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
4871
4872         intel_pps_vdd_off_sync(intel_dp);
4873 }
4874
4875 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
4876 {
4877         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
4878
4879         intel_pps_wait_power_cycle(intel_dp);
4880 }
4881
4882 static int intel_modeset_tile_group(struct intel_atomic_state *state,
4883                                     int tile_group_id)
4884 {
4885         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4886         struct drm_connector_list_iter conn_iter;
4887         struct drm_connector *connector;
4888         int ret = 0;
4889
4890         drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
4891         drm_for_each_connector_iter(connector, &conn_iter) {
4892                 struct drm_connector_state *conn_state;
4893                 struct intel_crtc_state *crtc_state;
4894                 struct intel_crtc *crtc;
4895
4896                 if (!connector->has_tile ||
4897                     connector->tile_group->id != tile_group_id)
4898                         continue;
4899
4900                 conn_state = drm_atomic_get_connector_state(&state->base,
4901                                                             connector);
4902                 if (IS_ERR(conn_state)) {
4903                         ret = PTR_ERR(conn_state);
4904                         break;
4905                 }
4906
4907                 crtc = to_intel_crtc(conn_state->crtc);
4908
4909                 if (!crtc)
4910                         continue;
4911
4912                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
4913                 crtc_state->uapi.mode_changed = true;
4914
4915                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
4916                 if (ret)
4917                         break;
4918         }
4919         drm_connector_list_iter_end(&conn_iter);
4920
4921         return ret;
4922 }
4923
4924 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
4925 {
4926         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4927         struct intel_crtc *crtc;
4928
4929         if (transcoders == 0)
4930                 return 0;
4931
4932         for_each_intel_crtc(&dev_priv->drm, crtc) {
4933                 struct intel_crtc_state *crtc_state;
4934                 int ret;
4935
4936                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
4937                 if (IS_ERR(crtc_state))
4938                         return PTR_ERR(crtc_state);
4939
4940                 if (!crtc_state->hw.enable)
4941                         continue;
4942
4943                 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
4944                         continue;
4945
4946                 crtc_state->uapi.mode_changed = true;
4947
4948                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
4949                 if (ret)
4950                         return ret;
4951
4952                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
4953                 if (ret)
4954                         return ret;
4955
4956                 transcoders &= ~BIT(crtc_state->cpu_transcoder);
4957         }
4958
4959         drm_WARN_ON(&dev_priv->drm, transcoders != 0);
4960
4961         return 0;
4962 }
4963
4964 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
4965                                       struct drm_connector *connector)
4966 {
4967         const struct drm_connector_state *old_conn_state =
4968                 drm_atomic_get_old_connector_state(&state->base, connector);
4969         const struct intel_crtc_state *old_crtc_state;
4970         struct intel_crtc *crtc;
4971         u8 transcoders;
4972
4973         crtc = to_intel_crtc(old_conn_state->crtc);
4974         if (!crtc)
4975                 return 0;
4976
4977         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
4978
4979         if (!old_crtc_state->hw.active)
4980                 return 0;
4981
4982         transcoders = old_crtc_state->sync_mode_slaves_mask;
4983         if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
4984                 transcoders |= BIT(old_crtc_state->master_transcoder);
4985
4986         return intel_modeset_affected_transcoders(state,
4987                                                   transcoders);
4988 }
4989
4990 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
4991                                            struct drm_atomic_state *_state)
4992 {
4993         struct drm_i915_private *dev_priv = to_i915(conn->dev);
4994         struct intel_atomic_state *state = to_intel_atomic_state(_state);
4995         int ret;
4996
4997         ret = intel_digital_connector_atomic_check(conn, &state->base);
4998         if (ret)
4999                 return ret;
5000
5001         /*
5002          * We don't enable port sync on BDW due to missing w/as and
5003          * due to not having adjusted the modeset sequence appropriately.
5004          */
5005         if (DISPLAY_VER(dev_priv) < 9)
5006                 return 0;
5007
5008         if (!intel_connector_needs_modeset(state, conn))
5009                 return 0;
5010
5011         if (conn->has_tile) {
5012                 ret = intel_modeset_tile_group(state, conn->tile_group->id);
5013                 if (ret)
5014                         return ret;
5015         }
5016
5017         return intel_modeset_synced_crtcs(state, conn);
5018 }
5019
5020 static void intel_dp_oob_hotplug_event(struct drm_connector *connector)
5021 {
5022         struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
5023         struct drm_i915_private *i915 = to_i915(connector->dev);
5024
5025         spin_lock_irq(&i915->irq_lock);
5026         i915->hotplug.event_bits |= BIT(encoder->hpd_pin);
5027         spin_unlock_irq(&i915->irq_lock);
5028         queue_delayed_work(system_wq, &i915->hotplug.hotplug_work, 0);
5029 }
5030
5031 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5032         .force = intel_dp_force,
5033         .fill_modes = drm_helper_probe_single_connector_modes,
5034         .atomic_get_property = intel_digital_connector_atomic_get_property,
5035         .atomic_set_property = intel_digital_connector_atomic_set_property,
5036         .late_register = intel_dp_connector_register,
5037         .early_unregister = intel_dp_connector_unregister,
5038         .destroy = intel_connector_destroy,
5039         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5040         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
5041         .oob_hotplug_event = intel_dp_oob_hotplug_event,
5042 };
5043
5044 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5045         .detect_ctx = intel_dp_detect,
5046         .get_modes = intel_dp_get_modes,
5047         .mode_valid = intel_dp_mode_valid,
5048         .atomic_check = intel_dp_connector_atomic_check,
5049 };
5050
5051 enum irqreturn
5052 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
5053 {
5054         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
5055         struct intel_dp *intel_dp = &dig_port->dp;
5056
5057         if (dig_port->base.type == INTEL_OUTPUT_EDP &&
5058             (long_hpd || !intel_pps_have_panel_power_or_vdd(intel_dp))) {
5059                 /*
5060                  * vdd off can generate a long/short pulse on eDP which
5061                  * would require vdd on to handle it, and thus we
5062                  * would end up in an endless cycle of
5063                  * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
5064                  */
5065                 drm_dbg_kms(&i915->drm,
5066                             "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
5067                             long_hpd ? "long" : "short",
5068                             dig_port->base.base.base.id,
5069                             dig_port->base.base.name);
5070                 return IRQ_HANDLED;
5071         }
5072
5073         drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
5074                     dig_port->base.base.base.id,
5075                     dig_port->base.base.name,
5076                     long_hpd ? "long" : "short");
5077
5078         if (long_hpd) {
5079                 intel_dp->reset_link_params = true;
5080                 return IRQ_NONE;
5081         }
5082
5083         if (intel_dp->is_mst) {
5084                 if (!intel_dp_check_mst_status(intel_dp))
5085                         return IRQ_NONE;
5086         } else if (!intel_dp_short_pulse(intel_dp)) {
5087                 return IRQ_NONE;
5088         }
5089
5090         return IRQ_HANDLED;
5091 }
5092
5093 /* check the VBT to see whether the eDP is on another port */
5094 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
5095 {
5096         /*
5097          * eDP not supported on g4x. so bail out early just
5098          * for a bit extra safety in case the VBT is bonkers.
5099          */
5100         if (DISPLAY_VER(dev_priv) < 5)
5101                 return false;
5102
5103         if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A)
5104                 return true;
5105
5106         return intel_bios_is_port_edp(dev_priv, port);
5107 }
5108
5109 static bool
5110 has_gamut_metadata_dip(struct drm_i915_private *i915, enum port port)
5111 {
5112         if (intel_bios_is_lspcon_present(i915, port))
5113                 return false;
5114
5115         if (DISPLAY_VER(i915) >= 11)
5116                 return true;
5117
5118         if (port == PORT_A)
5119                 return false;
5120
5121         if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
5122             DISPLAY_VER(i915) >= 9)
5123                 return true;
5124
5125         return false;
5126 }
5127
5128 static void
5129 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5130 {
5131         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5132         enum port port = dp_to_dig_port(intel_dp)->base.port;
5133
5134         if (!intel_dp_is_edp(intel_dp))
5135                 drm_connector_attach_dp_subconnector_property(connector);
5136
5137         if (!IS_G4X(dev_priv) && port != PORT_A)
5138                 intel_attach_force_audio_property(connector);
5139
5140         intel_attach_broadcast_rgb_property(connector);
5141         if (HAS_GMCH(dev_priv))
5142                 drm_connector_attach_max_bpc_property(connector, 6, 10);
5143         else if (DISPLAY_VER(dev_priv) >= 5)
5144                 drm_connector_attach_max_bpc_property(connector, 6, 12);
5145
5146         /* Register HDMI colorspace for case of lspcon */
5147         if (intel_bios_is_lspcon_present(dev_priv, port)) {
5148                 drm_connector_attach_content_type_property(connector);
5149                 intel_attach_hdmi_colorspace_property(connector);
5150         } else {
5151                 intel_attach_dp_colorspace_property(connector);
5152         }
5153
5154         if (has_gamut_metadata_dip(dev_priv, port))
5155                 drm_connector_attach_hdr_output_metadata_property(connector);
5156
5157         if (intel_dp_is_edp(intel_dp)) {
5158                 u32 allowed_scalers;
5159
5160                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
5161                 if (!HAS_GMCH(dev_priv))
5162                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
5163
5164                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
5165
5166                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
5167
5168         }
5169
5170         if (HAS_VRR(dev_priv))
5171                 drm_connector_attach_vrr_capable_property(connector);
5172 }
5173
5174 static void
5175 intel_edp_add_properties(struct intel_dp *intel_dp)
5176 {
5177         struct intel_connector *connector = intel_dp->attached_connector;
5178         struct drm_i915_private *i915 = to_i915(connector->base.dev);
5179         const struct drm_display_mode *fixed_mode =
5180                 intel_panel_preferred_fixed_mode(connector);
5181
5182         if (!fixed_mode)
5183                 return;
5184
5185         drm_connector_set_panel_orientation_with_quirk(&connector->base,
5186                                                        i915->vbt.orientation,
5187                                                        fixed_mode->hdisplay,
5188                                                        fixed_mode->vdisplay);
5189 }
5190
5191 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5192                                      struct intel_connector *intel_connector)
5193 {
5194         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5195         struct drm_device *dev = &dev_priv->drm;
5196         struct drm_connector *connector = &intel_connector->base;
5197         struct drm_display_mode *fixed_mode;
5198         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
5199         bool has_dpcd;
5200         enum pipe pipe = INVALID_PIPE;
5201         struct edid *edid;
5202
5203         if (!intel_dp_is_edp(intel_dp))
5204                 return true;
5205
5206         /*
5207          * On IBX/CPT we may get here with LVDS already registered. Since the
5208          * driver uses the only internal power sequencer available for both
5209          * eDP and LVDS bail out early in this case to prevent interfering
5210          * with an already powered-on LVDS power sequencer.
5211          */
5212         if (intel_get_lvds_encoder(dev_priv)) {
5213                 drm_WARN_ON(dev,
5214                             !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5215                 drm_info(&dev_priv->drm,
5216                          "LVDS was detected, not registering eDP\n");
5217
5218                 return false;
5219         }
5220
5221         intel_pps_init(intel_dp);
5222
5223         /* Cache DPCD and EDID for edp. */
5224         has_dpcd = intel_edp_init_dpcd(intel_dp);
5225
5226         if (!has_dpcd) {
5227                 /* if this fails, presume the device is a ghost */
5228                 drm_info(&dev_priv->drm,
5229                          "failed to retrieve link info, disabling eDP\n");
5230                 goto out_vdd_off;
5231         }
5232
5233         mutex_lock(&dev->mode_config.mutex);
5234         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5235         if (!edid) {
5236                 /* Fallback to EDID from ACPI OpRegion, if any */
5237                 edid = intel_opregion_get_edid(intel_connector);
5238                 if (edid)
5239                         drm_dbg_kms(&dev_priv->drm,
5240                                     "[CONNECTOR:%d:%s] Using OpRegion EDID\n",
5241                                     connector->base.id, connector->name);
5242         }
5243         if (edid) {
5244                 if (drm_add_edid_modes(connector, edid)) {
5245                         drm_connector_update_edid_property(connector, edid);
5246                 } else {
5247                         kfree(edid);
5248                         edid = ERR_PTR(-EINVAL);
5249                 }
5250         } else {
5251                 edid = ERR_PTR(-ENOENT);
5252         }
5253         intel_connector->edid = edid;
5254
5255         intel_bios_init_panel(dev_priv, &intel_connector->panel,
5256                               encoder->devdata, IS_ERR(edid) ? NULL : edid);
5257
5258         intel_panel_add_edid_fixed_modes(intel_connector,
5259                                          intel_connector->panel.vbt.drrs_type != DRRS_TYPE_NONE,
5260                                          intel_vrr_is_capable(intel_connector));
5261
5262         /* MSO requires information from the EDID */
5263         intel_edp_mso_init(intel_dp);
5264
5265         /* multiply the mode clock and horizontal timings for MSO */
5266         list_for_each_entry(fixed_mode, &intel_connector->panel.fixed_modes, head)
5267                 intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
5268
5269         /* fallback to VBT if available for eDP */
5270         if (!intel_panel_preferred_fixed_mode(intel_connector))
5271                 intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
5272
5273         mutex_unlock(&dev->mode_config.mutex);
5274
5275         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5276                 /*
5277                  * Figure out the current pipe for the initial backlight setup.
5278                  * If the current pipe isn't valid, try the PPS pipe, and if that
5279                  * fails just assume pipe A.
5280                  */
5281                 pipe = vlv_active_pipe(intel_dp);
5282
5283                 if (pipe != PIPE_A && pipe != PIPE_B)
5284                         pipe = intel_dp->pps.pps_pipe;
5285
5286                 if (pipe != PIPE_A && pipe != PIPE_B)
5287                         pipe = PIPE_A;
5288
5289                 drm_dbg_kms(&dev_priv->drm,
5290                             "using pipe %c for initial backlight setup\n",
5291                             pipe_name(pipe));
5292         }
5293
5294         intel_panel_init(intel_connector);
5295
5296         if (!(dev_priv->quirks & QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK))
5297                 intel_connector->panel.backlight.power = intel_pps_backlight_power;
5298         intel_backlight_setup(intel_connector, pipe);
5299
5300         intel_edp_add_properties(intel_dp);
5301
5302         intel_pps_init_late(intel_dp);
5303
5304         return true;
5305
5306 out_vdd_off:
5307         intel_pps_vdd_off_sync(intel_dp);
5308
5309         return false;
5310 }
5311
5312 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
5313 {
5314         struct intel_connector *intel_connector;
5315         struct drm_connector *connector;
5316
5317         intel_connector = container_of(work, typeof(*intel_connector),
5318                                        modeset_retry_work);
5319         connector = &intel_connector->base;
5320         drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", connector->base.id,
5321                     connector->name);
5322
5323         /* Grab the locks before changing connector property*/
5324         mutex_lock(&connector->dev->mode_config.mutex);
5325         /* Set connector link status to BAD and send a Uevent to notify
5326          * userspace to do a modeset.
5327          */
5328         drm_connector_set_link_status_property(connector,
5329                                                DRM_MODE_LINK_STATUS_BAD);
5330         mutex_unlock(&connector->dev->mode_config.mutex);
5331         /* Send Hotplug uevent so userspace can reprobe */
5332         drm_kms_helper_connector_hotplug_event(connector);
5333 }
5334
5335 bool
5336 intel_dp_init_connector(struct intel_digital_port *dig_port,
5337                         struct intel_connector *intel_connector)
5338 {
5339         struct drm_connector *connector = &intel_connector->base;
5340         struct intel_dp *intel_dp = &dig_port->dp;
5341         struct intel_encoder *intel_encoder = &dig_port->base;
5342         struct drm_device *dev = intel_encoder->base.dev;
5343         struct drm_i915_private *dev_priv = to_i915(dev);
5344         enum port port = intel_encoder->port;
5345         enum phy phy = intel_port_to_phy(dev_priv, port);
5346         int type;
5347
5348         /* Initialize the work for modeset in case of link train failure */
5349         INIT_WORK(&intel_connector->modeset_retry_work,
5350                   intel_dp_modeset_retry_work_fn);
5351
5352         if (drm_WARN(dev, dig_port->max_lanes < 1,
5353                      "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
5354                      dig_port->max_lanes, intel_encoder->base.base.id,
5355                      intel_encoder->base.name))
5356                 return false;
5357
5358         intel_dp->reset_link_params = true;
5359         intel_dp->pps.pps_pipe = INVALID_PIPE;
5360         intel_dp->pps.active_pipe = INVALID_PIPE;
5361
5362         /* Preserve the current hw state. */
5363         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
5364         intel_dp->attached_connector = intel_connector;
5365
5366         if (intel_dp_is_port_edp(dev_priv, port)) {
5367                 /*
5368                  * Currently we don't support eDP on TypeC ports, although in
5369                  * theory it could work on TypeC legacy ports.
5370                  */
5371                 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
5372                 type = DRM_MODE_CONNECTOR_eDP;
5373                 intel_encoder->type = INTEL_OUTPUT_EDP;
5374
5375                 /* eDP only on port B and/or C on vlv/chv */
5376                 if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
5377                                       IS_CHERRYVIEW(dev_priv)) &&
5378                                 port != PORT_B && port != PORT_C))
5379                         return false;
5380         } else {
5381                 type = DRM_MODE_CONNECTOR_DisplayPort;
5382         }
5383
5384         intel_dp_set_default_sink_rates(intel_dp);
5385         intel_dp_set_default_max_sink_lane_count(intel_dp);
5386
5387         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5388                 intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
5389
5390         drm_dbg_kms(&dev_priv->drm,
5391                     "Adding %s connector on [ENCODER:%d:%s]\n",
5392                     type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5393                     intel_encoder->base.base.id, intel_encoder->base.name);
5394
5395         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5396         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5397
5398         if (!HAS_GMCH(dev_priv))
5399                 connector->interlace_allowed = true;
5400         connector->doublescan_allowed = 0;
5401
5402         intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
5403
5404         intel_dp_aux_init(intel_dp);
5405
5406         intel_connector_attach_encoder(intel_connector, intel_encoder);
5407
5408         if (HAS_DDI(dev_priv))
5409                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5410         else
5411                 intel_connector->get_hw_state = intel_connector_get_hw_state;
5412
5413         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5414                 intel_dp_aux_fini(intel_dp);
5415                 goto fail;
5416         }
5417
5418         intel_dp_set_source_rates(intel_dp);
5419         intel_dp_set_common_rates(intel_dp);
5420         intel_dp_reset_max_link_params(intel_dp);
5421
5422         /* init MST on ports that can support it */
5423         intel_dp_mst_encoder_init(dig_port,
5424                                   intel_connector->base.base.id);
5425
5426         intel_dp_add_properties(intel_dp, connector);
5427
5428         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
5429                 int ret = intel_dp_hdcp_init(dig_port, intel_connector);
5430                 if (ret)
5431                         drm_dbg_kms(&dev_priv->drm,
5432                                     "HDCP init failed, skipping.\n");
5433         }
5434
5435         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5436          * 0xd.  Failure to do so will result in spurious interrupts being
5437          * generated on the port when a cable is not attached.
5438          */
5439         if (IS_G45(dev_priv)) {
5440                 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
5441                 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
5442                                (temp & ~0xf) | 0xd);
5443         }
5444
5445         intel_dp->frl.is_trained = false;
5446         intel_dp->frl.trained_rate_gbps = 0;
5447
5448         intel_psr_init(intel_dp);
5449
5450         return true;
5451
5452 fail:
5453         drm_connector_cleanup(connector);
5454
5455         return false;
5456 }
5457
5458 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
5459 {
5460         struct intel_encoder *encoder;
5461
5462         if (!HAS_DISPLAY(dev_priv))
5463                 return;
5464
5465         for_each_intel_encoder(&dev_priv->drm, encoder) {
5466                 struct intel_dp *intel_dp;
5467
5468                 if (encoder->type != INTEL_OUTPUT_DDI)
5469                         continue;
5470
5471                 intel_dp = enc_to_intel_dp(encoder);
5472
5473                 if (!intel_dp_mst_source_support(intel_dp))
5474                         continue;
5475
5476                 if (intel_dp->is_mst)
5477                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
5478         }
5479 }
5480
5481 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
5482 {
5483         struct intel_encoder *encoder;
5484
5485         if (!HAS_DISPLAY(dev_priv))
5486                 return;
5487
5488         for_each_intel_encoder(&dev_priv->drm, encoder) {
5489                 struct intel_dp *intel_dp;
5490                 int ret;
5491
5492                 if (encoder->type != INTEL_OUTPUT_DDI)
5493                         continue;
5494
5495                 intel_dp = enc_to_intel_dp(encoder);
5496
5497                 if (!intel_dp_mst_source_support(intel_dp))
5498                         continue;
5499
5500                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
5501                                                      true);
5502                 if (ret) {
5503                         intel_dp->is_mst = false;
5504                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5505                                                         false);
5506                 }
5507         }
5508 }