2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #ifndef __INTEL_DISPLAY_TYPES_H__
27 #define __INTEL_DISPLAY_TYPES_H__
29 #include <linux/async.h>
30 #include <linux/i2c.h>
31 #include <linux/pwm.h>
32 #include <linux/sched/clock.h>
34 #include <drm/drm_atomic.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_dp_dual_mode_helper.h>
37 #include <drm/drm_dp_mst_helper.h>
38 #include <drm/drm_encoder.h>
39 #include <drm/drm_fb_helper.h>
40 #include <drm/drm_probe_helper.h>
41 #include <drm/drm_rect.h>
42 #include <drm/drm_vblank.h>
43 #include <drm/i915_mei_hdcp_interface.h>
44 #include <media/cec-notifier.h>
50 struct __intel_global_objs_state;
53 * Display related stuff
56 /* these are outputs from the chip - integrated only
57 external chips are via DVO or SDVO output */
58 enum intel_output_type {
59 INTEL_OUTPUT_UNUSED = 0,
60 INTEL_OUTPUT_ANALOG = 1,
62 INTEL_OUTPUT_SDVO = 3,
63 INTEL_OUTPUT_LVDS = 4,
64 INTEL_OUTPUT_TVOUT = 5,
65 INTEL_OUTPUT_HDMI = 6,
69 INTEL_OUTPUT_DDI = 10,
70 INTEL_OUTPUT_DP_MST = 11,
73 enum hdmi_force_audio {
74 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
75 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
76 HDMI_AUDIO_AUTO, /* trust EDID */
77 HDMI_AUDIO_ON, /* force turn on HDMI audio */
80 /* "Broadcast RGB" property */
81 enum intel_broadcast_rgb {
82 INTEL_BROADCAST_RGB_AUTO,
83 INTEL_BROADCAST_RGB_FULL,
84 INTEL_BROADCAST_RGB_LIMITED,
87 struct intel_framebuffer {
88 struct drm_framebuffer base;
89 struct intel_frontbuffer *frontbuffer;
90 struct intel_rotation_info rot_info;
92 /* for each plane in the normal GTT view */
96 /* for each plane in the rotated GTT view for no-CCS formats */
99 unsigned int pitch; /* pixels */
104 struct drm_fb_helper helper;
105 struct intel_framebuffer *fb;
106 struct i915_vma *vma;
107 unsigned long vma_flags;
108 async_cookie_t cookie;
111 /* Whether or not fbdev hpd processing is temporarily suspended */
112 bool hpd_suspended : 1;
113 /* Set when a hotplug was received while HPD processing was
116 bool hpd_waiting : 1;
118 /* Protects hpd_suspended */
119 struct mutex hpd_lock;
122 enum intel_hotplug_state {
123 INTEL_HOTPLUG_UNCHANGED,
124 INTEL_HOTPLUG_CHANGED,
128 struct intel_encoder {
129 struct drm_encoder base;
131 enum intel_output_type type;
135 enum intel_hotplug_state (*hotplug)(struct intel_encoder *encoder,
136 struct intel_connector *connector);
137 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
138 struct intel_crtc_state *,
139 struct drm_connector_state *);
140 int (*compute_config)(struct intel_encoder *,
141 struct intel_crtc_state *,
142 struct drm_connector_state *);
143 int (*compute_config_late)(struct intel_encoder *,
144 struct intel_crtc_state *,
145 struct drm_connector_state *);
146 void (*update_prepare)(struct intel_atomic_state *,
147 struct intel_encoder *,
148 struct intel_crtc *);
149 void (*pre_pll_enable)(struct intel_atomic_state *,
150 struct intel_encoder *,
151 const struct intel_crtc_state *,
152 const struct drm_connector_state *);
153 void (*pre_enable)(struct intel_atomic_state *,
154 struct intel_encoder *,
155 const struct intel_crtc_state *,
156 const struct drm_connector_state *);
157 void (*enable)(struct intel_atomic_state *,
158 struct intel_encoder *,
159 const struct intel_crtc_state *,
160 const struct drm_connector_state *);
161 void (*update_complete)(struct intel_atomic_state *,
162 struct intel_encoder *,
163 struct intel_crtc *);
164 void (*disable)(struct intel_atomic_state *,
165 struct intel_encoder *,
166 const struct intel_crtc_state *,
167 const struct drm_connector_state *);
168 void (*post_disable)(struct intel_atomic_state *,
169 struct intel_encoder *,
170 const struct intel_crtc_state *,
171 const struct drm_connector_state *);
172 void (*post_pll_disable)(struct intel_atomic_state *,
173 struct intel_encoder *,
174 const struct intel_crtc_state *,
175 const struct drm_connector_state *);
176 void (*update_pipe)(struct intel_atomic_state *,
177 struct intel_encoder *,
178 const struct intel_crtc_state *,
179 const struct drm_connector_state *);
180 /* Read out the current hw state of this connector, returning true if
181 * the encoder is active. If the encoder is enabled it also set the pipe
182 * it is connected to in the pipe parameter. */
183 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
184 /* Reconstructs the equivalent mode flags for the current hardware
185 * state. This must be called _after_ display->get_pipe_config has
186 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
187 * be set correctly before calling this function. */
188 void (*get_config)(struct intel_encoder *,
189 struct intel_crtc_state *pipe_config);
192 * Optional hook called during init/resume to sync any state
193 * stored in the encoder (eg. DP link parameters) wrt. the HW state.
195 void (*sync_state)(struct intel_encoder *encoder,
196 const struct intel_crtc_state *crtc_state);
199 * Optional hook, returning true if this encoder allows a fastset
200 * during the initial commit, false otherwise.
202 bool (*initial_fastset_check)(struct intel_encoder *encoder,
203 struct intel_crtc_state *crtc_state);
206 * Acquires the power domains needed for an active encoder during
207 * hardware state readout.
209 void (*get_power_domains)(struct intel_encoder *encoder,
210 struct intel_crtc_state *crtc_state);
212 * Called during system suspend after all pending requests for the
213 * encoder are flushed (for example for DP AUX transactions) and
214 * device interrupts are disabled.
216 void (*suspend)(struct intel_encoder *);
218 * Called during system reboot/shutdown after all the
219 * encoders have been disabled and suspended.
221 void (*shutdown)(struct intel_encoder *encoder);
222 enum hpd_pin hpd_pin;
223 enum intel_display_power_domain power_domain;
224 /* for communication with audio component; protected by av_mutex */
225 const struct drm_connector *audio_connector;
228 struct intel_panel_bl_funcs {
229 /* Connector and platform specific backlight functions */
230 int (*setup)(struct intel_connector *connector, enum pipe pipe);
231 u32 (*get)(struct intel_connector *connector, enum pipe pipe);
232 void (*set)(const struct drm_connector_state *conn_state, u32 level);
233 void (*disable)(const struct drm_connector_state *conn_state, u32 level);
234 void (*enable)(const struct intel_crtc_state *crtc_state,
235 const struct drm_connector_state *conn_state, u32 level);
236 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
240 struct drm_display_mode *fixed_mode;
241 struct drm_display_mode *downclock_mode;
250 bool combination_mode; /* gen 2/4 only */
252 bool alternate_pwm_increment; /* lpt+ */
258 bool util_pin_active_low; /* bxt+ */
259 u8 controller; /* bxt+ only */
260 struct pwm_device *pwm;
261 struct pwm_state pwm_state;
273 struct backlight_device *device;
275 const struct intel_panel_bl_funcs *funcs;
276 const struct intel_panel_bl_funcs *pwm_funcs;
277 void (*power)(struct intel_connector *, bool enable);
281 struct intel_digital_port;
283 enum check_link_response {
284 HDCP_LINK_PROTECTED = 0,
285 HDCP_TOPOLOGY_CHANGE,
286 HDCP_LINK_INTEGRITY_FAILURE,
291 * This structure serves as a translation layer between the generic HDCP code
292 * and the bus-specific code. What that means is that HDCP over HDMI differs
293 * from HDCP over DP, so to account for these differences, we need to
294 * communicate with the receiver through this shim.
296 * For completeness, the 2 buses differ in the following ways:
298 * HDCP registers on the receiver are set via DP AUX for DP, and
299 * they are set via DDC for HDMI.
300 * - Receiver register offsets
301 * The offsets of the registers are different for DP vs. HDMI
302 * - Receiver register masks/offsets
303 * For instance, the ready bit for the KSV fifo is in a different
304 * place on DP vs HDMI
305 * - Receiver register names
306 * Seriously. In the DP spec, the 16-bit register containing
307 * downstream information is called BINFO, on HDMI it's called
308 * BSTATUS. To confuse matters further, DP has a BSTATUS register
309 * with a completely different definition.
311 * On HDMI, the ksv fifo is read all at once, whereas on DP it must
312 * be read 3 keys at a time
314 * Since Aksv is hidden in hardware, there's different procedures
315 * to send it over DP AUX vs DDC
317 struct intel_hdcp_shim {
318 /* Outputs the transmitter's An and Aksv values to the receiver. */
319 int (*write_an_aksv)(struct intel_digital_port *dig_port, u8 *an);
321 /* Reads the receiver's key selection vector */
322 int (*read_bksv)(struct intel_digital_port *dig_port, u8 *bksv);
325 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
326 * definitions are the same in the respective specs, but the names are
327 * different. Call it BSTATUS since that's the name the HDMI spec
328 * uses and it was there first.
330 int (*read_bstatus)(struct intel_digital_port *dig_port,
333 /* Determines whether a repeater is present downstream */
334 int (*repeater_present)(struct intel_digital_port *dig_port,
335 bool *repeater_present);
337 /* Reads the receiver's Ri' value */
338 int (*read_ri_prime)(struct intel_digital_port *dig_port, u8 *ri);
340 /* Determines if the receiver's KSV FIFO is ready for consumption */
341 int (*read_ksv_ready)(struct intel_digital_port *dig_port,
344 /* Reads the ksv fifo for num_downstream devices */
345 int (*read_ksv_fifo)(struct intel_digital_port *dig_port,
346 int num_downstream, u8 *ksv_fifo);
348 /* Reads a 32-bit part of V' from the receiver */
349 int (*read_v_prime_part)(struct intel_digital_port *dig_port,
352 /* Enables HDCP signalling on the port */
353 int (*toggle_signalling)(struct intel_digital_port *dig_port,
354 enum transcoder cpu_transcoder,
357 /* Enable/Disable stream encryption on DP MST Transport Link */
358 int (*stream_encryption)(struct intel_connector *connector,
361 /* Ensures the link is still protected */
362 bool (*check_link)(struct intel_digital_port *dig_port,
363 struct intel_connector *connector);
365 /* Detects panel's hdcp capability. This is optional for HDMI. */
366 int (*hdcp_capable)(struct intel_digital_port *dig_port,
369 /* HDCP adaptation(DP/HDMI) required on the port */
370 enum hdcp_wired_protocol protocol;
372 /* Detects whether sink is HDCP2.2 capable */
373 int (*hdcp_2_2_capable)(struct intel_digital_port *dig_port,
376 /* Write HDCP2.2 messages */
377 int (*write_2_2_msg)(struct intel_digital_port *dig_port,
378 void *buf, size_t size);
380 /* Read HDCP2.2 messages */
381 int (*read_2_2_msg)(struct intel_digital_port *dig_port,
382 u8 msg_id, void *buf, size_t size);
385 * Implementation of DP HDCP2.2 Errata for the communication of stream
386 * type to Receivers. In DP HDCP2.2 Stream type is one of the input to
387 * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI.
389 int (*config_stream_type)(struct intel_digital_port *dig_port,
390 bool is_repeater, u8 type);
392 /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */
393 int (*stream_2_2_encryption)(struct intel_connector *connector,
396 /* HDCP2.2 Link Integrity Check */
397 int (*check_2_2_link)(struct intel_digital_port *dig_port,
398 struct intel_connector *connector);
402 const struct intel_hdcp_shim *shim;
403 /* Mutex for hdcp state of the connector */
406 struct delayed_work check_work;
407 struct work_struct prop_work;
409 /* HDCP1.4 Encryption status */
412 /* HDCP2.2 related definitions */
413 /* Flag indicates whether this connector supports HDCP2.2 or not. */
414 bool hdcp2_supported;
416 /* HDCP2.2 Encryption status */
417 bool hdcp2_encrypted;
420 * Content Stream Type defined by content owner. TYPE0(0x0) content can
421 * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1)
422 * content can flow only through a link protected by HDCP2.2.
430 * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT.
431 * Incremented after processing the RepeaterAuth_Send_ReceiverID_List.
432 * When it rolls over re-auth has to be triggered.
437 * Count of RepeaterAuth_Stream_Manage msg propagated.
438 * Initialized to 0 on AKE_INIT. Incremented after every successful
439 * transmission of RepeaterAuth_Stream_Manage message. When it rolls
440 * over re-Auth has to be triggered.
445 * Work queue to signal the CP_IRQ. Used for the waiters to read the
446 * available information from HDCP DP sink.
448 wait_queue_head_t cp_irq_queue;
449 atomic_t cp_irq_count;
450 int cp_irq_count_cached;
453 * HDCP register access for gen12+ need the transcoder associated.
454 * Transcoder attached to the connector could be changed at modeset.
455 * Hence caching the transcoder here.
457 enum transcoder cpu_transcoder;
458 /* Only used for DP MST stream encryption */
459 enum transcoder stream_transcoder;
462 struct intel_connector {
463 struct drm_connector base;
465 * The fixed encoder this connector is connected to.
467 struct intel_encoder *encoder;
469 /* ACPI device id for ACPI and driver cooperation */
472 /* Reads out the current hw, returning true if the connector is enabled
473 * and active (i.e. dpms ON state). */
474 bool (*get_hw_state)(struct intel_connector *);
476 /* Panel info for eDP and LVDS */
477 struct intel_panel panel;
479 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
481 struct edid *detect_edid;
483 /* Number of times hotplug detection was tried after an HPD interrupt */
486 /* since POLL and HPD connectors may use the same HPD line keep the native
487 state of connector->polled in case hotplug storm detection changes it */
490 struct drm_dp_mst_port *port;
492 struct intel_dp *mst_port;
494 /* Work struct to schedule a uevent on link train failure */
495 struct work_struct modeset_retry_work;
497 struct intel_hdcp hdcp;
500 struct intel_digital_connector_state {
501 struct drm_connector_state base;
503 enum hdmi_force_audio force_audio;
507 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
521 struct intel_atomic_state {
522 struct drm_atomic_state base;
524 intel_wakeref_t wakeref;
526 struct __intel_global_objs_state *global_objs;
529 bool dpll_set, modeset;
531 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
534 * Current watermarks can't be trusted during hardware readout, so
535 * don't bother calculating intermediate watermarks.
537 bool skip_intermediate_wm;
539 bool rps_interactive;
541 struct i915_sw_fence commit_ready;
543 struct llist_node freed;
546 struct intel_plane_state {
547 struct drm_plane_state uapi;
550 * actual hardware state, the state we program to the hardware.
551 * The following members are used to verify the hardware state:
552 * During initial hw readout, they need to be copied from uapi.
555 struct drm_crtc *crtc;
556 struct drm_framebuffer *fb;
559 u16 pixel_blend_mode;
560 unsigned int rotation;
561 enum drm_color_encoding color_encoding;
562 enum drm_color_range color_range;
563 enum drm_scaling_filter scaling_filter;
566 struct i915_ggtt_view view;
567 struct i915_vma *vma;
569 #define PLANE_HAS_FENCE BIT(0)
575 * bytes for 0/180 degree rotation
576 * pixels for 90/270 degree rotation
582 /* plane control register */
585 /* plane color control register */
588 /* chroma upsampler control register */
593 * = -1 : not using a scaler
594 * >= 0 : using a scalers
596 * plane requiring a scaler:
597 * - During check_plane, its bit is set in
598 * crtc_state->scaler_state.scaler_users by calling helper function
599 * update_scaler_plane.
600 * - scaler_id indicates the scaler it got assigned.
602 * plane doesn't require a scaler:
603 * - this can happen when scaling is no more required or plane simply
605 * - During check_plane, corresponding bit is reset in
606 * crtc_state->scaler_state.scaler_users by calling helper function
607 * update_scaler_plane.
612 * planar_linked_plane:
614 * ICL planar formats require 2 planes that are updated as pairs.
615 * This member is used to make sure the other plane is also updated
616 * when required, and for update_slave() to find the correct
617 * plane_state to pass as argument.
619 struct intel_plane *planar_linked_plane;
623 * If set don't update use the linked plane's state for updating
624 * this plane during atomic commit with the update_slave() callback.
626 * It's also used by the watermark code to ignore wm calculations on
627 * this plane. They're calculated by the linked plane's wm code.
631 struct drm_intel_sprite_colorkey ckey;
633 struct drm_rect psr2_sel_fetch_area;
636 struct intel_initial_plane_config {
637 struct intel_framebuffer *fb;
638 struct i915_vma *vma;
645 struct intel_scaler {
650 struct intel_crtc_scaler_state {
651 #define SKL_NUM_SCALERS 2
652 struct intel_scaler scalers[SKL_NUM_SCALERS];
655 * scaler_users: keeps track of users requesting scalers on this crtc.
657 * If a bit is set, a user is using a scaler.
658 * Here user can be a plane or crtc as defined below:
659 * bits 0-30 - plane (bit position is index from drm_plane_index)
662 * Instead of creating a new index to cover planes and crtc, using
663 * existing drm_plane_index for planes which is well less than 31
664 * planes and bit 31 for crtc. This should be fine to cover all
667 * intel_atomic_setup_scalers will setup available scalers to users
668 * requesting scalers. It will gracefully fail if request exceeds
671 #define SKL_CRTC_INDEX 31
672 unsigned scaler_users;
674 /* scaler used by crtc for panel fitting purpose */
678 /* {crtc,crtc_state}->mode_flags */
679 /* Flag to get scanline using frame time stamps */
680 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
681 /* Flag to use the scanline counter instead of the pixel counter */
682 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
684 * TE0 or TE1 flag is set if the crtc has a DSI encoder which
685 * is operating in command mode.
686 * Flag to use TE from DSI0 instead of VBI in command mode
688 #define I915_MODE_FLAG_DSI_USE_TE0 (1<<3)
689 /* Flag to use TE from DSI1 instead of VBI in command mode */
690 #define I915_MODE_FLAG_DSI_USE_TE1 (1<<4)
691 /* Flag to indicate mipi dsi periodic command mode where we do not get TE */
692 #define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5)
694 struct intel_wm_level {
702 struct intel_pipe_wm {
703 struct intel_wm_level wm[5];
706 bool sprites_enabled;
710 struct skl_wm_level {
719 struct skl_plane_wm {
720 struct skl_wm_level wm[8];
721 struct skl_wm_level uv_wm[8];
722 struct skl_wm_level trans_wm;
723 struct skl_wm_level sagv_wm0;
728 struct skl_plane_wm planes[I915_MAX_PLANES];
735 VLV_WM_LEVEL_DDR_DVFS,
739 struct vlv_wm_state {
740 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
741 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
746 struct vlv_fifo_state {
747 u16 plane[I915_MAX_PLANES];
757 struct g4x_wm_state {
758 struct g4x_pipe_wm wm;
760 struct g4x_sr_wm hpll;
766 struct intel_crtc_wm_state {
770 * The "raw" watermark values produced by the formula
771 * given the plane's current state. They do not consider
772 * how much FIFO is actually allocated for each plane.
775 * The "optimal" watermark values given the current
776 * state of the planes and the amount of FIFO
777 * allocated to each, ignoring any previous state
781 * The "intermediate" watermark values when transitioning
782 * between the old and new "optimal" values. Used when
783 * the watermark registers are single buffered and hence
784 * their state changes asynchronously with regards to the
785 * actual plane registers. These are essentially the
786 * worst case combination of the old and new "optimal"
787 * watermarks, which are therefore safe to use when the
788 * plane is in either its old or new state.
791 struct intel_pipe_wm intermediate;
792 struct intel_pipe_wm optimal;
796 struct skl_pipe_wm raw;
797 /* gen9+ only needs 1-step wm programming */
798 struct skl_pipe_wm optimal;
799 struct skl_ddb_entry ddb;
800 struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
801 struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
805 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS]; /* not inverted */
806 struct vlv_wm_state intermediate; /* inverted */
807 struct vlv_wm_state optimal; /* inverted */
808 struct vlv_fifo_state fifo_state;
812 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
813 struct g4x_wm_state intermediate;
814 struct g4x_wm_state optimal;
819 * Platforms with two-step watermark programming will need to
820 * update watermark programming post-vblank to switch from the
821 * safe intermediate watermarks to the optimal final
824 bool need_postvbl_update;
827 enum intel_output_format {
828 INTEL_OUTPUT_FORMAT_INVALID,
829 INTEL_OUTPUT_FORMAT_RGB,
830 INTEL_OUTPUT_FORMAT_YCBCR420,
831 INTEL_OUTPUT_FORMAT_YCBCR444,
834 struct intel_crtc_state {
836 * uapi (drm) state. This is the software state shown to userspace.
837 * In particular, the following members are used for bookkeeping:
845 struct drm_crtc_state uapi;
848 * actual hardware state, the state we program to the hardware.
849 * The following members are used to verify the hardware state:
852 * - mode / pipe_mode / adjusted_mode
853 * - color property blobs.
855 * During initial hw readout, they need to be copied to uapi.
857 * Bigjoiner will allow a transcoder mode that spans 2 pipes;
858 * Use the pipe_mode for calculations like watermarks, pipe
859 * scaler, and bandwidth.
861 * Use adjusted_mode for things that need to know the full
862 * mode on the transcoder, which spans all pipes.
866 struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
867 struct drm_display_mode mode, pipe_mode, adjusted_mode;
868 enum drm_scaling_filter scaling_filter;
872 * quirks - bitfield with hw state readout quirks
874 * For various reasons the hw state readout code might not be able to
875 * completely faithfully read out the current state. These cases are
876 * tracked with quirk flags so that fastboot and state checker can act
879 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
880 #define PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE (1<<1) /* bigjoiner slave, partial readout */
881 unsigned long quirks;
883 unsigned fb_bits; /* framebuffers to flip */
884 bool update_pipe; /* can a fast modeset be performed? */
886 bool update_wm_pre, update_wm_post; /* watermarks are updated */
887 bool fifo_changed; /* FIFO split is changed */
889 bool inherited; /* state inherited from BIOS? */
891 /* Pipe source size (ie. panel fitter input size)
892 * All planes will be positioned inside this space,
893 * and get clipped at the edges. */
894 int pipe_src_w, pipe_src_h;
897 * Pipe pixel rate, adjusted for
898 * panel fitter/pipe scaler downscaling.
900 unsigned int pixel_rate;
902 /* Whether to set up the PCH/FDI. Note that we never allow sharing
903 * between pch encoders and cpu encoders. */
904 bool has_pch_encoder;
906 /* Are we sending infoframes on the attached port */
909 /* CPU Transcoder for the pipe. Currently this can only differ from the
910 * pipe on Haswell and later (where we have a special eDP transcoder)
911 * and Broxton (where we have special DSI transcoders). */
912 enum transcoder cpu_transcoder;
915 * Use reduced/limited/broadcast rbg range, compressing from the full
916 * range fed into the crtcs.
918 bool limited_color_range;
920 /* Bitmask of encoder types (enum intel_output_type)
921 * driven by the pipe.
923 unsigned int output_types;
925 /* Whether we should send NULL infoframes. Required for audio. */
928 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
929 * has_dp_encoder is set. */
933 * Enable dithering, used when the selected pipe bpp doesn't match the
939 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
940 * compliance video pattern tests.
941 * Disable dither only if it is a compliance test request for
944 bool dither_force_disable;
946 /* Controls for the clock computation, to override various stages. */
949 /* SDVO TV has a bunch of special case. To make multifunction encoders
950 * work correctly, we need to track this at runtime.*/
954 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
955 * required. This is set in the 2nd loop of calling encoder's
956 * ->compute_config if the first pick doesn't work out.
960 /* Settings for the intel dpll used on pretty much everything but
964 /* Selected dpll when shared or NULL. */
965 struct intel_shared_dpll *shared_dpll;
967 /* Actual register state of the dpll, for shared dpll cross-checking. */
968 struct intel_dpll_hw_state dpll_hw_state;
971 * ICL reserved DPLLs for the CRTC/port. The active PLL is selected by
972 * setting shared_dpll and dpll_hw_state to one of these reserved ones.
974 struct icl_port_dpll {
975 struct intel_shared_dpll *pll;
976 struct intel_dpll_hw_state hw_state;
977 } icl_port_dplls[ICL_PORT_DPLL_COUNT];
979 /* DSI PLL registers */
985 struct intel_link_m_n dp_m_n;
987 /* m2_n2 for eDP downclock */
988 struct intel_link_m_n dp_m2_n2;
993 bool enable_psr2_sel_fetch;
997 * Frequence the dpll for the port should run at. Differs from the
998 * adjusted dotclock e.g. for DP or 10/12bpc hdmi mode. This is also
999 * already multiplied by pixel_multiplier.
1003 /* Used by SDVO (and if we ever fix it, HDMI). */
1004 unsigned pixel_multiplier;
1006 /* I915_MODE_FLAG_* */
1012 * Used by platforms having DP/HDMI PHY with programmable lane
1013 * latency optimization.
1015 u8 lane_lat_optim_mask;
1017 /* minimum acceptable voltage level */
1018 u8 min_voltage_level;
1020 /* Panel fitter controls for gen2-gen4 + VLV */
1024 u32 lvds_border_bits;
1027 /* Panel fitter placement and size for Ironlake+ */
1029 struct drm_rect dst;
1034 /* FDI configuration, only valid if has_pch_encoder is set. */
1036 struct intel_link_m_n fdi_m_n;
1048 struct intel_crtc_scaler_state scaler_state;
1050 /* w/a for waiting 2 vblanks during crtc enable */
1051 enum pipe hsw_workaround_pipe;
1053 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
1056 struct intel_crtc_wm_state wm;
1058 int min_cdclk[I915_MAX_PLANES];
1060 u32 data_rate[I915_MAX_PLANES];
1062 /* FIXME unify with data_rate[] */
1063 u64 plane_data_rate[I915_MAX_PLANES];
1064 u64 uv_plane_data_rate[I915_MAX_PLANES];
1066 /* Gamma mode programmed on the pipe */
1070 /* CSC mode programmed on the pipe */
1077 /* bitmask of logically enabled planes (enum plane_id) */
1080 /* bitmask of actually visible planes (enum plane_id) */
1085 /* bitmask of planes that will be updated during the commit */
1091 union hdmi_infoframe avi;
1092 union hdmi_infoframe spd;
1093 union hdmi_infoframe hdmi;
1094 union hdmi_infoframe drm;
1095 struct drm_dp_vsc_sdp vsc;
1098 /* HDMI scrambling status */
1099 bool hdmi_scrambling;
1101 /* HDMI High TMDS char rate ratio */
1102 bool hdmi_high_tmds_clock_ratio;
1104 /* Output format RGB/YCBCR etc */
1105 enum intel_output_format output_format;
1107 /* enable pipe gamma? */
1110 /* enable pipe csc? */
1113 /* enable pipe big joiner? */
1116 /* big joiner slave crtc? */
1117 bool bigjoiner_slave;
1119 /* linked crtc for bigjoiner, either slave or master */
1120 struct intel_crtc *bigjoiner_linked_crtc;
1122 /* Display Stream compression state */
1124 bool compression_enable;
1128 struct drm_dsc_config config;
1131 /* HSW+ linetime watermarks */
1135 /* Forward Error correction State */
1138 /* Pointer to master transcoder in case of tiled displays */
1139 enum transcoder master_transcoder;
1141 /* Bitmask to indicate slaves attached */
1142 u8 sync_mode_slaves_mask;
1144 /* Only valid on TGL+ */
1145 enum transcoder mst_master_transcoder;
1147 /* For DSB related info */
1148 struct intel_dsb *dsb;
1150 u32 psr2_man_track_ctl;
1153 enum intel_pipe_crc_source {
1154 INTEL_PIPE_CRC_SOURCE_NONE,
1155 INTEL_PIPE_CRC_SOURCE_PLANE1,
1156 INTEL_PIPE_CRC_SOURCE_PLANE2,
1157 INTEL_PIPE_CRC_SOURCE_PLANE3,
1158 INTEL_PIPE_CRC_SOURCE_PLANE4,
1159 INTEL_PIPE_CRC_SOURCE_PLANE5,
1160 INTEL_PIPE_CRC_SOURCE_PLANE6,
1161 INTEL_PIPE_CRC_SOURCE_PLANE7,
1162 INTEL_PIPE_CRC_SOURCE_PIPE,
1163 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1164 INTEL_PIPE_CRC_SOURCE_TV,
1165 INTEL_PIPE_CRC_SOURCE_DP_B,
1166 INTEL_PIPE_CRC_SOURCE_DP_C,
1167 INTEL_PIPE_CRC_SOURCE_DP_D,
1168 INTEL_PIPE_CRC_SOURCE_AUTO,
1169 INTEL_PIPE_CRC_SOURCE_MAX,
1172 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1173 struct intel_pipe_crc {
1176 enum intel_pipe_crc_source source;
1180 struct drm_crtc base;
1183 * Whether the crtc and the connected output pipeline is active. Implies
1184 * that crtc->enabled is set, i.e. the current mode configuration has
1185 * some outputs connected to this crtc.
1190 /* I915_MODE_FLAG_* */
1193 struct intel_display_power_domain_set enabled_power_domains;
1194 struct intel_overlay *overlay;
1196 struct intel_crtc_state *config;
1198 /* Access to these should be protected by dev_priv->irq_lock. */
1199 bool cpu_fifo_underrun_disabled;
1200 bool pch_fifo_underrun_disabled;
1202 /* per-pipe watermark state */
1204 /* watermarks currently being used */
1206 struct intel_pipe_wm ilk;
1207 struct vlv_wm_state vlv;
1208 struct g4x_wm_state g4x;
1212 int scanline_offset;
1215 unsigned start_vbl_count;
1216 ktime_t start_vbl_time;
1217 int min_vbl, max_vbl;
1219 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
1225 unsigned int times[17]; /* [1us, 16ms] */
1230 /* scalers available on this crtc */
1233 #ifdef CONFIG_DEBUG_FS
1234 struct intel_pipe_crc pipe_crc;
1238 struct intel_plane {
1239 struct drm_plane base;
1240 enum i9xx_plane_id i9xx_plane;
1245 bool need_async_flip_disable_wa;
1246 u32 frontbuffer_bit;
1249 u32 base, cntl, size;
1253 * NOTE: Do not place new plane state fields here (e.g., when adding
1254 * new plane properties). New runtime state should now be placed in
1255 * the intel_plane_state structure and accessed via plane_state.
1258 int (*min_width)(const struct drm_framebuffer *fb,
1260 unsigned int rotation);
1261 int (*max_width)(const struct drm_framebuffer *fb,
1263 unsigned int rotation);
1264 int (*max_height)(const struct drm_framebuffer *fb,
1266 unsigned int rotation);
1267 unsigned int (*max_stride)(struct intel_plane *plane,
1268 u32 pixel_format, u64 modifier,
1269 unsigned int rotation);
1270 void (*update_plane)(struct intel_plane *plane,
1271 const struct intel_crtc_state *crtc_state,
1272 const struct intel_plane_state *plane_state);
1273 void (*disable_plane)(struct intel_plane *plane,
1274 const struct intel_crtc_state *crtc_state);
1275 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1276 int (*check_plane)(struct intel_crtc_state *crtc_state,
1277 struct intel_plane_state *plane_state);
1278 int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
1279 const struct intel_plane_state *plane_state);
1280 void (*async_flip)(struct intel_plane *plane,
1281 const struct intel_crtc_state *crtc_state,
1282 const struct intel_plane_state *plane_state,
1284 void (*enable_flip_done)(struct intel_plane *plane);
1285 void (*disable_flip_done)(struct intel_plane *plane);
1288 struct intel_watermark_params {
1296 struct cxsr_latency {
1297 bool is_desktop : 1;
1302 u16 display_hpll_disable;
1304 u16 cursor_hpll_disable;
1307 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1308 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1309 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi)
1310 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1311 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1312 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1313 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1314 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi)
1315 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1318 i915_reg_t hdmi_reg;
1321 enum drm_dp_dual_mode_type type;
1326 struct intel_connector *attached_connector;
1327 struct cec_notifier *cec_notifier;
1330 struct intel_dp_mst_encoder;
1332 * enum link_m_n_set:
1333 * When platform provides two set of M_N registers for dp, we can
1334 * program them and switch between them incase of DRRS.
1335 * But When only one such register is provided, we have to program the
1336 * required divider value on that registers itself based on the DRRS state.
1338 * M1_N1 : Program dp_m_n on M1_N1 registers
1339 * dp_m2_n2 on M2_N2 registers (If supported)
1341 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
1342 * M2_N2 registers are not supported
1346 /* Sets the m1_n1 and m2_n2 */
1351 struct intel_dp_compliance_data {
1354 u16 hdisplay, vdisplay;
1356 struct drm_dp_phy_test_params phytest;
1359 struct intel_dp_compliance {
1360 unsigned long test_type;
1361 struct intel_dp_compliance_data test_data;
1367 struct intel_dp_pcon_frl {
1369 int trained_rate_gbps;
1373 int panel_power_up_delay;
1374 int panel_power_down_delay;
1375 int panel_power_cycle_delay;
1376 int backlight_on_delay;
1377 int backlight_off_delay;
1378 struct delayed_work panel_vdd_work;
1379 bool want_panel_vdd;
1380 unsigned long last_power_on;
1381 unsigned long last_backlight_off;
1382 ktime_t panel_power_off_time;
1383 intel_wakeref_t vdd_wakeref;
1386 * Pipe whose power sequencer is currently locked into
1387 * this port. Only relevant on VLV/CHV.
1391 * Pipe currently driving the port. Used for preventing
1392 * the use of the PPS for any pipe currentrly driving
1393 * external DP as that will mess things up on VLV.
1395 enum pipe active_pipe;
1397 * Set if the sequencer may be reset due to a power transition,
1398 * requiring a reinitialization. Only relevant on BXT.
1401 struct edp_power_seq pps_delays;
1405 i915_reg_t output_reg;
1413 bool reset_link_params;
1414 bool use_max_params;
1415 u8 dpcd[DP_RECEIVER_CAP_SIZE];
1416 u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1417 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1418 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1419 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
1420 u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE];
1421 u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE];
1423 u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE];
1425 int num_source_rates;
1426 const int *source_rates;
1427 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1429 int sink_rates[DP_MAX_SUPPORTED_RATES];
1430 bool use_rate_select;
1431 /* intersection of source and sink rates */
1432 int num_common_rates;
1433 int common_rates[DP_MAX_SUPPORTED_RATES];
1434 /* Max lane count for the current link */
1435 int max_link_lane_count;
1436 /* Max rate for the current link */
1438 /* sink or branch descriptor */
1439 struct drm_dp_desc desc;
1440 struct drm_dp_aux aux;
1441 u32 aux_busy_last_status;
1444 struct intel_pps pps;
1446 bool can_mst; /* this port supports mst */
1448 int active_mst_links;
1450 /* connector directly attached - won't be use for modeset in mst world */
1451 struct intel_connector *attached_connector;
1453 /* mst connector list */
1454 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1455 struct drm_dp_mst_topology_mgr mst_mgr;
1457 u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1459 * This function returns the value we have to program the AUX_CTL
1460 * register with to kick off an AUX transaction.
1462 u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
1463 u32 aux_clock_divider);
1465 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1466 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1468 /* This is called before a link training is starterd */
1469 void (*prepare_link_retrain)(struct intel_dp *intel_dp,
1470 const struct intel_crtc_state *crtc_state);
1471 void (*set_link_train)(struct intel_dp *intel_dp,
1472 const struct intel_crtc_state *crtc_state,
1474 void (*set_idle_link_train)(struct intel_dp *intel_dp,
1475 const struct intel_crtc_state *crtc_state);
1476 void (*set_signal_levels)(struct intel_dp *intel_dp,
1477 const struct intel_crtc_state *crtc_state);
1479 u8 (*preemph_max)(struct intel_dp *intel_dp);
1480 u8 (*voltage_max)(struct intel_dp *intel_dp,
1481 const struct intel_crtc_state *crtc_state);
1483 /* Displayport compliance testing */
1484 struct intel_dp_compliance compliance;
1486 /* Downstream facing port caps */
1488 int min_tmds_clock, max_tmds_clock;
1490 int pcon_max_frl_bw;
1492 bool ycbcr_444_to_420;
1496 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1497 struct pm_qos_request pm_qos;
1499 /* Display stream compression testing */
1505 struct intel_dp_pcon_frl frl;
1508 enum lspcon_vendor {
1510 LSPCON_VENDOR_PARADE
1513 struct intel_lspcon {
1516 enum drm_lspcon_mode mode;
1517 enum lspcon_vendor vendor;
1520 struct intel_digital_port {
1521 struct intel_encoder base;
1522 u32 saved_port_bits;
1524 struct intel_hdmi hdmi;
1525 struct intel_lspcon lspcon;
1526 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1527 bool release_cl2_override;
1529 /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1531 enum intel_display_power_domain ddi_io_power_domain;
1532 intel_wakeref_t ddi_io_wakeref;
1533 intel_wakeref_t aux_wakeref;
1534 struct mutex tc_lock; /* protects the TypeC port mode */
1535 intel_wakeref_t tc_lock_wakeref;
1536 int tc_link_refcount;
1537 bool tc_legacy_port:1;
1538 char tc_port_name[8];
1539 enum tc_port_mode tc_mode;
1540 enum phy_fia tc_phy_fia;
1543 /* protects num_hdcp_streams reference count, hdcp_port_data and hdcp_auth_status */
1544 struct mutex hdcp_mutex;
1545 /* the number of pipes using HDCP signalling out of this port */
1546 unsigned int num_hdcp_streams;
1547 /* port HDCP auth status */
1548 bool hdcp_auth_status;
1549 /* HDCP port data need to pass to security f/w */
1550 struct hdcp_port_data hdcp_port_data;
1552 void (*write_infoframe)(struct intel_encoder *encoder,
1553 const struct intel_crtc_state *crtc_state,
1555 const void *frame, ssize_t len);
1556 void (*read_infoframe)(struct intel_encoder *encoder,
1557 const struct intel_crtc_state *crtc_state,
1559 void *frame, ssize_t len);
1560 void (*set_infoframes)(struct intel_encoder *encoder,
1562 const struct intel_crtc_state *crtc_state,
1563 const struct drm_connector_state *conn_state);
1564 u32 (*infoframes_enabled)(struct intel_encoder *encoder,
1565 const struct intel_crtc_state *pipe_config);
1566 bool (*connected)(struct intel_encoder *encoder);
1569 struct intel_dp_mst_encoder {
1570 struct intel_encoder base;
1572 struct intel_digital_port *primary;
1573 struct intel_connector *connector;
1576 static inline enum dpio_channel
1577 vlv_dig_port_to_channel(struct intel_digital_port *dig_port)
1579 switch (dig_port->base.port) {
1590 static inline enum dpio_phy
1591 vlv_dig_port_to_phy(struct intel_digital_port *dig_port)
1593 switch (dig_port->base.port) {
1604 static inline enum dpio_channel
1605 vlv_pipe_to_channel(enum pipe pipe)
1618 static inline struct intel_crtc *
1619 intel_get_first_crtc(struct drm_i915_private *dev_priv)
1621 return to_intel_crtc(drm_crtc_from_index(&dev_priv->drm, 0));
1624 static inline struct intel_crtc *
1625 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1627 /* pipe_to_crtc_mapping may have hole on any of 3 display pipe system */
1628 drm_WARN_ON(&dev_priv->drm,
1629 !(INTEL_INFO(dev_priv)->pipe_mask & BIT(pipe)));
1630 return dev_priv->pipe_to_crtc_mapping[pipe];
1633 static inline struct intel_crtc *
1634 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1636 return dev_priv->plane_to_crtc_mapping[plane];
1639 struct intel_load_detect_pipe {
1640 struct drm_atomic_state *restore_state;
1643 static inline struct intel_encoder *
1644 intel_attached_encoder(struct intel_connector *connector)
1646 return connector->encoder;
1649 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1651 switch (encoder->type) {
1652 case INTEL_OUTPUT_DDI:
1653 case INTEL_OUTPUT_DP:
1654 case INTEL_OUTPUT_EDP:
1655 case INTEL_OUTPUT_HDMI:
1662 static inline bool intel_encoder_is_mst(struct intel_encoder *encoder)
1664 return encoder->type == INTEL_OUTPUT_DP_MST;
1667 static inline struct intel_dp_mst_encoder *
1668 enc_to_mst(struct intel_encoder *encoder)
1670 return container_of(&encoder->base, struct intel_dp_mst_encoder,
1674 static inline struct intel_digital_port *
1675 enc_to_dig_port(struct intel_encoder *encoder)
1677 struct intel_encoder *intel_encoder = encoder;
1679 if (intel_encoder_is_dig_port(intel_encoder))
1680 return container_of(&encoder->base, struct intel_digital_port,
1682 else if (intel_encoder_is_mst(intel_encoder))
1683 return enc_to_mst(encoder)->primary;
1688 static inline struct intel_digital_port *
1689 intel_attached_dig_port(struct intel_connector *connector)
1691 return enc_to_dig_port(intel_attached_encoder(connector));
1694 static inline struct intel_dp *enc_to_intel_dp(struct intel_encoder *encoder)
1696 return &enc_to_dig_port(encoder)->dp;
1699 static inline struct intel_dp *intel_attached_dp(struct intel_connector *connector)
1701 return enc_to_intel_dp(intel_attached_encoder(connector));
1704 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1706 switch (encoder->type) {
1707 case INTEL_OUTPUT_DP:
1708 case INTEL_OUTPUT_EDP:
1710 case INTEL_OUTPUT_DDI:
1711 /* Skip pure HDMI/DVI DDI encoders */
1712 return i915_mmio_reg_valid(enc_to_intel_dp(encoder)->output_reg);
1718 static inline struct intel_lspcon *
1719 enc_to_intel_lspcon(struct intel_encoder *encoder)
1721 return &enc_to_dig_port(encoder)->lspcon;
1724 static inline struct intel_digital_port *
1725 dp_to_dig_port(struct intel_dp *intel_dp)
1727 return container_of(intel_dp, struct intel_digital_port, dp);
1730 static inline struct intel_lspcon *
1731 dp_to_lspcon(struct intel_dp *intel_dp)
1733 return &dp_to_dig_port(intel_dp)->lspcon;
1736 static inline struct drm_i915_private *
1737 dp_to_i915(struct intel_dp *intel_dp)
1739 return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1742 static inline struct intel_digital_port *
1743 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1745 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1748 static inline struct intel_plane_state *
1749 intel_atomic_get_plane_state(struct intel_atomic_state *state,
1750 struct intel_plane *plane)
1752 struct drm_plane_state *ret =
1753 drm_atomic_get_plane_state(&state->base, &plane->base);
1756 return ERR_CAST(ret);
1758 return to_intel_plane_state(ret);
1761 static inline struct intel_plane_state *
1762 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
1763 struct intel_plane *plane)
1765 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
1769 static inline struct intel_plane_state *
1770 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1771 struct intel_plane *plane)
1773 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1777 static inline struct intel_crtc_state *
1778 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1779 struct intel_crtc *crtc)
1781 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1785 static inline struct intel_crtc_state *
1786 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1787 struct intel_crtc *crtc)
1789 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1793 static inline struct intel_digital_connector_state *
1794 intel_atomic_get_new_connector_state(struct intel_atomic_state *state,
1795 struct intel_connector *connector)
1797 return to_intel_digital_connector_state(
1798 drm_atomic_get_new_connector_state(&state->base,
1802 static inline struct intel_digital_connector_state *
1803 intel_atomic_get_old_connector_state(struct intel_atomic_state *state,
1804 struct intel_connector *connector)
1806 return to_intel_digital_connector_state(
1807 drm_atomic_get_old_connector_state(&state->base,
1811 /* intel_display.c */
1813 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1814 enum intel_output_type type)
1816 return crtc_state->output_types & (1 << type);
1819 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1821 return crtc_state->output_types &
1822 ((1 << INTEL_OUTPUT_DP) |
1823 (1 << INTEL_OUTPUT_DP_MST) |
1824 (1 << INTEL_OUTPUT_EDP));
1828 intel_crtc_needs_modeset(const struct intel_crtc_state *crtc_state)
1830 return drm_atomic_crtc_needs_modeset(&crtc_state->uapi);
1834 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1836 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1838 drm_crtc_wait_one_vblank(&crtc->base);
1842 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, enum pipe pipe)
1844 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1847 intel_wait_for_vblank(dev_priv, pipe);
1850 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1852 return i915_ggtt_offset(state->vma);
1855 static inline struct intel_frontbuffer *
1856 to_intel_frontbuffer(struct drm_framebuffer *fb)
1858 return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
1861 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
1863 if (dev_priv->params.panel_use_ssc >= 0)
1864 return dev_priv->params.panel_use_ssc != 0;
1865 return dev_priv->vbt.lvds_use_ssc
1866 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
1869 static inline u32 i9xx_dpll_compute_fp(struct dpll *dpll)
1871 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
1874 static inline u32 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
1875 const struct intel_crtc_state *pipe_config)
1877 if (HAS_DDI(dev_priv))
1878 return pipe_config->port_clock; /* SPLL */
1880 return dev_priv->fdi_pll_freq;
1883 #endif /* __INTEL_DISPLAY_TYPES_H__ */