drivers/gpu/drm/i915/display/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/i2c.h>
  28 #include <linux/input.h>
  29 #include <linux/intel-iommu.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/dma-resv.h>
  33 #include <linux/slab.h>
  34
  35 #include <drm/drm_atomic.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_atomic_uapi.h>
  38 #include <drm/drm_damage_helper.h>
  39 #include <drm/drm_dp_helper.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_fourcc.h>
  42 #include <drm/drm_plane_helper.h>
  43 #include <drm/drm_probe_helper.h>
  44 #include <drm/drm_rect.h>
  45
  46 #include "display/intel_crt.h"
  47 #include "display/intel_ddi.h"
  48 #include "display/intel_dp.h"
  49 #include "display/intel_dp_mst.h"
  50 #include "display/intel_dpll_mgr.h"
  51 #include "display/intel_dsi.h"
  52 #include "display/intel_dvo.h"
  53 #include "display/intel_gmbus.h"
  54 #include "display/intel_hdmi.h"
  55 #include "display/intel_lvds.h"
  56 #include "display/intel_sdvo.h"
  57 #include "display/intel_tv.h"
  58 #include "display/intel_vdsc.h"
  59
  60 #include "gt/intel_rps.h"
  61
  62 #include "i915_drv.h"
  63 #include "i915_trace.h"
  64 #include "intel_acpi.h"
  65 #include "intel_atomic.h"
  66 #include "intel_atomic_plane.h"
  67 #include "intel_bw.h"
  68 #include "intel_cdclk.h"
  69 #include "intel_color.h"
  70 #include "intel_csr.h"
  71 #include "intel_display_types.h"
  72 #include "intel_dp_link_training.h"
  73 #include "intel_fbc.h"
  74 #include "intel_fbdev.h"
  75 #include "intel_fifo_underrun.h"
  76 #include "intel_frontbuffer.h"
  77 #include "intel_hdcp.h"
  78 #include "intel_hotplug.h"
  79 #include "intel_overlay.h"
  80 #include "intel_pipe_crc.h"
  81 #include "intel_pm.h"
  82 #include "intel_psr.h"
  83 #include "intel_quirks.h"
  84 #include "intel_sideband.h"
  85 #include "intel_sprite.h"
  86 #include "intel_tc.h"
  87 #include "intel_vga.h"
  88
  89 /* Primary plane formats for gen <= 3 */
  90 static const u32 i8xx_primary_formats[] = {
  91         DRM_FORMAT_C8,
  92         DRM_FORMAT_XRGB1555,
  93         DRM_FORMAT_RGB565,
  94         DRM_FORMAT_XRGB8888,
  95 };
  96
  97 /* Primary plane formats for ivb (no fp16 due to hw issue) */
  98 static const u32 ivb_primary_formats[] = {
  99         DRM_FORMAT_C8,
 100         DRM_FORMAT_RGB565,
 101         DRM_FORMAT_XRGB8888,
 102         DRM_FORMAT_XBGR8888,
 103         DRM_FORMAT_XRGB2101010,
 104         DRM_FORMAT_XBGR2101010,
 105 };
 106
 107 /* Primary plane formats for gen >= 4, except ivb */
 108 static const u32 i965_primary_formats[] = {
 109         DRM_FORMAT_C8,
 110         DRM_FORMAT_RGB565,
 111         DRM_FORMAT_XRGB8888,
 112         DRM_FORMAT_XBGR8888,
 113         DRM_FORMAT_XRGB2101010,
 114         DRM_FORMAT_XBGR2101010,
 115         DRM_FORMAT_XBGR16161616F,
 116 };
 117
 118 /* Primary plane formats for vlv/chv */
 119 static const u32 vlv_primary_formats[] = {
 120         DRM_FORMAT_C8,
 121         DRM_FORMAT_RGB565,
 122         DRM_FORMAT_XRGB8888,
 123         DRM_FORMAT_XBGR8888,
 124         DRM_FORMAT_ARGB8888,
 125         DRM_FORMAT_ABGR8888,
 126         DRM_FORMAT_XRGB2101010,
 127         DRM_FORMAT_XBGR2101010,
 128         DRM_FORMAT_ARGB2101010,
 129         DRM_FORMAT_ABGR2101010,
 130         DRM_FORMAT_XBGR16161616F,
 131 };
 132
 133 static const u64 i9xx_format_modifiers[] = {
 134         I915_FORMAT_MOD_X_TILED,
 135         DRM_FORMAT_MOD_LINEAR,
 136         DRM_FORMAT_MOD_INVALID
 137 };
 138
 139 /* Cursor formats */
 140 static const u32 intel_cursor_formats[] = {
 141         DRM_FORMAT_ARGB8888,
 142 };
 143
 144 static const u64 cursor_format_modifiers[] = {
 145         DRM_FORMAT_MOD_LINEAR,
 146         DRM_FORMAT_MOD_INVALID
 147 };
 148
 149 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 150                                 struct intel_crtc_state *pipe_config);
 151 static void ilk_pch_clock_get(struct intel_crtc *crtc,
 152                               struct intel_crtc_state *pipe_config);
 153
 154 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
 155                                   struct drm_i915_gem_object *obj,
 156                                   struct drm_mode_fb_cmd2 *mode_cmd);
 157 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
 158 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
 159 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
 160                                          const struct intel_link_m_n *m_n,
 161                                          const struct intel_link_m_n *m2_n2);
 162 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
 163 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
 164 static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state);
 165 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
 166 static void vlv_prepare_pll(struct intel_crtc *crtc,
 167                             const struct intel_crtc_state *pipe_config);
 168 static void chv_prepare_pll(struct intel_crtc *crtc,
 169                             const struct intel_crtc_state *pipe_config);
 170 static void skl_pfit_enable(const struct intel_crtc_state *crtc_state);
 171 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
 172 static void intel_modeset_setup_hw_state(struct drm_device *dev,
 173                                          struct drm_modeset_acquire_ctx *ctx);
 174 static struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc);
 175
 176 struct intel_limit {
 177         struct {
 178                 int min, max;
 179         } dot, vco, n, m, m1, m2, p, p1;
 180
 181         struct {
 182                 int dot_limit;
 183                 int p2_slow, p2_fast;
 184         } p2;
 185 };
 186
 187 /* returns HPLL frequency in kHz */
 188 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 189 {
 190         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 191
 192         /* Obtain SKU information */
 193         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 194                 CCK_FUSE_HPLL_FREQ_MASK;
 195
 196         return vco_freq[hpll_freq] * 1000;
 197 }
 198
 199 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 200                       const char *name, u32 reg, int ref_freq)
 201 {
 202         u32 val;
 203         int divider;
 204
 205         val = vlv_cck_read(dev_priv, reg);
 206         divider = val & CCK_FREQUENCY_VALUES;
 207
 208         drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
 209                  (divider << CCK_FREQUENCY_STATUS_SHIFT),
 210                  "%s change in progress\n", name);
 211
 212         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 213 }
 214
 215 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 216                            const char *name, u32 reg)
 217 {
 218         int hpll;
 219
 220         vlv_cck_get(dev_priv);
 221
 222         if (dev_priv->hpll_freq == 0)
 223                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 224
 225         hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
 226
 227         vlv_cck_put(dev_priv);
 228
 229         return hpll;
 230 }
 231
 232 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 233 {
 234         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 235                 return;
 236
 237         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 238                                                       CCK_CZ_CLOCK_CONTROL);
 239
 240         drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
 241                 dev_priv->czclk_freq);
 242 }
 243
 244 /* units of 100MHz */
 245 static u32 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 246                                const struct intel_crtc_state *pipe_config)
 247 {
 248         if (HAS_DDI(dev_priv))
 249                 return pipe_config->port_clock; /* SPLL */
 250         else
 251                 return dev_priv->fdi_pll_freq;
 252 }
 253
 254 static const struct intel_limit intel_limits_i8xx_dac = {
 255         .dot = { .min = 25000, .max = 350000 },
 256         .vco = { .min = 908000, .max = 1512000 },
 257         .n = { .min = 2, .max = 16 },
 258         .m = { .min = 96, .max = 140 },
 259         .m1 = { .min = 18, .max = 26 },
 260         .m2 = { .min = 6, .max = 16 },
 261         .p = { .min = 4, .max = 128 },
 262         .p1 = { .min = 2, .max = 33 },
 263         .p2 = { .dot_limit = 165000,
 264                 .p2_slow = 4, .p2_fast = 2 },
 265 };
 266
 267 static const struct intel_limit intel_limits_i8xx_dvo = {
 268         .dot = { .min = 25000, .max = 350000 },
 269         .vco = { .min = 908000, .max = 1512000 },
 270         .n = { .min = 2, .max = 16 },
 271         .m = { .min = 96, .max = 140 },
 272         .m1 = { .min = 18, .max = 26 },
 273         .m2 = { .min = 6, .max = 16 },
 274         .p = { .min = 4, .max = 128 },
 275         .p1 = { .min = 2, .max = 33 },
 276         .p2 = { .dot_limit = 165000,
 277                 .p2_slow = 4, .p2_fast = 4 },
 278 };
 279
 280 static const struct intel_limit intel_limits_i8xx_lvds = {
 281         .dot = { .min = 25000, .max = 350000 },
 282         .vco = { .min = 908000, .max = 1512000 },
 283         .n = { .min = 2, .max = 16 },
 284         .m = { .min = 96, .max = 140 },
 285         .m1 = { .min = 18, .max = 26 },
 286         .m2 = { .min = 6, .max = 16 },
 287         .p = { .min = 4, .max = 128 },
 288         .p1 = { .min = 1, .max = 6 },
 289         .p2 = { .dot_limit = 165000,
 290                 .p2_slow = 14, .p2_fast = 7 },
 291 };
 292
 293 static const struct intel_limit intel_limits_i9xx_sdvo = {
 294         .dot = { .min = 20000, .max = 400000 },
 295         .vco = { .min = 1400000, .max = 2800000 },
 296         .n = { .min = 1, .max = 6 },
 297         .m = { .min = 70, .max = 120 },
 298         .m1 = { .min = 8, .max = 18 },
 299         .m2 = { .min = 3, .max = 7 },
 300         .p = { .min = 5, .max = 80 },
 301         .p1 = { .min = 1, .max = 8 },
 302         .p2 = { .dot_limit = 200000,
 303                 .p2_slow = 10, .p2_fast = 5 },
 304 };
 305
 306 static const struct intel_limit intel_limits_i9xx_lvds = {
 307         .dot = { .min = 20000, .max = 400000 },
 308         .vco = { .min = 1400000, .max = 2800000 },
 309         .n = { .min = 1, .max = 6 },
 310         .m = { .min = 70, .max = 120 },
 311         .m1 = { .min = 8, .max = 18 },
 312         .m2 = { .min = 3, .max = 7 },
 313         .p = { .min = 7, .max = 98 },
 314         .p1 = { .min = 1, .max = 8 },
 315         .p2 = { .dot_limit = 112000,
 316                 .p2_slow = 14, .p2_fast = 7 },
 317 };
 318
 319
 320 static const struct intel_limit intel_limits_g4x_sdvo = {
 321         .dot = { .min = 25000, .max = 270000 },
 322         .vco = { .min = 1750000, .max = 3500000},
 323         .n = { .min = 1, .max = 4 },
 324         .m = { .min = 104, .max = 138 },
 325         .m1 = { .min = 17, .max = 23 },
 326         .m2 = { .min = 5, .max = 11 },
 327         .p = { .min = 10, .max = 30 },
 328         .p1 = { .min = 1, .max = 3},
 329         .p2 = { .dot_limit = 270000,
 330                 .p2_slow = 10,
 331                 .p2_fast = 10
 332         },
 333 };
 334
 335 static const struct intel_limit intel_limits_g4x_hdmi = {
 336         .dot = { .min = 22000, .max = 400000 },
 337         .vco = { .min = 1750000, .max = 3500000},
 338         .n = { .min = 1, .max = 4 },
 339         .m = { .min = 104, .max = 138 },
 340         .m1 = { .min = 16, .max = 23 },
 341         .m2 = { .min = 5, .max = 11 },
 342         .p = { .min = 5, .max = 80 },
 343         .p1 = { .min = 1, .max = 8},
 344         .p2 = { .dot_limit = 165000,
 345                 .p2_slow = 10, .p2_fast = 5 },
 346 };
 347
 348 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 349         .dot = { .min = 20000, .max = 115000 },
 350         .vco = { .min = 1750000, .max = 3500000 },
 351         .n = { .min = 1, .max = 3 },
 352         .m = { .min = 104, .max = 138 },
 353         .m1 = { .min = 17, .max = 23 },
 354         .m2 = { .min = 5, .max = 11 },
 355         .p = { .min = 28, .max = 112 },
 356         .p1 = { .min = 2, .max = 8 },
 357         .p2 = { .dot_limit = 0,
 358                 .p2_slow = 14, .p2_fast = 14
 359         },
 360 };
 361
 362 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 363         .dot = { .min = 80000, .max = 224000 },
 364         .vco = { .min = 1750000, .max = 3500000 },
 365         .n = { .min = 1, .max = 3 },
 366         .m = { .min = 104, .max = 138 },
 367         .m1 = { .min = 17, .max = 23 },
 368         .m2 = { .min = 5, .max = 11 },
 369         .p = { .min = 14, .max = 42 },
 370         .p1 = { .min = 2, .max = 6 },
 371         .p2 = { .dot_limit = 0,
 372                 .p2_slow = 7, .p2_fast = 7
 373         },
 374 };
 375
 376 static const struct intel_limit pnv_limits_sdvo = {
 377         .dot = { .min = 20000, .max = 400000},
 378         .vco = { .min = 1700000, .max = 3500000 },
 379         /* Pineview's Ncounter is a ring counter */
 380         .n = { .min = 3, .max = 6 },
 381         .m = { .min = 2, .max = 256 },
 382         /* Pineview only has one combined m divider, which we treat as m2. */
 383         .m1 = { .min = 0, .max = 0 },
 384         .m2 = { .min = 0, .max = 254 },
 385         .p = { .min = 5, .max = 80 },
 386         .p1 = { .min = 1, .max = 8 },
 387         .p2 = { .dot_limit = 200000,
 388                 .p2_slow = 10, .p2_fast = 5 },
 389 };
 390
 391 static const struct intel_limit pnv_limits_lvds = {
 392         .dot = { .min = 20000, .max = 400000 },
 393         .vco = { .min = 1700000, .max = 3500000 },
 394         .n = { .min = 3, .max = 6 },
 395         .m = { .min = 2, .max = 256 },
 396         .m1 = { .min = 0, .max = 0 },
 397         .m2 = { .min = 0, .max = 254 },
 398         .p = { .min = 7, .max = 112 },
 399         .p1 = { .min = 1, .max = 8 },
 400         .p2 = { .dot_limit = 112000,
 401                 .p2_slow = 14, .p2_fast = 14 },
 402 };
 403
 404 /* Ironlake / Sandybridge
 405  *
 406  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 407  * the range value for them is (actual_value - 2).
 408  */
 409 static const struct intel_limit ilk_limits_dac = {
 410         .dot = { .min = 25000, .max = 350000 },
 411         .vco = { .min = 1760000, .max = 3510000 },
 412         .n = { .min = 1, .max = 5 },
 413         .m = { .min = 79, .max = 127 },
 414         .m1 = { .min = 12, .max = 22 },
 415         .m2 = { .min = 5, .max = 9 },
 416         .p = { .min = 5, .max = 80 },
 417         .p1 = { .min = 1, .max = 8 },
 418         .p2 = { .dot_limit = 225000,
 419                 .p2_slow = 10, .p2_fast = 5 },
 420 };
 421
 422 static const struct intel_limit ilk_limits_single_lvds = {
 423         .dot = { .min = 25000, .max = 350000 },
 424         .vco = { .min = 1760000, .max = 3510000 },
 425         .n = { .min = 1, .max = 3 },
 426         .m = { .min = 79, .max = 118 },
 427         .m1 = { .min = 12, .max = 22 },
 428         .m2 = { .min = 5, .max = 9 },
 429         .p = { .min = 28, .max = 112 },
 430         .p1 = { .min = 2, .max = 8 },
 431         .p2 = { .dot_limit = 225000,
 432                 .p2_slow = 14, .p2_fast = 14 },
 433 };
 434
 435 static const struct intel_limit ilk_limits_dual_lvds = {
 436         .dot = { .min = 25000, .max = 350000 },
 437         .vco = { .min = 1760000, .max = 3510000 },
 438         .n = { .min = 1, .max = 3 },
 439         .m = { .min = 79, .max = 127 },
 440         .m1 = { .min = 12, .max = 22 },
 441         .m2 = { .min = 5, .max = 9 },
 442         .p = { .min = 14, .max = 56 },
 443         .p1 = { .min = 2, .max = 8 },
 444         .p2 = { .dot_limit = 225000,
 445                 .p2_slow = 7, .p2_fast = 7 },
 446 };
 447
 448 /* LVDS 100mhz refclk limits. */
 449 static const struct intel_limit ilk_limits_single_lvds_100m = {
 450         .dot = { .min = 25000, .max = 350000 },
 451         .vco = { .min = 1760000, .max = 3510000 },
 452         .n = { .min = 1, .max = 2 },
 453         .m = { .min = 79, .max = 126 },
 454         .m1 = { .min = 12, .max = 22 },
 455         .m2 = { .min = 5, .max = 9 },
 456         .p = { .min = 28, .max = 112 },
 457         .p1 = { .min = 2, .max = 8 },
 458         .p2 = { .dot_limit = 225000,
 459                 .p2_slow = 14, .p2_fast = 14 },
 460 };
 461
 462 static const struct intel_limit ilk_limits_dual_lvds_100m = {
 463         .dot = { .min = 25000, .max = 350000 },
 464         .vco = { .min = 1760000, .max = 3510000 },
 465         .n = { .min = 1, .max = 3 },
 466         .m = { .min = 79, .max = 126 },
 467         .m1 = { .min = 12, .max = 22 },
 468         .m2 = { .min = 5, .max = 9 },
 469         .p = { .min = 14, .max = 42 },
 470         .p1 = { .min = 2, .max = 6 },
 471         .p2 = { .dot_limit = 225000,
 472                 .p2_slow = 7, .p2_fast = 7 },
 473 };
 474
 475 static const struct intel_limit intel_limits_vlv = {
 476          /*
 477           * These are the data rate limits (measured in fast clocks)
 478           * since those are the strictest limits we have. The fast
 479           * clock and actual rate limits are more relaxed, so checking
 480           * them would make no difference.
 481           */
 482         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 483         .vco = { .min = 4000000, .max = 6000000 },
 484         .n = { .min = 1, .max = 7 },
 485         .m1 = { .min = 2, .max = 3 },
 486         .m2 = { .min = 11, .max = 156 },
 487         .p1 = { .min = 2, .max = 3 },
 488         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 489 };
 490
 491 static const struct intel_limit intel_limits_chv = {
 492         /*
 493          * These are the data rate limits (measured in fast clocks)
 494          * since those are the strictest limits we have.  The fast
 495          * clock and actual rate limits are more relaxed, so checking
 496          * them would make no difference.
 497          */
 498         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 499         .vco = { .min = 4800000, .max = 6480000 },
 500         .n = { .min = 1, .max = 1 },
 501         .m1 = { .min = 2, .max = 2 },
 502         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 503         .p1 = { .min = 2, .max = 4 },
 504         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 505 };
 506
 507 static const struct intel_limit intel_limits_bxt = {
 508         /* FIXME: find real dot limits */
 509         .dot = { .min = 0, .max = INT_MAX },
 510         .vco = { .min = 4800000, .max = 6700000 },
 511         .n = { .min = 1, .max = 1 },
 512         .m1 = { .min = 2, .max = 2 },
 513         /* FIXME: find real m2 limits */
 514         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 515         .p1 = { .min = 2, .max = 4 },
 516         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 517 };
 518
 519 /* WA Display #0827: Gen9:all */
 520 static void
 521 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
 522 {
 523         if (enable)
 524                 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
 525                                intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS);
 526         else
 527                 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
 528                                intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
 529 }
 530
 531 /* Wa_2006604312:icl,ehl */
 532 static void
 533 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 534                        bool enable)
 535 {
 536         if (enable)
 537                 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
 538                                intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
 539         else
 540                 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
 541                                intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
 542 }
 543
 544 static bool
 545 needs_modeset(const struct intel_crtc_state *state)
 546 {
 547         return drm_atomic_crtc_needs_modeset(&state->uapi);
 548 }
 549
 550 static bool
 551 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
 552 {
 553         return crtc_state->master_transcoder != INVALID_TRANSCODER;
 554 }
 555
 556 static bool
 557 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
 558 {
 559         return crtc_state->sync_mode_slaves_mask != 0;
 560 }
 561
 562 bool
 563 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
 564 {
 565         return is_trans_port_sync_master(crtc_state) ||
 566                 is_trans_port_sync_slave(crtc_state);
 567 }
 568
 569 /*
 570  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 571  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 572  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 573  * The helpers' return value is the rate of the clock that is fed to the
 574  * display engine's pipe which can be the above fast dot clock rate or a
 575  * divided-down version of it.
 576  */
 577 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 578 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 579 {
 580         clock->m = clock->m2 + 2;
 581         clock->p = clock->p1 * clock->p2;
 582         if (WARN_ON(clock->n == 0 || clock->p == 0))
 583                 return 0;
 584         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 585         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 586
 587         return clock->dot;
 588 }
 589
 590 static u32 i9xx_dpll_compute_m(struct dpll *dpll)
 591 {
 592         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 593 }
 594
 595 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 596 {
 597         clock->m = i9xx_dpll_compute_m(clock);
 598         clock->p = clock->p1 * clock->p2;
 599         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 600                 return 0;
 601         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 602         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 603
 604         return clock->dot;
 605 }
 606
 607 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 608 {
 609         clock->m = clock->m1 * clock->m2;
 610         clock->p = clock->p1 * clock->p2;
 611         if (WARN_ON(clock->n == 0 || clock->p == 0))
 612                 return 0;
 613         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 614         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 615
 616         return clock->dot / 5;
 617 }
 618
 619 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 620 {
 621         clock->m = clock->m1 * clock->m2;
 622         clock->p = clock->p1 * clock->p2;
 623         if (WARN_ON(clock->n == 0 || clock->p == 0))
 624                 return 0;
 625         clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
 626                                            clock->n << 22);
 627         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 628
 629         return clock->dot / 5;
 630 }
 631
 632 /*
 633  * Returns whether the given set of divisors are valid for a given refclk with
 634  * the given connectors.
 635  */
 636 static bool intel_pll_is_valid(struct drm_i915_private *dev_priv,
 637                                const struct intel_limit *limit,
 638                                const struct dpll *clock)
 639 {
 640         if (clock->n < limit->n.min || limit->n.max < clock->n)
 641                 return false;
 642         if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
 643                 return false;
 644         if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
 645                 return false;
 646         if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
 647                 return false;
 648
 649         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 650             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 651                 if (clock->m1 <= clock->m2)
 652                         return false;
 653
 654         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 655             !IS_GEN9_LP(dev_priv)) {
 656                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 657                         return false;
 658                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 659                         return false;
 660         }
 661
 662         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 663                 return false;
 664         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 665          * connector, etc., rather than just a single range.
 666          */
 667         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 668                 return false;
 669
 670         return true;
 671 }
 672
 673 static int
 674 i9xx_select_p2_div(const struct intel_limit *limit,
 675                    const struct intel_crtc_state *crtc_state,
 676                    int target)
 677 {
 678         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 679
 680         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 681                 /*
 682                  * For LVDS just rely on its current settings for dual-channel.
 683                  * We haven't figured out how to reliably set up different
 684                  * single/dual channel state, if we even can.
 685                  */
 686                 if (intel_is_dual_link_lvds(dev_priv))
 687                         return limit->p2.p2_fast;
 688                 else
 689                         return limit->p2.p2_slow;
 690         } else {
 691                 if (target < limit->p2.dot_limit)
 692                         return limit->p2.p2_slow;
 693                 else
 694                         return limit->p2.p2_fast;
 695         }
 696 }
 697
 698 /*
 699  * Returns a set of divisors for the desired target clock with the given
 700  * refclk, or FALSE.  The returned values represent the clock equation:
 701  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 702  *
 703  * Target and reference clocks are specified in kHz.
 704  *
 705  * If match_clock is provided, then best_clock P divider must match the P
 706  * divider from @match_clock used for LVDS downclocking.
 707  */
 708 static bool
 709 i9xx_find_best_dpll(const struct intel_limit *limit,
 710                     struct intel_crtc_state *crtc_state,
 711                     int target, int refclk, struct dpll *match_clock,
 712                     struct dpll *best_clock)
 713 {
 714         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 715         struct dpll clock;
 716         int err = target;
 717
 718         memset(best_clock, 0, sizeof(*best_clock));
 719
 720         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 721
 722         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 723              clock.m1++) {
 724                 for (clock.m2 = limit->m2.min;
 725                      clock.m2 <= limit->m2.max; clock.m2++) {
 726                         if (clock.m2 >= clock.m1)
 727                                 break;
 728                         for (clock.n = limit->n.min;
 729                              clock.n <= limit->n.max; clock.n++) {
 730                                 for (clock.p1 = limit->p1.min;
 731                                         clock.p1 <= limit->p1.max; clock.p1++) {
 732                                         int this_err;
 733
 734                                         i9xx_calc_dpll_params(refclk, &clock);
 735                                         if (!intel_pll_is_valid(to_i915(dev),
 736                                                                 limit,
 737                                                                 &clock))
 738                                                 continue;
 739                                         if (match_clock &&
 740                                             clock.p != match_clock->p)
 741                                                 continue;
 742
 743                                         this_err = abs(clock.dot - target);
 744                                         if (this_err < err) {
 745                                                 *best_clock = clock;
 746                                                 err = this_err;
 747                                         }
 748                                 }
 749                         }
 750                 }
 751         }
 752
 753         return (err != target);
 754 }
 755
 756 /*
 757  * Returns a set of divisors for the desired target clock with the given
 758  * refclk, or FALSE.  The returned values represent the clock equation:
 759  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 760  *
 761  * Target and reference clocks are specified in kHz.
 762  *
 763  * If match_clock is provided, then best_clock P divider must match the P
 764  * divider from @match_clock used for LVDS downclocking.
 765  */
 766 static bool
 767 pnv_find_best_dpll(const struct intel_limit *limit,
 768                    struct intel_crtc_state *crtc_state,
 769                    int target, int refclk, struct dpll *match_clock,
 770                    struct dpll *best_clock)
 771 {
 772         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 773         struct dpll clock;
 774         int err = target;
 775
 776         memset(best_clock, 0, sizeof(*best_clock));
 777
 778         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 779
 780         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 781              clock.m1++) {
 782                 for (clock.m2 = limit->m2.min;
 783                      clock.m2 <= limit->m2.max; clock.m2++) {
 784                         for (clock.n = limit->n.min;
 785                              clock.n <= limit->n.max; clock.n++) {
 786                                 for (clock.p1 = limit->p1.min;
 787                                         clock.p1 <= limit->p1.max; clock.p1++) {
 788                                         int this_err;
 789
 790                                         pnv_calc_dpll_params(refclk, &clock);
 791                                         if (!intel_pll_is_valid(to_i915(dev),
 792                                                                 limit,
 793                                                                 &clock))
 794                                                 continue;
 795                                         if (match_clock &&
 796                                             clock.p != match_clock->p)
 797                                                 continue;
 798
 799                                         this_err = abs(clock.dot - target);
 800                                         if (this_err < err) {
 801                                                 *best_clock = clock;
 802                                                 err = this_err;
 803                                         }
 804                                 }
 805                         }
 806                 }
 807         }
 808
 809         return (err != target);
 810 }
 811
 812 /*
 813  * Returns a set of divisors for the desired target clock with the given
 814  * refclk, or FALSE.  The returned values represent the clock equation:
 815  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 816  *
 817  * Target and reference clocks are specified in kHz.
 818  *
 819  * If match_clock is provided, then best_clock P divider must match the P
 820  * divider from @match_clock used for LVDS downclocking.
 821  */
 822 static bool
 823 g4x_find_best_dpll(const struct intel_limit *limit,
 824                    struct intel_crtc_state *crtc_state,
 825                    int target, int refclk, struct dpll *match_clock,
 826                    struct dpll *best_clock)
 827 {
 828         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 829         struct dpll clock;
 830         int max_n;
 831         bool found = false;
 832         /* approximately equals target * 0.00585 */
 833         int err_most = (target >> 8) + (target >> 9);
 834
 835         memset(best_clock, 0, sizeof(*best_clock));
 836
 837         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 838
 839         max_n = limit->n.max;
 840         /* based on hardware requirement, prefer smaller n to precision */
 841         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 842                 /* based on hardware requirement, prefere larger m1,m2 */
 843                 for (clock.m1 = limit->m1.max;
 844                      clock.m1 >= limit->m1.min; clock.m1--) {
 845                         for (clock.m2 = limit->m2.max;
 846                              clock.m2 >= limit->m2.min; clock.m2--) {
 847                                 for (clock.p1 = limit->p1.max;
 848                                      clock.p1 >= limit->p1.min; clock.p1--) {
 849                                         int this_err;
 850
 851                                         i9xx_calc_dpll_params(refclk, &clock);
 852                                         if (!intel_pll_is_valid(to_i915(dev),
 853                                                                 limit,
 854                                                                 &clock))
 855                                                 continue;
 856
 857                                         this_err = abs(clock.dot - target);
 858                                         if (this_err < err_most) {
 859                                                 *best_clock = clock;
 860                                                 err_most = this_err;
 861                                                 max_n = clock.n;
 862                                                 found = true;
 863                                         }
 864                                 }
 865                         }
 866                 }
 867         }
 868         return found;
 869 }
 870
 871 /*
 872  * Check if the calculated PLL configuration is more optimal compared to the
 873  * best configuration and error found so far. Return the calculated error.
 874  */
 875 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 876                                const struct dpll *calculated_clock,
 877                                const struct dpll *best_clock,
 878                                unsigned int best_error_ppm,
 879                                unsigned int *error_ppm)
 880 {
 881         /*
 882          * For CHV ignore the error and consider only the P value.
 883          * Prefer a bigger P value based on HW requirements.
 884          */
 885         if (IS_CHERRYVIEW(to_i915(dev))) {
 886                 *error_ppm = 0;
 887
 888                 return calculated_clock->p > best_clock->p;
 889         }
 890
 891         if (drm_WARN_ON_ONCE(dev, !target_freq))
 892                 return false;
 893
 894         *error_ppm = div_u64(1000000ULL *
 895                                 abs(target_freq - calculated_clock->dot),
 896                              target_freq);
 897         /*
 898          * Prefer a better P value over a better (smaller) error if the error
 899          * is small. Ensure this preference for future configurations too by
 900          * setting the error to 0.
 901          */
 902         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 903                 *error_ppm = 0;
 904
 905                 return true;
 906         }
 907
 908         return *error_ppm + 10 < best_error_ppm;
 909 }
 910
 911 /*
 912  * Returns a set of divisors for the desired target clock with the given
 913  * refclk, or FALSE.  The returned values represent the clock equation:
 914  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 915  */
 916 static bool
 917 vlv_find_best_dpll(const struct intel_limit *limit,
 918                    struct intel_crtc_state *crtc_state,
 919                    int target, int refclk, struct dpll *match_clock,
 920                    struct dpll *best_clock)
 921 {
 922         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 923         struct drm_device *dev = crtc->base.dev;
 924         struct dpll clock;
 925         unsigned int bestppm = 1000000;
 926         /* min update 19.2 MHz */
 927         int max_n = min(limit->n.max, refclk / 19200);
 928         bool found = false;
 929
 930         target *= 5; /* fast clock */
 931
 932         memset(best_clock, 0, sizeof(*best_clock));
 933
 934         /* based on hardware requirement, prefer smaller n to precision */
 935         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 936                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 937                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 938                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 939                                 clock.p = clock.p1 * clock.p2;
 940                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 941                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 942                                         unsigned int ppm;
 943
 944                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 945                                                                      refclk * clock.m1);
 946
 947                                         vlv_calc_dpll_params(refclk, &clock);
 948
 949                                         if (!intel_pll_is_valid(to_i915(dev),
 950                                                                 limit,
 951                                                                 &clock))
 952                                                 continue;
 953
 954                                         if (!vlv_PLL_is_optimal(dev, target,
 955                                                                 &clock,
 956                                                                 best_clock,
 957                                                                 bestppm, &ppm))
 958                                                 continue;
 959
 960                                         *best_clock = clock;
 961                                         bestppm = ppm;
 962                                         found = true;
 963                                 }
 964                         }
 965                 }
 966         }
 967
 968         return found;
 969 }
 970
 971 /*
 972  * Returns a set of divisors for the desired target clock with the given
 973  * refclk, or FALSE.  The returned values represent the clock equation:
 974  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 975  */
 976 static bool
 977 chv_find_best_dpll(const struct intel_limit *limit,
 978                    struct intel_crtc_state *crtc_state,
 979                    int target, int refclk, struct dpll *match_clock,
 980                    struct dpll *best_clock)
 981 {
 982         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 983         struct drm_device *dev = crtc->base.dev;
 984         unsigned int best_error_ppm;
 985         struct dpll clock;
 986         u64 m2;
 987         int found = false;
 988
 989         memset(best_clock, 0, sizeof(*best_clock));
 990         best_error_ppm = 1000000;
 991
 992         /*
 993          * Based on hardware doc, the n always set to 1, and m1 always
 994          * set to 2.  If requires to support 200Mhz refclk, we need to
 995          * revisit this because n may not 1 anymore.
 996          */
 997         clock.n = 1, clock.m1 = 2;
 998         target *= 5;    /* fast clock */
 999
1000         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1001                 for (clock.p2 = limit->p2.p2_fast;
1002                                 clock.p2 >= limit->p2.p2_slow;
1003                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1004                         unsigned int error_ppm;
1005
1006                         clock.p = clock.p1 * clock.p2;
1007
1008                         m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
1009                                                    refclk * clock.m1);
1010
1011                         if (m2 > INT_MAX/clock.m1)
1012                                 continue;
1013
1014                         clock.m2 = m2;
1015
1016                         chv_calc_dpll_params(refclk, &clock);
1017
1018                         if (!intel_pll_is_valid(to_i915(dev), limit, &clock))
1019                                 continue;
1020
1021                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1022                                                 best_error_ppm, &error_ppm))
1023                                 continue;
1024
1025                         *best_clock = clock;
1026                         best_error_ppm = error_ppm;
1027                         found = true;
1028                 }
1029         }
1030
1031         return found;
1032 }
1033
1034 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
1035                         struct dpll *best_clock)
1036 {
1037         int refclk = 100000;
1038         const struct intel_limit *limit = &intel_limits_bxt;
1039
1040         return chv_find_best_dpll(limit, crtc_state,
1041                                   crtc_state->port_clock, refclk,
1042                                   NULL, best_clock);
1043 }
1044
1045 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
1046                                     enum pipe pipe)
1047 {
1048         i915_reg_t reg = PIPEDSL(pipe);
1049         u32 line1, line2;
1050         u32 line_mask;
1051
1052         if (IS_GEN(dev_priv, 2))
1053                 line_mask = DSL_LINEMASK_GEN2;
1054         else
1055                 line_mask = DSL_LINEMASK_GEN3;
1056
1057         line1 = intel_de_read(dev_priv, reg) & line_mask;
1058         msleep(5);
1059         line2 = intel_de_read(dev_priv, reg) & line_mask;
1060
1061         return line1 != line2;
1062 }
1063
1064 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1065 {
1066         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1067         enum pipe pipe = crtc->pipe;
1068
1069         /* Wait for the display line to settle/start moving */
1070         if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1071                 drm_err(&dev_priv->drm,
1072                         "pipe %c scanline %s wait timed out\n",
1073                         pipe_name(pipe), onoff(state));
1074 }
1075
1076 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1077 {
1078         wait_for_pipe_scanline_moving(crtc, false);
1079 }
1080
1081 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1082 {
1083         wait_for_pipe_scanline_moving(crtc, true);
1084 }
1085
1086 static void
1087 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
1088 {
1089         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1090         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1091
1092         if (INTEL_GEN(dev_priv) >= 4) {
1093                 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1094                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1095
1096                 /* Wait for the Pipe State to go off */
1097                 if (intel_de_wait_for_clear(dev_priv, reg,
1098                                             I965_PIPECONF_ACTIVE, 100))
1099                         drm_WARN(&dev_priv->drm, 1,
1100                                  "pipe_off wait timed out\n");
1101         } else {
1102                 intel_wait_for_pipe_scanline_stopped(crtc);
1103         }
1104 }
1105
1106 /* Only for pre-ILK configs */
1107 void assert_pll(struct drm_i915_private *dev_priv,
1108                 enum pipe pipe, bool state)
1109 {
1110         u32 val;
1111         bool cur_state;
1112
1113         val = intel_de_read(dev_priv, DPLL(pipe));
1114         cur_state = !!(val & DPLL_VCO_ENABLE);
1115         I915_STATE_WARN(cur_state != state,
1116              "PLL state assertion failure (expected %s, current %s)\n",
1117                         onoff(state), onoff(cur_state));
1118 }
1119
1120 /* XXX: the dsi pll is shared between MIPI DSI ports */
1121 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1122 {
1123         u32 val;
1124         bool cur_state;
1125
1126         vlv_cck_get(dev_priv);
1127         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1128         vlv_cck_put(dev_priv);
1129
1130         cur_state = val & DSI_PLL_VCO_EN;
1131         I915_STATE_WARN(cur_state != state,
1132              "DSI PLL state assertion failure (expected %s, current %s)\n",
1133                         onoff(state), onoff(cur_state));
1134 }
1135
1136 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1137                           enum pipe pipe, bool state)
1138 {
1139         bool cur_state;
1140
1141         if (HAS_DDI(dev_priv)) {
1142                 /*
1143                  * DDI does not have a specific FDI_TX register.
1144                  *
1145                  * FDI is never fed from EDP transcoder
1146                  * so pipe->transcoder cast is fine here.
1147                  */
1148                 enum transcoder cpu_transcoder = (enum transcoder)pipe;
1149                 u32 val = intel_de_read(dev_priv,
1150                                         TRANS_DDI_FUNC_CTL(cpu_transcoder));
1151                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1152         } else {
1153                 u32 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe));
1154                 cur_state = !!(val & FDI_TX_ENABLE);
1155         }
1156         I915_STATE_WARN(cur_state != state,
1157              "FDI TX state assertion failure (expected %s, current %s)\n",
1158                         onoff(state), onoff(cur_state));
1159 }
1160 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1161 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1162
1163 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1164                           enum pipe pipe, bool state)
1165 {
1166         u32 val;
1167         bool cur_state;
1168
1169         val = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
1170         cur_state = !!(val & FDI_RX_ENABLE);
1171         I915_STATE_WARN(cur_state != state,
1172              "FDI RX state assertion failure (expected %s, current %s)\n",
1173                         onoff(state), onoff(cur_state));
1174 }
1175 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1176 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1177
1178 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1179                                       enum pipe pipe)
1180 {
1181         u32 val;
1182
1183         /* ILK FDI PLL is always enabled */
1184         if (IS_GEN(dev_priv, 5))
1185                 return;
1186
1187         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1188         if (HAS_DDI(dev_priv))
1189                 return;
1190
1191         val = intel_de_read(dev_priv, FDI_TX_CTL(pipe));
1192         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1193 }
1194
1195 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1196                        enum pipe pipe, bool state)
1197 {
1198         u32 val;
1199         bool cur_state;
1200
1201         val = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
1202         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1203         I915_STATE_WARN(cur_state != state,
1204              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1205                         onoff(state), onoff(cur_state));
1206 }
1207
1208 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1209 {
1210         i915_reg_t pp_reg;
1211         u32 val;
1212         enum pipe panel_pipe = INVALID_PIPE;
1213         bool locked = true;
1214
1215         if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv)))
1216                 return;
1217
1218         if (HAS_PCH_SPLIT(dev_priv)) {
1219                 u32 port_sel;
1220
1221                 pp_reg = PP_CONTROL(0);
1222                 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1223
1224                 switch (port_sel) {
1225                 case PANEL_PORT_SELECT_LVDS:
1226                         intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1227                         break;
1228                 case PANEL_PORT_SELECT_DPA:
1229                         intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1230                         break;
1231                 case PANEL_PORT_SELECT_DPC:
1232                         intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1233                         break;
1234                 case PANEL_PORT_SELECT_DPD:
1235                         intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1236                         break;
1237                 default:
1238                         MISSING_CASE(port_sel);
1239                         break;
1240                 }
1241         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1242                 /* presumably write lock depends on pipe, not port select */
1243                 pp_reg = PP_CONTROL(pipe);
1244                 panel_pipe = pipe;
1245         } else {
1246                 u32 port_sel;
1247
1248                 pp_reg = PP_CONTROL(0);
1249                 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1250
1251                 drm_WARN_ON(&dev_priv->drm,
1252                             port_sel != PANEL_PORT_SELECT_LVDS);
1253                 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1254         }
1255
1256         val = intel_de_read(dev_priv, pp_reg);
1257         if (!(val & PANEL_POWER_ON) ||
1258             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1259                 locked = false;
1260
1261         I915_STATE_WARN(panel_pipe == pipe && locked,
1262              "panel assertion failure, pipe %c regs locked\n",
1263              pipe_name(pipe));
1264 }
1265
1266 void assert_pipe(struct drm_i915_private *dev_priv,
1267                  enum transcoder cpu_transcoder, bool state)
1268 {
1269         bool cur_state;
1270         enum intel_display_power_domain power_domain;
1271         intel_wakeref_t wakeref;
1272
1273         /* we keep both pipes enabled on 830 */
1274         if (IS_I830(dev_priv))
1275                 state = true;
1276
1277         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1278         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1279         if (wakeref) {
1280                 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
1281                 cur_state = !!(val & PIPECONF_ENABLE);
1282
1283                 intel_display_power_put(dev_priv, power_domain, wakeref);
1284         } else {
1285                 cur_state = false;
1286         }
1287
1288         I915_STATE_WARN(cur_state != state,
1289                         "transcoder %s assertion failure (expected %s, current %s)\n",
1290                         transcoder_name(cpu_transcoder),
1291                         onoff(state), onoff(cur_state));
1292 }
1293
1294 static void assert_plane(struct intel_plane *plane, bool state)
1295 {
1296         enum pipe pipe;
1297         bool cur_state;
1298
1299         cur_state = plane->get_hw_state(plane, &pipe);
1300
1301         I915_STATE_WARN(cur_state != state,
1302                         "%s assertion failure (expected %s, current %s)\n",
1303                         plane->base.name, onoff(state), onoff(cur_state));
1304 }
1305
1306 #define assert_plane_enabled(p) assert_plane(p, true)
1307 #define assert_plane_disabled(p) assert_plane(p, false)
1308
1309 static void assert_planes_disabled(struct intel_crtc *crtc)
1310 {
1311         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1312         struct intel_plane *plane;
1313
1314         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1315                 assert_plane_disabled(plane);
1316 }
1317
1318 static void assert_vblank_disabled(struct drm_crtc *crtc)
1319 {
1320         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1321                 drm_crtc_vblank_put(crtc);
1322 }
1323
1324 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1325                                     enum pipe pipe)
1326 {
1327         u32 val;
1328         bool enabled;
1329
1330         val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe));
1331         enabled = !!(val & TRANS_ENABLE);
1332         I915_STATE_WARN(enabled,
1333              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1334              pipe_name(pipe));
1335 }
1336
1337 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1338                                    enum pipe pipe, enum port port,
1339                                    i915_reg_t dp_reg)
1340 {
1341         enum pipe port_pipe;
1342         bool state;
1343
1344         state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
1345
1346         I915_STATE_WARN(state && port_pipe == pipe,
1347                         "PCH DP %c enabled on transcoder %c, should be disabled\n",
1348                         port_name(port), pipe_name(pipe));
1349
1350         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1351                         "IBX PCH DP %c still using transcoder B\n",
1352                         port_name(port));
1353 }
1354
1355 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1356                                      enum pipe pipe, enum port port,
1357                                      i915_reg_t hdmi_reg)
1358 {
1359         enum pipe port_pipe;
1360         bool state;
1361
1362         state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
1363
1364         I915_STATE_WARN(state && port_pipe == pipe,
1365                         "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
1366                         port_name(port), pipe_name(pipe));
1367
1368         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1369                         "IBX PCH HDMI %c still using transcoder B\n",
1370                         port_name(port));
1371 }
1372
1373 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1374                                       enum pipe pipe)
1375 {
1376         enum pipe port_pipe;
1377
1378         assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
1379         assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
1380         assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
1381
1382         I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
1383                         port_pipe == pipe,
1384                         "PCH VGA enabled on transcoder %c, should be disabled\n",
1385                         pipe_name(pipe));
1386
1387         I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
1388                         port_pipe == pipe,
1389                         "PCH LVDS enabled on transcoder %c, should be disabled\n",
1390                         pipe_name(pipe));
1391
1392         /* PCH SDVOB multiplex with HDMIB */
1393         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
1394         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
1395         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
1396 }
1397
1398 static void _vlv_enable_pll(struct intel_crtc *crtc,
1399                             const struct intel_crtc_state *pipe_config)
1400 {
1401         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1402         enum pipe pipe = crtc->pipe;
1403
1404         intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1405         intel_de_posting_read(dev_priv, DPLL(pipe));
1406         udelay(150);
1407
1408         if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1409                 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe);
1410 }
1411
1412 static void vlv_enable_pll(struct intel_crtc *crtc,
1413                            const struct intel_crtc_state *pipe_config)
1414 {
1415         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1416         enum pipe pipe = crtc->pipe;
1417
1418         assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
1419
1420         /* PLL is protected by panel, make sure we can write it */
1421         assert_panel_unlocked(dev_priv, pipe);
1422
1423         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1424                 _vlv_enable_pll(crtc, pipe_config);
1425
1426         intel_de_write(dev_priv, DPLL_MD(pipe),
1427                        pipe_config->dpll_hw_state.dpll_md);
1428         intel_de_posting_read(dev_priv, DPLL_MD(pipe));
1429 }
1430
1431
1432 static void _chv_enable_pll(struct intel_crtc *crtc,
1433                             const struct intel_crtc_state *pipe_config)
1434 {
1435         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1436         enum pipe pipe = crtc->pipe;
1437         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1438         u32 tmp;
1439
1440         vlv_dpio_get(dev_priv);
1441
1442         /* Enable back the 10bit clock to display controller */
1443         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1444         tmp |= DPIO_DCLKP_EN;
1445         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1446
1447         vlv_dpio_put(dev_priv);
1448
1449         /*
1450          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1451          */
1452         udelay(1);
1453
1454         /* Enable PLL */
1455         intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1456
1457         /* Check PLL is locked */
1458         if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1459                 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe);
1460 }
1461
1462 static void chv_enable_pll(struct intel_crtc *crtc,
1463                            const struct intel_crtc_state *pipe_config)
1464 {
1465         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1466         enum pipe pipe = crtc->pipe;
1467
1468         assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
1469
1470         /* PLL is protected by panel, make sure we can write it */
1471         assert_panel_unlocked(dev_priv, pipe);
1472
1473         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1474                 _chv_enable_pll(crtc, pipe_config);
1475
1476         if (pipe != PIPE_A) {
1477                 /*
1478                  * WaPixelRepeatModeFixForC0:chv
1479                  *
1480                  * DPLLCMD is AWOL. Use chicken bits to propagate
1481                  * the value from DPLLBMD to either pipe B or C.
1482                  */
1483                 intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1484                 intel_de_write(dev_priv, DPLL_MD(PIPE_B),
1485                                pipe_config->dpll_hw_state.dpll_md);
1486                 intel_de_write(dev_priv, CBR4_VLV, 0);
1487                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1488
1489                 /*
1490                  * DPLLB VGA mode also seems to cause problems.
1491                  * We should always have it disabled.
1492                  */
1493                 drm_WARN_ON(&dev_priv->drm,
1494                             (intel_de_read(dev_priv, DPLL(PIPE_B)) &
1495                              DPLL_VGA_MODE_DIS) == 0);
1496         } else {
1497                 intel_de_write(dev_priv, DPLL_MD(pipe),
1498                                pipe_config->dpll_hw_state.dpll_md);
1499                 intel_de_posting_read(dev_priv, DPLL_MD(pipe));
1500         }
1501 }
1502
1503 static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
1504 {
1505         if (IS_I830(dev_priv))
1506                 return false;
1507
1508         return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
1509 }
1510
1511 static void i9xx_enable_pll(struct intel_crtc *crtc,
1512                             const struct intel_crtc_state *crtc_state)
1513 {
1514         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1515         i915_reg_t reg = DPLL(crtc->pipe);
1516         u32 dpll = crtc_state->dpll_hw_state.dpll;
1517         int i;
1518
1519         assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
1520
1521         /* PLL is protected by panel, make sure we can write it */
1522         if (i9xx_has_pps(dev_priv))
1523                 assert_panel_unlocked(dev_priv, crtc->pipe);
1524
1525         /*
1526          * Apparently we need to have VGA mode enabled prior to changing
1527          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1528          * dividers, even though the register value does change.
1529          */
1530         intel_de_write(dev_priv, reg, dpll & ~DPLL_VGA_MODE_DIS);
1531         intel_de_write(dev_priv, reg, dpll);
1532
1533         /* Wait for the clocks to stabilize. */
1534         intel_de_posting_read(dev_priv, reg);
1535         udelay(150);
1536
1537         if (INTEL_GEN(dev_priv) >= 4) {
1538                 intel_de_write(dev_priv, DPLL_MD(crtc->pipe),
1539                                crtc_state->dpll_hw_state.dpll_md);
1540         } else {
1541                 /* The pixel multiplier can only be updated once the
1542                  * DPLL is enabled and the clocks are stable.
1543                  *
1544                  * So write it again.
1545                  */
1546                 intel_de_write(dev_priv, reg, dpll);
1547         }
1548
1549         /* We do this three times for luck */
1550         for (i = 0; i < 3; i++) {
1551                 intel_de_write(dev_priv, reg, dpll);
1552                 intel_de_posting_read(dev_priv, reg);
1553                 udelay(150); /* wait for warmup */
1554         }
1555 }
1556
1557 static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
1558 {
1559         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1560         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1561         enum pipe pipe = crtc->pipe;
1562
1563         /* Don't disable pipe or pipe PLLs if needed */
1564         if (IS_I830(dev_priv))
1565                 return;
1566
1567         /* Make sure the pipe isn't still relying on us */
1568         assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
1569
1570         intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
1571         intel_de_posting_read(dev_priv, DPLL(pipe));
1572 }
1573
1574 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1575 {
1576         u32 val;
1577
1578         /* Make sure the pipe isn't still relying on us */
1579         assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
1580
1581         val = DPLL_INTEGRATED_REF_CLK_VLV |
1582                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1583         if (pipe != PIPE_A)
1584                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1585
1586         intel_de_write(dev_priv, DPLL(pipe), val);
1587         intel_de_posting_read(dev_priv, DPLL(pipe));
1588 }
1589
1590 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1591 {
1592         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1593         u32 val;
1594
1595         /* Make sure the pipe isn't still relying on us */
1596         assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
1597
1598         val = DPLL_SSC_REF_CLK_CHV |
1599                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1600         if (pipe != PIPE_A)
1601                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1602
1603         intel_de_write(dev_priv, DPLL(pipe), val);
1604         intel_de_posting_read(dev_priv, DPLL(pipe));
1605
1606         vlv_dpio_get(dev_priv);
1607
1608         /* Disable 10bit clock to display controller */
1609         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1610         val &= ~DPIO_DCLKP_EN;
1611         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1612
1613         vlv_dpio_put(dev_priv);
1614 }
1615
1616 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1617                          struct intel_digital_port *dig_port,
1618                          unsigned int expected_mask)
1619 {
1620         u32 port_mask;
1621         i915_reg_t dpll_reg;
1622
1623         switch (dig_port->base.port) {
1624         case PORT_B:
1625                 port_mask = DPLL_PORTB_READY_MASK;
1626                 dpll_reg = DPLL(0);
1627                 break;
1628         case PORT_C:
1629                 port_mask = DPLL_PORTC_READY_MASK;
1630                 dpll_reg = DPLL(0);
1631                 expected_mask <<= 4;
1632                 break;
1633         case PORT_D:
1634                 port_mask = DPLL_PORTD_READY_MASK;
1635                 dpll_reg = DPIO_PHY_STATUS;
1636                 break;
1637         default:
1638                 BUG();
1639         }
1640
1641         if (intel_de_wait_for_register(dev_priv, dpll_reg,
1642                                        port_mask, expected_mask, 1000))
1643                 drm_WARN(&dev_priv->drm, 1,
1644                          "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
1645                          dig_port->base.base.base.id, dig_port->base.base.name,
1646                          intel_de_read(dev_priv, dpll_reg) & port_mask,
1647                          expected_mask);
1648 }
1649
1650 static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
1651 {
1652         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1653         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1654         enum pipe pipe = crtc->pipe;
1655         i915_reg_t reg;
1656         u32 val, pipeconf_val;
1657
1658         /* Make sure PCH DPLL is enabled */
1659         assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
1660
1661         /* FDI must be feeding us bits for PCH ports */
1662         assert_fdi_tx_enabled(dev_priv, pipe);
1663         assert_fdi_rx_enabled(dev_priv, pipe);
1664
1665         if (HAS_PCH_CPT(dev_priv)) {
1666                 reg = TRANS_CHICKEN2(pipe);
1667                 val = intel_de_read(dev_priv, reg);
1668                 /*
1669                  * Workaround: Set the timing override bit
1670                  * before enabling the pch transcoder.
1671                  */
1672                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1673                 /* Configure frame start delay to match the CPU */
1674                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1675                 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
1676                 intel_de_write(dev_priv, reg, val);
1677         }
1678
1679         reg = PCH_TRANSCONF(pipe);
1680         val = intel_de_read(dev_priv, reg);
1681         pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe));
1682
1683         if (HAS_PCH_IBX(dev_priv)) {
1684                 /* Configure frame start delay to match the CPU */
1685                 val &= ~TRANS_FRAME_START_DELAY_MASK;
1686                 val |= TRANS_FRAME_START_DELAY(0);
1687
1688                 /*
1689                  * Make the BPC in transcoder be consistent with
1690                  * that in pipeconf reg. For HDMI we must use 8bpc
1691                  * here for both 8bpc and 12bpc.
1692                  */
1693                 val &= ~PIPECONF_BPC_MASK;
1694                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1695                         val |= PIPECONF_8BPC;
1696                 else
1697                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1698         }
1699
1700         val &= ~TRANS_INTERLACE_MASK;
1701         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
1702                 if (HAS_PCH_IBX(dev_priv) &&
1703                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
1704                         val |= TRANS_LEGACY_INTERLACED_ILK;
1705                 else
1706                         val |= TRANS_INTERLACED;
1707         } else {
1708                 val |= TRANS_PROGRESSIVE;
1709         }
1710
1711         intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
1712         if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
1713                 drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",
1714                         pipe_name(pipe));
1715 }
1716
1717 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1718                                       enum transcoder cpu_transcoder)
1719 {
1720         u32 val, pipeconf_val;
1721
1722         /* FDI must be feeding us bits for PCH ports */
1723         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1724         assert_fdi_rx_enabled(dev_priv, PIPE_A);
1725
1726         val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
1727         /* Workaround: set timing override bit. */
1728         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1729         /* Configure frame start delay to match the CPU */
1730         val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1731         val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
1732         intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
1733
1734         val = TRANS_ENABLE;
1735         pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
1736
1737         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1738             PIPECONF_INTERLACED_ILK)
1739                 val |= TRANS_INTERLACED;
1740         else
1741                 val |= TRANS_PROGRESSIVE;
1742
1743         intel_de_write(dev_priv, LPT_TRANSCONF, val);
1744         if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
1745                                   TRANS_STATE_ENABLE, 100))
1746                 drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n");
1747 }
1748
1749 static void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1750                                        enum pipe pipe)
1751 {
1752         i915_reg_t reg;
1753         u32 val;
1754
1755         /* FDI relies on the transcoder */
1756         assert_fdi_tx_disabled(dev_priv, pipe);
1757         assert_fdi_rx_disabled(dev_priv, pipe);
1758
1759         /* Ports must be off as well */
1760         assert_pch_ports_disabled(dev_priv, pipe);
1761
1762         reg = PCH_TRANSCONF(pipe);
1763         val = intel_de_read(dev_priv, reg);
1764         val &= ~TRANS_ENABLE;
1765         intel_de_write(dev_priv, reg, val);
1766         /* wait for PCH transcoder off, transcoder state */
1767         if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
1768                 drm_err(&dev_priv->drm, "failed to disable transcoder %c\n",
1769                         pipe_name(pipe));
1770
1771         if (HAS_PCH_CPT(dev_priv)) {
1772                 /* Workaround: Clear the timing override chicken bit again. */
1773                 reg = TRANS_CHICKEN2(pipe);
1774                 val = intel_de_read(dev_priv, reg);
1775                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1776                 intel_de_write(dev_priv, reg, val);
1777         }
1778 }
1779
1780 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1781 {
1782         u32 val;
1783
1784         val = intel_de_read(dev_priv, LPT_TRANSCONF);
1785         val &= ~TRANS_ENABLE;
1786         intel_de_write(dev_priv, LPT_TRANSCONF, val);
1787         /* wait for PCH transcoder off, transcoder state */
1788         if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
1789                                     TRANS_STATE_ENABLE, 50))
1790                 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
1791
1792         /* Workaround: clear timing override bit. */
1793         val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
1794         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1795         intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
1796 }
1797
1798 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1799 {
1800         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1801
1802         if (HAS_PCH_LPT(dev_priv))
1803                 return PIPE_A;
1804         else
1805                 return crtc->pipe;
1806 }
1807
1808 static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
1809 {
1810         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1811
1812         /*
1813          * On i965gm the hardware frame counter reads
1814          * zero when the TV encoder is enabled :(
1815          */
1816         if (IS_I965GM(dev_priv) &&
1817             (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)))
1818                 return 0;
1819
1820         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1821                 return 0xffffffff; /* full 32 bit counter */
1822         else if (INTEL_GEN(dev_priv) >= 3)
1823                 return 0xffffff; /* only 24 bits of frame count */
1824         else
1825                 return 0; /* Gen2 doesn't have a hardware frame counter */
1826 }
1827
1828 void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
1829 {
1830         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1831
1832         assert_vblank_disabled(&crtc->base);
1833         drm_crtc_set_max_vblank_count(&crtc->base,
1834                                       intel_crtc_max_vblank_count(crtc_state));
1835         drm_crtc_vblank_on(&crtc->base);
1836 }
1837
1838 void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state)
1839 {
1840         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1841
1842         drm_crtc_vblank_off(&crtc->base);
1843         assert_vblank_disabled(&crtc->base);
1844 }
1845
1846 void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
1847 {
1848         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1849         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1850         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1851         enum pipe pipe = crtc->pipe;
1852         i915_reg_t reg;
1853         u32 val;
1854
1855         drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
1856
1857         assert_planes_disabled(crtc);
1858
1859         /*
1860          * A pipe without a PLL won't actually be able to drive bits from
1861          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1862          * need the check.
1863          */
1864         if (HAS_GMCH(dev_priv)) {
1865                 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1866                         assert_dsi_pll_enabled(dev_priv);
1867                 else
1868                         assert_pll_enabled(dev_priv, pipe);
1869         } else {
1870                 if (new_crtc_state->has_pch_encoder) {
1871                         /* if driving the PCH, we need FDI enabled */
1872                         assert_fdi_rx_pll_enabled(dev_priv,
1873                                                   intel_crtc_pch_transcoder(crtc));
1874                         assert_fdi_tx_pll_enabled(dev_priv,
1875                                                   (enum pipe) cpu_transcoder);
1876                 }
1877                 /* FIXME: assert CPU port conditions for SNB+ */
1878         }
1879
1880         trace_intel_pipe_enable(crtc);
1881
1882         reg = PIPECONF(cpu_transcoder);
1883         val = intel_de_read(dev_priv, reg);
1884         if (val & PIPECONF_ENABLE) {
1885                 /* we keep both pipes enabled on 830 */
1886                 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
1887                 return;
1888         }
1889
1890         intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE);
1891         intel_de_posting_read(dev_priv, reg);
1892
1893         /*
1894          * Until the pipe starts PIPEDSL reads will return a stale value,
1895          * which causes an apparent vblank timestamp jump when PIPEDSL
1896          * resets to its proper value. That also messes up the frame count
1897          * when it's derived from the timestamps. So let's wait for the
1898          * pipe to start properly before we call drm_crtc_vblank_on()
1899          */
1900         if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
1901                 intel_wait_for_pipe_scanline_moving(crtc);
1902 }
1903
1904 void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1905 {
1906         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1907         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1908         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1909         enum pipe pipe = crtc->pipe;
1910         i915_reg_t reg;
1911         u32 val;
1912
1913         drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));
1914
1915         /*
1916          * Make sure planes won't keep trying to pump pixels to us,
1917          * or we might hang the display.
1918          */
1919         assert_planes_disabled(crtc);
1920
1921         trace_intel_pipe_disable(crtc);
1922
1923         reg = PIPECONF(cpu_transcoder);
1924         val = intel_de_read(dev_priv, reg);
1925         if ((val & PIPECONF_ENABLE) == 0)
1926                 return;
1927
1928         /*
1929          * Double wide has implications for planes
1930          * so best keep it disabled when not needed.
1931          */
1932         if (old_crtc_state->double_wide)
1933                 val &= ~PIPECONF_DOUBLE_WIDE;
1934
1935         /* Don't disable pipe or pipe PLLs if needed */
1936         if (!IS_I830(dev_priv))
1937                 val &= ~PIPECONF_ENABLE;
1938
1939         intel_de_write(dev_priv, reg, val);
1940         if ((val & PIPECONF_ENABLE) == 0)
1941                 intel_wait_for_pipe_off(old_crtc_state);
1942 }
1943
1944 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1945 {
1946         return IS_GEN(dev_priv, 2) ? 2048 : 4096;
1947 }
1948
1949 static bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
1950 {
1951         if (!is_ccs_modifier(fb->modifier))
1952                 return false;
1953
1954         return plane >= fb->format->num_planes / 2;
1955 }
1956
1957 static bool is_gen12_ccs_modifier(u64 modifier)
1958 {
1959         return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
1960                modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
1961
1962 }
1963
1964 static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
1965 {
1966         return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
1967 }
1968
1969 static bool is_aux_plane(const struct drm_framebuffer *fb, int plane)
1970 {
1971         if (is_ccs_modifier(fb->modifier))
1972                 return is_ccs_plane(fb, plane);
1973
1974         return plane == 1;
1975 }
1976
1977 static int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
1978 {
1979         drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
1980                     (main_plane && main_plane >= fb->format->num_planes / 2));
1981
1982         return fb->format->num_planes / 2 + main_plane;
1983 }
1984
1985 static int ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
1986 {
1987         drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
1988                     ccs_plane < fb->format->num_planes / 2);
1989
1990         return ccs_plane - fb->format->num_planes / 2;
1991 }
1992
1993 /* Return either the main plane's CCS or - if not a CCS FB - UV plane */
1994 int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
1995 {
1996         if (is_ccs_modifier(fb->modifier))
1997                 return main_to_ccs_plane(fb, main_plane);
1998
1999         return 1;
2000 }
2001
2002 bool
2003 intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
2004                                     uint64_t modifier)
2005 {
2006         return info->is_yuv &&
2007                info->num_planes == (is_ccs_modifier(modifier) ? 4 : 2);
2008 }
2009
2010 static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb,
2011                                    int color_plane)
2012 {
2013         return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
2014                color_plane == 1;
2015 }
2016
2017 static unsigned int
2018 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
2019 {
2020         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2021         unsigned int cpp = fb->format->cpp[color_plane];
2022
2023         switch (fb->modifier) {
2024         case DRM_FORMAT_MOD_LINEAR:
2025                 return intel_tile_size(dev_priv);
2026         case I915_FORMAT_MOD_X_TILED:
2027                 if (IS_GEN(dev_priv, 2))
2028                         return 128;
2029                 else
2030                         return 512;
2031         case I915_FORMAT_MOD_Y_TILED_CCS:
2032                 if (is_ccs_plane(fb, color_plane))
2033                         return 128;
2034                 fallthrough;
2035         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2036         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2037                 if (is_ccs_plane(fb, color_plane))
2038                         return 64;
2039                 fallthrough;
2040         case I915_FORMAT_MOD_Y_TILED:
2041                 if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
2042                         return 128;
2043                 else
2044                         return 512;
2045         case I915_FORMAT_MOD_Yf_TILED_CCS:
2046                 if (is_ccs_plane(fb, color_plane))
2047                         return 128;
2048                 fallthrough;
2049         case I915_FORMAT_MOD_Yf_TILED:
2050                 switch (cpp) {
2051                 case 1:
2052                         return 64;
2053                 case 2:
2054                 case 4:
2055                         return 128;
2056                 case 8:
2057                 case 16:
2058                         return 256;
2059                 default:
2060                         MISSING_CASE(cpp);
2061                         return cpp;
2062                 }
2063                 break;
2064         default:
2065                 MISSING_CASE(fb->modifier);
2066                 return cpp;
2067         }
2068 }
2069
2070 static unsigned int
2071 intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
2072 {
2073         if (is_gen12_ccs_plane(fb, color_plane))
2074                 return 1;
2075
2076         return intel_tile_size(to_i915(fb->dev)) /
2077                 intel_tile_width_bytes(fb, color_plane);
2078 }
2079
2080 /* Return the tile dimensions in pixel units */
2081 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
2082                             unsigned int *tile_width,
2083                             unsigned int *tile_height)
2084 {
2085         unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
2086         unsigned int cpp = fb->format->cpp[color_plane];
2087
2088         *tile_width = tile_width_bytes / cpp;
2089         *tile_height = intel_tile_height(fb, color_plane);
2090 }
2091
2092 static unsigned int intel_tile_row_size(const struct drm_framebuffer *fb,
2093                                         int color_plane)
2094 {
2095         unsigned int tile_width, tile_height;
2096
2097         intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2098
2099         return fb->pitches[color_plane] * tile_height;
2100 }
2101
2102 unsigned int
2103 intel_fb_align_height(const struct drm_framebuffer *fb,
2104                       int color_plane, unsigned int height)
2105 {
2106         unsigned int tile_height = intel_tile_height(fb, color_plane);
2107
2108         return ALIGN(height, tile_height);
2109 }
2110
2111 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2112 {
2113         unsigned int size = 0;
2114         int i;
2115
2116         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2117                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2118
2119         return size;
2120 }
2121
2122 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
2123 {
2124         unsigned int size = 0;
2125         int i;
2126
2127         for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++)
2128                 size += rem_info->plane[i].width * rem_info->plane[i].height;
2129
2130         return size;
2131 }
2132
2133 static void
2134 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2135                         const struct drm_framebuffer *fb,
2136                         unsigned int rotation)
2137 {
2138         view->type = I915_GGTT_VIEW_NORMAL;
2139         if (drm_rotation_90_or_270(rotation)) {
2140                 view->type = I915_GGTT_VIEW_ROTATED;
2141                 view->rotated = to_intel_framebuffer(fb)->rot_info;
2142         }
2143 }
2144
2145 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2146 {
2147         if (IS_I830(dev_priv))
2148                 return 16 * 1024;
2149         else if (IS_I85X(dev_priv))
2150                 return 256;
2151         else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2152                 return 32;
2153         else
2154                 return 4 * 1024;
2155 }
2156
2157 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2158 {
2159         if (INTEL_GEN(dev_priv) >= 9)
2160                 return 256 * 1024;
2161         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2162                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2163                 return 128 * 1024;
2164         else if (INTEL_GEN(dev_priv) >= 4)
2165                 return 4 * 1024;
2166         else
2167                 return 0;
2168 }
2169
2170 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2171                                          int color_plane)
2172 {
2173         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2174
2175         /* AUX_DIST needs only 4K alignment */
2176         if ((INTEL_GEN(dev_priv) < 12 && is_aux_plane(fb, color_plane)) ||
2177             is_ccs_plane(fb, color_plane))
2178                 return 4096;
2179
2180         switch (fb->modifier) {
2181         case DRM_FORMAT_MOD_LINEAR:
2182                 return intel_linear_alignment(dev_priv);
2183         case I915_FORMAT_MOD_X_TILED:
2184                 if (INTEL_GEN(dev_priv) >= 9)
2185                         return 256 * 1024;
2186                 return 0;
2187         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2188                 if (is_semiplanar_uv_plane(fb, color_plane))
2189                         return intel_tile_row_size(fb, color_plane);
2190                 fallthrough;
2191         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2192                 return 16 * 1024;
2193         case I915_FORMAT_MOD_Y_TILED_CCS:
2194         case I915_FORMAT_MOD_Yf_TILED_CCS:
2195         case I915_FORMAT_MOD_Y_TILED:
2196                 if (INTEL_GEN(dev_priv) >= 12 &&
2197                     is_semiplanar_uv_plane(fb, color_plane))
2198                         return intel_tile_row_size(fb, color_plane);
2199                 fallthrough;
2200         case I915_FORMAT_MOD_Yf_TILED:
2201                 return 1 * 1024 * 1024;
2202         default:
2203                 MISSING_CASE(fb->modifier);
2204                 return 0;
2205         }
2206 }
2207
2208 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
2209 {
2210         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2211         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2212
2213         return INTEL_GEN(dev_priv) < 4 ||
2214                 (plane->has_fbc &&
2215                  plane_state->view.type == I915_GGTT_VIEW_NORMAL);
2216 }
2217
2218 struct i915_vma *
2219 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2220                            const struct i915_ggtt_view *view,
2221                            bool uses_fence,
2222                            unsigned long *out_flags)
2223 {
2224         struct drm_device *dev = fb->dev;
2225         struct drm_i915_private *dev_priv = to_i915(dev);
2226         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2227         intel_wakeref_t wakeref;
2228         struct i915_vma *vma;
2229         unsigned int pinctl;
2230         u32 alignment;
2231
2232         if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj)))
2233                 return ERR_PTR(-EINVAL);
2234
2235         alignment = intel_surf_alignment(fb, 0);
2236         if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment)))
2237                 return ERR_PTR(-EINVAL);
2238
2239         /* Note that the w/a also requires 64 PTE of padding following the
2240          * bo. We currently fill all unused PTE with the shadow page and so
2241          * we should always have valid PTE following the scanout preventing
2242          * the VT-d warning.
2243          */
2244         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2245                 alignment = 256 * 1024;
2246
2247         /*
2248          * Global gtt pte registers are special registers which actually forward
2249          * writes to a chunk of system memory. Which means that there is no risk
2250          * that the register values disappear as soon as we call
2251          * intel_runtime_pm_put(), so it is correct to wrap only the
2252          * pin/unpin/fence and not more.
2253          */
2254         wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
2255
2256         atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2257
2258         /*
2259          * Valleyview is definitely limited to scanning out the first
2260          * 512MiB. Lets presume this behaviour was inherited from the
2261          * g4x display engine and that all earlier gen are similarly
2262          * limited. Testing suggests that it is a little more
2263          * complicated than this. For example, Cherryview appears quite
2264          * happy to scanout from anywhere within its global aperture.
2265          */
2266         pinctl = 0;
2267         if (HAS_GMCH(dev_priv))
2268                 pinctl |= PIN_MAPPABLE;
2269
2270         vma = i915_gem_object_pin_to_display_plane(obj,
2271                                                    alignment, view, pinctl);
2272         if (IS_ERR(vma))
2273                 goto err;
2274
2275         if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
2276                 int ret;
2277
2278                 /*
2279                  * Install a fence for tiled scan-out. Pre-i965 always needs a
2280                  * fence, whereas 965+ only requires a fence if using
2281                  * framebuffer compression.  For simplicity, we always, when
2282                  * possible, install a fence as the cost is not that onerous.
2283                  *
2284                  * If we fail to fence the tiled scanout, then either the
2285                  * modeset will reject the change (which is highly unlikely as
2286                  * the affected systems, all but one, do not have unmappable
2287                  * space) or we will not be able to enable full powersaving
2288                  * techniques (also likely not to apply due to various limits
2289                  * FBC and the like impose on the size of the buffer, which
2290                  * presumably we violated anyway with this unmappable buffer).
2291                  * Anyway, it is presumably better to stumble onwards with
2292                  * something and try to run the system in a "less than optimal"
2293                  * mode that matches the user configuration.
2294                  */
2295                 ret = i915_vma_pin_fence(vma);
2296                 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
2297                         i915_gem_object_unpin_from_display_plane(vma);
2298                         vma = ERR_PTR(ret);
2299                         goto err;
2300                 }
2301
2302                 if (ret == 0 && vma->fence)
2303                         *out_flags |= PLANE_HAS_FENCE;
2304         }
2305
2306         i915_vma_get(vma);
2307 err:
2308         atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2309         intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
2310         return vma;
2311 }
2312
2313 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
2314 {
2315         i915_gem_object_lock(vma->obj, NULL);
2316         if (flags & PLANE_HAS_FENCE)
2317                 i915_vma_unpin_fence(vma);
2318         i915_gem_object_unpin_from_display_plane(vma);
2319         i915_gem_object_unlock(vma->obj);
2320
2321         i915_vma_put(vma);
2322 }
2323
2324 static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane,
2325                           unsigned int rotation)
2326 {
2327         if (drm_rotation_90_or_270(rotation))
2328                 return to_intel_framebuffer(fb)->rotated[color_plane].pitch;
2329         else
2330                 return fb->pitches[color_plane];
2331 }
2332
2333 /*
2334  * Convert the x/y offsets into a linear offset.
2335  * Only valid with 0/180 degree rotation, which is fine since linear
2336  * offset is only used with linear buffers on pre-hsw and tiled buffers
2337  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2338  */
2339 u32 intel_fb_xy_to_linear(int x, int y,
2340                           const struct intel_plane_state *state,
2341                           int color_plane)
2342 {
2343         const struct drm_framebuffer *fb = state->hw.fb;
2344         unsigned int cpp = fb->format->cpp[color_plane];
2345         unsigned int pitch = state->color_plane[color_plane].stride;
2346
2347         return y * pitch + x * cpp;
2348 }
2349
2350 /*
2351  * Add the x/y offsets derived from fb->offsets[] to the user
2352  * specified plane src x/y offsets. The resulting x/y offsets
2353  * specify the start of scanout from the beginning of the gtt mapping.
2354  */
2355 void intel_add_fb_offsets(int *x, int *y,
2356                           const struct intel_plane_state *state,
2357                           int color_plane)
2358
2359 {
2360         *x += state->color_plane[color_plane].x;
2361         *y += state->color_plane[color_plane].y;
2362 }
2363
2364 static u32 intel_adjust_tile_offset(int *x, int *y,
2365                                     unsigned int tile_width,
2366                                     unsigned int tile_height,
2367                                     unsigned int tile_size,
2368                                     unsigned int pitch_tiles,
2369                                     u32 old_offset,
2370                                     u32 new_offset)
2371 {
2372         unsigned int pitch_pixels = pitch_tiles * tile_width;
2373         unsigned int tiles;
2374
2375         WARN_ON(old_offset & (tile_size - 1));
2376         WARN_ON(new_offset & (tile_size - 1));
2377         WARN_ON(new_offset > old_offset);
2378
2379         tiles = (old_offset - new_offset) / tile_size;
2380
2381         *y += tiles / pitch_tiles * tile_height;
2382         *x += tiles % pitch_tiles * tile_width;
2383
2384         /* minimize x in case it got needlessly big */
2385         *y += *x / pitch_pixels * tile_height;
2386         *x %= pitch_pixels;
2387
2388         return new_offset;
2389 }
2390
2391 static bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
2392 {
2393         return fb->modifier == DRM_FORMAT_MOD_LINEAR ||
2394                is_gen12_ccs_plane(fb, color_plane);
2395 }
2396
2397 static u32 intel_adjust_aligned_offset(int *x, int *y,
2398                                        const struct drm_framebuffer *fb,
2399                                        int color_plane,
2400                                        unsigned int rotation,
2401                                        unsigned int pitch,
2402                                        u32 old_offset, u32 new_offset)
2403 {
2404         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2405         unsigned int cpp = fb->format->cpp[color_plane];
2406
2407         drm_WARN_ON(&dev_priv->drm, new_offset > old_offset);
2408
2409         if (!is_surface_linear(fb, color_plane)) {
2410                 unsigned int tile_size, tile_width, tile_height;
2411                 unsigned int pitch_tiles;
2412
2413                 tile_size = intel_tile_size(dev_priv);
2414                 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2415
2416                 if (drm_rotation_90_or_270(rotation)) {
2417                         pitch_tiles = pitch / tile_height;
2418                         swap(tile_width, tile_height);
2419                 } else {
2420                         pitch_tiles = pitch / (tile_width * cpp);
2421                 }
2422
2423                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2424                                          tile_size, pitch_tiles,
2425                                          old_offset, new_offset);
2426         } else {
2427                 old_offset += *y * pitch + *x * cpp;
2428
2429                 *y = (old_offset - new_offset) / pitch;
2430                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2431         }
2432
2433         return new_offset;
2434 }
2435
2436 /*
2437  * Adjust the tile offset by moving the difference into
2438  * the x/y offsets.
2439  */
2440 static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
2441                                              const struct intel_plane_state *state,
2442                                              int color_plane,
2443                                              u32 old_offset, u32 new_offset)
2444 {
2445         return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane,
2446                                            state->hw.rotation,
2447                                            state->color_plane[color_plane].stride,
2448                                            old_offset, new_offset);
2449 }
2450
2451 /*
2452  * Computes the aligned offset to the base tile and adjusts
2453  * x, y. bytes per pixel is assumed to be a power-of-two.
2454  *
2455  * In the 90/270 rotated case, x and y are assumed
2456  * to be already rotated to match the rotated GTT view, and
2457  * pitch is the tile_height aligned framebuffer height.
2458  *
2459  * This function is used when computing the derived information
2460  * under intel_framebuffer, so using any of that information
2461  * here is not allowed. Anything under drm_framebuffer can be
2462  * used. This is why the user has to pass in the pitch since it
2463  * is specified in the rotated orientation.
2464  */
2465 static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
2466                                         int *x, int *y,
2467                                         const struct drm_framebuffer *fb,
2468                                         int color_plane,
2469                                         unsigned int pitch,
2470                                         unsigned int rotation,
2471                                         u32 alignment)
2472 {
2473         unsigned int cpp = fb->format->cpp[color_plane];
2474         u32 offset, offset_aligned;
2475
2476         if (!is_surface_linear(fb, color_plane)) {
2477                 unsigned int tile_size, tile_width, tile_height;
2478                 unsigned int tile_rows, tiles, pitch_tiles;
2479
2480                 tile_size = intel_tile_size(dev_priv);
2481                 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2482
2483                 if (drm_rotation_90_or_270(rotation)) {
2484                         pitch_tiles = pitch / tile_height;
2485                         swap(tile_width, tile_height);
2486                 } else {
2487                         pitch_tiles = pitch / (tile_width * cpp);
2488                 }
2489
2490                 tile_rows = *y / tile_height;
2491                 *y %= tile_height;
2492
2493                 tiles = *x / tile_width;
2494                 *x %= tile_width;
2495
2496                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2497
2498                 offset_aligned = offset;
2499                 if (alignment)
2500                         offset_aligned = rounddown(offset_aligned, alignment);
2501
2502                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2503                                          tile_size, pitch_tiles,
2504                                          offset, offset_aligned);
2505         } else {
2506                 offset = *y * pitch + *x * cpp;
2507                 offset_aligned = offset;
2508                 if (alignment) {
2509                         offset_aligned = rounddown(offset_aligned, alignment);
2510                         *y = (offset % alignment) / pitch;
2511                         *x = ((offset % alignment) - *y * pitch) / cpp;
2512                 } else {
2513                         *y = *x = 0;
2514                 }
2515         }
2516
2517         return offset_aligned;
2518 }
2519
2520 static u32 intel_plane_compute_aligned_offset(int *x, int *y,
2521                                               const struct intel_plane_state *state,
2522                                               int color_plane)
2523 {
2524         struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane);
2525         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2526         const struct drm_framebuffer *fb = state->hw.fb;
2527         unsigned int rotation = state->hw.rotation;
2528         int pitch = state->color_plane[color_plane].stride;
2529         u32 alignment;
2530
2531         if (intel_plane->id == PLANE_CURSOR)
2532                 alignment = intel_cursor_alignment(dev_priv);
2533         else
2534                 alignment = intel_surf_alignment(fb, color_plane);
2535
2536         return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane,
2537                                             pitch, rotation, alignment);
2538 }
2539
2540 /* Convert the fb->offset[] into x/y offsets */
2541 static int intel_fb_offset_to_xy(int *x, int *y,
2542                                  const struct drm_framebuffer *fb,
2543                                  int color_plane)
2544 {
2545         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2546         unsigned int height;
2547         u32 alignment;
2548
2549         if (INTEL_GEN(dev_priv) >= 12 &&
2550             is_semiplanar_uv_plane(fb, color_plane))
2551                 alignment = intel_tile_row_size(fb, color_plane);
2552         else if (fb->modifier != DRM_FORMAT_MOD_LINEAR)
2553                 alignment = intel_tile_size(dev_priv);
2554         else
2555                 alignment = 0;
2556
2557         if (alignment != 0 && fb->offsets[color_plane] % alignment) {
2558                 drm_dbg_kms(&dev_priv->drm,
2559                             "Misaligned offset 0x%08x for color plane %d\n",
2560                             fb->offsets[color_plane], color_plane);
2561                 return -EINVAL;
2562         }
2563
2564         height = drm_framebuffer_plane_height(fb->height, fb, color_plane);
2565         height = ALIGN(height, intel_tile_height(fb, color_plane));
2566
2567         /* Catch potential overflows early */
2568         if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]),
2569                             fb->offsets[color_plane])) {
2570                 drm_dbg_kms(&dev_priv->drm,
2571                             "Bad offset 0x%08x or pitch %d for color plane %d\n",
2572                             fb->offsets[color_plane], fb->pitches[color_plane],
2573                             color_plane);
2574                 return -ERANGE;
2575         }
2576
2577         *x = 0;
2578         *y = 0;
2579
2580         intel_adjust_aligned_offset(x, y,
2581                                     fb, color_plane, DRM_MODE_ROTATE_0,
2582                                     fb->pitches[color_plane],
2583                                     fb->offsets[color_plane], 0);
2584
2585         return 0;
2586 }
2587
2588 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
2589 {
2590         switch (fb_modifier) {
2591         case I915_FORMAT_MOD_X_TILED:
2592                 return I915_TILING_X;
2593         case I915_FORMAT_MOD_Y_TILED:
2594         case I915_FORMAT_MOD_Y_TILED_CCS:
2595         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2596         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2597                 return I915_TILING_Y;
2598         default:
2599                 return I915_TILING_NONE;
2600         }
2601 }
2602
2603 /*
2604  * From the Sky Lake PRM:
2605  * "The Color Control Surface (CCS) contains the compression status of
2606  *  the cache-line pairs. The compression state of the cache-line pair
2607  *  is specified by 2 bits in the CCS. Each CCS cache-line represents
2608  *  an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2609  *  cache-line-pairs. CCS is always Y tiled."
2610  *
2611  * Since cache line pairs refers to horizontally adjacent cache lines,
2612  * each cache line in the CCS corresponds to an area of 32x16 cache
2613  * lines on the main surface. Since each pixel is 4 bytes, this gives
2614  * us a ratio of one byte in the CCS for each 8x16 pixels in the
2615  * main surface.
2616  */
2617 static const struct drm_format_info skl_ccs_formats[] = {
2618         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
2619           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2620         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
2621           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2622         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
2623           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2624         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
2625           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2626 };
2627
2628 /*
2629  * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
2630  * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
2631  * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
2632  * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
2633  * the main surface.
2634  */
2635 static const struct drm_format_info gen12_ccs_formats[] = {
2636         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
2637           .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2638           .hsub = 1, .vsub = 1, },
2639         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
2640           .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2641           .hsub = 1, .vsub = 1, },
2642         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
2643           .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2644           .hsub = 1, .vsub = 1, .has_alpha = true },
2645         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
2646           .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2647           .hsub = 1, .vsub = 1, .has_alpha = true },
2648         { .format = DRM_FORMAT_YUYV, .num_planes = 2,
2649           .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2650           .hsub = 2, .vsub = 1, .is_yuv = true },
2651         { .format = DRM_FORMAT_YVYU, .num_planes = 2,
2652           .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2653           .hsub = 2, .vsub = 1, .is_yuv = true },
2654         { .format = DRM_FORMAT_UYVY, .num_planes = 2,
2655           .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2656           .hsub = 2, .vsub = 1, .is_yuv = true },
2657         { .format = DRM_FORMAT_VYUY, .num_planes = 2,
2658           .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2659           .hsub = 2, .vsub = 1, .is_yuv = true },
2660         { .format = DRM_FORMAT_NV12, .num_planes = 4,
2661           .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
2662           .hsub = 2, .vsub = 2, .is_yuv = true },
2663         { .format = DRM_FORMAT_P010, .num_planes = 4,
2664           .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2665           .hsub = 2, .vsub = 2, .is_yuv = true },
2666         { .format = DRM_FORMAT_P012, .num_planes = 4,
2667           .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2668           .hsub = 2, .vsub = 2, .is_yuv = true },
2669         { .format = DRM_FORMAT_P016, .num_planes = 4,
2670           .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2671           .hsub = 2, .vsub = 2, .is_yuv = true },
2672 };
2673
2674 static const struct drm_format_info *
2675 lookup_format_info(const struct drm_format_info formats[],
2676                    int num_formats, u32 format)
2677 {
2678         int i;
2679
2680         for (i = 0; i < num_formats; i++) {
2681                 if (formats[i].format == format)
2682                         return &formats[i];
2683         }
2684
2685         return NULL;
2686 }
2687
2688 static const struct drm_format_info *
2689 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2690 {
2691         switch (cmd->modifier[0]) {
2692         case I915_FORMAT_MOD_Y_TILED_CCS:
2693         case I915_FORMAT_MOD_Yf_TILED_CCS:
2694                 return lookup_format_info(skl_ccs_formats,
2695                                           ARRAY_SIZE(skl_ccs_formats),
2696                                           cmd->pixel_format);
2697         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2698         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2699                 return lookup_format_info(gen12_ccs_formats,
2700                                           ARRAY_SIZE(gen12_ccs_formats),
2701                                           cmd->pixel_format);
2702         default:
2703                 return NULL;
2704         }
2705 }
2706
2707 bool is_ccs_modifier(u64 modifier)
2708 {
2709         return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
2710                modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
2711                modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2712                modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
2713 }
2714
2715 static int gen12_ccs_aux_stride(struct drm_framebuffer *fb, int ccs_plane)
2716 {
2717         return DIV_ROUND_UP(fb->pitches[ccs_to_main_plane(fb, ccs_plane)],
2718                             512) * 64;
2719 }
2720
2721 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
2722                               u32 pixel_format, u64 modifier)
2723 {
2724         struct intel_crtc *crtc;
2725         struct intel_plane *plane;
2726
2727         /*
2728          * We assume the primary plane for pipe A has
2729          * the highest stride limits of them all,
2730          * if in case pipe A is disabled, use the first pipe from pipe_mask.
2731          */
2732         crtc = intel_get_first_crtc(dev_priv);
2733         if (!crtc)
2734                 return 0;
2735
2736         plane = to_intel_plane(crtc->base.primary);
2737
2738         return plane->max_stride(plane, pixel_format, modifier,
2739                                  DRM_MODE_ROTATE_0);
2740 }
2741
2742 static
2743 u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
2744                         u32 pixel_format, u64 modifier)
2745 {
2746         /*
2747          * Arbitrary limit for gen4+ chosen to match the
2748          * render engine max stride.
2749          *
2750          * The new CCS hash mode makes remapping impossible
2751          */
2752         if (!is_ccs_modifier(modifier)) {
2753                 if (INTEL_GEN(dev_priv) >= 7)
2754                         return 256*1024;
2755                 else if (INTEL_GEN(dev_priv) >= 4)
2756                         return 128*1024;
2757         }
2758
2759         return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
2760 }
2761
2762 static u32
2763 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
2764 {
2765         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2766         u32 tile_width;
2767
2768         if (is_surface_linear(fb, color_plane)) {
2769                 u32 max_stride = intel_plane_fb_max_stride(dev_priv,
2770                                                            fb->format->format,
2771                                                            fb->modifier);
2772
2773                 /*
2774                  * To make remapping with linear generally feasible
2775                  * we need the stride to be page aligned.
2776                  */
2777                 if (fb->pitches[color_plane] > max_stride &&
2778                     !is_ccs_modifier(fb->modifier))
2779                         return intel_tile_size(dev_priv);
2780                 else
2781                         return 64;
2782         }
2783
2784         tile_width = intel_tile_width_bytes(fb, color_plane);
2785         if (is_ccs_modifier(fb->modifier)) {
2786                 /*
2787                  * Display WA #0531: skl,bxt,kbl,glk
2788                  *
2789                  * Render decompression and plane width > 3840
2790                  * combined with horizontal panning requires the
2791                  * plane stride to be a multiple of 4. We'll just
2792                  * require the entire fb to accommodate that to avoid
2793                  * potential runtime errors at plane configuration time.
2794                  */
2795                 if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb->width > 3840)
2796                         tile_width *= 4;
2797                 /*
2798                  * The main surface pitch must be padded to a multiple of four
2799                  * tile widths.
2800                  */
2801                 else if (INTEL_GEN(dev_priv) >= 12)
2802                         tile_width *= 4;
2803         }
2804         return tile_width;
2805 }
2806
2807 bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
2808 {
2809         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2810         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2811         const struct drm_framebuffer *fb = plane_state->hw.fb;
2812         int i;
2813
2814         /* We don't want to deal with remapping with cursors */
2815         if (plane->id == PLANE_CURSOR)
2816                 return false;
2817
2818         /*
2819          * The display engine limits already match/exceed the
2820          * render engine limits, so not much point in remapping.
2821          * Would also need to deal with the fence POT alignment
2822          * and gen2 2KiB GTT tile size.
2823          */
2824         if (INTEL_GEN(dev_priv) < 4)
2825                 return false;
2826
2827         /*
2828          * The new CCS hash mode isn't compatible with remapping as
2829          * the virtual address of the pages affects the compressed data.
2830          */
2831         if (is_ccs_modifier(fb->modifier))
2832                 return false;
2833
2834         /* Linear needs a page aligned stride for remapping */
2835         if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
2836                 unsigned int alignment = intel_tile_size(dev_priv) - 1;
2837
2838                 for (i = 0; i < fb->format->num_planes; i++) {
2839                         if (fb->pitches[i] & alignment)
2840                                 return false;
2841                 }
2842         }
2843
2844         return true;
2845 }
2846
2847 static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
2848 {
2849         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2850         const struct drm_framebuffer *fb = plane_state->hw.fb;
2851         unsigned int rotation = plane_state->hw.rotation;
2852         u32 stride, max_stride;
2853
2854         /*
2855          * No remapping for invisible planes since we don't have
2856          * an actual source viewport to remap.
2857          */
2858         if (!plane_state->uapi.visible)
2859                 return false;
2860
2861         if (!intel_plane_can_remap(plane_state))
2862                 return false;
2863
2864         /*
2865          * FIXME: aux plane limits on gen9+ are
2866          * unclear in Bspec, for now no checking.
2867          */
2868         stride = intel_fb_pitch(fb, 0, rotation);
2869         max_stride = plane->max_stride(plane, fb->format->format,
2870                                        fb->modifier, rotation);
2871
2872         return stride > max_stride;
2873 }
2874
2875 static void
2876 intel_fb_plane_get_subsampling(int *hsub, int *vsub,
2877                                const struct drm_framebuffer *fb,
2878                                int color_plane)
2879 {
2880         int main_plane;
2881
2882         if (color_plane == 0) {
2883                 *hsub = 1;
2884                 *vsub = 1;
2885
2886                 return;
2887         }
2888
2889         /*
2890          * TODO: Deduct the subsampling from the char block for all CCS
2891          * formats and planes.
2892          */
2893         if (!is_gen12_ccs_plane(fb, color_plane)) {
2894                 *hsub = fb->format->hsub;
2895                 *vsub = fb->format->vsub;
2896
2897                 return;
2898         }
2899
2900         main_plane = ccs_to_main_plane(fb, color_plane);
2901         *hsub = drm_format_info_block_width(fb->format, color_plane) /
2902                 drm_format_info_block_width(fb->format, main_plane);
2903
2904         /*
2905          * The min stride check in the core framebuffer_check() function
2906          * assumes that format->hsub applies to every plane except for the
2907          * first plane. That's incorrect for the CCS AUX plane of the first
2908          * plane, but for the above check to pass we must define the block
2909          * width with that subsampling applied to it. Adjust the width here
2910          * accordingly, so we can calculate the actual subsampling factor.
2911          */
2912         if (main_plane == 0)
2913                 *hsub *= fb->format->hsub;
2914
2915         *vsub = 32;
2916 }
2917 static int
2918 intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int ccs_plane, int x, int y)
2919 {
2920         struct drm_i915_private *i915 = to_i915(fb->dev);
2921         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2922         int main_plane;
2923         int hsub, vsub;
2924         int tile_width, tile_height;
2925         int ccs_x, ccs_y;
2926         int main_x, main_y;
2927
2928         if (!is_ccs_plane(fb, ccs_plane))
2929                 return 0;
2930
2931         intel_tile_dims(fb, ccs_plane, &tile_width, &tile_height);
2932         intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
2933
2934         tile_width *= hsub;
2935         tile_height *= vsub;
2936
2937         ccs_x = (x * hsub) % tile_width;
2938         ccs_y = (y * vsub) % tile_height;
2939
2940         main_plane = ccs_to_main_plane(fb, ccs_plane);
2941         main_x = intel_fb->normal[main_plane].x % tile_width;
2942         main_y = intel_fb->normal[main_plane].y % tile_height;
2943
2944         /*
2945          * CCS doesn't have its own x/y offset register, so the intra CCS tile
2946          * x/y offsets must match between CCS and the main surface.
2947          */
2948         if (main_x != ccs_x || main_y != ccs_y) {
2949                 drm_dbg_kms(&i915->drm,
2950                               "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2951                               main_x, main_y,
2952                               ccs_x, ccs_y,
2953                               intel_fb->normal[main_plane].x,
2954                               intel_fb->normal[main_plane].y,
2955                               x, y);
2956                 return -EINVAL;
2957         }
2958
2959         return 0;
2960 }
2961
2962 static void
2963 intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int color_plane)
2964 {
2965         int main_plane = is_ccs_plane(fb, color_plane) ?
2966                          ccs_to_main_plane(fb, color_plane) : 0;
2967         int main_hsub, main_vsub;
2968         int hsub, vsub;
2969
2970         intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, main_plane);
2971         intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
2972         *w = fb->width / main_hsub / hsub;
2973         *h = fb->height / main_vsub / vsub;
2974 }
2975
2976 /*
2977  * Setup the rotated view for an FB plane and return the size the GTT mapping
2978  * requires for this view.
2979  */
2980 static u32
2981 setup_fb_rotation(int plane, const struct intel_remapped_plane_info *plane_info,
2982                   u32 gtt_offset_rotated, int x, int y,
2983                   unsigned int width, unsigned int height,
2984                   unsigned int tile_size,
2985                   unsigned int tile_width, unsigned int tile_height,
2986                   struct drm_framebuffer *fb)
2987 {
2988         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2989         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2990         unsigned int pitch_tiles;
2991         struct drm_rect r;
2992
2993         /* Y or Yf modifiers required for 90/270 rotation */
2994         if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
2995             fb->modifier != I915_FORMAT_MOD_Yf_TILED)
2996                 return 0;
2997
2998         if (drm_WARN_ON(fb->dev, plane >= ARRAY_SIZE(rot_info->plane)))
2999                 return 0;
3000
3001         rot_info->plane[plane] = *plane_info;
3002
3003         intel_fb->rotated[plane].pitch = plane_info->height * tile_height;
3004
3005         /* rotate the x/y offsets to match the GTT view */
3006         drm_rect_init(&r, x, y, width, height);
3007         drm_rect_rotate(&r,
3008                         plane_info->width * tile_width,
3009                         plane_info->height * tile_height,
3010                         DRM_MODE_ROTATE_270);
3011         x = r.x1;
3012         y = r.y1;
3013
3014         /* rotate the tile dimensions to match the GTT view */
3015         pitch_tiles = intel_fb->rotated[plane].pitch / tile_height;
3016         swap(tile_width, tile_height);
3017
3018         /*
3019          * We only keep the x/y offsets, so push all of the
3020          * gtt offset into the x/y offsets.
3021          */
3022         intel_adjust_tile_offset(&x, &y,
3023                                  tile_width, tile_height,
3024                                  tile_size, pitch_tiles,
3025                                  gtt_offset_rotated * tile_size, 0);
3026
3027         /*
3028          * First pixel of the framebuffer from
3029          * the start of the rotated gtt mapping.
3030          */
3031         intel_fb->rotated[plane].x = x;
3032         intel_fb->rotated[plane].y = y;
3033
3034         return plane_info->width * plane_info->height;
3035 }
3036
3037 static int
3038 intel_fill_fb_info(struct drm_i915_private *dev_priv,
3039                    struct drm_framebuffer *fb)
3040 {
3041         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3042         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3043         u32 gtt_offset_rotated = 0;
3044         unsigned int max_size = 0;
3045         int i, num_planes = fb->format->num_planes;
3046         unsigned int tile_size = intel_tile_size(dev_priv);
3047
3048         for (i = 0; i < num_planes; i++) {
3049                 unsigned int width, height;
3050                 unsigned int cpp, size;
3051                 u32 offset;
3052                 int x, y;
3053                 int ret;
3054
3055                 cpp = fb->format->cpp[i];
3056                 intel_fb_plane_dims(&width, &height, fb, i);
3057
3058                 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
3059                 if (ret) {
3060                         drm_dbg_kms(&dev_priv->drm,
3061                                     "bad fb plane %d offset: 0x%x\n",
3062                                     i, fb->offsets[i]);
3063                         return ret;
3064                 }
3065
3066                 ret = intel_fb_check_ccs_xy(fb, i, x, y);
3067                 if (ret)
3068                         return ret;
3069
3070                 /*
3071                  * The fence (if used) is aligned to the start of the object
3072                  * so having the framebuffer wrap around across the edge of the
3073                  * fenced region doesn't really work. We have no API to configure
3074                  * the fence start offset within the object (nor could we probably
3075                  * on gen2/3). So it's just easier if we just require that the
3076                  * fb layout agrees with the fence layout. We already check that the
3077                  * fb stride matches the fence stride elsewhere.
3078                  */
3079                 if (i == 0 && i915_gem_object_is_tiled(obj) &&
3080                     (x + width) * cpp > fb->pitches[i]) {
3081                         drm_dbg_kms(&dev_priv->drm,
3082                                     "bad fb plane %d offset: 0x%x\n",
3083                                      i, fb->offsets[i]);
3084                         return -EINVAL;
3085                 }
3086
3087                 /*
3088                  * First pixel of the framebuffer from
3089                  * the start of the normal gtt mapping.
3090                  */
3091                 intel_fb->normal[i].x = x;
3092                 intel_fb->normal[i].y = y;
3093
3094                 offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i,
3095                                                       fb->pitches[i],
3096                                                       DRM_MODE_ROTATE_0,
3097                                                       tile_size);
3098                 offset /= tile_size;
3099
3100                 if (!is_surface_linear(fb, i)) {
3101                         struct intel_remapped_plane_info plane_info;
3102                         unsigned int tile_width, tile_height;
3103
3104                         intel_tile_dims(fb, i, &tile_width, &tile_height);
3105
3106                         plane_info.offset = offset;
3107                         plane_info.stride = DIV_ROUND_UP(fb->pitches[i],
3108                                                          tile_width * cpp);
3109                         plane_info.width = DIV_ROUND_UP(x + width, tile_width);
3110                         plane_info.height = DIV_ROUND_UP(y + height,
3111                                                          tile_height);
3112
3113                         /* how many tiles does this plane need */
3114                         size = plane_info.stride * plane_info.height;
3115                         /*
3116                          * If the plane isn't horizontally tile aligned,
3117                          * we need one more tile.
3118                          */
3119                         if (x != 0)
3120                                 size++;
3121
3122                         gtt_offset_rotated +=
3123                                 setup_fb_rotation(i, &plane_info,
3124                                                   gtt_offset_rotated,
3125                                                   x, y, width, height,
3126                                                   tile_size,
3127                                                   tile_width, tile_height,
3128                                                   fb);
3129                 } else {
3130                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
3131                                             x * cpp, tile_size);
3132                 }
3133
3134                 /* how many tiles in total needed in the bo */
3135                 max_size = max(max_size, offset + size);
3136         }
3137
3138         if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
3139                 drm_dbg_kms(&dev_priv->drm,
3140                             "fb too big for bo (need %llu bytes, have %zu bytes)\n",
3141                             mul_u32_u32(max_size, tile_size), obj->base.size);
3142                 return -EINVAL;
3143         }
3144
3145         return 0;
3146 }
3147
3148 static void
3149 intel_plane_remap_gtt(struct intel_plane_state *plane_state)
3150 {
3151         struct drm_i915_private *dev_priv =
3152                 to_i915(plane_state->uapi.plane->dev);
3153         struct drm_framebuffer *fb = plane_state->hw.fb;
3154         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3155         struct intel_rotation_info *info = &plane_state->view.rotated;
3156         unsigned int rotation = plane_state->hw.rotation;
3157         int i, num_planes = fb->format->num_planes;
3158         unsigned int tile_size = intel_tile_size(dev_priv);
3159         unsigned int src_x, src_y;
3160         unsigned int src_w, src_h;
3161         u32 gtt_offset = 0;
3162
3163         memset(&plane_state->view, 0, sizeof(plane_state->view));
3164         plane_state->view.type = drm_rotation_90_or_270(rotation) ?
3165                 I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED;
3166
3167         src_x = plane_state->uapi.src.x1 >> 16;
3168         src_y = plane_state->uapi.src.y1 >> 16;
3169         src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
3170         src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
3171
3172         drm_WARN_ON(&dev_priv->drm, is_ccs_modifier(fb->modifier));
3173
3174         /* Make src coordinates relative to the viewport */
3175         drm_rect_translate(&plane_state->uapi.src,
3176                            -(src_x << 16), -(src_y << 16));
3177
3178         /* Rotate src coordinates to match rotated GTT view */
3179         if (drm_rotation_90_or_270(rotation))
3180                 drm_rect_rotate(&plane_state->uapi.src,
3181                                 src_w << 16, src_h << 16,
3182                                 DRM_MODE_ROTATE_270);
3183
3184         for (i = 0; i < num_planes; i++) {
3185                 unsigned int hsub = i ? fb->format->hsub : 1;
3186                 unsigned int vsub = i ? fb->format->vsub : 1;
3187                 unsigned int cpp = fb->format->cpp[i];
3188                 unsigned int tile_width, tile_height;
3189                 unsigned int width, height;
3190                 unsigned int pitch_tiles;
3191                 unsigned int x, y;
3192                 u32 offset;
3193
3194                 intel_tile_dims(fb, i, &tile_width, &tile_height);
3195
3196                 x = src_x / hsub;
3197                 y = src_y / vsub;
3198                 width = src_w / hsub;
3199                 height = src_h / vsub;
3200
3201                 /*
3202                  * First pixel of the src viewport from the
3203                  * start of the normal gtt mapping.
3204                  */
3205                 x += intel_fb->normal[i].x;
3206                 y += intel_fb->normal[i].y;
3207
3208                 offset = intel_compute_aligned_offset(dev_priv, &x, &y,
3209                                                       fb, i, fb->pitches[i],
3210                                                       DRM_MODE_ROTATE_0, tile_size);
3211                 offset /= tile_size;
3212
3213                 drm_WARN_ON(&dev_priv->drm, i >= ARRAY_SIZE(info->plane));
3214                 info->plane[i].offset = offset;
3215                 info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],
3216                                                      tile_width * cpp);
3217                 info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
3218                 info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
3219
3220                 if (drm_rotation_90_or_270(rotation)) {
3221                         struct drm_rect r;
3222
3223                         /* rotate the x/y offsets to match the GTT view */
3224                         drm_rect_init(&r, x, y, width, height);
3225                         drm_rect_rotate(&r,
3226                                         info->plane[i].width * tile_width,
3227                                         info->plane[i].height * tile_height,
3228                                         DRM_MODE_ROTATE_270);
3229                         x = r.x1;
3230                         y = r.y1;
3231
3232                         pitch_tiles = info->plane[i].height;
3233                         plane_state->color_plane[i].stride = pitch_tiles * tile_height;
3234
3235                         /* rotate the tile dimensions to match the GTT view */
3236                         swap(tile_width, tile_height);
3237                 } else {
3238                         pitch_tiles = info->plane[i].width;
3239                         plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp;
3240                 }
3241
3242                 /*
3243                  * We only keep the x/y offsets, so push all of the
3244                  * gtt offset into the x/y offsets.
3245                  */
3246                 intel_adjust_tile_offset(&x, &y,
3247                                          tile_width, tile_height,
3248                                          tile_size, pitch_tiles,
3249                                          gtt_offset * tile_size, 0);
3250
3251                 gtt_offset += info->plane[i].width * info->plane[i].height;
3252
3253                 plane_state->color_plane[i].offset = 0;
3254                 plane_state->color_plane[i].x = x;
3255                 plane_state->color_plane[i].y = y;
3256         }
3257 }
3258
3259 static int
3260 intel_plane_compute_gtt(struct intel_plane_state *plane_state)
3261 {
3262         const struct intel_framebuffer *fb =
3263                 to_intel_framebuffer(plane_state->hw.fb);
3264         unsigned int rotation = plane_state->hw.rotation;
3265         int i, num_planes;
3266
3267         if (!fb)
3268                 return 0;
3269
3270         num_planes = fb->base.format->num_planes;
3271
3272         if (intel_plane_needs_remap(plane_state)) {
3273                 intel_plane_remap_gtt(plane_state);
3274
3275                 /*
3276                  * Sometimes even remapping can't overcome
3277                  * the stride limitations :( Can happen with
3278                  * big plane sizes and suitably misaligned
3279                  * offsets.
3280                  */
3281                 return intel_plane_check_stride(plane_state);
3282         }
3283
3284         intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation);
3285
3286         for (i = 0; i < num_planes; i++) {
3287                 plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation);
3288                 plane_state->color_plane[i].offset = 0;
3289
3290                 if (drm_rotation_90_or_270(rotation)) {
3291                         plane_state->color_plane[i].x = fb->rotated[i].x;
3292                         plane_state->color_plane[i].y = fb->rotated[i].y;
3293                 } else {
3294                         plane_state->color_plane[i].x = fb->normal[i].x;
3295                         plane_state->color_plane[i].y = fb->normal[i].y;
3296                 }
3297         }
3298
3299         /* Rotate src coordinates to match rotated GTT view */
3300         if (drm_rotation_90_or_270(rotation))
3301                 drm_rect_rotate(&plane_state->uapi.src,
3302                                 fb->base.width << 16, fb->base.height << 16,
3303                                 DRM_MODE_ROTATE_270);
3304
3305         return intel_plane_check_stride(plane_state);
3306 }
3307
3308 static int i9xx_format_to_fourcc(int format)
3309 {
3310         switch (format) {
3311         case DISPPLANE_8BPP:
3312                 return DRM_FORMAT_C8;
3313         case DISPPLANE_BGRA555:
3314                 return DRM_FORMAT_ARGB1555;
3315         case DISPPLANE_BGRX555:
3316                 return DRM_FORMAT_XRGB1555;
3317         case DISPPLANE_BGRX565:
3318                 return DRM_FORMAT_RGB565;
3319         default:
3320         case DISPPLANE_BGRX888:
3321                 return DRM_FORMAT_XRGB8888;
3322         case DISPPLANE_RGBX888:
3323                 return DRM_FORMAT_XBGR8888;
3324         case DISPPLANE_BGRA888:
3325                 return DRM_FORMAT_ARGB8888;
3326         case DISPPLANE_RGBA888:
3327                 return DRM_FORMAT_ABGR8888;
3328         case DISPPLANE_BGRX101010:
3329                 return DRM_FORMAT_XRGB2101010;
3330         case DISPPLANE_RGBX101010:
3331                 return DRM_FORMAT_XBGR2101010;
3332         case DISPPLANE_BGRA101010:
3333                 return DRM_FORMAT_ARGB2101010;
3334         case DISPPLANE_RGBA101010:
3335                 return DRM_FORMAT_ABGR2101010;
3336         case DISPPLANE_RGBX161616:
3337                 return DRM_FORMAT_XBGR16161616F;
3338         }
3339 }
3340
3341 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
3342 {
3343         switch (format) {
3344         case PLANE_CTL_FORMAT_RGB_565:
3345                 return DRM_FORMAT_RGB565;
3346         case PLANE_CTL_FORMAT_NV12:
3347                 return DRM_FORMAT_NV12;
3348         case PLANE_CTL_FORMAT_XYUV:
3349                 return DRM_FORMAT_XYUV8888;
3350         case PLANE_CTL_FORMAT_P010:
3351                 return DRM_FORMAT_P010;
3352         case PLANE_CTL_FORMAT_P012:
3353                 return DRM_FORMAT_P012;
3354         case PLANE_CTL_FORMAT_P016:
3355                 return DRM_FORMAT_P016;
3356         case PLANE_CTL_FORMAT_Y210:
3357                 return DRM_FORMAT_Y210;
3358         case PLANE_CTL_FORMAT_Y212:
3359                 return DRM_FORMAT_Y212;
3360         case PLANE_CTL_FORMAT_Y216:
3361                 return DRM_FORMAT_Y216;
3362         case PLANE_CTL_FORMAT_Y410:
3363                 return DRM_FORMAT_XVYU2101010;
3364         case PLANE_CTL_FORMAT_Y412:
3365                 return DRM_FORMAT_XVYU12_16161616;
3366         case PLANE_CTL_FORMAT_Y416:
3367                 return DRM_FORMAT_XVYU16161616;
3368         default:
3369         case PLANE_CTL_FORMAT_XRGB_8888:
3370                 if (rgb_order) {
3371                         if (alpha)
3372                                 return DRM_FORMAT_ABGR8888;
3373                         else
3374                                 return DRM_FORMAT_XBGR8888;
3375                 } else {
3376                         if (alpha)
3377                                 return DRM_FORMAT_ARGB8888;
3378                         else
3379                                 return DRM_FORMAT_XRGB8888;
3380                 }
3381         case PLANE_CTL_FORMAT_XRGB_2101010:
3382                 if (rgb_order) {
3383                         if (alpha)
3384                                 return DRM_FORMAT_ABGR2101010;
3385                         else
3386                                 return DRM_FORMAT_XBGR2101010;
3387                 } else {
3388                         if (alpha)
3389                                 return DRM_FORMAT_ARGB2101010;
3390                         else
3391                                 return DRM_FORMAT_XRGB2101010;
3392                 }
3393         case PLANE_CTL_FORMAT_XRGB_16161616F:
3394                 if (rgb_order) {
3395                         if (alpha)
3396                                 return DRM_FORMAT_ABGR16161616F;
3397                         else
3398                                 return DRM_FORMAT_XBGR16161616F;
3399                 } else {
3400                         if (alpha)
3401                                 return DRM_FORMAT_ARGB16161616F;
3402                         else
3403                                 return DRM_FORMAT_XRGB16161616F;
3404                 }
3405         }
3406 }
3407
3408 static struct i915_vma *
3409 initial_plane_vma(struct drm_i915_private *i915,
3410                   struct intel_initial_plane_config *plane_config)
3411 {
3412         struct drm_i915_gem_object *obj;
3413         struct i915_vma *vma;
3414         u32 base, size;
3415
3416         if (plane_config->size == 0)
3417                 return NULL;
3418
3419         base = round_down(plane_config->base,
3420                           I915_GTT_MIN_ALIGNMENT);
3421         size = round_up(plane_config->base + plane_config->size,
3422                         I915_GTT_MIN_ALIGNMENT);
3423         size -= base;
3424
3425         /*
3426          * If the FB is too big, just don't use it since fbdev is not very
3427          * important and we should probably use that space with FBC or other
3428          * features.
3429          */
3430         if (size * 2 > i915->stolen_usable_size)
3431                 return NULL;
3432
3433         obj = i915_gem_object_create_stolen_for_preallocated(i915, base, size);
3434         if (IS_ERR(obj))
3435                 return NULL;
3436
3437         /*
3438          * Mark it WT ahead of time to avoid changing the
3439          * cache_level during fbdev initialization. The
3440          * unbind there would get stuck waiting for rcu.
3441          */
3442         i915_gem_object_set_cache_coherency(obj, HAS_WT(i915) ?
3443                                             I915_CACHE_WT : I915_CACHE_NONE);
3444
3445         switch (plane_config->tiling) {
3446         case I915_TILING_NONE:
3447                 break;
3448         case I915_TILING_X:
3449         case I915_TILING_Y:
3450                 obj->tiling_and_stride =
3451                         plane_config->fb->base.pitches[0] |
3452                         plane_config->tiling;
3453                 break;
3454         default:
3455                 MISSING_CASE(plane_config->tiling);
3456                 goto err_obj;
3457         }
3458
3459         vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
3460         if (IS_ERR(vma))
3461                 goto err_obj;
3462
3463         if (i915_ggtt_pin(vma, NULL, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base))
3464                 goto err_obj;
3465
3466         if (i915_gem_object_is_tiled(obj) &&
3467             !i915_vma_is_map_and_fenceable(vma))
3468                 goto err_obj;
3469
3470         return vma;
3471
3472 err_obj:
3473         i915_gem_object_put(obj);
3474         return NULL;
3475 }
3476
3477 static bool
3478 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
3479                               struct intel_initial_plane_config *plane_config)
3480 {
3481         struct drm_device *dev = crtc->base.dev;
3482         struct drm_i915_private *dev_priv = to_i915(dev);
3483         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
3484         struct drm_framebuffer *fb = &plane_config->fb->base;
3485         struct i915_vma *vma;
3486
3487         switch (fb->modifier) {
3488         case DRM_FORMAT_MOD_LINEAR:
3489         case I915_FORMAT_MOD_X_TILED:
3490         case I915_FORMAT_MOD_Y_TILED:
3491                 break;
3492         default:
3493                 drm_dbg(&dev_priv->drm,
3494                         "Unsupported modifier for initial FB: 0x%llx\n",
3495                         fb->modifier);
3496                 return false;
3497         }
3498
3499         vma = initial_plane_vma(dev_priv, plane_config);
3500         if (!vma)
3501                 return false;
3502
3503         mode_cmd.pixel_format = fb->format->format;
3504         mode_cmd.width = fb->width;
3505         mode_cmd.height = fb->height;
3506         mode_cmd.pitches[0] = fb->pitches[0];
3507         mode_cmd.modifier[0] = fb->modifier;
3508         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
3509
3510         if (intel_framebuffer_init(to_intel_framebuffer(fb),
3511                                    vma->obj, &mode_cmd)) {
3512                 drm_dbg_kms(&dev_priv->drm, "intel fb init failed\n");
3513                 goto err_vma;
3514         }
3515
3516         plane_config->vma = vma;
3517         return true;
3518
3519 err_vma:
3520         i915_vma_put(vma);
3521         return false;
3522 }
3523
3524 static void
3525 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
3526                         struct intel_plane_state *plane_state,
3527                         bool visible)
3528 {
3529         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
3530
3531         plane_state->uapi.visible = visible;
3532
3533         if (visible)
3534                 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
3535         else
3536                 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
3537 }
3538
3539 static void fixup_active_planes(struct intel_crtc_state *crtc_state)
3540 {
3541         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3542         struct drm_plane *plane;
3543
3544         /*
3545          * Active_planes aliases if multiple "primary" or cursor planes
3546          * have been used on the same (or wrong) pipe. plane_mask uses
3547          * unique ids, hence we can use that to reconstruct active_planes.
3548          */
3549         crtc_state->active_planes = 0;
3550
3551         drm_for_each_plane_mask(plane, &dev_priv->drm,
3552                                 crtc_state->uapi.plane_mask)
3553                 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
3554 }
3555
3556 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
3557                                          struct intel_plane *plane)
3558 {
3559         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3560         struct intel_crtc_state *crtc_state =
3561                 to_intel_crtc_state(crtc->base.state);
3562         struct intel_plane_state *plane_state =
3563                 to_intel_plane_state(plane->base.state);
3564
3565         drm_dbg_kms(&dev_priv->drm,
3566                     "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
3567                     plane->base.base.id, plane->base.name,
3568                     crtc->base.base.id, crtc->base.name);
3569
3570         intel_set_plane_visible(crtc_state, plane_state, false);
3571         fixup_active_planes(crtc_state);
3572         crtc_state->data_rate[plane->id] = 0;
3573         crtc_state->min_cdclk[plane->id] = 0;
3574
3575         if (plane->id == PLANE_PRIMARY)
3576                 hsw_disable_ips(crtc_state);
3577
3578         /*
3579          * Vblank time updates from the shadow to live plane control register
3580          * are blocked if the memory self-refresh mode is active at that
3581          * moment. So to make sure the plane gets truly disabled, disable
3582          * first the self-refresh mode. The self-refresh enable bit in turn
3583          * will be checked/applied by the HW only at the next frame start
3584          * event which is after the vblank start event, so we need to have a
3585          * wait-for-vblank between disabling the plane and the pipe.
3586          */
3587         if (HAS_GMCH(dev_priv) &&
3588             intel_set_memory_cxsr(dev_priv, false))
3589                 intel_wait_for_vblank(dev_priv, crtc->pipe);
3590
3591         /*
3592          * Gen2 reports pipe underruns whenever all planes are disabled.
3593          * So disable underrun reporting before all the planes get disabled.
3594          */
3595         if (IS_GEN(dev_priv, 2) && !crtc_state->active_planes)
3596                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
3597
3598         intel_disable_plane(plane, crtc_state);
3599 }
3600
3601 static struct intel_frontbuffer *
3602 to_intel_frontbuffer(struct drm_framebuffer *fb)
3603 {
3604         return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
3605 }
3606
3607 static void
3608 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
3609                              struct intel_initial_plane_config *plane_config)
3610 {
3611         struct drm_device *dev = intel_crtc->base.dev;
3612         struct drm_i915_private *dev_priv = to_i915(dev);
3613         struct drm_crtc *c;
3614         struct drm_plane *primary = intel_crtc->base.primary;
3615         struct drm_plane_state *plane_state = primary->state;
3616         struct intel_plane *intel_plane = to_intel_plane(primary);
3617         struct intel_plane_state *intel_state =
3618                 to_intel_plane_state(plane_state);
3619         struct drm_framebuffer *fb;
3620         struct i915_vma *vma;
3621
3622         if (!plane_config->fb)
3623                 return;
3624
3625         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
3626                 fb = &plane_config->fb->base;
3627                 vma = plane_config->vma;
3628                 goto valid_fb;
3629         }
3630
3631         /*
3632          * Failed to alloc the obj, check to see if we should share
3633          * an fb with another CRTC instead
3634          */
3635         for_each_crtc(dev, c) {
3636                 struct intel_plane_state *state;
3637
3638                 if (c == &intel_crtc->base)
3639                         continue;
3640
3641                 if (!to_intel_crtc(c)->active)
3642                         continue;
3643
3644                 state = to_intel_plane_state(c->primary->state);
3645                 if (!state->vma)
3646                         continue;
3647
3648                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
3649                         fb = state->hw.fb;
3650                         vma = state->vma;
3651                         goto valid_fb;
3652                 }
3653         }
3654
3655         /*
3656          * We've failed to reconstruct the BIOS FB.  Current display state
3657          * indicates that the primary plane is visible, but has a NULL FB,
3658          * which will lead to problems later if we don't fix it up.  The
3659          * simplest solution is to just disable the primary plane now and
3660          * pretend the BIOS never had it enabled.
3661          */
3662         intel_plane_disable_noatomic(intel_crtc, intel_plane);
3663
3664         return;
3665
3666 valid_fb:
3667         intel_state->hw.rotation = plane_config->rotation;
3668         intel_fill_fb_ggtt_view(&intel_state->view, fb,
3669                                 intel_state->hw.rotation);
3670         intel_state->color_plane[0].stride =
3671                 intel_fb_pitch(fb, 0, intel_state->hw.rotation);
3672
3673         __i915_vma_pin(vma);
3674         intel_state->vma = i915_vma_get(vma);
3675         if (intel_plane_uses_fence(intel_state) && i915_vma_pin_fence(vma) == 0)
3676                 if (vma->fence)
3677                         intel_state->flags |= PLANE_HAS_FENCE;
3678
3679         plane_state->src_x = 0;
3680         plane_state->src_y = 0;
3681         plane_state->src_w = fb->width << 16;
3682         plane_state->src_h = fb->height << 16;
3683
3684         plane_state->crtc_x = 0;
3685         plane_state->crtc_y = 0;
3686         plane_state->crtc_w = fb->width;
3687         plane_state->crtc_h = fb->height;
3688
3689         intel_state->uapi.src = drm_plane_state_src(plane_state);
3690         intel_state->uapi.dst = drm_plane_state_dest(plane_state);
3691
3692         if (plane_config->tiling)
3693                 dev_priv->preserve_bios_swizzle = true;
3694
3695         plane_state->fb = fb;
3696         drm_framebuffer_get(fb);
3697
3698         plane_state->crtc = &intel_crtc->base;
3699         intel_plane_copy_uapi_to_hw_state(intel_state, intel_state);
3700
3701         intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
3702
3703         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
3704                   &to_intel_frontbuffer(fb)->bits);
3705 }
3706
3707 static int skl_max_plane_width(const struct drm_framebuffer *fb,
3708                                int color_plane,
3709                                unsigned int rotation)
3710 {
3711         int cpp = fb->format->cpp[color_plane];
3712
3713         switch (fb->modifier) {
3714         case DRM_FORMAT_MOD_LINEAR:
3715         case I915_FORMAT_MOD_X_TILED:
3716                 /*
3717                  * Validated limit is 4k, but has 5k should
3718                  * work apart from the following features:
3719                  * - Ytile (already limited to 4k)
3720                  * - FP16 (already limited to 4k)
3721                  * - render compression (already limited to 4k)
3722                  * - KVMR sprite and cursor (don't care)
3723                  * - horizontal panning (TODO verify this)
3724                  * - pipe and plane scaling (TODO verify this)
3725                  */
3726                 if (cpp == 8)
3727                         return 4096;
3728                 else
3729                         return 5120;
3730         case I915_FORMAT_MOD_Y_TILED_CCS:
3731         case I915_FORMAT_MOD_Yf_TILED_CCS:
3732         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
3733                 /* FIXME AUX plane? */
3734         case I915_FORMAT_MOD_Y_TILED:
3735         case I915_FORMAT_MOD_Yf_TILED:
3736                 if (cpp == 8)
3737                         return 2048;
3738                 else
3739                         return 4096;
3740         default:
3741                 MISSING_CASE(fb->modifier);
3742                 return 2048;
3743         }
3744 }
3745
3746 static int glk_max_plane_width(const struct drm_framebuffer *fb,
3747                                int color_plane,
3748                                unsigned int rotation)
3749 {
3750         int cpp = fb->format->cpp[color_plane];
3751
3752         switch (fb->modifier) {
3753         case DRM_FORMAT_MOD_LINEAR:
3754         case I915_FORMAT_MOD_X_TILED:
3755                 if (cpp == 8)
3756                         return 4096;
3757                 else
3758                         return 5120;
3759         case I915_FORMAT_MOD_Y_TILED_CCS:
3760         case I915_FORMAT_MOD_Yf_TILED_CCS:
3761                 /* FIXME AUX plane? */
3762         case I915_FORMAT_MOD_Y_TILED:
3763         case I915_FORMAT_MOD_Yf_TILED:
3764                 if (cpp == 8)
3765                         return 2048;
3766                 else
3767                         return 5120;
3768         default:
3769                 MISSING_CASE(fb->modifier);
3770                 return 2048;
3771         }
3772 }
3773
3774 static int icl_min_plane_width(const struct drm_framebuffer *fb)
3775 {
3776         /* Wa_14011264657, Wa_14011050563: gen11+ */
3777         switch (fb->format->format) {
3778         case DRM_FORMAT_C8:
3779                 return 18;
3780         case DRM_FORMAT_RGB565:
3781                 return 10;
3782         case DRM_FORMAT_XRGB8888:
3783         case DRM_FORMAT_XBGR8888:
3784         case DRM_FORMAT_ARGB8888:
3785         case DRM_FORMAT_ABGR8888:
3786         case DRM_FORMAT_XRGB2101010:
3787         case DRM_FORMAT_XBGR2101010:
3788         case DRM_FORMAT_ARGB2101010:
3789         case DRM_FORMAT_ABGR2101010:
3790         case DRM_FORMAT_XVYU2101010:
3791         case DRM_FORMAT_Y212:
3792         case DRM_FORMAT_Y216:
3793                 return 6;
3794         case DRM_FORMAT_NV12:
3795                 return 20;
3796         case DRM_FORMAT_P010:
3797         case DRM_FORMAT_P012:
3798         case DRM_FORMAT_P016:
3799                 return 12;
3800         case DRM_FORMAT_XRGB16161616F:
3801         case DRM_FORMAT_XBGR16161616F:
3802         case DRM_FORMAT_ARGB16161616F:
3803         case DRM_FORMAT_ABGR16161616F:
3804         case DRM_FORMAT_XVYU12_16161616:
3805         case DRM_FORMAT_XVYU16161616:
3806                 return 4;
3807         default:
3808                 return 1;
3809         }
3810 }
3811
3812 static int icl_max_plane_width(const struct drm_framebuffer *fb,
3813                                int color_plane,
3814                                unsigned int rotation)
3815 {
3816         return 5120;
3817 }
3818
3819 static int skl_max_plane_height(void)
3820 {
3821         return 4096;
3822 }
3823
3824 static int icl_max_plane_height(void)
3825 {
3826         return 4320;
3827 }
3828
3829 static bool
3830 skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
3831                                int main_x, int main_y, u32 main_offset,
3832                                int ccs_plane)
3833 {
3834         const struct drm_framebuffer *fb = plane_state->hw.fb;
3835         int aux_x = plane_state->color_plane[ccs_plane].x;
3836         int aux_y = plane_state->color_plane[ccs_plane].y;
3837         u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
3838         u32 alignment = intel_surf_alignment(fb, ccs_plane);
3839         int hsub;
3840         int vsub;
3841
3842         intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
3843         while (aux_offset >= main_offset && aux_y <= main_y) {
3844                 int x, y;
3845
3846                 if (aux_x == main_x && aux_y == main_y)
3847                         break;
3848
3849                 if (aux_offset == 0)
3850                         break;
3851
3852                 x = aux_x / hsub;
3853                 y = aux_y / vsub;
3854                 aux_offset = intel_plane_adjust_aligned_offset(&x, &y,
3855                                                                plane_state,
3856                                                                ccs_plane,
3857                                                                aux_offset,
3858                                                                aux_offset -
3859                                                                 alignment);
3860                 aux_x = x * hsub + aux_x % hsub;
3861                 aux_y = y * vsub + aux_y % vsub;
3862         }
3863
3864         if (aux_x != main_x || aux_y != main_y)
3865                 return false;
3866
3867         plane_state->color_plane[ccs_plane].offset = aux_offset;
3868         plane_state->color_plane[ccs_plane].x = aux_x;
3869         plane_state->color_plane[ccs_plane].y = aux_y;
3870
3871         return true;
3872 }
3873
3874 unsigned int
3875 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
3876 {
3877         int x = 0, y = 0;
3878
3879         intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3880                                           plane_state->color_plane[0].offset, 0);
3881
3882         return y;
3883 }
3884
3885 static int skl_check_main_surface(struct intel_plane_state *plane_state)
3886 {
3887         struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev);
3888         const struct drm_framebuffer *fb = plane_state->hw.fb;
3889         unsigned int rotation = plane_state->hw.rotation;
3890         int x = plane_state->uapi.src.x1 >> 16;
3891         int y = plane_state->uapi.src.y1 >> 16;
3892         int w = drm_rect_width(&plane_state->uapi.src) >> 16;
3893         int h = drm_rect_height(&plane_state->uapi.src) >> 16;
3894         int max_width, min_width, max_height;
3895         u32 alignment, offset;
3896         int aux_plane = intel_main_to_aux_plane(fb, 0);
3897         u32 aux_offset = plane_state->color_plane[aux_plane].offset;
3898
3899         if (INTEL_GEN(dev_priv) >= 11) {
3900                 max_width = icl_max_plane_width(fb, 0, rotation);
3901                 min_width = icl_min_plane_width(fb);
3902         } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
3903                 max_width = glk_max_plane_width(fb, 0, rotation);
3904                 min_width = 1;
3905         } else {
3906                 max_width = skl_max_plane_width(fb, 0, rotation);
3907                 min_width = 1;
3908         }
3909
3910         if (INTEL_GEN(dev_priv) >= 11)
3911                 max_height = icl_max_plane_height();
3912         else
3913                 max_height = skl_max_plane_height();
3914
3915         if (w > max_width || w < min_width || h > max_height) {
3916                 drm_dbg_kms(&dev_priv->drm,
3917                             "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n",
3918                             w, h, min_width, max_width, max_height);
3919                 return -EINVAL;
3920         }
3921
3922         intel_add_fb_offsets(&x, &y, plane_state, 0);
3923         offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);
3924         alignment = intel_surf_alignment(fb, 0);
3925         if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment)))
3926                 return -EINVAL;
3927
3928         /*
3929          * AUX surface offset is specified as the distance from the
3930          * main surface offset, and it must be non-negative. Make
3931          * sure that is what we will get.
3932          */
3933         if (offset > aux_offset)
3934                 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3935                                                            offset, aux_offset & ~(alignment - 1));
3936
3937         /*
3938          * When using an X-tiled surface, the plane blows up
3939          * if the x offset + width exceed the stride.
3940          *
3941          * TODO: linear and Y-tiled seem fine, Yf untested,
3942          */
3943         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3944                 int cpp = fb->format->cpp[0];
3945
3946                 while ((x + w) * cpp > plane_state->color_plane[0].stride) {
3947                         if (offset == 0) {
3948                                 drm_dbg_kms(&dev_priv->drm,
3949                                             "Unable to find suitable display surface offset due to X-tiling\n");
3950                                 return -EINVAL;
3951                         }
3952
3953                         offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3954                                                                    offset, offset - alignment);
3955                 }
3956         }
3957
3958         /*
3959          * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3960          * they match with the main surface x/y offsets.
3961          */
3962         if (is_ccs_modifier(fb->modifier)) {
3963                 while (!skl_check_main_ccs_coordinates(plane_state, x, y,
3964                                                        offset, aux_plane)) {
3965                         if (offset == 0)
3966                                 break;
3967
3968                         offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3969                                                                    offset, offset - alignment);
3970                 }
3971
3972                 if (x != plane_state->color_plane[aux_plane].x ||
3973                     y != plane_state->color_plane[aux_plane].y) {
3974                         drm_dbg_kms(&dev_priv->drm,
3975                                     "Unable to find suitable display surface offset due to CCS\n");
3976                         return -EINVAL;
3977                 }
3978         }
3979
3980         plane_state->color_plane[0].offset = offset;
3981         plane_state->color_plane[0].x = x;
3982         plane_state->color_plane[0].y = y;
3983
3984         /*
3985          * Put the final coordinates back so that the src
3986          * coordinate checks will see the right values.
3987          */
3988         drm_rect_translate_to(&plane_state->uapi.src,
3989                               x << 16, y << 16);
3990
3991         return 0;
3992 }
3993
3994 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3995 {
3996         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
3997         const struct drm_framebuffer *fb = plane_state->hw.fb;
3998         unsigned int rotation = plane_state->hw.rotation;
3999         int uv_plane = 1;
4000         int max_width = skl_max_plane_width(fb, uv_plane, rotation);
4001         int max_height = 4096;
4002         int x = plane_state->uapi.src.x1 >> 17;
4003         int y = plane_state->uapi.src.y1 >> 17;
4004         int w = drm_rect_width(&plane_state->uapi.src) >> 17;
4005         int h = drm_rect_height(&plane_state->uapi.src) >> 17;
4006         u32 offset;
4007
4008         intel_add_fb_offsets(&x, &y, plane_state, uv_plane);
4009         offset = intel_plane_compute_aligned_offset(&x, &y,
4010                                                     plane_state, uv_plane);
4011
4012         /* FIXME not quite sure how/if these apply to the chroma plane */
4013         if (w > max_width || h > max_height) {
4014                 drm_dbg_kms(&i915->drm,
4015                             "CbCr source size %dx%d too big (limit %dx%d)\n",
4016                             w, h, max_width, max_height);
4017                 return -EINVAL;
4018         }
4019
4020         if (is_ccs_modifier(fb->modifier)) {
4021                 int ccs_plane = main_to_ccs_plane(fb, uv_plane);
4022                 int aux_offset = plane_state->color_plane[ccs_plane].offset;
4023                 int alignment = intel_surf_alignment(fb, uv_plane);
4024
4025                 if (offset > aux_offset)
4026                         offset = intel_plane_adjust_aligned_offset(&x, &y,
4027                                                                    plane_state,
4028                                                                    uv_plane,
4029                                                                    offset,
4030                                                                    aux_offset & ~(alignment - 1));
4031
4032                 while (!skl_check_main_ccs_coordinates(plane_state, x, y,
4033                                                        offset, ccs_plane)) {
4034                         if (offset == 0)
4035                                 break;
4036
4037                         offset = intel_plane_adjust_aligned_offset(&x, &y,
4038                                                                    plane_state,
4039                                                                    uv_plane,
4040                                                                    offset, offset - alignment);
4041                 }
4042
4043                 if (x != plane_state->color_plane[ccs_plane].x ||
4044                     y != plane_state->color_plane[ccs_plane].y) {
4045                         drm_dbg_kms(&i915->drm,
4046                                     "Unable to find suitable display surface offset due to CCS\n");
4047                         return -EINVAL;
4048                 }
4049         }
4050
4051         plane_state->color_plane[uv_plane].offset = offset;
4052         plane_state->color_plane[uv_plane].x = x;
4053         plane_state->color_plane[uv_plane].y = y;
4054
4055         return 0;
4056 }
4057
4058 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
4059 {
4060         const struct drm_framebuffer *fb = plane_state->hw.fb;
4061         int src_x = plane_state->uapi.src.x1 >> 16;
4062         int src_y = plane_state->uapi.src.y1 >> 16;
4063         u32 offset;
4064         int ccs_plane;
4065
4066         for (ccs_plane = 0; ccs_plane < fb->format->num_planes; ccs_plane++) {
4067                 int main_hsub, main_vsub;
4068                 int hsub, vsub;
4069                 int x, y;
4070
4071                 if (!is_ccs_plane(fb, ccs_plane))
4072                         continue;
4073
4074                 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb,
4075                                                ccs_to_main_plane(fb, ccs_plane));
4076                 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
4077
4078                 hsub *= main_hsub;
4079                 vsub *= main_vsub;
4080                 x = src_x / hsub;
4081                 y = src_y / vsub;
4082
4083                 intel_add_fb_offsets(&x, &y, plane_state, ccs_plane);
4084
4085                 offset = intel_plane_compute_aligned_offset(&x, &y,
4086                                                             plane_state,
4087                                                             ccs_plane);
4088
4089                 plane_state->color_plane[ccs_plane].offset = offset;
4090                 plane_state->color_plane[ccs_plane].x = (x * hsub +
4091                                                          src_x % hsub) /
4092                                                         main_hsub;
4093                 plane_state->color_plane[ccs_plane].y = (y * vsub +
4094                                                          src_y % vsub) /
4095                                                         main_vsub;
4096         }
4097
4098         return 0;
4099 }
4100
4101 int skl_check_plane_surface(struct intel_plane_state *plane_state)
4102 {
4103         const struct drm_framebuffer *fb = plane_state->hw.fb;
4104         int ret, i;
4105
4106         ret = intel_plane_compute_gtt(plane_state);
4107         if (ret)
4108                 return ret;
4109
4110         if (!plane_state->uapi.visible)
4111                 return 0;
4112
4113         /*
4114          * Handle the AUX surface first since the main surface setup depends on
4115          * it.
4116          */
4117         if (is_ccs_modifier(fb->modifier)) {
4118                 ret = skl_check_ccs_aux_surface(plane_state);
4119                 if (ret)
4120                         return ret;
4121         }
4122
4123         if (intel_format_info_is_yuv_semiplanar(fb->format,
4124                                                 fb->modifier)) {
4125                 ret = skl_check_nv12_aux_surface(plane_state);
4126                 if (ret)
4127                         return ret;
4128         }
4129
4130         for (i = fb->format->num_planes; i < ARRAY_SIZE(plane_state->color_plane); i++) {
4131                 plane_state->color_plane[i].offset = ~0xfff;
4132                 plane_state->color_plane[i].x = 0;
4133                 plane_state->color_plane[i].y = 0;
4134         }
4135
4136         ret = skl_check_main_surface(plane_state);
4137         if (ret)
4138                 return ret;
4139
4140         return 0;
4141 }
4142
4143 static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state,
4144                              const struct intel_plane_state *plane_state,
4145                              unsigned int *num, unsigned int *den)
4146 {
4147         const struct drm_framebuffer *fb = plane_state->hw.fb;
4148         unsigned int cpp = fb->format->cpp[0];
4149
4150         /*
4151          * g4x bspec says 64bpp pixel rate can't exceed 80%
4152          * of cdclk when the sprite plane is enabled on the
4153          * same pipe. ilk/snb bspec says 64bpp pixel rate is
4154          * never allowed to exceed 80% of cdclk. Let's just go
4155          * with the ilk/snb limit always.
4156          */
4157         if (cpp == 8) {
4158                 *num = 10;
4159                 *den = 8;
4160         } else {
4161                 *num = 1;
4162                 *den = 1;
4163         }
4164 }
4165
4166 static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
4167                                 const struct intel_plane_state *plane_state)
4168 {
4169         unsigned int pixel_rate;
4170         unsigned int num, den;
4171
4172         /*
4173          * Note that crtc_state->pixel_rate accounts for both
4174          * horizontal and vertical panel fitter downscaling factors.
4175          * Pre-HSW bspec tells us to only consider the horizontal
4176          * downscaling factor here. We ignore that and just consider
4177          * both for simplicity.
4178          */
4179         pixel_rate = crtc_state->pixel_rate;
4180
4181         i9xx_plane_ratio(crtc_state, plane_state, &num, &den);
4182
4183         /* two pixels per clock with double wide pipe */
4184         if (crtc_state->double_wide)
4185                 den *= 2;
4186
4187         return DIV_ROUND_UP(pixel_rate * num, den);
4188 }
4189
4190 unsigned int
4191 i9xx_plane_max_stride(struct intel_plane *plane,
4192                       u32 pixel_format, u64 modifier,
4193                       unsigned int rotation)
4194 {
4195         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4196
4197         if (!HAS_GMCH(dev_priv)) {
4198                 return 32*1024;
4199         } else if (INTEL_GEN(dev_priv) >= 4) {
4200                 if (modifier == I915_FORMAT_MOD_X_TILED)
4201                         return 16*1024;
4202                 else
4203                         return 32*1024;
4204         } else if (INTEL_GEN(dev_priv) >= 3) {
4205                 if (modifier == I915_FORMAT_MOD_X_TILED)
4206                         return 8*1024;
4207                 else
4208                         return 16*1024;
4209         } else {
4210                 if (plane->i9xx_plane == PLANE_C)
4211                         return 4*1024;
4212                 else
4213                         return 8*1024;
4214         }
4215 }
4216
4217 static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
4218 {
4219         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4220         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4221         u32 dspcntr = 0;
4222
4223         if (crtc_state->gamma_enable)
4224                 dspcntr |= DISPPLANE_GAMMA_ENABLE;
4225
4226         if (crtc_state->csc_enable)
4227                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
4228
4229         if (INTEL_GEN(dev_priv) < 5)
4230                 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
4231
4232         return dspcntr;
4233 }
4234
4235 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
4236                           const struct intel_plane_state *plane_state)
4237 {
4238         struct drm_i915_private *dev_priv =
4239                 to_i915(plane_state->uapi.plane->dev);
4240         const struct drm_framebuffer *fb = plane_state->hw.fb;
4241         unsigned int rotation = plane_state->hw.rotation;
4242         u32 dspcntr;
4243
4244         dspcntr = DISPLAY_PLANE_ENABLE;
4245
4246         if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
4247             IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
4248                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
4249
4250         switch (fb->format->format) {
4251         case DRM_FORMAT_C8:
4252                 dspcntr |= DISPPLANE_8BPP;
4253                 break;
4254         case DRM_FORMAT_XRGB1555:
4255                 dspcntr |= DISPPLANE_BGRX555;
4256                 break;
4257         case DRM_FORMAT_ARGB1555:
4258                 dspcntr |= DISPPLANE_BGRA555;
4259                 break;
4260         case DRM_FORMAT_RGB565:
4261                 dspcntr |= DISPPLANE_BGRX565;
4262                 break;
4263         case DRM_FORMAT_XRGB8888:
4264                 dspcntr |= DISPPLANE_BGRX888;
4265                 break;
4266         case DRM_FORMAT_XBGR8888:
4267                 dspcntr |= DISPPLANE_RGBX888;
4268                 break;
4269         case DRM_FORMAT_ARGB8888:
4270                 dspcntr |= DISPPLANE_BGRA888;
4271                 break;
4272         case DRM_FORMAT_ABGR8888:
4273                 dspcntr |= DISPPLANE_RGBA888;
4274                 break;
4275         case DRM_FORMAT_XRGB2101010:
4276                 dspcntr |= DISPPLANE_BGRX101010;
4277                 break;
4278         case DRM_FORMAT_XBGR2101010:
4279                 dspcntr |= DISPPLANE_RGBX101010;
4280                 break;
4281         case DRM_FORMAT_ARGB2101010:
4282                 dspcntr |= DISPPLANE_BGRA101010;
4283                 break;
4284         case DRM_FORMAT_ABGR2101010:
4285                 dspcntr |= DISPPLANE_RGBA101010;
4286                 break;
4287         case DRM_FORMAT_XBGR16161616F:
4288                 dspcntr |= DISPPLANE_RGBX161616;
4289                 break;
4290         default:
4291                 MISSING_CASE(fb->format->format);
4292                 return 0;
4293         }
4294
4295         if (INTEL_GEN(dev_priv) >= 4 &&
4296             fb->modifier == I915_FORMAT_MOD_X_TILED)
4297                 dspcntr |= DISPPLANE_TILED;
4298
4299         if (rotation & DRM_MODE_ROTATE_180)
4300                 dspcntr |= DISPPLANE_ROTATE_180;
4301
4302         if (rotation & DRM_MODE_REFLECT_X)
4303                 dspcntr |= DISPPLANE_MIRROR;
4304
4305         return dspcntr;
4306 }
4307
4308 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
4309 {
4310         struct drm_i915_private *dev_priv =
4311                 to_i915(plane_state->uapi.plane->dev);
4312         const struct drm_framebuffer *fb = plane_state->hw.fb;
4313         int src_x, src_y, src_w;
4314         u32 offset;
4315         int ret;
4316
4317         ret = intel_plane_compute_gtt(plane_state);
4318         if (ret)
4319                 return ret;
4320
4321         if (!plane_state->uapi.visible)
4322                 return 0;
4323
4324         src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
4325         src_x = plane_state->uapi.src.x1 >> 16;
4326         src_y = plane_state->uapi.src.y1 >> 16;
4327
4328         /* Undocumented hardware limit on i965/g4x/vlv/chv */
4329         if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048)
4330                 return -EINVAL;
4331
4332         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
4333
4334         if (INTEL_GEN(dev_priv) >= 4)
4335                 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
4336                                                             plane_state, 0);
4337         else
4338                 offset = 0;
4339
4340         /*
4341          * Put the final coordinates back so that the src
4342          * coordinate checks will see the right values.
4343          */
4344         drm_rect_translate_to(&plane_state->uapi.src,
4345                               src_x << 16, src_y << 16);
4346
4347         /* HSW/BDW do this automagically in hardware */
4348         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
4349                 unsigned int rotation = plane_state->hw.rotation;
4350                 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
4351                 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
4352
4353                 if (rotation & DRM_MODE_ROTATE_180) {
4354                         src_x += src_w - 1;
4355                         src_y += src_h - 1;
4356                 } else if (rotation & DRM_MODE_REFLECT_X) {
4357                         src_x += src_w - 1;
4358                 }
4359         }
4360
4361         plane_state->color_plane[0].offset = offset;
4362         plane_state->color_plane[0].x = src_x;
4363         plane_state->color_plane[0].y = src_y;
4364
4365         return 0;
4366 }
4367
4368 static bool i9xx_plane_has_windowing(struct intel_plane *plane)
4369 {
4370         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4371         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4372
4373         if (IS_CHERRYVIEW(dev_priv))
4374                 return i9xx_plane == PLANE_B;
4375         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
4376                 return false;
4377         else if (IS_GEN(dev_priv, 4))
4378                 return i9xx_plane == PLANE_C;
4379         else
4380                 return i9xx_plane == PLANE_B ||
4381                         i9xx_plane == PLANE_C;
4382 }
4383
4384 static int
4385 i9xx_plane_check(struct intel_crtc_state *crtc_state,
4386                  struct intel_plane_state *plane_state)
4387 {
4388         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
4389         int ret;
4390
4391         ret = chv_plane_check_rotation(plane_state);
4392         if (ret)
4393                 return ret;
4394
4395         ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
4396                                                   &crtc_state->uapi,
4397                                                   DRM_PLANE_HELPER_NO_SCALING,
4398                                                   DRM_PLANE_HELPER_NO_SCALING,
4399                                                   i9xx_plane_has_windowing(plane),
4400                                                   true);
4401         if (ret)
4402                 return ret;
4403
4404         ret = i9xx_check_plane_surface(plane_state);
4405         if (ret)
4406                 return ret;
4407
4408         if (!plane_state->uapi.visible)
4409                 return 0;
4410
4411         ret = intel_plane_check_src_coordinates(plane_state);
4412         if (ret)
4413                 return ret;
4414
4415         plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
4416
4417         return 0;
4418 }
4419
4420 static void i9xx_update_plane(struct intel_plane *plane,
4421                               const struct intel_crtc_state *crtc_state,
4422                               const struct intel_plane_state *plane_state)
4423 {
4424         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4425         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4426         u32 linear_offset;
4427         int x = plane_state->color_plane[0].x;
4428         int y = plane_state->color_plane[0].y;
4429         int crtc_x = plane_state->uapi.dst.x1;
4430         int crtc_y = plane_state->uapi.dst.y1;
4431         int crtc_w = drm_rect_width(&plane_state->uapi.dst);
4432         int crtc_h = drm_rect_height(&plane_state->uapi.dst);
4433         unsigned long irqflags;
4434         u32 dspaddr_offset;
4435         u32 dspcntr;
4436
4437         dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
4438
4439         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
4440
4441         if (INTEL_GEN(dev_priv) >= 4)
4442                 dspaddr_offset = plane_state->color_plane[0].offset;
4443         else
4444                 dspaddr_offset = linear_offset;
4445
4446         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4447
4448         intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane),
4449                           plane_state->color_plane[0].stride);
4450
4451         if (INTEL_GEN(dev_priv) < 4) {
4452                 /*
4453                  * PLANE_A doesn't actually have a full window
4454                  * generator but let's assume we still need to
4455                  * program whatever is there.
4456                  */
4457                 intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),
4458                                   (crtc_y << 16) | crtc_x);
4459                 intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
4460                                   ((crtc_h - 1) << 16) | (crtc_w - 1));
4461         } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
4462                 intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane),
4463                                   (crtc_y << 16) | crtc_x);
4464                 intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane),
4465                                   ((crtc_h - 1) << 16) | (crtc_w - 1));
4466                 intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0);
4467         }
4468
4469         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
4470                 intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane),
4471                                   (y << 16) | x);
4472         } else if (INTEL_GEN(dev_priv) >= 4) {
4473                 intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane),
4474                                   linear_offset);
4475                 intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane),
4476                                   (y << 16) | x);
4477         }
4478
4479         /*
4480          * The control register self-arms if the plane was previously
4481          * disabled. Try to make the plane enable atomic by writing
4482          * the control register just before the surface register.
4483          */
4484         intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
4485         if (INTEL_GEN(dev_priv) >= 4)
4486                 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
4487                                   intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
4488         else
4489                 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
4490                                   intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
4491
4492         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4493 }
4494
4495 static void i9xx_disable_plane(struct intel_plane *plane,
4496                                const struct intel_crtc_state *crtc_state)
4497 {
4498         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4499         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4500         unsigned long irqflags;
4501         u32 dspcntr;
4502
4503         /*
4504          * DSPCNTR pipe gamma enable on g4x+ and pipe csc
4505          * enable on ilk+ affect the pipe bottom color as
4506          * well, so we must configure them even if the plane
4507          * is disabled.
4508          *
4509          * On pre-g4x there is no way to gamma correct the
4510          * pipe bottom color but we'll keep on doing this
4511          * anyway so that the crtc state readout works correctly.
4512          */
4513         dspcntr = i9xx_plane_ctl_crtc(crtc_state);
4514
4515         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4516
4517         intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
4518         if (INTEL_GEN(dev_priv) >= 4)
4519                 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0);
4520         else
4521                 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0);
4522
4523         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4524 }
4525
4526 static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
4527                                     enum pipe *pipe)
4528 {
4529         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4530         enum intel_display_power_domain power_domain;
4531         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4532         intel_wakeref_t wakeref;
4533         bool ret;
4534         u32 val;
4535
4536         /*
4537          * Not 100% correct for planes that can move between pipes,
4538          * but that's only the case for gen2-4 which don't have any
4539          * display power wells.
4540          */
4541         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
4542         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
4543         if (!wakeref)
4544                 return false;
4545
4546         val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
4547
4548         ret = val & DISPLAY_PLANE_ENABLE;
4549
4550         if (INTEL_GEN(dev_priv) >= 5)
4551                 *pipe = plane->pipe;
4552         else
4553                 *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
4554                         DISPPLANE_SEL_PIPE_SHIFT;
4555
4556         intel_display_power_put(dev_priv, power_domain, wakeref);
4557
4558         return ret;
4559 }
4560
4561 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
4562 {
4563         struct drm_device *dev = intel_crtc->base.dev;
4564         struct drm_i915_private *dev_priv = to_i915(dev);
4565         unsigned long irqflags;
4566
4567         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4568
4569         intel_de_write_fw(dev_priv, SKL_PS_CTRL(intel_crtc->pipe, id), 0);
4570         intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
4571         intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
4572
4573         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4574 }
4575
4576 /*
4577  * This function detaches (aka. unbinds) unused scalers in hardware
4578  */
4579 static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
4580 {
4581         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
4582         const struct intel_crtc_scaler_state *scaler_state =
4583                 &crtc_state->scaler_state;
4584         int i;
4585
4586         /* loop through and disable scalers that aren't in use */
4587         for (i = 0; i < intel_crtc->num_scalers; i++) {
4588                 if (!scaler_state->scalers[i].in_use)
4589                         skl_detach_scaler(intel_crtc, i);
4590         }
4591 }
4592
4593 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
4594                                           int color_plane, unsigned int rotation)
4595 {
4596         /*
4597          * The stride is either expressed as a multiple of 64 bytes chunks for
4598          * linear buffers or in number of tiles for tiled buffers.
4599          */
4600         if (is_surface_linear(fb, color_plane))
4601                 return 64;
4602         else if (drm_rotation_90_or_270(rotation))
4603                 return intel_tile_height(fb, color_plane);
4604         else
4605                 return intel_tile_width_bytes(fb, color_plane);
4606 }
4607
4608 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
4609                      int color_plane)
4610 {
4611         const struct drm_framebuffer *fb = plane_state->hw.fb;
4612         unsigned int rotation = plane_state->hw.rotation;
4613         u32 stride = plane_state->color_plane[color_plane].stride;
4614
4615         if (color_plane >= fb->format->num_planes)
4616                 return 0;
4617
4618         return stride / skl_plane_stride_mult(fb, color_plane, rotation);
4619 }
4620
4621 static u32 skl_plane_ctl_format(u32 pixel_format)
4622 {
4623         switch (pixel_format) {
4624         case DRM_FORMAT_C8:
4625                 return PLANE_CTL_FORMAT_INDEXED;
4626         case DRM_FORMAT_RGB565:
4627                 return PLANE_CTL_FORMAT_RGB_565;
4628         case DRM_FORMAT_XBGR8888:
4629         case DRM_FORMAT_ABGR8888:
4630                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
4631         case DRM_FORMAT_XRGB8888:
4632         case DRM_FORMAT_ARGB8888:
4633                 return PLANE_CTL_FORMAT_XRGB_8888;
4634         case DRM_FORMAT_XBGR2101010:
4635         case DRM_FORMAT_ABGR2101010:
4636                 return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX;
4637         case DRM_FORMAT_XRGB2101010:
4638         case DRM_FORMAT_ARGB2101010:
4639                 return PLANE_CTL_FORMAT_XRGB_2101010;
4640         case DRM_FORMAT_XBGR16161616F:
4641         case DRM_FORMAT_ABGR16161616F:
4642                 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
4643         case DRM_FORMAT_XRGB16161616F:
4644         case DRM_FORMAT_ARGB16161616F:
4645                 return PLANE_CTL_FORMAT_XRGB_16161616F;
4646         case DRM_FORMAT_XYUV8888:
4647                 return PLANE_CTL_FORMAT_XYUV;
4648         case DRM_FORMAT_YUYV:
4649                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
4650         case DRM_FORMAT_YVYU:
4651                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
4652         case DRM_FORMAT_UYVY:
4653                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
4654         case DRM_FORMAT_VYUY:
4655                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
4656         case DRM_FORMAT_NV12:
4657                 return PLANE_CTL_FORMAT_NV12;
4658         case DRM_FORMAT_P010:
4659                 return PLANE_CTL_FORMAT_P010;
4660         case DRM_FORMAT_P012:
4661                 return PLANE_CTL_FORMAT_P012;
4662         case DRM_FORMAT_P016:
4663                 return PLANE_CTL_FORMAT_P016;
4664         case DRM_FORMAT_Y210:
4665                 return PLANE_CTL_FORMAT_Y210;
4666         case DRM_FORMAT_Y212:
4667                 return PLANE_CTL_FORMAT_Y212;
4668         case DRM_FORMAT_Y216:
4669                 return PLANE_CTL_FORMAT_Y216;
4670         case DRM_FORMAT_XVYU2101010:
4671                 return PLANE_CTL_FORMAT_Y410;
4672         case DRM_FORMAT_XVYU12_16161616:
4673                 return PLANE_CTL_FORMAT_Y412;
4674         case DRM_FORMAT_XVYU16161616:
4675                 return PLANE_CTL_FORMAT_Y416;
4676         default:
4677                 MISSING_CASE(pixel_format);
4678         }
4679
4680         return 0;
4681 }
4682
4683 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
4684 {
4685         if (!plane_state->hw.fb->format->has_alpha)
4686                 return PLANE_CTL_ALPHA_DISABLE;
4687
4688         switch (plane_state->hw.pixel_blend_mode) {
4689         case DRM_MODE_BLEND_PIXEL_NONE:
4690                 return PLANE_CTL_ALPHA_DISABLE;
4691         case DRM_MODE_BLEND_PREMULTI:
4692                 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
4693         case DRM_MODE_BLEND_COVERAGE:
4694                 return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
4695         default:
4696                 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4697                 return PLANE_CTL_ALPHA_DISABLE;
4698         }
4699 }
4700
4701 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
4702 {
4703         if (!plane_state->hw.fb->format->has_alpha)
4704                 return PLANE_COLOR_ALPHA_DISABLE;
4705
4706         switch (plane_state->hw.pixel_blend_mode) {
4707         case DRM_MODE_BLEND_PIXEL_NONE:
4708                 return PLANE_COLOR_ALPHA_DISABLE;
4709         case DRM_MODE_BLEND_PREMULTI:
4710                 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
4711         case DRM_MODE_BLEND_COVERAGE:
4712                 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
4713         default:
4714                 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4715                 return PLANE_COLOR_ALPHA_DISABLE;
4716         }
4717 }
4718
4719 static u32 skl_plane_ctl_tiling(u64 fb_modifier)
4720 {
4721         switch (fb_modifier) {
4722         case DRM_FORMAT_MOD_LINEAR:
4723                 break;
4724         case I915_FORMAT_MOD_X_TILED:
4725                 return PLANE_CTL_TILED_X;
4726         case I915_FORMAT_MOD_Y_TILED:
4727                 return PLANE_CTL_TILED_Y;
4728         case I915_FORMAT_MOD_Y_TILED_CCS:
4729                 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4730         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
4731                 return PLANE_CTL_TILED_Y |
4732                        PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
4733                        PLANE_CTL_CLEAR_COLOR_DISABLE;
4734         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
4735                 return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
4736         case I915_FORMAT_MOD_Yf_TILED:
4737                 return PLANE_CTL_TILED_YF;
4738         case I915_FORMAT_MOD_Yf_TILED_CCS:
4739                 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4740         default:
4741                 MISSING_CASE(fb_modifier);
4742         }
4743
4744         return 0;
4745 }
4746
4747 static u32 skl_plane_ctl_rotate(unsigned int rotate)
4748 {
4749         switch (rotate) {
4750         case DRM_MODE_ROTATE_0:
4751                 break;
4752         /*
4753          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
4754          * while i915 HW rotation is clockwise, thats why this swapping.
4755          */
4756         case DRM_MODE_ROTATE_90:
4757                 return PLANE_CTL_ROTATE_270;
4758         case DRM_MODE_ROTATE_180:
4759                 return PLANE_CTL_ROTATE_180;
4760         case DRM_MODE_ROTATE_270:
4761                 return PLANE_CTL_ROTATE_90;
4762         default:
4763                 MISSING_CASE(rotate);
4764         }
4765
4766         return 0;
4767 }
4768
4769 static u32 cnl_plane_ctl_flip(unsigned int reflect)
4770 {
4771         switch (reflect) {
4772         case 0:
4773                 break;
4774         case DRM_MODE_REFLECT_X:
4775                 return PLANE_CTL_FLIP_HORIZONTAL;
4776         case DRM_MODE_REFLECT_Y:
4777         default:
4778                 MISSING_CASE(reflect);
4779         }
4780
4781         return 0;
4782 }
4783
4784 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
4785 {
4786         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4787         u32 plane_ctl = 0;
4788
4789         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4790                 return plane_ctl;
4791
4792         if (crtc_state->gamma_enable)
4793                 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
4794
4795         if (crtc_state->csc_enable)
4796                 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
4797
4798         return plane_ctl;
4799 }
4800
4801 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
4802                   const struct intel_plane_state *plane_state)
4803 {
4804         struct drm_i915_private *dev_priv =
4805                 to_i915(plane_state->uapi.plane->dev);
4806         const struct drm_framebuffer *fb = plane_state->hw.fb;
4807         unsigned int rotation = plane_state->hw.rotation;
4808         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
4809         u32 plane_ctl;
4810
4811         plane_ctl = PLANE_CTL_ENABLE;
4812
4813         if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
4814                 plane_ctl |= skl_plane_ctl_alpha(plane_state);
4815                 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
4816
4817                 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
4818                         plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
4819
4820                 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4821                         plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
4822         }
4823
4824         plane_ctl |= skl_plane_ctl_format(fb->format->format);
4825         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
4826         plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
4827
4828         if (INTEL_GEN(dev_priv) >= 10)
4829                 plane_ctl |= cnl_plane_ctl_flip(rotation &
4830                                                 DRM_MODE_REFLECT_MASK);
4831
4832         if (key->flags & I915_SET_COLORKEY_DESTINATION)
4833                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
4834         else if (key->flags & I915_SET_COLORKEY_SOURCE)
4835                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
4836
4837         return plane_ctl;
4838 }
4839
4840 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
4841 {
4842         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4843         u32 plane_color_ctl = 0;
4844
4845         if (INTEL_GEN(dev_priv) >= 11)
4846                 return plane_color_ctl;
4847
4848         if (crtc_state->gamma_enable)
4849                 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
4850
4851         if (crtc_state->csc_enable)
4852                 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
4853
4854         return plane_color_ctl;
4855 }
4856
4857 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
4858                         const struct intel_plane_state *plane_state)
4859 {
4860         struct drm_i915_private *dev_priv =
4861                 to_i915(plane_state->uapi.plane->dev);
4862         const struct drm_framebuffer *fb = plane_state->hw.fb;
4863         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
4864         u32 plane_color_ctl = 0;
4865
4866         plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
4867         plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
4868
4869         if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
4870                 switch (plane_state->hw.color_encoding) {
4871                 case DRM_COLOR_YCBCR_BT709:
4872                         plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
4873                         break;
4874                 case DRM_COLOR_YCBCR_BT2020:
4875                         plane_color_ctl |=
4876                                 PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020;
4877                         break;
4878                 default:
4879                         plane_color_ctl |=
4880                                 PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601;
4881                 }
4882                 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4883                         plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
4884         } else if (fb->format->is_yuv) {
4885                 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
4886         }
4887
4888         return plane_color_ctl;
4889 }
4890
4891 static int
4892 __intel_display_resume(struct drm_device *dev,
4893                        struct drm_atomic_state *state,
4894                        struct drm_modeset_acquire_ctx *ctx)
4895 {
4896         struct drm_crtc_state *crtc_state;
4897         struct drm_crtc *crtc;
4898         int i, ret;
4899
4900         intel_modeset_setup_hw_state(dev, ctx);
4901         intel_vga_redisable(to_i915(dev));
4902
4903         if (!state)
4904                 return 0;
4905
4906         /*
4907          * We've duplicated the state, pointers to the old state are invalid.
4908          *
4909          * Don't attempt to use the old state until we commit the duplicated state.
4910          */
4911         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
4912                 /*
4913                  * Force recalculation even if we restore
4914                  * current state. With fast modeset this may not result
4915                  * in a modeset when the state is compatible.
4916                  */
4917                 crtc_state->mode_changed = true;
4918         }
4919
4920         /* ignore any reset values/BIOS leftovers in the WM registers */
4921         if (!HAS_GMCH(to_i915(dev)))
4922                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
4923
4924         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
4925
4926         drm_WARN_ON(dev, ret == -EDEADLK);
4927         return ret;
4928 }
4929
4930 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
4931 {
4932         return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
4933                 intel_has_gpu_reset(&dev_priv->gt));
4934 }
4935
4936 void intel_prepare_reset(struct drm_i915_private *dev_priv)
4937 {
4938         struct drm_device *dev = &dev_priv->drm;
4939         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4940         struct drm_atomic_state *state;
4941         int ret;
4942
4943         /* reset doesn't touch the display */
4944         if (!dev_priv->params.force_reset_modeset_test &&
4945             !gpu_reset_clobbers_display(dev_priv))
4946                 return;
4947
4948         /* We have a modeset vs reset deadlock, defensively unbreak it. */
4949         set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4950         smp_mb__after_atomic();
4951         wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET);
4952
4953         if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
4954                 drm_dbg_kms(&dev_priv->drm,
4955                             "Modeset potentially stuck, unbreaking through wedging\n");
4956                 intel_gt_set_wedged(&dev_priv->gt);
4957         }
4958
4959         /*
4960          * Need mode_config.mutex so that we don't
4961          * trample ongoing ->detect() and whatnot.
4962          */
4963         mutex_lock(&dev->mode_config.mutex);
4964         drm_modeset_acquire_init(ctx, 0);
4965         while (1) {
4966                 ret = drm_modeset_lock_all_ctx(dev, ctx);
4967                 if (ret != -EDEADLK)
4968                         break;
4969
4970                 drm_modeset_backoff(ctx);
4971         }
4972         /*
4973          * Disabling the crtcs gracefully seems nicer. Also the
4974          * g33 docs say we should at least disable all the planes.
4975          */
4976         state = drm_atomic_helper_duplicate_state(dev, ctx);
4977         if (IS_ERR(state)) {
4978                 ret = PTR_ERR(state);
4979                 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n",
4980                         ret);
4981                 return;
4982         }
4983
4984         ret = drm_atomic_helper_disable_all(dev, ctx);
4985         if (ret) {
4986                 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
4987                         ret);
4988                 drm_atomic_state_put(state);
4989                 return;
4990         }
4991
4992         dev_priv->modeset_restore_state = state;
4993         state->acquire_ctx = ctx;
4994 }
4995
4996 void intel_finish_reset(struct drm_i915_private *dev_priv)
4997 {
4998         struct drm_device *dev = &dev_priv->drm;
4999         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
5000         struct drm_atomic_state *state;
5001         int ret;
5002
5003         /* reset doesn't touch the display */
5004         if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
5005                 return;
5006
5007         state = fetch_and_zero(&dev_priv->modeset_restore_state);
5008         if (!state)
5009                 goto unlock;
5010
5011         /* reset doesn't touch the display */
5012         if (!gpu_reset_clobbers_display(dev_priv)) {
5013                 /* for testing only restore the display */
5014                 ret = __intel_display_resume(dev, state, ctx);
5015                 if (ret)
5016                         drm_err(&dev_priv->drm,
5017                                 "Restoring old state failed with %i\n", ret);
5018         } else {
5019                 /*
5020                  * The display has been reset as well,
5021                  * so need a full re-initialization.
5022                  */
5023                 intel_pps_unlock_regs_wa(dev_priv);
5024                 intel_modeset_init_hw(dev_priv);
5025                 intel_init_clock_gating(dev_priv);
5026
5027                 spin_lock_irq(&dev_priv->irq_lock);
5028                 if (dev_priv->display.hpd_irq_setup)
5029                         dev_priv->display.hpd_irq_setup(dev_priv);
5030                 spin_unlock_irq(&dev_priv->irq_lock);
5031
5032                 ret = __intel_display_resume(dev, state, ctx);
5033                 if (ret)
5034                         drm_err(&dev_priv->drm,
5035                                 "Restoring old state failed with %i\n", ret);
5036
5037                 intel_hpd_init(dev_priv);
5038         }
5039
5040         drm_atomic_state_put(state);
5041 unlock:
5042         drm_modeset_drop_locks(ctx);
5043         drm_modeset_acquire_fini(ctx);
5044         mutex_unlock(&dev->mode_config.mutex);
5045
5046         clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
5047 }
5048
5049 static void icl_set_pipe_chicken(struct intel_crtc *crtc)
5050 {
5051         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5052         enum pipe pipe = crtc->pipe;
5053         u32 tmp;
5054
5055         tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe));
5056
5057         /*
5058          * Display WA #1153: icl
5059          * enable hardware to bypass the alpha math
5060          * and rounding for per-pixel values 00 and 0xff
5061          */
5062         tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
5063         /*
5064          * Display WA # 1605353570: icl
5065          * Set the pixel rounding bit to 1 for allowing
5066          * passthrough of Frame buffer pixels unmodified
5067          * across pipe
5068          */
5069         tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
5070         intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
5071 }
5072
5073 static void intel_fdi_normal_train(struct intel_crtc *crtc)
5074 {
5075         struct drm_device *dev = crtc->base.dev;
5076         struct drm_i915_private *dev_priv = to_i915(dev);
5077         enum pipe pipe = crtc->pipe;
5078         i915_reg_t reg;
5079         u32 temp;
5080
5081         /* enable normal train */
5082         reg = FDI_TX_CTL(pipe);
5083         temp = intel_de_read(dev_priv, reg);
5084         if (IS_IVYBRIDGE(dev_priv)) {
5085                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
5086                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
5087         } else {
5088                 temp &= ~FDI_LINK_TRAIN_NONE;
5089                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
5090         }
5091         intel_de_write(dev_priv, reg, temp);
5092
5093         reg = FDI_RX_CTL(pipe);
5094         temp = intel_de_read(dev_priv, reg);
5095         if (HAS_PCH_CPT(dev_priv)) {
5096                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5097                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
5098         } else {
5099                 temp &= ~FDI_LINK_TRAIN_NONE;
5100                 temp |= FDI_LINK_TRAIN_NONE;
5101         }
5102         intel_de_write(dev_priv, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
5103
5104         /* wait one idle pattern time */
5105         intel_de_posting_read(dev_priv, reg);
5106         udelay(1000);
5107
5108         /* IVB wants error correction enabled */
5109         if (IS_IVYBRIDGE(dev_priv))
5110                 intel_de_write(dev_priv, reg,
5111                                intel_de_read(dev_priv, reg) | FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE);
5112 }
5113
5114 /* The FDI link training functions for ILK/Ibexpeak. */
5115 static void ilk_fdi_link_train(struct intel_crtc *crtc,
5116                                const struct intel_crtc_state *crtc_state)
5117 {
5118         struct drm_device *dev = crtc->base.dev;
5119         struct drm_i915_private *dev_priv = to_i915(dev);
5120         enum pipe pipe = crtc->pipe;
5121         i915_reg_t reg;
5122         u32 temp, tries;
5123
5124         /* FDI needs bits from pipe first */
5125         assert_pipe_enabled(dev_priv, crtc_state->cpu_transcoder);
5126
5127         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5128            for train result */
5129         reg = FDI_RX_IMR(pipe);
5130         temp = intel_de_read(dev_priv, reg);
5131         temp &= ~FDI_RX_SYMBOL_LOCK;
5132         temp &= ~FDI_RX_BIT_LOCK;
5133         intel_de_write(dev_priv, reg, temp);
5134         intel_de_read(dev_priv, reg);
5135         udelay(150);
5136
5137         /* enable CPU FDI TX and PCH FDI RX */
5138         reg = FDI_TX_CTL(pipe);
5139         temp = intel_de_read(dev_priv, reg);
5140         temp &= ~FDI_DP_PORT_WIDTH_MASK;
5141         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5142         temp &= ~FDI_LINK_TRAIN_NONE;
5143         temp |= FDI_LINK_TRAIN_PATTERN_1;
5144         intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
5145
5146         reg = FDI_RX_CTL(pipe);
5147         temp = intel_de_read(dev_priv, reg);
5148         temp &= ~FDI_LINK_TRAIN_NONE;
5149         temp |= FDI_LINK_TRAIN_PATTERN_1;
5150         intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
5151
5152         intel_de_posting_read(dev_priv, reg);
5153         udelay(150);
5154
5155         /* Ironlake workaround, enable clock pointer after FDI enable*/
5156         intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
5157                        FDI_RX_PHASE_SYNC_POINTER_OVR);
5158         intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
5159                        FDI_RX_PHASE_SYNC_POINTER_OVR | FDI_RX_PHASE_SYNC_POINTER_EN);
5160
5161         reg = FDI_RX_IIR(pipe);
5162         for (tries = 0; tries < 5; tries++) {
5163                 temp = intel_de_read(dev_priv, reg);
5164                 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5165
5166                 if ((temp & FDI_RX_BIT_LOCK)) {
5167                         drm_dbg_kms(&dev_priv->drm, "FDI train 1 done.\n");
5168                         intel_de_write(dev_priv, reg, temp | FDI_RX_BIT_LOCK);
5169                         break;
5170                 }
5171         }
5172         if (tries == 5)
5173                 drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
5174
5175         /* Train 2 */
5176         reg = FDI_TX_CTL(pipe);
5177         temp = intel_de_read(dev_priv, reg);
5178         temp &= ~FDI_LINK_TRAIN_NONE;
5179         temp |= FDI_LINK_TRAIN_PATTERN_2;
5180         intel_de_write(dev_priv, reg, temp);
5181
5182         reg = FDI_RX_CTL(pipe);
5183         temp = intel_de_read(dev_priv, reg);
5184         temp &= ~FDI_LINK_TRAIN_NONE;
5185         temp |= FDI_LINK_TRAIN_PATTERN_2;
5186         intel_de_write(dev_priv, reg, temp);
5187
5188         intel_de_posting_read(dev_priv, reg);
5189         udelay(150);
5190
5191         reg = FDI_RX_IIR(pipe);
5192         for (tries = 0; tries < 5; tries++) {
5193                 temp = intel_de_read(dev_priv, reg);
5194                 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5195
5196                 if (temp & FDI_RX_SYMBOL_LOCK) {
5197                         intel_de_write(dev_priv, reg,
5198                                        temp | FDI_RX_SYMBOL_LOCK);
5199                         drm_dbg_kms(&dev_priv->drm, "FDI train 2 done.\n");
5200                         break;
5201                 }
5202         }
5203         if (tries == 5)
5204                 drm_err(&dev_priv->drm, "FDI train 2 fail!\n");
5205
5206         drm_dbg_kms(&dev_priv->drm, "FDI train done\n");
5207
5208 }
5209
5210 static const int snb_b_fdi_train_param[] = {
5211         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
5212         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
5213         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
5214         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
5215 };
5216
5217 /* The FDI link training functions for SNB/Cougarpoint. */
5218 static void gen6_fdi_link_train(struct intel_crtc *crtc,
5219                                 const struct intel_crtc_state *crtc_state)
5220 {
5221         struct drm_device *dev = crtc->base.dev;
5222         struct drm_i915_private *dev_priv = to_i915(dev);
5223         enum pipe pipe = crtc->pipe;
5224         i915_reg_t reg;
5225         u32 temp, i, retry;
5226
5227         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5228            for train result */
5229         reg = FDI_RX_IMR(pipe);
5230         temp = intel_de_read(dev_priv, reg);
5231         temp &= ~FDI_RX_SYMBOL_LOCK;
5232         temp &= ~FDI_RX_BIT_LOCK;
5233         intel_de_write(dev_priv, reg, temp);
5234
5235         intel_de_posting_read(dev_priv, reg);
5236         udelay(150);
5237
5238         /* enable CPU FDI TX and PCH FDI RX */
5239         reg = FDI_TX_CTL(pipe);
5240         temp = intel_de_read(dev_priv, reg);
5241         temp &= ~FDI_DP_PORT_WIDTH_MASK;
5242         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5243         temp &= ~FDI_LINK_TRAIN_NONE;
5244         temp |= FDI_LINK_TRAIN_PATTERN_1;
5245         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5246         /* SNB-B */
5247         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5248         intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
5249
5250         intel_de_write(dev_priv, FDI_RX_MISC(pipe),
5251                        FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
5252
5253         reg = FDI_RX_CTL(pipe);
5254         temp = intel_de_read(dev_priv, reg);
5255         if (HAS_PCH_CPT(dev_priv)) {
5256                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5257                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5258         } else {
5259                 temp &= ~FDI_LINK_TRAIN_NONE;
5260                 temp |= FDI_LINK_TRAIN_PATTERN_1;
5261         }
5262         intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
5263
5264         intel_de_posting_read(dev_priv, reg);
5265         udelay(150);
5266
5267         for (i = 0; i < 4; i++) {
5268                 reg = FDI_TX_CTL(pipe);
5269                 temp = intel_de_read(dev_priv, reg);
5270                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5271                 temp |= snb_b_fdi_train_param[i];
5272                 intel_de_write(dev_priv, reg, temp);
5273
5274                 intel_de_posting_read(dev_priv, reg);
5275                 udelay(500);
5276
5277                 for (retry = 0; retry < 5; retry++) {
5278                         reg = FDI_RX_IIR(pipe);
5279                         temp = intel_de_read(dev_priv, reg);
5280                         drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5281                         if (temp & FDI_RX_BIT_LOCK) {
5282                                 intel_de_write(dev_priv, reg,
5283                                                temp | FDI_RX_BIT_LOCK);
5284                                 drm_dbg_kms(&dev_priv->drm,
5285                                             "FDI train 1 done.\n");
5286                                 break;
5287                         }
5288                         udelay(50);
5289                 }
5290                 if (retry < 5)
5291                         break;
5292         }
5293         if (i == 4)
5294                 drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
5295
5296         /* Train 2 */
5297         reg = FDI_TX_CTL(pipe);
5298         temp = intel_de_read(dev_priv, reg);
5299         temp &= ~FDI_LINK_TRAIN_NONE;
5300         temp |= FDI_LINK_TRAIN_PATTERN_2;
5301         if (IS_GEN(dev_priv, 6)) {
5302                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5303                 /* SNB-B */
5304                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5305         }
5306         intel_de_write(dev_priv, reg, temp);
5307
5308         reg = FDI_RX_CTL(pipe);
5309         temp = intel_de_read(dev_priv, reg);
5310         if (HAS_PCH_CPT(dev_priv)) {
5311                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5312                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
5313         } else {
5314                 temp &= ~FDI_LINK_TRAIN_NONE;
5315                 temp |= FDI_LINK_TRAIN_PATTERN_2;
5316         }
5317         intel_de_write(dev_priv, reg, temp);
5318
5319         intel_de_posting_read(dev_priv, reg);
5320         udelay(150);
5321
5322         for (i = 0; i < 4; i++) {
5323                 reg = FDI_TX_CTL(pipe);
5324                 temp = intel_de_read(dev_priv, reg);
5325                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5326                 temp |= snb_b_fdi_train_param[i];
5327                 intel_de_write(dev_priv, reg, temp);
5328
5329                 intel_de_posting_read(dev_priv, reg);
5330                 udelay(500);
5331
5332                 for (retry = 0; retry < 5; retry++) {
5333                         reg = FDI_RX_IIR(pipe);
5334                         temp = intel_de_read(dev_priv, reg);
5335                         drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5336                         if (temp & FDI_RX_SYMBOL_LOCK) {
5337                                 intel_de_write(dev_priv, reg,
5338                                                temp | FDI_RX_SYMBOL_LOCK);
5339                                 drm_dbg_kms(&dev_priv->drm,
5340                                             "FDI train 2 done.\n");
5341                                 break;
5342                         }
5343                         udelay(50);
5344                 }
5345                 if (retry < 5)
5346                         break;
5347         }
5348         if (i == 4)
5349                 drm_err(&dev_priv->drm, "FDI train 2 fail!\n");
5350
5351         drm_dbg_kms(&dev_priv->drm, "FDI train done.\n");
5352 }
5353
5354 /* Manual link training for Ivy Bridge A0 parts */
5355 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
5356                                       const struct intel_crtc_state *crtc_state)
5357 {
5358         struct drm_device *dev = crtc->base.dev;
5359         struct drm_i915_private *dev_priv = to_i915(dev);
5360         enum pipe pipe = crtc->pipe;
5361         i915_reg_t reg;
5362         u32 temp, i, j;
5363
5364         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5365            for train result */
5366         reg = FDI_RX_IMR(pipe);
5367         temp = intel_de_read(dev_priv, reg);
5368         temp &= ~FDI_RX_SYMBOL_LOCK;
5369         temp &= ~FDI_RX_BIT_LOCK;
5370         intel_de_write(dev_priv, reg, temp);
5371
5372         intel_de_posting_read(dev_priv, reg);
5373         udelay(150);
5374
5375         drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR before link train 0x%x\n",
5376                     intel_de_read(dev_priv, FDI_RX_IIR(pipe)));
5377
5378         /* Try each vswing and preemphasis setting twice before moving on */
5379         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
5380                 /* disable first in case we need to retry */
5381                 reg = FDI_TX_CTL(pipe);
5382                 temp = intel_de_read(dev_priv, reg);
5383                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
5384                 temp &= ~FDI_TX_ENABLE;
5385                 intel_de_write(dev_priv, reg, temp);
5386
5387                 reg = FDI_RX_CTL(pipe);
5388                 temp = intel_de_read(dev_priv, reg);
5389                 temp &= ~FDI_LINK_TRAIN_AUTO;
5390                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5391                 temp &= ~FDI_RX_ENABLE;
5392                 intel_de_write(dev_priv, reg, temp);
5393
5394                 /* enable CPU FDI TX and PCH FDI RX */
5395                 reg = FDI_TX_CTL(pipe);
5396                 temp = intel_de_read(dev_priv, reg);
5397                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
5398                 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5399                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
5400                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5401                 temp |= snb_b_fdi_train_param[j/2];
5402                 temp |= FDI_COMPOSITE_SYNC;
5403                 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
5404
5405                 intel_de_write(dev_priv, FDI_RX_MISC(pipe),
5406                                FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
5407
5408                 reg = FDI_RX_CTL(pipe);
5409                 temp = intel_de_read(dev_priv, reg);
5410                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5411                 temp |= FDI_COMPOSITE_SYNC;
5412                 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
5413
5414                 intel_de_posting_read(dev_priv, reg);
5415                 udelay(1); /* should be 0.5us */
5416
5417                 for (i = 0; i < 4; i++) {
5418                         reg = FDI_RX_IIR(pipe);
5419                         temp = intel_de_read(dev_priv, reg);
5420                         drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5421
5422                         if (temp & FDI_RX_BIT_LOCK ||
5423                             (intel_de_read(dev_priv, reg) & FDI_RX_BIT_LOCK)) {
5424                                 intel_de_write(dev_priv, reg,
5425                                                temp | FDI_RX_BIT_LOCK);
5426                                 drm_dbg_kms(&dev_priv->drm,
5427                                             "FDI train 1 done, level %i.\n",
5428                                             i);
5429                                 break;
5430                         }
5431                         udelay(1); /* should be 0.5us */
5432                 }
5433                 if (i == 4) {
5434                         drm_dbg_kms(&dev_priv->drm,
5435                                     "FDI train 1 fail on vswing %d\n", j / 2);
5436                         continue;
5437                 }
5438
5439                 /* Train 2 */
5440                 reg = FDI_TX_CTL(pipe);
5441                 temp = intel_de_read(dev_priv, reg);
5442                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
5443                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
5444                 intel_de_write(dev_priv, reg, temp);
5445
5446                 reg = FDI_RX_CTL(pipe);
5447                 temp = intel_de_read(dev_priv, reg);
5448                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5449                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
5450                 intel_de_write(dev_priv, reg, temp);
5451
5452                 intel_de_posting_read(dev_priv, reg);
5453                 udelay(2); /* should be 1.5us */
5454
5455                 for (i = 0; i < 4; i++) {
5456                         reg = FDI_RX_IIR(pipe);
5457                         temp = intel_de_read(dev_priv, reg);
5458                         drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5459
5460                         if (temp & FDI_RX_SYMBOL_LOCK ||
5461                             (intel_de_read(dev_priv, reg) & FDI_RX_SYMBOL_LOCK)) {
5462                                 intel_de_write(dev_priv, reg,
5463                                                temp | FDI_RX_SYMBOL_LOCK);
5464                                 drm_dbg_kms(&dev_priv->drm,
5465                                             "FDI train 2 done, level %i.\n",
5466                                             i);
5467                                 goto train_done;
5468                         }
5469                         udelay(2); /* should be 1.5us */
5470                 }
5471                 if (i == 4)
5472                         drm_dbg_kms(&dev_priv->drm,
5473                                     "FDI train 2 fail on vswing %d\n", j / 2);
5474         }
5475
5476 train_done:
5477         drm_dbg_kms(&dev_priv->drm, "FDI train done.\n");
5478 }
5479
5480 static void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
5481 {
5482         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
5483         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
5484         enum pipe pipe = intel_crtc->pipe;
5485         i915_reg_t reg;
5486         u32 temp;
5487
5488         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5489         reg = FDI_RX_CTL(pipe);
5490         temp = intel_de_read(dev_priv, reg);
5491         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
5492         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5493         temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5494         intel_de_write(dev_priv, reg, temp | FDI_RX_PLL_ENABLE);
5495
5496         intel_de_posting_read(dev_priv, reg);
5497         udelay(200);
5498
5499         /* Switch from Rawclk to PCDclk */
5500         temp = intel_de_read(dev_priv, reg);
5501         intel_de_write(dev_priv, reg, temp | FDI_PCDCLK);
5502
5503         intel_de_posting_read(dev_priv, reg);
5504         udelay(200);
5505
5506         /* Enable CPU FDI TX PLL, always on for Ironlake */
5507         reg = FDI_TX_CTL(pipe);
5508         temp = intel_de_read(dev_priv, reg);
5509         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5510                 intel_de_write(dev_priv, reg, temp | FDI_TX_PLL_ENABLE);
5511
5512                 intel_de_posting_read(dev_priv, reg);
5513                 udelay(100);
5514         }
5515 }
5516
5517 static void ilk_fdi_pll_disable(struct intel_crtc *intel_crtc)
5518 {
5519         struct drm_device *dev = intel_crtc->base.dev;
5520         struct drm_i915_private *dev_priv = to_i915(dev);
5521         enum pipe pipe = intel_crtc->pipe;
5522         i915_reg_t reg;
5523         u32 temp;
5524
5525         /* Switch from PCDclk to Rawclk */
5526         reg = FDI_RX_CTL(pipe);
5527         temp = intel_de_read(dev_priv, reg);
5528         intel_de_write(dev_priv, reg, temp & ~FDI_PCDCLK);
5529
5530         /* Disable CPU FDI TX PLL */
5531         reg = FDI_TX_CTL(pipe);
5532         temp = intel_de_read(dev_priv, reg);
5533         intel_de_write(dev_priv, reg, temp & ~FDI_TX_PLL_ENABLE);
5534
5535         intel_de_posting_read(dev_priv, reg);
5536         udelay(100);
5537
5538         reg = FDI_RX_CTL(pipe);
5539         temp = intel_de_read(dev_priv, reg);
5540         intel_de_write(dev_priv, reg, temp & ~FDI_RX_PLL_ENABLE);
5541
5542         /* Wait for the clocks to turn off. */
5543         intel_de_posting_read(dev_priv, reg);
5544         udelay(100);
5545 }
5546
5547 static void ilk_fdi_disable(struct intel_crtc *crtc)
5548 {
5549         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5550         enum pipe pipe = crtc->pipe;
5551         i915_reg_t reg;
5552         u32 temp;
5553
5554         /* disable CPU FDI tx and PCH FDI rx */
5555         reg = FDI_TX_CTL(pipe);
5556         temp = intel_de_read(dev_priv, reg);
5557         intel_de_write(dev_priv, reg, temp & ~FDI_TX_ENABLE);
5558         intel_de_posting_read(dev_priv, reg);
5559
5560         reg = FDI_RX_CTL(pipe);
5561         temp = intel_de_read(dev_priv, reg);
5562         temp &= ~(0x7 << 16);
5563         temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5564         intel_de_write(dev_priv, reg, temp & ~FDI_RX_ENABLE);
5565
5566         intel_de_posting_read(dev_priv, reg);
5567         udelay(100);
5568
5569         /* Ironlake workaround, disable clock pointer after downing FDI */
5570         if (HAS_PCH_IBX(dev_priv))
5571                 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
5572                                FDI_RX_PHASE_SYNC_POINTER_OVR);
5573
5574         /* still set train pattern 1 */
5575         reg = FDI_TX_CTL(pipe);
5576         temp = intel_de_read(dev_priv, reg);
5577         temp &= ~FDI_LINK_TRAIN_NONE;
5578         temp |= FDI_LINK_TRAIN_PATTERN_1;
5579         intel_de_write(dev_priv, reg, temp);
5580
5581         reg = FDI_RX_CTL(pipe);
5582         temp = intel_de_read(dev_priv, reg);
5583         if (HAS_PCH_CPT(dev_priv)) {
5584                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5585                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5586         } else {
5587                 temp &= ~FDI_LINK_TRAIN_NONE;
5588                 temp |= FDI_LINK_TRAIN_PATTERN_1;
5589         }
5590         /* BPC in FDI rx is consistent with that in PIPECONF */
5591         temp &= ~(0x07 << 16);
5592         temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5593         intel_de_write(dev_priv, reg, temp);
5594
5595         intel_de_posting_read(dev_priv, reg);
5596         udelay(100);
5597 }
5598
5599 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
5600 {
5601         struct drm_crtc *crtc;
5602         bool cleanup_done;
5603
5604         drm_for_each_crtc(crtc, &dev_priv->drm) {
5605                 struct drm_crtc_commit *commit;
5606                 spin_lock(&crtc->commit_lock);
5607                 commit = list_first_entry_or_null(&crtc->commit_list,
5608                                                   struct drm_crtc_commit, commit_entry);
5609                 cleanup_done = commit ?
5610                         try_wait_for_completion(&commit->cleanup_done) : true;
5611                 spin_unlock(&crtc->commit_lock);
5612
5613                 if (cleanup_done)
5614                         continue;
5615
5616                 drm_crtc_wait_one_vblank(crtc);
5617
5618                 return true;
5619         }
5620
5621         return false;
5622 }
5623
5624 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
5625 {
5626         u32 temp;
5627
5628         intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_GATE);
5629
5630         mutex_lock(&dev_priv->sb_lock);
5631
5632         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5633         temp |= SBI_SSCCTL_DISABLE;
5634         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5635
5636         mutex_unlock(&dev_priv->sb_lock);
5637 }
5638
5639 /* Program iCLKIP clock to the desired frequency */
5640 static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
5641 {
5642         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5643         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5644         int clock = crtc_state->hw.adjusted_mode.crtc_clock;
5645         u32 divsel, phaseinc, auxdiv, phasedir = 0;
5646         u32 temp;
5647
5648         lpt_disable_iclkip(dev_priv);
5649
5650         /* The iCLK virtual clock root frequency is in MHz,
5651          * but the adjusted_mode->crtc_clock in in KHz. To get the
5652          * divisors, it is necessary to divide one by another, so we
5653          * convert the virtual clock precision to KHz here for higher
5654          * precision.
5655          */
5656         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
5657                 u32 iclk_virtual_root_freq = 172800 * 1000;
5658                 u32 iclk_pi_range = 64;
5659                 u32 desired_divisor;
5660
5661                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5662                                                     clock << auxdiv);
5663                 divsel = (desired_divisor / iclk_pi_range) - 2;
5664                 phaseinc = desired_divisor % iclk_pi_range;
5665
5666                 /*
5667                  * Near 20MHz is a corner case which is
5668                  * out of range for the 7-bit divisor
5669                  */
5670                 if (divsel <= 0x7f)
5671                         break;
5672         }
5673
5674         /* This should not happen with any sane values */
5675         drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
5676                     ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
5677         drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(phasedir) &
5678                     ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
5679
5680         drm_dbg_kms(&dev_priv->drm,
5681                     "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
5682                     clock, auxdiv, divsel, phasedir, phaseinc);
5683
5684         mutex_lock(&dev_priv->sb_lock);
5685
5686         /* Program SSCDIVINTPHASE6 */
5687         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5688         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
5689         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
5690         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
5691         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
5692         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
5693         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
5694         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
5695
5696         /* Program SSCAUXDIV */
5697         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5698         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
5699         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
5700         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
5701
5702         /* Enable modulator and associated divider */
5703         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5704         temp &= ~SBI_SSCCTL_DISABLE;
5705         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5706
5707         mutex_unlock(&dev_priv->sb_lock);
5708
5709         /* Wait for initialization time */
5710         udelay(24);
5711
5712         intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_UNGATE);
5713 }
5714
5715 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
5716 {
5717         u32 divsel, phaseinc, auxdiv;
5718         u32 iclk_virtual_root_freq = 172800 * 1000;
5719         u32 iclk_pi_range = 64;
5720         u32 desired_divisor;
5721         u32 temp;
5722
5723         if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
5724                 return 0;
5725
5726         mutex_lock(&dev_priv->sb_lock);
5727
5728         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5729         if (temp & SBI_SSCCTL_DISABLE) {
5730                 mutex_unlock(&dev_priv->sb_lock);
5731                 return 0;
5732         }
5733
5734         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5735         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
5736                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
5737         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
5738                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
5739
5740         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5741         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
5742                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
5743
5744         mutex_unlock(&dev_priv->sb_lock);
5745
5746         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
5747
5748         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5749                                  desired_divisor << auxdiv);
5750 }
5751
5752 static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
5753                                            enum pipe pch_transcoder)
5754 {
5755         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5756         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5757         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5758
5759         intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
5760                        intel_de_read(dev_priv, HTOTAL(cpu_transcoder)));
5761         intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
5762                        intel_de_read(dev_priv, HBLANK(cpu_transcoder)));
5763         intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
5764                        intel_de_read(dev_priv, HSYNC(cpu_transcoder)));
5765
5766         intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
5767                        intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
5768         intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
5769                        intel_de_read(dev_priv, VBLANK(cpu_transcoder)));
5770         intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
5771                        intel_de_read(dev_priv, VSYNC(cpu_transcoder)));
5772         intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
5773                        intel_de_read(dev_priv, VSYNCSHIFT(cpu_transcoder)));
5774 }
5775
5776 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
5777 {
5778         u32 temp;
5779
5780         temp = intel_de_read(dev_priv, SOUTH_CHICKEN1);
5781         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
5782                 return;
5783
5784         drm_WARN_ON(&dev_priv->drm,
5785                     intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) &
5786                     FDI_RX_ENABLE);
5787         drm_WARN_ON(&dev_priv->drm,
5788                     intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) &
5789                     FDI_RX_ENABLE);
5790
5791         temp &= ~FDI_BC_BIFURCATION_SELECT;
5792         if (enable)
5793                 temp |= FDI_BC_BIFURCATION_SELECT;
5794
5795         drm_dbg_kms(&dev_priv->drm, "%sabling fdi C rx\n",
5796                     enable ? "en" : "dis");
5797         intel_de_write(dev_priv, SOUTH_CHICKEN1, temp);
5798         intel_de_posting_read(dev_priv, SOUTH_CHICKEN1);
5799 }
5800
5801 static void ivb_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
5802 {
5803         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5804         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5805
5806         switch (crtc->pipe) {
5807         case PIPE_A:
5808                 break;
5809         case PIPE_B:
5810                 if (crtc_state->fdi_lanes > 2)
5811                         cpt_set_fdi_bc_bifurcation(dev_priv, false);
5812                 else
5813                         cpt_set_fdi_bc_bifurcation(dev_priv, true);
5814
5815                 break;
5816         case PIPE_C:
5817                 cpt_set_fdi_bc_bifurcation(dev_priv, true);
5818
5819                 break;
5820         default:
5821                 BUG();
5822         }
5823 }
5824
5825 /*
5826  * Finds the encoder associated with the given CRTC. This can only be
5827  * used when we know that the CRTC isn't feeding multiple encoders!
5828  */
5829 static struct intel_encoder *
5830 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
5831                            const struct intel_crtc_state *crtc_state)
5832 {
5833         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5834         const struct drm_connector_state *connector_state;
5835         const struct drm_connector *connector;
5836         struct intel_encoder *encoder = NULL;
5837         int num_encoders = 0;
5838         int i;
5839
5840         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
5841                 if (connector_state->crtc != &crtc->base)
5842                         continue;
5843
5844                 encoder = to_intel_encoder(connector_state->best_encoder);
5845                 num_encoders++;
5846         }
5847
5848         drm_WARN(encoder->base.dev, num_encoders != 1,
5849                  "%d encoders for pipe %c\n",
5850                  num_encoders, pipe_name(crtc->pipe));
5851
5852         return encoder;
5853 }
5854
5855 /*
5856  * Enable PCH resources required for PCH ports:
5857  *   - PCH PLLs
5858  *   - FDI training & RX/TX
5859  *   - update transcoder timings
5860  *   - DP transcoding bits
5861  *   - transcoder
5862  */
5863 static void ilk_pch_enable(const struct intel_atomic_state *state,
5864                            const struct intel_crtc_state *crtc_state)
5865 {
5866         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5867         struct drm_device *dev = crtc->base.dev;
5868         struct drm_i915_private *dev_priv = to_i915(dev);
5869         enum pipe pipe = crtc->pipe;
5870         u32 temp;
5871
5872         assert_pch_transcoder_disabled(dev_priv, pipe);
5873
5874         if (IS_IVYBRIDGE(dev_priv))
5875                 ivb_update_fdi_bc_bifurcation(crtc_state);
5876
5877         /* Write the TU size bits before fdi link training, so that error
5878          * detection works. */
5879         intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
5880                        intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
5881
5882         /* For PCH output, training FDI link */
5883         dev_priv->display.fdi_link_train(crtc, crtc_state);
5884
5885         /* We need to program the right clock selection before writing the pixel
5886          * mutliplier into the DPLL. */
5887         if (HAS_PCH_CPT(dev_priv)) {
5888                 u32 sel;
5889
5890                 temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
5891                 temp |= TRANS_DPLL_ENABLE(pipe);
5892                 sel = TRANS_DPLLB_SEL(pipe);
5893                 if (crtc_state->shared_dpll ==
5894                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
5895                         temp |= sel;
5896                 else
5897                         temp &= ~sel;
5898                 intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
5899         }
5900
5901         /* XXX: pch pll's can be enabled any time before we enable the PCH
5902          * transcoder, and we actually should do this to not upset any PCH
5903          * transcoder that already use the clock when we share it.
5904          *
5905          * Note that enable_shared_dpll tries to do the right thing, but
5906          * get_shared_dpll unconditionally resets the pll - we need that to have
5907          * the right LVDS enable sequence. */
5908         intel_enable_shared_dpll(crtc_state);
5909
5910         /* set transcoder timing, panel must allow it */
5911         assert_panel_unlocked(dev_priv, pipe);
5912         ilk_pch_transcoder_set_timings(crtc_state, pipe);
5913
5914         intel_fdi_normal_train(crtc);
5915
5916         /* For PCH DP, enable TRANS_DP_CTL */
5917         if (HAS_PCH_CPT(dev_priv) &&
5918             intel_crtc_has_dp_encoder(crtc_state)) {
5919                 const struct drm_display_mode *adjusted_mode =
5920                         &crtc_state->hw.adjusted_mode;
5921                 u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5922                 i915_reg_t reg = TRANS_DP_CTL(pipe);
5923                 enum port port;
5924
5925                 temp = intel_de_read(dev_priv, reg);
5926                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
5927                           TRANS_DP_SYNC_MASK |
5928                           TRANS_DP_BPC_MASK);
5929                 temp |= TRANS_DP_OUTPUT_ENABLE;
5930                 temp |= bpc << 9; /* same format but at 11:9 */
5931
5932                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
5933                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
5934                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
5935                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
5936
5937                 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
5938                 drm_WARN_ON(dev, port < PORT_B || port > PORT_D);
5939                 temp |= TRANS_DP_PORT_SEL(port);
5940
5941                 intel_de_write(dev_priv, reg, temp);
5942         }
5943
5944         ilk_enable_pch_transcoder(crtc_state);
5945 }
5946
5947 void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
5948 {
5949         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5950         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5951         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5952
5953         assert_pch_transcoder_disabled(dev_priv, PIPE_A);
5954
5955         lpt_program_iclkip(crtc_state);
5956
5957         /* Set transcoder timing. */
5958         ilk_pch_transcoder_set_timings(crtc_state, PIPE_A);
5959
5960         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
5961 }
5962
5963 static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
5964                                enum pipe pipe)
5965 {
5966         i915_reg_t dslreg = PIPEDSL(pipe);
5967         u32 temp;
5968
5969         temp = intel_de_read(dev_priv, dslreg);
5970         udelay(500);
5971         if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) {
5972                 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5))
5973                         drm_err(&dev_priv->drm,
5974                                 "mode set failed: pipe %c stuck\n",
5975                                 pipe_name(pipe));
5976         }
5977 }
5978
5979 /*
5980  * The hardware phase 0.0 refers to the center of the pixel.
5981  * We want to start from the top/left edge which is phase
5982  * -0.5. That matches how the hardware calculates the scaling
5983  * factors (from top-left of the first pixel to bottom-right
5984  * of the last pixel, as opposed to the pixel centers).
5985  *
5986  * For 4:2:0 subsampled chroma planes we obviously have to
5987  * adjust that so that the chroma sample position lands in
5988  * the right spot.
5989  *
5990  * Note that for packed YCbCr 4:2:2 formats there is no way to
5991  * control chroma siting. The hardware simply replicates the
5992  * chroma samples for both of the luma samples, and thus we don't
5993  * actually get the expected MPEG2 chroma siting convention :(
5994  * The same behaviour is observed on pre-SKL platforms as well.
5995  *
5996  * Theory behind the formula (note that we ignore sub-pixel
5997  * source coordinates):
5998  * s = source sample position
5999  * d = destination sample position
6000  *
6001  * Downscaling 4:1:
6002  * -0.5
6003  * | 0.0
6004  * | |     1.5 (initial phase)
6005  * | |     |
6006  * v v     v
6007  * | s | s | s | s |
6008  * |       d       |
6009  *
6010  * Upscaling 1:4:
6011  * -0.5
6012  * | -0.375 (initial phase)
6013  * | |     0.0
6014  * | |     |
6015  * v v     v
6016  * |       s       |
6017  * | d | d | d | d |
6018  */
6019 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
6020 {
6021         int phase = -0x8000;
6022         u16 trip = 0;
6023
6024         if (chroma_cosited)
6025                 phase += (sub - 1) * 0x8000 / sub;
6026
6027         phase += scale / (2 * sub);
6028
6029         /*
6030          * Hardware initial phase limited to [-0.5:1.5].
6031          * Since the max hardware scale factor is 3.0, we
6032          * should never actually excdeed 1.0 here.
6033          */
6034         WARN_ON(phase < -0x8000 || phase > 0x18000);
6035
6036         if (phase < 0)
6037                 phase = 0x10000 + phase;
6038         else
6039                 trip = PS_PHASE_TRIP;
6040
6041         return ((phase >> 2) & PS_PHASE_MASK) | trip;
6042 }
6043
6044 #define SKL_MIN_SRC_W 8
6045 #define SKL_MAX_SRC_W 4096
6046 #define SKL_MIN_SRC_H 8
6047 #define SKL_MAX_SRC_H 4096
6048 #define SKL_MIN_DST_W 8
6049 #define SKL_MAX_DST_W 4096
6050 #define SKL_MIN_DST_H 8
6051 #define SKL_MAX_DST_H 4096
6052 #define ICL_MAX_SRC_W 5120
6053 #define ICL_MAX_SRC_H 4096
6054 #define ICL_MAX_DST_W 5120
6055 #define ICL_MAX_DST_H 4096
6056 #define SKL_MIN_YUV_420_SRC_W 16
6057 #define SKL_MIN_YUV_420_SRC_H 16
6058
6059 static int
6060 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
6061                   unsigned int scaler_user, int *scaler_id,
6062                   int src_w, int src_h, int dst_w, int dst_h,
6063                   const struct drm_format_info *format,
6064                   u64 modifier, bool need_scaler)
6065 {
6066         struct intel_crtc_scaler_state *scaler_state =
6067                 &crtc_state->scaler_state;
6068         struct intel_crtc *intel_crtc =
6069                 to_intel_crtc(crtc_state->uapi.crtc);
6070         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6071         const struct drm_display_mode *adjusted_mode =
6072                 &crtc_state->hw.adjusted_mode;
6073
6074         /*
6075          * Src coordinates are already rotated by 270 degrees for
6076          * the 90/270 degree plane rotation cases (to match the
6077          * GTT mapping), hence no need to account for rotation here.
6078          */
6079         if (src_w != dst_w || src_h != dst_h)
6080                 need_scaler = true;
6081
6082         /*
6083          * Scaling/fitting not supported in IF-ID mode in GEN9+
6084          * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
6085          * Once NV12 is enabled, handle it here while allocating scaler
6086          * for NV12.
6087          */
6088         if (INTEL_GEN(dev_priv) >= 9 && crtc_state->hw.enable &&
6089             need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6090                 drm_dbg_kms(&dev_priv->drm,
6091                             "Pipe/Plane scaling not supported with IF-ID mode\n");
6092                 return -EINVAL;
6093         }
6094
6095         /*
6096          * if plane is being disabled or scaler is no more required or force detach
6097          *  - free scaler binded to this plane/crtc
6098          *  - in order to do this, update crtc->scaler_usage
6099          *
6100          * Here scaler state in crtc_state is set free so that
6101          * scaler can be assigned to other user. Actual register
6102          * update to free the scaler is done in plane/panel-fit programming.
6103          * For this purpose crtc/plane_state->scaler_id isn't reset here.
6104          */
6105         if (force_detach || !need_scaler) {
6106                 if (*scaler_id >= 0) {
6107                         scaler_state->scaler_users &= ~(1 << scaler_user);
6108                         scaler_state->scalers[*scaler_id].in_use = 0;
6109
6110                         drm_dbg_kms(&dev_priv->drm,
6111                                     "scaler_user index %u.%u: "
6112                                     "Staged freeing scaler id %d scaler_users = 0x%x\n",
6113                                     intel_crtc->pipe, scaler_user, *scaler_id,
6114                                     scaler_state->scaler_users);
6115                         *scaler_id = -1;
6116                 }
6117                 return 0;
6118         }
6119
6120         if (format && intel_format_info_is_yuv_semiplanar(format, modifier) &&
6121             (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
6122                 drm_dbg_kms(&dev_priv->drm,
6123                             "Planar YUV: src dimensions not met\n");
6124                 return -EINVAL;
6125         }
6126
6127         /* range checks */
6128         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
6129             dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
6130             (INTEL_GEN(dev_priv) >= 11 &&
6131              (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
6132               dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
6133             (INTEL_GEN(dev_priv) < 11 &&
6134              (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
6135               dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
6136                 drm_dbg_kms(&dev_priv->drm,
6137                             "scaler_user index %u.%u: src %ux%u dst %ux%u "
6138                             "size is out of scaler range\n",
6139                             intel_crtc->pipe, scaler_user, src_w, src_h,
6140                             dst_w, dst_h);
6141                 return -EINVAL;
6142         }
6143
6144         /* mark this plane as a scaler user in crtc_state */
6145         scaler_state->scaler_users |= (1 << scaler_user);
6146         drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: "
6147                     "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
6148                     intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
6149                     scaler_state->scaler_users);
6150
6151         return 0;
6152 }
6153
6154 static int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
6155 {
6156         const struct drm_display_mode *adjusted_mode =
6157                 &crtc_state->hw.adjusted_mode;
6158         int width, height;
6159
6160         if (crtc_state->pch_pfit.enabled) {
6161                 width = drm_rect_width(&crtc_state->pch_pfit.dst);
6162                 height = drm_rect_height(&crtc_state->pch_pfit.dst);
6163         } else {
6164                 width = adjusted_mode->crtc_hdisplay;
6165                 height = adjusted_mode->crtc_vdisplay;
6166         }
6167
6168         return skl_update_scaler(crtc_state, !crtc_state->hw.active,
6169                                  SKL_CRTC_INDEX,
6170                                  &crtc_state->scaler_state.scaler_id,
6171                                  crtc_state->pipe_src_w, crtc_state->pipe_src_h,
6172                                  width, height, NULL, 0,
6173                                  crtc_state->pch_pfit.enabled);
6174 }
6175
6176 /**
6177  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
6178  * @crtc_state: crtc's scaler state
6179  * @plane_state: atomic plane state to update
6180  *
6181  * Return
6182  *     0 - scaler_usage updated successfully
6183  *    error - requested scaling cannot be supported or other error condition
6184  */
6185 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
6186                                    struct intel_plane_state *plane_state)
6187 {
6188         struct intel_plane *intel_plane =
6189                 to_intel_plane(plane_state->uapi.plane);
6190         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
6191         struct drm_framebuffer *fb = plane_state->hw.fb;
6192         int ret;
6193         bool force_detach = !fb || !plane_state->uapi.visible;
6194         bool need_scaler = false;
6195
6196         /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
6197         if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
6198             fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
6199                 need_scaler = true;
6200
6201         ret = skl_update_scaler(crtc_state, force_detach,
6202                                 drm_plane_index(&intel_plane->base),
6203                                 &plane_state->scaler_id,
6204                                 drm_rect_width(&plane_state->uapi.src) >> 16,
6205                                 drm_rect_height(&plane_state->uapi.src) >> 16,
6206                                 drm_rect_width(&plane_state->uapi.dst),
6207                                 drm_rect_height(&plane_state->uapi.dst),
6208                                 fb ? fb->format : NULL,
6209                                 fb ? fb->modifier : 0,
6210                                 need_scaler);
6211
6212         if (ret || plane_state->scaler_id < 0)
6213                 return ret;
6214
6215         /* check colorkey */
6216         if (plane_state->ckey.flags) {
6217                 drm_dbg_kms(&dev_priv->drm,
6218                             "[PLANE:%d:%s] scaling with color key not allowed",
6219                             intel_plane->base.base.id,
6220                             intel_plane->base.name);
6221                 return -EINVAL;
6222         }
6223
6224         /* Check src format */
6225         switch (fb->format->format) {
6226         case DRM_FORMAT_RGB565:
6227         case DRM_FORMAT_XBGR8888:
6228         case DRM_FORMAT_XRGB8888:
6229         case DRM_FORMAT_ABGR8888:
6230         case DRM_FORMAT_ARGB8888:
6231         case DRM_FORMAT_XRGB2101010:
6232         case DRM_FORMAT_XBGR2101010:
6233         case DRM_FORMAT_ARGB2101010:
6234         case DRM_FORMAT_ABGR2101010:
6235         case DRM_FORMAT_YUYV:
6236         case DRM_FORMAT_YVYU:
6237         case DRM_FORMAT_UYVY:
6238         case DRM_FORMAT_VYUY:
6239         case DRM_FORMAT_NV12:
6240         case DRM_FORMAT_XYUV8888:
6241         case DRM_FORMAT_P010:
6242         case DRM_FORMAT_P012:
6243         case DRM_FORMAT_P016:
6244         case DRM_FORMAT_Y210:
6245         case DRM_FORMAT_Y212:
6246         case DRM_FORMAT_Y216:
6247         case DRM_FORMAT_XVYU2101010:
6248         case DRM_FORMAT_XVYU12_16161616:
6249         case DRM_FORMAT_XVYU16161616:
6250                 break;
6251         case DRM_FORMAT_XBGR16161616F:
6252         case DRM_FORMAT_ABGR16161616F:
6253         case DRM_FORMAT_XRGB16161616F:
6254         case DRM_FORMAT_ARGB16161616F:
6255                 if (INTEL_GEN(dev_priv) >= 11)
6256                         break;
6257                 fallthrough;
6258         default:
6259                 drm_dbg_kms(&dev_priv->drm,
6260                             "[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
6261                             intel_plane->base.base.id, intel_plane->base.name,
6262                             fb->base.id, fb->format->format);
6263                 return -EINVAL;
6264         }
6265
6266         return 0;
6267 }
6268
6269 void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state)
6270 {
6271         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
6272         int i;
6273
6274         for (i = 0; i < crtc->num_scalers; i++)
6275                 skl_detach_scaler(crtc, i);
6276 }
6277
6278 static void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
6279 {
6280         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6281         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6282         const struct intel_crtc_scaler_state *scaler_state =
6283                 &crtc_state->scaler_state;
6284         struct drm_rect src = {
6285                 .x2 = crtc_state->pipe_src_w << 16,
6286                 .y2 = crtc_state->pipe_src_h << 16,
6287         };
6288         const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
6289         u16 uv_rgb_hphase, uv_rgb_vphase;
6290         enum pipe pipe = crtc->pipe;
6291         int width = drm_rect_width(dst);
6292         int height = drm_rect_height(dst);
6293         int x = dst->x1;
6294         int y = dst->y1;
6295         int hscale, vscale;
6296         unsigned long irqflags;
6297         int id;
6298
6299         if (!crtc_state->pch_pfit.enabled)
6300                 return;
6301
6302         if (drm_WARN_ON(&dev_priv->drm,
6303                         crtc_state->scaler_state.scaler_id < 0))
6304                 return;
6305
6306         hscale = drm_rect_calc_hscale(&src, dst, 0, INT_MAX);
6307         vscale = drm_rect_calc_vscale(&src, dst, 0, INT_MAX);
6308
6309         uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
6310         uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
6311
6312         id = scaler_state->scaler_id;
6313
6314         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
6315
6316         intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
6317                           PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
6318         intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
6319                           PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
6320         intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
6321                           PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
6322         intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
6323                           x << 16 | y);
6324         intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
6325                           width << 16 | height);
6326
6327         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
6328 }
6329
6330 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
6331 {
6332         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6333         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6334         const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
6335         enum pipe pipe = crtc->pipe;
6336         int width = drm_rect_width(dst);
6337         int height = drm_rect_height(dst);
6338         int x = dst->x1;
6339         int y = dst->y1;
6340
6341         if (!crtc_state->pch_pfit.enabled)
6342                 return;
6343
6344         /* Force use of hard-coded filter coefficients
6345          * as some pre-programmed values are broken,
6346          * e.g. x201.
6347          */
6348         if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
6349                 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
6350                                PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
6351         else
6352                 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
6353                                PF_FILTER_MED_3x3);
6354         intel_de_write(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
6355         intel_de_write(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
6356 }
6357
6358 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
6359 {
6360         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6361         struct drm_device *dev = crtc->base.dev;
6362         struct drm_i915_private *dev_priv = to_i915(dev);
6363
6364         if (!crtc_state->ips_enabled)
6365                 return;
6366
6367         /*
6368          * We can only enable IPS after we enable a plane and wait for a vblank
6369          * This function is called from post_plane_update, which is run after
6370          * a vblank wait.
6371          */
6372         drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
6373
6374         if (IS_BROADWELL(dev_priv)) {
6375                 drm_WARN_ON(dev, sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
6376                                                          IPS_ENABLE | IPS_PCODE_CONTROL));
6377                 /* Quoting Art Runyan: "its not safe to expect any particular
6378                  * value in IPS_CTL bit 31 after enabling IPS through the
6379                  * mailbox." Moreover, the mailbox may return a bogus state,
6380                  * so we need to just enable it and continue on.
6381                  */
6382         } else {
6383                 intel_de_write(dev_priv, IPS_CTL, IPS_ENABLE);
6384                 /* The bit only becomes 1 in the next vblank, so this wait here
6385                  * is essentially intel_wait_for_vblank. If we don't have this
6386                  * and don't wait for vblanks until the end of crtc_enable, then
6387                  * the HW state readout code will complain that the expected
6388                  * IPS_CTL value is not the one we read. */
6389                 if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50))
6390                         drm_err(&dev_priv->drm,
6391                                 "Timed out waiting for IPS enable\n");
6392         }
6393 }
6394
6395 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
6396 {
6397         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6398         struct drm_device *dev = crtc->base.dev;
6399         struct drm_i915_private *dev_priv = to_i915(dev);
6400
6401         if (!crtc_state->ips_enabled)
6402                 return;
6403
6404         if (IS_BROADWELL(dev_priv)) {
6405                 drm_WARN_ON(dev,
6406                             sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
6407                 /*
6408                  * Wait for PCODE to finish disabling IPS. The BSpec specified
6409                  * 42ms timeout value leads to occasional timeouts so use 100ms
6410                  * instead.
6411                  */
6412                 if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100))
6413                         drm_err(&dev_priv->drm,
6414                                 "Timed out waiting for IPS disable\n");
6415         } else {
6416                 intel_de_write(dev_priv, IPS_CTL, 0);
6417                 intel_de_posting_read(dev_priv, IPS_CTL);
6418         }
6419
6420         /* We need to wait for a vblank before we can disable the plane. */
6421         intel_wait_for_vblank(dev_priv, crtc->pipe);
6422 }
6423
6424 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
6425 {
6426         if (intel_crtc->overlay)
6427                 (void) intel_overlay_switch_off(intel_crtc->overlay);
6428
6429         /* Let userspace switch the overlay on again. In most cases userspace
6430          * has to recompute where to put it anyway.
6431          */
6432 }
6433
6434 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
6435                                        const struct intel_crtc_state *new_crtc_state)
6436 {
6437         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6438         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6439
6440         if (!old_crtc_state->ips_enabled)
6441                 return false;
6442
6443         if (needs_modeset(new_crtc_state))
6444                 return true;
6445
6446         /*
6447          * Workaround : Do not read or write the pipe palette/gamma data while
6448          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6449          *
6450          * Disable IPS before we program the LUT.
6451          */
6452         if (IS_HASWELL(dev_priv) &&
6453             (new_crtc_state->uapi.color_mgmt_changed ||
6454              new_crtc_state->update_pipe) &&
6455             new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
6456                 return true;
6457
6458         return !new_crtc_state->ips_enabled;
6459 }
6460
6461 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
6462                                        const struct intel_crtc_state *new_crtc_state)
6463 {
6464         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6465         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6466
6467         if (!new_crtc_state->ips_enabled)
6468                 return false;
6469
6470         if (needs_modeset(new_crtc_state))
6471                 return true;
6472
6473         /*
6474          * Workaround : Do not read or write the pipe palette/gamma data while
6475          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6476          *
6477          * Re-enable IPS after the LUT has been programmed.
6478          */
6479         if (IS_HASWELL(dev_priv) &&
6480             (new_crtc_state->uapi.color_mgmt_changed ||
6481              new_crtc_state->update_pipe) &&
6482             new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
6483                 return true;
6484
6485         /*
6486          * We can't read out IPS on broadwell, assume the worst and
6487          * forcibly enable IPS on the first fastset.
6488          */
6489         if (new_crtc_state->update_pipe && old_crtc_state->inherited)
6490                 return true;
6491
6492         return !old_crtc_state->ips_enabled;
6493 }
6494
6495 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
6496 {
6497         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
6498
6499         if (!crtc_state->nv12_planes)
6500                 return false;
6501
6502         /* WA Display #0827: Gen9:all */
6503         if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
6504                 return true;
6505
6506         return false;
6507 }
6508
6509 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
6510 {
6511         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
6512
6513         /* Wa_2006604312:icl,ehl */
6514         if (crtc_state->scaler_state.scaler_users > 0 && IS_GEN(dev_priv, 11))
6515                 return true;
6516
6517         return false;
6518 }
6519
6520 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
6521                             const struct intel_crtc_state *new_crtc_state)
6522 {
6523         return (!old_crtc_state->active_planes || needs_modeset(new_crtc_state)) &&
6524                 new_crtc_state->active_planes;
6525 }
6526
6527 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
6528                              const struct intel_crtc_state *new_crtc_state)
6529 {
6530         return old_crtc_state->active_planes &&
6531                 (!new_crtc_state->active_planes || needs_modeset(new_crtc_state));
6532 }
6533
6534 static void intel_post_plane_update(struct intel_atomic_state *state,
6535                                     struct intel_crtc *crtc)
6536 {
6537         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6538         const struct intel_crtc_state *old_crtc_state =
6539                 intel_atomic_get_old_crtc_state(state, crtc);
6540         const struct intel_crtc_state *new_crtc_state =
6541                 intel_atomic_get_new_crtc_state(state, crtc);
6542         enum pipe pipe = crtc->pipe;
6543
6544         intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
6545
6546         if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
6547                 intel_update_watermarks(crtc);
6548
6549         if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
6550                 hsw_enable_ips(new_crtc_state);
6551
6552         intel_fbc_post_update(state, crtc);
6553
6554         if (needs_nv12_wa(old_crtc_state) &&
6555             !needs_nv12_wa(new_crtc_state))
6556                 skl_wa_827(dev_priv, pipe, false);
6557
6558         if (needs_scalerclk_wa(old_crtc_state) &&
6559             !needs_scalerclk_wa(new_crtc_state))
6560                 icl_wa_scalerclkgating(dev_priv, pipe, false);
6561 }
6562
6563 static void intel_pre_plane_update(struct intel_atomic_state *state,
6564                                    struct intel_crtc *crtc)
6565 {
6566         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6567         const struct intel_crtc_state *old_crtc_state =
6568                 intel_atomic_get_old_crtc_state(state, crtc);
6569         const struct intel_crtc_state *new_crtc_state =
6570                 intel_atomic_get_new_crtc_state(state, crtc);
6571         enum pipe pipe = crtc->pipe;
6572
6573         if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
6574                 hsw_disable_ips(old_crtc_state);
6575
6576         if (intel_fbc_pre_update(state, crtc))
6577                 intel_wait_for_vblank(dev_priv, pipe);
6578
6579         /* Display WA 827 */
6580         if (!needs_nv12_wa(old_crtc_state) &&
6581             needs_nv12_wa(new_crtc_state))
6582                 skl_wa_827(dev_priv, pipe, true);
6583
6584         /* Wa_2006604312:icl,ehl */
6585         if (!needs_scalerclk_wa(old_crtc_state) &&
6586             needs_scalerclk_wa(new_crtc_state))
6587                 icl_wa_scalerclkgating(dev_priv, pipe, true);
6588
6589         /*
6590          * Vblank time updates from the shadow to live plane control register
6591          * are blocked if the memory self-refresh mode is active at that
6592          * moment. So to make sure the plane gets truly disabled, disable
6593          * first the self-refresh mode. The self-refresh enable bit in turn
6594          * will be checked/applied by the HW only at the next frame start
6595          * event which is after the vblank start event, so we need to have a
6596          * wait-for-vblank between disabling the plane and the pipe.
6597          */
6598         if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
6599             new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
6600                 intel_wait_for_vblank(dev_priv, pipe);
6601
6602         /*
6603          * IVB workaround: must disable low power watermarks for at least
6604          * one frame before enabling scaling.  LP watermarks can be re-enabled
6605          * when scaling is disabled.
6606          *
6607          * WaCxSRDisabledForSpriteScaling:ivb
6608          */
6609         if (old_crtc_state->hw.active &&
6610             new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
6611                 intel_wait_for_vblank(dev_priv, pipe);
6612
6613         /*
6614          * If we're doing a modeset we don't need to do any
6615          * pre-vblank watermark programming here.
6616          */
6617         if (!needs_modeset(new_crtc_state)) {
6618                 /*
6619                  * For platforms that support atomic watermarks, program the
6620                  * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
6621                  * will be the intermediate values that are safe for both pre- and
6622                  * post- vblank; when vblank happens, the 'active' values will be set
6623                  * to the final 'target' values and we'll do this again to get the
6624                  * optimal watermarks.  For gen9+ platforms, the values we program here
6625                  * will be the final target values which will get automatically latched
6626                  * at vblank time; no further programming will be necessary.
6627                  *
6628                  * If a platform hasn't been transitioned to atomic watermarks yet,
6629                  * we'll continue to update watermarks the old way, if flags tell
6630                  * us to.
6631                  */
6632                 if (dev_priv->display.initial_watermarks)
6633                         dev_priv->display.initial_watermarks(state, crtc);
6634                 else if (new_crtc_state->update_wm_pre)
6635                         intel_update_watermarks(crtc);
6636         }
6637
6638         /*
6639          * Gen2 reports pipe underruns whenever all planes are disabled.
6640          * So disable underrun reporting before all the planes get disabled.
6641          *
6642          * We do this after .initial_watermarks() so that we have a
6643          * chance of catching underruns with the intermediate watermarks
6644          * vs. the old plane configuration.
6645          */
6646         if (IS_GEN(dev_priv, 2) && planes_disabling(old_crtc_state, new_crtc_state))
6647                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6648 }
6649
6650 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
6651                                       struct intel_crtc *crtc)
6652 {
6653         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6654         const struct intel_crtc_state *new_crtc_state =
6655                 intel_atomic_get_new_crtc_state(state, crtc);
6656         unsigned int update_mask = new_crtc_state->update_planes;
6657         const struct intel_plane_state *old_plane_state;
6658         struct intel_plane *plane;
6659         unsigned fb_bits = 0;
6660         int i;
6661
6662         intel_crtc_dpms_overlay_disable(crtc);
6663
6664         for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
6665                 if (crtc->pipe != plane->pipe ||
6666                     !(update_mask & BIT(plane->id)))
6667                         continue;
6668
6669                 intel_disable_plane(plane, new_crtc_state);
6670
6671                 if (old_plane_state->uapi.visible)
6672                         fb_bits |= plane->frontbuffer_bit;
6673         }
6674
6675         intel_frontbuffer_flip(dev_priv, fb_bits);
6676 }
6677
6678 /*
6679  * intel_connector_primary_encoder - get the primary encoder for a connector
6680  * @connector: connector for which to return the encoder
6681  *
6682  * Returns the primary encoder for a connector. There is a 1:1 mapping from
6683  * all connectors to their encoder, except for DP-MST connectors which have
6684  * both a virtual and a primary encoder. These DP-MST primary encoders can be
6685  * pointed to by as many DP-MST connectors as there are pipes.
6686  */
6687 static struct intel_encoder *
6688 intel_connector_primary_encoder(struct intel_connector *connector)
6689 {
6690         struct intel_encoder *encoder;
6691
6692         if (connector->mst_port)
6693                 return &dp_to_dig_port(connector->mst_port)->base;
6694
6695         encoder = intel_attached_encoder(connector);
6696         drm_WARN_ON(connector->base.dev, !encoder);
6697
6698         return encoder;
6699 }
6700
6701 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
6702 {
6703         struct drm_connector_state *new_conn_state;
6704         struct drm_connector *connector;
6705         int i;
6706
6707         for_each_new_connector_in_state(&state->base, connector, new_conn_state,
6708                                         i) {
6709                 struct intel_connector *intel_connector;
6710                 struct intel_encoder *encoder;
6711                 struct intel_crtc *crtc;
6712
6713                 if (!intel_connector_needs_modeset(state, connector))
6714                         continue;
6715
6716                 intel_connector = to_intel_connector(connector);
6717                 encoder = intel_connector_primary_encoder(intel_connector);
6718                 if (!encoder->update_prepare)
6719                         continue;
6720
6721                 crtc = new_conn_state->crtc ?
6722                         to_intel_crtc(new_conn_state->crtc) : NULL;
6723                 encoder->update_prepare(state, encoder, crtc);
6724         }
6725 }
6726
6727 static void intel_encoders_update_complete(struct intel_atomic_state *state)
6728 {
6729         struct drm_connector_state *new_conn_state;
6730         struct drm_connector *connector;
6731         int i;
6732
6733         for_each_new_connector_in_state(&state->base, connector, new_conn_state,
6734                                         i) {
6735                 struct intel_connector *intel_connector;
6736                 struct intel_encoder *encoder;
6737                 struct intel_crtc *crtc;
6738
6739                 if (!intel_connector_needs_modeset(state, connector))
6740                         continue;
6741
6742                 intel_connector = to_intel_connector(connector);
6743                 encoder = intel_connector_primary_encoder(intel_connector);
6744                 if (!encoder->update_complete)
6745                         continue;
6746
6747                 crtc = new_conn_state->crtc ?
6748                         to_intel_crtc(new_conn_state->crtc) : NULL;
6749                 encoder->update_complete(state, encoder, crtc);
6750         }
6751 }
6752
6753 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
6754                                           struct intel_crtc *crtc)
6755 {
6756         const struct intel_crtc_state *crtc_state =
6757                 intel_atomic_get_new_crtc_state(state, crtc);
6758         const struct drm_connector_state *conn_state;
6759         struct drm_connector *conn;
6760         int i;
6761
6762         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6763                 struct intel_encoder *encoder =
6764                         to_intel_encoder(conn_state->best_encoder);
6765
6766                 if (conn_state->crtc != &crtc->base)
6767                         continue;
6768
6769                 if (encoder->pre_pll_enable)
6770                         encoder->pre_pll_enable(state, encoder,
6771                                                 crtc_state, conn_state);
6772         }
6773 }
6774
6775 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
6776                                       struct intel_crtc *crtc)
6777 {
6778         const struct intel_crtc_state *crtc_state =
6779                 intel_atomic_get_new_crtc_state(state, crtc);
6780         const struct drm_connector_state *conn_state;
6781         struct drm_connector *conn;
6782         int i;
6783
6784         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6785                 struct intel_encoder *encoder =
6786                         to_intel_encoder(conn_state->best_encoder);
6787
6788                 if (conn_state->crtc != &crtc->base)
6789                         continue;
6790
6791                 if (encoder->pre_enable)
6792                         encoder->pre_enable(state, encoder,
6793                                             crtc_state, conn_state);
6794         }
6795 }
6796
6797 static void intel_encoders_enable(struct intel_atomic_state *state,
6798                                   struct intel_crtc *crtc)
6799 {
6800         const struct intel_crtc_state *crtc_state =
6801                 intel_atomic_get_new_crtc_state(state, crtc);
6802         const struct drm_connector_state *conn_state;
6803         struct drm_connector *conn;
6804         int i;
6805
6806         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6807                 struct intel_encoder *encoder =
6808                         to_intel_encoder(conn_state->best_encoder);
6809
6810                 if (conn_state->crtc != &crtc->base)
6811                         continue;
6812
6813                 if (encoder->enable)
6814                         encoder->enable(state, encoder,
6815                                         crtc_state, conn_state);
6816                 intel_opregion_notify_encoder(encoder, true);
6817         }
6818 }
6819
6820 static void intel_encoders_disable(struct intel_atomic_state *state,
6821                                    struct intel_crtc *crtc)
6822 {
6823         const struct intel_crtc_state *old_crtc_state =
6824                 intel_atomic_get_old_crtc_state(state, crtc);
6825         const struct drm_connector_state *old_conn_state;
6826         struct drm_connector *conn;
6827         int i;
6828
6829         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6830                 struct intel_encoder *encoder =
6831                         to_intel_encoder(old_conn_state->best_encoder);
6832
6833                 if (old_conn_state->crtc != &crtc->base)
6834                         continue;
6835
6836                 intel_opregion_notify_encoder(encoder, false);
6837                 if (encoder->disable)
6838                         encoder->disable(state, encoder,
6839                                          old_crtc_state, old_conn_state);
6840         }
6841 }
6842
6843 static void intel_encoders_post_disable(struct intel_atomic_state *state,
6844                                         struct intel_crtc *crtc)
6845 {
6846         const struct intel_crtc_state *old_crtc_state =
6847                 intel_atomic_get_old_crtc_state(state, crtc);
6848         const struct drm_connector_state *old_conn_state;
6849         struct drm_connector *conn;
6850         int i;
6851
6852         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6853                 struct intel_encoder *encoder =
6854                         to_intel_encoder(old_conn_state->best_encoder);
6855
6856                 if (old_conn_state->crtc != &crtc->base)
6857                         continue;
6858
6859                 if (encoder->post_disable)
6860                         encoder->post_disable(state, encoder,
6861                                               old_crtc_state, old_conn_state);
6862         }
6863 }
6864
6865 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
6866                                             struct intel_crtc *crtc)
6867 {
6868         const struct intel_crtc_state *old_crtc_state =
6869                 intel_atomic_get_old_crtc_state(state, crtc);
6870         const struct drm_connector_state *old_conn_state;
6871         struct drm_connector *conn;
6872         int i;
6873
6874         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6875                 struct intel_encoder *encoder =
6876                         to_intel_encoder(old_conn_state->best_encoder);
6877
6878                 if (old_conn_state->crtc != &crtc->base)
6879                         continue;
6880
6881                 if (encoder->post_pll_disable)
6882                         encoder->post_pll_disable(state, encoder,
6883                                                   old_crtc_state, old_conn_state);
6884         }
6885 }
6886
6887 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
6888                                        struct intel_crtc *crtc)
6889 {
6890         const struct intel_crtc_state *crtc_state =
6891                 intel_atomic_get_new_crtc_state(state, crtc);
6892         const struct drm_connector_state *conn_state;
6893         struct drm_connector *conn;
6894         int i;
6895
6896         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6897                 struct intel_encoder *encoder =
6898                         to_intel_encoder(conn_state->best_encoder);
6899
6900                 if (conn_state->crtc != &crtc->base)
6901                         continue;
6902
6903                 if (encoder->update_pipe)
6904                         encoder->update_pipe(state, encoder,
6905                                              crtc_state, conn_state);
6906         }
6907 }
6908
6909 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
6910 {
6911         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6912         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
6913
6914         plane->disable_plane(plane, crtc_state);
6915 }
6916
6917 static void ilk_crtc_enable(struct intel_atomic_state *state,
6918                             struct intel_crtc *crtc)
6919 {
6920         const struct intel_crtc_state *new_crtc_state =
6921                 intel_atomic_get_new_crtc_state(state, crtc);
6922         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6923         enum pipe pipe = crtc->pipe;
6924
6925         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
6926                 return;
6927
6928         /*
6929          * Sometimes spurious CPU pipe underruns happen during FDI
6930          * training, at least with VGA+HDMI cloning. Suppress them.
6931          *
6932          * On ILK we get an occasional spurious CPU pipe underruns
6933          * between eDP port A enable and vdd enable. Also PCH port
6934          * enable seems to result in the occasional CPU pipe underrun.
6935          *
6936          * Spurious PCH underruns also occur during PCH enabling.
6937          */
6938         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6939         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
6940
6941         if (new_crtc_state->has_pch_encoder)
6942                 intel_prepare_shared_dpll(new_crtc_state);
6943
6944         if (intel_crtc_has_dp_encoder(new_crtc_state))
6945                 intel_dp_set_m_n(new_crtc_state, M1_N1);
6946
6947         intel_set_pipe_timings(new_crtc_state);
6948         intel_set_pipe_src_size(new_crtc_state);
6949
6950         if (new_crtc_state->has_pch_encoder)
6951                 intel_cpu_transcoder_set_m_n(new_crtc_state,
6952                                              &new_crtc_state->fdi_m_n, NULL);
6953
6954         ilk_set_pipeconf(new_crtc_state);
6955
6956         crtc->active = true;
6957
6958         intel_encoders_pre_enable(state, crtc);
6959
6960         if (new_crtc_state->has_pch_encoder) {
6961                 /* Note: FDI PLL enabling _must_ be done before we enable the
6962                  * cpu pipes, hence this is separate from all the other fdi/pch
6963                  * enabling. */
6964                 ilk_fdi_pll_enable(new_crtc_state);
6965         } else {
6966                 assert_fdi_tx_disabled(dev_priv, pipe);
6967                 assert_fdi_rx_disabled(dev_priv, pipe);
6968         }
6969
6970         ilk_pfit_enable(new_crtc_state);
6971
6972         /*
6973          * On ILK+ LUT must be loaded before the pipe is running but with
6974          * clocks enabled
6975          */
6976         intel_color_load_luts(new_crtc_state);
6977         intel_color_commit(new_crtc_state);
6978         /* update DSPCNTR to configure gamma for pipe bottom color */
6979         intel_disable_primary_plane(new_crtc_state);
6980
6981         if (dev_priv->display.initial_watermarks)
6982                 dev_priv->display.initial_watermarks(state, crtc);
6983         intel_enable_pipe(new_crtc_state);
6984
6985         if (new_crtc_state->has_pch_encoder)
6986                 ilk_pch_enable(state, new_crtc_state);
6987
6988         intel_crtc_vblank_on(new_crtc_state);
6989
6990         intel_encoders_enable(state, crtc);
6991
6992         if (HAS_PCH_CPT(dev_priv))
6993                 cpt_verify_modeset(dev_priv, pipe);
6994
6995         /*
6996          * Must wait for vblank to avoid spurious PCH FIFO underruns.
6997          * And a second vblank wait is needed at least on ILK with
6998          * some interlaced HDMI modes. Let's do the double wait always
6999          * in case there are more corner cases we don't know about.
7000          */
7001         if (new_crtc_state->has_pch_encoder) {
7002                 intel_wait_for_vblank(dev_priv, pipe);
7003                 intel_wait_for_vblank(dev_priv, pipe);
7004         }
7005         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7006         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
7007 }
7008
7009 /* IPS only exists on ULT machines and is tied to pipe A. */
7010 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
7011 {
7012         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
7013 }
7014
7015 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
7016                                             enum pipe pipe, bool apply)
7017 {
7018         u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe));
7019         u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
7020
7021         if (apply)
7022                 val |= mask;
7023         else
7024                 val &= ~mask;
7025
7026         intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
7027 }
7028
7029 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
7030 {
7031         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7032         enum pipe pipe = crtc->pipe;
7033         u32 val;
7034
7035         val = MBUS_DBOX_A_CREDIT(2);
7036
7037         if (INTEL_GEN(dev_priv) >= 12) {
7038                 val |= MBUS_DBOX_BW_CREDIT(2);
7039                 val |= MBUS_DBOX_B_CREDIT(12);
7040         } else {
7041                 val |= MBUS_DBOX_BW_CREDIT(1);
7042                 val |= MBUS_DBOX_B_CREDIT(8);
7043         }
7044
7045         intel_de_write(dev_priv, PIPE_MBUS_DBOX_CTL(pipe), val);
7046 }
7047
7048 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
7049 {
7050         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7051         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7052
7053         intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),
7054                        HSW_LINETIME(crtc_state->linetime) |
7055                        HSW_IPS_LINETIME(crtc_state->ips_linetime));
7056 }
7057
7058 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
7059 {
7060         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7061         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7062         i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
7063         u32 val;
7064
7065         val = intel_de_read(dev_priv, reg);
7066         val &= ~HSW_FRAME_START_DELAY_MASK;
7067         val |= HSW_FRAME_START_DELAY(0);
7068         intel_de_write(dev_priv, reg, val);
7069 }
7070
7071 static void hsw_crtc_enable(struct intel_atomic_state *state,
7072                             struct intel_crtc *crtc)
7073 {
7074         const struct intel_crtc_state *new_crtc_state =
7075                 intel_atomic_get_new_crtc_state(state, crtc);
7076         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7077         enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
7078         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
7079         bool psl_clkgate_wa;
7080
7081         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7082                 return;
7083
7084         intel_encoders_pre_pll_enable(state, crtc);
7085
7086         if (new_crtc_state->shared_dpll)
7087                 intel_enable_shared_dpll(new_crtc_state);
7088
7089         intel_encoders_pre_enable(state, crtc);
7090
7091         if (!transcoder_is_dsi(cpu_transcoder))
7092                 intel_set_pipe_timings(new_crtc_state);
7093
7094         intel_set_pipe_src_size(new_crtc_state);
7095
7096         if (cpu_transcoder != TRANSCODER_EDP &&
7097             !transcoder_is_dsi(cpu_transcoder))
7098                 intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
7099                                new_crtc_state->pixel_multiplier - 1);
7100
7101         if (new_crtc_state->has_pch_encoder)
7102                 intel_cpu_transcoder_set_m_n(new_crtc_state,
7103                                              &new_crtc_state->fdi_m_n, NULL);
7104
7105         if (!transcoder_is_dsi(cpu_transcoder)) {
7106                 hsw_set_frame_start_delay(new_crtc_state);
7107                 hsw_set_pipeconf(new_crtc_state);
7108         }
7109
7110         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
7111                 bdw_set_pipemisc(new_crtc_state);
7112
7113         crtc->active = true;
7114
7115         /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
7116         psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
7117                 new_crtc_state->pch_pfit.enabled;
7118         if (psl_clkgate_wa)
7119                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
7120
7121         if (INTEL_GEN(dev_priv) >= 9)
7122                 skl_pfit_enable(new_crtc_state);
7123         else
7124                 ilk_pfit_enable(new_crtc_state);
7125
7126         /*
7127          * On ILK+ LUT must be loaded before the pipe is running but with
7128          * clocks enabled
7129          */
7130         intel_color_load_luts(new_crtc_state);
7131         intel_color_commit(new_crtc_state);
7132         /* update DSPCNTR to configure gamma/csc for pipe bottom color */
7133         if (INTEL_GEN(dev_priv) < 9)
7134                 intel_disable_primary_plane(new_crtc_state);
7135
7136         hsw_set_linetime_wm(new_crtc_state);
7137
7138         if (INTEL_GEN(dev_priv) >= 11)
7139                 icl_set_pipe_chicken(crtc);
7140
7141         if (dev_priv->display.initial_watermarks)
7142                 dev_priv->display.initial_watermarks(state, crtc);
7143
7144         if (INTEL_GEN(dev_priv) >= 11)
7145                 icl_pipe_mbus_enable(crtc);
7146
7147         intel_encoders_enable(state, crtc);
7148
7149         if (psl_clkgate_wa) {
7150                 intel_wait_for_vblank(dev_priv, pipe);
7151                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
7152         }
7153
7154         /* If we change the relative order between pipe/planes enabling, we need
7155          * to change the workaround. */
7156         hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
7157         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
7158                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
7159                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
7160         }
7161 }
7162
7163 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
7164 {
7165         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
7166         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7167         enum pipe pipe = crtc->pipe;
7168
7169         /* To avoid upsetting the power well on haswell only disable the pfit if
7170          * it's in use. The hw state code will make sure we get this right. */
7171         if (!old_crtc_state->pch_pfit.enabled)
7172                 return;
7173
7174         intel_de_write(dev_priv, PF_CTL(pipe), 0);
7175         intel_de_write(dev_priv, PF_WIN_POS(pipe), 0);
7176         intel_de_write(dev_priv, PF_WIN_SZ(pipe), 0);
7177 }
7178
7179 static void ilk_crtc_disable(struct intel_atomic_state *state,
7180                              struct intel_crtc *crtc)
7181 {
7182         const struct intel_crtc_state *old_crtc_state =
7183                 intel_atomic_get_old_crtc_state(state, crtc);
7184         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7185         enum pipe pipe = crtc->pipe;
7186
7187         /*
7188          * Sometimes spurious CPU pipe underruns happen when the
7189          * pipe is already disabled, but FDI RX/TX is still enabled.
7190          * Happens at least with VGA+HDMI cloning. Suppress them.
7191          */
7192         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7193         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
7194
7195         intel_encoders_disable(state, crtc);
7196
7197         intel_crtc_vblank_off(old_crtc_state);
7198
7199         intel_disable_pipe(old_crtc_state);
7200
7201         ilk_pfit_disable(old_crtc_state);
7202
7203         if (old_crtc_state->has_pch_encoder)
7204                 ilk_fdi_disable(crtc);
7205
7206         intel_encoders_post_disable(state, crtc);
7207
7208         if (old_crtc_state->has_pch_encoder) {
7209                 ilk_disable_pch_transcoder(dev_priv, pipe);
7210
7211                 if (HAS_PCH_CPT(dev_priv)) {
7212                         i915_reg_t reg;
7213                         u32 temp;
7214
7215                         /* disable TRANS_DP_CTL */
7216                         reg = TRANS_DP_CTL(pipe);
7217                         temp = intel_de_read(dev_priv, reg);
7218                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
7219                                   TRANS_DP_PORT_SEL_MASK);
7220                         temp |= TRANS_DP_PORT_SEL_NONE;
7221                         intel_de_write(dev_priv, reg, temp);
7222
7223                         /* disable DPLL_SEL */
7224                         temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
7225                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
7226                         intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
7227                 }
7228
7229                 ilk_fdi_pll_disable(crtc);
7230         }
7231
7232         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7233         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
7234 }
7235
7236 static void hsw_crtc_disable(struct intel_atomic_state *state,
7237                              struct intel_crtc *crtc)
7238 {
7239         /*
7240          * FIXME collapse everything to one hook.
7241          * Need care with mst->ddi interactions.
7242          */
7243         intel_encoders_disable(state, crtc);
7244         intel_encoders_post_disable(state, crtc);
7245 }
7246
7247 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
7248 {
7249         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7250         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7251
7252         if (!crtc_state->gmch_pfit.control)
7253                 return;
7254
7255         /*
7256          * The panel fitter should only be adjusted whilst the pipe is disabled,
7257          * according to register description and PRM.
7258          */
7259         drm_WARN_ON(&dev_priv->drm,
7260                     intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
7261         assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
7262
7263         intel_de_write(dev_priv, PFIT_PGM_RATIOS,
7264                        crtc_state->gmch_pfit.pgm_ratios);
7265         intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
7266
7267         /* Border color in case we don't scale up to the full screen. Black by
7268          * default, change to something else for debugging. */
7269         intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
7270 }
7271
7272 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
7273 {
7274         if (phy == PHY_NONE)
7275                 return false;
7276         else if (IS_ROCKETLAKE(dev_priv))
7277                 return phy <= PHY_D;
7278         else if (IS_ELKHARTLAKE(dev_priv))
7279                 return phy <= PHY_C;
7280         else if (INTEL_GEN(dev_priv) >= 11)
7281                 return phy <= PHY_B;
7282         else
7283                 return false;
7284 }
7285
7286 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
7287 {
7288         if (IS_ROCKETLAKE(dev_priv))
7289                 return false;
7290         else if (INTEL_GEN(dev_priv) >= 12)
7291                 return phy >= PHY_D && phy <= PHY_I;
7292         else if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
7293                 return phy >= PHY_C && phy <= PHY_F;
7294         else
7295                 return false;
7296 }
7297
7298 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
7299 {
7300         if (IS_ROCKETLAKE(i915) && port >= PORT_D)
7301                 return (enum phy)port - 1;
7302         else if (IS_ELKHARTLAKE(i915) && port == PORT_D)
7303                 return PHY_A;
7304
7305         return (enum phy)port;
7306 }
7307
7308 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
7309 {
7310         if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
7311                 return PORT_TC_NONE;
7312
7313         if (INTEL_GEN(dev_priv) >= 12)
7314                 return port - PORT_D;
7315
7316         return port - PORT_C;
7317 }
7318
7319 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
7320 {
7321         switch (port) {
7322         case PORT_A:
7323                 return POWER_DOMAIN_PORT_DDI_A_LANES;
7324         case PORT_B:
7325                 return POWER_DOMAIN_PORT_DDI_B_LANES;
7326         case PORT_C:
7327                 return POWER_DOMAIN_PORT_DDI_C_LANES;
7328         case PORT_D:
7329                 return POWER_DOMAIN_PORT_DDI_D_LANES;
7330         case PORT_E:
7331                 return POWER_DOMAIN_PORT_DDI_E_LANES;
7332         case PORT_F:
7333                 return POWER_DOMAIN_PORT_DDI_F_LANES;
7334         case PORT_G:
7335                 return POWER_DOMAIN_PORT_DDI_G_LANES;
7336         case PORT_H:
7337                 return POWER_DOMAIN_PORT_DDI_H_LANES;
7338         case PORT_I:
7339                 return POWER_DOMAIN_PORT_DDI_I_LANES;
7340         default:
7341                 MISSING_CASE(port);
7342                 return POWER_DOMAIN_PORT_OTHER;
7343         }
7344 }
7345
7346 enum intel_display_power_domain
7347 intel_aux_power_domain(struct intel_digital_port *dig_port)
7348 {
7349         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
7350         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
7351
7352         if (intel_phy_is_tc(dev_priv, phy) &&
7353             dig_port->tc_mode == TC_PORT_TBT_ALT) {
7354                 switch (dig_port->aux_ch) {
7355                 case AUX_CH_C:
7356                         return POWER_DOMAIN_AUX_C_TBT;
7357                 case AUX_CH_D:
7358                         return POWER_DOMAIN_AUX_D_TBT;
7359                 case AUX_CH_E:
7360                         return POWER_DOMAIN_AUX_E_TBT;
7361                 case AUX_CH_F:
7362                         return POWER_DOMAIN_AUX_F_TBT;
7363                 case AUX_CH_G:
7364                         return POWER_DOMAIN_AUX_G_TBT;
7365                 case AUX_CH_H:
7366                         return POWER_DOMAIN_AUX_H_TBT;
7367                 case AUX_CH_I:
7368                         return POWER_DOMAIN_AUX_I_TBT;
7369                 default:
7370                         MISSING_CASE(dig_port->aux_ch);
7371                         return POWER_DOMAIN_AUX_C_TBT;
7372                 }
7373         }
7374
7375         return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
7376 }
7377
7378 /*
7379  * Converts aux_ch to power_domain without caring about TBT ports for that use
7380  * intel_aux_power_domain()
7381  */
7382 enum intel_display_power_domain
7383 intel_legacy_aux_to_power_domain(enum aux_ch aux_ch)
7384 {
7385         switch (aux_ch) {
7386         case AUX_CH_A:
7387                 return POWER_DOMAIN_AUX_A;
7388         case AUX_CH_B:
7389                 return POWER_DOMAIN_AUX_B;
7390         case AUX_CH_C:
7391                 return POWER_DOMAIN_AUX_C;
7392         case AUX_CH_D:
7393                 return POWER_DOMAIN_AUX_D;
7394         case AUX_CH_E:
7395                 return POWER_DOMAIN_AUX_E;
7396         case AUX_CH_F:
7397                 return POWER_DOMAIN_AUX_F;
7398         case AUX_CH_G:
7399                 return POWER_DOMAIN_AUX_G;
7400         case AUX_CH_H:
7401                 return POWER_DOMAIN_AUX_H;
7402         case AUX_CH_I:
7403                 return POWER_DOMAIN_AUX_I;
7404         default:
7405                 MISSING_CASE(aux_ch);
7406                 return POWER_DOMAIN_AUX_A;
7407         }
7408 }
7409
7410 static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
7411 {
7412         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7413         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7414         struct drm_encoder *encoder;
7415         enum pipe pipe = crtc->pipe;
7416         u64 mask;
7417         enum transcoder transcoder = crtc_state->cpu_transcoder;
7418
7419         if (!crtc_state->hw.active)
7420                 return 0;
7421
7422         mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
7423         mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
7424         if (crtc_state->pch_pfit.enabled ||
7425             crtc_state->pch_pfit.force_thru)
7426                 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
7427
7428         drm_for_each_encoder_mask(encoder, &dev_priv->drm,
7429                                   crtc_state->uapi.encoder_mask) {
7430                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
7431
7432                 mask |= BIT_ULL(intel_encoder->power_domain);
7433         }
7434
7435         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
7436                 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
7437
7438         if (crtc_state->shared_dpll)
7439                 mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
7440
7441         return mask;
7442 }
7443
7444 static u64
7445 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
7446 {
7447         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7448         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7449         enum intel_display_power_domain domain;
7450         u64 domains, new_domains, old_domains;
7451
7452         old_domains = crtc->enabled_power_domains;
7453         crtc->enabled_power_domains = new_domains =
7454                 get_crtc_power_domains(crtc_state);
7455
7456         domains = new_domains & ~old_domains;
7457
7458         for_each_power_domain(domain, domains)
7459                 intel_display_power_get(dev_priv, domain);
7460
7461         return old_domains & ~new_domains;
7462 }
7463
7464 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
7465                                       u64 domains)
7466 {
7467         enum intel_display_power_domain domain;
7468
7469         for_each_power_domain(domain, domains)
7470                 intel_display_power_put_unchecked(dev_priv, domain);
7471 }
7472
7473 static void valleyview_crtc_enable(struct intel_atomic_state *state,
7474                                    struct intel_crtc *crtc)
7475 {
7476         const struct intel_crtc_state *new_crtc_state =
7477                 intel_atomic_get_new_crtc_state(state, crtc);
7478         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7479         enum pipe pipe = crtc->pipe;
7480
7481         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7482                 return;
7483
7484         if (intel_crtc_has_dp_encoder(new_crtc_state))
7485                 intel_dp_set_m_n(new_crtc_state, M1_N1);
7486
7487         intel_set_pipe_timings(new_crtc_state);
7488         intel_set_pipe_src_size(new_crtc_state);
7489
7490         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
7491                 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
7492                 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
7493         }
7494
7495         i9xx_set_pipeconf(new_crtc_state);
7496
7497         crtc->active = true;
7498
7499         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7500
7501         intel_encoders_pre_pll_enable(state, crtc);
7502
7503         if (IS_CHERRYVIEW(dev_priv)) {
7504                 chv_prepare_pll(crtc, new_crtc_state);
7505                 chv_enable_pll(crtc, new_crtc_state);
7506         } else {
7507                 vlv_prepare_pll(crtc, new_crtc_state);
7508                 vlv_enable_pll(crtc, new_crtc_state);
7509         }
7510
7511         intel_encoders_pre_enable(state, crtc);
7512
7513         i9xx_pfit_enable(new_crtc_state);
7514
7515         intel_color_load_luts(new_crtc_state);
7516         intel_color_commit(new_crtc_state);
7517         /* update DSPCNTR to configure gamma for pipe bottom color */
7518         intel_disable_primary_plane(new_crtc_state);
7519
7520         dev_priv->display.initial_watermarks(state, crtc);
7521         intel_enable_pipe(new_crtc_state);
7522
7523         intel_crtc_vblank_on(new_crtc_state);
7524
7525         intel_encoders_enable(state, crtc);
7526 }
7527
7528 static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
7529 {
7530         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7531         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7532
7533         intel_de_write(dev_priv, FP0(crtc->pipe),
7534                        crtc_state->dpll_hw_state.fp0);
7535         intel_de_write(dev_priv, FP1(crtc->pipe),
7536                        crtc_state->dpll_hw_state.fp1);
7537 }
7538
7539 static void i9xx_crtc_enable(struct intel_atomic_state *state,
7540                              struct intel_crtc *crtc)
7541 {
7542         const struct intel_crtc_state *new_crtc_state =
7543                 intel_atomic_get_new_crtc_state(state, crtc);
7544         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7545         enum pipe pipe = crtc->pipe;
7546
7547         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7548                 return;
7549
7550         i9xx_set_pll_dividers(new_crtc_state);
7551
7552         if (intel_crtc_has_dp_encoder(new_crtc_state))
7553                 intel_dp_set_m_n(new_crtc_state, M1_N1);
7554
7555         intel_set_pipe_timings(new_crtc_state);
7556         intel_set_pipe_src_size(new_crtc_state);
7557
7558         i9xx_set_pipeconf(new_crtc_state);
7559
7560         crtc->active = true;
7561
7562         if (!IS_GEN(dev_priv, 2))
7563                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7564
7565         intel_encoders_pre_enable(state, crtc);
7566
7567         i9xx_enable_pll(crtc, new_crtc_state);
7568
7569         i9xx_pfit_enable(new_crtc_state);
7570
7571         intel_color_load_luts(new_crtc_state);
7572         intel_color_commit(new_crtc_state);
7573         /* update DSPCNTR to configure gamma for pipe bottom color */
7574         intel_disable_primary_plane(new_crtc_state);
7575
7576         if (dev_priv->display.initial_watermarks)
7577                 dev_priv->display.initial_watermarks(state, crtc);
7578         else
7579                 intel_update_watermarks(crtc);
7580         intel_enable_pipe(new_crtc_state);
7581
7582         intel_crtc_vblank_on(new_crtc_state);
7583
7584         intel_encoders_enable(state, crtc);
7585
7586         /* prevents spurious underruns */
7587         if (IS_GEN(dev_priv, 2))
7588                 intel_wait_for_vblank(dev_priv, pipe);
7589 }
7590
7591 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
7592 {
7593         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
7594         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7595
7596         if (!old_crtc_state->gmch_pfit.control)
7597                 return;
7598
7599         assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
7600
7601         drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
7602                     intel_de_read(dev_priv, PFIT_CONTROL));
7603         intel_de_write(dev_priv, PFIT_CONTROL, 0);
7604 }
7605
7606 static void i9xx_crtc_disable(struct intel_atomic_state *state,
7607                               struct intel_crtc *crtc)
7608 {
7609         struct intel_crtc_state *old_crtc_state =
7610                 intel_atomic_get_old_crtc_state(state, crtc);
7611         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7612         enum pipe pipe = crtc->pipe;
7613
7614         /*
7615          * On gen2 planes are double buffered but the pipe isn't, so we must
7616          * wait for planes to fully turn off before disabling the pipe.
7617          */
7618         if (IS_GEN(dev_priv, 2))
7619                 intel_wait_for_vblank(dev_priv, pipe);
7620
7621         intel_encoders_disable(state, crtc);
7622
7623         intel_crtc_vblank_off(old_crtc_state);
7624
7625         intel_disable_pipe(old_crtc_state);
7626
7627         i9xx_pfit_disable(old_crtc_state);
7628
7629         intel_encoders_post_disable(state, crtc);
7630
7631         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
7632                 if (IS_CHERRYVIEW(dev_priv))
7633                         chv_disable_pll(dev_priv, pipe);
7634                 else if (IS_VALLEYVIEW(dev_priv))
7635                         vlv_disable_pll(dev_priv, pipe);
7636                 else
7637                         i9xx_disable_pll(old_crtc_state);
7638         }
7639
7640         intel_encoders_post_pll_disable(state, crtc);
7641
7642         if (!IS_GEN(dev_priv, 2))
7643                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7644
7645         if (!dev_priv->display.initial_watermarks)
7646                 intel_update_watermarks(crtc);
7647
7648         /* clock the pipe down to 640x480@60 to potentially save power */
7649         if (IS_I830(dev_priv))
7650                 i830_enable_pipe(dev_priv, pipe);
7651 }
7652
7653 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
7654                                         struct drm_modeset_acquire_ctx *ctx)
7655 {
7656         struct intel_encoder *encoder;
7657         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7658         struct intel_bw_state *bw_state =
7659                 to_intel_bw_state(dev_priv->bw_obj.state);
7660         struct intel_cdclk_state *cdclk_state =
7661                 to_intel_cdclk_state(dev_priv->cdclk.obj.state);
7662         struct intel_dbuf_state *dbuf_state =
7663                 to_intel_dbuf_state(dev_priv->dbuf.obj.state);
7664         struct intel_crtc_state *crtc_state =
7665                 to_intel_crtc_state(crtc->base.state);
7666         enum intel_display_power_domain domain;
7667         struct intel_plane *plane;
7668         struct drm_atomic_state *state;
7669         struct intel_crtc_state *temp_crtc_state;
7670         enum pipe pipe = crtc->pipe;
7671         u64 domains;
7672         int ret;
7673
7674         if (!crtc_state->hw.active)
7675                 return;
7676
7677         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
7678                 const struct intel_plane_state *plane_state =
7679                         to_intel_plane_state(plane->base.state);
7680
7681                 if (plane_state->uapi.visible)
7682                         intel_plane_disable_noatomic(crtc, plane);
7683         }
7684
7685         state = drm_atomic_state_alloc(&dev_priv->drm);
7686         if (!state) {
7687                 drm_dbg_kms(&dev_priv->drm,
7688                             "failed to disable [CRTC:%d:%s], out of memory",
7689                             crtc->base.base.id, crtc->base.name);
7690                 return;
7691         }
7692
7693         state->acquire_ctx = ctx;
7694
7695         /* Everything's already locked, -EDEADLK can't happen. */
7696         temp_crtc_state = intel_atomic_get_crtc_state(state, crtc);
7697         ret = drm_atomic_add_affected_connectors(state, &crtc->base);
7698
7699         drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret);
7700
7701         dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc);
7702
7703         drm_atomic_state_put(state);
7704
7705         drm_dbg_kms(&dev_priv->drm,
7706                     "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
7707                     crtc->base.base.id, crtc->base.name);
7708
7709         crtc->active = false;
7710         crtc->base.enabled = false;
7711
7712         drm_WARN_ON(&dev_priv->drm,
7713                     drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0);
7714         crtc_state->uapi.active = false;
7715         crtc_state->uapi.connector_mask = 0;
7716         crtc_state->uapi.encoder_mask = 0;
7717         intel_crtc_free_hw_state(crtc_state);
7718         memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));
7719
7720         for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder)
7721                 encoder->base.crtc = NULL;
7722
7723         intel_fbc_disable(crtc);
7724         intel_update_watermarks(crtc);
7725         intel_disable_shared_dpll(crtc_state);
7726
7727         domains = crtc->enabled_power_domains;
7728         for_each_power_domain(domain, domains)
7729                 intel_display_power_put_unchecked(dev_priv, domain);
7730         crtc->enabled_power_domains = 0;
7731
7732         dev_priv->active_pipes &= ~BIT(pipe);
7733         cdclk_state->min_cdclk[pipe] = 0;
7734         cdclk_state->min_voltage_level[pipe] = 0;
7735         cdclk_state->active_pipes &= ~BIT(pipe);
7736
7737         dbuf_state->active_pipes &= ~BIT(pipe);
7738
7739         bw_state->data_rate[pipe] = 0;
7740         bw_state->num_active_planes[pipe] = 0;
7741 }
7742
7743 /*
7744  * turn all crtc's off, but do not adjust state
7745  * This has to be paired with a call to intel_modeset_setup_hw_state.
7746  */
7747 int intel_display_suspend(struct drm_device *dev)
7748 {
7749         struct drm_i915_private *dev_priv = to_i915(dev);
7750         struct drm_atomic_state *state;
7751         int ret;
7752
7753         state = drm_atomic_helper_suspend(dev);
7754         ret = PTR_ERR_OR_ZERO(state);
7755         if (ret)
7756                 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
7757                         ret);
7758         else
7759                 dev_priv->modeset_restore_state = state;
7760         return ret;
7761 }
7762
7763 void intel_encoder_destroy(struct drm_encoder *encoder)
7764 {
7765         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
7766
7767         drm_encoder_cleanup(encoder);
7768         kfree(intel_encoder);
7769 }
7770
7771 /* Cross check the actual hw state with our own modeset state tracking (and it's
7772  * internal consistency). */
7773 static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
7774                                          struct drm_connector_state *conn_state)
7775 {
7776         struct intel_connector *connector = to_intel_connector(conn_state->connector);
7777         struct drm_i915_private *i915 = to_i915(connector->base.dev);
7778
7779         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
7780                     connector->base.base.id, connector->base.name);
7781
7782         if (connector->get_hw_state(connector)) {
7783                 struct intel_encoder *encoder = intel_attached_encoder(connector);
7784
7785                 I915_STATE_WARN(!crtc_state,
7786                          "connector enabled without attached crtc\n");
7787
7788                 if (!crtc_state)
7789                         return;
7790
7791                 I915_STATE_WARN(!crtc_state->hw.active,
7792                                 "connector is active, but attached crtc isn't\n");
7793
7794                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
7795                         return;
7796
7797                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
7798                         "atomic encoder doesn't match attached encoder\n");
7799
7800                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
7801                         "attached encoder crtc differs from connector crtc\n");
7802         } else {
7803                 I915_STATE_WARN(crtc_state && crtc_state->hw.active,
7804                                 "attached crtc is active, but connector isn't\n");
7805                 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
7806                         "best encoder set without crtc!\n");
7807         }
7808 }
7809
7810 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7811 {
7812         if (crtc_state->hw.enable && crtc_state->has_pch_encoder)
7813                 return crtc_state->fdi_lanes;
7814
7815         return 0;
7816 }
7817
7818 static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7819                                struct intel_crtc_state *pipe_config)
7820 {
7821         struct drm_i915_private *dev_priv = to_i915(dev);
7822         struct drm_atomic_state *state = pipe_config->uapi.state;
7823         struct intel_crtc *other_crtc;
7824         struct intel_crtc_state *other_crtc_state;
7825
7826         drm_dbg_kms(&dev_priv->drm,
7827                     "checking fdi config on pipe %c, lanes %i\n",
7828                     pipe_name(pipe), pipe_config->fdi_lanes);
7829         if (pipe_config->fdi_lanes > 4) {
7830                 drm_dbg_kms(&dev_priv->drm,
7831                             "invalid fdi lane config on pipe %c: %i lanes\n",
7832                             pipe_name(pipe), pipe_config->fdi_lanes);
7833                 return -EINVAL;
7834         }
7835
7836         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7837                 if (pipe_config->fdi_lanes > 2) {
7838                         drm_dbg_kms(&dev_priv->drm,
7839                                     "only 2 lanes on haswell, required: %i lanes\n",
7840                                     pipe_config->fdi_lanes);
7841                         return -EINVAL;
7842                 } else {
7843                         return 0;
7844                 }
7845         }
7846
7847         if (INTEL_NUM_PIPES(dev_priv) == 2)
7848                 return 0;
7849
7850         /* Ivybridge 3 pipe is really complicated */
7851         switch (pipe) {
7852         case PIPE_A:
7853                 return 0;
7854         case PIPE_B:
7855                 if (pipe_config->fdi_lanes <= 2)
7856                         return 0;
7857
7858                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
7859                 other_crtc_state =
7860                         intel_atomic_get_crtc_state(state, other_crtc);
7861                 if (IS_ERR(other_crtc_state))
7862                         return PTR_ERR(other_crtc_state);
7863
7864                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7865                         drm_dbg_kms(&dev_priv->drm,
7866                                     "invalid shared fdi lane config on pipe %c: %i lanes\n",
7867                                     pipe_name(pipe), pipe_config->fdi_lanes);
7868                         return -EINVAL;
7869                 }
7870                 return 0;
7871         case PIPE_C:
7872                 if (pipe_config->fdi_lanes > 2) {
7873                         drm_dbg_kms(&dev_priv->drm,
7874                                     "only 2 lanes on pipe %c: required %i lanes\n",
7875                                     pipe_name(pipe), pipe_config->fdi_lanes);
7876                         return -EINVAL;
7877                 }
7878
7879                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
7880                 other_crtc_state =
7881                         intel_atomic_get_crtc_state(state, other_crtc);
7882                 if (IS_ERR(other_crtc_state))
7883                         return PTR_ERR(other_crtc_state);
7884
7885                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7886                         drm_dbg_kms(&dev_priv->drm,
7887                                     "fdi link B uses too many lanes to enable link C\n");
7888                         return -EINVAL;
7889                 }
7890                 return 0;
7891         default:
7892                 BUG();
7893         }
7894 }
7895
7896 #define RETRY 1
7897 static int ilk_fdi_compute_config(struct intel_crtc *intel_crtc,
7898                                   struct intel_crtc_state *pipe_config)
7899 {
7900         struct drm_device *dev = intel_crtc->base.dev;
7901         struct drm_i915_private *i915 = to_i915(dev);
7902         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
7903         int lane, link_bw, fdi_dotclock, ret;
7904         bool needs_recompute = false;
7905
7906 retry:
7907         /* FDI is a binary signal running at ~2.7GHz, encoding
7908          * each output octet as 10 bits. The actual frequency
7909          * is stored as a divider into a 100MHz clock, and the
7910          * mode pixel clock is stored in units of 1KHz.
7911          * Hence the bw of each lane in terms of the mode signal
7912          * is:
7913          */
7914         link_bw = intel_fdi_link_freq(i915, pipe_config);
7915
7916         fdi_dotclock = adjusted_mode->crtc_clock;
7917
7918         lane = ilk_get_lanes_required(fdi_dotclock, link_bw,
7919                                       pipe_config->pipe_bpp);
7920
7921         pipe_config->fdi_lanes = lane;
7922
7923         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7924                                link_bw, &pipe_config->fdi_m_n, false, false);
7925
7926         ret = ilk_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7927         if (ret == -EDEADLK)
7928                 return ret;
7929
7930         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7931                 pipe_config->pipe_bpp -= 2*3;
7932                 drm_dbg_kms(&i915->drm,
7933                             "fdi link bw constraint, reducing pipe bpp to %i\n",
7934                             pipe_config->pipe_bpp);
7935                 needs_recompute = true;
7936                 pipe_config->bw_constrained = true;
7937
7938                 goto retry;
7939         }
7940
7941         if (needs_recompute)
7942                 return RETRY;
7943
7944         return ret;
7945 }
7946
7947 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
7948 {
7949         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7950         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7951
7952         /* IPS only exists on ULT machines and is tied to pipe A. */
7953         if (!hsw_crtc_supports_ips(crtc))
7954                 return false;
7955
7956         if (!dev_priv->params.enable_ips)
7957                 return false;
7958
7959         if (crtc_state->pipe_bpp > 24)
7960                 return false;
7961
7962         /*
7963          * We compare against max which means we must take
7964          * the increased cdclk requirement into account when
7965          * calculating the new cdclk.
7966          *
7967          * Should measure whether using a lower cdclk w/o IPS
7968          */
7969         if (IS_BROADWELL(dev_priv) &&
7970             crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
7971                 return false;
7972
7973         return true;
7974 }
7975
7976 static int hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
7977 {
7978         struct drm_i915_private *dev_priv =
7979                 to_i915(crtc_state->uapi.crtc->dev);
7980         struct intel_atomic_state *state =
7981                 to_intel_atomic_state(crtc_state->uapi.state);
7982
7983         crtc_state->ips_enabled = false;
7984
7985         if (!hsw_crtc_state_ips_capable(crtc_state))
7986                 return 0;
7987
7988         /*
7989          * When IPS gets enabled, the pipe CRC changes. Since IPS gets
7990          * enabled and disabled dynamically based on package C states,
7991          * user space can't make reliable use of the CRCs, so let's just
7992          * completely disable it.
7993          */
7994         if (crtc_state->crc_enabled)
7995                 return 0;
7996
7997         /* IPS should be fine as long as at least one plane is enabled. */
7998         if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
7999                 return 0;
8000
8001         if (IS_BROADWELL(dev_priv)) {
8002                 const struct intel_cdclk_state *cdclk_state;
8003
8004                 cdclk_state = intel_atomic_get_cdclk_state(state);
8005                 if (IS_ERR(cdclk_state))
8006                         return PTR_ERR(cdclk_state);
8007
8008                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
8009                 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
8010                         return 0;
8011         }
8012
8013         crtc_state->ips_enabled = true;
8014
8015         return 0;
8016 }
8017
8018 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
8019 {
8020         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8021
8022         /* GDG double wide on either pipe, otherwise pipe A only */
8023         return INTEL_GEN(dev_priv) < 4 &&
8024                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
8025 }
8026
8027 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
8028 {
8029         u32 pixel_rate = crtc_state->hw.adjusted_mode.crtc_clock;
8030         unsigned int pipe_w, pipe_h, pfit_w, pfit_h;
8031
8032         /*
8033          * We only use IF-ID interlacing. If we ever use
8034          * PF-ID we'll need to adjust the pixel_rate here.
8035          */
8036
8037         if (!crtc_state->pch_pfit.enabled)
8038                 return pixel_rate;
8039
8040         pipe_w = crtc_state->pipe_src_w;
8041         pipe_h = crtc_state->pipe_src_h;
8042
8043         pfit_w = drm_rect_width(&crtc_state->pch_pfit.dst);
8044         pfit_h = drm_rect_height(&crtc_state->pch_pfit.dst);
8045
8046         if (pipe_w < pfit_w)
8047                 pipe_w = pfit_w;
8048         if (pipe_h < pfit_h)
8049                 pipe_h = pfit_h;
8050
8051         if (drm_WARN_ON(crtc_state->uapi.crtc->dev,
8052                         !pfit_w || !pfit_h))
8053                 return pixel_rate;
8054
8055         return div_u64(mul_u32_u32(pixel_rate, pipe_w * pipe_h),
8056                        pfit_w * pfit_h);
8057 }
8058
8059 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
8060 {
8061         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
8062
8063         if (HAS_GMCH(dev_priv))
8064                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
8065                 crtc_state->pixel_rate =
8066                         crtc_state->hw.adjusted_mode.crtc_clock;
8067         else
8068                 crtc_state->pixel_rate =
8069                         ilk_pipe_pixel_rate(crtc_state);
8070 }
8071
8072 static int intel_crtc_compute_config(struct intel_crtc *crtc,
8073                                      struct intel_crtc_state *pipe_config)
8074 {
8075         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8076         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
8077         int clock_limit = dev_priv->max_dotclk_freq;
8078
8079         if (INTEL_GEN(dev_priv) < 4) {
8080                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
8081
8082                 /*
8083                  * Enable double wide mode when the dot clock
8084                  * is > 90% of the (display) core speed.
8085                  */
8086                 if (intel_crtc_supports_double_wide(crtc) &&
8087                     adjusted_mode->crtc_clock > clock_limit) {
8088                         clock_limit = dev_priv->max_dotclk_freq;
8089                         pipe_config->double_wide = true;
8090                 }
8091         }
8092
8093         if (adjusted_mode->crtc_clock > clock_limit) {
8094                 drm_dbg_kms(&dev_priv->drm,
8095                             "requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
8096                             adjusted_mode->crtc_clock, clock_limit,
8097                             yesno(pipe_config->double_wide));
8098                 return -EINVAL;
8099         }
8100
8101         if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
8102              pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
8103              pipe_config->hw.ctm) {
8104                 /*
8105                  * There is only one pipe CSC unit per pipe, and we need that
8106                  * for output conversion from RGB->YCBCR. So if CTM is already
8107                  * applied we can't support YCBCR420 output.
8108                  */
8109                 drm_dbg_kms(&dev_priv->drm,
8110                             "YCBCR420 and CTM together are not possible\n");
8111                 return -EINVAL;
8112         }
8113
8114         /*
8115          * Pipe horizontal size must be even in:
8116          * - DVO ganged mode
8117          * - LVDS dual channel mode
8118          * - Double wide pipe
8119          */
8120         if (pipe_config->pipe_src_w & 1) {
8121                 if (pipe_config->double_wide) {
8122                         drm_dbg_kms(&dev_priv->drm,
8123                                     "Odd pipe source width not supported with double wide pipe\n");
8124                         return -EINVAL;
8125                 }
8126
8127                 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
8128                     intel_is_dual_link_lvds(dev_priv)) {
8129                         drm_dbg_kms(&dev_priv->drm,
8130                                     "Odd pipe source width not supported with dual link LVDS\n");
8131                         return -EINVAL;
8132                 }
8133         }
8134
8135         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
8136          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
8137          */
8138         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
8139                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
8140                 return -EINVAL;
8141
8142         intel_crtc_compute_pixel_rate(pipe_config);
8143
8144         if (pipe_config->has_pch_encoder)
8145                 return ilk_fdi_compute_config(crtc, pipe_config);
8146
8147         return 0;
8148 }
8149
8150 static void
8151 intel_reduce_m_n_ratio(u32 *num, u32 *den)
8152 {
8153         while (*num > DATA_LINK_M_N_MASK ||
8154                *den > DATA_LINK_M_N_MASK) {
8155                 *num >>= 1;
8156                 *den >>= 1;
8157         }
8158 }
8159
8160 static void compute_m_n(unsigned int m, unsigned int n,
8161                         u32 *ret_m, u32 *ret_n,
8162                         bool constant_n)
8163 {
8164         /*
8165          * Several DP dongles in particular seem to be fussy about
8166          * too large link M/N values. Give N value as 0x8000 that
8167          * should be acceptable by specific devices. 0x8000 is the
8168          * specified fixed N value for asynchronous clock mode,
8169          * which the devices expect also in synchronous clock mode.
8170          */
8171         if (constant_n)
8172                 *ret_n = DP_LINK_CONSTANT_N_VALUE;
8173         else
8174                 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
8175
8176         *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
8177         intel_reduce_m_n_ratio(ret_m, ret_n);
8178 }
8179
8180 void
8181 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
8182                        int pixel_clock, int link_clock,
8183                        struct intel_link_m_n *m_n,
8184                        bool constant_n, bool fec_enable)
8185 {
8186         u32 data_clock = bits_per_pixel * pixel_clock;
8187
8188         if (fec_enable)
8189                 data_clock = intel_dp_mode_to_fec_clock(data_clock);
8190
8191         m_n->tu = 64;
8192         compute_m_n(data_clock,
8193                     link_clock * nlanes * 8,
8194                     &m_n->gmch_m, &m_n->gmch_n,
8195                     constant_n);
8196
8197         compute_m_n(pixel_clock, link_clock,
8198                     &m_n->link_m, &m_n->link_n,
8199                     constant_n);
8200 }
8201
8202 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
8203 {
8204         /*
8205          * There may be no VBT; and if the BIOS enabled SSC we can
8206          * just keep using it to avoid unnecessary flicker.  Whereas if the
8207          * BIOS isn't using it, don't assume it will work even if the VBT
8208          * indicates as much.
8209          */
8210         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
8211                 bool bios_lvds_use_ssc = intel_de_read(dev_priv,
8212                                                        PCH_DREF_CONTROL) &
8213                         DREF_SSC1_ENABLE;
8214
8215                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
8216                         drm_dbg_kms(&dev_priv->drm,
8217                                     "SSC %s by BIOS, overriding VBT which says %s\n",
8218                                     enableddisabled(bios_lvds_use_ssc),
8219                                     enableddisabled(dev_priv->vbt.lvds_use_ssc));
8220                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
8221                 }
8222         }
8223 }
8224
8225 static bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
8226 {
8227         if (dev_priv->params.panel_use_ssc >= 0)
8228                 return dev_priv->params.panel_use_ssc != 0;
8229         return dev_priv->vbt.lvds_use_ssc
8230                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
8231 }
8232
8233 static u32 pnv_dpll_compute_fp(struct dpll *dpll)
8234 {
8235         return (1 << dpll->n) << 16 | dpll->m2;
8236 }
8237
8238 static u32 i9xx_dpll_compute_fp(struct dpll *dpll)
8239 {
8240         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
8241 }
8242
8243 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
8244                                      struct intel_crtc_state *crtc_state,
8245                                      struct dpll *reduced_clock)
8246 {
8247         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8248         u32 fp, fp2 = 0;
8249
8250         if (IS_PINEVIEW(dev_priv)) {
8251                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
8252                 if (reduced_clock)
8253                         fp2 = pnv_dpll_compute_fp(reduced_clock);
8254         } else {
8255                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8256                 if (reduced_clock)
8257                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
8258         }
8259
8260         crtc_state->dpll_hw_state.fp0 = fp;
8261
8262         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8263             reduced_clock) {
8264                 crtc_state->dpll_hw_state.fp1 = fp2;
8265         } else {
8266                 crtc_state->dpll_hw_state.fp1 = fp;
8267         }
8268 }
8269
8270 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
8271                 pipe)
8272 {
8273         u32 reg_val;
8274
8275         /*
8276          * PLLB opamp always calibrates to max value of 0x3f, force enable it
8277          * and set it to a reasonable value instead.
8278          */
8279         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
8280         reg_val &= 0xffffff00;
8281         reg_val |= 0x00000030;
8282         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
8283
8284         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
8285         reg_val &= 0x00ffffff;
8286         reg_val |= 0x8c000000;
8287         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
8288
8289         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
8290         reg_val &= 0xffffff00;
8291         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
8292
8293         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
8294         reg_val &= 0x00ffffff;
8295         reg_val |= 0xb0000000;
8296         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
8297 }
8298
8299 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
8300                                          const struct intel_link_m_n *m_n)
8301 {
8302         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8303         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8304         enum pipe pipe = crtc->pipe;
8305
8306         intel_de_write(dev_priv, PCH_TRANS_DATA_M1(pipe),
8307                        TU_SIZE(m_n->tu) | m_n->gmch_m);
8308         intel_de_write(dev_priv, PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
8309         intel_de_write(dev_priv, PCH_TRANS_LINK_M1(pipe), m_n->link_m);
8310         intel_de_write(dev_priv, PCH_TRANS_LINK_N1(pipe), m_n->link_n);
8311 }
8312
8313 static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
8314                                  enum transcoder transcoder)
8315 {
8316         if (IS_HASWELL(dev_priv))
8317                 return transcoder == TRANSCODER_EDP;
8318
8319         /*
8320          * Strictly speaking some registers are available before
8321          * gen7, but we only support DRRS on gen7+
8322          */
8323         return IS_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv);
8324 }
8325
8326 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
8327                                          const struct intel_link_m_n *m_n,
8328                                          const struct intel_link_m_n *m2_n2)
8329 {
8330         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8331         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8332         enum pipe pipe = crtc->pipe;
8333         enum transcoder transcoder = crtc_state->cpu_transcoder;
8334
8335         if (INTEL_GEN(dev_priv) >= 5) {
8336                 intel_de_write(dev_priv, PIPE_DATA_M1(transcoder),
8337                                TU_SIZE(m_n->tu) | m_n->gmch_m);
8338                 intel_de_write(dev_priv, PIPE_DATA_N1(transcoder),
8339                                m_n->gmch_n);
8340                 intel_de_write(dev_priv, PIPE_LINK_M1(transcoder),
8341                                m_n->link_m);
8342                 intel_de_write(dev_priv, PIPE_LINK_N1(transcoder),
8343                                m_n->link_n);
8344                 /*
8345                  *  M2_N2 registers are set only if DRRS is supported
8346                  * (to make sure the registers are not unnecessarily accessed).
8347                  */
8348                 if (m2_n2 && crtc_state->has_drrs &&
8349                     transcoder_has_m2_n2(dev_priv, transcoder)) {
8350                         intel_de_write(dev_priv, PIPE_DATA_M2(transcoder),
8351                                        TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
8352                         intel_de_write(dev_priv, PIPE_DATA_N2(transcoder),
8353                                        m2_n2->gmch_n);
8354                         intel_de_write(dev_priv, PIPE_LINK_M2(transcoder),
8355                                        m2_n2->link_m);
8356                         intel_de_write(dev_priv, PIPE_LINK_N2(transcoder),
8357                                        m2_n2->link_n);
8358                 }
8359         } else {
8360                 intel_de_write(dev_priv, PIPE_DATA_M_G4X(pipe),
8361                                TU_SIZE(m_n->tu) | m_n->gmch_m);
8362                 intel_de_write(dev_priv, PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
8363                 intel_de_write(dev_priv, PIPE_LINK_M_G4X(pipe), m_n->link_m);
8364                 intel_de_write(dev_priv, PIPE_LINK_N_G4X(pipe), m_n->link_n);
8365         }
8366 }
8367
8368 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
8369 {
8370         const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
8371         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
8372
8373         if (m_n == M1_N1) {
8374                 dp_m_n = &crtc_state->dp_m_n;
8375                 dp_m2_n2 = &crtc_state->dp_m2_n2;
8376         } else if (m_n == M2_N2) {
8377
8378                 /*
8379                  * M2_N2 registers are not supported. Hence m2_n2 divider value
8380                  * needs to be programmed into M1_N1.
8381                  */
8382                 dp_m_n = &crtc_state->dp_m2_n2;
8383         } else {
8384                 drm_err(&i915->drm, "Unsupported divider value\n");
8385                 return;
8386         }
8387
8388         if (crtc_state->has_pch_encoder)
8389                 intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);
8390         else
8391                 intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
8392 }
8393
8394 static void vlv_compute_dpll(struct intel_crtc *crtc,
8395                              struct intel_crtc_state *pipe_config)
8396 {
8397         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
8398                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
8399         if (crtc->pipe != PIPE_A)
8400                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
8401
8402         /* DPLL not used with DSI, but still need the rest set up */
8403         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
8404                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
8405                         DPLL_EXT_BUFFER_ENABLE_VLV;
8406
8407         pipe_config->dpll_hw_state.dpll_md =
8408                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8409 }
8410
8411 static void chv_compute_dpll(struct intel_crtc *crtc,
8412                              struct intel_crtc_state *pipe_config)
8413 {
8414         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
8415                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
8416         if (crtc->pipe != PIPE_A)
8417                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
8418
8419         /* DPLL not used with DSI, but still need the rest set up */
8420         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
8421                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
8422
8423         pipe_config->dpll_hw_state.dpll_md =
8424                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8425 }
8426
8427 static void vlv_prepare_pll(struct intel_crtc *crtc,
8428                             const struct intel_crtc_state *pipe_config)
8429 {
8430         struct drm_device *dev = crtc->base.dev;
8431         struct drm_i915_private *dev_priv = to_i915(dev);
8432         enum pipe pipe = crtc->pipe;
8433         u32 mdiv;
8434         u32 bestn, bestm1, bestm2, bestp1, bestp2;
8435         u32 coreclk, reg_val;
8436
8437         /* Enable Refclk */
8438         intel_de_write(dev_priv, DPLL(pipe),
8439                        pipe_config->dpll_hw_state.dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
8440
8441         /* No need to actually set up the DPLL with DSI */
8442         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8443                 return;
8444
8445         vlv_dpio_get(dev_priv);
8446
8447         bestn = pipe_config->dpll.n;
8448         bestm1 = pipe_config->dpll.m1;
8449         bestm2 = pipe_config->dpll.m2;
8450         bestp1 = pipe_config->dpll.p1;
8451         bestp2 = pipe_config->dpll.p2;
8452
8453         /* See eDP HDMI DPIO driver vbios notes doc */
8454
8455         /* PLL B needs special handling */
8456         if (pipe == PIPE_B)
8457                 vlv_pllb_recal_opamp(dev_priv, pipe);
8458
8459         /* Set up Tx target for periodic Rcomp update */
8460         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
8461
8462         /* Disable target IRef on PLL */
8463         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
8464         reg_val &= 0x00ffffff;
8465         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
8466
8467         /* Disable fast lock */
8468         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
8469
8470         /* Set idtafcrecal before PLL is enabled */
8471         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
8472         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
8473         mdiv |= ((bestn << DPIO_N_SHIFT));
8474         mdiv |= (1 << DPIO_K_SHIFT);
8475
8476         /*
8477          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
8478          * but we don't support that).
8479          * Note: don't use the DAC post divider as it seems unstable.
8480          */
8481         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
8482         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
8483
8484         mdiv |= DPIO_ENABLE_CALIBRATION;
8485         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
8486
8487         /* Set HBR and RBR LPF coefficients */
8488         if (pipe_config->port_clock == 162000 ||
8489             intel_crtc_has_type(pipe_config, INTEL_OUTPUT_ANALOG) ||
8490             intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
8491                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
8492                                  0x009f0003);
8493         else
8494                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
8495                                  0x00d0000f);
8496
8497         if (intel_crtc_has_dp_encoder(pipe_config)) {
8498                 /* Use SSC source */
8499                 if (pipe == PIPE_A)
8500                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8501                                          0x0df40000);
8502                 else
8503                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8504                                          0x0df70000);
8505         } else { /* HDMI or VGA */
8506                 /* Use bend source */
8507                 if (pipe == PIPE_A)
8508                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8509                                          0x0df70000);
8510                 else
8511                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8512                                          0x0df40000);
8513         }
8514
8515         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
8516         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
8517         if (intel_crtc_has_dp_encoder(pipe_config))
8518                 coreclk |= 0x01000000;
8519         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
8520
8521         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
8522
8523         vlv_dpio_put(dev_priv);
8524 }
8525
8526 static void chv_prepare_pll(struct intel_crtc *crtc,
8527                             const struct intel_crtc_state *pipe_config)
8528 {
8529         struct drm_device *dev = crtc->base.dev;
8530         struct drm_i915_private *dev_priv = to_i915(dev);
8531         enum pipe pipe = crtc->pipe;
8532         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8533         u32 loopfilter, tribuf_calcntr;
8534         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
8535         u32 dpio_val;
8536         int vco;
8537
8538         /* Enable Refclk and SSC */
8539         intel_de_write(dev_priv, DPLL(pipe),
8540                        pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
8541
8542         /* No need to actually set up the DPLL with DSI */
8543         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8544                 return;
8545
8546         bestn = pipe_config->dpll.n;
8547         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
8548         bestm1 = pipe_config->dpll.m1;
8549         bestm2 = pipe_config->dpll.m2 >> 22;
8550         bestp1 = pipe_config->dpll.p1;
8551         bestp2 = pipe_config->dpll.p2;
8552         vco = pipe_config->dpll.vco;
8553         dpio_val = 0;
8554         loopfilter = 0;
8555
8556         vlv_dpio_get(dev_priv);
8557
8558         /* p1 and p2 divider */
8559         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
8560                         5 << DPIO_CHV_S1_DIV_SHIFT |
8561                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
8562                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
8563                         1 << DPIO_CHV_K_DIV_SHIFT);
8564
8565         /* Feedback post-divider - m2 */
8566         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
8567
8568         /* Feedback refclk divider - n and m1 */
8569         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8570                         DPIO_CHV_M1_DIV_BY_2 |
8571                         1 << DPIO_CHV_N_DIV_SHIFT);
8572
8573         /* M2 fraction division */
8574         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8575
8576         /* M2 fraction division enable */
8577         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8578         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8579         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8580         if (bestm2_frac)
8581                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8582         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8583
8584         /* Program digital lock detect threshold */
8585         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8586         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8587                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8588         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8589         if (!bestm2_frac)
8590                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8591         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8592
8593         /* Loop filter */
8594         if (vco == 5400000) {
8595                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8596                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8597                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8598                 tribuf_calcntr = 0x9;
8599         } else if (vco <= 6200000) {
8600                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8601                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8602                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8603                 tribuf_calcntr = 0x9;
8604         } else if (vco <= 6480000) {
8605                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8606                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8607                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8608                 tribuf_calcntr = 0x8;
8609         } else {
8610                 /* Not supported. Apply the same limits as in the max case */
8611                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8612                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8613                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8614                 tribuf_calcntr = 0;
8615         }
8616         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8617
8618         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8619         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8620         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8621         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8622
8623         /* AFC Recal */
8624         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8625                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8626                         DPIO_AFC_RECAL);
8627
8628         vlv_dpio_put(dev_priv);
8629 }
8630
8631 /**
8632  * vlv_force_pll_on - forcibly enable just the PLL
8633  * @dev_priv: i915 private structure
8634  * @pipe: pipe PLL to enable
8635  * @dpll: PLL configuration
8636  *
8637  * Enable the PLL for @pipe using the supplied @dpll config. To be used
8638  * in cases where we need the PLL enabled even when @pipe is not going to
8639  * be enabled.
8640  */
8641 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
8642                      const struct dpll *dpll)
8643 {
8644         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
8645         struct intel_crtc_state *pipe_config;
8646
8647         pipe_config = intel_crtc_state_alloc(crtc);
8648         if (!pipe_config)
8649                 return -ENOMEM;
8650
8651         pipe_config->cpu_transcoder = (enum transcoder)pipe;
8652         pipe_config->pixel_multiplier = 1;
8653         pipe_config->dpll = *dpll;
8654
8655         if (IS_CHERRYVIEW(dev_priv)) {
8656                 chv_compute_dpll(crtc, pipe_config);
8657                 chv_prepare_pll(crtc, pipe_config);
8658                 chv_enable_pll(crtc, pipe_config);
8659         } else {
8660                 vlv_compute_dpll(crtc, pipe_config);
8661                 vlv_prepare_pll(crtc, pipe_config);
8662                 vlv_enable_pll(crtc, pipe_config);
8663         }
8664
8665         kfree(pipe_config);
8666
8667         return 0;
8668 }
8669
8670 /**
8671  * vlv_force_pll_off - forcibly disable just the PLL
8672  * @dev_priv: i915 private structure
8673  * @pipe: pipe PLL to disable
8674  *
8675  * Disable the PLL for @pipe. To be used in cases where we need
8676  * the PLL enabled even when @pipe is not going to be enabled.
8677  */
8678 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
8679 {
8680         if (IS_CHERRYVIEW(dev_priv))
8681                 chv_disable_pll(dev_priv, pipe);
8682         else
8683                 vlv_disable_pll(dev_priv, pipe);
8684 }
8685
8686 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8687                               struct intel_crtc_state *crtc_state,
8688                               struct dpll *reduced_clock)
8689 {
8690         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8691         u32 dpll;
8692         struct dpll *clock = &crtc_state->dpll;
8693
8694         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8695
8696         dpll = DPLL_VGA_MODE_DIS;
8697
8698         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8699                 dpll |= DPLLB_MODE_LVDS;
8700         else
8701                 dpll |= DPLLB_MODE_DAC_SERIAL;
8702
8703         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8704             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8705                 dpll |= (crtc_state->pixel_multiplier - 1)
8706                         << SDVO_MULTIPLIER_SHIFT_HIRES;
8707         }
8708
8709         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8710             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8711                 dpll |= DPLL_SDVO_HIGH_SPEED;
8712
8713         if (intel_crtc_has_dp_encoder(crtc_state))
8714                 dpll |= DPLL_SDVO_HIGH_SPEED;
8715
8716         /* compute bitmask from p1 value */
8717         if (IS_PINEVIEW(dev_priv))
8718                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8719         else {
8720                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8721                 if (IS_G4X(dev_priv) && reduced_clock)
8722                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8723         }
8724         switch (clock->p2) {
8725         case 5:
8726                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8727                 break;
8728         case 7:
8729                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8730                 break;
8731         case 10:
8732                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8733                 break;
8734         case 14:
8735                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8736                 break;
8737         }
8738         if (INTEL_GEN(dev_priv) >= 4)
8739                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8740
8741         if (crtc_state->sdvo_tv_clock)
8742                 dpll |= PLL_REF_INPUT_TVCLKINBC;
8743         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8744                  intel_panel_use_ssc(dev_priv))
8745                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8746         else
8747                 dpll |= PLL_REF_INPUT_DREFCLK;
8748
8749         dpll |= DPLL_VCO_ENABLE;
8750         crtc_state->dpll_hw_state.dpll = dpll;
8751
8752         if (INTEL_GEN(dev_priv) >= 4) {
8753                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8754                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8755                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8756         }
8757 }
8758
8759 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8760                               struct intel_crtc_state *crtc_state,
8761                               struct dpll *reduced_clock)
8762 {
8763         struct drm_device *dev = crtc->base.dev;
8764         struct drm_i915_private *dev_priv = to_i915(dev);
8765         u32 dpll;
8766         struct dpll *clock = &crtc_state->dpll;
8767
8768         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8769
8770         dpll = DPLL_VGA_MODE_DIS;
8771
8772         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8773                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8774         } else {
8775                 if (clock->p1 == 2)
8776                         dpll |= PLL_P1_DIVIDE_BY_TWO;
8777                 else
8778                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8779                 if (clock->p2 == 4)
8780                         dpll |= PLL_P2_DIVIDE_BY_4;
8781         }
8782
8783         /*
8784          * Bspec:
8785          * "[Almador Errata}: For the correct operation of the muxed DVO pins
8786          *  (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
8787          *  GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
8788          *  Enable) must be set to “1” in both the DPLL A Control Register
8789          *  (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
8790          *
8791          * For simplicity We simply keep both bits always enabled in
8792          * both DPLLS. The spec says we should disable the DVO 2X clock
8793          * when not needed, but this seems to work fine in practice.
8794          */
8795         if (IS_I830(dev_priv) ||
8796             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8797                 dpll |= DPLL_DVO_2X_MODE;
8798
8799         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8800             intel_panel_use_ssc(dev_priv))
8801                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8802         else
8803                 dpll |= PLL_REF_INPUT_DREFCLK;
8804
8805         dpll |= DPLL_VCO_ENABLE;
8806         crtc_state->dpll_hw_state.dpll = dpll;
8807 }
8808
8809 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
8810 {
8811         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8812         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8813         enum pipe pipe = crtc->pipe;
8814         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8815         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
8816         u32 crtc_vtotal, crtc_vblank_end;
8817         int vsyncshift = 0;
8818
8819         /* We need to be careful not to changed the adjusted mode, for otherwise
8820          * the hw state checker will get angry at the mismatch. */
8821         crtc_vtotal = adjusted_mode->crtc_vtotal;
8822         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8823
8824         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8825                 /* the chip adds 2 halflines automatically */
8826                 crtc_vtotal -= 1;
8827                 crtc_vblank_end -= 1;
8828
8829                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
8830                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8831                 else
8832                         vsyncshift = adjusted_mode->crtc_hsync_start -
8833                                 adjusted_mode->crtc_htotal / 2;
8834                 if (vsyncshift < 0)
8835                         vsyncshift += adjusted_mode->crtc_htotal;
8836         }
8837
8838         if (INTEL_GEN(dev_priv) > 3)
8839                 intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder),
8840                                vsyncshift);
8841
8842         intel_de_write(dev_priv, HTOTAL(cpu_transcoder),
8843                        (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16));
8844         intel_de_write(dev_priv, HBLANK(cpu_transcoder),
8845                        (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
8846         intel_de_write(dev_priv, HSYNC(cpu_transcoder),
8847                        (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
8848
8849         intel_de_write(dev_priv, VTOTAL(cpu_transcoder),
8850                        (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16));
8851         intel_de_write(dev_priv, VBLANK(cpu_transcoder),
8852                        (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16));
8853         intel_de_write(dev_priv, VSYNC(cpu_transcoder),
8854                        (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
8855
8856         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8857          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8858          * documented on the DDI_FUNC_CTL register description, EDP Input Select
8859          * bits. */
8860         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
8861             (pipe == PIPE_B || pipe == PIPE_C))
8862                 intel_de_write(dev_priv, VTOTAL(pipe),
8863                                intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
8864
8865 }
8866
8867 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
8868 {
8869         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8870         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8871         enum pipe pipe = crtc->pipe;
8872
8873         /* pipesrc controls the size that is scaled from, which should
8874          * always be the user's requested size.
8875          */
8876         intel_de_write(dev_priv, PIPESRC(pipe),
8877                        ((crtc_state->pipe_src_w - 1) << 16) | (crtc_state->pipe_src_h - 1));
8878 }
8879
8880 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
8881 {
8882         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
8883         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8884
8885         if (IS_GEN(dev_priv, 2))
8886                 return false;
8887
8888         if (INTEL_GEN(dev_priv) >= 9 ||
8889             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
8890                 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW;
8891         else
8892                 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
8893 }
8894
8895 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8896                                    struct intel_crtc_state *pipe_config)
8897 {
8898         struct drm_device *dev = crtc->base.dev;
8899         struct drm_i915_private *dev_priv = to_i915(dev);
8900         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8901         u32 tmp;
8902
8903         tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder));
8904         pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8905         pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8906
8907         if (!transcoder_is_dsi(cpu_transcoder)) {
8908                 tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder));
8909                 pipe_config->hw.adjusted_mode.crtc_hblank_start =
8910                                                         (tmp & 0xffff) + 1;
8911                 pipe_config->hw.adjusted_mode.crtc_hblank_end =
8912                                                 ((tmp >> 16) & 0xffff) + 1;
8913         }
8914         tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder));
8915         pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8916         pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8917
8918         tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder));
8919         pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8920         pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8921
8922         if (!transcoder_is_dsi(cpu_transcoder)) {
8923                 tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder));
8924                 pipe_config->hw.adjusted_mode.crtc_vblank_start =
8925                                                         (tmp & 0xffff) + 1;
8926                 pipe_config->hw.adjusted_mode.crtc_vblank_end =
8927                                                 ((tmp >> 16) & 0xffff) + 1;
8928         }
8929         tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder));
8930         pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8931         pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8932
8933         if (intel_pipe_is_interlaced(pipe_config)) {
8934                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8935                 pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
8936                 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
8937         }
8938 }
8939
8940 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8941                                     struct intel_crtc_state *pipe_config)
8942 {
8943         struct drm_device *dev = crtc->base.dev;
8944         struct drm_i915_private *dev_priv = to_i915(dev);
8945         u32 tmp;
8946
8947         tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
8948         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8949         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8950
8951         pipe_config->hw.mode.vdisplay = pipe_config->pipe_src_h;
8952         pipe_config->hw.mode.hdisplay = pipe_config->pipe_src_w;
8953 }
8954
8955 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8956                                  struct intel_crtc_state *pipe_config)
8957 {
8958         mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay;
8959         mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal;
8960         mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start;
8961         mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end;
8962
8963         mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay;
8964         mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal;
8965         mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start;
8966         mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end;
8967
8968         mode->flags = pipe_config->hw.adjusted_mode.flags;
8969         mode->type = DRM_MODE_TYPE_DRIVER;
8970
8971         mode->clock = pipe_config->hw.adjusted_mode.crtc_clock;
8972
8973         drm_mode_set_name(mode);
8974 }
8975
8976 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
8977 {
8978         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8979         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8980         u32 pipeconf;
8981
8982         pipeconf = 0;
8983
8984         /* we keep both pipes enabled on 830 */
8985         if (IS_I830(dev_priv))
8986                 pipeconf |= intel_de_read(dev_priv, PIPECONF(crtc->pipe)) & PIPECONF_ENABLE;
8987
8988         if (crtc_state->double_wide)
8989                 pipeconf |= PIPECONF_DOUBLE_WIDE;
8990
8991         /* only g4x and later have fancy bpc/dither controls */
8992         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8993             IS_CHERRYVIEW(dev_priv)) {
8994                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8995                 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
8996                         pipeconf |= PIPECONF_DITHER_EN |
8997                                     PIPECONF_DITHER_TYPE_SP;
8998
8999                 switch (crtc_state->pipe_bpp) {
9000                 case 18:
9001                         pipeconf |= PIPECONF_6BPC;
9002                         break;
9003                 case 24:
9004                         pipeconf |= PIPECONF_8BPC;
9005                         break;
9006                 case 30:
9007                         pipeconf |= PIPECONF_10BPC;
9008                         break;
9009                 default:
9010                         /* Case prevented by intel_choose_pipe_bpp_dither. */
9011                         BUG();
9012                 }
9013         }
9014
9015         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
9016                 if (INTEL_GEN(dev_priv) < 4 ||
9017                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
9018                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
9019                 else
9020                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
9021         } else {
9022                 pipeconf |= PIPECONF_PROGRESSIVE;
9023         }
9024
9025         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
9026              crtc_state->limited_color_range)
9027                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9028
9029         pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
9030
9031         pipeconf |= PIPECONF_FRAME_START_DELAY(0);
9032
9033         intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf);
9034         intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe));
9035 }
9036
9037 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
9038                                    struct intel_crtc_state *crtc_state)
9039 {
9040         struct drm_device *dev = crtc->base.dev;
9041         struct drm_i915_private *dev_priv = to_i915(dev);
9042         const struct intel_limit *limit;
9043         int refclk = 48000;
9044
9045         memset(&crtc_state->dpll_hw_state, 0,
9046                sizeof(crtc_state->dpll_hw_state));
9047
9048         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9049                 if (intel_panel_use_ssc(dev_priv)) {
9050                         refclk = dev_priv->vbt.lvds_ssc_freq;
9051                         drm_dbg_kms(&dev_priv->drm,
9052                                     "using SSC reference clock of %d kHz\n",
9053                                     refclk);
9054                 }
9055
9056                 limit = &intel_limits_i8xx_lvds;
9057         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
9058                 limit = &intel_limits_i8xx_dvo;
9059         } else {
9060                 limit = &intel_limits_i8xx_dac;
9061         }
9062
9063         if (!crtc_state->clock_set &&
9064             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9065                                  refclk, NULL, &crtc_state->dpll)) {
9066                 drm_err(&dev_priv->drm,
9067                         "Couldn't find PLL settings for mode!\n");
9068                 return -EINVAL;
9069         }
9070
9071         i8xx_compute_dpll(crtc, crtc_state, NULL);
9072
9073         return 0;
9074 }
9075
9076 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
9077                                   struct intel_crtc_state *crtc_state)
9078 {
9079         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9080         const struct intel_limit *limit;
9081         int refclk = 96000;
9082
9083         memset(&crtc_state->dpll_hw_state, 0,
9084                sizeof(crtc_state->dpll_hw_state));
9085
9086         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9087                 if (intel_panel_use_ssc(dev_priv)) {
9088                         refclk = dev_priv->vbt.lvds_ssc_freq;
9089                         drm_dbg_kms(&dev_priv->drm,
9090                                     "using SSC reference clock of %d kHz\n",
9091                                     refclk);
9092                 }
9093
9094                 if (intel_is_dual_link_lvds(dev_priv))
9095                         limit = &intel_limits_g4x_dual_channel_lvds;
9096                 else
9097                         limit = &intel_limits_g4x_single_channel_lvds;
9098         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
9099                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
9100                 limit = &intel_limits_g4x_hdmi;
9101         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
9102                 limit = &intel_limits_g4x_sdvo;
9103         } else {
9104                 /* The option is for other outputs */
9105                 limit = &intel_limits_i9xx_sdvo;
9106         }
9107
9108         if (!crtc_state->clock_set &&
9109             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9110                                 refclk, NULL, &crtc_state->dpll)) {
9111                 drm_err(&dev_priv->drm,
9112                         "Couldn't find PLL settings for mode!\n");
9113                 return -EINVAL;
9114         }
9115
9116         i9xx_compute_dpll(crtc, crtc_state, NULL);
9117
9118         return 0;
9119 }
9120
9121 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
9122                                   struct intel_crtc_state *crtc_state)
9123 {
9124         struct drm_device *dev = crtc->base.dev;
9125         struct drm_i915_private *dev_priv = to_i915(dev);
9126         const struct intel_limit *limit;
9127         int refclk = 96000;
9128
9129         memset(&crtc_state->dpll_hw_state, 0,
9130                sizeof(crtc_state->dpll_hw_state));
9131
9132         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9133                 if (intel_panel_use_ssc(dev_priv)) {
9134                         refclk = dev_priv->vbt.lvds_ssc_freq;
9135                         drm_dbg_kms(&dev_priv->drm,
9136                                     "using SSC reference clock of %d kHz\n",
9137                                     refclk);
9138                 }
9139
9140                 limit = &pnv_limits_lvds;
9141         } else {
9142                 limit = &pnv_limits_sdvo;
9143         }
9144
9145         if (!crtc_state->clock_set &&
9146             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9147                                 refclk, NULL, &crtc_state->dpll)) {
9148                 drm_err(&dev_priv->drm,
9149                         "Couldn't find PLL settings for mode!\n");
9150                 return -EINVAL;
9151         }
9152
9153         i9xx_compute_dpll(crtc, crtc_state, NULL);
9154
9155         return 0;
9156 }
9157
9158 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
9159                                    struct intel_crtc_state *crtc_state)
9160 {
9161         struct drm_device *dev = crtc->base.dev;
9162         struct drm_i915_private *dev_priv = to_i915(dev);
9163         const struct intel_limit *limit;
9164         int refclk = 96000;
9165
9166         memset(&crtc_state->dpll_hw_state, 0,
9167                sizeof(crtc_state->dpll_hw_state));
9168
9169         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9170                 if (intel_panel_use_ssc(dev_priv)) {
9171                         refclk = dev_priv->vbt.lvds_ssc_freq;
9172                         drm_dbg_kms(&dev_priv->drm,
9173                                     "using SSC reference clock of %d kHz\n",
9174                                     refclk);
9175                 }
9176
9177                 limit = &intel_limits_i9xx_lvds;
9178         } else {
9179                 limit = &intel_limits_i9xx_sdvo;
9180         }
9181
9182         if (!crtc_state->clock_set &&
9183             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9184                                  refclk, NULL, &crtc_state->dpll)) {
9185                 drm_err(&dev_priv->drm,
9186                         "Couldn't find PLL settings for mode!\n");
9187                 return -EINVAL;
9188         }
9189
9190         i9xx_compute_dpll(crtc, crtc_state, NULL);
9191
9192         return 0;
9193 }
9194
9195 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
9196                                   struct intel_crtc_state *crtc_state)
9197 {
9198         int refclk = 100000;
9199         const struct intel_limit *limit = &intel_limits_chv;
9200         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
9201
9202         memset(&crtc_state->dpll_hw_state, 0,
9203                sizeof(crtc_state->dpll_hw_state));
9204
9205         if (!crtc_state->clock_set &&
9206             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9207                                 refclk, NULL, &crtc_state->dpll)) {
9208                 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n");
9209                 return -EINVAL;
9210         }
9211
9212         chv_compute_dpll(crtc, crtc_state);
9213
9214         return 0;
9215 }
9216
9217 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
9218                                   struct intel_crtc_state *crtc_state)
9219 {
9220         int refclk = 100000;
9221         const struct intel_limit *limit = &intel_limits_vlv;
9222         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
9223
9224         memset(&crtc_state->dpll_hw_state, 0,
9225                sizeof(crtc_state->dpll_hw_state));
9226
9227         if (!crtc_state->clock_set &&
9228             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9229                                 refclk, NULL, &crtc_state->dpll)) {
9230                 drm_err(&i915->drm,  "Couldn't find PLL settings for mode!\n");
9231                 return -EINVAL;
9232         }
9233
9234         vlv_compute_dpll(crtc, crtc_state);
9235
9236         return 0;
9237 }
9238
9239 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
9240 {
9241         if (IS_I830(dev_priv))
9242                 return false;
9243
9244         return INTEL_GEN(dev_priv) >= 4 ||
9245                 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
9246 }
9247
9248 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
9249 {
9250         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9251         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9252         u32 tmp;
9253
9254         if (!i9xx_has_pfit(dev_priv))
9255                 return;
9256
9257         tmp = intel_de_read(dev_priv, PFIT_CONTROL);
9258         if (!(tmp & PFIT_ENABLE))
9259                 return;
9260
9261         /* Check whether the pfit is attached to our pipe. */
9262         if (INTEL_GEN(dev_priv) < 4) {
9263                 if (crtc->pipe != PIPE_B)
9264                         return;
9265         } else {
9266                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
9267                         return;
9268         }
9269
9270         crtc_state->gmch_pfit.control = tmp;
9271         crtc_state->gmch_pfit.pgm_ratios =
9272                 intel_de_read(dev_priv, PFIT_PGM_RATIOS);
9273 }
9274
9275 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
9276                                struct intel_crtc_state *pipe_config)
9277 {
9278         struct drm_device *dev = crtc->base.dev;
9279         struct drm_i915_private *dev_priv = to_i915(dev);
9280         enum pipe pipe = crtc->pipe;
9281         struct dpll clock;
9282         u32 mdiv;
9283         int refclk = 100000;
9284
9285         /* In case of DSI, DPLL will not be used */
9286         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
9287                 return;
9288
9289         vlv_dpio_get(dev_priv);
9290         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
9291         vlv_dpio_put(dev_priv);
9292
9293         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
9294         clock.m2 = mdiv & DPIO_M2DIV_MASK;
9295         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
9296         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
9297         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
9298
9299         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
9300 }
9301
9302 static void
9303 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
9304                               struct intel_initial_plane_config *plane_config)
9305 {
9306         struct drm_device *dev = crtc->base.dev;
9307         struct drm_i915_private *dev_priv = to_i915(dev);
9308         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
9309         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
9310         enum pipe pipe;
9311         u32 val, base, offset;
9312         int fourcc, pixel_format;
9313         unsigned int aligned_height;
9314         struct drm_framebuffer *fb;
9315         struct intel_framebuffer *intel_fb;
9316
9317         if (!plane->get_hw_state(plane, &pipe))
9318                 return;
9319
9320         drm_WARN_ON(dev, pipe != crtc->pipe);
9321
9322         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9323         if (!intel_fb) {
9324                 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
9325                 return;
9326         }
9327
9328         fb = &intel_fb->base;
9329
9330         fb->dev = dev;
9331
9332         val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
9333
9334         if (INTEL_GEN(dev_priv) >= 4) {
9335                 if (val & DISPPLANE_TILED) {
9336                         plane_config->tiling = I915_TILING_X;
9337                         fb->modifier = I915_FORMAT_MOD_X_TILED;
9338                 }
9339
9340                 if (val & DISPPLANE_ROTATE_180)
9341                         plane_config->rotation = DRM_MODE_ROTATE_180;
9342         }
9343
9344         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
9345             val & DISPPLANE_MIRROR)
9346                 plane_config->rotation |= DRM_MODE_REFLECT_X;
9347
9348         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9349         fourcc = i9xx_format_to_fourcc(pixel_format);
9350         fb->format = drm_format_info(fourcc);
9351
9352         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
9353                 offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));
9354                 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
9355         } else if (INTEL_GEN(dev_priv) >= 4) {
9356                 if (plane_config->tiling)
9357                         offset = intel_de_read(dev_priv,
9358                                                DSPTILEOFF(i9xx_plane));
9359                 else
9360                         offset = intel_de_read(dev_priv,
9361                                                DSPLINOFF(i9xx_plane));
9362                 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
9363         } else {
9364                 base = intel_de_read(dev_priv, DSPADDR(i9xx_plane));
9365         }
9366         plane_config->base = base;
9367
9368         val = intel_de_read(dev_priv, PIPESRC(pipe));
9369         fb->width = ((val >> 16) & 0xfff) + 1;
9370         fb->height = ((val >> 0) & 0xfff) + 1;
9371
9372         val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane));
9373         fb->pitches[0] = val & 0xffffffc0;
9374
9375         aligned_height = intel_fb_align_height(fb, 0, fb->height);
9376
9377         plane_config->size = fb->pitches[0] * aligned_height;
9378
9379         drm_dbg_kms(&dev_priv->drm,
9380                     "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9381                     crtc->base.name, plane->base.name, fb->width, fb->height,
9382                     fb->format->cpp[0] * 8, base, fb->pitches[0],
9383                     plane_config->size);
9384
9385         plane_config->fb = intel_fb;
9386 }
9387
9388 static void chv_crtc_clock_get(struct intel_crtc *crtc,
9389                                struct intel_crtc_state *pipe_config)
9390 {
9391         struct drm_device *dev = crtc->base.dev;
9392         struct drm_i915_private *dev_priv = to_i915(dev);
9393         enum pipe pipe = crtc->pipe;
9394         enum dpio_channel port = vlv_pipe_to_channel(pipe);
9395         struct dpll clock;
9396         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
9397         int refclk = 100000;
9398
9399         /* In case of DSI, DPLL will not be used */
9400         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
9401                 return;
9402
9403         vlv_dpio_get(dev_priv);
9404         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
9405         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
9406         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
9407         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
9408         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
9409         vlv_dpio_put(dev_priv);
9410
9411         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
9412         clock.m2 = (pll_dw0 & 0xff) << 22;
9413         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
9414                 clock.m2 |= pll_dw2 & 0x3fffff;
9415         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
9416         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
9417         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
9418
9419         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
9420 }
9421
9422 static enum intel_output_format
9423 bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
9424 {
9425         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9426         u32 tmp;
9427
9428         tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
9429
9430         if (tmp & PIPEMISC_YUV420_ENABLE) {
9431                 /* We support 4:2:0 in full blend mode only */
9432                 drm_WARN_ON(&dev_priv->drm,
9433                             (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0);
9434
9435                 return INTEL_OUTPUT_FORMAT_YCBCR420;
9436         } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
9437                 return INTEL_OUTPUT_FORMAT_YCBCR444;
9438         } else {
9439                 return INTEL_OUTPUT_FORMAT_RGB;
9440         }
9441 }
9442
9443 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
9444 {
9445         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9446         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
9447         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9448         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
9449         u32 tmp;
9450
9451         tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
9452
9453         if (tmp & DISPPLANE_GAMMA_ENABLE)
9454                 crtc_state->gamma_enable = true;
9455
9456         if (!HAS_GMCH(dev_priv) &&
9457             tmp & DISPPLANE_PIPE_CSC_ENABLE)
9458                 crtc_state->csc_enable = true;
9459 }
9460
9461 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
9462                                  struct intel_crtc_state *pipe_config)
9463 {
9464         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9465         enum intel_display_power_domain power_domain;
9466         intel_wakeref_t wakeref;
9467         u32 tmp;
9468         bool ret;
9469
9470         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9471         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
9472         if (!wakeref)
9473                 return false;
9474
9475         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
9476         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9477         pipe_config->shared_dpll = NULL;
9478
9479         ret = false;
9480
9481         tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
9482         if (!(tmp & PIPECONF_ENABLE))
9483                 goto out;
9484
9485         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
9486             IS_CHERRYVIEW(dev_priv)) {
9487                 switch (tmp & PIPECONF_BPC_MASK) {
9488                 case PIPECONF_6BPC:
9489                         pipe_config->pipe_bpp = 18;
9490                         break;
9491                 case PIPECONF_8BPC:
9492                         pipe_config->pipe_bpp = 24;
9493                         break;
9494                 case PIPECONF_10BPC:
9495                         pipe_config->pipe_bpp = 30;
9496                         break;
9497                 default:
9498                         break;
9499                 }
9500         }
9501
9502         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
9503             (tmp & PIPECONF_COLOR_RANGE_SELECT))
9504                 pipe_config->limited_color_range = true;
9505
9506         pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
9507                 PIPECONF_GAMMA_MODE_SHIFT;
9508
9509         if (IS_CHERRYVIEW(dev_priv))
9510                 pipe_config->cgm_mode = intel_de_read(dev_priv,
9511                                                       CGM_PIPE_MODE(crtc->pipe));
9512
9513         i9xx_get_pipe_color_config(pipe_config);
9514         intel_color_get_config(pipe_config);
9515
9516         if (INTEL_GEN(dev_priv) < 4)
9517                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
9518
9519         intel_get_pipe_timings(crtc, pipe_config);
9520         intel_get_pipe_src_size(crtc, pipe_config);
9521
9522         i9xx_get_pfit_config(pipe_config);
9523
9524         if (INTEL_GEN(dev_priv) >= 4) {
9525                 /* No way to read it out on pipes B and C */
9526                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
9527                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
9528                 else
9529                         tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
9530                 pipe_config->pixel_multiplier =
9531                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
9532                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
9533                 pipe_config->dpll_hw_state.dpll_md = tmp;
9534         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
9535                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
9536                 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe));
9537                 pipe_config->pixel_multiplier =
9538                         ((tmp & SDVO_MULTIPLIER_MASK)
9539                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
9540         } else {
9541                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
9542                  * port and will be fixed up in the encoder->get_config
9543                  * function. */
9544                 pipe_config->pixel_multiplier = 1;
9545         }
9546         pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv,
9547                                                         DPLL(crtc->pipe));
9548         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
9549                 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv,
9550                                                                FP0(crtc->pipe));
9551                 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv,
9552                                                                FP1(crtc->pipe));
9553         } else {
9554                 /* Mask out read-only status bits. */
9555                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
9556                                                      DPLL_PORTC_READY_MASK |
9557                                                      DPLL_PORTB_READY_MASK);
9558         }
9559
9560         if (IS_CHERRYVIEW(dev_priv))
9561                 chv_crtc_clock_get(crtc, pipe_config);
9562         else if (IS_VALLEYVIEW(dev_priv))
9563                 vlv_crtc_clock_get(crtc, pipe_config);
9564         else
9565                 i9xx_crtc_clock_get(crtc, pipe_config);
9566
9567         /*
9568          * Normally the dotclock is filled in by the encoder .get_config()
9569          * but in case the pipe is enabled w/o any ports we need a sane
9570          * default.
9571          */
9572         pipe_config->hw.adjusted_mode.crtc_clock =
9573                 pipe_config->port_clock / pipe_config->pixel_multiplier;
9574
9575         ret = true;
9576
9577 out:
9578         intel_display_power_put(dev_priv, power_domain, wakeref);
9579
9580         return ret;
9581 }
9582
9583 static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
9584 {
9585         struct intel_encoder *encoder;
9586         int i;
9587         u32 val, final;
9588         bool has_lvds = false;
9589         bool has_cpu_edp = false;
9590         bool has_panel = false;
9591         bool has_ck505 = false;
9592         bool can_ssc = false;
9593         bool using_ssc_source = false;
9594
9595         /* We need to take the global config into account */
9596         for_each_intel_encoder(&dev_priv->drm, encoder) {
9597                 switch (encoder->type) {
9598                 case INTEL_OUTPUT_LVDS:
9599                         has_panel = true;
9600                         has_lvds = true;
9601                         break;
9602                 case INTEL_OUTPUT_EDP:
9603                         has_panel = true;
9604                         if (encoder->port == PORT_A)
9605                                 has_cpu_edp = true;
9606                         break;
9607                 default:
9608                         break;
9609                 }
9610         }
9611
9612         if (HAS_PCH_IBX(dev_priv)) {
9613                 has_ck505 = dev_priv->vbt.display_clock_mode;
9614                 can_ssc = has_ck505;
9615         } else {
9616                 has_ck505 = false;
9617                 can_ssc = true;
9618         }
9619
9620         /* Check if any DPLLs are using the SSC source */
9621         for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
9622                 u32 temp = intel_de_read(dev_priv, PCH_DPLL(i));
9623
9624                 if (!(temp & DPLL_VCO_ENABLE))
9625                         continue;
9626
9627                 if ((temp & PLL_REF_INPUT_MASK) ==
9628                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
9629                         using_ssc_source = true;
9630                         break;
9631                 }
9632         }
9633
9634         drm_dbg_kms(&dev_priv->drm,
9635                     "has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
9636                     has_panel, has_lvds, has_ck505, using_ssc_source);
9637
9638         /* Ironlake: try to setup display ref clock before DPLL
9639          * enabling. This is only under driver's control after
9640          * PCH B stepping, previous chipset stepping should be
9641          * ignoring this setting.
9642          */
9643         val = intel_de_read(dev_priv, PCH_DREF_CONTROL);
9644
9645         /* As we must carefully and slowly disable/enable each source in turn,
9646          * compute the final state we want first and check if we need to
9647          * make any changes at all.
9648          */
9649         final = val;
9650         final &= ~DREF_NONSPREAD_SOURCE_MASK;
9651         if (has_ck505)
9652                 final |= DREF_NONSPREAD_CK505_ENABLE;
9653         else
9654                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
9655
9656         final &= ~DREF_SSC_SOURCE_MASK;
9657         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9658         final &= ~DREF_SSC1_ENABLE;
9659
9660         if (has_panel) {
9661                 final |= DREF_SSC_SOURCE_ENABLE;
9662
9663                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9664                         final |= DREF_SSC1_ENABLE;
9665
9666                 if (has_cpu_edp) {
9667                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
9668                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9669                         else
9670                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9671                 } else
9672                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9673         } else if (using_ssc_source) {
9674                 final |= DREF_SSC_SOURCE_ENABLE;
9675                 final |= DREF_SSC1_ENABLE;
9676         }
9677
9678         if (final == val)
9679                 return;
9680
9681         /* Always enable nonspread source */
9682         val &= ~DREF_NONSPREAD_SOURCE_MASK;
9683
9684         if (has_ck505)
9685                 val |= DREF_NONSPREAD_CK505_ENABLE;
9686         else
9687                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9688
9689         if (has_panel) {
9690                 val &= ~DREF_SSC_SOURCE_MASK;
9691                 val |= DREF_SSC_SOURCE_ENABLE;
9692
9693                 /* SSC must be turned on before enabling the CPU output  */
9694                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9695                         drm_dbg_kms(&dev_priv->drm, "Using SSC on panel\n");
9696                         val |= DREF_SSC1_ENABLE;
9697                 } else
9698                         val &= ~DREF_SSC1_ENABLE;
9699
9700                 /* Get SSC going before enabling the outputs */
9701                 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9702                 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9703                 udelay(200);
9704
9705                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9706
9707                 /* Enable CPU source on CPU attached eDP */
9708                 if (has_cpu_edp) {
9709                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9710                                 drm_dbg_kms(&dev_priv->drm,
9711                                             "Using SSC on eDP\n");
9712                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9713                         } else
9714                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9715                 } else
9716                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9717
9718                 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9719                 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9720                 udelay(200);
9721         } else {
9722                 drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n");
9723
9724                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9725
9726                 /* Turn off CPU output */
9727                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9728
9729                 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9730                 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9731                 udelay(200);
9732
9733                 if (!using_ssc_source) {
9734                         drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n");
9735
9736                         /* Turn off the SSC source */
9737                         val &= ~DREF_SSC_SOURCE_MASK;
9738                         val |= DREF_SSC_SOURCE_DISABLE;
9739
9740                         /* Turn off SSC1 */
9741                         val &= ~DREF_SSC1_ENABLE;
9742
9743                         intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9744                         intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9745                         udelay(200);
9746                 }
9747         }
9748
9749         BUG_ON(val != final);
9750 }
9751
9752 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9753 {
9754         u32 tmp;
9755
9756         tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
9757         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9758         intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
9759
9760         if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) &
9761                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9762                 drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n");
9763
9764         tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
9765         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9766         intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
9767
9768         if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) &
9769                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9770                 drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n");
9771 }
9772
9773 /* WaMPhyProgramming:hsw */
9774 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9775 {
9776         u32 tmp;
9777
9778         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9779         tmp &= ~(0xFF << 24);
9780         tmp |= (0x12 << 24);
9781         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9782
9783         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9784         tmp |= (1 << 11);
9785         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9786
9787         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9788         tmp |= (1 << 11);
9789         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9790
9791         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9792         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9793         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9794
9795         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9796         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9797         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9798
9799         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9800         tmp &= ~(7 << 13);
9801         tmp |= (5 << 13);
9802         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9803
9804         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9805         tmp &= ~(7 << 13);
9806         tmp |= (5 << 13);
9807         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9808
9809         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9810         tmp &= ~0xFF;
9811         tmp |= 0x1C;
9812         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9813
9814         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9815         tmp &= ~0xFF;
9816         tmp |= 0x1C;
9817         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9818
9819         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9820         tmp &= ~(0xFF << 16);
9821         tmp |= (0x1C << 16);
9822         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9823
9824         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9825         tmp &= ~(0xFF << 16);
9826         tmp |= (0x1C << 16);
9827         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9828
9829         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9830         tmp |= (1 << 27);
9831         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9832
9833         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9834         tmp |= (1 << 27);
9835         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9836
9837         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9838         tmp &= ~(0xF << 28);
9839         tmp |= (4 << 28);
9840         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9841
9842         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9843         tmp &= ~(0xF << 28);
9844         tmp |= (4 << 28);
9845         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9846 }
9847
9848 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9849  * Programming" based on the parameters passed:
9850  * - Sequence to enable CLKOUT_DP
9851  * - Sequence to enable CLKOUT_DP without spread
9852  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9853  */
9854 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
9855                                  bool with_spread, bool with_fdi)
9856 {
9857         u32 reg, tmp;
9858
9859         if (drm_WARN(&dev_priv->drm, with_fdi && !with_spread,
9860                      "FDI requires downspread\n"))
9861                 with_spread = true;
9862         if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) &&
9863                      with_fdi, "LP PCH doesn't have FDI\n"))
9864                 with_fdi = false;
9865
9866         mutex_lock(&dev_priv->sb_lock);
9867
9868         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9869         tmp &= ~SBI_SSCCTL_DISABLE;
9870         tmp |= SBI_SSCCTL_PATHALT;
9871         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9872
9873         udelay(24);
9874
9875         if (with_spread) {
9876                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9877                 tmp &= ~SBI_SSCCTL_PATHALT;
9878                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9879
9880                 if (with_fdi) {
9881                         lpt_reset_fdi_mphy(dev_priv);
9882                         lpt_program_fdi_mphy(dev_priv);
9883                 }
9884         }
9885
9886         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9887         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9888         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9889         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9890
9891         mutex_unlock(&dev_priv->sb_lock);
9892 }
9893
9894 /* Sequence to disable CLKOUT_DP */
9895 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
9896 {
9897         u32 reg, tmp;
9898
9899         mutex_lock(&dev_priv->sb_lock);
9900
9901         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9902         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9903         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9904         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9905
9906         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9907         if (!(tmp & SBI_SSCCTL_DISABLE)) {
9908                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9909                         tmp |= SBI_SSCCTL_PATHALT;
9910                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9911                         udelay(32);
9912                 }
9913                 tmp |= SBI_SSCCTL_DISABLE;
9914                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9915         }
9916
9917         mutex_unlock(&dev_priv->sb_lock);
9918 }
9919
9920 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9921
9922 static const u16 sscdivintphase[] = {
9923         [BEND_IDX( 50)] = 0x3B23,
9924         [BEND_IDX( 45)] = 0x3B23,
9925         [BEND_IDX( 40)] = 0x3C23,
9926         [BEND_IDX( 35)] = 0x3C23,
9927         [BEND_IDX( 30)] = 0x3D23,
9928         [BEND_IDX( 25)] = 0x3D23,
9929         [BEND_IDX( 20)] = 0x3E23,
9930         [BEND_IDX( 15)] = 0x3E23,
9931         [BEND_IDX( 10)] = 0x3F23,
9932         [BEND_IDX(  5)] = 0x3F23,
9933         [BEND_IDX(  0)] = 0x0025,
9934         [BEND_IDX( -5)] = 0x0025,
9935         [BEND_IDX(-10)] = 0x0125,
9936         [BEND_IDX(-15)] = 0x0125,
9937         [BEND_IDX(-20)] = 0x0225,
9938         [BEND_IDX(-25)] = 0x0225,
9939         [BEND_IDX(-30)] = 0x0325,
9940         [BEND_IDX(-35)] = 0x0325,
9941         [BEND_IDX(-40)] = 0x0425,
9942         [BEND_IDX(-45)] = 0x0425,
9943         [BEND_IDX(-50)] = 0x0525,
9944 };
9945
9946 /*
9947  * Bend CLKOUT_DP
9948  * steps -50 to 50 inclusive, in steps of 5
9949  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9950  * change in clock period = -(steps / 10) * 5.787 ps
9951  */
9952 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9953 {
9954         u32 tmp;
9955         int idx = BEND_IDX(steps);
9956
9957         if (drm_WARN_ON(&dev_priv->drm, steps % 5 != 0))
9958                 return;
9959
9960         if (drm_WARN_ON(&dev_priv->drm, idx >= ARRAY_SIZE(sscdivintphase)))
9961                 return;
9962
9963         mutex_lock(&dev_priv->sb_lock);
9964
9965         if (steps % 10 != 0)
9966                 tmp = 0xAAAAAAAB;
9967         else
9968                 tmp = 0x00000000;
9969         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9970
9971         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9972         tmp &= 0xffff0000;
9973         tmp |= sscdivintphase[idx];
9974         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9975
9976         mutex_unlock(&dev_priv->sb_lock);
9977 }
9978
9979 #undef BEND_IDX
9980
9981 static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
9982 {
9983         u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
9984         u32 ctl = intel_de_read(dev_priv, SPLL_CTL);
9985
9986         if ((ctl & SPLL_PLL_ENABLE) == 0)
9987                 return false;
9988
9989         if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC &&
9990             (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
9991                 return true;
9992
9993         if (IS_BROADWELL(dev_priv) &&
9994             (ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW)
9995                 return true;
9996
9997         return false;
9998 }
9999
10000 static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
10001                                enum intel_dpll_id id)
10002 {
10003         u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
10004         u32 ctl = intel_de_read(dev_priv, WRPLL_CTL(id));
10005
10006         if ((ctl & WRPLL_PLL_ENABLE) == 0)
10007                 return false;
10008
10009         if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
10010                 return true;
10011
10012         if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
10013             (ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW &&
10014             (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
10015                 return true;
10016
10017         return false;
10018 }
10019
10020 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
10021 {
10022         struct intel_encoder *encoder;
10023         bool has_fdi = false;
10024
10025         for_each_intel_encoder(&dev_priv->drm, encoder) {
10026                 switch (encoder->type) {
10027                 case INTEL_OUTPUT_ANALOG:
10028                         has_fdi = true;
10029                         break;
10030                 default:
10031                         break;
10032                 }
10033         }
10034
10035         /*
10036          * The BIOS may have decided to use the PCH SSC
10037          * reference so we must not disable it until the
10038          * relevant PLLs have stopped relying on it. We'll
10039          * just leave the PCH SSC reference enabled in case
10040          * any active PLL is using it. It will get disabled
10041          * after runtime suspend if we don't have FDI.
10042          *
10043          * TODO: Move the whole reference clock handling
10044          * to the modeset sequence proper so that we can
10045          * actually enable/disable/reconfigure these things
10046          * safely. To do that we need to introduce a real
10047          * clock hierarchy. That would also allow us to do
10048          * clock bending finally.
10049          */
10050         dev_priv->pch_ssc_use = 0;
10051
10052         if (spll_uses_pch_ssc(dev_priv)) {
10053                 drm_dbg_kms(&dev_priv->drm, "SPLL using PCH SSC\n");
10054                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
10055         }
10056
10057         if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
10058                 drm_dbg_kms(&dev_priv->drm, "WRPLL1 using PCH SSC\n");
10059                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
10060         }
10061
10062         if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
10063                 drm_dbg_kms(&dev_priv->drm, "WRPLL2 using PCH SSC\n");
10064                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
10065         }
10066
10067         if (dev_priv->pch_ssc_use)
10068                 return;
10069
10070         if (has_fdi) {
10071                 lpt_bend_clkout_dp(dev_priv, 0);
10072                 lpt_enable_clkout_dp(dev_priv, true, true);
10073         } else {
10074                 lpt_disable_clkout_dp(dev_priv);
10075         }
10076 }
10077
10078 /*
10079  * Initialize reference clocks when the driver loads
10080  */
10081 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
10082 {
10083         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
10084                 ilk_init_pch_refclk(dev_priv);
10085         else if (HAS_PCH_LPT(dev_priv))
10086                 lpt_init_pch_refclk(dev_priv);
10087 }
10088
10089 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
10090 {
10091         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10092         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10093         enum pipe pipe = crtc->pipe;
10094         u32 val;
10095
10096         val = 0;
10097
10098         switch (crtc_state->pipe_bpp) {
10099         case 18:
10100                 val |= PIPECONF_6BPC;
10101                 break;
10102         case 24:
10103                 val |= PIPECONF_8BPC;
10104                 break;
10105         case 30:
10106                 val |= PIPECONF_10BPC;
10107                 break;
10108         case 36:
10109                 val |= PIPECONF_12BPC;
10110                 break;
10111         default:
10112                 /* Case prevented by intel_choose_pipe_bpp_dither. */
10113                 BUG();
10114         }
10115
10116         if (crtc_state->dither)
10117                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
10118
10119         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
10120                 val |= PIPECONF_INTERLACED_ILK;
10121         else
10122                 val |= PIPECONF_PROGRESSIVE;
10123
10124         /*
10125          * This would end up with an odd purple hue over
10126          * the entire display. Make sure we don't do it.
10127          */
10128         drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
10129                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
10130
10131         if (crtc_state->limited_color_range &&
10132             !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
10133                 val |= PIPECONF_COLOR_RANGE_SELECT;
10134
10135         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
10136                 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
10137
10138         val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
10139
10140         val |= PIPECONF_FRAME_START_DELAY(0);
10141
10142         intel_de_write(dev_priv, PIPECONF(pipe), val);
10143         intel_de_posting_read(dev_priv, PIPECONF(pipe));
10144 }
10145
10146 static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state)
10147 {
10148         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10149         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10150         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
10151         u32 val = 0;
10152
10153         if (IS_HASWELL(dev_priv) && crtc_state->dither)
10154                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
10155
10156         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
10157                 val |= PIPECONF_INTERLACED_ILK;
10158         else
10159                 val |= PIPECONF_PROGRESSIVE;
10160
10161         if (IS_HASWELL(dev_priv) &&
10162             crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
10163                 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
10164
10165         intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val);
10166         intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder));
10167 }
10168
10169 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
10170 {
10171         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10172         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10173         u32 val = 0;
10174
10175         switch (crtc_state->pipe_bpp) {
10176         case 18:
10177                 val |= PIPEMISC_DITHER_6_BPC;
10178                 break;
10179         case 24:
10180                 val |= PIPEMISC_DITHER_8_BPC;
10181                 break;
10182         case 30:
10183                 val |= PIPEMISC_DITHER_10_BPC;
10184                 break;
10185         case 36:
10186                 val |= PIPEMISC_DITHER_12_BPC;
10187                 break;
10188         default:
10189                 MISSING_CASE(crtc_state->pipe_bpp);
10190                 break;
10191         }
10192
10193         if (crtc_state->dither)
10194                 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
10195
10196         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
10197             crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
10198                 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
10199
10200         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
10201                 val |= PIPEMISC_YUV420_ENABLE |
10202                         PIPEMISC_YUV420_MODE_FULL_BLEND;
10203
10204         if (INTEL_GEN(dev_priv) >= 11 &&
10205             (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
10206                                            BIT(PLANE_CURSOR))) == 0)
10207                 val |= PIPEMISC_HDR_MODE_PRECISION;
10208
10209         if (INTEL_GEN(dev_priv) >= 12)
10210                 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC;
10211
10212         intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val);
10213 }
10214
10215 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
10216 {
10217         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10218         u32 tmp;
10219
10220         tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
10221
10222         switch (tmp & PIPEMISC_DITHER_BPC_MASK) {
10223         case PIPEMISC_DITHER_6_BPC:
10224                 return 18;
10225         case PIPEMISC_DITHER_8_BPC:
10226                 return 24;
10227         case PIPEMISC_DITHER_10_BPC:
10228                 return 30;
10229         case PIPEMISC_DITHER_12_BPC:
10230                 return 36;
10231         default:
10232                 MISSING_CASE(tmp);
10233                 return 0;
10234         }
10235 }
10236
10237 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
10238 {
10239         /*
10240          * Account for spread spectrum to avoid
10241          * oversubscribing the link. Max center spread
10242          * is 2.5%; use 5% for safety's sake.
10243          */
10244         u32 bps = target_clock * bpp * 21 / 20;
10245         return DIV_ROUND_UP(bps, link_bw * 8);
10246 }
10247
10248 static bool ilk_needs_fb_cb_tune(struct dpll *dpll, int factor)
10249 {
10250         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
10251 }
10252
10253 static void ilk_compute_dpll(struct intel_crtc *crtc,
10254                              struct intel_crtc_state *crtc_state,
10255                              struct dpll *reduced_clock)
10256 {
10257         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10258         u32 dpll, fp, fp2;
10259         int factor;
10260
10261         /* Enable autotuning of the PLL clock (if permissible) */
10262         factor = 21;
10263         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
10264                 if ((intel_panel_use_ssc(dev_priv) &&
10265                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
10266                     (HAS_PCH_IBX(dev_priv) &&
10267                      intel_is_dual_link_lvds(dev_priv)))
10268                         factor = 25;
10269         } else if (crtc_state->sdvo_tv_clock) {
10270                 factor = 20;
10271         }
10272
10273         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
10274
10275         if (ilk_needs_fb_cb_tune(&crtc_state->dpll, factor))
10276                 fp |= FP_CB_TUNE;
10277
10278         if (reduced_clock) {
10279                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
10280
10281                 if (reduced_clock->m < factor * reduced_clock->n)
10282                         fp2 |= FP_CB_TUNE;
10283         } else {
10284                 fp2 = fp;
10285         }
10286
10287         dpll = 0;
10288
10289         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
10290                 dpll |= DPLLB_MODE_LVDS;
10291         else
10292                 dpll |= DPLLB_MODE_DAC_SERIAL;
10293
10294         dpll |= (crtc_state->pixel_multiplier - 1)
10295                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
10296
10297         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
10298             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
10299                 dpll |= DPLL_SDVO_HIGH_SPEED;
10300
10301         if (intel_crtc_has_dp_encoder(crtc_state))
10302                 dpll |= DPLL_SDVO_HIGH_SPEED;
10303
10304         /*
10305          * The high speed IO clock is only really required for
10306          * SDVO/HDMI/DP, but we also enable it for CRT to make it
10307          * possible to share the DPLL between CRT and HDMI. Enabling
10308          * the clock needlessly does no real harm, except use up a
10309          * bit of power potentially.
10310          *
10311          * We'll limit this to IVB with 3 pipes, since it has only two
10312          * DPLLs and so DPLL sharing is the only way to get three pipes
10313          * driving PCH ports at the same time. On SNB we could do this,
10314          * and potentially avoid enabling the second DPLL, but it's not
10315          * clear if it''s a win or loss power wise. No point in doing
10316          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
10317          */
10318         if (INTEL_NUM_PIPES(dev_priv) == 3 &&
10319             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
10320                 dpll |= DPLL_SDVO_HIGH_SPEED;
10321
10322         /* compute bitmask from p1 value */
10323         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
10324         /* also FPA1 */
10325         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
10326
10327         switch (crtc_state->dpll.p2) {
10328         case 5:
10329                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
10330                 break;
10331         case 7:
10332                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
10333                 break;
10334         case 10:
10335                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
10336                 break;
10337         case 14:
10338                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
10339                 break;
10340         }
10341
10342         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
10343             intel_panel_use_ssc(dev_priv))
10344                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
10345         else
10346                 dpll |= PLL_REF_INPUT_DREFCLK;
10347
10348         dpll |= DPLL_VCO_ENABLE;
10349
10350         crtc_state->dpll_hw_state.dpll = dpll;
10351         crtc_state->dpll_hw_state.fp0 = fp;
10352         crtc_state->dpll_hw_state.fp1 = fp2;
10353 }
10354
10355 static int ilk_crtc_compute_clock(struct intel_crtc *crtc,
10356                                   struct intel_crtc_state *crtc_state)
10357 {
10358         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10359         struct intel_atomic_state *state =
10360                 to_intel_atomic_state(crtc_state->uapi.state);
10361         const struct intel_limit *limit;
10362         int refclk = 120000;
10363
10364         memset(&crtc_state->dpll_hw_state, 0,
10365                sizeof(crtc_state->dpll_hw_state));
10366
10367         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
10368         if (!crtc_state->has_pch_encoder)
10369                 return 0;
10370
10371         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
10372                 if (intel_panel_use_ssc(dev_priv)) {
10373                         drm_dbg_kms(&dev_priv->drm,
10374                                     "using SSC reference clock of %d kHz\n",
10375                                     dev_priv->vbt.lvds_ssc_freq);
10376                         refclk = dev_priv->vbt.lvds_ssc_freq;
10377                 }
10378
10379                 if (intel_is_dual_link_lvds(dev_priv)) {
10380                         if (refclk == 100000)
10381                                 limit = &ilk_limits_dual_lvds_100m;
10382                         else
10383                                 limit = &ilk_limits_dual_lvds;
10384                 } else {
10385                         if (refclk == 100000)
10386                                 limit = &ilk_limits_single_lvds_100m;
10387                         else
10388                                 limit = &ilk_limits_single_lvds;
10389                 }
10390         } else {
10391                 limit = &ilk_limits_dac;
10392         }
10393
10394         if (!crtc_state->clock_set &&
10395             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
10396                                 refclk, NULL, &crtc_state->dpll)) {
10397                 drm_err(&dev_priv->drm,
10398                         "Couldn't find PLL settings for mode!\n");
10399                 return -EINVAL;
10400         }
10401
10402         ilk_compute_dpll(crtc, crtc_state, NULL);
10403
10404         if (!intel_reserve_shared_dplls(state, crtc, NULL)) {
10405                 drm_dbg_kms(&dev_priv->drm,
10406                             "failed to find PLL for pipe %c\n",
10407                             pipe_name(crtc->pipe));
10408                 return -EINVAL;
10409         }
10410
10411         return 0;
10412 }
10413
10414 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
10415                                          struct intel_link_m_n *m_n)
10416 {
10417         struct drm_device *dev = crtc->base.dev;
10418         struct drm_i915_private *dev_priv = to_i915(dev);
10419         enum pipe pipe = crtc->pipe;
10420
10421         m_n->link_m = intel_de_read(dev_priv, PCH_TRANS_LINK_M1(pipe));
10422         m_n->link_n = intel_de_read(dev_priv, PCH_TRANS_LINK_N1(pipe));
10423         m_n->gmch_m = intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
10424                 & ~TU_SIZE_MASK;
10425         m_n->gmch_n = intel_de_read(dev_priv, PCH_TRANS_DATA_N1(pipe));
10426         m_n->tu = ((intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
10427                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10428 }
10429
10430 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
10431                                          enum transcoder transcoder,
10432                                          struct intel_link_m_n *m_n,
10433                                          struct intel_link_m_n *m2_n2)
10434 {
10435         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10436         enum pipe pipe = crtc->pipe;
10437
10438         if (INTEL_GEN(dev_priv) >= 5) {
10439                 m_n->link_m = intel_de_read(dev_priv,
10440                                             PIPE_LINK_M1(transcoder));
10441                 m_n->link_n = intel_de_read(dev_priv,
10442                                             PIPE_LINK_N1(transcoder));
10443                 m_n->gmch_m = intel_de_read(dev_priv,
10444                                             PIPE_DATA_M1(transcoder))
10445                         & ~TU_SIZE_MASK;
10446                 m_n->gmch_n = intel_de_read(dev_priv,
10447                                             PIPE_DATA_N1(transcoder));
10448                 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M1(transcoder))
10449                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10450
10451                 if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
10452                         m2_n2->link_m = intel_de_read(dev_priv,
10453                                                       PIPE_LINK_M2(transcoder));
10454                         m2_n2->link_n = intel_de_read(dev_priv,
10455                                                              PIPE_LINK_N2(transcoder));
10456                         m2_n2->gmch_m = intel_de_read(dev_priv,
10457                                                              PIPE_DATA_M2(transcoder))
10458                                         & ~TU_SIZE_MASK;
10459                         m2_n2->gmch_n = intel_de_read(dev_priv,
10460                                                              PIPE_DATA_N2(transcoder));
10461                         m2_n2->tu = ((intel_de_read(dev_priv, PIPE_DATA_M2(transcoder))
10462                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10463                 }
10464         } else {
10465                 m_n->link_m = intel_de_read(dev_priv, PIPE_LINK_M_G4X(pipe));
10466                 m_n->link_n = intel_de_read(dev_priv, PIPE_LINK_N_G4X(pipe));
10467                 m_n->gmch_m = intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
10468                         & ~TU_SIZE_MASK;
10469                 m_n->gmch_n = intel_de_read(dev_priv, PIPE_DATA_N_G4X(pipe));
10470                 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
10471                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10472         }
10473 }
10474
10475 void intel_dp_get_m_n(struct intel_crtc *crtc,
10476                       struct intel_crtc_state *pipe_config)
10477 {
10478         if (pipe_config->has_pch_encoder)
10479                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
10480         else
10481                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
10482                                              &pipe_config->dp_m_n,
10483                                              &pipe_config->dp_m2_n2);
10484 }
10485
10486 static void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
10487                                    struct intel_crtc_state *pipe_config)
10488 {
10489         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
10490                                      &pipe_config->fdi_m_n, NULL);
10491 }
10492
10493 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state,
10494                                   u32 pos, u32 size)
10495 {
10496         drm_rect_init(&crtc_state->pch_pfit.dst,
10497                       pos >> 16, pos & 0xffff,
10498                       size >> 16, size & 0xffff);
10499 }
10500
10501 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state)
10502 {
10503         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10504         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10505         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
10506         int id = -1;
10507         int i;
10508
10509         /* find scaler attached to this pipe */
10510         for (i = 0; i < crtc->num_scalers; i++) {
10511                 u32 ctl, pos, size;
10512
10513                 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
10514                 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)
10515                         continue;
10516
10517                 id = i;
10518                 crtc_state->pch_pfit.enabled = true;
10519
10520                 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i));
10521                 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
10522
10523                 ilk_get_pfit_pos_size(crtc_state, pos, size);
10524
10525                 scaler_state->scalers[i].in_use = true;
10526                 break;
10527         }
10528
10529         scaler_state->scaler_id = id;
10530         if (id >= 0)
10531                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
10532         else
10533                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
10534 }
10535
10536 static void
10537 skl_get_initial_plane_config(struct intel_crtc *crtc,
10538                              struct intel_initial_plane_config *plane_config)
10539 {
10540         struct drm_device *dev = crtc->base.dev;
10541         struct drm_i915_private *dev_priv = to_i915(dev);
10542         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
10543         enum plane_id plane_id = plane->id;
10544         enum pipe pipe;
10545         u32 val, base, offset, stride_mult, tiling, alpha;
10546         int fourcc, pixel_format;
10547         unsigned int aligned_height;
10548         struct drm_framebuffer *fb;
10549         struct intel_framebuffer *intel_fb;
10550
10551         if (!plane->get_hw_state(plane, &pipe))
10552                 return;
10553
10554         drm_WARN_ON(dev, pipe != crtc->pipe);
10555
10556         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10557         if (!intel_fb) {
10558                 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
10559                 return;
10560         }
10561
10562         fb = &intel_fb->base;
10563
10564         fb->dev = dev;
10565
10566         val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id));
10567
10568         if (INTEL_GEN(dev_priv) >= 11)
10569                 pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
10570         else
10571                 pixel_format = val & PLANE_CTL_FORMAT_MASK;
10572
10573         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
10574                 alpha = intel_de_read(dev_priv,
10575                                       PLANE_COLOR_CTL(pipe, plane_id));
10576                 alpha &= PLANE_COLOR_ALPHA_MASK;
10577         } else {
10578                 alpha = val & PLANE_CTL_ALPHA_MASK;
10579         }
10580
10581         fourcc = skl_format_to_fourcc(pixel_format,
10582                                       val & PLANE_CTL_ORDER_RGBX, alpha);
10583         fb->format = drm_format_info(fourcc);
10584
10585         tiling = val & PLANE_CTL_TILED_MASK;
10586         switch (tiling) {
10587         case PLANE_CTL_TILED_LINEAR:
10588                 fb->modifier = DRM_FORMAT_MOD_LINEAR;
10589                 break;
10590         case PLANE_CTL_TILED_X:
10591                 plane_config->tiling = I915_TILING_X;
10592                 fb->modifier = I915_FORMAT_MOD_X_TILED;
10593                 break;
10594         case PLANE_CTL_TILED_Y:
10595                 plane_config->tiling = I915_TILING_Y;
10596                 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
10597                         fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
10598                                 I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
10599                                 I915_FORMAT_MOD_Y_TILED_CCS;
10600                 else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
10601                         fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
10602                 else
10603                         fb->modifier = I915_FORMAT_MOD_Y_TILED;
10604                 break;
10605         case PLANE_CTL_TILED_YF:
10606                 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
10607                         fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
10608                 else
10609                         fb->modifier = I915_FORMAT_MOD_Yf_TILED;
10610                 break;
10611         default:
10612                 MISSING_CASE(tiling);
10613                 goto error;
10614         }
10615
10616         /*
10617          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
10618          * while i915 HW rotation is clockwise, thats why this swapping.
10619          */
10620         switch (val & PLANE_CTL_ROTATE_MASK) {
10621         case PLANE_CTL_ROTATE_0:
10622                 plane_config->rotation = DRM_MODE_ROTATE_0;
10623                 break;
10624         case PLANE_CTL_ROTATE_90:
10625                 plane_config->rotation = DRM_MODE_ROTATE_270;
10626                 break;
10627         case PLANE_CTL_ROTATE_180:
10628                 plane_config->rotation = DRM_MODE_ROTATE_180;
10629                 break;
10630         case PLANE_CTL_ROTATE_270:
10631                 plane_config->rotation = DRM_MODE_ROTATE_90;
10632                 break;
10633         }
10634
10635         if (INTEL_GEN(dev_priv) >= 10 &&
10636             val & PLANE_CTL_FLIP_HORIZONTAL)
10637                 plane_config->rotation |= DRM_MODE_REFLECT_X;
10638
10639         base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xfffff000;
10640         plane_config->base = base;
10641
10642         offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id));
10643
10644         val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id));
10645         fb->height = ((val >> 16) & 0xffff) + 1;
10646         fb->width = ((val >> 0) & 0xffff) + 1;
10647
10648         val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
10649         stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
10650         fb->pitches[0] = (val & 0x3ff) * stride_mult;
10651
10652         aligned_height = intel_fb_align_height(fb, 0, fb->height);
10653
10654         plane_config->size = fb->pitches[0] * aligned_height;
10655
10656         drm_dbg_kms(&dev_priv->drm,
10657                     "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
10658                     crtc->base.name, plane->base.name, fb->width, fb->height,
10659                     fb->format->cpp[0] * 8, base, fb->pitches[0],
10660                     plane_config->size);
10661
10662         plane_config->fb = intel_fb;
10663         return;
10664
10665 error:
10666         kfree(intel_fb);
10667 }
10668
10669 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
10670 {
10671         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10672         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10673         u32 ctl, pos, size;
10674
10675         ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
10676         if ((ctl & PF_ENABLE) == 0)
10677                 return;
10678
10679         crtc_state->pch_pfit.enabled = true;
10680
10681         pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
10682         size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
10683
10684         ilk_get_pfit_pos_size(crtc_state, pos, size);
10685
10686         /*
10687          * We currently do not free assignements of panel fitters on
10688          * ivb/hsw (since we don't use the higher upscaling modes which
10689          * differentiates them) so just WARN about this case for now.
10690          */
10691         drm_WARN_ON(&dev_priv->drm, IS_GEN(dev_priv, 7) &&
10692                     (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe));
10693 }
10694
10695 static bool ilk_get_pipe_config(struct intel_crtc *crtc,
10696                                 struct intel_crtc_state *pipe_config)
10697 {
10698         struct drm_device *dev = crtc->base.dev;
10699         struct drm_i915_private *dev_priv = to_i915(dev);
10700         enum intel_display_power_domain power_domain;
10701         intel_wakeref_t wakeref;
10702         u32 tmp;
10703         bool ret;
10704
10705         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10706         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
10707         if (!wakeref)
10708                 return false;
10709
10710         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10711         pipe_config->shared_dpll = NULL;
10712
10713         ret = false;
10714         tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
10715         if (!(tmp & PIPECONF_ENABLE))
10716                 goto out;
10717
10718         switch (tmp & PIPECONF_BPC_MASK) {
10719         case PIPECONF_6BPC:
10720                 pipe_config->pipe_bpp = 18;
10721                 break;
10722         case PIPECONF_8BPC:
10723                 pipe_config->pipe_bpp = 24;
10724                 break;
10725         case PIPECONF_10BPC:
10726                 pipe_config->pipe_bpp = 30;
10727                 break;
10728         case PIPECONF_12BPC:
10729                 pipe_config->pipe_bpp = 36;
10730                 break;
10731         default:
10732                 break;
10733         }
10734
10735         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
10736                 pipe_config->limited_color_range = true;
10737
10738         switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
10739         case PIPECONF_OUTPUT_COLORSPACE_YUV601:
10740         case PIPECONF_OUTPUT_COLORSPACE_YUV709:
10741                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
10742                 break;
10743         default:
10744                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
10745                 break;
10746         }
10747
10748         pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
10749                 PIPECONF_GAMMA_MODE_SHIFT;
10750
10751         pipe_config->csc_mode = intel_de_read(dev_priv,
10752                                               PIPE_CSC_MODE(crtc->pipe));
10753
10754         i9xx_get_pipe_color_config(pipe_config);
10755         intel_color_get_config(pipe_config);
10756
10757         if (intel_de_read(dev_priv, PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
10758                 struct intel_shared_dpll *pll;
10759                 enum intel_dpll_id pll_id;
10760
10761                 pipe_config->has_pch_encoder = true;
10762
10763                 tmp = intel_de_read(dev_priv, FDI_RX_CTL(crtc->pipe));
10764                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10765                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10766
10767                 ilk_get_fdi_m_n_config(crtc, pipe_config);
10768
10769                 if (HAS_PCH_IBX(dev_priv)) {
10770                         /*
10771                          * The pipe->pch transcoder and pch transcoder->pll
10772                          * mapping is fixed.
10773                          */
10774                         pll_id = (enum intel_dpll_id) crtc->pipe;
10775                 } else {
10776                         tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
10777                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
10778                                 pll_id = DPLL_ID_PCH_PLL_B;
10779                         else
10780                                 pll_id= DPLL_ID_PCH_PLL_A;
10781                 }
10782
10783                 pipe_config->shared_dpll =
10784                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
10785                 pll = pipe_config->shared_dpll;
10786
10787                 drm_WARN_ON(dev, !pll->info->funcs->get_hw_state(dev_priv, pll,
10788                                                  &pipe_config->dpll_hw_state));
10789
10790                 tmp = pipe_config->dpll_hw_state.dpll;
10791                 pipe_config->pixel_multiplier =
10792                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
10793                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
10794
10795                 ilk_pch_clock_get(crtc, pipe_config);
10796         } else {
10797                 pipe_config->pixel_multiplier = 1;
10798         }
10799
10800         intel_get_pipe_timings(crtc, pipe_config);
10801         intel_get_pipe_src_size(crtc, pipe_config);
10802
10803         ilk_get_pfit_config(pipe_config);
10804
10805         ret = true;
10806
10807 out:
10808         intel_display_power_put(dev_priv, power_domain, wakeref);
10809
10810         return ret;
10811 }
10812
10813 static int hsw_crtc_compute_clock(struct intel_crtc *crtc,
10814                                   struct intel_crtc_state *crtc_state)
10815 {
10816         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10817         struct intel_atomic_state *state =
10818                 to_intel_atomic_state(crtc_state->uapi.state);
10819
10820         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
10821             INTEL_GEN(dev_priv) >= 11) {
10822                 struct intel_encoder *encoder =
10823                         intel_get_crtc_new_encoder(state, crtc_state);
10824
10825                 if (!intel_reserve_shared_dplls(state, crtc, encoder)) {
10826                         drm_dbg_kms(&dev_priv->drm,
10827                                     "failed to find PLL for pipe %c\n",
10828                                     pipe_name(crtc->pipe));
10829                         return -EINVAL;
10830                 }
10831         }
10832
10833         return 0;
10834 }
10835
10836 static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10837                             struct intel_crtc_state *pipe_config)
10838 {
10839         enum intel_dpll_id id;
10840         u32 temp;
10841
10842         temp = intel_de_read(dev_priv, DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
10843         id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
10844
10845         if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL2))
10846                 return;
10847
10848         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10849 }
10850
10851 static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10852                             struct intel_crtc_state *pipe_config)
10853 {
10854         enum phy phy = intel_port_to_phy(dev_priv, port);
10855         enum icl_port_dpll_id port_dpll_id;
10856         enum intel_dpll_id id;
10857         u32 temp;
10858
10859         if (intel_phy_is_combo(dev_priv, phy)) {
10860                 u32 mask, shift;
10861
10862                 if (IS_ROCKETLAKE(dev_priv)) {
10863                         mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
10864                         shift = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
10865                 } else {
10866                         mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
10867                         shift = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
10868                 }
10869
10870                 temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & mask;
10871                 id = temp >> shift;
10872                 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10873         } else if (intel_phy_is_tc(dev_priv, phy)) {
10874                 u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
10875
10876                 if (clk_sel == DDI_CLK_SEL_MG) {
10877                         id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
10878                                                                     port));
10879                         port_dpll_id = ICL_PORT_DPLL_MG_PHY;
10880                 } else {
10881                         drm_WARN_ON(&dev_priv->drm,
10882                                     clk_sel < DDI_CLK_SEL_TBT_162);
10883                         id = DPLL_ID_ICL_TBTPLL;
10884                         port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10885                 }
10886         } else {
10887                 drm_WARN(&dev_priv->drm, 1, "Invalid port %x\n", port);
10888                 return;
10889         }
10890
10891         pipe_config->icl_port_dplls[port_dpll_id].pll =
10892                 intel_get_shared_dpll_by_id(dev_priv, id);
10893
10894         icl_set_active_port_dpll(pipe_config, port_dpll_id);
10895 }
10896
10897 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10898                                 enum port port,
10899                                 struct intel_crtc_state *pipe_config)
10900 {
10901         enum intel_dpll_id id;
10902
10903         switch (port) {
10904         case PORT_A:
10905                 id = DPLL_ID_SKL_DPLL0;
10906                 break;
10907         case PORT_B:
10908                 id = DPLL_ID_SKL_DPLL1;
10909                 break;
10910         case PORT_C:
10911                 id = DPLL_ID_SKL_DPLL2;
10912                 break;
10913         default:
10914                 drm_err(&dev_priv->drm, "Incorrect port type\n");
10915                 return;
10916         }
10917
10918         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10919 }
10920
10921 static void skl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10922                             struct intel_crtc_state *pipe_config)
10923 {
10924         enum intel_dpll_id id;
10925         u32 temp;
10926
10927         temp = intel_de_read(dev_priv, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10928         id = temp >> (port * 3 + 1);
10929
10930         if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL3))
10931                 return;
10932
10933         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10934 }
10935
10936 static void hsw_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10937                             struct intel_crtc_state *pipe_config)
10938 {
10939         enum intel_dpll_id id;
10940         u32 ddi_pll_sel = intel_de_read(dev_priv, PORT_CLK_SEL(port));
10941
10942         switch (ddi_pll_sel) {
10943         case PORT_CLK_SEL_WRPLL1:
10944                 id = DPLL_ID_WRPLL1;
10945                 break;
10946         case PORT_CLK_SEL_WRPLL2:
10947                 id = DPLL_ID_WRPLL2;
10948                 break;
10949         case PORT_CLK_SEL_SPLL:
10950                 id = DPLL_ID_SPLL;
10951                 break;
10952         case PORT_CLK_SEL_LCPLL_810:
10953                 id = DPLL_ID_LCPLL_810;
10954                 break;
10955         case PORT_CLK_SEL_LCPLL_1350:
10956                 id = DPLL_ID_LCPLL_1350;
10957                 break;
10958         case PORT_CLK_SEL_LCPLL_2700:
10959                 id = DPLL_ID_LCPLL_2700;
10960                 break;
10961         default:
10962                 MISSING_CASE(ddi_pll_sel);
10963                 fallthrough;
10964         case PORT_CLK_SEL_NONE:
10965                 return;
10966         }
10967
10968         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10969 }
10970
10971 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10972                                      struct intel_crtc_state *pipe_config,
10973                                      u64 *power_domain_mask,
10974                                      intel_wakeref_t *wakerefs)
10975 {
10976         struct drm_device *dev = crtc->base.dev;
10977         struct drm_i915_private *dev_priv = to_i915(dev);
10978         enum intel_display_power_domain power_domain;
10979         unsigned long panel_transcoder_mask = BIT(TRANSCODER_EDP);
10980         unsigned long enabled_panel_transcoders = 0;
10981         enum transcoder panel_transcoder;
10982         intel_wakeref_t wf;
10983         u32 tmp;
10984
10985         if (INTEL_GEN(dev_priv) >= 11)
10986                 panel_transcoder_mask |=
10987                         BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
10988
10989         /*
10990          * The pipe->transcoder mapping is fixed with the exception of the eDP
10991          * and DSI transcoders handled below.
10992          */
10993         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10994
10995         /*
10996          * XXX: Do intel_display_power_get_if_enabled before reading this (for
10997          * consistency and less surprising code; it's in always on power).
10998          */
10999         for_each_cpu_transcoder_masked(dev_priv, panel_transcoder,
11000                                        panel_transcoder_mask) {
11001                 bool force_thru = false;
11002                 enum pipe trans_pipe;
11003
11004                 tmp = intel_de_read(dev_priv,
11005                                     TRANS_DDI_FUNC_CTL(panel_transcoder));
11006                 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
11007                         continue;
11008
11009                 /*
11010                  * Log all enabled ones, only use the first one.
11011                  *
11012                  * FIXME: This won't work for two separate DSI displays.
11013                  */
11014                 enabled_panel_transcoders |= BIT(panel_transcoder);
11015                 if (enabled_panel_transcoders != BIT(panel_transcoder))
11016                         continue;
11017
11018                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
11019                 default:
11020                         drm_WARN(dev, 1,
11021                                  "unknown pipe linked to transcoder %s\n",
11022                                  transcoder_name(panel_transcoder));
11023                         fallthrough;
11024                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
11025                         force_thru = true;
11026                         fallthrough;
11027                 case TRANS_DDI_EDP_INPUT_A_ON:
11028                         trans_pipe = PIPE_A;
11029                         break;
11030                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
11031                         trans_pipe = PIPE_B;
11032                         break;
11033                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
11034                         trans_pipe = PIPE_C;
11035                         break;
11036                 case TRANS_DDI_EDP_INPUT_D_ONOFF:
11037                         trans_pipe = PIPE_D;
11038                         break;
11039                 }
11040
11041                 if (trans_pipe == crtc->pipe) {
11042                         pipe_config->cpu_transcoder = panel_transcoder;
11043                         pipe_config->pch_pfit.force_thru = force_thru;
11044                 }
11045         }
11046
11047         /*
11048          * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1
11049          */
11050         drm_WARN_ON(dev, (enabled_panel_transcoders & BIT(TRANSCODER_EDP)) &&
11051                     enabled_panel_transcoders != BIT(TRANSCODER_EDP));
11052
11053         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
11054         drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain));
11055
11056         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11057         if (!wf)
11058                 return false;
11059
11060         wakerefs[power_domain] = wf;
11061         *power_domain_mask |= BIT_ULL(power_domain);
11062
11063         tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder));
11064
11065         return tmp & PIPECONF_ENABLE;
11066 }
11067
11068 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
11069                                          struct intel_crtc_state *pipe_config,
11070                                          u64 *power_domain_mask,
11071                                          intel_wakeref_t *wakerefs)
11072 {
11073         struct drm_device *dev = crtc->base.dev;
11074         struct drm_i915_private *dev_priv = to_i915(dev);
11075         enum intel_display_power_domain power_domain;
11076         enum transcoder cpu_transcoder;
11077         intel_wakeref_t wf;
11078         enum port port;
11079         u32 tmp;
11080
11081         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
11082                 if (port == PORT_A)
11083                         cpu_transcoder = TRANSCODER_DSI_A;
11084                 else
11085                         cpu_transcoder = TRANSCODER_DSI_C;
11086
11087                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
11088                 drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain));
11089
11090                 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11091                 if (!wf)
11092                         continue;
11093
11094                 wakerefs[power_domain] = wf;
11095                 *power_domain_mask |= BIT_ULL(power_domain);
11096
11097                 /*
11098                  * The PLL needs to be enabled with a valid divider
11099                  * configuration, otherwise accessing DSI registers will hang
11100                  * the machine. See BSpec North Display Engine
11101                  * registers/MIPI[BXT]. We can break out here early, since we
11102                  * need the same DSI PLL to be enabled for both DSI ports.
11103                  */
11104                 if (!bxt_dsi_pll_is_enabled(dev_priv))
11105                         break;
11106
11107                 /* XXX: this works for video mode only */
11108                 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
11109                 if (!(tmp & DPI_ENABLE))
11110                         continue;
11111
11112                 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
11113                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
11114                         continue;
11115
11116                 pipe_config->cpu_transcoder = cpu_transcoder;
11117                 break;
11118         }
11119
11120         return transcoder_is_dsi(pipe_config->cpu_transcoder);
11121 }
11122
11123 static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
11124                                    struct intel_crtc_state *pipe_config)
11125 {
11126         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11127         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
11128         struct intel_shared_dpll *pll;
11129         enum port port;
11130         u32 tmp;
11131
11132         if (transcoder_is_dsi(cpu_transcoder)) {
11133                 port = (cpu_transcoder == TRANSCODER_DSI_A) ?
11134                                                 PORT_A : PORT_B;
11135         } else {
11136                 tmp = intel_de_read(dev_priv,
11137                                     TRANS_DDI_FUNC_CTL(cpu_transcoder));
11138                 if (INTEL_GEN(dev_priv) >= 12)
11139                         port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
11140                 else
11141                         port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
11142         }
11143
11144         if (INTEL_GEN(dev_priv) >= 11)
11145                 icl_get_ddi_pll(dev_priv, port, pipe_config);
11146         else if (IS_CANNONLAKE(dev_priv))
11147                 cnl_get_ddi_pll(dev_priv, port, pipe_config);
11148         else if (IS_GEN9_BC(dev_priv))
11149                 skl_get_ddi_pll(dev_priv, port, pipe_config);
11150         else if (IS_GEN9_LP(dev_priv))
11151                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
11152         else
11153                 hsw_get_ddi_pll(dev_priv, port, pipe_config);
11154
11155         pll = pipe_config->shared_dpll;
11156         if (pll) {
11157                 drm_WARN_ON(&dev_priv->drm,
11158                             !pll->info->funcs->get_hw_state(dev_priv, pll,
11159                                                 &pipe_config->dpll_hw_state));
11160         }
11161
11162         /*
11163          * Haswell has only FDI/PCH transcoder A. It is which is connected to
11164          * DDI E. So just check whether this pipe is wired to DDI E and whether
11165          * the PCH transcoder is on.
11166          */
11167         if (INTEL_GEN(dev_priv) < 9 &&
11168             (port == PORT_E) && intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) {
11169                 pipe_config->has_pch_encoder = true;
11170
11171                 tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
11172                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
11173                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
11174
11175                 ilk_get_fdi_m_n_config(crtc, pipe_config);
11176         }
11177 }
11178
11179 static bool hsw_get_pipe_config(struct intel_crtc *crtc,
11180                                 struct intel_crtc_state *pipe_config)
11181 {
11182         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11183         intel_wakeref_t wakerefs[POWER_DOMAIN_NUM], wf;
11184         enum intel_display_power_domain power_domain;
11185         u64 power_domain_mask;
11186         bool active;
11187         u32 tmp;
11188
11189         pipe_config->master_transcoder = INVALID_TRANSCODER;
11190
11191         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
11192         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11193         if (!wf)
11194                 return false;
11195
11196         wakerefs[power_domain] = wf;
11197         power_domain_mask = BIT_ULL(power_domain);
11198
11199         pipe_config->shared_dpll = NULL;
11200
11201         active = hsw_get_transcoder_state(crtc, pipe_config,
11202                                           &power_domain_mask, wakerefs);
11203
11204         if (IS_GEN9_LP(dev_priv) &&
11205             bxt_get_dsi_transcoder_state(crtc, pipe_config,
11206                                          &power_domain_mask, wakerefs)) {
11207                 drm_WARN_ON(&dev_priv->drm, active);
11208                 active = true;
11209         }
11210
11211         if (!active)
11212                 goto out;
11213
11214         if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
11215             INTEL_GEN(dev_priv) >= 11) {
11216                 hsw_get_ddi_port_state(crtc, pipe_config);
11217                 intel_get_pipe_timings(crtc, pipe_config);
11218         }
11219
11220         intel_get_pipe_src_size(crtc, pipe_config);
11221
11222         if (IS_HASWELL(dev_priv)) {
11223                 u32 tmp = intel_de_read(dev_priv,
11224                                         PIPECONF(pipe_config->cpu_transcoder));
11225
11226                 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
11227                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
11228                 else
11229                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
11230         } else {
11231                 pipe_config->output_format =
11232                         bdw_get_pipemisc_output_format(crtc);
11233
11234                 /*
11235                  * Currently there is no interface defined to
11236                  * check user preference between RGB/YCBCR444
11237                  * or YCBCR420. So the only possible case for
11238                  * YCBCR444 usage is driving YCBCR420 output
11239                  * with LSPCON, when pipe is configured for
11240                  * YCBCR444 output and LSPCON takes care of
11241                  * downsampling it.
11242                  */
11243                 pipe_config->lspcon_downsampling =
11244                         pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444;
11245         }
11246
11247         pipe_config->gamma_mode = intel_de_read(dev_priv,
11248                                                 GAMMA_MODE(crtc->pipe));
11249
11250         pipe_config->csc_mode = intel_de_read(dev_priv,
11251                                               PIPE_CSC_MODE(crtc->pipe));
11252
11253         if (INTEL_GEN(dev_priv) >= 9) {
11254                 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe));
11255
11256                 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
11257                         pipe_config->gamma_enable = true;
11258
11259                 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
11260                         pipe_config->csc_enable = true;
11261         } else {
11262                 i9xx_get_pipe_color_config(pipe_config);
11263         }
11264
11265         intel_color_get_config(pipe_config);
11266
11267         tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));
11268         pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
11269         if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
11270                 pipe_config->ips_linetime =
11271                         REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
11272
11273         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
11274         drm_WARN_ON(&dev_priv->drm, power_domain_mask & BIT_ULL(power_domain));
11275
11276         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11277         if (wf) {
11278                 wakerefs[power_domain] = wf;
11279                 power_domain_mask |= BIT_ULL(power_domain);
11280
11281                 if (INTEL_GEN(dev_priv) >= 9)
11282                         skl_get_pfit_config(pipe_config);
11283                 else
11284                         ilk_get_pfit_config(pipe_config);
11285         }
11286
11287         if (hsw_crtc_supports_ips(crtc)) {
11288                 if (IS_HASWELL(dev_priv))
11289                         pipe_config->ips_enabled = intel_de_read(dev_priv,
11290                                                                  IPS_CTL) & IPS_ENABLE;
11291                 else {
11292                         /*
11293                          * We cannot readout IPS state on broadwell, set to
11294                          * true so we can set it to a defined state on first
11295                          * commit.
11296                          */
11297                         pipe_config->ips_enabled = true;
11298                 }
11299         }
11300
11301         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
11302             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
11303                 pipe_config->pixel_multiplier =
11304                         intel_de_read(dev_priv,
11305                                       PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
11306         } else {
11307                 pipe_config->pixel_multiplier = 1;
11308         }
11309
11310 out:
11311         for_each_power_domain(power_domain, power_domain_mask)
11312                 intel_display_power_put(dev_priv,
11313                                         power_domain, wakerefs[power_domain]);
11314
11315         return active;
11316 }
11317
11318 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
11319 {
11320         struct drm_i915_private *dev_priv =
11321                 to_i915(plane_state->uapi.plane->dev);
11322         const struct drm_framebuffer *fb = plane_state->hw.fb;
11323         const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11324         u32 base;
11325
11326         if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
11327                 base = sg_dma_address(obj->mm.pages->sgl);
11328         else
11329                 base = intel_plane_ggtt_offset(plane_state);
11330
11331         return base + plane_state->color_plane[0].offset;
11332 }
11333
11334 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
11335 {
11336         int x = plane_state->uapi.dst.x1;
11337         int y = plane_state->uapi.dst.y1;
11338         u32 pos = 0;
11339
11340         if (x < 0) {
11341                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
11342                 x = -x;
11343         }
11344         pos |= x << CURSOR_X_SHIFT;
11345
11346         if (y < 0) {
11347                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
11348                 y = -y;
11349         }
11350         pos |= y << CURSOR_Y_SHIFT;
11351
11352         return pos;
11353 }
11354
11355 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
11356 {
11357         const struct drm_mode_config *config =
11358                 &plane_state->uapi.plane->dev->mode_config;
11359         int width = drm_rect_width(&plane_state->uapi.dst);
11360         int height = drm_rect_height(&plane_state->uapi.dst);
11361
11362         return width > 0 && width <= config->cursor_width &&
11363                 height > 0 && height <= config->cursor_height;
11364 }
11365
11366 static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
11367 {
11368         struct drm_i915_private *dev_priv =
11369                 to_i915(plane_state->uapi.plane->dev);
11370         unsigned int rotation = plane_state->hw.rotation;
11371         int src_x, src_y;
11372         u32 offset;
11373         int ret;
11374
11375         ret = intel_plane_compute_gtt(plane_state);
11376         if (ret)
11377                 return ret;
11378
11379         if (!plane_state->uapi.visible)
11380                 return 0;
11381
11382         src_x = plane_state->uapi.src.x1 >> 16;
11383         src_y = plane_state->uapi.src.y1 >> 16;
11384
11385         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
11386         offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
11387                                                     plane_state, 0);
11388
11389         if (src_x != 0 || src_y != 0) {
11390                 drm_dbg_kms(&dev_priv->drm,
11391                             "Arbitrary cursor panning not supported\n");
11392                 return -EINVAL;
11393         }
11394
11395         /*
11396          * Put the final coordinates back so that the src
11397          * coordinate checks will see the right values.
11398          */
11399         drm_rect_translate_to(&plane_state->uapi.src,
11400                               src_x << 16, src_y << 16);
11401
11402         /* ILK+ do this automagically in hardware */
11403         if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) {
11404                 const struct drm_framebuffer *fb = plane_state->hw.fb;
11405                 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
11406                 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
11407
11408                 offset += (src_h * src_w - 1) * fb->format->cpp[0];
11409         }
11410
11411         plane_state->color_plane[0].offset = offset;
11412         plane_state->color_plane[0].x = src_x;
11413         plane_state->color_plane[0].y = src_y;
11414
11415         return 0;
11416 }
11417
11418 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
11419                               struct intel_plane_state *plane_state)
11420 {
11421         const struct drm_framebuffer *fb = plane_state->hw.fb;
11422         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
11423         int ret;
11424
11425         if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
11426                 drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n");
11427                 return -EINVAL;
11428         }
11429
11430         ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
11431                                                   &crtc_state->uapi,
11432                                                   DRM_PLANE_HELPER_NO_SCALING,
11433                                                   DRM_PLANE_HELPER_NO_SCALING,
11434                                                   true, true);
11435         if (ret)
11436                 return ret;
11437
11438         /* Use the unclipped src/dst rectangles, which we program to hw */
11439         plane_state->uapi.src = drm_plane_state_src(&plane_state->uapi);
11440         plane_state->uapi.dst = drm_plane_state_dest(&plane_state->uapi);
11441
11442         ret = intel_cursor_check_surface(plane_state);
11443         if (ret)
11444                 return ret;
11445
11446         if (!plane_state->uapi.visible)
11447                 return 0;
11448
11449         ret = intel_plane_check_src_coordinates(plane_state);
11450         if (ret)
11451                 return ret;
11452
11453         return 0;
11454 }
11455
11456 static unsigned int
11457 i845_cursor_max_stride(struct intel_plane *plane,
11458                        u32 pixel_format, u64 modifier,
11459                        unsigned int rotation)
11460 {
11461         return 2048;
11462 }
11463
11464 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
11465 {
11466         u32 cntl = 0;
11467
11468         if (crtc_state->gamma_enable)
11469                 cntl |= CURSOR_GAMMA_ENABLE;
11470
11471         return cntl;
11472 }
11473
11474 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
11475                            const struct intel_plane_state *plane_state)
11476 {
11477         return CURSOR_ENABLE |
11478                 CURSOR_FORMAT_ARGB |
11479                 CURSOR_STRIDE(plane_state->color_plane[0].stride);
11480 }
11481
11482 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
11483 {
11484         int width = drm_rect_width(&plane_state->uapi.dst);
11485
11486         /*
11487          * 845g/865g are only limited by the width of their cursors,
11488          * the height is arbitrary up to the precision of the register.
11489          */
11490         return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
11491 }
11492
11493 static int i845_check_cursor(struct intel_crtc_state *crtc_state,
11494                              struct intel_plane_state *plane_state)
11495 {
11496         const struct drm_framebuffer *fb = plane_state->hw.fb;
11497         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
11498         int ret;
11499
11500         ret = intel_check_cursor(crtc_state, plane_state);
11501         if (ret)
11502                 return ret;
11503
11504         /* if we want to turn off the cursor ignore width and height */
11505         if (!fb)
11506                 return 0;
11507
11508         /* Check for which cursor types we support */
11509         if (!i845_cursor_size_ok(plane_state)) {
11510                 drm_dbg_kms(&i915->drm,
11511                             "Cursor dimension %dx%d not supported\n",
11512                             drm_rect_width(&plane_state->uapi.dst),
11513                             drm_rect_height(&plane_state->uapi.dst));
11514                 return -EINVAL;
11515         }
11516
11517         drm_WARN_ON(&i915->drm, plane_state->uapi.visible &&
11518                     plane_state->color_plane[0].stride != fb->pitches[0]);
11519
11520         switch (fb->pitches[0]) {
11521         case 256:
11522         case 512:
11523         case 1024:
11524         case 2048:
11525                 break;
11526         default:
11527                  drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n",
11528                              fb->pitches[0]);
11529                 return -EINVAL;
11530         }
11531
11532         plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
11533
11534         return 0;
11535 }
11536
11537 static void i845_update_cursor(struct intel_plane *plane,
11538                                const struct intel_crtc_state *crtc_state,
11539                                const struct intel_plane_state *plane_state)
11540 {
11541         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11542         u32 cntl = 0, base = 0, pos = 0, size = 0;
11543         unsigned long irqflags;
11544
11545         if (plane_state && plane_state->uapi.visible) {
11546                 unsigned int width = drm_rect_width(&plane_state->uapi.dst);
11547                 unsigned int height = drm_rect_height(&plane_state->uapi.dst);
11548
11549                 cntl = plane_state->ctl |
11550                         i845_cursor_ctl_crtc(crtc_state);
11551
11552                 size = (height << 12) | width;
11553
11554                 base = intel_cursor_base(plane_state);
11555                 pos = intel_cursor_position(plane_state);
11556         }
11557
11558         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11559
11560         /* On these chipsets we can only modify the base/size/stride
11561          * whilst the cursor is disabled.
11562          */
11563         if (plane->cursor.base != base ||
11564             plane->cursor.size != size ||
11565             plane->cursor.cntl != cntl) {
11566                 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0);
11567                 intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base);
11568                 intel_de_write_fw(dev_priv, CURSIZE, size);
11569                 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
11570                 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl);
11571
11572                 plane->cursor.base = base;
11573                 plane->cursor.size = size;
11574                 plane->cursor.cntl = cntl;
11575         } else {
11576                 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
11577         }
11578
11579         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11580 }
11581
11582 static void i845_disable_cursor(struct intel_plane *plane,
11583                                 const struct intel_crtc_state *crtc_state)
11584 {
11585         i845_update_cursor(plane, crtc_state, NULL);
11586 }
11587
11588 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
11589                                      enum pipe *pipe)
11590 {
11591         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11592         enum intel_display_power_domain power_domain;
11593         intel_wakeref_t wakeref;
11594         bool ret;
11595
11596         power_domain = POWER_DOMAIN_PIPE(PIPE_A);
11597         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11598         if (!wakeref)
11599                 return false;
11600
11601         ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE;
11602
11603         *pipe = PIPE_A;
11604
11605         intel_display_power_put(dev_priv, power_domain, wakeref);
11606
11607         return ret;
11608 }
11609
11610 static unsigned int
11611 i9xx_cursor_max_stride(struct intel_plane *plane,
11612                        u32 pixel_format, u64 modifier,
11613                        unsigned int rotation)
11614 {
11615         return plane->base.dev->mode_config.cursor_width * 4;
11616 }
11617
11618 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
11619 {
11620         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
11621         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11622         u32 cntl = 0;
11623
11624         if (INTEL_GEN(dev_priv) >= 11)
11625                 return cntl;
11626
11627         if (crtc_state->gamma_enable)
11628                 cntl = MCURSOR_GAMMA_ENABLE;
11629
11630         if (crtc_state->csc_enable)
11631                 cntl |= MCURSOR_PIPE_CSC_ENABLE;
11632
11633         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11634                 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
11635
11636         return cntl;
11637 }
11638
11639 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
11640                            const struct intel_plane_state *plane_state)
11641 {
11642         struct drm_i915_private *dev_priv =
11643                 to_i915(plane_state->uapi.plane->dev);
11644         u32 cntl = 0;
11645
11646         if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
11647                 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
11648
11649         switch (drm_rect_width(&plane_state->uapi.dst)) {
11650         case 64:
11651                 cntl |= MCURSOR_MODE_64_ARGB_AX;
11652                 break;
11653         case 128:
11654                 cntl |= MCURSOR_MODE_128_ARGB_AX;
11655                 break;
11656         case 256:
11657                 cntl |= MCURSOR_MODE_256_ARGB_AX;
11658                 break;
11659         default:
11660                 MISSING_CASE(drm_rect_width(&plane_state->uapi.dst));
11661                 return 0;
11662         }
11663
11664         if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)
11665                 cntl |= MCURSOR_ROTATE_180;
11666
11667         return cntl;
11668 }
11669
11670 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
11671 {
11672         struct drm_i915_private *dev_priv =
11673                 to_i915(plane_state->uapi.plane->dev);
11674         int width = drm_rect_width(&plane_state->uapi.dst);
11675         int height = drm_rect_height(&plane_state->uapi.dst);
11676
11677         if (!intel_cursor_size_ok(plane_state))
11678                 return false;
11679
11680         /* Cursor width is limited to a few power-of-two sizes */
11681         switch (width) {
11682         case 256:
11683         case 128:
11684         case 64:
11685                 break;
11686         default:
11687                 return false;
11688         }
11689
11690         /*
11691          * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
11692          * height from 8 lines up to the cursor width, when the
11693          * cursor is not rotated. Everything else requires square
11694          * cursors.
11695          */
11696         if (HAS_CUR_FBC(dev_priv) &&
11697             plane_state->hw.rotation & DRM_MODE_ROTATE_0) {
11698                 if (height < 8 || height > width)
11699                         return false;
11700         } else {
11701                 if (height != width)
11702                         return false;
11703         }
11704
11705         return true;
11706 }
11707
11708 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
11709                              struct intel_plane_state *plane_state)
11710 {
11711         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
11712         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11713         const struct drm_framebuffer *fb = plane_state->hw.fb;
11714         enum pipe pipe = plane->pipe;
11715         int ret;
11716
11717         ret = intel_check_cursor(crtc_state, plane_state);
11718         if (ret)
11719                 return ret;
11720
11721         /* if we want to turn off the cursor ignore width and height */
11722         if (!fb)
11723                 return 0;
11724
11725         /* Check for which cursor types we support */
11726         if (!i9xx_cursor_size_ok(plane_state)) {
11727                 drm_dbg(&dev_priv->drm,
11728                         "Cursor dimension %dx%d not supported\n",
11729                         drm_rect_width(&plane_state->uapi.dst),
11730                         drm_rect_height(&plane_state->uapi.dst));
11731                 return -EINVAL;
11732         }
11733
11734         drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible &&
11735                     plane_state->color_plane[0].stride != fb->pitches[0]);
11736
11737         if (fb->pitches[0] !=
11738             drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) {
11739                 drm_dbg_kms(&dev_priv->drm,
11740                             "Invalid cursor stride (%u) (cursor width %d)\n",
11741                             fb->pitches[0],
11742                             drm_rect_width(&plane_state->uapi.dst));
11743                 return -EINVAL;
11744         }
11745
11746         /*
11747          * There's something wrong with the cursor on CHV pipe C.
11748          * If it straddles the left edge of the screen then
11749          * moving it away from the edge or disabling it often
11750          * results in a pipe underrun, and often that can lead to
11751          * dead pipe (constant underrun reported, and it scans
11752          * out just a solid color). To recover from that, the
11753          * display power well must be turned off and on again.
11754          * Refuse the put the cursor into that compromised position.
11755          */
11756         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
11757             plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) {
11758                 drm_dbg_kms(&dev_priv->drm,
11759                             "CHV cursor C not allowed to straddle the left screen edge\n");
11760                 return -EINVAL;
11761         }
11762
11763         plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
11764
11765         return 0;
11766 }
11767
11768 static void i9xx_update_cursor(struct intel_plane *plane,
11769                                const struct intel_crtc_state *crtc_state,
11770                                const struct intel_plane_state *plane_state)
11771 {
11772         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11773         enum pipe pipe = plane->pipe;
11774         u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
11775         unsigned long irqflags;
11776
11777         if (plane_state && plane_state->uapi.visible) {
11778                 unsigned width = drm_rect_width(&plane_state->uapi.dst);
11779                 unsigned height = drm_rect_height(&plane_state->uapi.dst);
11780
11781                 cntl = plane_state->ctl |
11782                         i9xx_cursor_ctl_crtc(crtc_state);
11783
11784                 if (width != height)
11785                         fbc_ctl = CUR_FBC_CTL_EN | (height - 1);
11786
11787                 base = intel_cursor_base(plane_state);
11788                 pos = intel_cursor_position(plane_state);
11789         }
11790
11791         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11792
11793         /*
11794          * On some platforms writing CURCNTR first will also
11795          * cause CURPOS to be armed by the CURBASE write.
11796          * Without the CURCNTR write the CURPOS write would
11797          * arm itself. Thus we always update CURCNTR before
11798          * CURPOS.
11799          *
11800          * On other platforms CURPOS always requires the
11801          * CURBASE write to arm the update. Additonally
11802          * a write to any of the cursor register will cancel
11803          * an already armed cursor update. Thus leaving out
11804          * the CURBASE write after CURPOS could lead to a
11805          * cursor that doesn't appear to move, or even change
11806          * shape. Thus we always write CURBASE.
11807          *
11808          * The other registers are armed by by the CURBASE write
11809          * except when the plane is getting enabled at which time
11810          * the CURCNTR write arms the update.
11811          */
11812
11813         if (INTEL_GEN(dev_priv) >= 9)
11814                 skl_write_cursor_wm(plane, crtc_state);
11815
11816         if (plane->cursor.base != base ||
11817             plane->cursor.size != fbc_ctl ||
11818             plane->cursor.cntl != cntl) {
11819                 if (HAS_CUR_FBC(dev_priv))
11820                         intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe),
11821                                           fbc_ctl);
11822                 intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl);
11823                 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
11824                 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
11825
11826                 plane->cursor.base = base;
11827                 plane->cursor.size = fbc_ctl;
11828                 plane->cursor.cntl = cntl;
11829         } else {
11830                 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
11831                 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
11832         }
11833
11834         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11835 }
11836
11837 static void i9xx_disable_cursor(struct intel_plane *plane,
11838                                 const struct intel_crtc_state *crtc_state)
11839 {
11840         i9xx_update_cursor(plane, crtc_state, NULL);
11841 }
11842
11843 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
11844                                      enum pipe *pipe)
11845 {
11846         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11847         enum intel_display_power_domain power_domain;
11848         intel_wakeref_t wakeref;
11849         bool ret;
11850         u32 val;
11851
11852         /*
11853          * Not 100% correct for planes that can move between pipes,
11854          * but that's only the case for gen2-3 which don't have any
11855          * display power wells.
11856          */
11857         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
11858         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11859         if (!wakeref)
11860                 return false;
11861
11862         val = intel_de_read(dev_priv, CURCNTR(plane->pipe));
11863
11864         ret = val & MCURSOR_MODE;
11865
11866         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
11867                 *pipe = plane->pipe;
11868         else
11869                 *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
11870                         MCURSOR_PIPE_SELECT_SHIFT;
11871
11872         intel_display_power_put(dev_priv, power_domain, wakeref);
11873
11874         return ret;
11875 }
11876
11877 /* VESA 640x480x72Hz mode to set on the pipe */
11878 static const struct drm_display_mode load_detect_mode = {
11879         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
11880                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
11881 };
11882
11883 struct drm_framebuffer *
11884 intel_framebuffer_create(struct drm_i915_gem_object *obj,
11885                          struct drm_mode_fb_cmd2 *mode_cmd)
11886 {
11887         struct intel_framebuffer *intel_fb;
11888         int ret;
11889
11890         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
11891         if (!intel_fb)
11892                 return ERR_PTR(-ENOMEM);
11893
11894         ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
11895         if (ret)
11896                 goto err;
11897
11898         return &intel_fb->base;
11899
11900 err:
11901         kfree(intel_fb);
11902         return ERR_PTR(ret);
11903 }
11904
11905 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
11906                                         struct drm_crtc *crtc)
11907 {
11908         struct drm_plane *plane;
11909         struct drm_plane_state *plane_state;
11910         int ret, i;
11911
11912         ret = drm_atomic_add_affected_planes(state, crtc);
11913         if (ret)
11914                 return ret;
11915
11916         for_each_new_plane_in_state(state, plane, plane_state, i) {
11917                 if (plane_state->crtc != crtc)
11918                         continue;
11919
11920                 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
11921                 if (ret)
11922                         return ret;
11923
11924                 drm_atomic_set_fb_for_plane(plane_state, NULL);
11925         }
11926
11927         return 0;
11928 }
11929
11930 int intel_get_load_detect_pipe(struct drm_connector *connector,
11931                                struct intel_load_detect_pipe *old,
11932                                struct drm_modeset_acquire_ctx *ctx)
11933 {
11934         struct intel_crtc *intel_crtc;
11935         struct intel_encoder *intel_encoder =
11936                 intel_attached_encoder(to_intel_connector(connector));
11937         struct drm_crtc *possible_crtc;
11938         struct drm_encoder *encoder = &intel_encoder->base;
11939         struct drm_crtc *crtc = NULL;
11940         struct drm_device *dev = encoder->dev;
11941         struct drm_i915_private *dev_priv = to_i915(dev);
11942         struct drm_mode_config *config = &dev->mode_config;
11943         struct drm_atomic_state *state = NULL, *restore_state = NULL;
11944         struct drm_connector_state *connector_state;
11945         struct intel_crtc_state *crtc_state;
11946         int ret, i = -1;
11947
11948         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11949                     connector->base.id, connector->name,
11950                     encoder->base.id, encoder->name);
11951
11952         old->restore_state = NULL;
11953
11954         drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex));
11955
11956         /*
11957          * Algorithm gets a little messy:
11958          *
11959          *   - if the connector already has an assigned crtc, use it (but make
11960          *     sure it's on first)
11961          *
11962          *   - try to find the first unused crtc that can drive this connector,
11963          *     and use that if we find one
11964          */
11965
11966         /* See if we already have a CRTC for this connector */
11967         if (connector->state->crtc) {
11968                 crtc = connector->state->crtc;
11969
11970                 ret = drm_modeset_lock(&crtc->mutex, ctx);
11971                 if (ret)
11972                         goto fail;
11973
11974                 /* Make sure the crtc and connector are running */
11975                 goto found;
11976         }
11977
11978         /* Find an unused one (if possible) */
11979         for_each_crtc(dev, possible_crtc) {
11980                 i++;
11981                 if (!(encoder->possible_crtcs & (1 << i)))
11982                         continue;
11983
11984                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11985                 if (ret)
11986                         goto fail;
11987
11988                 if (possible_crtc->state->enable) {
11989                         drm_modeset_unlock(&possible_crtc->mutex);
11990                         continue;
11991                 }
11992
11993                 crtc = possible_crtc;
11994                 break;
11995         }
11996
11997         /*
11998          * If we didn't find an unused CRTC, don't use any.
11999          */
12000         if (!crtc) {
12001                 drm_dbg_kms(&dev_priv->drm,
12002                             "no pipe available for load-detect\n");
12003                 ret = -ENODEV;
12004                 goto fail;
12005         }
12006
12007 found:
12008         intel_crtc = to_intel_crtc(crtc);
12009
12010         state = drm_atomic_state_alloc(dev);
12011         restore_state = drm_atomic_state_alloc(dev);
12012         if (!state || !restore_state) {
12013                 ret = -ENOMEM;
12014                 goto fail;
12015         }
12016
12017         state->acquire_ctx = ctx;
12018         restore_state->acquire_ctx = ctx;
12019
12020         connector_state = drm_atomic_get_connector_state(state, connector);
12021         if (IS_ERR(connector_state)) {
12022                 ret = PTR_ERR(connector_state);
12023                 goto fail;
12024         }
12025
12026         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
12027         if (ret)
12028                 goto fail;
12029
12030         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
12031         if (IS_ERR(crtc_state)) {
12032                 ret = PTR_ERR(crtc_state);
12033                 goto fail;
12034         }
12035
12036         crtc_state->uapi.active = true;
12037
12038         ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi,
12039                                            &load_detect_mode);
12040         if (ret)
12041                 goto fail;
12042
12043         ret = intel_modeset_disable_planes(state, crtc);
12044         if (ret)
12045                 goto fail;
12046
12047         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
12048         if (!ret)
12049                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
12050         if (!ret)
12051                 ret = drm_atomic_add_affected_planes(restore_state, crtc);
12052         if (ret) {
12053                 drm_dbg_kms(&dev_priv->drm,
12054                             "Failed to create a copy of old state to restore: %i\n",
12055                             ret);
12056                 goto fail;
12057         }
12058
12059         ret = drm_atomic_commit(state);
12060         if (ret) {
12061                 drm_dbg_kms(&dev_priv->drm,
12062                             "failed to set mode on load-detect pipe\n");
12063                 goto fail;
12064         }
12065
12066         old->restore_state = restore_state;
12067         drm_atomic_state_put(state);
12068
12069         /* let the connector get through one full cycle before testing */
12070         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
12071         return true;
12072
12073 fail:
12074         if (state) {
12075                 drm_atomic_state_put(state);
12076                 state = NULL;
12077         }
12078         if (restore_state) {
12079                 drm_atomic_state_put(restore_state);
12080                 restore_state = NULL;
12081         }
12082
12083         if (ret == -EDEADLK)
12084                 return ret;
12085
12086         return false;
12087 }
12088
12089 void intel_release_load_detect_pipe(struct drm_connector *connector,
12090                                     struct intel_load_detect_pipe *old,
12091                                     struct drm_modeset_acquire_ctx *ctx)
12092 {
12093         struct intel_encoder *intel_encoder =
12094                 intel_attached_encoder(to_intel_connector(connector));
12095         struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev);
12096         struct drm_encoder *encoder = &intel_encoder->base;
12097         struct drm_atomic_state *state = old->restore_state;
12098         int ret;
12099
12100         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
12101                     connector->base.id, connector->name,
12102                     encoder->base.id, encoder->name);
12103
12104         if (!state)
12105                 return;
12106
12107         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
12108         if (ret)
12109                 drm_dbg_kms(&i915->drm,
12110                             "Couldn't release load detect pipe: %i\n", ret);
12111         drm_atomic_state_put(state);
12112 }
12113
12114 static int i9xx_pll_refclk(struct drm_device *dev,
12115                            const struct intel_crtc_state *pipe_config)
12116 {
12117         struct drm_i915_private *dev_priv = to_i915(dev);
12118         u32 dpll = pipe_config->dpll_hw_state.dpll;
12119
12120         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
12121                 return dev_priv->vbt.lvds_ssc_freq;
12122         else if (HAS_PCH_SPLIT(dev_priv))
12123                 return 120000;
12124         else if (!IS_GEN(dev_priv, 2))
12125                 return 96000;
12126         else
12127                 return 48000;
12128 }
12129
12130 /* Returns the clock of the currently programmed mode of the given pipe. */
12131 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
12132                                 struct intel_crtc_state *pipe_config)
12133 {
12134         struct drm_device *dev = crtc->base.dev;
12135         struct drm_i915_private *dev_priv = to_i915(dev);
12136         enum pipe pipe = crtc->pipe;
12137         u32 dpll = pipe_config->dpll_hw_state.dpll;
12138         u32 fp;
12139         struct dpll clock;
12140         int port_clock;
12141         int refclk = i9xx_pll_refclk(dev, pipe_config);
12142
12143         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
12144                 fp = pipe_config->dpll_hw_state.fp0;
12145         else
12146                 fp = pipe_config->dpll_hw_state.fp1;
12147
12148         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
12149         if (IS_PINEVIEW(dev_priv)) {
12150                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
12151                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
12152         } else {
12153                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
12154                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
12155         }
12156
12157         if (!IS_GEN(dev_priv, 2)) {
12158                 if (IS_PINEVIEW(dev_priv))
12159                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
12160                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
12161                 else
12162                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
12163                                DPLL_FPA01_P1_POST_DIV_SHIFT);
12164
12165                 switch (dpll & DPLL_MODE_MASK) {
12166                 case DPLLB_MODE_DAC_SERIAL:
12167                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
12168                                 5 : 10;
12169                         break;
12170                 case DPLLB_MODE_LVDS:
12171                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
12172                                 7 : 14;
12173                         break;
12174                 default:
12175                         drm_dbg_kms(&dev_priv->drm,
12176                                     "Unknown DPLL mode %08x in programmed "
12177                                     "mode\n", (int)(dpll & DPLL_MODE_MASK));
12178                         return;
12179                 }
12180
12181                 if (IS_PINEVIEW(dev_priv))
12182                         port_clock = pnv_calc_dpll_params(refclk, &clock);
12183                 else
12184                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
12185         } else {
12186                 u32 lvds = IS_I830(dev_priv) ? 0 : intel_de_read(dev_priv,
12187                                                                  LVDS);
12188                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
12189
12190                 if (is_lvds) {
12191                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
12192                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
12193
12194                         if (lvds & LVDS_CLKB_POWER_UP)
12195                                 clock.p2 = 7;
12196                         else
12197                                 clock.p2 = 14;
12198                 } else {
12199                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
12200                                 clock.p1 = 2;
12201                         else {
12202                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
12203                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
12204                         }
12205                         if (dpll & PLL_P2_DIVIDE_BY_4)
12206                                 clock.p2 = 4;
12207                         else
12208                                 clock.p2 = 2;
12209                 }
12210
12211                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
12212         }
12213
12214         /*
12215          * This value includes pixel_multiplier. We will use
12216          * port_clock to compute adjusted_mode.crtc_clock in the
12217          * encoder's get_config() function.
12218          */
12219         pipe_config->port_clock = port_clock;
12220 }
12221
12222 int intel_dotclock_calculate(int link_freq,
12223                              const struct intel_link_m_n *m_n)
12224 {
12225         /*
12226          * The calculation for the data clock is:
12227          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
12228          * But we want to avoid losing precison if possible, so:
12229          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
12230          *
12231          * and the link clock is simpler:
12232          * link_clock = (m * link_clock) / n
12233          */
12234
12235         if (!m_n->link_n)
12236                 return 0;
12237
12238         return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
12239 }
12240
12241 static void ilk_pch_clock_get(struct intel_crtc *crtc,
12242                               struct intel_crtc_state *pipe_config)
12243 {
12244         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12245
12246         /* read out port_clock from the DPLL */
12247         i9xx_crtc_clock_get(crtc, pipe_config);
12248
12249         /*
12250          * In case there is an active pipe without active ports,
12251          * we may need some idea for the dotclock anyway.
12252          * Calculate one based on the FDI configuration.
12253          */
12254         pipe_config->hw.adjusted_mode.crtc_clock =
12255                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12256                                          &pipe_config->fdi_m_n);
12257 }
12258
12259 static void intel_crtc_state_reset(struct intel_crtc_state *crtc_state,
12260                                    struct intel_crtc *crtc)
12261 {
12262         memset(crtc_state, 0, sizeof(*crtc_state));
12263
12264         __drm_atomic_helper_crtc_state_reset(&crtc_state->uapi, &crtc->base);
12265
12266         crtc_state->cpu_transcoder = INVALID_TRANSCODER;
12267         crtc_state->master_transcoder = INVALID_TRANSCODER;
12268         crtc_state->hsw_workaround_pipe = INVALID_PIPE;
12269         crtc_state->output_format = INTEL_OUTPUT_FORMAT_INVALID;
12270         crtc_state->scaler_state.scaler_id = -1;
12271         crtc_state->mst_master_transcoder = INVALID_TRANSCODER;
12272 }
12273
12274 static struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc)
12275 {
12276         struct intel_crtc_state *crtc_state;
12277
12278         crtc_state = kmalloc(sizeof(*crtc_state), GFP_KERNEL);
12279
12280         if (crtc_state)
12281                 intel_crtc_state_reset(crtc_state, crtc);
12282
12283         return crtc_state;
12284 }
12285
12286 /* Returns the currently programmed mode of the given encoder. */
12287 struct drm_display_mode *
12288 intel_encoder_current_mode(struct intel_encoder *encoder)
12289 {
12290         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
12291         struct intel_crtc_state *crtc_state;
12292         struct drm_display_mode *mode;
12293         struct intel_crtc *crtc;
12294         enum pipe pipe;
12295
12296         if (!encoder->get_hw_state(encoder, &pipe))
12297                 return NULL;
12298
12299         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12300
12301         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
12302         if (!mode)
12303                 return NULL;
12304
12305         crtc_state = intel_crtc_state_alloc(crtc);
12306         if (!crtc_state) {
12307                 kfree(mode);
12308                 return NULL;
12309         }
12310
12311         if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
12312                 kfree(crtc_state);
12313                 kfree(mode);
12314                 return NULL;
12315         }
12316
12317         encoder->get_config(encoder, crtc_state);
12318
12319         intel_mode_from_pipe_config(mode, crtc_state);
12320
12321         kfree(crtc_state);
12322
12323         return mode;
12324 }
12325
12326 static void intel_crtc_destroy(struct drm_crtc *crtc)
12327 {
12328         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12329
12330         drm_crtc_cleanup(crtc);
12331         kfree(intel_crtc);
12332 }
12333
12334 /**
12335  * intel_wm_need_update - Check whether watermarks need updating
12336  * @cur: current plane state
12337  * @new: new plane state
12338  *
12339  * Check current plane state versus the new one to determine whether
12340  * watermarks need to be recalculated.
12341  *
12342  * Returns true or false.
12343  */
12344 static bool intel_wm_need_update(const struct intel_plane_state *cur,
12345                                  struct intel_plane_state *new)
12346 {
12347         /* Update watermarks on tiling or size changes. */
12348         if (new->uapi.visible != cur->uapi.visible)
12349                 return true;
12350
12351         if (!cur->hw.fb || !new->hw.fb)
12352                 return false;
12353
12354         if (cur->hw.fb->modifier != new->hw.fb->modifier ||
12355             cur->hw.rotation != new->hw.rotation ||
12356             drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
12357             drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
12358             drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
12359             drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
12360                 return true;
12361
12362         return false;
12363 }
12364
12365 static bool needs_scaling(const struct intel_plane_state *state)
12366 {
12367         int src_w = drm_rect_width(&state->uapi.src) >> 16;
12368         int src_h = drm_rect_height(&state->uapi.src) >> 16;
12369         int dst_w = drm_rect_width(&state->uapi.dst);
12370         int dst_h = drm_rect_height(&state->uapi.dst);
12371
12372         return (src_w != dst_w || src_h != dst_h);
12373 }
12374
12375 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
12376                                     struct intel_crtc_state *crtc_state,
12377                                     const struct intel_plane_state *old_plane_state,
12378                                     struct intel_plane_state *plane_state)
12379 {
12380         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12381         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
12382         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12383         bool mode_changed = needs_modeset(crtc_state);
12384         bool was_crtc_enabled = old_crtc_state->hw.active;
12385         bool is_crtc_enabled = crtc_state->hw.active;
12386         bool turn_off, turn_on, visible, was_visible;
12387         int ret;
12388
12389         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
12390                 ret = skl_update_scaler_plane(crtc_state, plane_state);
12391                 if (ret)
12392                         return ret;
12393         }
12394
12395         was_visible = old_plane_state->uapi.visible;
12396         visible = plane_state->uapi.visible;
12397
12398         if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible))
12399                 was_visible = false;
12400
12401         /*
12402          * Visibility is calculated as if the crtc was on, but
12403          * after scaler setup everything depends on it being off
12404          * when the crtc isn't active.
12405          *
12406          * FIXME this is wrong for watermarks. Watermarks should also
12407          * be computed as if the pipe would be active. Perhaps move
12408          * per-plane wm computation to the .check_plane() hook, and
12409          * only combine the results from all planes in the current place?
12410          */
12411         if (!is_crtc_enabled) {
12412                 intel_plane_set_invisible(crtc_state, plane_state);
12413                 visible = false;
12414         }
12415
12416         if (!was_visible && !visible)
12417                 return 0;
12418
12419         turn_off = was_visible && (!visible || mode_changed);
12420         turn_on = visible && (!was_visible || mode_changed);
12421
12422         drm_dbg_atomic(&dev_priv->drm,
12423                        "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12424                        crtc->base.base.id, crtc->base.name,
12425                        plane->base.base.id, plane->base.name,
12426                        was_visible, visible,
12427                        turn_off, turn_on, mode_changed);
12428
12429         if (turn_on) {
12430                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
12431                         crtc_state->update_wm_pre = true;
12432
12433                 /* must disable cxsr around plane enable/disable */
12434                 if (plane->id != PLANE_CURSOR)
12435                         crtc_state->disable_cxsr = true;
12436         } else if (turn_off) {
12437                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
12438                         crtc_state->update_wm_post = true;
12439
12440                 /* must disable cxsr around plane enable/disable */
12441                 if (plane->id != PLANE_CURSOR)
12442                         crtc_state->disable_cxsr = true;
12443         } else if (intel_wm_need_update(old_plane_state, plane_state)) {
12444                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
12445                         /* FIXME bollocks */
12446                         crtc_state->update_wm_pre = true;
12447                         crtc_state->update_wm_post = true;
12448                 }
12449         }
12450
12451         if (visible || was_visible)
12452                 crtc_state->fb_bits |= plane->frontbuffer_bit;
12453
12454         /*
12455          * ILK/SNB DVSACNTR/Sprite Enable
12456          * IVB SPR_CTL/Sprite Enable
12457          * "When in Self Refresh Big FIFO mode, a write to enable the
12458          *  plane will be internally buffered and delayed while Big FIFO
12459          *  mode is exiting."
12460          *
12461          * Which means that enabling the sprite can take an extra frame
12462          * when we start in big FIFO mode (LP1+). Thus we need to drop
12463          * down to LP0 and wait for vblank in order to make sure the
12464          * sprite gets enabled on the next vblank after the register write.
12465          * Doing otherwise would risk enabling the sprite one frame after
12466          * we've already signalled flip completion. We can resume LP1+
12467          * once the sprite has been enabled.
12468          *
12469          *
12470          * WaCxSRDisabledForSpriteScaling:ivb
12471          * IVB SPR_SCALE/Scaling Enable
12472          * "Low Power watermarks must be disabled for at least one
12473          *  frame before enabling sprite scaling, and kept disabled
12474          *  until sprite scaling is disabled."
12475          *
12476          * ILK/SNB DVSASCALE/Scaling Enable
12477          * "When in Self Refresh Big FIFO mode, scaling enable will be
12478          *  masked off while Big FIFO mode is exiting."
12479          *
12480          * Despite the w/a only being listed for IVB we assume that
12481          * the ILK/SNB note has similar ramifications, hence we apply
12482          * the w/a on all three platforms.
12483          *
12484          * With experimental results seems this is needed also for primary
12485          * plane, not only sprite plane.
12486          */
12487         if (plane->id != PLANE_CURSOR &&
12488             (IS_GEN_RANGE(dev_priv, 5, 6) ||
12489              IS_IVYBRIDGE(dev_priv)) &&
12490             (turn_on || (!needs_scaling(old_plane_state) &&
12491                          needs_scaling(plane_state))))
12492                 crtc_state->disable_lp_wm = true;
12493
12494         return 0;
12495 }
12496
12497 static bool encoders_cloneable(const struct intel_encoder *a,
12498                                const struct intel_encoder *b)
12499 {
12500         /* masks could be asymmetric, so check both ways */
12501         return a == b || (a->cloneable & (1 << b->type) &&
12502                           b->cloneable & (1 << a->type));
12503 }
12504
12505 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12506                                          struct intel_crtc *crtc,
12507                                          struct intel_encoder *encoder)
12508 {
12509         struct intel_encoder *source_encoder;
12510         struct drm_connector *connector;
12511         struct drm_connector_state *connector_state;
12512         int i;
12513
12514         for_each_new_connector_in_state(state, connector, connector_state, i) {
12515                 if (connector_state->crtc != &crtc->base)
12516                         continue;
12517
12518                 source_encoder =
12519                         to_intel_encoder(connector_state->best_encoder);
12520                 if (!encoders_cloneable(encoder, source_encoder))
12521                         return false;
12522         }
12523
12524         return true;
12525 }
12526
12527 static int icl_add_linked_planes(struct intel_atomic_state *state)
12528 {
12529         struct intel_plane *plane, *linked;
12530         struct intel_plane_state *plane_state, *linked_plane_state;
12531         int i;
12532
12533         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12534                 linked = plane_state->planar_linked_plane;
12535
12536                 if (!linked)
12537                         continue;
12538
12539                 linked_plane_state = intel_atomic_get_plane_state(state, linked);
12540                 if (IS_ERR(linked_plane_state))
12541                         return PTR_ERR(linked_plane_state);
12542
12543                 drm_WARN_ON(state->base.dev,
12544                             linked_plane_state->planar_linked_plane != plane);
12545                 drm_WARN_ON(state->base.dev,
12546                             linked_plane_state->planar_slave == plane_state->planar_slave);
12547         }
12548
12549         return 0;
12550 }
12551
12552 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
12553 {
12554         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12555         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12556         struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
12557         struct intel_plane *plane, *linked;
12558         struct intel_plane_state *plane_state;
12559         int i;
12560
12561         if (INTEL_GEN(dev_priv) < 11)
12562                 return 0;
12563
12564         /*
12565          * Destroy all old plane links and make the slave plane invisible
12566          * in the crtc_state->active_planes mask.
12567          */
12568         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12569                 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
12570                         continue;
12571
12572                 plane_state->planar_linked_plane = NULL;
12573                 if (plane_state->planar_slave && !plane_state->uapi.visible) {
12574                         crtc_state->active_planes &= ~BIT(plane->id);
12575                         crtc_state->update_planes |= BIT(plane->id);
12576                 }
12577
12578                 plane_state->planar_slave = false;
12579         }
12580
12581         if (!crtc_state->nv12_planes)
12582                 return 0;
12583
12584         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12585                 struct intel_plane_state *linked_state = NULL;
12586
12587                 if (plane->pipe != crtc->pipe ||
12588                     !(crtc_state->nv12_planes & BIT(plane->id)))
12589                         continue;
12590
12591                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
12592                         if (!icl_is_nv12_y_plane(dev_priv, linked->id))
12593                                 continue;
12594
12595                         if (crtc_state->active_planes & BIT(linked->id))
12596                                 continue;
12597
12598                         linked_state = intel_atomic_get_plane_state(state, linked);
12599                         if (IS_ERR(linked_state))
12600                                 return PTR_ERR(linked_state);
12601
12602                         break;
12603                 }
12604
12605                 if (!linked_state) {
12606                         drm_dbg_kms(&dev_priv->drm,
12607                                     "Need %d free Y planes for planar YUV\n",
12608                                     hweight8(crtc_state->nv12_planes));
12609
12610                         return -EINVAL;
12611                 }
12612
12613                 plane_state->planar_linked_plane = linked;
12614
12615                 linked_state->planar_slave = true;
12616                 linked_state->planar_linked_plane = plane;
12617                 crtc_state->active_planes |= BIT(linked->id);
12618                 crtc_state->update_planes |= BIT(linked->id);
12619                 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
12620                             linked->base.name, plane->base.name);
12621
12622                 /* Copy parameters to slave plane */
12623                 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
12624                 linked_state->color_ctl = plane_state->color_ctl;
12625                 linked_state->view = plane_state->view;
12626                 memcpy(linked_state->color_plane, plane_state->color_plane,
12627                        sizeof(linked_state->color_plane));
12628
12629                 intel_plane_copy_uapi_to_hw_state(linked_state, plane_state);
12630                 linked_state->uapi.src = plane_state->uapi.src;
12631                 linked_state->uapi.dst = plane_state->uapi.dst;
12632
12633                 if (icl_is_hdr_plane(dev_priv, plane->id)) {
12634                         if (linked->id == PLANE_SPRITE5)
12635                                 plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
12636                         else if (linked->id == PLANE_SPRITE4)
12637                                 plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
12638                         else if (linked->id == PLANE_SPRITE3)
12639                                 plane_state->cus_ctl |= PLANE_CUS_PLANE_5_RKL;
12640                         else if (linked->id == PLANE_SPRITE2)
12641                                 plane_state->cus_ctl |= PLANE_CUS_PLANE_4_RKL;
12642                         else
12643                                 MISSING_CASE(linked->id);
12644                 }
12645         }
12646
12647         return 0;
12648 }
12649
12650 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
12651 {
12652         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
12653         struct intel_atomic_state *state =
12654                 to_intel_atomic_state(new_crtc_state->uapi.state);
12655         const struct intel_crtc_state *old_crtc_state =
12656                 intel_atomic_get_old_crtc_state(state, crtc);
12657
12658         return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
12659 }
12660
12661 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
12662 {
12663         const struct drm_display_mode *adjusted_mode =
12664                 &crtc_state->hw.adjusted_mode;
12665         int linetime_wm;
12666
12667         if (!crtc_state->hw.enable)
12668                 return 0;
12669
12670         linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
12671                                         adjusted_mode->crtc_clock);
12672
12673         return min(linetime_wm, 0x1ff);
12674 }
12675
12676 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
12677                                const struct intel_cdclk_state *cdclk_state)
12678 {
12679         const struct drm_display_mode *adjusted_mode =
12680                 &crtc_state->hw.adjusted_mode;
12681         int linetime_wm;
12682
12683         if (!crtc_state->hw.enable)
12684                 return 0;
12685
12686         linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
12687                                         cdclk_state->logical.cdclk);
12688
12689         return min(linetime_wm, 0x1ff);
12690 }
12691
12692 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
12693 {
12694         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12695         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12696         const struct drm_display_mode *adjusted_mode =
12697                 &crtc_state->hw.adjusted_mode;
12698         int linetime_wm;
12699
12700         if (!crtc_state->hw.enable)
12701                 return 0;
12702
12703         linetime_wm = DIV_ROUND_UP(adjusted_mode->crtc_htotal * 1000 * 8,
12704                                    crtc_state->pixel_rate);
12705
12706         /* Display WA #1135: BXT:ALL GLK:ALL */
12707         if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled)
12708                 linetime_wm /= 2;
12709
12710         return min(linetime_wm, 0x1ff);
12711 }
12712
12713 static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
12714                                    struct intel_crtc *crtc)
12715 {
12716         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12717         struct intel_crtc_state *crtc_state =
12718                 intel_atomic_get_new_crtc_state(state, crtc);
12719         const struct intel_cdclk_state *cdclk_state;
12720
12721         if (INTEL_GEN(dev_priv) >= 9)
12722                 crtc_state->linetime = skl_linetime_wm(crtc_state);
12723         else
12724                 crtc_state->linetime = hsw_linetime_wm(crtc_state);
12725
12726         if (!hsw_crtc_supports_ips(crtc))
12727                 return 0;
12728
12729         cdclk_state = intel_atomic_get_cdclk_state(state);
12730         if (IS_ERR(cdclk_state))
12731                 return PTR_ERR(cdclk_state);
12732
12733         crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
12734                                                        cdclk_state);
12735
12736         return 0;
12737 }
12738
12739 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
12740                                    struct intel_crtc *crtc)
12741 {
12742         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12743         struct intel_crtc_state *crtc_state =
12744                 intel_atomic_get_new_crtc_state(state, crtc);
12745         bool mode_changed = needs_modeset(crtc_state);
12746         int ret;
12747
12748         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
12749             mode_changed && !crtc_state->hw.active)
12750                 crtc_state->update_wm_post = true;
12751
12752         if (mode_changed && crtc_state->hw.enable &&
12753             dev_priv->display.crtc_compute_clock &&
12754             !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
12755                 ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
12756                 if (ret)
12757                         return ret;
12758         }
12759
12760         /*
12761          * May need to update pipe gamma enable bits
12762          * when C8 planes are getting enabled/disabled.
12763          */
12764         if (c8_planes_changed(crtc_state))
12765                 crtc_state->uapi.color_mgmt_changed = true;
12766
12767         if (mode_changed || crtc_state->update_pipe ||
12768             crtc_state->uapi.color_mgmt_changed) {
12769                 ret = intel_color_check(crtc_state);
12770                 if (ret)
12771                         return ret;
12772         }
12773
12774         if (dev_priv->display.compute_pipe_wm) {
12775                 ret = dev_priv->display.compute_pipe_wm(crtc_state);
12776                 if (ret) {
12777                         drm_dbg_kms(&dev_priv->drm,
12778                                     "Target pipe watermarks are invalid\n");
12779                         return ret;
12780                 }
12781         }
12782
12783         if (dev_priv->display.compute_intermediate_wm) {
12784                 if (drm_WARN_ON(&dev_priv->drm,
12785                                 !dev_priv->display.compute_pipe_wm))
12786                         return 0;
12787
12788                 /*
12789                  * Calculate 'intermediate' watermarks that satisfy both the
12790                  * old state and the new state.  We can program these
12791                  * immediately.
12792                  */
12793                 ret = dev_priv->display.compute_intermediate_wm(crtc_state);
12794                 if (ret) {
12795                         drm_dbg_kms(&dev_priv->drm,
12796                                     "No valid intermediate pipe watermarks are possible\n");
12797                         return ret;
12798                 }
12799         }
12800
12801         if (INTEL_GEN(dev_priv) >= 9) {
12802                 if (mode_changed || crtc_state->update_pipe) {
12803                         ret = skl_update_scaler_crtc(crtc_state);
12804                         if (ret)
12805                                 return ret;
12806                 }
12807
12808                 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state);
12809                 if (ret)
12810                         return ret;
12811         }
12812
12813         if (HAS_IPS(dev_priv)) {
12814                 ret = hsw_compute_ips_config(crtc_state);
12815                 if (ret)
12816                         return ret;
12817         }
12818
12819         if (INTEL_GEN(dev_priv) >= 9 ||
12820             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
12821                 ret = hsw_compute_linetime_wm(state, crtc);
12822                 if (ret)
12823                         return ret;
12824
12825         }
12826
12827         if (!mode_changed)
12828                 intel_psr2_sel_fetch_update(state, crtc);
12829
12830         return 0;
12831 }
12832
12833 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12834 {
12835         struct intel_connector *connector;
12836         struct drm_connector_list_iter conn_iter;
12837
12838         drm_connector_list_iter_begin(dev, &conn_iter);
12839         for_each_intel_connector_iter(connector, &conn_iter) {
12840                 if (connector->base.state->crtc)
12841                         drm_connector_put(&connector->base);
12842
12843                 if (connector->base.encoder) {
12844                         connector->base.state->best_encoder =
12845                                 connector->base.encoder;
12846                         connector->base.state->crtc =
12847                                 connector->base.encoder->crtc;
12848
12849                         drm_connector_get(&connector->base);
12850                 } else {
12851                         connector->base.state->best_encoder = NULL;
12852                         connector->base.state->crtc = NULL;
12853                 }
12854         }
12855         drm_connector_list_iter_end(&conn_iter);
12856 }
12857
12858 static int
12859 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
12860                       struct intel_crtc_state *pipe_config)
12861 {
12862         struct drm_connector *connector = conn_state->connector;
12863         struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
12864         const struct drm_display_info *info = &connector->display_info;
12865         int bpp;
12866
12867         switch (conn_state->max_bpc) {
12868         case 6 ... 7:
12869                 bpp = 6 * 3;
12870                 break;
12871         case 8 ... 9:
12872                 bpp = 8 * 3;
12873                 break;
12874         case 10 ... 11:
12875                 bpp = 10 * 3;
12876                 break;
12877         case 12:
12878                 bpp = 12 * 3;
12879                 break;
12880         default:
12881                 return -EINVAL;
12882         }
12883
12884         if (bpp < pipe_config->pipe_bpp) {
12885                 drm_dbg_kms(&i915->drm,
12886                             "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
12887                             "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
12888                             connector->base.id, connector->name,
12889                             bpp, 3 * info->bpc,
12890                             3 * conn_state->max_requested_bpc,
12891                             pipe_config->pipe_bpp);
12892
12893                 pipe_config->pipe_bpp = bpp;
12894         }
12895
12896         return 0;
12897 }
12898
12899 static int
12900 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12901                           struct intel_crtc_state *pipe_config)
12902 {
12903         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12904         struct drm_atomic_state *state = pipe_config->uapi.state;
12905         struct drm_connector *connector;
12906         struct drm_connector_state *connector_state;
12907         int bpp, i;
12908
12909         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
12910             IS_CHERRYVIEW(dev_priv)))
12911                 bpp = 10*3;
12912         else if (INTEL_GEN(dev_priv) >= 5)
12913                 bpp = 12*3;
12914         else
12915                 bpp = 8*3;
12916
12917         pipe_config->pipe_bpp = bpp;
12918
12919         /* Clamp display bpp to connector max bpp */
12920         for_each_new_connector_in_state(state, connector, connector_state, i) {
12921                 int ret;
12922
12923                 if (connector_state->crtc != &crtc->base)
12924                         continue;
12925
12926                 ret = compute_sink_pipe_bpp(connector_state, pipe_config);
12927                 if (ret)
12928                         return ret;
12929         }
12930
12931         return 0;
12932 }
12933
12934 static void intel_dump_crtc_timings(struct drm_i915_private *i915,
12935                                     const struct drm_display_mode *mode)
12936 {
12937         drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, "
12938                     "type: 0x%x flags: 0x%x\n",
12939                     mode->crtc_clock,
12940                     mode->crtc_hdisplay, mode->crtc_hsync_start,
12941                     mode->crtc_hsync_end, mode->crtc_htotal,
12942                     mode->crtc_vdisplay, mode->crtc_vsync_start,
12943                     mode->crtc_vsync_end, mode->crtc_vtotal,
12944                     mode->type, mode->flags);
12945 }
12946
12947 static void
12948 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
12949                       const char *id, unsigned int lane_count,
12950                       const struct intel_link_m_n *m_n)
12951 {
12952         struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
12953
12954         drm_dbg_kms(&i915->drm,
12955                     "%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12956                     id, lane_count,
12957                     m_n->gmch_m, m_n->gmch_n,
12958                     m_n->link_m, m_n->link_n, m_n->tu);
12959 }
12960
12961 static void
12962 intel_dump_infoframe(struct drm_i915_private *dev_priv,
12963                      const union hdmi_infoframe *frame)
12964 {
12965         if (!drm_debug_enabled(DRM_UT_KMS))
12966                 return;
12967
12968         hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
12969 }
12970
12971 static void
12972 intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
12973                       const struct drm_dp_vsc_sdp *vsc)
12974 {
12975         if (!drm_debug_enabled(DRM_UT_KMS))
12976                 return;
12977
12978         drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
12979 }
12980
12981 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
12982
12983 static const char * const output_type_str[] = {
12984         OUTPUT_TYPE(UNUSED),
12985         OUTPUT_TYPE(ANALOG),
12986         OUTPUT_TYPE(DVO),
12987         OUTPUT_TYPE(SDVO),
12988         OUTPUT_TYPE(LVDS),
12989         OUTPUT_TYPE(TVOUT),
12990         OUTPUT_TYPE(HDMI),
12991         OUTPUT_TYPE(DP),
12992         OUTPUT_TYPE(EDP),
12993         OUTPUT_TYPE(DSI),
12994         OUTPUT_TYPE(DDI),
12995         OUTPUT_TYPE(DP_MST),
12996 };
12997
12998 #undef OUTPUT_TYPE
12999
13000 static void snprintf_output_types(char *buf, size_t len,
13001                                   unsigned int output_types)
13002 {
13003         char *str = buf;
13004         int i;
13005
13006         str[0] = '\0';
13007
13008         for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
13009                 int r;
13010
13011                 if ((output_types & BIT(i)) == 0)
13012                         continue;
13013
13014                 r = snprintf(str, len, "%s%s",
13015                              str != buf ? "," : "", output_type_str[i]);
13016                 if (r >= len)
13017                         break;
13018                 str += r;
13019                 len -= r;
13020
13021                 output_types &= ~BIT(i);
13022         }
13023
13024         WARN_ON_ONCE(output_types != 0);
13025 }
13026
13027 static const char * const output_format_str[] = {
13028         [INTEL_OUTPUT_FORMAT_INVALID] = "Invalid",
13029         [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
13030         [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
13031         [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
13032 };
13033
13034 static const char *output_formats(enum intel_output_format format)
13035 {
13036         if (format >= ARRAY_SIZE(output_format_str))
13037                 format = INTEL_OUTPUT_FORMAT_INVALID;
13038         return output_format_str[format];
13039 }
13040
13041 static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
13042 {
13043         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
13044         struct drm_i915_private *i915 = to_i915(plane->base.dev);
13045         const struct drm_framebuffer *fb = plane_state->hw.fb;
13046         struct drm_format_name_buf format_name;
13047
13048         if (!fb) {
13049                 drm_dbg_kms(&i915->drm,
13050                             "[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
13051                             plane->base.base.id, plane->base.name,
13052                             yesno(plane_state->uapi.visible));
13053                 return;
13054         }
13055
13056         drm_dbg_kms(&i915->drm,
13057                     "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s, visible: %s\n",
13058                     plane->base.base.id, plane->base.name,
13059                     fb->base.id, fb->width, fb->height,
13060                     drm_get_format_name(fb->format->format, &format_name),
13061                     yesno(plane_state->uapi.visible));
13062         drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n",
13063                     plane_state->hw.rotation, plane_state->scaler_id);
13064         if (plane_state->uapi.visible)
13065                 drm_dbg_kms(&i915->drm,
13066                             "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
13067                             DRM_RECT_FP_ARG(&plane_state->uapi.src),
13068                             DRM_RECT_ARG(&plane_state->uapi.dst));
13069 }
13070
13071 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
13072                                    struct intel_atomic_state *state,
13073                                    const char *context)
13074 {
13075         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
13076         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13077         const struct intel_plane_state *plane_state;
13078         struct intel_plane *plane;
13079         char buf[64];
13080         int i;
13081
13082         drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n",
13083                     crtc->base.base.id, crtc->base.name,
13084                     yesno(pipe_config->hw.enable), context);
13085
13086         if (!pipe_config->hw.enable)
13087                 goto dump_planes;
13088
13089         snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
13090         drm_dbg_kms(&dev_priv->drm,
13091                     "active: %s, output_types: %s (0x%x), output format: %s\n",
13092                     yesno(pipe_config->hw.active),
13093                     buf, pipe_config->output_types,
13094                     output_formats(pipe_config->output_format));
13095
13096         drm_dbg_kms(&dev_priv->drm,
13097                     "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
13098                     transcoder_name(pipe_config->cpu_transcoder),
13099                     pipe_config->pipe_bpp, pipe_config->dither);
13100
13101         drm_dbg_kms(&dev_priv->drm,
13102                     "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n",
13103                     transcoder_name(pipe_config->master_transcoder),
13104                     pipe_config->sync_mode_slaves_mask);
13105
13106         if (pipe_config->has_pch_encoder)
13107                 intel_dump_m_n_config(pipe_config, "fdi",
13108                                       pipe_config->fdi_lanes,
13109                                       &pipe_config->fdi_m_n);
13110
13111         if (intel_crtc_has_dp_encoder(pipe_config)) {
13112                 intel_dump_m_n_config(pipe_config, "dp m_n",
13113                                 pipe_config->lane_count, &pipe_config->dp_m_n);
13114                 if (pipe_config->has_drrs)
13115                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
13116                                               pipe_config->lane_count,
13117                                               &pipe_config->dp_m2_n2);
13118         }
13119
13120         drm_dbg_kms(&dev_priv->drm,
13121                     "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
13122                     pipe_config->has_audio, pipe_config->has_infoframe,
13123                     pipe_config->infoframes.enable);
13124
13125         if (pipe_config->infoframes.enable &
13126             intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
13127                 drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n",
13128                             pipe_config->infoframes.gcp);
13129         if (pipe_config->infoframes.enable &
13130             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
13131                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
13132         if (pipe_config->infoframes.enable &
13133             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
13134                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
13135         if (pipe_config->infoframes.enable &
13136             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
13137                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
13138         if (pipe_config->infoframes.enable &
13139             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
13140                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
13141         if (pipe_config->infoframes.enable &
13142             intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
13143                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
13144         if (pipe_config->infoframes.enable &
13145             intel_hdmi_infoframe_enable(DP_SDP_VSC))
13146                 intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
13147
13148         drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
13149         drm_mode_debug_printmodeline(&pipe_config->hw.mode);
13150         drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n");
13151         drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
13152         intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode);
13153         drm_dbg_kms(&dev_priv->drm,
13154                     "port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
13155                     pipe_config->port_clock,
13156                     pipe_config->pipe_src_w, pipe_config->pipe_src_h,
13157                     pipe_config->pixel_rate);
13158
13159         drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n",
13160                     pipe_config->linetime, pipe_config->ips_linetime);
13161
13162         if (INTEL_GEN(dev_priv) >= 9)
13163                 drm_dbg_kms(&dev_priv->drm,
13164                             "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
13165                             crtc->num_scalers,
13166                             pipe_config->scaler_state.scaler_users,
13167                             pipe_config->scaler_state.scaler_id);
13168
13169         if (HAS_GMCH(dev_priv))
13170                 drm_dbg_kms(&dev_priv->drm,
13171                             "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
13172                             pipe_config->gmch_pfit.control,
13173                             pipe_config->gmch_pfit.pgm_ratios,
13174                             pipe_config->gmch_pfit.lvds_border_bits);
13175         else
13176                 drm_dbg_kms(&dev_priv->drm,
13177                             "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
13178                             DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
13179                             enableddisabled(pipe_config->pch_pfit.enabled),
13180                             yesno(pipe_config->pch_pfit.force_thru));
13181
13182         drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i\n",
13183                     pipe_config->ips_enabled, pipe_config->double_wide);
13184
13185         intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
13186
13187         if (IS_CHERRYVIEW(dev_priv))
13188                 drm_dbg_kms(&dev_priv->drm,
13189                             "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
13190                             pipe_config->cgm_mode, pipe_config->gamma_mode,
13191                             pipe_config->gamma_enable, pipe_config->csc_enable);
13192         else
13193                 drm_dbg_kms(&dev_priv->drm,
13194                             "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
13195                             pipe_config->csc_mode, pipe_config->gamma_mode,
13196                             pipe_config->gamma_enable, pipe_config->csc_enable);
13197
13198         drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n",
13199                     transcoder_name(pipe_config->mst_master_transcoder));
13200
13201 dump_planes:
13202         if (!state)
13203                 return;
13204
13205         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
13206                 if (plane->pipe == crtc->pipe)
13207                         intel_dump_plane_state(plane_state);
13208         }
13209 }
13210
13211 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
13212 {
13213         struct drm_device *dev = state->base.dev;
13214         struct drm_connector *connector;
13215         struct drm_connector_list_iter conn_iter;
13216         unsigned int used_ports = 0;
13217         unsigned int used_mst_ports = 0;
13218         bool ret = true;
13219
13220         /*
13221          * We're going to peek into connector->state,
13222          * hence connection_mutex must be held.
13223          */
13224         drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
13225
13226         /*
13227          * Walk the connector list instead of the encoder
13228          * list to detect the problem on ddi platforms
13229          * where there's just one encoder per digital port.
13230          */
13231         drm_connector_list_iter_begin(dev, &conn_iter);
13232         drm_for_each_connector_iter(connector, &conn_iter) {
13233                 struct drm_connector_state *connector_state;
13234                 struct intel_encoder *encoder;
13235
13236                 connector_state =
13237                         drm_atomic_get_new_connector_state(&state->base,
13238                                                            connector);
13239                 if (!connector_state)
13240                         connector_state = connector->state;
13241
13242                 if (!connector_state->best_encoder)
13243                         continue;
13244
13245                 encoder = to_intel_encoder(connector_state->best_encoder);
13246
13247                 drm_WARN_ON(dev, !connector_state->crtc);
13248
13249                 switch (encoder->type) {
13250                 case INTEL_OUTPUT_DDI:
13251                         if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev))))
13252                                 break;
13253                         fallthrough;
13254                 case INTEL_OUTPUT_DP:
13255                 case INTEL_OUTPUT_HDMI:
13256                 case INTEL_OUTPUT_EDP:
13257                         /* the same port mustn't appear more than once */
13258                         if (used_ports & BIT(encoder->port))
13259                                 ret = false;
13260
13261                         used_ports |= BIT(encoder->port);
13262                         break;
13263                 case INTEL_OUTPUT_DP_MST:
13264                         used_mst_ports |=
13265                                 1 << encoder->port;
13266                         break;
13267                 default:
13268                         break;
13269                 }
13270         }
13271         drm_connector_list_iter_end(&conn_iter);
13272
13273         /* can't mix MST and SST/HDMI on the same port */
13274         if (used_ports & used_mst_ports)
13275                 return false;
13276
13277         return ret;
13278 }
13279
13280 static void
13281 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_crtc_state *crtc_state)
13282 {
13283         intel_crtc_copy_color_blobs(crtc_state);
13284 }
13285
13286 static void
13287 intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
13288 {
13289         crtc_state->hw.enable = crtc_state->uapi.enable;
13290         crtc_state->hw.active = crtc_state->uapi.active;
13291         crtc_state->hw.mode = crtc_state->uapi.mode;
13292         crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
13293         intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
13294 }
13295
13296 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
13297 {
13298         crtc_state->uapi.enable = crtc_state->hw.enable;
13299         crtc_state->uapi.active = crtc_state->hw.active;
13300         drm_WARN_ON(crtc_state->uapi.crtc->dev,
13301                     drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
13302
13303         crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
13304
13305         /* copy color blobs to uapi */
13306         drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
13307                                   crtc_state->hw.degamma_lut);
13308         drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
13309                                   crtc_state->hw.gamma_lut);
13310         drm_property_replace_blob(&crtc_state->uapi.ctm,
13311                                   crtc_state->hw.ctm);
13312 }
13313
13314 static int
13315 intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
13316 {
13317         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
13318         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13319         struct intel_crtc_state *saved_state;
13320
13321         saved_state = intel_crtc_state_alloc(crtc);
13322         if (!saved_state)
13323                 return -ENOMEM;
13324
13325         /* free the old crtc_state->hw members */
13326         intel_crtc_free_hw_state(crtc_state);
13327
13328         /* FIXME: before the switch to atomic started, a new pipe_config was
13329          * kzalloc'd. Code that depends on any field being zero should be
13330          * fixed, so that the crtc_state can be safely duplicated. For now,
13331          * only fields that are know to not cause problems are preserved. */
13332
13333         saved_state->uapi = crtc_state->uapi;
13334         saved_state->scaler_state = crtc_state->scaler_state;
13335         saved_state->shared_dpll = crtc_state->shared_dpll;
13336         saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
13337         memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
13338                sizeof(saved_state->icl_port_dplls));
13339         saved_state->crc_enabled = crtc_state->crc_enabled;
13340         if (IS_G4X(dev_priv) ||
13341             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13342                 saved_state->wm = crtc_state->wm;
13343
13344         memcpy(crtc_state, saved_state, sizeof(*crtc_state));
13345         kfree(saved_state);
13346
13347         intel_crtc_copy_uapi_to_hw_state(crtc_state);
13348
13349         return 0;
13350 }
13351
13352 static int
13353 intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
13354 {
13355         struct drm_crtc *crtc = pipe_config->uapi.crtc;
13356         struct drm_atomic_state *state = pipe_config->uapi.state;
13357         struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
13358         struct drm_connector *connector;
13359         struct drm_connector_state *connector_state;
13360         int base_bpp, ret, i;
13361         bool retry = true;
13362
13363         pipe_config->cpu_transcoder =
13364                 (enum transcoder) to_intel_crtc(crtc)->pipe;
13365
13366         /*
13367          * Sanitize sync polarity flags based on requested ones. If neither
13368          * positive or negative polarity is requested, treat this as meaning
13369          * negative polarity.
13370          */
13371         if (!(pipe_config->hw.adjusted_mode.flags &
13372               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
13373                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
13374
13375         if (!(pipe_config->hw.adjusted_mode.flags &
13376               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
13377                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
13378
13379         ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
13380                                         pipe_config);
13381         if (ret)
13382                 return ret;
13383
13384         base_bpp = pipe_config->pipe_bpp;
13385
13386         /*
13387          * Determine the real pipe dimensions. Note that stereo modes can
13388          * increase the actual pipe size due to the frame doubling and
13389          * insertion of additional space for blanks between the frame. This
13390          * is stored in the crtc timings. We use the requested mode to do this
13391          * computation to clearly distinguish it from the adjusted mode, which
13392          * can be changed by the connectors in the below retry loop.
13393          */
13394         drm_mode_get_hv_timing(&pipe_config->hw.mode,
13395                                &pipe_config->pipe_src_w,
13396                                &pipe_config->pipe_src_h);
13397
13398         for_each_new_connector_in_state(state, connector, connector_state, i) {
13399                 struct intel_encoder *encoder =
13400                         to_intel_encoder(connector_state->best_encoder);
13401
13402                 if (connector_state->crtc != crtc)
13403                         continue;
13404
13405                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
13406                         drm_dbg_kms(&i915->drm,
13407                                     "rejecting invalid cloning configuration\n");
13408                         return -EINVAL;
13409                 }
13410
13411                 /*
13412                  * Determine output_types before calling the .compute_config()
13413                  * hooks so that the hooks can use this information safely.
13414                  */
13415                 if (encoder->compute_output_type)
13416                         pipe_config->output_types |=
13417                                 BIT(encoder->compute_output_type(encoder, pipe_config,
13418                                                                  connector_state));
13419                 else
13420                         pipe_config->output_types |= BIT(encoder->type);
13421         }
13422
13423 encoder_retry:
13424         /* Ensure the port clock defaults are reset when retrying. */
13425         pipe_config->port_clock = 0;
13426         pipe_config->pixel_multiplier = 1;
13427
13428         /* Fill in default crtc timings, allow encoders to overwrite them. */
13429         drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,
13430                               CRTC_STEREO_DOUBLE);
13431
13432         /* Pass our mode to the connectors and the CRTC to give them a chance to
13433          * adjust it according to limitations or connector properties, and also
13434          * a chance to reject the mode entirely.
13435          */
13436         for_each_new_connector_in_state(state, connector, connector_state, i) {
13437                 struct intel_encoder *encoder =
13438                         to_intel_encoder(connector_state->best_encoder);
13439
13440                 if (connector_state->crtc != crtc)
13441                         continue;
13442
13443                 ret = encoder->compute_config(encoder, pipe_config,
13444                                               connector_state);
13445                 if (ret < 0) {
13446                         if (ret != -EDEADLK)
13447                                 drm_dbg_kms(&i915->drm,
13448                                             "Encoder config failure: %d\n",
13449                                             ret);
13450                         return ret;
13451                 }
13452         }
13453
13454         /* Set default port clock if not overwritten by the encoder. Needs to be
13455          * done afterwards in case the encoder adjusts the mode. */
13456         if (!pipe_config->port_clock)
13457                 pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
13458                         * pipe_config->pixel_multiplier;
13459
13460         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
13461         if (ret == -EDEADLK)
13462                 return ret;
13463         if (ret < 0) {
13464                 drm_dbg_kms(&i915->drm, "CRTC fixup failed\n");
13465                 return ret;
13466         }
13467
13468         if (ret == RETRY) {
13469                 if (drm_WARN(&i915->drm, !retry,
13470                              "loop in pipe configuration computation\n"))
13471                         return -EINVAL;
13472
13473                 drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n");
13474                 retry = false;
13475                 goto encoder_retry;
13476         }
13477
13478         /* Dithering seems to not pass-through bits correctly when it should, so
13479          * only enable it on 6bpc panels and when its not a compliance
13480          * test requesting 6bpc video pattern.
13481          */
13482         pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
13483                 !pipe_config->dither_force_disable;
13484         drm_dbg_kms(&i915->drm,
13485                     "hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
13486                     base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
13487
13488         return 0;
13489 }
13490
13491 static int
13492 intel_modeset_pipe_config_late(struct intel_crtc_state *crtc_state)
13493 {
13494         struct intel_atomic_state *state =
13495                 to_intel_atomic_state(crtc_state->uapi.state);
13496         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
13497         struct drm_connector_state *conn_state;
13498         struct drm_connector *connector;
13499         int i;
13500
13501         for_each_new_connector_in_state(&state->base, connector,
13502                                         conn_state, i) {
13503                 struct intel_encoder *encoder =
13504                         to_intel_encoder(conn_state->best_encoder);
13505                 int ret;
13506
13507                 if (conn_state->crtc != &crtc->base ||
13508                     !encoder->compute_config_late)
13509                         continue;
13510
13511                 ret = encoder->compute_config_late(encoder, crtc_state,
13512                                                    conn_state);
13513                 if (ret)
13514                         return ret;
13515         }
13516
13517         return 0;
13518 }
13519
13520 bool intel_fuzzy_clock_check(int clock1, int clock2)
13521 {
13522         int diff;
13523
13524         if (clock1 == clock2)
13525                 return true;
13526
13527         if (!clock1 || !clock2)
13528                 return false;
13529
13530         diff = abs(clock1 - clock2);
13531
13532         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
13533                 return true;
13534
13535         return false;
13536 }
13537
13538 static bool
13539 intel_compare_m_n(unsigned int m, unsigned int n,
13540                   unsigned int m2, unsigned int n2,
13541                   bool exact)
13542 {
13543         if (m == m2 && n == n2)
13544                 return true;
13545
13546         if (exact || !m || !n || !m2 || !n2)
13547                 return false;
13548
13549         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
13550
13551         if (n > n2) {
13552                 while (n > n2) {
13553                         m2 <<= 1;
13554                         n2 <<= 1;
13555                 }
13556         } else if (n < n2) {
13557                 while (n < n2) {
13558                         m <<= 1;
13559                         n <<= 1;
13560                 }
13561         }
13562
13563         if (n != n2)
13564                 return false;
13565
13566         return intel_fuzzy_clock_check(m, m2);
13567 }
13568
13569 static bool
13570 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
13571                        const struct intel_link_m_n *m2_n2,
13572                        bool exact)
13573 {
13574         return m_n->tu == m2_n2->tu &&
13575                 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
13576                                   m2_n2->gmch_m, m2_n2->gmch_n, exact) &&
13577                 intel_compare_m_n(m_n->link_m, m_n->link_n,
13578                                   m2_n2->link_m, m2_n2->link_n, exact);
13579 }
13580
13581 static bool
13582 intel_compare_infoframe(const union hdmi_infoframe *a,
13583                         const union hdmi_infoframe *b)
13584 {
13585         return memcmp(a, b, sizeof(*a)) == 0;
13586 }
13587
13588 static bool
13589 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
13590                          const struct drm_dp_vsc_sdp *b)
13591 {
13592         return memcmp(a, b, sizeof(*a)) == 0;
13593 }
13594
13595 static void
13596 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
13597                                bool fastset, const char *name,
13598                                const union hdmi_infoframe *a,
13599                                const union hdmi_infoframe *b)
13600 {
13601         if (fastset) {
13602                 if (!drm_debug_enabled(DRM_UT_KMS))
13603                         return;
13604
13605                 drm_dbg_kms(&dev_priv->drm,
13606                             "fastset mismatch in %s infoframe\n", name);
13607                 drm_dbg_kms(&dev_priv->drm, "expected:\n");
13608                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
13609                 drm_dbg_kms(&dev_priv->drm, "found:\n");
13610                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
13611         } else {
13612                 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name);
13613                 drm_err(&dev_priv->drm, "expected:\n");
13614                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
13615                 drm_err(&dev_priv->drm, "found:\n");
13616                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
13617         }
13618 }
13619
13620 static void
13621 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
13622                                 bool fastset, const char *name,
13623                                 const struct drm_dp_vsc_sdp *a,
13624                                 const struct drm_dp_vsc_sdp *b)
13625 {
13626         if (fastset) {
13627                 if (!drm_debug_enabled(DRM_UT_KMS))
13628                         return;
13629
13630                 drm_dbg_kms(&dev_priv->drm,
13631                             "fastset mismatch in %s dp sdp\n", name);
13632                 drm_dbg_kms(&dev_priv->drm, "expected:\n");
13633                 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
13634                 drm_dbg_kms(&dev_priv->drm, "found:\n");
13635                 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
13636         } else {
13637                 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name);
13638                 drm_err(&dev_priv->drm, "expected:\n");
13639                 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
13640                 drm_err(&dev_priv->drm, "found:\n");
13641                 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
13642         }
13643 }
13644
13645 static void __printf(4, 5)
13646 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
13647                      const char *name, const char *format, ...)
13648 {
13649         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
13650         struct va_format vaf;
13651         va_list args;
13652
13653         va_start(args, format);
13654         vaf.fmt = format;
13655         vaf.va = &args;
13656
13657         if (fastset)
13658                 drm_dbg_kms(&i915->drm,
13659                             "[CRTC:%d:%s] fastset mismatch in %s %pV\n",
13660                             crtc->base.base.id, crtc->base.name, name, &vaf);
13661         else
13662                 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n",
13663                         crtc->base.base.id, crtc->base.name, name, &vaf);
13664
13665         va_end(args);
13666 }
13667
13668 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
13669 {
13670         if (dev_priv->params.fastboot != -1)
13671                 return dev_priv->params.fastboot;
13672
13673         /* Enable fastboot by default on Skylake and newer */
13674         if (INTEL_GEN(dev_priv) >= 9)
13675                 return true;
13676
13677         /* Enable fastboot by default on VLV and CHV */
13678         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13679                 return true;
13680
13681         /* Disabled by default on all others */
13682         return false;
13683 }
13684
13685 static bool
13686 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
13687                           const struct intel_crtc_state *pipe_config,
13688                           bool fastset)
13689 {
13690         struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
13691         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
13692         bool ret = true;
13693         u32 bp_gamma = 0;
13694         bool fixup_inherited = fastset &&
13695                 current_config->inherited && !pipe_config->inherited;
13696
13697         if (fixup_inherited && !fastboot_enabled(dev_priv)) {
13698                 drm_dbg_kms(&dev_priv->drm,
13699                             "initial modeset and fastboot not set\n");
13700                 ret = false;
13701         }
13702
13703 #define PIPE_CONF_CHECK_X(name) do { \
13704         if (current_config->name != pipe_config->name) { \
13705                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13706                                      "(expected 0x%08x, found 0x%08x)", \
13707                                      current_config->name, \
13708                                      pipe_config->name); \
13709                 ret = false; \
13710         } \
13711 } while (0)
13712
13713 #define PIPE_CONF_CHECK_I(name) do { \
13714         if (current_config->name != pipe_config->name) { \
13715                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13716                                      "(expected %i, found %i)", \
13717                                      current_config->name, \
13718                                      pipe_config->name); \
13719                 ret = false; \
13720         } \
13721 } while (0)
13722
13723 #define PIPE_CONF_CHECK_BOOL(name) do { \
13724         if (current_config->name != pipe_config->name) { \
13725                 pipe_config_mismatch(fastset, crtc,  __stringify(name), \
13726                                      "(expected %s, found %s)", \
13727                                      yesno(current_config->name), \
13728                                      yesno(pipe_config->name)); \
13729                 ret = false; \
13730         } \
13731 } while (0)
13732
13733 /*
13734  * Checks state where we only read out the enabling, but not the entire
13735  * state itself (like full infoframes or ELD for audio). These states
13736  * require a full modeset on bootup to fix up.
13737  */
13738 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
13739         if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
13740                 PIPE_CONF_CHECK_BOOL(name); \
13741         } else { \
13742                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13743                                      "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
13744                                      yesno(current_config->name), \
13745                                      yesno(pipe_config->name)); \
13746                 ret = false; \
13747         } \
13748 } while (0)
13749
13750 #define PIPE_CONF_CHECK_P(name) do { \
13751         if (current_config->name != pipe_config->name) { \
13752                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13753                                      "(expected %p, found %p)", \
13754                                      current_config->name, \
13755                                      pipe_config->name); \
13756                 ret = false; \
13757         } \
13758 } while (0)
13759
13760 #define PIPE_CONF_CHECK_M_N(name) do { \
13761         if (!intel_compare_link_m_n(&current_config->name, \
13762                                     &pipe_config->name,\
13763                                     !fastset)) { \
13764                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13765                                      "(expected tu %i gmch %i/%i link %i/%i, " \
13766                                      "found tu %i, gmch %i/%i link %i/%i)", \
13767                                      current_config->name.tu, \
13768                                      current_config->name.gmch_m, \
13769                                      current_config->name.gmch_n, \
13770                                      current_config->name.link_m, \
13771                                      current_config->name.link_n, \
13772                                      pipe_config->name.tu, \
13773                                      pipe_config->name.gmch_m, \
13774                                      pipe_config->name.gmch_n, \
13775                                      pipe_config->name.link_m, \
13776                                      pipe_config->name.link_n); \
13777                 ret = false; \
13778         } \
13779 } while (0)
13780
13781 /* This is required for BDW+ where there is only one set of registers for
13782  * switching between high and low RR.
13783  * This macro can be used whenever a comparison has to be made between one
13784  * hw state and multiple sw state variables.
13785  */
13786 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
13787         if (!intel_compare_link_m_n(&current_config->name, \
13788                                     &pipe_config->name, !fastset) && \
13789             !intel_compare_link_m_n(&current_config->alt_name, \
13790                                     &pipe_config->name, !fastset)) { \
13791                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13792                                      "(expected tu %i gmch %i/%i link %i/%i, " \
13793                                      "or tu %i gmch %i/%i link %i/%i, " \
13794                                      "found tu %i, gmch %i/%i link %i/%i)", \
13795                                      current_config->name.tu, \
13796                                      current_config->name.gmch_m, \
13797                                      current_config->name.gmch_n, \
13798                                      current_config->name.link_m, \
13799                                      current_config->name.link_n, \
13800                                      current_config->alt_name.tu, \
13801                                      current_config->alt_name.gmch_m, \
13802                                      current_config->alt_name.gmch_n, \
13803                                      current_config->alt_name.link_m, \
13804                                      current_config->alt_name.link_n, \
13805                                      pipe_config->name.tu, \
13806                                      pipe_config->name.gmch_m, \
13807                                      pipe_config->name.gmch_n, \
13808                                      pipe_config->name.link_m, \
13809                                      pipe_config->name.link_n); \
13810                 ret = false; \
13811         } \
13812 } while (0)
13813
13814 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
13815         if ((current_config->name ^ pipe_config->name) & (mask)) { \
13816                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13817                                      "(%x) (expected %i, found %i)", \
13818                                      (mask), \
13819                                      current_config->name & (mask), \
13820                                      pipe_config->name & (mask)); \
13821                 ret = false; \
13822         } \
13823 } while (0)
13824
13825 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
13826         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13827                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13828                                      "(expected %i, found %i)", \
13829                                      current_config->name, \
13830                                      pipe_config->name); \
13831                 ret = false; \
13832         } \
13833 } while (0)
13834
13835 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
13836         if (!intel_compare_infoframe(&current_config->infoframes.name, \
13837                                      &pipe_config->infoframes.name)) { \
13838                 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
13839                                                &current_config->infoframes.name, \
13840                                                &pipe_config->infoframes.name); \
13841                 ret = false; \
13842         } \
13843 } while (0)
13844
13845 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
13846         if (!current_config->has_psr && !pipe_config->has_psr && \
13847             !intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \
13848                                       &pipe_config->infoframes.name)) { \
13849                 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
13850                                                 &current_config->infoframes.name, \
13851                                                 &pipe_config->infoframes.name); \
13852                 ret = false; \
13853         } \
13854 } while (0)
13855
13856 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
13857         if (current_config->name1 != pipe_config->name1) { \
13858                 pipe_config_mismatch(fastset, crtc, __stringify(name1), \
13859                                 "(expected %i, found %i, won't compare lut values)", \
13860                                 current_config->name1, \
13861                                 pipe_config->name1); \
13862                 ret = false;\
13863         } else { \
13864                 if (!intel_color_lut_equal(current_config->name2, \
13865                                         pipe_config->name2, pipe_config->name1, \
13866                                         bit_precision)) { \
13867                         pipe_config_mismatch(fastset, crtc, __stringify(name2), \
13868                                         "hw_state doesn't match sw_state"); \
13869                         ret = false; \
13870                 } \
13871         } \
13872 } while (0)
13873
13874 #define PIPE_CONF_QUIRK(quirk) \
13875         ((current_config->quirks | pipe_config->quirks) & (quirk))
13876
13877         PIPE_CONF_CHECK_I(cpu_transcoder);
13878
13879         PIPE_CONF_CHECK_BOOL(has_pch_encoder);
13880         PIPE_CONF_CHECK_I(fdi_lanes);
13881         PIPE_CONF_CHECK_M_N(fdi_m_n);
13882
13883         PIPE_CONF_CHECK_I(lane_count);
13884         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13885
13886         if (INTEL_GEN(dev_priv) < 8) {
13887                 PIPE_CONF_CHECK_M_N(dp_m_n);
13888
13889                 if (current_config->has_drrs)
13890                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
13891         } else
13892                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13893
13894         PIPE_CONF_CHECK_X(output_types);
13895
13896         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
13897         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
13898         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
13899         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
13900         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
13901         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
13902
13903         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
13904         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
13905         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
13906         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
13907         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
13908         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
13909
13910         PIPE_CONF_CHECK_I(pixel_multiplier);
13911         PIPE_CONF_CHECK_I(output_format);
13912         PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
13913         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
13914             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13915                 PIPE_CONF_CHECK_BOOL(limited_color_range);
13916
13917         PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
13918         PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
13919         PIPE_CONF_CHECK_BOOL(has_infoframe);
13920         PIPE_CONF_CHECK_BOOL(fec_enable);
13921
13922         PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
13923
13924         PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13925                               DRM_MODE_FLAG_INTERLACE);
13926
13927         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13928                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13929                                       DRM_MODE_FLAG_PHSYNC);
13930                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13931                                       DRM_MODE_FLAG_NHSYNC);
13932                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13933                                       DRM_MODE_FLAG_PVSYNC);
13934                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13935                                       DRM_MODE_FLAG_NVSYNC);
13936         }
13937
13938         PIPE_CONF_CHECK_X(gmch_pfit.control);
13939         /* pfit ratios are autocomputed by the hw on gen4+ */
13940         if (INTEL_GEN(dev_priv) < 4)
13941                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13942         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13943
13944         /*
13945          * Changing the EDP transcoder input mux
13946          * (A_ONOFF vs. A_ON) requires a full modeset.
13947          */
13948         PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
13949
13950         if (!fastset) {
13951                 PIPE_CONF_CHECK_I(pipe_src_w);
13952                 PIPE_CONF_CHECK_I(pipe_src_h);
13953
13954                 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
13955                 if (current_config->pch_pfit.enabled) {
13956                         PIPE_CONF_CHECK_I(pch_pfit.dst.x1);
13957                         PIPE_CONF_CHECK_I(pch_pfit.dst.y1);
13958                         PIPE_CONF_CHECK_I(pch_pfit.dst.x2);
13959                         PIPE_CONF_CHECK_I(pch_pfit.dst.y2);
13960                 }
13961
13962                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13963                 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
13964
13965                 PIPE_CONF_CHECK_X(gamma_mode);
13966                 if (IS_CHERRYVIEW(dev_priv))
13967                         PIPE_CONF_CHECK_X(cgm_mode);
13968                 else
13969                         PIPE_CONF_CHECK_X(csc_mode);
13970                 PIPE_CONF_CHECK_BOOL(gamma_enable);
13971                 PIPE_CONF_CHECK_BOOL(csc_enable);
13972
13973                 PIPE_CONF_CHECK_I(linetime);
13974                 PIPE_CONF_CHECK_I(ips_linetime);
13975
13976                 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
13977                 if (bp_gamma)
13978                         PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
13979         }
13980
13981         PIPE_CONF_CHECK_BOOL(double_wide);
13982
13983         PIPE_CONF_CHECK_P(shared_dpll);
13984         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13985         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13986         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13987         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13988         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13989         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13990         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13991         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13992         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13993         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
13994         PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
13995         PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
13996         PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
13997         PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
13998         PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
13999         PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
14000         PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
14001         PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
14002         PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
14003         PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
14004         PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
14005         PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
14006         PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
14007         PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
14008         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
14009         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
14010         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
14011         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
14012         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
14013         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
14014         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
14015
14016         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
14017         PIPE_CONF_CHECK_X(dsi_pll.div);
14018
14019         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
14020                 PIPE_CONF_CHECK_I(pipe_bpp);
14021
14022         PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
14023         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
14024
14025         PIPE_CONF_CHECK_I(min_voltage_level);
14026
14027         PIPE_CONF_CHECK_X(infoframes.enable);
14028         PIPE_CONF_CHECK_X(infoframes.gcp);
14029         PIPE_CONF_CHECK_INFOFRAME(avi);
14030         PIPE_CONF_CHECK_INFOFRAME(spd);
14031         PIPE_CONF_CHECK_INFOFRAME(hdmi);
14032         PIPE_CONF_CHECK_INFOFRAME(drm);
14033         PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
14034
14035         PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
14036         PIPE_CONF_CHECK_I(master_transcoder);
14037
14038         PIPE_CONF_CHECK_I(dsc.compression_enable);
14039         PIPE_CONF_CHECK_I(dsc.dsc_split);
14040         PIPE_CONF_CHECK_I(dsc.compressed_bpp);
14041
14042         PIPE_CONF_CHECK_I(mst_master_transcoder);
14043
14044 #undef PIPE_CONF_CHECK_X
14045 #undef PIPE_CONF_CHECK_I
14046 #undef PIPE_CONF_CHECK_BOOL
14047 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
14048 #undef PIPE_CONF_CHECK_P
14049 #undef PIPE_CONF_CHECK_FLAGS
14050 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
14051 #undef PIPE_CONF_CHECK_COLOR_LUT
14052 #undef PIPE_CONF_QUIRK
14053
14054         return ret;
14055 }
14056
14057 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
14058                                            const struct intel_crtc_state *pipe_config)
14059 {
14060         if (pipe_config->has_pch_encoder) {
14061                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
14062                                                             &pipe_config->fdi_m_n);
14063                 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
14064
14065                 /*
14066                  * FDI already provided one idea for the dotclock.
14067                  * Yell if the encoder disagrees.
14068                  */
14069                 drm_WARN(&dev_priv->drm,
14070                          !intel_fuzzy_clock_check(fdi_dotclock, dotclock),
14071                          "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
14072                          fdi_dotclock, dotclock);
14073         }
14074 }
14075
14076 static void verify_wm_state(struct intel_crtc *crtc,
14077                             struct intel_crtc_state *new_crtc_state)
14078 {
14079         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14080         struct skl_hw_state {
14081                 struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
14082                 struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
14083                 struct skl_pipe_wm wm;
14084         } *hw;
14085         struct skl_pipe_wm *sw_wm;
14086         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
14087         u8 hw_enabled_slices;
14088         const enum pipe pipe = crtc->pipe;
14089         int plane, level, max_level = ilk_wm_max_level(dev_priv);
14090
14091         if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active)
14092                 return;
14093
14094         hw = kzalloc(sizeof(*hw), GFP_KERNEL);
14095         if (!hw)
14096                 return;
14097
14098         skl_pipe_wm_get_hw_state(crtc, &hw->wm);
14099         sw_wm = &new_crtc_state->wm.skl.optimal;
14100
14101         skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
14102
14103         hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
14104
14105         if (INTEL_GEN(dev_priv) >= 11 &&
14106             hw_enabled_slices != dev_priv->dbuf.enabled_slices)
14107                 drm_err(&dev_priv->drm,
14108                         "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n",
14109                         dev_priv->dbuf.enabled_slices,
14110                         hw_enabled_slices);
14111
14112         /* planes */
14113         for_each_universal_plane(dev_priv, pipe, plane) {
14114                 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
14115
14116                 hw_plane_wm = &hw->wm.planes[plane];
14117                 sw_plane_wm = &sw_wm->planes[plane];
14118
14119                 /* Watermarks */
14120                 for (level = 0; level <= max_level; level++) {
14121                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
14122                                                 &sw_plane_wm->wm[level]) ||
14123                             (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
14124                                                                &sw_plane_wm->sagv_wm0)))
14125                                 continue;
14126
14127                         drm_err(&dev_priv->drm,
14128                                 "mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14129                                 pipe_name(pipe), plane + 1, level,
14130                                 sw_plane_wm->wm[level].plane_en,
14131                                 sw_plane_wm->wm[level].plane_res_b,
14132                                 sw_plane_wm->wm[level].plane_res_l,
14133                                 hw_plane_wm->wm[level].plane_en,
14134                                 hw_plane_wm->wm[level].plane_res_b,
14135                                 hw_plane_wm->wm[level].plane_res_l);
14136                 }
14137
14138                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
14139                                          &sw_plane_wm->trans_wm)) {
14140                         drm_err(&dev_priv->drm,
14141                                 "mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14142                                 pipe_name(pipe), plane + 1,
14143                                 sw_plane_wm->trans_wm.plane_en,
14144                                 sw_plane_wm->trans_wm.plane_res_b,
14145                                 sw_plane_wm->trans_wm.plane_res_l,
14146                                 hw_plane_wm->trans_wm.plane_en,
14147                                 hw_plane_wm->trans_wm.plane_res_b,
14148                                 hw_plane_wm->trans_wm.plane_res_l);
14149                 }
14150
14151                 /* DDB */
14152                 hw_ddb_entry = &hw->ddb_y[plane];
14153                 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane];
14154
14155                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
14156                         drm_err(&dev_priv->drm,
14157                                 "mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
14158                                 pipe_name(pipe), plane + 1,
14159                                 sw_ddb_entry->start, sw_ddb_entry->end,
14160                                 hw_ddb_entry->start, hw_ddb_entry->end);
14161                 }
14162         }
14163
14164         /*
14165          * cursor
14166          * If the cursor plane isn't active, we may not have updated it's ddb
14167          * allocation. In that case since the ddb allocation will be updated
14168          * once the plane becomes visible, we can skip this check
14169          */
14170         if (1) {
14171                 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
14172
14173                 hw_plane_wm = &hw->wm.planes[PLANE_CURSOR];
14174                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
14175
14176                 /* Watermarks */
14177                 for (level = 0; level <= max_level; level++) {
14178                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
14179                                                 &sw_plane_wm->wm[level]) ||
14180                             (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
14181                                                                &sw_plane_wm->sagv_wm0)))
14182                                 continue;
14183
14184                         drm_err(&dev_priv->drm,
14185                                 "mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14186                                 pipe_name(pipe), level,
14187                                 sw_plane_wm->wm[level].plane_en,
14188                                 sw_plane_wm->wm[level].plane_res_b,
14189                                 sw_plane_wm->wm[level].plane_res_l,
14190                                 hw_plane_wm->wm[level].plane_en,
14191                                 hw_plane_wm->wm[level].plane_res_b,
14192                                 hw_plane_wm->wm[level].plane_res_l);
14193                 }
14194
14195                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
14196                                          &sw_plane_wm->trans_wm)) {
14197                         drm_err(&dev_priv->drm,
14198                                 "mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14199                                 pipe_name(pipe),
14200                                 sw_plane_wm->trans_wm.plane_en,
14201                                 sw_plane_wm->trans_wm.plane_res_b,
14202                                 sw_plane_wm->trans_wm.plane_res_l,
14203                                 hw_plane_wm->trans_wm.plane_en,
14204                                 hw_plane_wm->trans_wm.plane_res_b,
14205                                 hw_plane_wm->trans_wm.plane_res_l);
14206                 }
14207
14208                 /* DDB */
14209                 hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR];
14210                 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
14211
14212                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
14213                         drm_err(&dev_priv->drm,
14214                                 "mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
14215                                 pipe_name(pipe),
14216                                 sw_ddb_entry->start, sw_ddb_entry->end,
14217                                 hw_ddb_entry->start, hw_ddb_entry->end);
14218                 }
14219         }
14220
14221         kfree(hw);
14222 }
14223
14224 static void
14225 verify_connector_state(struct intel_atomic_state *state,
14226                        struct intel_crtc *crtc)
14227 {
14228         struct drm_connector *connector;
14229         struct drm_connector_state *new_conn_state;
14230         int i;
14231
14232         for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) {
14233                 struct drm_encoder *encoder = connector->encoder;
14234                 struct intel_crtc_state *crtc_state = NULL;
14235
14236                 if (new_conn_state->crtc != &crtc->base)
14237                         continue;
14238
14239                 if (crtc)
14240                         crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
14241
14242                 intel_connector_verify_state(crtc_state, new_conn_state);
14243
14244                 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
14245                      "connector's atomic encoder doesn't match legacy encoder\n");
14246         }
14247 }
14248
14249 static void
14250 verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state)
14251 {
14252         struct intel_encoder *encoder;
14253         struct drm_connector *connector;
14254         struct drm_connector_state *old_conn_state, *new_conn_state;
14255         int i;
14256
14257         for_each_intel_encoder(&dev_priv->drm, encoder) {
14258                 bool enabled = false, found = false;
14259                 enum pipe pipe;
14260
14261                 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n",
14262                             encoder->base.base.id,
14263                             encoder->base.name);
14264
14265                 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,
14266                                                    new_conn_state, i) {
14267                         if (old_conn_state->best_encoder == &encoder->base)
14268                                 found = true;
14269
14270                         if (new_conn_state->best_encoder != &encoder->base)
14271                                 continue;
14272                         found = enabled = true;
14273
14274                         I915_STATE_WARN(new_conn_state->crtc !=
14275                                         encoder->base.crtc,
14276                              "connector's crtc doesn't match encoder crtc\n");
14277                 }
14278
14279                 if (!found)
14280                         continue;
14281
14282                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
14283                      "encoder's enabled state mismatch "
14284                      "(expected %i, found %i)\n",
14285                      !!encoder->base.crtc, enabled);
14286
14287                 if (!encoder->base.crtc) {
14288                         bool active;
14289
14290                         active = encoder->get_hw_state(encoder, &pipe);
14291                         I915_STATE_WARN(active,
14292                              "encoder detached but still enabled on pipe %c.\n",
14293                              pipe_name(pipe));
14294                 }
14295         }
14296 }
14297
14298 static void
14299 verify_crtc_state(struct intel_crtc *crtc,
14300                   struct intel_crtc_state *old_crtc_state,
14301                   struct intel_crtc_state *new_crtc_state)
14302 {
14303         struct drm_device *dev = crtc->base.dev;
14304         struct drm_i915_private *dev_priv = to_i915(dev);
14305         struct intel_encoder *encoder;
14306         struct intel_crtc_state *pipe_config = old_crtc_state;
14307         struct drm_atomic_state *state = old_crtc_state->uapi.state;
14308
14309         __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
14310         intel_crtc_free_hw_state(old_crtc_state);
14311         intel_crtc_state_reset(old_crtc_state, crtc);
14312         old_crtc_state->uapi.state = state;
14313
14314         drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id,
14315                     crtc->base.name);
14316
14317         pipe_config->hw.enable = new_crtc_state->hw.enable;
14318
14319         pipe_config->hw.active =
14320                 dev_priv->display.get_pipe_config(crtc, pipe_config);
14321
14322         /* we keep both pipes enabled on 830 */
14323         if (IS_I830(dev_priv) && pipe_config->hw.active)
14324                 pipe_config->hw.active = new_crtc_state->hw.active;
14325
14326         I915_STATE_WARN(new_crtc_state->hw.active != pipe_config->hw.active,
14327                         "crtc active state doesn't match with hw state "
14328                         "(expected %i, found %i)\n",
14329                         new_crtc_state->hw.active, pipe_config->hw.active);
14330
14331         I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,
14332                         "transitional active state does not match atomic hw state "
14333                         "(expected %i, found %i)\n",
14334                         new_crtc_state->hw.active, crtc->active);
14335
14336         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14337                 enum pipe pipe;
14338                 bool active;
14339
14340                 active = encoder->get_hw_state(encoder, &pipe);
14341                 I915_STATE_WARN(active != new_crtc_state->hw.active,
14342                                 "[ENCODER:%i] active %i with crtc active %i\n",
14343                                 encoder->base.base.id, active,
14344                                 new_crtc_state->hw.active);
14345
14346                 I915_STATE_WARN(active && crtc->pipe != pipe,
14347                                 "Encoder connected to wrong pipe %c\n",
14348                                 pipe_name(pipe));
14349
14350                 if (active)
14351                         encoder->get_config(encoder, pipe_config);
14352         }
14353
14354         intel_crtc_compute_pixel_rate(pipe_config);
14355
14356         if (!new_crtc_state->hw.active)
14357                 return;
14358
14359         intel_pipe_config_sanity_check(dev_priv, pipe_config);
14360
14361         if (!intel_pipe_config_compare(new_crtc_state,
14362                                        pipe_config, false)) {
14363                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
14364                 intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
14365                 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
14366         }
14367 }
14368
14369 static void
14370 intel_verify_planes(struct intel_atomic_state *state)
14371 {
14372         struct intel_plane *plane;
14373         const struct intel_plane_state *plane_state;
14374         int i;
14375
14376         for_each_new_intel_plane_in_state(state, plane,
14377                                           plane_state, i)
14378                 assert_plane(plane, plane_state->planar_slave ||
14379                              plane_state->uapi.visible);
14380 }
14381
14382 static void
14383 verify_single_dpll_state(struct drm_i915_private *dev_priv,
14384                          struct intel_shared_dpll *pll,
14385                          struct intel_crtc *crtc,
14386                          struct intel_crtc_state *new_crtc_state)
14387 {
14388         struct intel_dpll_hw_state dpll_hw_state;
14389         unsigned int crtc_mask;
14390         bool active;
14391
14392         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
14393
14394         drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name);
14395
14396         active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
14397
14398         if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
14399                 I915_STATE_WARN(!pll->on && pll->active_mask,
14400                      "pll in active use but not on in sw tracking\n");
14401                 I915_STATE_WARN(pll->on && !pll->active_mask,
14402                      "pll is on but not used by any active crtc\n");
14403                 I915_STATE_WARN(pll->on != active,
14404                      "pll on state mismatch (expected %i, found %i)\n",
14405                      pll->on, active);
14406         }
14407
14408         if (!crtc) {
14409                 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
14410                                 "more active pll users than references: %x vs %x\n",
14411                                 pll->active_mask, pll->state.crtc_mask);
14412
14413                 return;
14414         }
14415
14416         crtc_mask = drm_crtc_mask(&crtc->base);
14417
14418         if (new_crtc_state->hw.active)
14419                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
14420                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
14421                                 pipe_name(crtc->pipe), pll->active_mask);
14422         else
14423                 I915_STATE_WARN(pll->active_mask & crtc_mask,
14424                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
14425                                 pipe_name(crtc->pipe), pll->active_mask);
14426
14427         I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
14428                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
14429                         crtc_mask, pll->state.crtc_mask);
14430
14431         I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
14432                                           &dpll_hw_state,
14433                                           sizeof(dpll_hw_state)),
14434                         "pll hw state mismatch\n");
14435 }
14436
14437 static void
14438 verify_shared_dpll_state(struct intel_crtc *crtc,
14439                          struct intel_crtc_state *old_crtc_state,
14440                          struct intel_crtc_state *new_crtc_state)
14441 {
14442         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14443
14444         if (new_crtc_state->shared_dpll)
14445                 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state);
14446
14447         if (old_crtc_state->shared_dpll &&
14448             old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
14449                 unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
14450                 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
14451
14452                 I915_STATE_WARN(pll->active_mask & crtc_mask,
14453                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
14454                                 pipe_name(crtc->pipe));
14455                 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
14456                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
14457                                 pipe_name(crtc->pipe));
14458         }
14459 }
14460
14461 static void
14462 intel_modeset_verify_crtc(struct intel_crtc *crtc,
14463                           struct intel_atomic_state *state,
14464                           struct intel_crtc_state *old_crtc_state,
14465                           struct intel_crtc_state *new_crtc_state)
14466 {
14467         if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
14468                 return;
14469
14470         verify_wm_state(crtc, new_crtc_state);
14471         verify_connector_state(state, crtc);
14472         verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
14473         verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
14474 }
14475
14476 static void
14477 verify_disabled_dpll_state(struct drm_i915_private *dev_priv)
14478 {
14479         int i;
14480
14481         for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++)
14482                 verify_single_dpll_state(dev_priv,
14483                                          &dev_priv->dpll.shared_dplls[i],
14484                                          NULL, NULL);
14485 }
14486
14487 static void
14488 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
14489                               struct intel_atomic_state *state)
14490 {
14491         verify_encoder_state(dev_priv, state);
14492         verify_connector_state(state, NULL);
14493         verify_disabled_dpll_state(dev_priv);
14494 }
14495
14496 static void
14497 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
14498 {
14499         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
14500         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14501         const struct drm_display_mode *adjusted_mode =
14502                 &crtc_state->hw.adjusted_mode;
14503
14504         drm_calc_timestamping_constants(&crtc->base, adjusted_mode);
14505
14506         crtc->mode_flags = crtc_state->mode_flags;
14507
14508         /*
14509          * The scanline counter increments at the leading edge of hsync.
14510          *
14511          * On most platforms it starts counting from vtotal-1 on the
14512          * first active line. That means the scanline counter value is
14513          * always one less than what we would expect. Ie. just after
14514          * start of vblank, which also occurs at start of hsync (on the
14515          * last active line), the scanline counter will read vblank_start-1.
14516          *
14517          * On gen2 the scanline counter starts counting from 1 instead
14518          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
14519          * to keep the value positive), instead of adding one.
14520          *
14521          * On HSW+ the behaviour of the scanline counter depends on the output
14522          * type. For DP ports it behaves like most other platforms, but on HDMI
14523          * there's an extra 1 line difference. So we need to add two instead of
14524          * one to the value.
14525          *
14526          * On VLV/CHV DSI the scanline counter would appear to increment
14527          * approx. 1/3 of a scanline before start of vblank. Unfortunately
14528          * that means we can't tell whether we're in vblank or not while
14529          * we're on that particular line. We must still set scanline_offset
14530          * to 1 so that the vblank timestamps come out correct when we query
14531          * the scanline counter from within the vblank interrupt handler.
14532          * However if queried just before the start of vblank we'll get an
14533          * answer that's slightly in the future.
14534          */
14535         if (IS_GEN(dev_priv, 2)) {
14536                 int vtotal;
14537
14538                 vtotal = adjusted_mode->crtc_vtotal;
14539                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
14540                         vtotal /= 2;
14541
14542                 crtc->scanline_offset = vtotal - 1;
14543         } else if (HAS_DDI(dev_priv) &&
14544                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
14545                 crtc->scanline_offset = 2;
14546         } else {
14547                 crtc->scanline_offset = 1;
14548         }
14549 }
14550
14551 static void intel_modeset_clear_plls(struct intel_atomic_state *state)
14552 {
14553         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14554         struct intel_crtc_state *new_crtc_state;
14555         struct intel_crtc *crtc;
14556         int i;
14557
14558         if (!dev_priv->display.crtc_compute_clock)
14559                 return;
14560
14561         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14562                 if (!needs_modeset(new_crtc_state))
14563                         continue;
14564
14565                 intel_release_shared_dplls(state, crtc);
14566         }
14567 }
14568
14569 /*
14570  * This implements the workaround described in the "notes" section of the mode
14571  * set sequence documentation. When going from no pipes or single pipe to
14572  * multiple pipes, and planes are enabled after the pipe, we need to wait at
14573  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
14574  */
14575 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
14576 {
14577         struct intel_crtc_state *crtc_state;
14578         struct intel_crtc *crtc;
14579         struct intel_crtc_state *first_crtc_state = NULL;
14580         struct intel_crtc_state *other_crtc_state = NULL;
14581         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
14582         int i;
14583
14584         /* look at all crtc's that are going to be enabled in during modeset */
14585         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14586                 if (!crtc_state->hw.active ||
14587                     !needs_modeset(crtc_state))
14588                         continue;
14589
14590                 if (first_crtc_state) {
14591                         other_crtc_state = crtc_state;
14592                         break;
14593                 } else {
14594                         first_crtc_state = crtc_state;
14595                         first_pipe = crtc->pipe;
14596                 }
14597         }
14598
14599         /* No workaround needed? */
14600         if (!first_crtc_state)
14601                 return 0;
14602
14603         /* w/a possibly needed, check how many crtc's are already enabled. */
14604         for_each_intel_crtc(state->base.dev, crtc) {
14605                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
14606                 if (IS_ERR(crtc_state))
14607                         return PTR_ERR(crtc_state);
14608
14609                 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
14610
14611                 if (!crtc_state->hw.active ||
14612                     needs_modeset(crtc_state))
14613                         continue;
14614
14615                 /* 2 or more enabled crtcs means no need for w/a */
14616                 if (enabled_pipe != INVALID_PIPE)
14617                         return 0;
14618
14619                 enabled_pipe = crtc->pipe;
14620         }
14621
14622         if (enabled_pipe != INVALID_PIPE)
14623                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
14624         else if (other_crtc_state)
14625                 other_crtc_state->hsw_workaround_pipe = first_pipe;
14626
14627         return 0;
14628 }
14629
14630 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
14631                            u8 active_pipes)
14632 {
14633         const struct intel_crtc_state *crtc_state;
14634         struct intel_crtc *crtc;
14635         int i;
14636
14637         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14638                 if (crtc_state->hw.active)
14639                         active_pipes |= BIT(crtc->pipe);
14640                 else
14641                         active_pipes &= ~BIT(crtc->pipe);
14642         }
14643
14644         return active_pipes;
14645 }
14646
14647 static int intel_modeset_checks(struct intel_atomic_state *state)
14648 {
14649         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14650
14651         state->modeset = true;
14652
14653         if (IS_HASWELL(dev_priv))
14654                 return hsw_mode_set_planes_workaround(state);
14655
14656         return 0;
14657 }
14658
14659 /*
14660  * Handle calculation of various watermark data at the end of the atomic check
14661  * phase.  The code here should be run after the per-crtc and per-plane 'check'
14662  * handlers to ensure that all derived state has been updated.
14663  */
14664 static int calc_watermark_data(struct intel_atomic_state *state)
14665 {
14666         struct drm_device *dev = state->base.dev;
14667         struct drm_i915_private *dev_priv = to_i915(dev);
14668
14669         /* Is there platform-specific watermark information to calculate? */
14670         if (dev_priv->display.compute_global_watermarks)
14671                 return dev_priv->display.compute_global_watermarks(state);
14672
14673         return 0;
14674 }
14675
14676 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
14677                                      struct intel_crtc_state *new_crtc_state)
14678 {
14679         if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
14680                 return;
14681
14682         new_crtc_state->uapi.mode_changed = false;
14683         new_crtc_state->update_pipe = true;
14684 }
14685
14686 static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state,
14687                                     struct intel_crtc_state *new_crtc_state)
14688 {
14689         /*
14690          * If we're not doing the full modeset we want to
14691          * keep the current M/N values as they may be
14692          * sufficiently different to the computed values
14693          * to cause problems.
14694          *
14695          * FIXME: should really copy more fuzzy state here
14696          */
14697         new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n;
14698         new_crtc_state->dp_m_n = old_crtc_state->dp_m_n;
14699         new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
14700         new_crtc_state->has_drrs = old_crtc_state->has_drrs;
14701 }
14702
14703 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
14704                                           struct intel_crtc *crtc,
14705                                           u8 plane_ids_mask)
14706 {
14707         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14708         struct intel_plane *plane;
14709
14710         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
14711                 struct intel_plane_state *plane_state;
14712
14713                 if ((plane_ids_mask & BIT(plane->id)) == 0)
14714                         continue;
14715
14716                 plane_state = intel_atomic_get_plane_state(state, plane);
14717                 if (IS_ERR(plane_state))
14718                         return PTR_ERR(plane_state);
14719         }
14720
14721         return 0;
14722 }
14723
14724 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
14725 {
14726         /* See {hsw,vlv,ivb}_plane_ratio() */
14727         return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
14728                 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
14729                 IS_IVYBRIDGE(dev_priv) || (INTEL_GEN(dev_priv) >= 11);
14730 }
14731
14732 static int intel_atomic_check_planes(struct intel_atomic_state *state)
14733 {
14734         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14735         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14736         struct intel_plane_state *plane_state;
14737         struct intel_plane *plane;
14738         struct intel_crtc *crtc;
14739         int i, ret;
14740
14741         ret = icl_add_linked_planes(state);
14742         if (ret)
14743                 return ret;
14744
14745         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
14746                 ret = intel_plane_atomic_check(state, plane);
14747                 if (ret) {
14748                         drm_dbg_atomic(&dev_priv->drm,
14749                                        "[PLANE:%d:%s] atomic driver check failed\n",
14750                                        plane->base.base.id, plane->base.name);
14751                         return ret;
14752                 }
14753         }
14754
14755         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14756                                             new_crtc_state, i) {
14757                 u8 old_active_planes, new_active_planes;
14758
14759                 ret = icl_check_nv12_planes(new_crtc_state);
14760                 if (ret)
14761                         return ret;
14762
14763                 /*
14764                  * On some platforms the number of active planes affects
14765                  * the planes' minimum cdclk calculation. Add such planes
14766                  * to the state before we compute the minimum cdclk.
14767                  */
14768                 if (!active_planes_affects_min_cdclk(dev_priv))
14769                         continue;
14770
14771                 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
14772                 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
14773
14774                 /*
14775                  * Not only the number of planes, but if the plane configuration had
14776                  * changed might already mean we need to recompute min CDCLK,
14777                  * because different planes might consume different amount of Dbuf bandwidth
14778                  * according to formula: Bw per plane = Pixel rate * bpp * pipe/plane scale factor
14779                  */
14780                 if (old_active_planes == new_active_planes)
14781                         continue;
14782
14783                 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
14784                 if (ret)
14785                         return ret;
14786         }
14787
14788         return 0;
14789 }
14790
14791 static int intel_atomic_check_cdclk(struct intel_atomic_state *state,
14792                                     bool *need_cdclk_calc)
14793 {
14794         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14795         const struct intel_cdclk_state *old_cdclk_state;
14796         const struct intel_cdclk_state *new_cdclk_state;
14797         struct intel_plane_state *plane_state;
14798         struct intel_bw_state *new_bw_state;
14799         struct intel_plane *plane;
14800         int min_cdclk = 0;
14801         enum pipe pipe;
14802         int ret;
14803         int i;
14804         /*
14805          * active_planes bitmask has been updated, and potentially
14806          * affected planes are part of the state. We can now
14807          * compute the minimum cdclk for each plane.
14808          */
14809         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
14810                 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc);
14811                 if (ret)
14812                         return ret;
14813         }
14814
14815         old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
14816         new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
14817
14818         if (new_cdclk_state &&
14819             old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
14820                 *need_cdclk_calc = true;
14821
14822         ret = dev_priv->display.bw_calc_min_cdclk(state);
14823         if (ret)
14824                 return ret;
14825
14826         new_bw_state = intel_atomic_get_new_bw_state(state);
14827
14828         if (!new_cdclk_state || !new_bw_state)
14829                 return 0;
14830
14831         for_each_pipe(dev_priv, pipe) {
14832                 min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk);
14833
14834                 /*
14835                  * Currently do this change only if we need to increase
14836                  */
14837                 if (new_bw_state->min_cdclk > min_cdclk)
14838                         *need_cdclk_calc = true;
14839         }
14840
14841         return 0;
14842 }
14843
14844 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
14845 {
14846         struct intel_crtc_state *crtc_state;
14847         struct intel_crtc *crtc;
14848         int i;
14849
14850         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14851                 int ret = intel_crtc_atomic_check(state, crtc);
14852                 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
14853                 if (ret) {
14854                         drm_dbg_atomic(&i915->drm,
14855                                        "[CRTC:%d:%s] atomic driver check failed\n",
14856                                        crtc->base.base.id, crtc->base.name);
14857                         return ret;
14858                 }
14859         }
14860
14861         return 0;
14862 }
14863
14864 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
14865                                                u8 transcoders)
14866 {
14867         const struct intel_crtc_state *new_crtc_state;
14868         struct intel_crtc *crtc;
14869         int i;
14870
14871         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14872                 if (new_crtc_state->hw.enable &&
14873                     transcoders & BIT(new_crtc_state->cpu_transcoder) &&
14874                     needs_modeset(new_crtc_state))
14875                         return true;
14876         }
14877
14878         return false;
14879 }
14880
14881 /**
14882  * intel_atomic_check - validate state object
14883  * @dev: drm device
14884  * @_state: state to validate
14885  */
14886 static int intel_atomic_check(struct drm_device *dev,
14887                               struct drm_atomic_state *_state)
14888 {
14889         struct drm_i915_private *dev_priv = to_i915(dev);
14890         struct intel_atomic_state *state = to_intel_atomic_state(_state);
14891         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14892         struct intel_crtc *crtc;
14893         int ret, i;
14894         bool any_ms = false;
14895
14896         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14897                                             new_crtc_state, i) {
14898                 if (new_crtc_state->inherited != old_crtc_state->inherited)
14899                         new_crtc_state->uapi.mode_changed = true;
14900         }
14901
14902         ret = drm_atomic_helper_check_modeset(dev, &state->base);
14903         if (ret)
14904                 goto fail;
14905
14906         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14907                                             new_crtc_state, i) {
14908                 if (!needs_modeset(new_crtc_state)) {
14909                         /* Light copy */
14910                         intel_crtc_copy_uapi_to_hw_state_nomodeset(new_crtc_state);
14911
14912                         continue;
14913                 }
14914
14915                 ret = intel_crtc_prepare_cleared_state(new_crtc_state);
14916                 if (ret)
14917                         goto fail;
14918
14919                 if (!new_crtc_state->hw.enable)
14920                         continue;
14921
14922                 ret = intel_modeset_pipe_config(new_crtc_state);
14923                 if (ret)
14924                         goto fail;
14925         }
14926
14927         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14928                                             new_crtc_state, i) {
14929                 if (!needs_modeset(new_crtc_state))
14930                         continue;
14931
14932                 ret = intel_modeset_pipe_config_late(new_crtc_state);
14933                 if (ret)
14934                         goto fail;
14935
14936                 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
14937         }
14938
14939         /**
14940          * Check if fastset is allowed by external dependencies like other
14941          * pipes and transcoders.
14942          *
14943          * Right now it only forces a fullmodeset when the MST master
14944          * transcoder did not changed but the pipe of the master transcoder
14945          * needs a fullmodeset so all slaves also needs to do a fullmodeset or
14946          * in case of port synced crtcs, if one of the synced crtcs
14947          * needs a full modeset, all other synced crtcs should be
14948          * forced a full modeset.
14949          */
14950         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14951                 if (!new_crtc_state->hw.enable || needs_modeset(new_crtc_state))
14952                         continue;
14953
14954                 if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
14955                         enum transcoder master = new_crtc_state->mst_master_transcoder;
14956
14957                         if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
14958                                 new_crtc_state->uapi.mode_changed = true;
14959                                 new_crtc_state->update_pipe = false;
14960                         }
14961                 }
14962
14963                 if (is_trans_port_sync_mode(new_crtc_state)) {
14964                         u8 trans = new_crtc_state->sync_mode_slaves_mask;
14965
14966                         if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
14967                                 trans |= BIT(new_crtc_state->master_transcoder);
14968
14969                         if (intel_cpu_transcoders_need_modeset(state, trans)) {
14970                                 new_crtc_state->uapi.mode_changed = true;
14971                                 new_crtc_state->update_pipe = false;
14972                         }
14973                 }
14974         }
14975
14976         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14977                                             new_crtc_state, i) {
14978                 if (needs_modeset(new_crtc_state)) {
14979                         any_ms = true;
14980                         continue;
14981                 }
14982
14983                 if (!new_crtc_state->update_pipe)
14984                         continue;
14985
14986                 intel_crtc_copy_fastset(old_crtc_state, new_crtc_state);
14987         }
14988
14989         if (any_ms && !check_digital_port_conflicts(state)) {
14990                 drm_dbg_kms(&dev_priv->drm,
14991                             "rejecting conflicting digital port configuration\n");
14992                 ret = -EINVAL;
14993                 goto fail;
14994         }
14995
14996         ret = drm_dp_mst_atomic_check(&state->base);
14997         if (ret)
14998                 goto fail;
14999
15000         ret = intel_atomic_check_planes(state);
15001         if (ret)
15002                 goto fail;
15003
15004         /*
15005          * distrust_bios_wm will force a full dbuf recomputation
15006          * but the hardware state will only get updated accordingly
15007          * if state->modeset==true. Hence distrust_bios_wm==true &&
15008          * state->modeset==false is an invalid combination which
15009          * would cause the hardware and software dbuf state to get
15010          * out of sync. We must prevent that.
15011          *
15012          * FIXME clean up this mess and introduce better
15013          * state tracking for dbuf.
15014          */
15015         if (dev_priv->wm.distrust_bios_wm)
15016                 any_ms = true;
15017
15018         intel_fbc_choose_crtc(dev_priv, state);
15019         ret = calc_watermark_data(state);
15020         if (ret)
15021                 goto fail;
15022
15023         ret = intel_bw_atomic_check(state);
15024         if (ret)
15025                 goto fail;
15026
15027         ret = intel_atomic_check_cdclk(state, &any_ms);
15028         if (ret)
15029                 goto fail;
15030
15031         if (any_ms) {
15032                 ret = intel_modeset_checks(state);
15033                 if (ret)
15034                         goto fail;
15035
15036                 ret = intel_modeset_calc_cdclk(state);
15037                 if (ret)
15038                         return ret;
15039
15040                 intel_modeset_clear_plls(state);
15041         }
15042
15043         ret = intel_atomic_check_crtcs(state);
15044         if (ret)
15045                 goto fail;
15046
15047         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15048                                             new_crtc_state, i) {
15049                 if (!needs_modeset(new_crtc_state) &&
15050                     !new_crtc_state->update_pipe)
15051                         continue;
15052
15053                 intel_dump_pipe_config(new_crtc_state, state,
15054                                        needs_modeset(new_crtc_state) ?
15055                                        "[modeset]" : "[fastset]");
15056         }
15057
15058         return 0;
15059
15060  fail:
15061         if (ret == -EDEADLK)
15062                 return ret;
15063
15064         /*
15065          * FIXME would probably be nice to know which crtc specifically
15066          * caused the failure, in cases where we can pinpoint it.
15067          */
15068         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15069                                             new_crtc_state, i)
15070                 intel_dump_pipe_config(new_crtc_state, state, "[failed]");
15071
15072         return ret;
15073 }
15074
15075 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
15076 {
15077         struct intel_crtc_state *crtc_state;
15078         struct intel_crtc *crtc;
15079         int i, ret;
15080
15081         ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
15082         if (ret < 0)
15083                 return ret;
15084
15085         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
15086                 bool mode_changed = needs_modeset(crtc_state);
15087
15088                 if (mode_changed || crtc_state->update_pipe ||
15089                     crtc_state->uapi.color_mgmt_changed) {
15090                         intel_dsb_prepare(crtc_state);
15091                 }
15092         }
15093
15094         return 0;
15095 }
15096
15097 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
15098 {
15099         struct drm_device *dev = crtc->base.dev;
15100         struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)];
15101
15102         if (!vblank->max_vblank_count)
15103                 return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
15104
15105         return crtc->base.funcs->get_vblank_counter(&crtc->base);
15106 }
15107
15108 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
15109                                   struct intel_crtc_state *crtc_state)
15110 {
15111         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15112
15113         if (!IS_GEN(dev_priv, 2) || crtc_state->active_planes)
15114                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
15115
15116         if (crtc_state->has_pch_encoder) {
15117                 enum pipe pch_transcoder =
15118                         intel_crtc_pch_transcoder(crtc);
15119
15120                 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
15121         }
15122 }
15123
15124 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
15125                                const struct intel_crtc_state *new_crtc_state)
15126 {
15127         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
15128         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15129
15130         /*
15131          * Update pipe size and adjust fitter if needed: the reason for this is
15132          * that in compute_mode_changes we check the native mode (not the pfit
15133          * mode) to see if we can flip rather than do a full mode set. In the
15134          * fastboot case, we'll flip, but if we don't update the pipesrc and
15135          * pfit state, we'll end up with a big fb scanned out into the wrong
15136          * sized surface.
15137          */
15138         intel_set_pipe_src_size(new_crtc_state);
15139
15140         /* on skylake this is done by detaching scalers */
15141         if (INTEL_GEN(dev_priv) >= 9) {
15142                 skl_detach_scalers(new_crtc_state);
15143
15144                 if (new_crtc_state->pch_pfit.enabled)
15145                         skl_pfit_enable(new_crtc_state);
15146         } else if (HAS_PCH_SPLIT(dev_priv)) {
15147                 if (new_crtc_state->pch_pfit.enabled)
15148                         ilk_pfit_enable(new_crtc_state);
15149                 else if (old_crtc_state->pch_pfit.enabled)
15150                         ilk_pfit_disable(old_crtc_state);
15151         }
15152
15153         /*
15154          * The register is supposedly single buffered so perhaps
15155          * not 100% correct to do this here. But SKL+ calculate
15156          * this based on the adjust pixel rate so pfit changes do
15157          * affect it and so it must be updated for fastsets.
15158          * HSW/BDW only really need this here for fastboot, after
15159          * that the value should not change without a full modeset.
15160          */
15161         if (INTEL_GEN(dev_priv) >= 9 ||
15162             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
15163                 hsw_set_linetime_wm(new_crtc_state);
15164
15165         if (INTEL_GEN(dev_priv) >= 11)
15166                 icl_set_pipe_chicken(crtc);
15167 }
15168
15169 static void commit_pipe_config(struct intel_atomic_state *state,
15170                                struct intel_crtc *crtc)
15171 {
15172         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15173         const struct intel_crtc_state *old_crtc_state =
15174                 intel_atomic_get_old_crtc_state(state, crtc);
15175         const struct intel_crtc_state *new_crtc_state =
15176                 intel_atomic_get_new_crtc_state(state, crtc);
15177         bool modeset = needs_modeset(new_crtc_state);
15178
15179         /*
15180          * During modesets pipe configuration was programmed as the
15181          * CRTC was enabled.
15182          */
15183         if (!modeset) {
15184                 if (new_crtc_state->uapi.color_mgmt_changed ||
15185                     new_crtc_state->update_pipe)
15186                         intel_color_commit(new_crtc_state);
15187
15188                 if (INTEL_GEN(dev_priv) >= 9)
15189                         skl_detach_scalers(new_crtc_state);
15190
15191                 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
15192                         bdw_set_pipemisc(new_crtc_state);
15193
15194                 if (new_crtc_state->update_pipe)
15195                         intel_pipe_fastset(old_crtc_state, new_crtc_state);
15196
15197                 intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
15198         }
15199
15200         if (dev_priv->display.atomic_update_watermarks)
15201                 dev_priv->display.atomic_update_watermarks(state, crtc);
15202 }
15203
15204 static void intel_enable_crtc(struct intel_atomic_state *state,
15205                               struct intel_crtc *crtc)
15206 {
15207         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15208         const struct intel_crtc_state *new_crtc_state =
15209                 intel_atomic_get_new_crtc_state(state, crtc);
15210
15211         if (!needs_modeset(new_crtc_state))
15212                 return;
15213
15214         intel_crtc_update_active_timings(new_crtc_state);
15215
15216         dev_priv->display.crtc_enable(state, crtc);
15217
15218         /* vblanks work again, re-enable pipe CRC. */
15219         intel_crtc_enable_pipe_crc(crtc);
15220 }
15221
15222 static void intel_update_crtc(struct intel_atomic_state *state,
15223                               struct intel_crtc *crtc)
15224 {
15225         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15226         const struct intel_crtc_state *old_crtc_state =
15227                 intel_atomic_get_old_crtc_state(state, crtc);
15228         struct intel_crtc_state *new_crtc_state =
15229                 intel_atomic_get_new_crtc_state(state, crtc);
15230         bool modeset = needs_modeset(new_crtc_state);
15231
15232         if (!modeset) {
15233                 if (new_crtc_state->preload_luts &&
15234                     (new_crtc_state->uapi.color_mgmt_changed ||
15235                      new_crtc_state->update_pipe))
15236                         intel_color_load_luts(new_crtc_state);
15237
15238                 intel_pre_plane_update(state, crtc);
15239
15240                 if (new_crtc_state->update_pipe)
15241                         intel_encoders_update_pipe(state, crtc);
15242         }
15243
15244         if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
15245                 intel_fbc_disable(crtc);
15246         else
15247                 intel_fbc_enable(state, crtc);
15248
15249         /* Perform vblank evasion around commit operation */
15250         intel_pipe_update_start(new_crtc_state);
15251
15252         commit_pipe_config(state, crtc);
15253
15254         if (INTEL_GEN(dev_priv) >= 9)
15255                 skl_update_planes_on_crtc(state, crtc);
15256         else
15257                 i9xx_update_planes_on_crtc(state, crtc);
15258
15259         intel_pipe_update_end(new_crtc_state);
15260
15261         /*
15262          * We usually enable FIFO underrun interrupts as part of the
15263          * CRTC enable sequence during modesets.  But when we inherit a
15264          * valid pipe configuration from the BIOS we need to take care
15265          * of enabling them on the CRTC's first fastset.
15266          */
15267         if (new_crtc_state->update_pipe && !modeset &&
15268             old_crtc_state->inherited)
15269                 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
15270 }
15271
15272
15273 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
15274                                           struct intel_crtc_state *old_crtc_state,
15275                                           struct intel_crtc_state *new_crtc_state,
15276                                           struct intel_crtc *crtc)
15277 {
15278         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15279
15280         intel_crtc_disable_planes(state, crtc);
15281
15282         /*
15283          * We need to disable pipe CRC before disabling the pipe,
15284          * or we race against vblank off.
15285          */
15286         intel_crtc_disable_pipe_crc(crtc);
15287
15288         dev_priv->display.crtc_disable(state, crtc);
15289         crtc->active = false;
15290         intel_fbc_disable(crtc);
15291         intel_disable_shared_dpll(old_crtc_state);
15292
15293         /* FIXME unify this for all platforms */
15294         if (!new_crtc_state->hw.active &&
15295             !HAS_GMCH(dev_priv) &&
15296             dev_priv->display.initial_watermarks)
15297                 dev_priv->display.initial_watermarks(state, crtc);
15298 }
15299
15300 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
15301 {
15302         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
15303         struct intel_crtc *crtc;
15304         u32 handled = 0;
15305         int i;
15306
15307         /* Only disable port sync and MST slaves */
15308         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15309                                             new_crtc_state, i) {
15310                 if (!needs_modeset(new_crtc_state))
15311                         continue;
15312
15313                 if (!old_crtc_state->hw.active)
15314                         continue;
15315
15316                 /* In case of Transcoder port Sync master slave CRTCs can be
15317                  * assigned in any order and we need to make sure that
15318                  * slave CRTCs are disabled first and then master CRTC since
15319                  * Slave vblanks are masked till Master Vblanks.
15320                  */
15321                 if (!is_trans_port_sync_slave(old_crtc_state) &&
15322                     !intel_dp_mst_is_slave_trans(old_crtc_state))
15323                         continue;
15324
15325                 intel_pre_plane_update(state, crtc);
15326                 intel_old_crtc_state_disables(state, old_crtc_state,
15327                                               new_crtc_state, crtc);
15328                 handled |= BIT(crtc->pipe);
15329         }
15330
15331         /* Disable everything else left on */
15332         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15333                                             new_crtc_state, i) {
15334                 if (!needs_modeset(new_crtc_state) ||
15335                     (handled & BIT(crtc->pipe)))
15336                         continue;
15337
15338                 intel_pre_plane_update(state, crtc);
15339                 if (old_crtc_state->hw.active)
15340                         intel_old_crtc_state_disables(state, old_crtc_state,
15341                                                       new_crtc_state, crtc);
15342         }
15343 }
15344
15345 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
15346 {
15347         struct intel_crtc_state *new_crtc_state;
15348         struct intel_crtc *crtc;
15349         int i;
15350
15351         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15352                 if (!new_crtc_state->hw.active)
15353                         continue;
15354
15355                 intel_enable_crtc(state, crtc);
15356                 intel_update_crtc(state, crtc);
15357         }
15358 }
15359
15360 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
15361 {
15362         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15363         struct intel_crtc *crtc;
15364         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
15365         struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
15366         u8 update_pipes = 0, modeset_pipes = 0;
15367         int i;
15368
15369         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
15370                 enum pipe pipe = crtc->pipe;
15371
15372                 if (!new_crtc_state->hw.active)
15373                         continue;
15374
15375                 /* ignore allocations for crtc's that have been turned off. */
15376                 if (!needs_modeset(new_crtc_state)) {
15377                         entries[pipe] = old_crtc_state->wm.skl.ddb;
15378                         update_pipes |= BIT(pipe);
15379                 } else {
15380                         modeset_pipes |= BIT(pipe);
15381                 }
15382         }
15383
15384         /*
15385          * Whenever the number of active pipes changes, we need to make sure we
15386          * update the pipes in the right order so that their ddb allocations
15387          * never overlap with each other between CRTC updates. Otherwise we'll
15388          * cause pipe underruns and other bad stuff.
15389          *
15390          * So first lets enable all pipes that do not need a fullmodeset as
15391          * those don't have any external dependency.
15392          */
15393         while (update_pipes) {
15394                 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15395                                                     new_crtc_state, i) {
15396                         enum pipe pipe = crtc->pipe;
15397
15398                         if ((update_pipes & BIT(pipe)) == 0)
15399                                 continue;
15400
15401                         if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
15402                                                         entries, I915_MAX_PIPES, pipe))
15403                                 continue;
15404
15405                         entries[pipe] = new_crtc_state->wm.skl.ddb;
15406                         update_pipes &= ~BIT(pipe);
15407
15408                         intel_update_crtc(state, crtc);
15409
15410                         /*
15411                          * If this is an already active pipe, it's DDB changed,
15412                          * and this isn't the last pipe that needs updating
15413                          * then we need to wait for a vblank to pass for the
15414                          * new ddb allocation to take effect.
15415                          */
15416                         if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
15417                                                  &old_crtc_state->wm.skl.ddb) &&
15418                             (update_pipes | modeset_pipes))
15419                                 intel_wait_for_vblank(dev_priv, pipe);
15420                 }
15421         }
15422
15423         update_pipes = modeset_pipes;
15424
15425         /*
15426          * Enable all pipes that needs a modeset and do not depends on other
15427          * pipes
15428          */
15429         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15430                 enum pipe pipe = crtc->pipe;
15431
15432                 if ((modeset_pipes & BIT(pipe)) == 0)
15433                         continue;
15434
15435                 if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
15436                     is_trans_port_sync_master(new_crtc_state))
15437                         continue;
15438
15439                 modeset_pipes &= ~BIT(pipe);
15440
15441                 intel_enable_crtc(state, crtc);
15442         }
15443
15444         /*
15445          * Then we enable all remaining pipes that depend on other
15446          * pipes: MST slaves and port sync masters.
15447          */
15448         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15449                 enum pipe pipe = crtc->pipe;
15450
15451                 if ((modeset_pipes & BIT(pipe)) == 0)
15452                         continue;
15453
15454                 modeset_pipes &= ~BIT(pipe);
15455
15456                 intel_enable_crtc(state, crtc);
15457         }
15458
15459         /*
15460          * Finally we do the plane updates/etc. for all pipes that got enabled.
15461          */
15462         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15463                 enum pipe pipe = crtc->pipe;
15464
15465                 if ((update_pipes & BIT(pipe)) == 0)
15466                         continue;
15467
15468                 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
15469                                                                         entries, I915_MAX_PIPES, pipe));
15470
15471                 entries[pipe] = new_crtc_state->wm.skl.ddb;
15472                 update_pipes &= ~BIT(pipe);
15473
15474                 intel_update_crtc(state, crtc);
15475         }
15476
15477         drm_WARN_ON(&dev_priv->drm, modeset_pipes);
15478         drm_WARN_ON(&dev_priv->drm, update_pipes);
15479 }
15480
15481 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
15482 {
15483         struct intel_atomic_state *state, *next;
15484         struct llist_node *freed;
15485
15486         freed = llist_del_all(&dev_priv->atomic_helper.free_list);
15487         llist_for_each_entry_safe(state, next, freed, freed)
15488                 drm_atomic_state_put(&state->base);
15489 }
15490
15491 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
15492 {
15493         struct drm_i915_private *dev_priv =
15494                 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
15495
15496         intel_atomic_helper_free_state(dev_priv);
15497 }
15498
15499 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
15500 {
15501         struct wait_queue_entry wait_fence, wait_reset;
15502         struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
15503
15504         init_wait_entry(&wait_fence, 0);
15505         init_wait_entry(&wait_reset, 0);
15506         for (;;) {
15507                 prepare_to_wait(&intel_state->commit_ready.wait,
15508                                 &wait_fence, TASK_UNINTERRUPTIBLE);
15509                 prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
15510                                               I915_RESET_MODESET),
15511                                 &wait_reset, TASK_UNINTERRUPTIBLE);
15512
15513
15514                 if (i915_sw_fence_done(&intel_state->commit_ready) ||
15515                     test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
15516                         break;
15517
15518                 schedule();
15519         }
15520         finish_wait(&intel_state->commit_ready.wait, &wait_fence);
15521         finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
15522                                   I915_RESET_MODESET),
15523                     &wait_reset);
15524 }
15525
15526 static void intel_cleanup_dsbs(struct intel_atomic_state *state)
15527 {
15528         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
15529         struct intel_crtc *crtc;
15530         int i;
15531
15532         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15533                                             new_crtc_state, i)
15534                 intel_dsb_cleanup(old_crtc_state);
15535 }
15536
15537 static void intel_atomic_cleanup_work(struct work_struct *work)
15538 {
15539         struct intel_atomic_state *state =
15540                 container_of(work, struct intel_atomic_state, base.commit_work);
15541         struct drm_i915_private *i915 = to_i915(state->base.dev);
15542
15543         intel_cleanup_dsbs(state);
15544         drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
15545         drm_atomic_helper_commit_cleanup_done(&state->base);
15546         drm_atomic_state_put(&state->base);
15547
15548         intel_atomic_helper_free_state(i915);
15549 }
15550
15551 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
15552 {
15553         struct drm_device *dev = state->base.dev;
15554         struct drm_i915_private *dev_priv = to_i915(dev);
15555         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
15556         struct intel_crtc *crtc;
15557         u64 put_domains[I915_MAX_PIPES] = {};
15558         intel_wakeref_t wakeref = 0;
15559         int i;
15560
15561         intel_atomic_commit_fence_wait(state);
15562
15563         drm_atomic_helper_wait_for_dependencies(&state->base);
15564
15565         if (state->modeset)
15566                 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
15567
15568         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15569                                             new_crtc_state, i) {
15570                 if (needs_modeset(new_crtc_state) ||
15571                     new_crtc_state->update_pipe) {
15572
15573                         put_domains[crtc->pipe] =
15574                                 modeset_get_crtc_power_domains(new_crtc_state);
15575                 }
15576         }
15577
15578         intel_commit_modeset_disables(state);
15579
15580         /* FIXME: Eventually get rid of our crtc->config pointer */
15581         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
15582                 crtc->config = new_crtc_state;
15583
15584         if (state->modeset) {
15585                 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
15586
15587                 intel_set_cdclk_pre_plane_update(state);
15588
15589                 intel_modeset_verify_disabled(dev_priv, state);
15590         }
15591
15592         intel_sagv_pre_plane_update(state);
15593
15594         /* Complete the events for pipes that have now been disabled */
15595         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15596                 bool modeset = needs_modeset(new_crtc_state);
15597
15598                 /* Complete events for now disable pipes here. */
15599                 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
15600                         spin_lock_irq(&dev->event_lock);
15601                         drm_crtc_send_vblank_event(&crtc->base,
15602                                                    new_crtc_state->uapi.event);
15603                         spin_unlock_irq(&dev->event_lock);
15604
15605                         new_crtc_state->uapi.event = NULL;
15606                 }
15607         }
15608
15609         if (state->modeset)
15610                 intel_encoders_update_prepare(state);
15611
15612         intel_dbuf_pre_plane_update(state);
15613
15614         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
15615         dev_priv->display.commit_modeset_enables(state);
15616
15617         if (state->modeset) {
15618                 intel_encoders_update_complete(state);
15619
15620                 intel_set_cdclk_post_plane_update(state);
15621         }
15622
15623         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
15624          * already, but still need the state for the delayed optimization. To
15625          * fix this:
15626          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
15627          * - schedule that vblank worker _before_ calling hw_done
15628          * - at the start of commit_tail, cancel it _synchrously
15629          * - switch over to the vblank wait helper in the core after that since
15630          *   we don't need out special handling any more.
15631          */
15632         drm_atomic_helper_wait_for_flip_done(dev, &state->base);
15633
15634         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15635                 if (new_crtc_state->hw.active &&
15636                     !needs_modeset(new_crtc_state) &&
15637                     !new_crtc_state->preload_luts &&
15638                     (new_crtc_state->uapi.color_mgmt_changed ||
15639                      new_crtc_state->update_pipe))
15640                         intel_color_load_luts(new_crtc_state);
15641         }
15642
15643         /*
15644          * Now that the vblank has passed, we can go ahead and program the
15645          * optimal watermarks on platforms that need two-step watermark
15646          * programming.
15647          *
15648          * TODO: Move this (and other cleanup) to an async worker eventually.
15649          */
15650         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15651                                             new_crtc_state, i) {
15652                 /*
15653                  * Gen2 reports pipe underruns whenever all planes are disabled.
15654                  * So re-enable underrun reporting after some planes get enabled.
15655                  *
15656                  * We do this before .optimize_watermarks() so that we have a
15657                  * chance of catching underruns with the intermediate watermarks
15658                  * vs. the new plane configuration.
15659                  */
15660                 if (IS_GEN(dev_priv, 2) && planes_enabling(old_crtc_state, new_crtc_state))
15661                         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
15662
15663                 if (dev_priv->display.optimize_watermarks)
15664                         dev_priv->display.optimize_watermarks(state, crtc);
15665         }
15666
15667         intel_dbuf_post_plane_update(state);
15668
15669         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
15670                 intel_post_plane_update(state, crtc);
15671
15672                 if (put_domains[i])
15673                         modeset_put_power_domains(dev_priv, put_domains[i]);
15674
15675                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
15676
15677                 /*
15678                  * DSB cleanup is done in cleanup_work aligning with framebuffer
15679                  * cleanup. So copy and reset the dsb structure to sync with
15680                  * commit_done and later do dsb cleanup in cleanup_work.
15681                  */
15682                 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb);
15683         }
15684
15685         /* Underruns don't always raise interrupts, so check manually */
15686         intel_check_cpu_fifo_underruns(dev_priv);
15687         intel_check_pch_fifo_underruns(dev_priv);
15688
15689         if (state->modeset)
15690                 intel_verify_planes(state);
15691
15692         intel_sagv_post_plane_update(state);
15693
15694         drm_atomic_helper_commit_hw_done(&state->base);
15695
15696         if (state->modeset) {
15697                 /* As one of the primary mmio accessors, KMS has a high
15698                  * likelihood of triggering bugs in unclaimed access. After we
15699                  * finish modesetting, see if an error has been flagged, and if
15700                  * so enable debugging for the next modeset - and hope we catch
15701                  * the culprit.
15702                  */
15703                 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
15704                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
15705         }
15706         intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
15707
15708         /*
15709          * Defer the cleanup of the old state to a separate worker to not
15710          * impede the current task (userspace for blocking modesets) that
15711          * are executed inline. For out-of-line asynchronous modesets/flips,
15712          * deferring to a new worker seems overkill, but we would place a
15713          * schedule point (cond_resched()) here anyway to keep latencies
15714          * down.
15715          */
15716         INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
15717         queue_work(system_highpri_wq, &state->base.commit_work);
15718 }
15719
15720 static void intel_atomic_commit_work(struct work_struct *work)
15721 {
15722         struct intel_atomic_state *state =
15723                 container_of(work, struct intel_atomic_state, base.commit_work);
15724
15725         intel_atomic_commit_tail(state);
15726 }
15727
15728 static int __i915_sw_fence_call
15729 intel_atomic_commit_ready(struct i915_sw_fence *fence,
15730                           enum i915_sw_fence_notify notify)
15731 {
15732         struct intel_atomic_state *state =
15733                 container_of(fence, struct intel_atomic_state, commit_ready);
15734
15735         switch (notify) {
15736         case FENCE_COMPLETE:
15737                 /* we do blocking waits in the worker, nothing to do here */
15738                 break;
15739         case FENCE_FREE:
15740                 {
15741                         struct intel_atomic_helper *helper =
15742                                 &to_i915(state->base.dev)->atomic_helper;
15743
15744                         if (llist_add(&state->freed, &helper->free_list))
15745                                 schedule_work(&helper->free_work);
15746                         break;
15747                 }
15748         }
15749
15750         return NOTIFY_DONE;
15751 }
15752
15753 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
15754 {
15755         struct intel_plane_state *old_plane_state, *new_plane_state;
15756         struct intel_plane *plane;
15757         int i;
15758
15759         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
15760                                              new_plane_state, i)
15761                 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
15762                                         to_intel_frontbuffer(new_plane_state->hw.fb),
15763                                         plane->frontbuffer_bit);
15764 }
15765
15766 static int intel_atomic_commit(struct drm_device *dev,
15767                                struct drm_atomic_state *_state,
15768                                bool nonblock)
15769 {
15770         struct intel_atomic_state *state = to_intel_atomic_state(_state);
15771         struct drm_i915_private *dev_priv = to_i915(dev);
15772         int ret = 0;
15773
15774         state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
15775
15776         drm_atomic_state_get(&state->base);
15777         i915_sw_fence_init(&state->commit_ready,
15778                            intel_atomic_commit_ready);
15779
15780         /*
15781          * The intel_legacy_cursor_update() fast path takes care
15782          * of avoiding the vblank waits for simple cursor
15783          * movement and flips. For cursor on/off and size changes,
15784          * we want to perform the vblank waits so that watermark
15785          * updates happen during the correct frames. Gen9+ have
15786          * double buffered watermarks and so shouldn't need this.
15787          *
15788          * Unset state->legacy_cursor_update before the call to
15789          * drm_atomic_helper_setup_commit() because otherwise
15790          * drm_atomic_helper_wait_for_flip_done() is a noop and
15791          * we get FIFO underruns because we didn't wait
15792          * for vblank.
15793          *
15794          * FIXME doing watermarks and fb cleanup from a vblank worker
15795          * (assuming we had any) would solve these problems.
15796          */
15797         if (INTEL_GEN(dev_priv) < 9 && state->base.legacy_cursor_update) {
15798                 struct intel_crtc_state *new_crtc_state;
15799                 struct intel_crtc *crtc;
15800                 int i;
15801
15802                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
15803                         if (new_crtc_state->wm.need_postvbl_update ||
15804                             new_crtc_state->update_wm_post)
15805                                 state->base.legacy_cursor_update = false;
15806         }
15807
15808         ret = intel_atomic_prepare_commit(state);
15809         if (ret) {
15810                 drm_dbg_atomic(&dev_priv->drm,
15811                                "Preparing state failed with %i\n", ret);
15812                 i915_sw_fence_commit(&state->commit_ready);
15813                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
15814                 return ret;
15815         }
15816
15817         ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
15818         if (!ret)
15819                 ret = drm_atomic_helper_swap_state(&state->base, true);
15820         if (!ret)
15821                 intel_atomic_swap_global_state(state);
15822
15823         if (ret) {
15824                 struct intel_crtc_state *new_crtc_state;
15825                 struct intel_crtc *crtc;
15826                 int i;
15827
15828                 i915_sw_fence_commit(&state->commit_ready);
15829
15830                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
15831                         intel_dsb_cleanup(new_crtc_state);
15832
15833                 drm_atomic_helper_cleanup_planes(dev, &state->base);
15834                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
15835                 return ret;
15836         }
15837         dev_priv->wm.distrust_bios_wm = false;
15838         intel_shared_dpll_swap_state(state);
15839         intel_atomic_track_fbs(state);
15840
15841         drm_atomic_state_get(&state->base);
15842         INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
15843
15844         i915_sw_fence_commit(&state->commit_ready);
15845         if (nonblock && state->modeset) {
15846                 queue_work(dev_priv->modeset_wq, &state->base.commit_work);
15847         } else if (nonblock) {
15848                 queue_work(dev_priv->flip_wq, &state->base.commit_work);
15849         } else {
15850                 if (state->modeset)
15851                         flush_workqueue(dev_priv->modeset_wq);
15852                 intel_atomic_commit_tail(state);
15853         }
15854
15855         return 0;
15856 }
15857
15858 struct wait_rps_boost {
15859         struct wait_queue_entry wait;
15860
15861         struct drm_crtc *crtc;
15862         struct i915_request *request;
15863 };
15864
15865 static int do_rps_boost(struct wait_queue_entry *_wait,
15866                         unsigned mode, int sync, void *key)
15867 {
15868         struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
15869         struct i915_request *rq = wait->request;
15870
15871         /*
15872          * If we missed the vblank, but the request is already running it
15873          * is reasonable to assume that it will complete before the next
15874          * vblank without our intervention, so leave RPS alone.
15875          */
15876         if (!i915_request_started(rq))
15877                 intel_rps_boost(rq);
15878         i915_request_put(rq);
15879
15880         drm_crtc_vblank_put(wait->crtc);
15881
15882         list_del(&wait->wait.entry);
15883         kfree(wait);
15884         return 1;
15885 }
15886
15887 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
15888                                        struct dma_fence *fence)
15889 {
15890         struct wait_rps_boost *wait;
15891
15892         if (!dma_fence_is_i915(fence))
15893                 return;
15894
15895         if (INTEL_GEN(to_i915(crtc->dev)) < 6)
15896                 return;
15897
15898         if (drm_crtc_vblank_get(crtc))
15899                 return;
15900
15901         wait = kmalloc(sizeof(*wait), GFP_KERNEL);
15902         if (!wait) {
15903                 drm_crtc_vblank_put(crtc);
15904                 return;
15905         }
15906
15907         wait->request = to_request(dma_fence_get(fence));
15908         wait->crtc = crtc;
15909
15910         wait->wait.func = do_rps_boost;
15911         wait->wait.flags = 0;
15912
15913         add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
15914 }
15915
15916 static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
15917 {
15918         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
15919         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15920         struct drm_framebuffer *fb = plane_state->hw.fb;
15921         struct i915_vma *vma;
15922
15923         if (plane->id == PLANE_CURSOR &&
15924             INTEL_INFO(dev_priv)->display.cursor_needs_physical) {
15925                 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15926                 const int align = intel_cursor_alignment(dev_priv);
15927                 int err;
15928
15929                 err = i915_gem_object_attach_phys(obj, align);
15930                 if (err)
15931                         return err;
15932         }
15933
15934         vma = intel_pin_and_fence_fb_obj(fb,
15935                                          &plane_state->view,
15936                                          intel_plane_uses_fence(plane_state),
15937                                          &plane_state->flags);
15938         if (IS_ERR(vma))
15939                 return PTR_ERR(vma);
15940
15941         plane_state->vma = vma;
15942
15943         return 0;
15944 }
15945
15946 static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
15947 {
15948         struct i915_vma *vma;
15949
15950         vma = fetch_and_zero(&old_plane_state->vma);
15951         if (vma)
15952                 intel_unpin_fb_vma(vma, old_plane_state->flags);
15953 }
15954
15955 static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
15956 {
15957         struct i915_sched_attr attr = {
15958                 .priority = I915_USER_PRIORITY(I915_PRIORITY_DISPLAY),
15959         };
15960
15961         i915_gem_object_wait_priority(obj, 0, &attr);
15962 }
15963
15964 /**
15965  * intel_prepare_plane_fb - Prepare fb for usage on plane
15966  * @_plane: drm plane to prepare for
15967  * @_new_plane_state: the plane state being prepared
15968  *
15969  * Prepares a framebuffer for usage on a display plane.  Generally this
15970  * involves pinning the underlying object and updating the frontbuffer tracking
15971  * bits.  Some older platforms need special physical address handling for
15972  * cursor planes.
15973  *
15974  * Returns 0 on success, negative error code on failure.
15975  */
15976 int
15977 intel_prepare_plane_fb(struct drm_plane *_plane,
15978                        struct drm_plane_state *_new_plane_state)
15979 {
15980         struct intel_plane *plane = to_intel_plane(_plane);
15981         struct intel_plane_state *new_plane_state =
15982                 to_intel_plane_state(_new_plane_state);
15983         struct intel_atomic_state *state =
15984                 to_intel_atomic_state(new_plane_state->uapi.state);
15985         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15986         const struct intel_plane_state *old_plane_state =
15987                 intel_atomic_get_old_plane_state(state, plane);
15988         struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb);
15989         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_plane_state->hw.fb);
15990         int ret;
15991
15992         if (old_obj) {
15993                 const struct intel_crtc_state *crtc_state =
15994                         intel_atomic_get_new_crtc_state(state,
15995                                                         to_intel_crtc(old_plane_state->hw.crtc));
15996
15997                 /* Big Hammer, we also need to ensure that any pending
15998                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
15999                  * current scanout is retired before unpinning the old
16000                  * framebuffer. Note that we rely on userspace rendering
16001                  * into the buffer attached to the pipe they are waiting
16002                  * on. If not, userspace generates a GPU hang with IPEHR
16003                  * point to the MI_WAIT_FOR_EVENT.
16004                  *
16005                  * This should only fail upon a hung GPU, in which case we
16006                  * can safely continue.
16007                  */
16008                 if (needs_modeset(crtc_state)) {
16009                         ret = i915_sw_fence_await_reservation(&state->commit_ready,
16010                                                               old_obj->base.resv, NULL,
16011                                                               false, 0,
16012                                                               GFP_KERNEL);
16013                         if (ret < 0)
16014                                 return ret;
16015                 }
16016         }
16017
16018         if (new_plane_state->uapi.fence) { /* explicit fencing */
16019                 ret = i915_sw_fence_await_dma_fence(&state->commit_ready,
16020                                                     new_plane_state->uapi.fence,
16021                                                     i915_fence_timeout(dev_priv),
16022                                                     GFP_KERNEL);
16023                 if (ret < 0)
16024                         return ret;
16025         }
16026
16027         if (!obj)
16028                 return 0;
16029
16030         ret = i915_gem_object_pin_pages(obj);
16031         if (ret)
16032                 return ret;
16033
16034         ret = intel_plane_pin_fb(new_plane_state);
16035
16036         i915_gem_object_unpin_pages(obj);
16037         if (ret)
16038                 return ret;
16039
16040         fb_obj_bump_render_priority(obj);
16041         i915_gem_object_flush_frontbuffer(obj, ORIGIN_DIRTYFB);
16042
16043         if (!new_plane_state->uapi.fence) { /* implicit fencing */
16044                 struct dma_fence *fence;
16045
16046                 ret = i915_sw_fence_await_reservation(&state->commit_ready,
16047                                                       obj->base.resv, NULL,
16048                                                       false,
16049                                                       i915_fence_timeout(dev_priv),
16050                                                       GFP_KERNEL);
16051                 if (ret < 0)
16052                         goto unpin_fb;
16053
16054                 fence = dma_resv_get_excl_rcu(obj->base.resv);
16055                 if (fence) {
16056                         add_rps_boost_after_vblank(new_plane_state->hw.crtc,
16057                                                    fence);
16058                         dma_fence_put(fence);
16059                 }
16060         } else {
16061                 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
16062                                            new_plane_state->uapi.fence);
16063         }
16064
16065         /*
16066          * We declare pageflips to be interactive and so merit a small bias
16067          * towards upclocking to deliver the frame on time. By only changing
16068          * the RPS thresholds to sample more regularly and aim for higher
16069          * clocks we can hopefully deliver low power workloads (like kodi)
16070          * that are not quite steady state without resorting to forcing
16071          * maximum clocks following a vblank miss (see do_rps_boost()).
16072          */
16073         if (!state->rps_interactive) {
16074                 intel_rps_mark_interactive(&dev_priv->gt.rps, true);
16075                 state->rps_interactive = true;
16076         }
16077
16078         return 0;
16079
16080 unpin_fb:
16081         intel_plane_unpin_fb(new_plane_state);
16082
16083         return ret;
16084 }
16085
16086 /**
16087  * intel_cleanup_plane_fb - Cleans up an fb after plane use
16088  * @plane: drm plane to clean up for
16089  * @_old_plane_state: the state from the previous modeset
16090  *
16091  * Cleans up a framebuffer that has just been removed from a plane.
16092  */
16093 void
16094 intel_cleanup_plane_fb(struct drm_plane *plane,
16095                        struct drm_plane_state *_old_plane_state)
16096 {
16097         struct intel_plane_state *old_plane_state =
16098                 to_intel_plane_state(_old_plane_state);
16099         struct intel_atomic_state *state =
16100                 to_intel_atomic_state(old_plane_state->uapi.state);
16101         struct drm_i915_private *dev_priv = to_i915(plane->dev);
16102         struct drm_i915_gem_object *obj = intel_fb_obj(old_plane_state->hw.fb);
16103
16104         if (!obj)
16105                 return;
16106
16107         if (state->rps_interactive) {
16108                 intel_rps_mark_interactive(&dev_priv->gt.rps, false);
16109                 state->rps_interactive = false;
16110         }
16111
16112         /* Should only be called after a successful intel_prepare_plane_fb()! */
16113         intel_plane_unpin_fb(old_plane_state);
16114 }
16115
16116 /**
16117  * intel_plane_destroy - destroy a plane
16118  * @plane: plane to destroy
16119  *
16120  * Common destruction function for all types of planes (primary, cursor,
16121  * sprite).
16122  */
16123 void intel_plane_destroy(struct drm_plane *plane)
16124 {
16125         drm_plane_cleanup(plane);
16126         kfree(to_intel_plane(plane));
16127 }
16128
16129 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
16130                                             u32 format, u64 modifier)
16131 {
16132         switch (modifier) {
16133         case DRM_FORMAT_MOD_LINEAR:
16134         case I915_FORMAT_MOD_X_TILED:
16135                 break;
16136         default:
16137                 return false;
16138         }
16139
16140         switch (format) {
16141         case DRM_FORMAT_C8:
16142         case DRM_FORMAT_RGB565:
16143         case DRM_FORMAT_XRGB1555:
16144         case DRM_FORMAT_XRGB8888:
16145                 return modifier == DRM_FORMAT_MOD_LINEAR ||
16146                         modifier == I915_FORMAT_MOD_X_TILED;
16147         default:
16148                 return false;
16149         }
16150 }
16151
16152 static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
16153                                             u32 format, u64 modifier)
16154 {
16155         switch (modifier) {
16156         case DRM_FORMAT_MOD_LINEAR:
16157         case I915_FORMAT_MOD_X_TILED:
16158                 break;
16159         default:
16160                 return false;
16161         }
16162
16163         switch (format) {
16164         case DRM_FORMAT_C8:
16165         case DRM_FORMAT_RGB565:
16166         case DRM_FORMAT_XRGB8888:
16167         case DRM_FORMAT_XBGR8888:
16168         case DRM_FORMAT_ARGB8888:
16169         case DRM_FORMAT_ABGR8888:
16170         case DRM_FORMAT_XRGB2101010:
16171         case DRM_FORMAT_XBGR2101010:
16172         case DRM_FORMAT_ARGB2101010:
16173         case DRM_FORMAT_ABGR2101010:
16174         case DRM_FORMAT_XBGR16161616F:
16175                 return modifier == DRM_FORMAT_MOD_LINEAR ||
16176                         modifier == I915_FORMAT_MOD_X_TILED;
16177         default:
16178                 return false;
16179         }
16180 }
16181
16182 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
16183                                               u32 format, u64 modifier)
16184 {
16185         return modifier == DRM_FORMAT_MOD_LINEAR &&
16186                 format == DRM_FORMAT_ARGB8888;
16187 }
16188
16189 static const struct drm_plane_funcs i965_plane_funcs = {
16190         .update_plane = drm_atomic_helper_update_plane,
16191         .disable_plane = drm_atomic_helper_disable_plane,
16192         .destroy = intel_plane_destroy,
16193         .atomic_duplicate_state = intel_plane_duplicate_state,
16194         .atomic_destroy_state = intel_plane_destroy_state,
16195         .format_mod_supported = i965_plane_format_mod_supported,
16196 };
16197
16198 static const struct drm_plane_funcs i8xx_plane_funcs = {
16199         .update_plane = drm_atomic_helper_update_plane,
16200         .disable_plane = drm_atomic_helper_disable_plane,
16201         .destroy = intel_plane_destroy,
16202         .atomic_duplicate_state = intel_plane_duplicate_state,
16203         .atomic_destroy_state = intel_plane_destroy_state,
16204         .format_mod_supported = i8xx_plane_format_mod_supported,
16205 };
16206
16207 static int
16208 intel_legacy_cursor_update(struct drm_plane *_plane,
16209                            struct drm_crtc *_crtc,
16210                            struct drm_framebuffer *fb,
16211                            int crtc_x, int crtc_y,
16212                            unsigned int crtc_w, unsigned int crtc_h,
16213                            u32 src_x, u32 src_y,
16214                            u32 src_w, u32 src_h,
16215                            struct drm_modeset_acquire_ctx *ctx)
16216 {
16217         struct intel_plane *plane = to_intel_plane(_plane);
16218         struct intel_crtc *crtc = to_intel_crtc(_crtc);
16219         struct intel_plane_state *old_plane_state =
16220                 to_intel_plane_state(plane->base.state);
16221         struct intel_plane_state *new_plane_state;
16222         struct intel_crtc_state *crtc_state =
16223                 to_intel_crtc_state(crtc->base.state);
16224         struct intel_crtc_state *new_crtc_state;
16225         int ret;
16226
16227         /*
16228          * When crtc is inactive or there is a modeset pending,
16229          * wait for it to complete in the slowpath
16230          */
16231         if (!crtc_state->hw.active || needs_modeset(crtc_state) ||
16232             crtc_state->update_pipe)
16233                 goto slow;
16234
16235         /*
16236          * Don't do an async update if there is an outstanding commit modifying
16237          * the plane.  This prevents our async update's changes from getting
16238          * overridden by a previous synchronous update's state.
16239          */
16240         if (old_plane_state->uapi.commit &&
16241             !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done))
16242                 goto slow;
16243
16244         /*
16245          * If any parameters change that may affect watermarks,
16246          * take the slowpath. Only changing fb or position should be
16247          * in the fastpath.
16248          */
16249         if (old_plane_state->uapi.crtc != &crtc->base ||
16250             old_plane_state->uapi.src_w != src_w ||
16251             old_plane_state->uapi.src_h != src_h ||
16252             old_plane_state->uapi.crtc_w != crtc_w ||
16253             old_plane_state->uapi.crtc_h != crtc_h ||
16254             !old_plane_state->uapi.fb != !fb)
16255                 goto slow;
16256
16257         new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base));
16258         if (!new_plane_state)
16259                 return -ENOMEM;
16260
16261         new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base));
16262         if (!new_crtc_state) {
16263                 ret = -ENOMEM;
16264                 goto out_free;
16265         }
16266
16267         drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb);
16268
16269         new_plane_state->uapi.src_x = src_x;
16270         new_plane_state->uapi.src_y = src_y;
16271         new_plane_state->uapi.src_w = src_w;
16272         new_plane_state->uapi.src_h = src_h;
16273         new_plane_state->uapi.crtc_x = crtc_x;
16274         new_plane_state->uapi.crtc_y = crtc_y;
16275         new_plane_state->uapi.crtc_w = crtc_w;
16276         new_plane_state->uapi.crtc_h = crtc_h;
16277
16278         intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state);
16279
16280         ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
16281                                                   old_plane_state, new_plane_state);
16282         if (ret)
16283                 goto out_free;
16284
16285         ret = intel_plane_pin_fb(new_plane_state);
16286         if (ret)
16287                 goto out_free;
16288
16289         intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb),
16290                                 ORIGIN_FLIP);
16291         intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
16292                                 to_intel_frontbuffer(new_plane_state->hw.fb),
16293                                 plane->frontbuffer_bit);
16294
16295         /* Swap plane state */
16296         plane->base.state = &new_plane_state->uapi;
16297
16298         /*
16299          * We cannot swap crtc_state as it may be in use by an atomic commit or
16300          * page flip that's running simultaneously. If we swap crtc_state and
16301          * destroy the old state, we will cause a use-after-free there.
16302          *
16303          * Only update active_planes, which is needed for our internal
16304          * bookkeeping. Either value will do the right thing when updating
16305          * planes atomically. If the cursor was part of the atomic update then
16306          * we would have taken the slowpath.
16307          */
16308         crtc_state->active_planes = new_crtc_state->active_planes;
16309
16310         if (new_plane_state->uapi.visible)
16311                 intel_update_plane(plane, crtc_state, new_plane_state);
16312         else
16313                 intel_disable_plane(plane, crtc_state);
16314
16315         intel_plane_unpin_fb(old_plane_state);
16316
16317 out_free:
16318         if (new_crtc_state)
16319                 intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
16320         if (ret)
16321                 intel_plane_destroy_state(&plane->base, &new_plane_state->uapi);
16322         else
16323                 intel_plane_destroy_state(&plane->base, &old_plane_state->uapi);
16324         return ret;
16325
16326 slow:
16327         return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb,
16328                                               crtc_x, crtc_y, crtc_w, crtc_h,
16329                                               src_x, src_y, src_w, src_h, ctx);
16330 }
16331
16332 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
16333         .update_plane = intel_legacy_cursor_update,
16334         .disable_plane = drm_atomic_helper_disable_plane,
16335         .destroy = intel_plane_destroy,
16336         .atomic_duplicate_state = intel_plane_duplicate_state,
16337         .atomic_destroy_state = intel_plane_destroy_state,
16338         .format_mod_supported = intel_cursor_format_mod_supported,
16339 };
16340
16341 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
16342                                enum i9xx_plane_id i9xx_plane)
16343 {
16344         if (!HAS_FBC(dev_priv))
16345                 return false;
16346
16347         if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
16348                 return i9xx_plane == PLANE_A; /* tied to pipe A */
16349         else if (IS_IVYBRIDGE(dev_priv))
16350                 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
16351                         i9xx_plane == PLANE_C;
16352         else if (INTEL_GEN(dev_priv) >= 4)
16353                 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
16354         else
16355                 return i9xx_plane == PLANE_A;
16356 }
16357
16358 static struct intel_plane *
16359 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
16360 {
16361         struct intel_plane *plane;
16362         const struct drm_plane_funcs *plane_funcs;
16363         unsigned int supported_rotations;
16364         const u32 *formats;
16365         int num_formats;
16366         int ret, zpos;
16367
16368         if (INTEL_GEN(dev_priv) >= 9)
16369                 return skl_universal_plane_create(dev_priv, pipe,
16370                                                   PLANE_PRIMARY);
16371
16372         plane = intel_plane_alloc();
16373         if (IS_ERR(plane))
16374                 return plane;
16375
16376         plane->pipe = pipe;
16377         /*
16378          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
16379          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
16380          */
16381         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4 &&
16382             INTEL_NUM_PIPES(dev_priv) == 2)
16383                 plane->i9xx_plane = (enum i9xx_plane_id) !pipe;
16384         else
16385                 plane->i9xx_plane = (enum i9xx_plane_id) pipe;
16386         plane->id = PLANE_PRIMARY;
16387         plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
16388
16389         plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane);
16390         if (plane->has_fbc) {
16391                 struct intel_fbc *fbc = &dev_priv->fbc;
16392
16393                 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
16394         }
16395
16396         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16397                 formats = vlv_primary_formats;
16398                 num_formats = ARRAY_SIZE(vlv_primary_formats);
16399         } else if (INTEL_GEN(dev_priv) >= 4) {
16400                 /*
16401                  * WaFP16GammaEnabling:ivb
16402                  * "Workaround : When using the 64-bit format, the plane
16403                  *  output on each color channel has one quarter amplitude.
16404                  *  It can be brought up to full amplitude by using pipe
16405                  *  gamma correction or pipe color space conversion to
16406                  *  multiply the plane output by four."
16407                  *
16408                  * There is no dedicated plane gamma for the primary plane,
16409                  * and using the pipe gamma/csc could conflict with other
16410                  * planes, so we choose not to expose fp16 on IVB primary
16411                  * planes. HSW primary planes no longer have this problem.
16412                  */
16413                 if (IS_IVYBRIDGE(dev_priv)) {
16414                         formats = ivb_primary_formats;
16415                         num_formats = ARRAY_SIZE(ivb_primary_formats);
16416                 } else {
16417                         formats = i965_primary_formats;
16418                         num_formats = ARRAY_SIZE(i965_primary_formats);
16419                 }
16420         } else {
16421                 formats = i8xx_primary_formats;
16422                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
16423         }
16424
16425         if (INTEL_GEN(dev_priv) >= 4)
16426                 plane_funcs = &i965_plane_funcs;
16427         else
16428                 plane_funcs = &i8xx_plane_funcs;
16429
16430         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16431                 plane->min_cdclk = vlv_plane_min_cdclk;
16432         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
16433                 plane->min_cdclk = hsw_plane_min_cdclk;
16434         else if (IS_IVYBRIDGE(dev_priv))
16435                 plane->min_cdclk = ivb_plane_min_cdclk;
16436         else
16437                 plane->min_cdclk = i9xx_plane_min_cdclk;
16438
16439         plane->max_stride = i9xx_plane_max_stride;
16440         plane->update_plane = i9xx_update_plane;
16441         plane->disable_plane = i9xx_disable_plane;
16442         plane->get_hw_state = i9xx_plane_get_hw_state;
16443         plane->check_plane = i9xx_plane_check;
16444
16445         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
16446                 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
16447                                                0, plane_funcs,
16448                                                formats, num_formats,
16449                                                i9xx_format_modifiers,
16450                                                DRM_PLANE_TYPE_PRIMARY,
16451                                                "primary %c", pipe_name(pipe));
16452         else
16453                 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
16454                                                0, plane_funcs,
16455                                                formats, num_formats,
16456                                                i9xx_format_modifiers,
16457                                                DRM_PLANE_TYPE_PRIMARY,
16458                                                "plane %c",
16459                                                plane_name(plane->i9xx_plane));
16460         if (ret)
16461                 goto fail;
16462
16463         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
16464                 supported_rotations =
16465                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
16466                         DRM_MODE_REFLECT_X;
16467         } else if (INTEL_GEN(dev_priv) >= 4) {
16468                 supported_rotations =
16469                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
16470         } else {
16471                 supported_rotations = DRM_MODE_ROTATE_0;
16472         }
16473
16474         if (INTEL_GEN(dev_priv) >= 4)
16475                 drm_plane_create_rotation_property(&plane->base,
16476                                                    DRM_MODE_ROTATE_0,
16477                                                    supported_rotations);
16478
16479         zpos = 0;
16480         drm_plane_create_zpos_immutable_property(&plane->base, zpos);
16481
16482         drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
16483
16484         return plane;
16485
16486 fail:
16487         intel_plane_free(plane);
16488
16489         return ERR_PTR(ret);
16490 }
16491
16492 static struct intel_plane *
16493 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
16494                           enum pipe pipe)
16495 {
16496         struct intel_plane *cursor;
16497         int ret, zpos;
16498
16499         cursor = intel_plane_alloc();
16500         if (IS_ERR(cursor))
16501                 return cursor;
16502
16503         cursor->pipe = pipe;
16504         cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
16505         cursor->id = PLANE_CURSOR;
16506         cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
16507
16508         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
16509                 cursor->max_stride = i845_cursor_max_stride;
16510                 cursor->update_plane = i845_update_cursor;
16511                 cursor->disable_plane = i845_disable_cursor;
16512                 cursor->get_hw_state = i845_cursor_get_hw_state;
16513                 cursor->check_plane = i845_check_cursor;
16514         } else {
16515                 cursor->max_stride = i9xx_cursor_max_stride;
16516                 cursor->update_plane = i9xx_update_cursor;
16517                 cursor->disable_plane = i9xx_disable_cursor;
16518                 cursor->get_hw_state = i9xx_cursor_get_hw_state;
16519                 cursor->check_plane = i9xx_check_cursor;
16520         }
16521
16522         cursor->cursor.base = ~0;
16523         cursor->cursor.cntl = ~0;
16524
16525         if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
16526                 cursor->cursor.size = ~0;
16527
16528         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
16529                                        0, &intel_cursor_plane_funcs,
16530                                        intel_cursor_formats,
16531                                        ARRAY_SIZE(intel_cursor_formats),
16532                                        cursor_format_modifiers,
16533                                        DRM_PLANE_TYPE_CURSOR,
16534                                        "cursor %c", pipe_name(pipe));
16535         if (ret)
16536                 goto fail;
16537
16538         if (INTEL_GEN(dev_priv) >= 4)
16539                 drm_plane_create_rotation_property(&cursor->base,
16540                                                    DRM_MODE_ROTATE_0,
16541                                                    DRM_MODE_ROTATE_0 |
16542                                                    DRM_MODE_ROTATE_180);
16543
16544         zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
16545         drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
16546
16547         if (INTEL_GEN(dev_priv) >= 12)
16548                 drm_plane_enable_fb_damage_clips(&cursor->base);
16549
16550         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
16551
16552         return cursor;
16553
16554 fail:
16555         intel_plane_free(cursor);
16556
16557         return ERR_PTR(ret);
16558 }
16559
16560 #define INTEL_CRTC_FUNCS \
16561         .gamma_set = drm_atomic_helper_legacy_gamma_set, \
16562         .set_config = drm_atomic_helper_set_config, \
16563         .destroy = intel_crtc_destroy, \
16564         .page_flip = drm_atomic_helper_page_flip, \
16565         .atomic_duplicate_state = intel_crtc_duplicate_state, \
16566         .atomic_destroy_state = intel_crtc_destroy_state, \
16567         .set_crc_source = intel_crtc_set_crc_source, \
16568         .verify_crc_source = intel_crtc_verify_crc_source, \
16569         .get_crc_sources = intel_crtc_get_crc_sources
16570
16571 static const struct drm_crtc_funcs bdw_crtc_funcs = {
16572         INTEL_CRTC_FUNCS,
16573
16574         .get_vblank_counter = g4x_get_vblank_counter,
16575         .enable_vblank = bdw_enable_vblank,
16576         .disable_vblank = bdw_disable_vblank,
16577         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16578 };
16579
16580 static const struct drm_crtc_funcs ilk_crtc_funcs = {
16581         INTEL_CRTC_FUNCS,
16582
16583         .get_vblank_counter = g4x_get_vblank_counter,
16584         .enable_vblank = ilk_enable_vblank,
16585         .disable_vblank = ilk_disable_vblank,
16586         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16587 };
16588
16589 static const struct drm_crtc_funcs g4x_crtc_funcs = {
16590         INTEL_CRTC_FUNCS,
16591
16592         .get_vblank_counter = g4x_get_vblank_counter,
16593         .enable_vblank = i965_enable_vblank,
16594         .disable_vblank = i965_disable_vblank,
16595         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16596 };
16597
16598 static const struct drm_crtc_funcs i965_crtc_funcs = {
16599         INTEL_CRTC_FUNCS,
16600
16601         .get_vblank_counter = i915_get_vblank_counter,
16602         .enable_vblank = i965_enable_vblank,
16603         .disable_vblank = i965_disable_vblank,
16604         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16605 };
16606
16607 static const struct drm_crtc_funcs i915gm_crtc_funcs = {
16608         INTEL_CRTC_FUNCS,
16609
16610         .get_vblank_counter = i915_get_vblank_counter,
16611         .enable_vblank = i915gm_enable_vblank,
16612         .disable_vblank = i915gm_disable_vblank,
16613         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16614 };
16615
16616 static const struct drm_crtc_funcs i915_crtc_funcs = {
16617         INTEL_CRTC_FUNCS,
16618
16619         .get_vblank_counter = i915_get_vblank_counter,
16620         .enable_vblank = i8xx_enable_vblank,
16621         .disable_vblank = i8xx_disable_vblank,
16622         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16623 };
16624
16625 static const struct drm_crtc_funcs i8xx_crtc_funcs = {
16626         INTEL_CRTC_FUNCS,
16627
16628         /* no hw vblank counter */
16629         .enable_vblank = i8xx_enable_vblank,
16630         .disable_vblank = i8xx_disable_vblank,
16631         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16632 };
16633
16634 static struct intel_crtc *intel_crtc_alloc(void)
16635 {
16636         struct intel_crtc_state *crtc_state;
16637         struct intel_crtc *crtc;
16638
16639         crtc = kzalloc(sizeof(*crtc), GFP_KERNEL);
16640         if (!crtc)
16641                 return ERR_PTR(-ENOMEM);
16642
16643         crtc_state = intel_crtc_state_alloc(crtc);
16644         if (!crtc_state) {
16645                 kfree(crtc);
16646                 return ERR_PTR(-ENOMEM);
16647         }
16648
16649         crtc->base.state = &crtc_state->uapi;
16650         crtc->config = crtc_state;
16651
16652         return crtc;
16653 }
16654
16655 static void intel_crtc_free(struct intel_crtc *crtc)
16656 {
16657         intel_crtc_destroy_state(&crtc->base, crtc->base.state);
16658         kfree(crtc);
16659 }
16660
16661 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv)
16662 {
16663         struct intel_plane *plane;
16664
16665         for_each_intel_plane(&dev_priv->drm, plane) {
16666                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
16667                                                                   plane->pipe);
16668
16669                 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base);
16670         }
16671 }
16672
16673 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
16674 {
16675         struct intel_plane *primary, *cursor;
16676         const struct drm_crtc_funcs *funcs;
16677         struct intel_crtc *crtc;
16678         int sprite, ret;
16679
16680         crtc = intel_crtc_alloc();
16681         if (IS_ERR(crtc))
16682                 return PTR_ERR(crtc);
16683
16684         crtc->pipe = pipe;
16685         crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[pipe];
16686
16687         primary = intel_primary_plane_create(dev_priv, pipe);
16688         if (IS_ERR(primary)) {
16689                 ret = PTR_ERR(primary);
16690                 goto fail;
16691         }
16692         crtc->plane_ids_mask |= BIT(primary->id);
16693
16694         for_each_sprite(dev_priv, pipe, sprite) {
16695                 struct intel_plane *plane;
16696
16697                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
16698                 if (IS_ERR(plane)) {
16699                         ret = PTR_ERR(plane);
16700                         goto fail;
16701                 }
16702                 crtc->plane_ids_mask |= BIT(plane->id);
16703         }
16704
16705         cursor = intel_cursor_plane_create(dev_priv, pipe);
16706         if (IS_ERR(cursor)) {
16707                 ret = PTR_ERR(cursor);
16708                 goto fail;
16709         }
16710         crtc->plane_ids_mask |= BIT(cursor->id);
16711
16712         if (HAS_GMCH(dev_priv)) {
16713                 if (IS_CHERRYVIEW(dev_priv) ||
16714                     IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv))
16715                         funcs = &g4x_crtc_funcs;
16716                 else if (IS_GEN(dev_priv, 4))
16717                         funcs = &i965_crtc_funcs;
16718                 else if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv))
16719                         funcs = &i915gm_crtc_funcs;
16720                 else if (IS_GEN(dev_priv, 3))
16721                         funcs = &i915_crtc_funcs;
16722                 else
16723                         funcs = &i8xx_crtc_funcs;
16724         } else {
16725                 if (INTEL_GEN(dev_priv) >= 8)
16726                         funcs = &bdw_crtc_funcs;
16727                 else
16728                         funcs = &ilk_crtc_funcs;
16729         }
16730
16731         ret = drm_crtc_init_with_planes(&dev_priv->drm, &crtc->base,
16732                                         &primary->base, &cursor->base,
16733                                         funcs, "pipe %c", pipe_name(pipe));
16734         if (ret)
16735                 goto fail;
16736
16737         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
16738                dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
16739         dev_priv->pipe_to_crtc_mapping[pipe] = crtc;
16740
16741         if (INTEL_GEN(dev_priv) < 9) {
16742                 enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
16743
16744                 BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
16745                        dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
16746                 dev_priv->plane_to_crtc_mapping[i9xx_plane] = crtc;
16747         }
16748
16749         intel_color_init(crtc);
16750
16751         intel_crtc_crc_init(crtc);
16752
16753         drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) != crtc->pipe);
16754
16755         return 0;
16756
16757 fail:
16758         intel_crtc_free(crtc);
16759
16760         return ret;
16761 }
16762
16763 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
16764                                       struct drm_file *file)
16765 {
16766         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
16767         struct drm_crtc *drmmode_crtc;
16768         struct intel_crtc *crtc;
16769
16770         drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
16771         if (!drmmode_crtc)
16772                 return -ENOENT;
16773
16774         crtc = to_intel_crtc(drmmode_crtc);
16775         pipe_from_crtc_id->pipe = crtc->pipe;
16776
16777         return 0;
16778 }
16779
16780 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
16781 {
16782         struct drm_device *dev = encoder->base.dev;
16783         struct intel_encoder *source_encoder;
16784         u32 possible_clones = 0;
16785
16786         for_each_intel_encoder(dev, source_encoder) {
16787                 if (encoders_cloneable(encoder, source_encoder))
16788                         possible_clones |= drm_encoder_mask(&source_encoder->base);
16789         }
16790
16791         return possible_clones;
16792 }
16793
16794 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
16795 {
16796         struct drm_device *dev = encoder->base.dev;
16797         struct intel_crtc *crtc;
16798         u32 possible_crtcs = 0;
16799
16800         for_each_intel_crtc(dev, crtc) {
16801                 if (encoder->pipe_mask & BIT(crtc->pipe))
16802                         possible_crtcs |= drm_crtc_mask(&crtc->base);
16803         }
16804
16805         return possible_crtcs;
16806 }
16807
16808 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
16809 {
16810         if (!IS_MOBILE(dev_priv))
16811                 return false;
16812
16813         if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)
16814                 return false;
16815
16816         if (IS_GEN(dev_priv, 5) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
16817                 return false;
16818
16819         return true;
16820 }
16821
16822 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
16823 {
16824         if (INTEL_GEN(dev_priv) >= 9)
16825                 return false;
16826
16827         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
16828                 return false;
16829
16830         if (HAS_PCH_LPT_H(dev_priv) &&
16831             intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
16832                 return false;
16833
16834         /* DDI E can't be used if DDI A requires 4 lanes */
16835         if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
16836                 return false;
16837
16838         if (!dev_priv->vbt.int_crt_support)
16839                 return false;
16840
16841         return true;
16842 }
16843
16844 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
16845 {
16846         int pps_num;
16847         int pps_idx;
16848
16849         if (HAS_DDI(dev_priv))
16850                 return;
16851         /*
16852          * This w/a is needed at least on CPT/PPT, but to be sure apply it
16853          * everywhere where registers can be write protected.
16854          */
16855         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16856                 pps_num = 2;
16857         else
16858                 pps_num = 1;
16859
16860         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
16861                 u32 val = intel_de_read(dev_priv, PP_CONTROL(pps_idx));
16862
16863                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
16864                 intel_de_write(dev_priv, PP_CONTROL(pps_idx), val);
16865         }
16866 }
16867
16868 static void intel_pps_init(struct drm_i915_private *dev_priv)
16869 {
16870         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
16871                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
16872         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16873                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
16874         else
16875                 dev_priv->pps_mmio_base = PPS_BASE;
16876
16877         intel_pps_unlock_regs_wa(dev_priv);
16878 }
16879
16880 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
16881 {
16882         struct intel_encoder *encoder;
16883         bool dpd_is_edp = false;
16884
16885         intel_pps_init(dev_priv);
16886
16887         if (!HAS_DISPLAY(dev_priv))
16888                 return;
16889
16890         if (IS_ROCKETLAKE(dev_priv)) {
16891                 intel_ddi_init(dev_priv, PORT_A);
16892                 intel_ddi_init(dev_priv, PORT_B);
16893                 intel_ddi_init(dev_priv, PORT_D);       /* DDI TC1 */
16894                 intel_ddi_init(dev_priv, PORT_E);       /* DDI TC2 */
16895         } else if (INTEL_GEN(dev_priv) >= 12) {
16896                 intel_ddi_init(dev_priv, PORT_A);
16897                 intel_ddi_init(dev_priv, PORT_B);
16898                 intel_ddi_init(dev_priv, PORT_D);
16899                 intel_ddi_init(dev_priv, PORT_E);
16900                 intel_ddi_init(dev_priv, PORT_F);
16901                 intel_ddi_init(dev_priv, PORT_G);
16902                 intel_ddi_init(dev_priv, PORT_H);
16903                 intel_ddi_init(dev_priv, PORT_I);
16904                 icl_dsi_init(dev_priv);
16905         } else if (IS_ELKHARTLAKE(dev_priv)) {
16906                 intel_ddi_init(dev_priv, PORT_A);
16907                 intel_ddi_init(dev_priv, PORT_B);
16908                 intel_ddi_init(dev_priv, PORT_C);
16909                 intel_ddi_init(dev_priv, PORT_D);
16910                 icl_dsi_init(dev_priv);
16911         } else if (IS_GEN(dev_priv, 11)) {
16912                 intel_ddi_init(dev_priv, PORT_A);
16913                 intel_ddi_init(dev_priv, PORT_B);
16914                 intel_ddi_init(dev_priv, PORT_C);
16915                 intel_ddi_init(dev_priv, PORT_D);
16916                 intel_ddi_init(dev_priv, PORT_E);
16917                 /*
16918                  * On some ICL SKUs port F is not present. No strap bits for
16919                  * this, so rely on VBT.
16920                  * Work around broken VBTs on SKUs known to have no port F.
16921                  */
16922                 if (IS_ICL_WITH_PORT_F(dev_priv) &&
16923                     intel_bios_is_port_present(dev_priv, PORT_F))
16924                         intel_ddi_init(dev_priv, PORT_F);
16925
16926                 icl_dsi_init(dev_priv);
16927         } else if (IS_GEN9_LP(dev_priv)) {
16928                 /*
16929                  * FIXME: Broxton doesn't support port detection via the
16930                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
16931                  * detect the ports.
16932                  */
16933                 intel_ddi_init(dev_priv, PORT_A);
16934                 intel_ddi_init(dev_priv, PORT_B);
16935                 intel_ddi_init(dev_priv, PORT_C);
16936
16937                 vlv_dsi_init(dev_priv);
16938         } else if (HAS_DDI(dev_priv)) {
16939                 int found;
16940
16941                 if (intel_ddi_crt_present(dev_priv))
16942                         intel_crt_init(dev_priv);
16943
16944                 /*
16945                  * Haswell uses DDI functions to detect digital outputs.
16946                  * On SKL pre-D0 the strap isn't connected, so we assume
16947                  * it's there.
16948                  */
16949                 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
16950                 /* WaIgnoreDDIAStrap: skl */
16951                 if (found || IS_GEN9_BC(dev_priv))
16952                         intel_ddi_init(dev_priv, PORT_A);
16953
16954                 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
16955                  * register */
16956                 found = intel_de_read(dev_priv, SFUSE_STRAP);
16957
16958                 if (found & SFUSE_STRAP_DDIB_DETECTED)
16959                         intel_ddi_init(dev_priv, PORT_B);
16960                 if (found & SFUSE_STRAP_DDIC_DETECTED)
16961                         intel_ddi_init(dev_priv, PORT_C);
16962                 if (found & SFUSE_STRAP_DDID_DETECTED)
16963                         intel_ddi_init(dev_priv, PORT_D);
16964                 if (found & SFUSE_STRAP_DDIF_DETECTED)
16965                         intel_ddi_init(dev_priv, PORT_F);
16966                 /*
16967                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
16968                  */
16969                 if (IS_GEN9_BC(dev_priv) &&
16970                     intel_bios_is_port_present(dev_priv, PORT_E))
16971                         intel_ddi_init(dev_priv, PORT_E);
16972
16973         } else if (HAS_PCH_SPLIT(dev_priv)) {
16974                 int found;
16975
16976                 /*
16977                  * intel_edp_init_connector() depends on this completing first,
16978                  * to prevent the registration of both eDP and LVDS and the
16979                  * incorrect sharing of the PPS.
16980                  */
16981                 intel_lvds_init(dev_priv);
16982                 intel_crt_init(dev_priv);
16983
16984                 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
16985
16986                 if (ilk_has_edp_a(dev_priv))
16987                         intel_dp_init(dev_priv, DP_A, PORT_A);
16988
16989                 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
16990                         /* PCH SDVOB multiplex with HDMIB */
16991                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
16992                         if (!found)
16993                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
16994                         if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
16995                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
16996                 }
16997
16998                 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
16999                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
17000
17001                 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED)
17002                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
17003
17004                 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
17005                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
17006
17007                 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
17008                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
17009         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
17010                 bool has_edp, has_port;
17011
17012                 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
17013                         intel_crt_init(dev_priv);
17014
17015                 /*
17016                  * The DP_DETECTED bit is the latched state of the DDC
17017                  * SDA pin at boot. However since eDP doesn't require DDC
17018                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
17019                  * eDP ports may have been muxed to an alternate function.
17020                  * Thus we can't rely on the DP_DETECTED bit alone to detect
17021                  * eDP ports. Consult the VBT as well as DP_DETECTED to
17022                  * detect eDP ports.
17023                  *
17024                  * Sadly the straps seem to be missing sometimes even for HDMI
17025                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
17026                  * and VBT for the presence of the port. Additionally we can't
17027                  * trust the port type the VBT declares as we've seen at least
17028                  * HDMI ports that the VBT claim are DP or eDP.
17029                  */
17030                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
17031                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
17032                 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
17033                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
17034                 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
17035                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
17036
17037                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
17038                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
17039                 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
17040                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
17041                 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
17042                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
17043
17044                 if (IS_CHERRYVIEW(dev_priv)) {
17045                         /*
17046                          * eDP not supported on port D,
17047                          * so no need to worry about it
17048                          */
17049                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
17050                         if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
17051                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
17052                         if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
17053                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
17054                 }
17055
17056                 vlv_dsi_init(dev_priv);
17057         } else if (IS_PINEVIEW(dev_priv)) {
17058                 intel_lvds_init(dev_priv);
17059                 intel_crt_init(dev_priv);
17060         } else if (IS_GEN_RANGE(dev_priv, 3, 4)) {
17061                 bool found = false;
17062
17063                 if (IS_MOBILE(dev_priv))
17064                         intel_lvds_init(dev_priv);
17065
17066                 intel_crt_init(dev_priv);
17067
17068                 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
17069                         drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
17070                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
17071                         if (!found && IS_G4X(dev_priv)) {
17072                                 drm_dbg_kms(&dev_priv->drm,
17073                                             "probing HDMI on SDVOB\n");
17074                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
17075                         }
17076
17077                         if (!found && IS_G4X(dev_priv))
17078                                 intel_dp_init(dev_priv, DP_B, PORT_B);
17079                 }
17080
17081                 /* Before G4X SDVOC doesn't have its own detect register */
17082
17083                 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
17084                         drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");
17085                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
17086                 }
17087
17088                 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) {
17089
17090                         if (IS_G4X(dev_priv)) {
17091                                 drm_dbg_kms(&dev_priv->drm,
17092                                             "probing HDMI on SDVOC\n");
17093                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
17094                         }
17095                         if (IS_G4X(dev_priv))
17096                                 intel_dp_init(dev_priv, DP_C, PORT_C);
17097                 }
17098
17099                 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED))
17100                         intel_dp_init(dev_priv, DP_D, PORT_D);
17101
17102                 if (SUPPORTS_TV(dev_priv))
17103                         intel_tv_init(dev_priv);
17104         } else if (IS_GEN(dev_priv, 2)) {
17105                 if (IS_I85X(dev_priv))
17106                         intel_lvds_init(dev_priv);
17107
17108                 intel_crt_init(dev_priv);
17109                 intel_dvo_init(dev_priv);
17110         }
17111
17112         intel_psr_init(dev_priv);
17113
17114         for_each_intel_encoder(&dev_priv->drm, encoder) {
17115                 encoder->base.possible_crtcs =
17116                         intel_encoder_possible_crtcs(encoder);
17117                 encoder->base.possible_clones =
17118                         intel_encoder_possible_clones(encoder);
17119         }
17120
17121         intel_init_pch_refclk(dev_priv);
17122
17123         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
17124 }
17125
17126 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
17127 {
17128         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
17129
17130         drm_framebuffer_cleanup(fb);
17131         intel_frontbuffer_put(intel_fb->frontbuffer);
17132
17133         kfree(intel_fb);
17134 }
17135
17136 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
17137                                                 struct drm_file *file,
17138                                                 unsigned int *handle)
17139 {
17140         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
17141         struct drm_i915_private *i915 = to_i915(obj->base.dev);
17142
17143         if (obj->userptr.mm) {
17144                 drm_dbg(&i915->drm,
17145                         "attempting to use a userptr for a framebuffer, denied\n");
17146                 return -EINVAL;
17147         }
17148
17149         return drm_gem_handle_create(file, &obj->base, handle);
17150 }
17151
17152 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
17153                                         struct drm_file *file,
17154                                         unsigned flags, unsigned color,
17155                                         struct drm_clip_rect *clips,
17156                                         unsigned num_clips)
17157 {
17158         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
17159
17160         i915_gem_object_flush_if_display(obj);
17161         intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
17162
17163         return 0;
17164 }
17165
17166 static const struct drm_framebuffer_funcs intel_fb_funcs = {
17167         .destroy = intel_user_framebuffer_destroy,
17168         .create_handle = intel_user_framebuffer_create_handle,
17169         .dirty = intel_user_framebuffer_dirty,
17170 };
17171
17172 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
17173                                   struct drm_i915_gem_object *obj,
17174                                   struct drm_mode_fb_cmd2 *mode_cmd)
17175 {
17176         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
17177         struct drm_framebuffer *fb = &intel_fb->base;
17178         u32 max_stride;
17179         unsigned int tiling, stride;
17180         int ret = -EINVAL;
17181         int i;
17182
17183         intel_fb->frontbuffer = intel_frontbuffer_get(obj);
17184         if (!intel_fb->frontbuffer)
17185                 return -ENOMEM;
17186
17187         i915_gem_object_lock(obj, NULL);
17188         tiling = i915_gem_object_get_tiling(obj);
17189         stride = i915_gem_object_get_stride(obj);
17190         i915_gem_object_unlock(obj);
17191
17192         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
17193                 /*
17194                  * If there's a fence, enforce that
17195                  * the fb modifier and tiling mode match.
17196                  */
17197                 if (tiling != I915_TILING_NONE &&
17198                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
17199                         drm_dbg_kms(&dev_priv->drm,
17200                                     "tiling_mode doesn't match fb modifier\n");
17201                         goto err;
17202                 }
17203         } else {
17204                 if (tiling == I915_TILING_X) {
17205                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
17206                 } else if (tiling == I915_TILING_Y) {
17207                         drm_dbg_kms(&dev_priv->drm,
17208                                     "No Y tiling for legacy addfb\n");
17209                         goto err;
17210                 }
17211         }
17212
17213         if (!drm_any_plane_has_format(&dev_priv->drm,
17214                                       mode_cmd->pixel_format,
17215                                       mode_cmd->modifier[0])) {
17216                 struct drm_format_name_buf format_name;
17217
17218                 drm_dbg_kms(&dev_priv->drm,
17219                             "unsupported pixel format %s / modifier 0x%llx\n",
17220                             drm_get_format_name(mode_cmd->pixel_format,
17221                                                 &format_name),
17222                             mode_cmd->modifier[0]);
17223                 goto err;
17224         }
17225
17226         /*
17227          * gen2/3 display engine uses the fence if present,
17228          * so the tiling mode must match the fb modifier exactly.
17229          */
17230         if (INTEL_GEN(dev_priv) < 4 &&
17231             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
17232                 drm_dbg_kms(&dev_priv->drm,
17233                             "tiling_mode must match fb modifier exactly on gen2/3\n");
17234                 goto err;
17235         }
17236
17237         max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
17238                                          mode_cmd->modifier[0]);
17239         if (mode_cmd->pitches[0] > max_stride) {
17240                 drm_dbg_kms(&dev_priv->drm,
17241                             "%s pitch (%u) must be at most %d\n",
17242                             mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
17243                             "tiled" : "linear",
17244                             mode_cmd->pitches[0], max_stride);
17245                 goto err;
17246         }
17247
17248         /*
17249          * If there's a fence, enforce that
17250          * the fb pitch and fence stride match.
17251          */
17252         if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
17253                 drm_dbg_kms(&dev_priv->drm,
17254                             "pitch (%d) must match tiling stride (%d)\n",
17255                             mode_cmd->pitches[0], stride);
17256                 goto err;
17257         }
17258
17259         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
17260         if (mode_cmd->offsets[0] != 0) {
17261                 drm_dbg_kms(&dev_priv->drm,
17262                             "plane 0 offset (0x%08x) must be 0\n",
17263                             mode_cmd->offsets[0]);
17264                 goto err;
17265         }
17266
17267         drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
17268
17269         for (i = 0; i < fb->format->num_planes; i++) {
17270                 u32 stride_alignment;
17271
17272                 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
17273                         drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n",
17274                                     i);
17275                         goto err;
17276                 }
17277
17278                 stride_alignment = intel_fb_stride_alignment(fb, i);
17279                 if (fb->pitches[i] & (stride_alignment - 1)) {
17280                         drm_dbg_kms(&dev_priv->drm,
17281                                     "plane %d pitch (%d) must be at least %u byte aligned\n",
17282                                     i, fb->pitches[i], stride_alignment);
17283                         goto err;
17284                 }
17285
17286                 if (is_gen12_ccs_plane(fb, i)) {
17287                         int ccs_aux_stride = gen12_ccs_aux_stride(fb, i);
17288
17289                         if (fb->pitches[i] != ccs_aux_stride) {
17290                                 drm_dbg_kms(&dev_priv->drm,
17291                                             "ccs aux plane %d pitch (%d) must be %d\n",
17292                                             i,
17293                                             fb->pitches[i], ccs_aux_stride);
17294                                 goto err;
17295                         }
17296                 }
17297
17298                 fb->obj[i] = &obj->base;
17299         }
17300
17301         ret = intel_fill_fb_info(dev_priv, fb);
17302         if (ret)
17303                 goto err;
17304
17305         ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
17306         if (ret) {
17307                 drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret);
17308                 goto err;
17309         }
17310
17311         return 0;
17312
17313 err:
17314         intel_frontbuffer_put(intel_fb->frontbuffer);
17315         return ret;
17316 }
17317
17318 static struct drm_framebuffer *
17319 intel_user_framebuffer_create(struct drm_device *dev,
17320                               struct drm_file *filp,
17321                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
17322 {
17323         struct drm_framebuffer *fb;
17324         struct drm_i915_gem_object *obj;
17325         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
17326
17327         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
17328         if (!obj)
17329                 return ERR_PTR(-ENOENT);
17330
17331         fb = intel_framebuffer_create(obj, &mode_cmd);
17332         i915_gem_object_put(obj);
17333
17334         return fb;
17335 }
17336
17337 static enum drm_mode_status
17338 intel_mode_valid(struct drm_device *dev,
17339                  const struct drm_display_mode *mode)
17340 {
17341         struct drm_i915_private *dev_priv = to_i915(dev);
17342         int hdisplay_max, htotal_max;
17343         int vdisplay_max, vtotal_max;
17344
17345         /*
17346          * Can't reject DBLSCAN here because Xorg ddxen can add piles
17347          * of DBLSCAN modes to the output's mode list when they detect
17348          * the scaling mode property on the connector. And they don't
17349          * ask the kernel to validate those modes in any way until
17350          * modeset time at which point the client gets a protocol error.
17351          * So in order to not upset those clients we silently ignore the
17352          * DBLSCAN flag on such connectors. For other connectors we will
17353          * reject modes with the DBLSCAN flag in encoder->compute_config().
17354          * And we always reject DBLSCAN modes in connector->mode_valid()
17355          * as we never want such modes on the connector's mode list.
17356          */
17357
17358         if (mode->vscan > 1)
17359                 return MODE_NO_VSCAN;
17360
17361         if (mode->flags & DRM_MODE_FLAG_HSKEW)
17362                 return MODE_H_ILLEGAL;
17363
17364         if (mode->flags & (DRM_MODE_FLAG_CSYNC |
17365                            DRM_MODE_FLAG_NCSYNC |
17366                            DRM_MODE_FLAG_PCSYNC))
17367                 return MODE_HSYNC;
17368
17369         if (mode->flags & (DRM_MODE_FLAG_BCAST |
17370                            DRM_MODE_FLAG_PIXMUX |
17371                            DRM_MODE_FLAG_CLKDIV2))
17372                 return MODE_BAD;
17373
17374         /* Transcoder timing limits */
17375         if (INTEL_GEN(dev_priv) >= 11) {
17376                 hdisplay_max = 16384;
17377                 vdisplay_max = 8192;
17378                 htotal_max = 16384;
17379                 vtotal_max = 8192;
17380         } else if (INTEL_GEN(dev_priv) >= 9 ||
17381                    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
17382                 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
17383                 vdisplay_max = 4096;
17384                 htotal_max = 8192;
17385                 vtotal_max = 8192;
17386         } else if (INTEL_GEN(dev_priv) >= 3) {
17387                 hdisplay_max = 4096;
17388                 vdisplay_max = 4096;
17389                 htotal_max = 8192;
17390                 vtotal_max = 8192;
17391         } else {
17392                 hdisplay_max = 2048;
17393                 vdisplay_max = 2048;
17394                 htotal_max = 4096;
17395                 vtotal_max = 4096;
17396         }
17397
17398         if (mode->hdisplay > hdisplay_max ||
17399             mode->hsync_start > htotal_max ||
17400             mode->hsync_end > htotal_max ||
17401             mode->htotal > htotal_max)
17402                 return MODE_H_ILLEGAL;
17403
17404         if (mode->vdisplay > vdisplay_max ||
17405             mode->vsync_start > vtotal_max ||
17406             mode->vsync_end > vtotal_max ||
17407             mode->vtotal > vtotal_max)
17408                 return MODE_V_ILLEGAL;
17409
17410         if (INTEL_GEN(dev_priv) >= 5) {
17411                 if (mode->hdisplay < 64 ||
17412                     mode->htotal - mode->hdisplay < 32)
17413                         return MODE_H_ILLEGAL;
17414
17415                 if (mode->vtotal - mode->vdisplay < 5)
17416                         return MODE_V_ILLEGAL;
17417         } else {
17418                 if (mode->htotal - mode->hdisplay < 32)
17419                         return MODE_H_ILLEGAL;
17420
17421                 if (mode->vtotal - mode->vdisplay < 3)
17422                         return MODE_V_ILLEGAL;
17423         }
17424
17425         return MODE_OK;
17426 }
17427
17428 enum drm_mode_status
17429 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
17430                                 const struct drm_display_mode *mode)
17431 {
17432         int plane_width_max, plane_height_max;
17433
17434         /*
17435          * intel_mode_valid() should be
17436          * sufficient on older platforms.
17437          */
17438         if (INTEL_GEN(dev_priv) < 9)
17439                 return MODE_OK;
17440
17441         /*
17442          * Most people will probably want a fullscreen
17443          * plane so let's not advertize modes that are
17444          * too big for that.
17445          */
17446         if (INTEL_GEN(dev_priv) >= 11) {
17447                 plane_width_max = 5120;
17448                 plane_height_max = 4320;
17449         } else {
17450                 plane_width_max = 5120;
17451                 plane_height_max = 4096;
17452         }
17453
17454         if (mode->hdisplay > plane_width_max)
17455                 return MODE_H_ILLEGAL;
17456
17457         if (mode->vdisplay > plane_height_max)
17458                 return MODE_V_ILLEGAL;
17459
17460         return MODE_OK;
17461 }
17462
17463 static const struct drm_mode_config_funcs intel_mode_funcs = {
17464         .fb_create = intel_user_framebuffer_create,
17465         .get_format_info = intel_get_format_info,
17466         .output_poll_changed = intel_fbdev_output_poll_changed,
17467         .mode_valid = intel_mode_valid,
17468         .atomic_check = intel_atomic_check,
17469         .atomic_commit = intel_atomic_commit,
17470         .atomic_state_alloc = intel_atomic_state_alloc,
17471         .atomic_state_clear = intel_atomic_state_clear,
17472         .atomic_state_free = intel_atomic_state_free,
17473 };
17474
17475 /**
17476  * intel_init_display_hooks - initialize the display modesetting hooks
17477  * @dev_priv: device private
17478  */
17479 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
17480 {
17481         intel_init_cdclk_hooks(dev_priv);
17482
17483         if (INTEL_GEN(dev_priv) >= 9) {
17484                 dev_priv->display.get_pipe_config = hsw_get_pipe_config;
17485                 dev_priv->display.get_initial_plane_config =
17486                         skl_get_initial_plane_config;
17487                 dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock;
17488                 dev_priv->display.crtc_enable = hsw_crtc_enable;
17489                 dev_priv->display.crtc_disable = hsw_crtc_disable;
17490         } else if (HAS_DDI(dev_priv)) {
17491                 dev_priv->display.get_pipe_config = hsw_get_pipe_config;
17492                 dev_priv->display.get_initial_plane_config =
17493                         i9xx_get_initial_plane_config;
17494                 dev_priv->display.crtc_compute_clock =
17495                         hsw_crtc_compute_clock;
17496                 dev_priv->display.crtc_enable = hsw_crtc_enable;
17497                 dev_priv->display.crtc_disable = hsw_crtc_disable;
17498         } else if (HAS_PCH_SPLIT(dev_priv)) {
17499                 dev_priv->display.get_pipe_config = ilk_get_pipe_config;
17500                 dev_priv->display.get_initial_plane_config =
17501                         i9xx_get_initial_plane_config;
17502                 dev_priv->display.crtc_compute_clock =
17503                         ilk_crtc_compute_clock;
17504                 dev_priv->display.crtc_enable = ilk_crtc_enable;
17505                 dev_priv->display.crtc_disable = ilk_crtc_disable;
17506         } else if (IS_CHERRYVIEW(dev_priv)) {
17507                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17508                 dev_priv->display.get_initial_plane_config =
17509                         i9xx_get_initial_plane_config;
17510                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
17511                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
17512                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17513         } else if (IS_VALLEYVIEW(dev_priv)) {
17514                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17515                 dev_priv->display.get_initial_plane_config =
17516                         i9xx_get_initial_plane_config;
17517                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
17518                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
17519                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17520         } else if (IS_G4X(dev_priv)) {
17521                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17522                 dev_priv->display.get_initial_plane_config =
17523                         i9xx_get_initial_plane_config;
17524                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
17525                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17526                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17527         } else if (IS_PINEVIEW(dev_priv)) {
17528                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17529                 dev_priv->display.get_initial_plane_config =
17530                         i9xx_get_initial_plane_config;
17531                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
17532                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17533                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17534         } else if (!IS_GEN(dev_priv, 2)) {
17535                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17536                 dev_priv->display.get_initial_plane_config =
17537                         i9xx_get_initial_plane_config;
17538                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
17539                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17540                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17541         } else {
17542                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17543                 dev_priv->display.get_initial_plane_config =
17544                         i9xx_get_initial_plane_config;
17545                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
17546                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17547                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17548         }
17549
17550         if (IS_GEN(dev_priv, 5)) {
17551                 dev_priv->display.fdi_link_train = ilk_fdi_link_train;
17552         } else if (IS_GEN(dev_priv, 6)) {
17553                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
17554         } else if (IS_IVYBRIDGE(dev_priv)) {
17555                 /* FIXME: detect B0+ stepping and use auto training */
17556                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
17557         }
17558
17559         if (INTEL_GEN(dev_priv) >= 9)
17560                 dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables;
17561         else
17562                 dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables;
17563
17564 }
17565
17566 void intel_modeset_init_hw(struct drm_i915_private *i915)
17567 {
17568         struct intel_cdclk_state *cdclk_state =
17569                 to_intel_cdclk_state(i915->cdclk.obj.state);
17570         struct intel_dbuf_state *dbuf_state =
17571                 to_intel_dbuf_state(i915->dbuf.obj.state);
17572
17573         intel_update_cdclk(i915);
17574         intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
17575         cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;
17576
17577         dbuf_state->enabled_slices = i915->dbuf.enabled_slices;
17578 }
17579
17580 static int sanitize_watermarks_add_affected(struct drm_atomic_state *state)
17581 {
17582         struct drm_plane *plane;
17583         struct intel_crtc *crtc;
17584
17585         for_each_intel_crtc(state->dev, crtc) {
17586                 struct intel_crtc_state *crtc_state;
17587
17588                 crtc_state = intel_atomic_get_crtc_state(state, crtc);
17589                 if (IS_ERR(crtc_state))
17590                         return PTR_ERR(crtc_state);
17591
17592                 if (crtc_state->hw.active) {
17593                         /*
17594                          * Preserve the inherited flag to avoid
17595                          * taking the full modeset path.
17596                          */
17597                         crtc_state->inherited = true;
17598                 }
17599         }
17600
17601         drm_for_each_plane(plane, state->dev) {
17602                 struct drm_plane_state *plane_state;
17603
17604                 plane_state = drm_atomic_get_plane_state(state, plane);
17605                 if (IS_ERR(plane_state))
17606                         return PTR_ERR(plane_state);
17607         }
17608
17609         return 0;
17610 }
17611
17612 /*
17613  * Calculate what we think the watermarks should be for the state we've read
17614  * out of the hardware and then immediately program those watermarks so that
17615  * we ensure the hardware settings match our internal state.
17616  *
17617  * We can calculate what we think WM's should be by creating a duplicate of the
17618  * current state (which was constructed during hardware readout) and running it
17619  * through the atomic check code to calculate new watermark values in the
17620  * state object.
17621  */
17622 static void sanitize_watermarks(struct drm_i915_private *dev_priv)
17623 {
17624         struct drm_atomic_state *state;
17625         struct intel_atomic_state *intel_state;
17626         struct intel_crtc *crtc;
17627         struct intel_crtc_state *crtc_state;
17628         struct drm_modeset_acquire_ctx ctx;
17629         int ret;
17630         int i;
17631
17632         /* Only supported on platforms that use atomic watermark design */
17633         if (!dev_priv->display.optimize_watermarks)
17634                 return;
17635
17636         state = drm_atomic_state_alloc(&dev_priv->drm);
17637         if (drm_WARN_ON(&dev_priv->drm, !state))
17638                 return;
17639
17640         intel_state = to_intel_atomic_state(state);
17641
17642         drm_modeset_acquire_init(&ctx, 0);
17643
17644 retry:
17645         state->acquire_ctx = &ctx;
17646
17647         /*
17648          * Hardware readout is the only time we don't want to calculate
17649          * intermediate watermarks (since we don't trust the current
17650          * watermarks).
17651          */
17652         if (!HAS_GMCH(dev_priv))
17653                 intel_state->skip_intermediate_wm = true;
17654
17655         ret = sanitize_watermarks_add_affected(state);
17656         if (ret)
17657                 goto fail;
17658
17659         ret = intel_atomic_check(&dev_priv->drm, state);
17660         if (ret)
17661                 goto fail;
17662
17663         /* Write calculated watermark values back */
17664         for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
17665                 crtc_state->wm.need_postvbl_update = true;
17666                 dev_priv->display.optimize_watermarks(intel_state, crtc);
17667
17668                 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
17669         }
17670
17671 fail:
17672         if (ret == -EDEADLK) {
17673                 drm_atomic_state_clear(state);
17674                 drm_modeset_backoff(&ctx);
17675                 goto retry;
17676         }
17677
17678         /*
17679          * If we fail here, it means that the hardware appears to be
17680          * programmed in a way that shouldn't be possible, given our
17681          * understanding of watermark requirements.  This might mean a
17682          * mistake in the hardware readout code or a mistake in the
17683          * watermark calculations for a given platform.  Raise a WARN
17684          * so that this is noticeable.
17685          *
17686          * If this actually happens, we'll have to just leave the
17687          * BIOS-programmed watermarks untouched and hope for the best.
17688          */
17689         drm_WARN(&dev_priv->drm, ret,
17690                  "Could not determine valid watermarks for inherited state\n");
17691
17692         drm_atomic_state_put(state);
17693
17694         drm_modeset_drop_locks(&ctx);
17695         drm_modeset_acquire_fini(&ctx);
17696 }
17697
17698 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
17699 {
17700         if (IS_GEN(dev_priv, 5)) {
17701                 u32 fdi_pll_clk =
17702                         intel_de_read(dev_priv, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
17703
17704                 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
17705         } else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) {
17706                 dev_priv->fdi_pll_freq = 270000;
17707         } else {
17708                 return;
17709         }
17710
17711         drm_dbg(&dev_priv->drm, "FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
17712 }
17713
17714 static int intel_initial_commit(struct drm_device *dev)
17715 {
17716         struct drm_atomic_state *state = NULL;
17717         struct drm_modeset_acquire_ctx ctx;
17718         struct intel_crtc *crtc;
17719         int ret = 0;
17720
17721         state = drm_atomic_state_alloc(dev);
17722         if (!state)
17723                 return -ENOMEM;
17724
17725         drm_modeset_acquire_init(&ctx, 0);
17726
17727 retry:
17728         state->acquire_ctx = &ctx;
17729
17730         for_each_intel_crtc(dev, crtc) {
17731                 struct intel_crtc_state *crtc_state =
17732                         intel_atomic_get_crtc_state(state, crtc);
17733
17734                 if (IS_ERR(crtc_state)) {
17735                         ret = PTR_ERR(crtc_state);
17736                         goto out;
17737                 }
17738
17739                 if (crtc_state->hw.active) {
17740                         /*
17741                          * We've not yet detected sink capabilities
17742                          * (audio,infoframes,etc.) and thus we don't want to
17743                          * force a full state recomputation yet. We want that to
17744                          * happen only for the first real commit from userspace.
17745                          * So preserve the inherited flag for the time being.
17746                          */
17747                         crtc_state->inherited = true;
17748
17749                         ret = drm_atomic_add_affected_planes(state, &crtc->base);
17750                         if (ret)
17751                                 goto out;
17752
17753                         /*
17754                          * FIXME hack to force a LUT update to avoid the
17755                          * plane update forcing the pipe gamma on without
17756                          * having a proper LUT loaded. Remove once we
17757                          * have readout for pipe gamma enable.
17758                          */
17759                         crtc_state->uapi.color_mgmt_changed = true;
17760
17761                         /*
17762                          * FIXME hack to force full modeset when DSC is being
17763                          * used.
17764                          *
17765                          * As long as we do not have full state readout and
17766                          * config comparison of crtc_state->dsc, we have no way
17767                          * to ensure reliable fastset. Remove once we have
17768                          * readout for DSC.
17769                          */
17770                         if (crtc_state->dsc.compression_enable) {
17771                                 ret = drm_atomic_add_affected_connectors(state,
17772                                                                          &crtc->base);
17773                                 if (ret)
17774                                         goto out;
17775                                 crtc_state->uapi.mode_changed = true;
17776                                 drm_dbg_kms(dev, "Force full modeset for DSC\n");
17777                         }
17778                 }
17779         }
17780
17781         ret = drm_atomic_commit(state);
17782
17783 out:
17784         if (ret == -EDEADLK) {
17785                 drm_atomic_state_clear(state);
17786                 drm_modeset_backoff(&ctx);
17787                 goto retry;
17788         }
17789
17790         drm_atomic_state_put(state);
17791
17792         drm_modeset_drop_locks(&ctx);
17793         drm_modeset_acquire_fini(&ctx);
17794
17795         return ret;
17796 }
17797
17798 static void intel_mode_config_init(struct drm_i915_private *i915)
17799 {
17800         struct drm_mode_config *mode_config = &i915->drm.mode_config;
17801
17802         drm_mode_config_init(&i915->drm);
17803         INIT_LIST_HEAD(&i915->global_obj_list);
17804
17805         mode_config->min_width = 0;
17806         mode_config->min_height = 0;
17807
17808         mode_config->preferred_depth = 24;
17809         mode_config->prefer_shadow = 1;
17810
17811         mode_config->allow_fb_modifiers = true;
17812
17813         mode_config->funcs = &intel_mode_funcs;
17814
17815         /*
17816          * Maximum framebuffer dimensions, chosen to match
17817          * the maximum render engine surface size on gen4+.
17818          */
17819         if (INTEL_GEN(i915) >= 7) {
17820                 mode_config->max_width = 16384;
17821                 mode_config->max_height = 16384;
17822         } else if (INTEL_GEN(i915) >= 4) {
17823                 mode_config->max_width = 8192;
17824                 mode_config->max_height = 8192;
17825         } else if (IS_GEN(i915, 3)) {
17826                 mode_config->max_width = 4096;
17827                 mode_config->max_height = 4096;
17828         } else {
17829                 mode_config->max_width = 2048;
17830                 mode_config->max_height = 2048;
17831         }
17832
17833         if (IS_I845G(i915) || IS_I865G(i915)) {
17834                 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512;
17835                 mode_config->cursor_height = 1023;
17836         } else if (IS_I830(i915) || IS_I85X(i915) ||
17837                    IS_I915G(i915) || IS_I915GM(i915)) {
17838                 mode_config->cursor_width = 64;
17839                 mode_config->cursor_height = 64;
17840         } else {
17841                 mode_config->cursor_width = 256;
17842                 mode_config->cursor_height = 256;
17843         }
17844 }
17845
17846 static void intel_mode_config_cleanup(struct drm_i915_private *i915)
17847 {
17848         intel_atomic_global_obj_cleanup(i915);
17849         drm_mode_config_cleanup(&i915->drm);
17850 }
17851
17852 static void plane_config_fini(struct intel_initial_plane_config *plane_config)
17853 {
17854         if (plane_config->fb) {
17855                 struct drm_framebuffer *fb = &plane_config->fb->base;
17856
17857                 /* We may only have the stub and not a full framebuffer */
17858                 if (drm_framebuffer_read_refcount(fb))
17859                         drm_framebuffer_put(fb);
17860                 else
17861                         kfree(fb);
17862         }
17863
17864         if (plane_config->vma)
17865                 i915_vma_put(plane_config->vma);
17866 }
17867
17868 /* part #1: call before irq install */
17869 int intel_modeset_init_noirq(struct drm_i915_private *i915)
17870 {
17871         int ret;
17872
17873         if (i915_inject_probe_failure(i915))
17874                 return -ENODEV;
17875
17876         if (HAS_DISPLAY(i915)) {
17877                 ret = drm_vblank_init(&i915->drm,
17878                                       INTEL_NUM_PIPES(i915));
17879                 if (ret)
17880                         return ret;
17881         }
17882
17883         intel_bios_init(i915);
17884
17885         ret = intel_vga_register(i915);
17886         if (ret)
17887                 goto cleanup_bios;
17888
17889         /* FIXME: completely on the wrong abstraction layer */
17890         intel_power_domains_init_hw(i915, false);
17891
17892         intel_csr_ucode_init(i915);
17893
17894         i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
17895         i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
17896                                         WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
17897
17898         intel_mode_config_init(i915);
17899
17900         ret = intel_cdclk_init(i915);
17901         if (ret)
17902                 goto cleanup_vga_client_pw_domain_csr;
17903
17904         ret = intel_dbuf_init(i915);
17905         if (ret)
17906                 goto cleanup_vga_client_pw_domain_csr;
17907
17908         ret = intel_bw_init(i915);
17909         if (ret)
17910                 goto cleanup_vga_client_pw_domain_csr;
17911
17912         init_llist_head(&i915->atomic_helper.free_list);
17913         INIT_WORK(&i915->atomic_helper.free_work,
17914                   intel_atomic_helper_free_state_worker);
17915
17916         intel_init_quirks(i915);
17917
17918         intel_fbc_init(i915);
17919
17920         return 0;
17921
17922 cleanup_vga_client_pw_domain_csr:
17923         intel_csr_ucode_fini(i915);
17924         intel_power_domains_driver_remove(i915);
17925         intel_vga_unregister(i915);
17926 cleanup_bios:
17927         intel_bios_driver_remove(i915);
17928
17929         return ret;
17930 }
17931
17932 /* part #2: call after irq install, but before gem init */
17933 int intel_modeset_init_nogem(struct drm_i915_private *i915)
17934 {
17935         struct drm_device *dev = &i915->drm;
17936         enum pipe pipe;
17937         struct intel_crtc *crtc;
17938         int ret;
17939
17940         intel_init_pm(i915);
17941
17942         intel_panel_sanitize_ssc(i915);
17943
17944         intel_gmbus_setup(i915);
17945
17946         drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n",
17947                     INTEL_NUM_PIPES(i915),
17948                     INTEL_NUM_PIPES(i915) > 1 ? "s" : "");
17949
17950         if (HAS_DISPLAY(i915)) {
17951                 for_each_pipe(i915, pipe) {
17952                         ret = intel_crtc_init(i915, pipe);
17953                         if (ret) {
17954                                 intel_mode_config_cleanup(i915);
17955                                 return ret;
17956                         }
17957                 }
17958         }
17959
17960         intel_plane_possible_crtcs_init(i915);
17961         intel_shared_dpll_init(dev);
17962         intel_update_fdi_pll_freq(i915);
17963
17964         intel_update_czclk(i915);
17965         intel_modeset_init_hw(i915);
17966
17967         intel_hdcp_component_init(i915);
17968
17969         if (i915->max_cdclk_freq == 0)
17970                 intel_update_max_cdclk(i915);
17971
17972         /*
17973          * If the platform has HTI, we need to find out whether it has reserved
17974          * any display resources before we create our display outputs.
17975          */
17976         if (INTEL_INFO(i915)->display.has_hti)
17977                 i915->hti_state = intel_de_read(i915, HDPORT_STATE);
17978
17979         /* Just disable it once at startup */
17980         intel_vga_disable(i915);
17981         intel_setup_outputs(i915);
17982
17983         drm_modeset_lock_all(dev);
17984         intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
17985         drm_modeset_unlock_all(dev);
17986
17987         for_each_intel_crtc(dev, crtc) {
17988                 struct intel_initial_plane_config plane_config = {};
17989
17990                 if (!crtc->active)
17991                         continue;
17992
17993                 /*
17994                  * Note that reserving the BIOS fb up front prevents us
17995                  * from stuffing other stolen allocations like the ring
17996                  * on top.  This prevents some ugliness at boot time, and
17997                  * can even allow for smooth boot transitions if the BIOS
17998                  * fb is large enough for the active pipe configuration.
17999                  */
18000                 i915->display.get_initial_plane_config(crtc, &plane_config);
18001
18002                 /*
18003                  * If the fb is shared between multiple heads, we'll
18004                  * just get the first one.
18005                  */
18006                 intel_find_initial_plane_obj(crtc, &plane_config);
18007
18008                 plane_config_fini(&plane_config);
18009         }
18010
18011         /*
18012          * Make sure hardware watermarks really match the state we read out.
18013          * Note that we need to do this after reconstructing the BIOS fb's
18014          * since the watermark calculation done here will use pstate->fb.
18015          */
18016         if (!HAS_GMCH(i915))
18017                 sanitize_watermarks(i915);
18018
18019         /*
18020          * Force all active planes to recompute their states. So that on
18021          * mode_setcrtc after probe, all the intel_plane_state variables
18022          * are already calculated and there is no assert_plane warnings
18023          * during bootup.
18024          */
18025         ret = intel_initial_commit(dev);
18026         if (ret)
18027                 drm_dbg_kms(&i915->drm, "Initial commit in probe failed.\n");
18028
18029         return 0;
18030 }
18031
18032 /* part #3: call after gem init */
18033 int intel_modeset_init(struct drm_i915_private *i915)
18034 {
18035         int ret;
18036
18037         intel_overlay_setup(i915);
18038
18039         if (!HAS_DISPLAY(i915))
18040                 return 0;
18041
18042         ret = intel_fbdev_init(&i915->drm);
18043         if (ret)
18044                 return ret;
18045
18046         /* Only enable hotplug handling once the fbdev is fully set up. */
18047         intel_hpd_init(i915);
18048
18049         intel_init_ipc(i915);
18050
18051         intel_psr_set_force_mode_changed(i915->psr.dp);
18052
18053         return 0;
18054 }
18055
18056 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
18057 {
18058         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18059         /* 640x480@60Hz, ~25175 kHz */
18060         struct dpll clock = {
18061                 .m1 = 18,
18062                 .m2 = 7,
18063                 .p1 = 13,
18064                 .p2 = 4,
18065                 .n = 2,
18066         };
18067         u32 dpll, fp;
18068         int i;
18069
18070         drm_WARN_ON(&dev_priv->drm,
18071                     i9xx_calc_dpll_params(48000, &clock) != 25154);
18072
18073         drm_dbg_kms(&dev_priv->drm,
18074                     "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
18075                     pipe_name(pipe), clock.vco, clock.dot);
18076
18077         fp = i9xx_dpll_compute_fp(&clock);
18078         dpll = DPLL_DVO_2X_MODE |
18079                 DPLL_VGA_MODE_DIS |
18080                 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
18081                 PLL_P2_DIVIDE_BY_4 |
18082                 PLL_REF_INPUT_DREFCLK |
18083                 DPLL_VCO_ENABLE;
18084
18085         intel_de_write(dev_priv, FP0(pipe), fp);
18086         intel_de_write(dev_priv, FP1(pipe), fp);
18087
18088         intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
18089         intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
18090         intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
18091         intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
18092         intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
18093         intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
18094         intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
18095
18096         /*
18097          * Apparently we need to have VGA mode enabled prior to changing
18098          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
18099          * dividers, even though the register value does change.
18100          */
18101         intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
18102         intel_de_write(dev_priv, DPLL(pipe), dpll);
18103
18104         /* Wait for the clocks to stabilize. */
18105         intel_de_posting_read(dev_priv, DPLL(pipe));
18106         udelay(150);
18107
18108         /* The pixel multiplier can only be updated once the
18109          * DPLL is enabled and the clocks are stable.
18110          *
18111          * So write it again.
18112          */
18113         intel_de_write(dev_priv, DPLL(pipe), dpll);
18114
18115         /* We do this three times for luck */
18116         for (i = 0; i < 3 ; i++) {
18117                 intel_de_write(dev_priv, DPLL(pipe), dpll);
18118                 intel_de_posting_read(dev_priv, DPLL(pipe));
18119                 udelay(150); /* wait for warmup */
18120         }
18121
18122         intel_de_write(dev_priv, PIPECONF(pipe),
18123                        PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
18124         intel_de_posting_read(dev_priv, PIPECONF(pipe));
18125
18126         intel_wait_for_pipe_scanline_moving(crtc);
18127 }
18128
18129 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
18130 {
18131         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18132
18133         drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",
18134                     pipe_name(pipe));
18135
18136         drm_WARN_ON(&dev_priv->drm,
18137                     intel_de_read(dev_priv, DSPCNTR(PLANE_A)) &
18138                     DISPLAY_PLANE_ENABLE);
18139         drm_WARN_ON(&dev_priv->drm,
18140                     intel_de_read(dev_priv, DSPCNTR(PLANE_B)) &
18141                     DISPLAY_PLANE_ENABLE);
18142         drm_WARN_ON(&dev_priv->drm,
18143                     intel_de_read(dev_priv, DSPCNTR(PLANE_C)) &
18144                     DISPLAY_PLANE_ENABLE);
18145         drm_WARN_ON(&dev_priv->drm,
18146                     intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE);
18147         drm_WARN_ON(&dev_priv->drm,
18148                     intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE);
18149
18150         intel_de_write(dev_priv, PIPECONF(pipe), 0);
18151         intel_de_posting_read(dev_priv, PIPECONF(pipe));
18152
18153         intel_wait_for_pipe_scanline_stopped(crtc);
18154
18155         intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
18156         intel_de_posting_read(dev_priv, DPLL(pipe));
18157 }
18158
18159 static void
18160 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
18161 {
18162         struct intel_crtc *crtc;
18163
18164         if (INTEL_GEN(dev_priv) >= 4)
18165                 return;
18166
18167         for_each_intel_crtc(&dev_priv->drm, crtc) {
18168                 struct intel_plane *plane =
18169                         to_intel_plane(crtc->base.primary);
18170                 struct intel_crtc *plane_crtc;
18171                 enum pipe pipe;
18172
18173                 if (!plane->get_hw_state(plane, &pipe))
18174                         continue;
18175
18176                 if (pipe == crtc->pipe)
18177                         continue;
18178
18179                 drm_dbg_kms(&dev_priv->drm,
18180                             "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
18181                             plane->base.base.id, plane->base.name);
18182
18183                 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18184                 intel_plane_disable_noatomic(plane_crtc, plane);
18185         }
18186 }
18187
18188 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
18189 {
18190         struct drm_device *dev = crtc->base.dev;
18191         struct intel_encoder *encoder;
18192
18193         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
18194                 return true;
18195
18196         return false;
18197 }
18198
18199 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
18200 {
18201         struct drm_device *dev = encoder->base.dev;
18202         struct intel_connector *connector;
18203
18204         for_each_connector_on_encoder(dev, &encoder->base, connector)
18205                 return connector;
18206
18207         return NULL;
18208 }
18209
18210 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
18211                               enum pipe pch_transcoder)
18212 {
18213         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
18214                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
18215 }
18216
18217 static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc_state)
18218 {
18219         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
18220         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
18221         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
18222
18223         if (INTEL_GEN(dev_priv) >= 9 ||
18224             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
18225                 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
18226                 u32 val;
18227
18228                 if (transcoder_is_dsi(cpu_transcoder))
18229                         return;
18230
18231                 val = intel_de_read(dev_priv, reg);
18232                 val &= ~HSW_FRAME_START_DELAY_MASK;
18233                 val |= HSW_FRAME_START_DELAY(0);
18234                 intel_de_write(dev_priv, reg, val);
18235         } else {
18236                 i915_reg_t reg = PIPECONF(cpu_transcoder);
18237                 u32 val;
18238
18239                 val = intel_de_read(dev_priv, reg);
18240                 val &= ~PIPECONF_FRAME_START_DELAY_MASK;
18241                 val |= PIPECONF_FRAME_START_DELAY(0);
18242                 intel_de_write(dev_priv, reg, val);
18243         }
18244
18245         if (!crtc_state->has_pch_encoder)
18246                 return;
18247
18248         if (HAS_PCH_IBX(dev_priv)) {
18249                 i915_reg_t reg = PCH_TRANSCONF(crtc->pipe);
18250                 u32 val;
18251
18252                 val = intel_de_read(dev_priv, reg);
18253                 val &= ~TRANS_FRAME_START_DELAY_MASK;
18254                 val |= TRANS_FRAME_START_DELAY(0);
18255                 intel_de_write(dev_priv, reg, val);
18256         } else {
18257                 enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc);
18258                 i915_reg_t reg = TRANS_CHICKEN2(pch_transcoder);
18259                 u32 val;
18260
18261                 val = intel_de_read(dev_priv, reg);
18262                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
18263                 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
18264                 intel_de_write(dev_priv, reg, val);
18265         }
18266 }
18267
18268 static void intel_sanitize_crtc(struct intel_crtc *crtc,
18269                                 struct drm_modeset_acquire_ctx *ctx)
18270 {
18271         struct drm_device *dev = crtc->base.dev;
18272         struct drm_i915_private *dev_priv = to_i915(dev);
18273         struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
18274
18275         if (crtc_state->hw.active) {
18276                 struct intel_plane *plane;
18277
18278                 /* Clear any frame start delays used for debugging left by the BIOS */
18279                 intel_sanitize_frame_start_delay(crtc_state);
18280
18281                 /* Disable everything but the primary plane */
18282                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
18283                         const struct intel_plane_state *plane_state =
18284                                 to_intel_plane_state(plane->base.state);
18285
18286                         if (plane_state->uapi.visible &&
18287                             plane->base.type != DRM_PLANE_TYPE_PRIMARY)
18288                                 intel_plane_disable_noatomic(crtc, plane);
18289                 }
18290
18291                 /*
18292                  * Disable any background color set by the BIOS, but enable the
18293                  * gamma and CSC to match how we program our planes.
18294                  */
18295                 if (INTEL_GEN(dev_priv) >= 9)
18296                         intel_de_write(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe),
18297                                        SKL_BOTTOM_COLOR_GAMMA_ENABLE | SKL_BOTTOM_COLOR_CSC_ENABLE);
18298         }
18299
18300         /* Adjust the state of the output pipe according to whether we
18301          * have active connectors/encoders. */
18302         if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc))
18303                 intel_crtc_disable_noatomic(crtc, ctx);
18304
18305         if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
18306                 /*
18307                  * We start out with underrun reporting disabled to avoid races.
18308                  * For correct bookkeeping mark this on active crtcs.
18309                  *
18310                  * Also on gmch platforms we dont have any hardware bits to
18311                  * disable the underrun reporting. Which means we need to start
18312                  * out with underrun reporting disabled also on inactive pipes,
18313                  * since otherwise we'll complain about the garbage we read when
18314                  * e.g. coming up after runtime pm.
18315                  *
18316                  * No protection against concurrent access is required - at
18317                  * worst a fifo underrun happens which also sets this to false.
18318                  */
18319                 crtc->cpu_fifo_underrun_disabled = true;
18320                 /*
18321                  * We track the PCH trancoder underrun reporting state
18322                  * within the crtc. With crtc for pipe A housing the underrun
18323                  * reporting state for PCH transcoder A, crtc for pipe B housing
18324                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
18325                  * and marking underrun reporting as disabled for the non-existing
18326                  * PCH transcoders B and C would prevent enabling the south
18327                  * error interrupt (see cpt_can_enable_serr_int()).
18328                  */
18329                 if (has_pch_trancoder(dev_priv, crtc->pipe))
18330                         crtc->pch_fifo_underrun_disabled = true;
18331         }
18332 }
18333
18334 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
18335 {
18336         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
18337
18338         /*
18339          * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
18340          * the hardware when a high res displays plugged in. DPLL P
18341          * divider is zero, and the pipe timings are bonkers. We'll
18342          * try to disable everything in that case.
18343          *
18344          * FIXME would be nice to be able to sanitize this state
18345          * without several WARNs, but for now let's take the easy
18346          * road.
18347          */
18348         return IS_GEN(dev_priv, 6) &&
18349                 crtc_state->hw.active &&
18350                 crtc_state->shared_dpll &&
18351                 crtc_state->port_clock == 0;
18352 }
18353
18354 static void intel_sanitize_encoder(struct intel_encoder *encoder)
18355 {
18356         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
18357         struct intel_connector *connector;
18358         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18359         struct intel_crtc_state *crtc_state = crtc ?
18360                 to_intel_crtc_state(crtc->base.state) : NULL;
18361
18362         /* We need to check both for a crtc link (meaning that the
18363          * encoder is active and trying to read from a pipe) and the
18364          * pipe itself being active. */
18365         bool has_active_crtc = crtc_state &&
18366                 crtc_state->hw.active;
18367
18368         if (crtc_state && has_bogus_dpll_config(crtc_state)) {
18369                 drm_dbg_kms(&dev_priv->drm,
18370                             "BIOS has misprogrammed the hardware. Disabling pipe %c\n",
18371                             pipe_name(crtc->pipe));
18372                 has_active_crtc = false;
18373         }
18374
18375         connector = intel_encoder_find_connector(encoder);
18376         if (connector && !has_active_crtc) {
18377                 drm_dbg_kms(&dev_priv->drm,
18378                             "[ENCODER:%d:%s] has active connectors but no active pipe!\n",
18379                             encoder->base.base.id,
18380                             encoder->base.name);
18381
18382                 /* Connector is active, but has no active pipe. This is
18383                  * fallout from our resume register restoring. Disable
18384                  * the encoder manually again. */
18385                 if (crtc_state) {
18386                         struct drm_encoder *best_encoder;
18387
18388                         drm_dbg_kms(&dev_priv->drm,
18389                                     "[ENCODER:%d:%s] manually disabled\n",
18390                                     encoder->base.base.id,
18391                                     encoder->base.name);
18392
18393                         /* avoid oopsing in case the hooks consult best_encoder */
18394                         best_encoder = connector->base.state->best_encoder;
18395                         connector->base.state->best_encoder = &encoder->base;
18396
18397                         /* FIXME NULL atomic state passed! */
18398                         if (encoder->disable)
18399                                 encoder->disable(NULL, encoder, crtc_state,
18400                                                  connector->base.state);
18401                         if (encoder->post_disable)
18402                                 encoder->post_disable(NULL, encoder, crtc_state,
18403                                                       connector->base.state);
18404
18405                         connector->base.state->best_encoder = best_encoder;
18406                 }
18407                 encoder->base.crtc = NULL;
18408
18409                 /* Inconsistent output/port/pipe state happens presumably due to
18410                  * a bug in one of the get_hw_state functions. Or someplace else
18411                  * in our code, like the register restore mess on resume. Clamp
18412                  * things to off as a safer default. */
18413
18414                 connector->base.dpms = DRM_MODE_DPMS_OFF;
18415                 connector->base.encoder = NULL;
18416         }
18417
18418         /* notify opregion of the sanitized encoder state */
18419         intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
18420
18421         if (INTEL_GEN(dev_priv) >= 11)
18422                 icl_sanitize_encoder_pll_mapping(encoder);
18423 }
18424
18425 /* FIXME read out full plane state for all planes */
18426 static void readout_plane_state(struct drm_i915_private *dev_priv)
18427 {
18428         struct intel_plane *plane;
18429         struct intel_crtc *crtc;
18430
18431         for_each_intel_plane(&dev_priv->drm, plane) {
18432                 struct intel_plane_state *plane_state =
18433                         to_intel_plane_state(plane->base.state);
18434                 struct intel_crtc_state *crtc_state;
18435                 enum pipe pipe = PIPE_A;
18436                 bool visible;
18437
18438                 visible = plane->get_hw_state(plane, &pipe);
18439
18440                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18441                 crtc_state = to_intel_crtc_state(crtc->base.state);
18442
18443                 intel_set_plane_visible(crtc_state, plane_state, visible);
18444
18445                 drm_dbg_kms(&dev_priv->drm,
18446                             "[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
18447                             plane->base.base.id, plane->base.name,
18448                             enableddisabled(visible), pipe_name(pipe));
18449         }
18450
18451         for_each_intel_crtc(&dev_priv->drm, crtc) {
18452                 struct intel_crtc_state *crtc_state =
18453                         to_intel_crtc_state(crtc->base.state);
18454
18455                 fixup_active_planes(crtc_state);
18456         }
18457 }
18458
18459 static void intel_modeset_readout_hw_state(struct drm_device *dev)
18460 {
18461         struct drm_i915_private *dev_priv = to_i915(dev);
18462         struct intel_cdclk_state *cdclk_state =
18463                 to_intel_cdclk_state(dev_priv->cdclk.obj.state);
18464         struct intel_dbuf_state *dbuf_state =
18465                 to_intel_dbuf_state(dev_priv->dbuf.obj.state);
18466         enum pipe pipe;
18467         struct intel_crtc *crtc;
18468         struct intel_encoder *encoder;
18469         struct intel_connector *connector;
18470         struct drm_connector_list_iter conn_iter;
18471         u8 active_pipes = 0;
18472
18473         for_each_intel_crtc(dev, crtc) {
18474                 struct intel_crtc_state *crtc_state =
18475                         to_intel_crtc_state(crtc->base.state);
18476
18477                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
18478                 intel_crtc_free_hw_state(crtc_state);
18479                 intel_crtc_state_reset(crtc_state, crtc);
18480
18481                 crtc_state->hw.active = crtc_state->hw.enable =
18482                         dev_priv->display.get_pipe_config(crtc, crtc_state);
18483
18484                 crtc->base.enabled = crtc_state->hw.enable;
18485                 crtc->active = crtc_state->hw.active;
18486
18487                 if (crtc_state->hw.active)
18488                         active_pipes |= BIT(crtc->pipe);
18489
18490                 drm_dbg_kms(&dev_priv->drm,
18491                             "[CRTC:%d:%s] hw state readout: %s\n",
18492                             crtc->base.base.id, crtc->base.name,
18493                             enableddisabled(crtc_state->hw.active));
18494         }
18495
18496         dev_priv->active_pipes = cdclk_state->active_pipes =
18497                 dbuf_state->active_pipes = active_pipes;
18498
18499         readout_plane_state(dev_priv);
18500
18501         intel_dpll_readout_hw_state(dev_priv);
18502
18503         for_each_intel_encoder(dev, encoder) {
18504                 pipe = 0;
18505
18506                 if (encoder->get_hw_state(encoder, &pipe)) {
18507                         struct intel_crtc_state *crtc_state;
18508
18509                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18510                         crtc_state = to_intel_crtc_state(crtc->base.state);
18511
18512                         encoder->base.crtc = &crtc->base;
18513                         encoder->get_config(encoder, crtc_state);
18514                 } else {
18515                         encoder->base.crtc = NULL;
18516                 }
18517
18518                 drm_dbg_kms(&dev_priv->drm,
18519                             "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
18520                             encoder->base.base.id, encoder->base.name,
18521                             enableddisabled(encoder->base.crtc),
18522                             pipe_name(pipe));
18523         }
18524
18525         drm_connector_list_iter_begin(dev, &conn_iter);
18526         for_each_intel_connector_iter(connector, &conn_iter) {
18527                 if (connector->get_hw_state(connector)) {
18528                         struct intel_crtc_state *crtc_state;
18529                         struct intel_crtc *crtc;
18530
18531                         connector->base.dpms = DRM_MODE_DPMS_ON;
18532
18533                         encoder = intel_attached_encoder(connector);
18534                         connector->base.encoder = &encoder->base;
18535
18536                         crtc = to_intel_crtc(encoder->base.crtc);
18537                         crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
18538
18539                         if (crtc_state && crtc_state->hw.active) {
18540                                 /*
18541                                  * This has to be done during hardware readout
18542                                  * because anything calling .crtc_disable may
18543                                  * rely on the connector_mask being accurate.
18544                                  */
18545                                 crtc_state->uapi.connector_mask |=
18546                                         drm_connector_mask(&connector->base);
18547                                 crtc_state->uapi.encoder_mask |=
18548                                         drm_encoder_mask(&encoder->base);
18549                         }
18550                 } else {
18551                         connector->base.dpms = DRM_MODE_DPMS_OFF;
18552                         connector->base.encoder = NULL;
18553                 }
18554                 drm_dbg_kms(&dev_priv->drm,
18555                             "[CONNECTOR:%d:%s] hw state readout: %s\n",
18556                             connector->base.base.id, connector->base.name,
18557                             enableddisabled(connector->base.encoder));
18558         }
18559         drm_connector_list_iter_end(&conn_iter);
18560
18561         for_each_intel_crtc(dev, crtc) {
18562                 struct intel_bw_state *bw_state =
18563                         to_intel_bw_state(dev_priv->bw_obj.state);
18564                 struct intel_crtc_state *crtc_state =
18565                         to_intel_crtc_state(crtc->base.state);
18566                 struct intel_plane *plane;
18567                 int min_cdclk = 0;
18568
18569                 if (crtc_state->hw.active) {
18570                         struct drm_display_mode *mode = &crtc_state->hw.mode;
18571
18572                         intel_mode_from_pipe_config(&crtc_state->hw.adjusted_mode,
18573                                                     crtc_state);
18574
18575                         *mode = crtc_state->hw.adjusted_mode;
18576                         mode->hdisplay = crtc_state->pipe_src_w;
18577                         mode->vdisplay = crtc_state->pipe_src_h;
18578
18579                         /*
18580                          * The initial mode needs to be set in order to keep
18581                          * the atomic core happy. It wants a valid mode if the
18582                          * crtc's enabled, so we do the above call.
18583                          *
18584                          * But we don't set all the derived state fully, hence
18585                          * set a flag to indicate that a full recalculation is
18586                          * needed on the next commit.
18587                          */
18588                         crtc_state->inherited = true;
18589
18590                         intel_crtc_compute_pixel_rate(crtc_state);
18591
18592                         intel_crtc_update_active_timings(crtc_state);
18593
18594                         intel_crtc_copy_hw_to_uapi_state(crtc_state);
18595                 }
18596
18597                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
18598                         const struct intel_plane_state *plane_state =
18599                                 to_intel_plane_state(plane->base.state);
18600
18601                         /*
18602                          * FIXME don't have the fb yet, so can't
18603                          * use intel_plane_data_rate() :(
18604                          */
18605                         if (plane_state->uapi.visible)
18606                                 crtc_state->data_rate[plane->id] =
18607                                         4 * crtc_state->pixel_rate;
18608                         /*
18609                          * FIXME don't have the fb yet, so can't
18610                          * use plane->min_cdclk() :(
18611                          */
18612                         if (plane_state->uapi.visible && plane->min_cdclk) {
18613                                 if (crtc_state->double_wide ||
18614                                     INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
18615                                         crtc_state->min_cdclk[plane->id] =
18616                                                 DIV_ROUND_UP(crtc_state->pixel_rate, 2);
18617                                 else
18618                                         crtc_state->min_cdclk[plane->id] =
18619                                                 crtc_state->pixel_rate;
18620                         }
18621                         drm_dbg_kms(&dev_priv->drm,
18622                                     "[PLANE:%d:%s] min_cdclk %d kHz\n",
18623                                     plane->base.base.id, plane->base.name,
18624                                     crtc_state->min_cdclk[plane->id]);
18625                 }
18626
18627                 if (crtc_state->hw.active) {
18628                         min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
18629                         if (drm_WARN_ON(dev, min_cdclk < 0))
18630                                 min_cdclk = 0;
18631                 }
18632
18633                 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
18634                 cdclk_state->min_voltage_level[crtc->pipe] =
18635                         crtc_state->min_voltage_level;
18636
18637                 intel_bw_crtc_update(bw_state, crtc_state);
18638
18639                 intel_pipe_config_sanity_check(dev_priv, crtc_state);
18640         }
18641 }
18642
18643 static void
18644 get_encoder_power_domains(struct drm_i915_private *dev_priv)
18645 {
18646         struct intel_encoder *encoder;
18647
18648         for_each_intel_encoder(&dev_priv->drm, encoder) {
18649                 struct intel_crtc_state *crtc_state;
18650
18651                 if (!encoder->get_power_domains)
18652                         continue;
18653
18654                 /*
18655                  * MST-primary and inactive encoders don't have a crtc state
18656                  * and neither of these require any power domain references.
18657                  */
18658                 if (!encoder->base.crtc)
18659                         continue;
18660
18661                 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
18662                 encoder->get_power_domains(encoder, crtc_state);
18663         }
18664 }
18665
18666 static void intel_early_display_was(struct drm_i915_private *dev_priv)
18667 {
18668         /*
18669          * Display WA #1185 WaDisableDARBFClkGating:cnl,glk,icl,ehl,tgl
18670          * Also known as Wa_14010480278.
18671          */
18672         if (IS_GEN_RANGE(dev_priv, 10, 12) || IS_GEMINILAKE(dev_priv))
18673                 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0,
18674                                intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS);
18675
18676         if (IS_HASWELL(dev_priv)) {
18677                 /*
18678                  * WaRsPkgCStateDisplayPMReq:hsw
18679                  * System hang if this isn't done before disabling all planes!
18680                  */
18681                 intel_de_write(dev_priv, CHICKEN_PAR1_1,
18682                                intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
18683         }
18684 }
18685
18686 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
18687                                        enum port port, i915_reg_t hdmi_reg)
18688 {
18689         u32 val = intel_de_read(dev_priv, hdmi_reg);
18690
18691         if (val & SDVO_ENABLE ||
18692             (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
18693                 return;
18694
18695         drm_dbg_kms(&dev_priv->drm,
18696                     "Sanitizing transcoder select for HDMI %c\n",
18697                     port_name(port));
18698
18699         val &= ~SDVO_PIPE_SEL_MASK;
18700         val |= SDVO_PIPE_SEL(PIPE_A);
18701
18702         intel_de_write(dev_priv, hdmi_reg, val);
18703 }
18704
18705 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
18706                                      enum port port, i915_reg_t dp_reg)
18707 {
18708         u32 val = intel_de_read(dev_priv, dp_reg);
18709
18710         if (val & DP_PORT_EN ||
18711             (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
18712                 return;
18713
18714         drm_dbg_kms(&dev_priv->drm,
18715                     "Sanitizing transcoder select for DP %c\n",
18716                     port_name(port));
18717
18718         val &= ~DP_PIPE_SEL_MASK;
18719         val |= DP_PIPE_SEL(PIPE_A);
18720
18721         intel_de_write(dev_priv, dp_reg, val);
18722 }
18723
18724 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
18725 {
18726         /*
18727          * The BIOS may select transcoder B on some of the PCH
18728          * ports even it doesn't enable the port. This would trip
18729          * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
18730          * Sanitize the transcoder select bits to prevent that. We
18731          * assume that the BIOS never actually enabled the port,
18732          * because if it did we'd actually have to toggle the port
18733          * on and back off to make the transcoder A select stick
18734          * (see. intel_dp_link_down(), intel_disable_hdmi(),
18735          * intel_disable_sdvo()).
18736          */
18737         ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
18738         ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
18739         ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
18740
18741         /* PCH SDVOB multiplex with HDMIB */
18742         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
18743         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
18744         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
18745 }
18746
18747 /* Scan out the current hw modeset state,
18748  * and sanitizes it to the current state
18749  */
18750 static void
18751 intel_modeset_setup_hw_state(struct drm_device *dev,
18752                              struct drm_modeset_acquire_ctx *ctx)
18753 {
18754         struct drm_i915_private *dev_priv = to_i915(dev);
18755         struct intel_encoder *encoder;
18756         struct intel_crtc *crtc;
18757         intel_wakeref_t wakeref;
18758
18759         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
18760
18761         intel_early_display_was(dev_priv);
18762         intel_modeset_readout_hw_state(dev);
18763
18764         /* HW state is read out, now we need to sanitize this mess. */
18765
18766         /* Sanitize the TypeC port mode upfront, encoders depend on this */
18767         for_each_intel_encoder(dev, encoder) {
18768                 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
18769
18770                 /* We need to sanitize only the MST primary port. */
18771                 if (encoder->type != INTEL_OUTPUT_DP_MST &&
18772                     intel_phy_is_tc(dev_priv, phy))
18773                         intel_tc_port_sanitize(enc_to_dig_port(encoder));
18774         }
18775
18776         get_encoder_power_domains(dev_priv);
18777
18778         if (HAS_PCH_IBX(dev_priv))
18779                 ibx_sanitize_pch_ports(dev_priv);
18780
18781         /*
18782          * intel_sanitize_plane_mapping() may need to do vblank
18783          * waits, so we need vblank interrupts restored beforehand.
18784          */
18785         for_each_intel_crtc(&dev_priv->drm, crtc) {
18786                 struct intel_crtc_state *crtc_state =
18787                         to_intel_crtc_state(crtc->base.state);
18788
18789                 drm_crtc_vblank_reset(&crtc->base);
18790
18791                 if (crtc_state->hw.active)
18792                         intel_crtc_vblank_on(crtc_state);
18793         }
18794
18795         intel_sanitize_plane_mapping(dev_priv);
18796
18797         for_each_intel_encoder(dev, encoder)
18798                 intel_sanitize_encoder(encoder);
18799
18800         for_each_intel_crtc(&dev_priv->drm, crtc) {
18801                 struct intel_crtc_state *crtc_state =
18802                         to_intel_crtc_state(crtc->base.state);
18803
18804                 intel_sanitize_crtc(crtc, ctx);
18805                 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
18806         }
18807
18808         intel_modeset_update_connector_atomic_state(dev);
18809
18810         intel_dpll_sanitize_state(dev_priv);
18811
18812         if (IS_G4X(dev_priv)) {
18813                 g4x_wm_get_hw_state(dev_priv);
18814                 g4x_wm_sanitize(dev_priv);
18815         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
18816                 vlv_wm_get_hw_state(dev_priv);
18817                 vlv_wm_sanitize(dev_priv);
18818         } else if (INTEL_GEN(dev_priv) >= 9) {
18819                 skl_wm_get_hw_state(dev_priv);
18820         } else if (HAS_PCH_SPLIT(dev_priv)) {
18821                 ilk_wm_get_hw_state(dev_priv);
18822         }
18823
18824         for_each_intel_crtc(dev, crtc) {
18825                 struct intel_crtc_state *crtc_state =
18826                         to_intel_crtc_state(crtc->base.state);
18827                 u64 put_domains;
18828
18829                 put_domains = modeset_get_crtc_power_domains(crtc_state);
18830                 if (drm_WARN_ON(dev, put_domains))
18831                         modeset_put_power_domains(dev_priv, put_domains);
18832         }
18833
18834         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
18835 }
18836
18837 void intel_display_resume(struct drm_device *dev)
18838 {
18839         struct drm_i915_private *dev_priv = to_i915(dev);
18840         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
18841         struct drm_modeset_acquire_ctx ctx;
18842         int ret;
18843
18844         dev_priv->modeset_restore_state = NULL;
18845         if (state)
18846                 state->acquire_ctx = &ctx;
18847
18848         drm_modeset_acquire_init(&ctx, 0);
18849
18850         while (1) {
18851                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
18852                 if (ret != -EDEADLK)
18853                         break;
18854
18855                 drm_modeset_backoff(&ctx);
18856         }
18857
18858         if (!ret)
18859                 ret = __intel_display_resume(dev, state, &ctx);
18860
18861         intel_enable_ipc(dev_priv);
18862         drm_modeset_drop_locks(&ctx);
18863         drm_modeset_acquire_fini(&ctx);
18864
18865         if (ret)
18866                 drm_err(&dev_priv->drm,
18867                         "Restoring old state failed with %i\n", ret);
18868         if (state)
18869                 drm_atomic_state_put(state);
18870 }
18871
18872 static void intel_hpd_poll_fini(struct drm_i915_private *i915)
18873 {
18874         struct intel_connector *connector;
18875         struct drm_connector_list_iter conn_iter;
18876
18877         /* Kill all the work that may have been queued by hpd. */
18878         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
18879         for_each_intel_connector_iter(connector, &conn_iter) {
18880                 if (connector->modeset_retry_work.func)
18881                         cancel_work_sync(&connector->modeset_retry_work);
18882                 if (connector->hdcp.shim) {
18883                         cancel_delayed_work_sync(&connector->hdcp.check_work);
18884                         cancel_work_sync(&connector->hdcp.prop_work);
18885                 }
18886         }
18887         drm_connector_list_iter_end(&conn_iter);
18888 }
18889
18890 /* part #1: call before irq uninstall */
18891 void intel_modeset_driver_remove(struct drm_i915_private *i915)
18892 {
18893         flush_workqueue(i915->flip_wq);
18894         flush_workqueue(i915->modeset_wq);
18895
18896         flush_work(&i915->atomic_helper.free_work);
18897         drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list));
18898 }
18899
18900 /* part #2: call after irq uninstall */
18901 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915)
18902 {
18903         /*
18904          * Due to the hpd irq storm handling the hotplug work can re-arm the
18905          * poll handlers. Hence disable polling after hpd handling is shut down.
18906          */
18907         intel_hpd_poll_fini(i915);
18908
18909         /*
18910          * MST topology needs to be suspended so we don't have any calls to
18911          * fbdev after it's finalized. MST will be destroyed later as part of
18912          * drm_mode_config_cleanup()
18913          */
18914         intel_dp_mst_suspend(i915);
18915
18916         /* poll work can call into fbdev, hence clean that up afterwards */
18917         intel_fbdev_fini(i915);
18918
18919         intel_unregister_dsm_handler();
18920
18921         intel_fbc_global_disable(i915);
18922
18923         /* flush any delayed tasks or pending work */
18924         flush_scheduled_work();
18925
18926         intel_hdcp_component_fini(i915);
18927
18928         intel_mode_config_cleanup(i915);
18929
18930         intel_overlay_cleanup(i915);
18931
18932         intel_gmbus_teardown(i915);
18933
18934         destroy_workqueue(i915->flip_wq);
18935         destroy_workqueue(i915->modeset_wq);
18936
18937         intel_fbc_cleanup_cfb(i915);
18938 }
18939
18940 /* part #3: call after gem init */
18941 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915)
18942 {
18943         intel_csr_ucode_fini(i915);
18944
18945         intel_power_domains_driver_remove(i915);
18946
18947         intel_vga_unregister(i915);
18948
18949         intel_bios_driver_remove(i915);
18950 }
18951
18952 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
18953
18954 struct intel_display_error_state {
18955
18956         u32 power_well_driver;
18957
18958         struct intel_cursor_error_state {
18959                 u32 control;
18960                 u32 position;
18961                 u32 base;
18962                 u32 size;
18963         } cursor[I915_MAX_PIPES];
18964
18965         struct intel_pipe_error_state {
18966                 bool power_domain_on;
18967                 u32 source;
18968                 u32 stat;
18969         } pipe[I915_MAX_PIPES];
18970
18971         struct intel_plane_error_state {
18972                 u32 control;
18973                 u32 stride;
18974                 u32 size;
18975                 u32 pos;
18976                 u32 addr;
18977                 u32 surface;
18978                 u32 tile_offset;
18979         } plane[I915_MAX_PIPES];
18980
18981         struct intel_transcoder_error_state {
18982                 bool available;
18983                 bool power_domain_on;
18984                 enum transcoder cpu_transcoder;
18985
18986                 u32 conf;
18987
18988                 u32 htotal;
18989                 u32 hblank;
18990                 u32 hsync;
18991                 u32 vtotal;
18992                 u32 vblank;
18993                 u32 vsync;
18994         } transcoder[5];
18995 };
18996
18997 struct intel_display_error_state *
18998 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
18999 {
19000         struct intel_display_error_state *error;
19001         int transcoders[] = {
19002                 TRANSCODER_A,
19003                 TRANSCODER_B,
19004                 TRANSCODER_C,
19005                 TRANSCODER_D,
19006                 TRANSCODER_EDP,
19007         };
19008         int i;
19009
19010         BUILD_BUG_ON(ARRAY_SIZE(transcoders) != ARRAY_SIZE(error->transcoder));
19011
19012         if (!HAS_DISPLAY(dev_priv))
19013                 return NULL;
19014
19015         error = kzalloc(sizeof(*error), GFP_ATOMIC);
19016         if (error == NULL)
19017                 return NULL;
19018
19019         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
19020                 error->power_well_driver = intel_de_read(dev_priv,
19021                                                          HSW_PWR_WELL_CTL2);
19022
19023         for_each_pipe(dev_priv, i) {
19024                 error->pipe[i].power_domain_on =
19025                         __intel_display_power_is_enabled(dev_priv,
19026                                                          POWER_DOMAIN_PIPE(i));
19027                 if (!error->pipe[i].power_domain_on)
19028                         continue;
19029
19030                 error->cursor[i].control = intel_de_read(dev_priv, CURCNTR(i));
19031                 error->cursor[i].position = intel_de_read(dev_priv, CURPOS(i));
19032                 error->cursor[i].base = intel_de_read(dev_priv, CURBASE(i));
19033
19034                 error->plane[i].control = intel_de_read(dev_priv, DSPCNTR(i));
19035                 error->plane[i].stride = intel_de_read(dev_priv, DSPSTRIDE(i));
19036                 if (INTEL_GEN(dev_priv) <= 3) {
19037                         error->plane[i].size = intel_de_read(dev_priv,
19038                                                              DSPSIZE(i));
19039                         error->plane[i].pos = intel_de_read(dev_priv,
19040                                                             DSPPOS(i));
19041                 }
19042                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
19043                         error->plane[i].addr = intel_de_read(dev_priv,
19044                                                              DSPADDR(i));
19045                 if (INTEL_GEN(dev_priv) >= 4) {
19046                         error->plane[i].surface = intel_de_read(dev_priv,
19047                                                                 DSPSURF(i));
19048                         error->plane[i].tile_offset = intel_de_read(dev_priv,
19049                                                                     DSPTILEOFF(i));
19050                 }
19051
19052                 error->pipe[i].source = intel_de_read(dev_priv, PIPESRC(i));
19053
19054                 if (HAS_GMCH(dev_priv))
19055                         error->pipe[i].stat = intel_de_read(dev_priv,
19056                                                             PIPESTAT(i));
19057         }
19058
19059         for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
19060                 enum transcoder cpu_transcoder = transcoders[i];
19061
19062                 if (!HAS_TRANSCODER(dev_priv, cpu_transcoder))
19063                         continue;
19064
19065                 error->transcoder[i].available = true;
19066                 error->transcoder[i].power_domain_on =
19067                         __intel_display_power_is_enabled(dev_priv,
19068                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
19069                 if (!error->transcoder[i].power_domain_on)
19070                         continue;
19071
19072                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
19073
19074                 error->transcoder[i].conf = intel_de_read(dev_priv,
19075                                                           PIPECONF(cpu_transcoder));
19076                 error->transcoder[i].htotal = intel_de_read(dev_priv,
19077                                                             HTOTAL(cpu_transcoder));
19078                 error->transcoder[i].hblank = intel_de_read(dev_priv,
19079                                                             HBLANK(cpu_transcoder));
19080                 error->transcoder[i].hsync = intel_de_read(dev_priv,
19081                                                            HSYNC(cpu_transcoder));
19082                 error->transcoder[i].vtotal = intel_de_read(dev_priv,
19083                                                             VTOTAL(cpu_transcoder));
19084                 error->transcoder[i].vblank = intel_de_read(dev_priv,
19085                                                             VBLANK(cpu_transcoder));
19086                 error->transcoder[i].vsync = intel_de_read(dev_priv,
19087                                                            VSYNC(cpu_transcoder));
19088         }
19089
19090         return error;
19091 }
19092
19093 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
19094
19095 void
19096 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
19097                                 struct intel_display_error_state *error)
19098 {
19099         struct drm_i915_private *dev_priv = m->i915;
19100         int i;
19101
19102         if (!error)
19103                 return;
19104
19105         err_printf(m, "Num Pipes: %d\n", INTEL_NUM_PIPES(dev_priv));
19106         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
19107                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
19108                            error->power_well_driver);
19109         for_each_pipe(dev_priv, i) {
19110                 err_printf(m, "Pipe [%d]:\n", i);
19111                 err_printf(m, "  Power: %s\n",
19112                            onoff(error->pipe[i].power_domain_on));
19113                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
19114                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
19115
19116                 err_printf(m, "Plane [%d]:\n", i);
19117                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
19118                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
19119                 if (INTEL_GEN(dev_priv) <= 3) {
19120                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
19121                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
19122                 }
19123                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
19124                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
19125                 if (INTEL_GEN(dev_priv) >= 4) {
19126                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
19127                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
19128                 }
19129
19130                 err_printf(m, "Cursor [%d]:\n", i);
19131                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
19132                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
19133                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
19134         }
19135
19136         for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
19137                 if (!error->transcoder[i].available)
19138                         continue;
19139
19140                 err_printf(m, "CPU transcoder: %s\n",
19141                            transcoder_name(error->transcoder[i].cpu_transcoder));
19142                 err_printf(m, "  Power: %s\n",
19143                            onoff(error->transcoder[i].power_domain_on));
19144                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
19145                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
19146                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
19147                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
19148                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
19149                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
19150                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
19151         }
19152 }
19153
19154 #endif