2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <acpi/video.h>
28 #include <linux/i2c.h>
29 #include <linux/input.h>
30 #include <linux/intel-iommu.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/dma-resv.h>
34 #include <linux/slab.h>
36 #include <drm/drm_atomic.h>
37 #include <drm/drm_atomic_helper.h>
38 #include <drm/drm_atomic_uapi.h>
39 #include <drm/drm_damage_helper.h>
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_edid.h>
42 #include <drm/drm_fourcc.h>
43 #include <drm/drm_plane_helper.h>
44 #include <drm/drm_probe_helper.h>
45 #include <drm/drm_rect.h>
47 #include "display/intel_audio.h"
48 #include "display/intel_crt.h"
49 #include "display/intel_ddi.h"
50 #include "display/intel_display_debugfs.h"
51 #include "display/intel_dp.h"
52 #include "display/intel_dp_mst.h"
53 #include "display/intel_dpll.h"
54 #include "display/intel_dpll_mgr.h"
55 #include "display/intel_dsi.h"
56 #include "display/intel_dvo.h"
57 #include "display/intel_fb.h"
58 #include "display/intel_gmbus.h"
59 #include "display/intel_hdmi.h"
60 #include "display/intel_lvds.h"
61 #include "display/intel_sdvo.h"
62 #include "display/intel_tv.h"
63 #include "display/intel_vdsc.h"
64 #include "display/intel_vrr.h"
66 #include "gem/i915_gem_lmem.h"
67 #include "gem/i915_gem_object.h"
69 #include "gt/intel_rps.h"
70 #include "gt/gen8_ppgtt.h"
75 #include "intel_acpi.h"
76 #include "intel_atomic.h"
77 #include "intel_atomic_plane.h"
79 #include "intel_cdclk.h"
80 #include "intel_color.h"
81 #include "intel_crtc.h"
83 #include "intel_display_types.h"
84 #include "intel_dmc.h"
85 #include "intel_dp_link_training.h"
86 #include "intel_fbc.h"
87 #include "intel_fdi.h"
88 #include "intel_fbdev.h"
89 #include "intel_fifo_underrun.h"
90 #include "intel_frontbuffer.h"
91 #include "intel_hdcp.h"
92 #include "intel_hotplug.h"
93 #include "intel_overlay.h"
94 #include "intel_pipe_crc.h"
96 #include "intel_pps.h"
97 #include "intel_psr.h"
98 #include "intel_quirks.h"
99 #include "intel_sideband.h"
100 #include "intel_sprite.h"
101 #include "intel_tc.h"
102 #include "intel_vga.h"
103 #include "i9xx_plane.h"
104 #include "skl_scaler.h"
105 #include "skl_universal_plane.h"
107 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
108 struct intel_crtc_state *pipe_config);
109 static void ilk_pch_clock_get(struct intel_crtc *crtc,
110 struct intel_crtc_state *pipe_config);
112 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
113 struct drm_i915_gem_object *obj,
114 struct drm_mode_fb_cmd2 *mode_cmd);
115 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
116 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
117 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
118 const struct intel_link_m_n *m_n,
119 const struct intel_link_m_n *m2_n2);
120 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
121 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
122 static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state);
123 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
124 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
125 static void intel_modeset_setup_hw_state(struct drm_device *dev,
126 struct drm_modeset_acquire_ctx *ctx);
129 struct i915_address_space vm;
131 struct drm_i915_gem_object *obj;
132 struct i915_vma *vma;
136 #define i915_is_dpt(vm) ((vm)->is_dpt)
138 static inline struct i915_dpt *
139 i915_vm_to_dpt(struct i915_address_space *vm)
141 BUILD_BUG_ON(offsetof(struct i915_dpt, vm));
142 GEM_BUG_ON(!i915_is_dpt(vm));
143 return container_of(vm, struct i915_dpt, vm);
146 #define dpt_total_entries(dpt) ((dpt)->vm.total >> PAGE_SHIFT)
148 static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
153 static void dpt_insert_page(struct i915_address_space *vm,
156 enum i915_cache_level level,
159 struct i915_dpt *dpt = i915_vm_to_dpt(vm);
160 gen8_pte_t __iomem *base = dpt->iomem;
162 gen8_set_pte(base + offset / I915_GTT_PAGE_SIZE,
163 vm->pte_encode(addr, level, flags));
166 static void dpt_insert_entries(struct i915_address_space *vm,
167 struct i915_vma *vma,
168 enum i915_cache_level level,
171 struct i915_dpt *dpt = i915_vm_to_dpt(vm);
172 gen8_pte_t __iomem *base = dpt->iomem;
173 const gen8_pte_t pte_encode = vm->pte_encode(0, level, flags);
174 struct sgt_iter sgt_iter;
179 * Note that we ignore PTE_READ_ONLY here. The caller must be careful
180 * not to allow the user to override access to a read only page.
183 i = vma->node.start / I915_GTT_PAGE_SIZE;
184 for_each_sgt_daddr(addr, sgt_iter, vma->pages)
185 gen8_set_pte(&base[i++], pte_encode | addr);
188 static void dpt_clear_range(struct i915_address_space *vm,
189 u64 start, u64 length)
193 static void dpt_bind_vma(struct i915_address_space *vm,
194 struct i915_vm_pt_stash *stash,
195 struct i915_vma *vma,
196 enum i915_cache_level cache_level,
199 struct drm_i915_gem_object *obj = vma->obj;
202 /* Applicable to VLV (gen8+ do not support RO in the GGTT) */
204 if (vma->vm->has_read_only && i915_gem_object_is_readonly(obj))
205 pte_flags |= PTE_READ_ONLY;
206 if (i915_gem_object_is_lmem(obj))
209 vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags);
211 vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
214 * Without aliasing PPGTT there's no difference between
215 * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
216 * upgrade to both bound if we bind either to avoid double-binding.
218 atomic_or(I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND, &vma->flags);
221 static void dpt_unbind_vma(struct i915_address_space *vm, struct i915_vma *vma)
223 vm->clear_range(vm, vma->node.start, vma->size);
226 static void dpt_cleanup(struct i915_address_space *vm)
228 struct i915_dpt *dpt = i915_vm_to_dpt(vm);
230 i915_gem_object_put(dpt->obj);
233 static struct i915_address_space *
234 intel_dpt_create(struct intel_framebuffer *fb)
236 struct drm_gem_object *obj = &intel_fb_obj(&fb->base)->base;
237 struct drm_i915_private *i915 = to_i915(obj->dev);
238 struct drm_i915_gem_object *dpt_obj;
239 struct i915_address_space *vm;
240 struct i915_dpt *dpt;
244 if (intel_fb_needs_pot_stride_remap(fb))
245 size = intel_remapped_info_size(&fb->remapped_view.gtt.remapped);
247 size = DIV_ROUND_UP_ULL(obj->size, I915_GTT_PAGE_SIZE);
249 size = round_up(size * sizeof(gen8_pte_t), I915_GTT_PAGE_SIZE);
252 dpt_obj = i915_gem_object_create_lmem(i915, size, 0);
254 dpt_obj = i915_gem_object_create_stolen(i915, size);
256 return ERR_CAST(dpt_obj);
258 ret = i915_gem_object_set_cache_level(dpt_obj, I915_CACHE_NONE);
260 i915_gem_object_put(dpt_obj);
264 dpt = kzalloc(sizeof(*dpt), GFP_KERNEL);
266 i915_gem_object_put(dpt_obj);
267 return ERR_PTR(-ENOMEM);
274 vm->dma = i915->drm.dev;
275 vm->total = (size / sizeof(gen8_pte_t)) * I915_GTT_PAGE_SIZE;
278 i915_address_space_init(vm, VM_CLASS_DPT);
280 vm->insert_page = dpt_insert_page;
281 vm->clear_range = dpt_clear_range;
282 vm->insert_entries = dpt_insert_entries;
283 vm->cleanup = dpt_cleanup;
285 vm->vma_ops.bind_vma = dpt_bind_vma;
286 vm->vma_ops.unbind_vma = dpt_unbind_vma;
287 vm->vma_ops.set_pages = ggtt_set_pages;
288 vm->vma_ops.clear_pages = clear_pages;
290 vm->pte_encode = gen8_ggtt_pte_encode;
297 static void intel_dpt_destroy(struct i915_address_space *vm)
299 struct i915_dpt *dpt = i915_vm_to_dpt(vm);
301 i915_vm_close(&dpt->vm);
304 /* returns HPLL frequency in kHz */
305 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
307 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
309 /* Obtain SKU information */
310 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
311 CCK_FUSE_HPLL_FREQ_MASK;
313 return vco_freq[hpll_freq] * 1000;
316 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
317 const char *name, u32 reg, int ref_freq)
322 val = vlv_cck_read(dev_priv, reg);
323 divider = val & CCK_FREQUENCY_VALUES;
325 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
326 (divider << CCK_FREQUENCY_STATUS_SHIFT),
327 "%s change in progress\n", name);
329 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
332 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
333 const char *name, u32 reg)
337 vlv_cck_get(dev_priv);
339 if (dev_priv->hpll_freq == 0)
340 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
342 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
344 vlv_cck_put(dev_priv);
349 static void intel_update_czclk(struct drm_i915_private *dev_priv)
351 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
354 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
355 CCK_CZ_CLOCK_CONTROL);
357 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
358 dev_priv->czclk_freq);
361 /* WA Display #0827: Gen9:all */
363 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
366 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
367 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS);
369 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
370 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
373 /* Wa_2006604312:icl,ehl */
375 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
379 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
380 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
382 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
383 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
387 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
389 return crtc_state->master_transcoder != INVALID_TRANSCODER;
393 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
395 return crtc_state->sync_mode_slaves_mask != 0;
399 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
401 return is_trans_port_sync_master(crtc_state) ||
402 is_trans_port_sync_slave(crtc_state);
405 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
408 i915_reg_t reg = PIPEDSL(pipe);
412 if (DISPLAY_VER(dev_priv) == 2)
413 line_mask = DSL_LINEMASK_GEN2;
415 line_mask = DSL_LINEMASK_GEN3;
417 line1 = intel_de_read(dev_priv, reg) & line_mask;
419 line2 = intel_de_read(dev_priv, reg) & line_mask;
421 return line1 != line2;
424 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
426 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
427 enum pipe pipe = crtc->pipe;
429 /* Wait for the display line to settle/start moving */
430 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
431 drm_err(&dev_priv->drm,
432 "pipe %c scanline %s wait timed out\n",
433 pipe_name(pipe), onoff(state));
436 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
438 wait_for_pipe_scanline_moving(crtc, false);
441 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
443 wait_for_pipe_scanline_moving(crtc, true);
447 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
449 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
450 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
452 if (DISPLAY_VER(dev_priv) >= 4) {
453 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
454 i915_reg_t reg = PIPECONF(cpu_transcoder);
456 /* Wait for the Pipe State to go off */
457 if (intel_de_wait_for_clear(dev_priv, reg,
458 I965_PIPECONF_ACTIVE, 100))
459 drm_WARN(&dev_priv->drm, 1,
460 "pipe_off wait timed out\n");
462 intel_wait_for_pipe_scanline_stopped(crtc);
466 /* Only for pre-ILK configs */
467 void assert_pll(struct drm_i915_private *dev_priv,
468 enum pipe pipe, bool state)
473 val = intel_de_read(dev_priv, DPLL(pipe));
474 cur_state = !!(val & DPLL_VCO_ENABLE);
475 I915_STATE_WARN(cur_state != state,
476 "PLL state assertion failure (expected %s, current %s)\n",
477 onoff(state), onoff(cur_state));
480 /* XXX: the dsi pll is shared between MIPI DSI ports */
481 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
486 vlv_cck_get(dev_priv);
487 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
488 vlv_cck_put(dev_priv);
490 cur_state = val & DSI_PLL_VCO_EN;
491 I915_STATE_WARN(cur_state != state,
492 "DSI PLL state assertion failure (expected %s, current %s)\n",
493 onoff(state), onoff(cur_state));
496 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
497 enum pipe pipe, bool state)
501 if (HAS_DDI(dev_priv)) {
503 * DDI does not have a specific FDI_TX register.
505 * FDI is never fed from EDP transcoder
506 * so pipe->transcoder cast is fine here.
508 enum transcoder cpu_transcoder = (enum transcoder)pipe;
509 u32 val = intel_de_read(dev_priv,
510 TRANS_DDI_FUNC_CTL(cpu_transcoder));
511 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
513 u32 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe));
514 cur_state = !!(val & FDI_TX_ENABLE);
516 I915_STATE_WARN(cur_state != state,
517 "FDI TX state assertion failure (expected %s, current %s)\n",
518 onoff(state), onoff(cur_state));
520 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
521 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
523 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
524 enum pipe pipe, bool state)
529 val = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
530 cur_state = !!(val & FDI_RX_ENABLE);
531 I915_STATE_WARN(cur_state != state,
532 "FDI RX state assertion failure (expected %s, current %s)\n",
533 onoff(state), onoff(cur_state));
535 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
536 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
538 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
543 /* ILK FDI PLL is always enabled */
544 if (IS_IRONLAKE(dev_priv))
547 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
548 if (HAS_DDI(dev_priv))
551 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe));
552 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
555 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
556 enum pipe pipe, bool state)
561 val = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
562 cur_state = !!(val & FDI_RX_PLL_ENABLE);
563 I915_STATE_WARN(cur_state != state,
564 "FDI RX PLL assertion failure (expected %s, current %s)\n",
565 onoff(state), onoff(cur_state));
568 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
572 enum pipe panel_pipe = INVALID_PIPE;
575 if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv)))
578 if (HAS_PCH_SPLIT(dev_priv)) {
581 pp_reg = PP_CONTROL(0);
582 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
585 case PANEL_PORT_SELECT_LVDS:
586 intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
588 case PANEL_PORT_SELECT_DPA:
589 g4x_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
591 case PANEL_PORT_SELECT_DPC:
592 g4x_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
594 case PANEL_PORT_SELECT_DPD:
595 g4x_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
598 MISSING_CASE(port_sel);
601 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
602 /* presumably write lock depends on pipe, not port select */
603 pp_reg = PP_CONTROL(pipe);
608 pp_reg = PP_CONTROL(0);
609 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
611 drm_WARN_ON(&dev_priv->drm,
612 port_sel != PANEL_PORT_SELECT_LVDS);
613 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
616 val = intel_de_read(dev_priv, pp_reg);
617 if (!(val & PANEL_POWER_ON) ||
618 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
621 I915_STATE_WARN(panel_pipe == pipe && locked,
622 "panel assertion failure, pipe %c regs locked\n",
626 void assert_pipe(struct drm_i915_private *dev_priv,
627 enum transcoder cpu_transcoder, bool state)
630 enum intel_display_power_domain power_domain;
631 intel_wakeref_t wakeref;
633 /* we keep both pipes enabled on 830 */
634 if (IS_I830(dev_priv))
637 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
638 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
640 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
641 cur_state = !!(val & PIPECONF_ENABLE);
643 intel_display_power_put(dev_priv, power_domain, wakeref);
648 I915_STATE_WARN(cur_state != state,
649 "transcoder %s assertion failure (expected %s, current %s)\n",
650 transcoder_name(cpu_transcoder),
651 onoff(state), onoff(cur_state));
654 static void assert_plane(struct intel_plane *plane, bool state)
659 cur_state = plane->get_hw_state(plane, &pipe);
661 I915_STATE_WARN(cur_state != state,
662 "%s assertion failure (expected %s, current %s)\n",
663 plane->base.name, onoff(state), onoff(cur_state));
666 #define assert_plane_enabled(p) assert_plane(p, true)
667 #define assert_plane_disabled(p) assert_plane(p, false)
669 static void assert_planes_disabled(struct intel_crtc *crtc)
671 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
672 struct intel_plane *plane;
674 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
675 assert_plane_disabled(plane);
678 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
684 val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe));
685 enabled = !!(val & TRANS_ENABLE);
686 I915_STATE_WARN(enabled,
687 "transcoder assertion failed, should be off on pipe %c but is still active\n",
691 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
692 enum pipe pipe, enum port port,
698 state = g4x_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
700 I915_STATE_WARN(state && port_pipe == pipe,
701 "PCH DP %c enabled on transcoder %c, should be disabled\n",
702 port_name(port), pipe_name(pipe));
704 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
705 "IBX PCH DP %c still using transcoder B\n",
709 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
710 enum pipe pipe, enum port port,
716 state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
718 I915_STATE_WARN(state && port_pipe == pipe,
719 "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
720 port_name(port), pipe_name(pipe));
722 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
723 "IBX PCH HDMI %c still using transcoder B\n",
727 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
732 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
733 assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
734 assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
736 I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
738 "PCH VGA enabled on transcoder %c, should be disabled\n",
741 I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
743 "PCH LVDS enabled on transcoder %c, should be disabled\n",
746 /* PCH SDVOB multiplex with HDMIB */
747 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
748 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
749 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
752 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
753 struct intel_digital_port *dig_port,
754 unsigned int expected_mask)
759 switch (dig_port->base.port) {
761 port_mask = DPLL_PORTB_READY_MASK;
765 port_mask = DPLL_PORTC_READY_MASK;
770 port_mask = DPLL_PORTD_READY_MASK;
771 dpll_reg = DPIO_PHY_STATUS;
777 if (intel_de_wait_for_register(dev_priv, dpll_reg,
778 port_mask, expected_mask, 1000))
779 drm_WARN(&dev_priv->drm, 1,
780 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
781 dig_port->base.base.base.id, dig_port->base.base.name,
782 intel_de_read(dev_priv, dpll_reg) & port_mask,
786 static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
788 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
789 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
790 enum pipe pipe = crtc->pipe;
792 u32 val, pipeconf_val;
794 /* Make sure PCH DPLL is enabled */
795 assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
797 /* FDI must be feeding us bits for PCH ports */
798 assert_fdi_tx_enabled(dev_priv, pipe);
799 assert_fdi_rx_enabled(dev_priv, pipe);
801 if (HAS_PCH_CPT(dev_priv)) {
802 reg = TRANS_CHICKEN2(pipe);
803 val = intel_de_read(dev_priv, reg);
805 * Workaround: Set the timing override bit
806 * before enabling the pch transcoder.
808 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
809 /* Configure frame start delay to match the CPU */
810 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
811 val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
812 intel_de_write(dev_priv, reg, val);
815 reg = PCH_TRANSCONF(pipe);
816 val = intel_de_read(dev_priv, reg);
817 pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe));
819 if (HAS_PCH_IBX(dev_priv)) {
820 /* Configure frame start delay to match the CPU */
821 val &= ~TRANS_FRAME_START_DELAY_MASK;
822 val |= TRANS_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
825 * Make the BPC in transcoder be consistent with
826 * that in pipeconf reg. For HDMI we must use 8bpc
827 * here for both 8bpc and 12bpc.
829 val &= ~PIPECONF_BPC_MASK;
830 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
831 val |= PIPECONF_8BPC;
833 val |= pipeconf_val & PIPECONF_BPC_MASK;
836 val &= ~TRANS_INTERLACE_MASK;
837 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
838 if (HAS_PCH_IBX(dev_priv) &&
839 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
840 val |= TRANS_LEGACY_INTERLACED_ILK;
842 val |= TRANS_INTERLACED;
844 val |= TRANS_PROGRESSIVE;
847 intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
848 if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
849 drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",
853 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
854 enum transcoder cpu_transcoder)
856 u32 val, pipeconf_val;
858 /* FDI must be feeding us bits for PCH ports */
859 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
860 assert_fdi_rx_enabled(dev_priv, PIPE_A);
862 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
863 /* Workaround: set timing override bit. */
864 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
865 /* Configure frame start delay to match the CPU */
866 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
867 val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
868 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
871 pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
873 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
874 PIPECONF_INTERLACED_ILK)
875 val |= TRANS_INTERLACED;
877 val |= TRANS_PROGRESSIVE;
879 intel_de_write(dev_priv, LPT_TRANSCONF, val);
880 if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
881 TRANS_STATE_ENABLE, 100))
882 drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n");
885 static void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv,
891 /* FDI relies on the transcoder */
892 assert_fdi_tx_disabled(dev_priv, pipe);
893 assert_fdi_rx_disabled(dev_priv, pipe);
895 /* Ports must be off as well */
896 assert_pch_ports_disabled(dev_priv, pipe);
898 reg = PCH_TRANSCONF(pipe);
899 val = intel_de_read(dev_priv, reg);
900 val &= ~TRANS_ENABLE;
901 intel_de_write(dev_priv, reg, val);
902 /* wait for PCH transcoder off, transcoder state */
903 if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
904 drm_err(&dev_priv->drm, "failed to disable transcoder %c\n",
907 if (HAS_PCH_CPT(dev_priv)) {
908 /* Workaround: Clear the timing override chicken bit again. */
909 reg = TRANS_CHICKEN2(pipe);
910 val = intel_de_read(dev_priv, reg);
911 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
912 intel_de_write(dev_priv, reg, val);
916 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
920 val = intel_de_read(dev_priv, LPT_TRANSCONF);
921 val &= ~TRANS_ENABLE;
922 intel_de_write(dev_priv, LPT_TRANSCONF, val);
923 /* wait for PCH transcoder off, transcoder state */
924 if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
925 TRANS_STATE_ENABLE, 50))
926 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
928 /* Workaround: clear timing override bit. */
929 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
930 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
931 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
934 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
936 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
938 if (HAS_PCH_LPT(dev_priv))
944 void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
946 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
947 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
948 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
949 enum pipe pipe = crtc->pipe;
953 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
955 assert_planes_disabled(crtc);
958 * A pipe without a PLL won't actually be able to drive bits from
959 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
962 if (HAS_GMCH(dev_priv)) {
963 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
964 assert_dsi_pll_enabled(dev_priv);
966 assert_pll_enabled(dev_priv, pipe);
968 if (new_crtc_state->has_pch_encoder) {
969 /* if driving the PCH, we need FDI enabled */
970 assert_fdi_rx_pll_enabled(dev_priv,
971 intel_crtc_pch_transcoder(crtc));
972 assert_fdi_tx_pll_enabled(dev_priv,
973 (enum pipe) cpu_transcoder);
975 /* FIXME: assert CPU port conditions for SNB+ */
978 /* Wa_22012358565:adlp */
979 if (DISPLAY_VER(dev_priv) == 13)
980 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe),
981 0, PIPE_ARB_USE_PROG_SLOTS);
983 reg = PIPECONF(cpu_transcoder);
984 val = intel_de_read(dev_priv, reg);
985 if (val & PIPECONF_ENABLE) {
986 /* we keep both pipes enabled on 830 */
987 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
991 intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE);
992 intel_de_posting_read(dev_priv, reg);
995 * Until the pipe starts PIPEDSL reads will return a stale value,
996 * which causes an apparent vblank timestamp jump when PIPEDSL
997 * resets to its proper value. That also messes up the frame count
998 * when it's derived from the timestamps. So let's wait for the
999 * pipe to start properly before we call drm_crtc_vblank_on()
1001 if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
1002 intel_wait_for_pipe_scanline_moving(crtc);
1005 void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1007 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1008 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1009 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1010 enum pipe pipe = crtc->pipe;
1014 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));
1017 * Make sure planes won't keep trying to pump pixels to us,
1018 * or we might hang the display.
1020 assert_planes_disabled(crtc);
1022 reg = PIPECONF(cpu_transcoder);
1023 val = intel_de_read(dev_priv, reg);
1024 if ((val & PIPECONF_ENABLE) == 0)
1028 * Double wide has implications for planes
1029 * so best keep it disabled when not needed.
1031 if (old_crtc_state->double_wide)
1032 val &= ~PIPECONF_DOUBLE_WIDE;
1034 /* Don't disable pipe or pipe PLLs if needed */
1035 if (!IS_I830(dev_priv))
1036 val &= ~PIPECONF_ENABLE;
1038 intel_de_write(dev_priv, reg, val);
1039 if ((val & PIPECONF_ENABLE) == 0)
1040 intel_wait_for_pipe_off(old_crtc_state);
1044 intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
1047 return info->is_yuv &&
1048 info->num_planes == (is_ccs_modifier(modifier) ? 4 : 2);
1052 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
1054 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1055 unsigned int cpp = fb->format->cpp[color_plane];
1057 switch (fb->modifier) {
1058 case DRM_FORMAT_MOD_LINEAR:
1059 return intel_tile_size(dev_priv);
1060 case I915_FORMAT_MOD_X_TILED:
1061 if (DISPLAY_VER(dev_priv) == 2)
1065 case I915_FORMAT_MOD_Y_TILED_CCS:
1066 if (is_ccs_plane(fb, color_plane))
1069 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
1070 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
1071 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
1072 if (is_ccs_plane(fb, color_plane))
1075 case I915_FORMAT_MOD_Y_TILED:
1076 if (DISPLAY_VER(dev_priv) == 2 || HAS_128_BYTE_Y_TILING(dev_priv))
1080 case I915_FORMAT_MOD_Yf_TILED_CCS:
1081 if (is_ccs_plane(fb, color_plane))
1084 case I915_FORMAT_MOD_Yf_TILED:
1100 MISSING_CASE(fb->modifier);
1106 intel_fb_align_height(const struct drm_framebuffer *fb,
1107 int color_plane, unsigned int height)
1109 unsigned int tile_height = intel_tile_height(fb, color_plane);
1111 return ALIGN(height, tile_height);
1114 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
1116 unsigned int size = 0;
1119 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
1120 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width;
1125 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
1127 unsigned int size = 0;
1130 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++)
1131 size += rem_info->plane[i].dst_stride * rem_info->plane[i].height;
1136 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
1138 if (DISPLAY_VER(dev_priv) >= 9)
1140 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
1141 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1143 else if (DISPLAY_VER(dev_priv) >= 4)
1149 static bool has_async_flips(struct drm_i915_private *i915)
1151 return DISPLAY_VER(i915) >= 5;
1154 unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
1157 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1159 if (intel_fb_uses_dpt(fb))
1162 /* AUX_DIST needs only 4K alignment */
1163 if (is_ccs_plane(fb, color_plane))
1166 if (is_semiplanar_uv_plane(fb, color_plane)) {
1168 * TODO: cross-check wrt. the bspec stride in bytes * 64 bytes
1169 * alignment for linear UV planes on all platforms.
1171 if (DISPLAY_VER(dev_priv) >= 12) {
1172 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
1173 return intel_linear_alignment(dev_priv);
1175 return intel_tile_row_size(fb, color_plane);
1181 drm_WARN_ON(&dev_priv->drm, color_plane != 0);
1183 switch (fb->modifier) {
1184 case DRM_FORMAT_MOD_LINEAR:
1185 return intel_linear_alignment(dev_priv);
1186 case I915_FORMAT_MOD_X_TILED:
1187 if (has_async_flips(dev_priv))
1190 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
1191 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
1192 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
1194 case I915_FORMAT_MOD_Y_TILED_CCS:
1195 case I915_FORMAT_MOD_Yf_TILED_CCS:
1196 case I915_FORMAT_MOD_Y_TILED:
1197 case I915_FORMAT_MOD_Yf_TILED:
1198 return 1 * 1024 * 1024;
1200 MISSING_CASE(fb->modifier);
1205 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
1207 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1208 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1210 return DISPLAY_VER(dev_priv) < 4 ||
1212 plane_state->view.gtt.type == I915_GGTT_VIEW_NORMAL);
1215 static struct i915_vma *
1216 intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
1217 const struct i915_ggtt_view *view,
1219 unsigned long *out_flags,
1220 struct i915_address_space *vm)
1222 struct drm_device *dev = fb->dev;
1223 struct drm_i915_private *dev_priv = to_i915(dev);
1224 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1225 struct i915_vma *vma;
1229 if (WARN_ON(!i915_gem_object_is_framebuffer(obj)))
1230 return ERR_PTR(-EINVAL);
1232 alignment = 4096 * 512;
1234 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
1236 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
1242 vma = i915_vma_instance(obj, vm, view);
1246 if (i915_vma_misplaced(vma, 0, alignment, 0)) {
1247 ret = i915_vma_unbind(vma);
1254 ret = i915_vma_pin(vma, 0, alignment, PIN_GLOBAL);
1260 vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
1262 i915_gem_object_flush_if_display(obj);
1266 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
1272 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1274 const struct i915_ggtt_view *view,
1276 unsigned long *out_flags)
1278 struct drm_device *dev = fb->dev;
1279 struct drm_i915_private *dev_priv = to_i915(dev);
1280 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1281 intel_wakeref_t wakeref;
1282 struct i915_gem_ww_ctx ww;
1283 struct i915_vma *vma;
1284 unsigned int pinctl;
1288 if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj)))
1289 return ERR_PTR(-EINVAL);
1292 alignment = intel_cursor_alignment(dev_priv);
1294 alignment = intel_surf_alignment(fb, 0);
1295 if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment)))
1296 return ERR_PTR(-EINVAL);
1298 /* Note that the w/a also requires 64 PTE of padding following the
1299 * bo. We currently fill all unused PTE with the shadow page and so
1300 * we should always have valid PTE following the scanout preventing
1303 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
1304 alignment = 256 * 1024;
1307 * Global gtt pte registers are special registers which actually forward
1308 * writes to a chunk of system memory. Which means that there is no risk
1309 * that the register values disappear as soon as we call
1310 * intel_runtime_pm_put(), so it is correct to wrap only the
1311 * pin/unpin/fence and not more.
1313 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
1315 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
1318 * Valleyview is definitely limited to scanning out the first
1319 * 512MiB. Lets presume this behaviour was inherited from the
1320 * g4x display engine and that all earlier gen are similarly
1321 * limited. Testing suggests that it is a little more
1322 * complicated than this. For example, Cherryview appears quite
1323 * happy to scanout from anywhere within its global aperture.
1326 if (HAS_GMCH(dev_priv))
1327 pinctl |= PIN_MAPPABLE;
1329 i915_gem_ww_ctx_init(&ww, true);
1331 ret = i915_gem_object_lock(obj, &ww);
1332 if (!ret && phys_cursor)
1333 ret = i915_gem_object_attach_phys(obj, alignment);
1335 ret = i915_gem_object_pin_pages(obj);
1340 vma = i915_gem_object_pin_to_display_plane(obj, &ww, alignment,
1348 if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
1350 * Install a fence for tiled scan-out. Pre-i965 always needs a
1351 * fence, whereas 965+ only requires a fence if using
1352 * framebuffer compression. For simplicity, we always, when
1353 * possible, install a fence as the cost is not that onerous.
1355 * If we fail to fence the tiled scanout, then either the
1356 * modeset will reject the change (which is highly unlikely as
1357 * the affected systems, all but one, do not have unmappable
1358 * space) or we will not be able to enable full powersaving
1359 * techniques (also likely not to apply due to various limits
1360 * FBC and the like impose on the size of the buffer, which
1361 * presumably we violated anyway with this unmappable buffer).
1362 * Anyway, it is presumably better to stumble onwards with
1363 * something and try to run the system in a "less than optimal"
1364 * mode that matches the user configuration.
1366 ret = i915_vma_pin_fence(vma);
1367 if (ret != 0 && DISPLAY_VER(dev_priv) < 4) {
1368 i915_vma_unpin(vma);
1374 *out_flags |= PLANE_HAS_FENCE;
1380 i915_gem_object_unpin_pages(obj);
1382 if (ret == -EDEADLK) {
1383 ret = i915_gem_ww_ctx_backoff(&ww);
1387 i915_gem_ww_ctx_fini(&ww);
1391 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
1392 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
1396 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
1398 if (flags & PLANE_HAS_FENCE)
1399 i915_vma_unpin_fence(vma);
1400 i915_vma_unpin(vma);
1405 * Convert the x/y offsets into a linear offset.
1406 * Only valid with 0/180 degree rotation, which is fine since linear
1407 * offset is only used with linear buffers on pre-hsw and tiled buffers
1408 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
1410 u32 intel_fb_xy_to_linear(int x, int y,
1411 const struct intel_plane_state *state,
1414 const struct drm_framebuffer *fb = state->hw.fb;
1415 unsigned int cpp = fb->format->cpp[color_plane];
1416 unsigned int pitch = state->view.color_plane[color_plane].stride;
1418 return y * pitch + x * cpp;
1422 * Add the x/y offsets derived from fb->offsets[] to the user
1423 * specified plane src x/y offsets. The resulting x/y offsets
1424 * specify the start of scanout from the beginning of the gtt mapping.
1426 void intel_add_fb_offsets(int *x, int *y,
1427 const struct intel_plane_state *state,
1431 *x += state->view.color_plane[color_plane].x;
1432 *y += state->view.color_plane[color_plane].y;
1435 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
1437 switch (fb_modifier) {
1438 case I915_FORMAT_MOD_X_TILED:
1439 return I915_TILING_X;
1440 case I915_FORMAT_MOD_Y_TILED:
1441 case I915_FORMAT_MOD_Y_TILED_CCS:
1442 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
1443 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
1444 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
1445 return I915_TILING_Y;
1447 return I915_TILING_NONE;
1452 * From the Sky Lake PRM:
1453 * "The Color Control Surface (CCS) contains the compression status of
1454 * the cache-line pairs. The compression state of the cache-line pair
1455 * is specified by 2 bits in the CCS. Each CCS cache-line represents
1456 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
1457 * cache-line-pairs. CCS is always Y tiled."
1459 * Since cache line pairs refers to horizontally adjacent cache lines,
1460 * each cache line in the CCS corresponds to an area of 32x16 cache
1461 * lines on the main surface. Since each pixel is 4 bytes, this gives
1462 * us a ratio of one byte in the CCS for each 8x16 pixels in the
1465 static const struct drm_format_info skl_ccs_formats[] = {
1466 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
1467 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
1468 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
1469 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
1470 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
1471 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
1472 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
1473 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
1477 * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
1478 * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
1479 * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
1480 * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
1483 static const struct drm_format_info gen12_ccs_formats[] = {
1484 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
1485 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1486 .hsub = 1, .vsub = 1, },
1487 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
1488 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1489 .hsub = 1, .vsub = 1, },
1490 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
1491 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1492 .hsub = 1, .vsub = 1, .has_alpha = true },
1493 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
1494 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1495 .hsub = 1, .vsub = 1, .has_alpha = true },
1496 { .format = DRM_FORMAT_YUYV, .num_planes = 2,
1497 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1498 .hsub = 2, .vsub = 1, .is_yuv = true },
1499 { .format = DRM_FORMAT_YVYU, .num_planes = 2,
1500 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1501 .hsub = 2, .vsub = 1, .is_yuv = true },
1502 { .format = DRM_FORMAT_UYVY, .num_planes = 2,
1503 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1504 .hsub = 2, .vsub = 1, .is_yuv = true },
1505 { .format = DRM_FORMAT_VYUY, .num_planes = 2,
1506 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1507 .hsub = 2, .vsub = 1, .is_yuv = true },
1508 { .format = DRM_FORMAT_XYUV8888, .num_planes = 2,
1509 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1510 .hsub = 1, .vsub = 1, .is_yuv = true },
1511 { .format = DRM_FORMAT_NV12, .num_planes = 4,
1512 .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
1513 .hsub = 2, .vsub = 2, .is_yuv = true },
1514 { .format = DRM_FORMAT_P010, .num_planes = 4,
1515 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
1516 .hsub = 2, .vsub = 2, .is_yuv = true },
1517 { .format = DRM_FORMAT_P012, .num_planes = 4,
1518 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
1519 .hsub = 2, .vsub = 2, .is_yuv = true },
1520 { .format = DRM_FORMAT_P016, .num_planes = 4,
1521 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
1522 .hsub = 2, .vsub = 2, .is_yuv = true },
1526 * Same as gen12_ccs_formats[] above, but with additional surface used
1527 * to pass Clear Color information in plane 2 with 64 bits of data.
1529 static const struct drm_format_info gen12_ccs_cc_formats[] = {
1530 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
1531 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
1532 .hsub = 1, .vsub = 1, },
1533 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
1534 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
1535 .hsub = 1, .vsub = 1, },
1536 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
1537 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
1538 .hsub = 1, .vsub = 1, .has_alpha = true },
1539 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
1540 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
1541 .hsub = 1, .vsub = 1, .has_alpha = true },
1544 static const struct drm_format_info *
1545 lookup_format_info(const struct drm_format_info formats[],
1546 int num_formats, u32 format)
1550 for (i = 0; i < num_formats; i++) {
1551 if (formats[i].format == format)
1558 static const struct drm_format_info *
1559 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
1561 switch (cmd->modifier[0]) {
1562 case I915_FORMAT_MOD_Y_TILED_CCS:
1563 case I915_FORMAT_MOD_Yf_TILED_CCS:
1564 return lookup_format_info(skl_ccs_formats,
1565 ARRAY_SIZE(skl_ccs_formats),
1567 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
1568 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
1569 return lookup_format_info(gen12_ccs_formats,
1570 ARRAY_SIZE(gen12_ccs_formats),
1572 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
1573 return lookup_format_info(gen12_ccs_cc_formats,
1574 ARRAY_SIZE(gen12_ccs_cc_formats),
1581 static int gen12_ccs_aux_stride(struct drm_framebuffer *fb, int ccs_plane)
1583 return DIV_ROUND_UP(fb->pitches[skl_ccs_to_main_plane(fb, ccs_plane)],
1587 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
1588 u32 pixel_format, u64 modifier)
1590 struct intel_crtc *crtc;
1591 struct intel_plane *plane;
1593 if (!HAS_DISPLAY(dev_priv))
1597 * We assume the primary plane for pipe A has
1598 * the highest stride limits of them all,
1599 * if in case pipe A is disabled, use the first pipe from pipe_mask.
1601 crtc = intel_get_first_crtc(dev_priv);
1605 plane = to_intel_plane(crtc->base.primary);
1607 return plane->max_stride(plane, pixel_format, modifier,
1612 u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
1613 u32 pixel_format, u64 modifier)
1616 * Arbitrary limit for gen4+ chosen to match the
1617 * render engine max stride.
1619 * The new CCS hash mode makes remapping impossible
1621 if (DISPLAY_VER(dev_priv) < 4 || is_ccs_modifier(modifier) ||
1622 intel_modifier_uses_dpt(dev_priv, modifier))
1623 return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
1624 else if (DISPLAY_VER(dev_priv) >= 7)
1631 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
1633 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1636 if (is_surface_linear(fb, color_plane)) {
1637 u32 max_stride = intel_plane_fb_max_stride(dev_priv,
1642 * To make remapping with linear generally feasible
1643 * we need the stride to be page aligned.
1645 if (fb->pitches[color_plane] > max_stride &&
1646 !is_ccs_modifier(fb->modifier))
1647 return intel_tile_size(dev_priv);
1652 tile_width = intel_tile_width_bytes(fb, color_plane);
1653 if (is_ccs_modifier(fb->modifier)) {
1655 * Display WA #0531: skl,bxt,kbl,glk
1657 * Render decompression and plane width > 3840
1658 * combined with horizontal panning requires the
1659 * plane stride to be a multiple of 4. We'll just
1660 * require the entire fb to accommodate that to avoid
1661 * potential runtime errors at plane configuration time.
1663 if ((DISPLAY_VER(dev_priv) == 9 || IS_GEMINILAKE(dev_priv)) &&
1664 color_plane == 0 && fb->width > 3840)
1667 * The main surface pitch must be padded to a multiple of four
1670 else if (DISPLAY_VER(dev_priv) >= 12)
1676 static struct i915_vma *
1677 initial_plane_vma(struct drm_i915_private *i915,
1678 struct intel_initial_plane_config *plane_config)
1680 struct drm_i915_gem_object *obj;
1681 struct i915_vma *vma;
1684 if (plane_config->size == 0)
1687 base = round_down(plane_config->base,
1688 I915_GTT_MIN_ALIGNMENT);
1689 size = round_up(plane_config->base + plane_config->size,
1690 I915_GTT_MIN_ALIGNMENT);
1694 * If the FB is too big, just don't use it since fbdev is not very
1695 * important and we should probably use that space with FBC or other
1698 if (IS_ENABLED(CONFIG_FRAMEBUFFER_CONSOLE) &&
1699 size * 2 > i915->stolen_usable_size)
1702 obj = i915_gem_object_create_stolen_for_preallocated(i915, base, size);
1707 * Mark it WT ahead of time to avoid changing the
1708 * cache_level during fbdev initialization. The
1709 * unbind there would get stuck waiting for rcu.
1711 i915_gem_object_set_cache_coherency(obj, HAS_WT(i915) ?
1712 I915_CACHE_WT : I915_CACHE_NONE);
1714 switch (plane_config->tiling) {
1715 case I915_TILING_NONE:
1719 obj->tiling_and_stride =
1720 plane_config->fb->base.pitches[0] |
1721 plane_config->tiling;
1724 MISSING_CASE(plane_config->tiling);
1728 vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
1732 if (i915_ggtt_pin(vma, NULL, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base))
1735 if (i915_gem_object_is_tiled(obj) &&
1736 !i915_vma_is_map_and_fenceable(vma))
1742 i915_gem_object_put(obj);
1747 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
1748 struct intel_initial_plane_config *plane_config)
1750 struct drm_device *dev = crtc->base.dev;
1751 struct drm_i915_private *dev_priv = to_i915(dev);
1752 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
1753 struct drm_framebuffer *fb = &plane_config->fb->base;
1754 struct i915_vma *vma;
1756 switch (fb->modifier) {
1757 case DRM_FORMAT_MOD_LINEAR:
1758 case I915_FORMAT_MOD_X_TILED:
1759 case I915_FORMAT_MOD_Y_TILED:
1762 drm_dbg(&dev_priv->drm,
1763 "Unsupported modifier for initial FB: 0x%llx\n",
1768 vma = initial_plane_vma(dev_priv, plane_config);
1772 mode_cmd.pixel_format = fb->format->format;
1773 mode_cmd.width = fb->width;
1774 mode_cmd.height = fb->height;
1775 mode_cmd.pitches[0] = fb->pitches[0];
1776 mode_cmd.modifier[0] = fb->modifier;
1777 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
1779 if (intel_framebuffer_init(to_intel_framebuffer(fb),
1780 vma->obj, &mode_cmd)) {
1781 drm_dbg_kms(&dev_priv->drm, "intel fb init failed\n");
1785 plane_config->vma = vma;
1794 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
1795 struct intel_plane_state *plane_state,
1798 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1800 plane_state->uapi.visible = visible;
1803 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
1805 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
1808 static void fixup_plane_bitmasks(struct intel_crtc_state *crtc_state)
1810 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1811 struct drm_plane *plane;
1814 * Active_planes aliases if multiple "primary" or cursor planes
1815 * have been used on the same (or wrong) pipe. plane_mask uses
1816 * unique ids, hence we can use that to reconstruct active_planes.
1818 crtc_state->enabled_planes = 0;
1819 crtc_state->active_planes = 0;
1821 drm_for_each_plane_mask(plane, &dev_priv->drm,
1822 crtc_state->uapi.plane_mask) {
1823 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);
1824 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
1828 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
1829 struct intel_plane *plane)
1831 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1832 struct intel_crtc_state *crtc_state =
1833 to_intel_crtc_state(crtc->base.state);
1834 struct intel_plane_state *plane_state =
1835 to_intel_plane_state(plane->base.state);
1837 drm_dbg_kms(&dev_priv->drm,
1838 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
1839 plane->base.base.id, plane->base.name,
1840 crtc->base.base.id, crtc->base.name);
1842 intel_set_plane_visible(crtc_state, plane_state, false);
1843 fixup_plane_bitmasks(crtc_state);
1844 crtc_state->data_rate[plane->id] = 0;
1845 crtc_state->min_cdclk[plane->id] = 0;
1847 if (plane->id == PLANE_PRIMARY)
1848 hsw_disable_ips(crtc_state);
1851 * Vblank time updates from the shadow to live plane control register
1852 * are blocked if the memory self-refresh mode is active at that
1853 * moment. So to make sure the plane gets truly disabled, disable
1854 * first the self-refresh mode. The self-refresh enable bit in turn
1855 * will be checked/applied by the HW only at the next frame start
1856 * event which is after the vblank start event, so we need to have a
1857 * wait-for-vblank between disabling the plane and the pipe.
1859 if (HAS_GMCH(dev_priv) &&
1860 intel_set_memory_cxsr(dev_priv, false))
1861 intel_wait_for_vblank(dev_priv, crtc->pipe);
1864 * Gen2 reports pipe underruns whenever all planes are disabled.
1865 * So disable underrun reporting before all the planes get disabled.
1867 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)
1868 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
1870 intel_disable_plane(plane, crtc_state);
1871 intel_wait_for_vblank(dev_priv, crtc->pipe);
1874 static struct i915_vma *intel_dpt_pin(struct i915_address_space *vm)
1876 struct drm_i915_private *i915 = vm->i915;
1877 struct i915_dpt *dpt = i915_vm_to_dpt(vm);
1878 intel_wakeref_t wakeref;
1879 struct i915_vma *vma;
1880 void __iomem *iomem;
1882 wakeref = intel_runtime_pm_get(&i915->runtime_pm);
1883 atomic_inc(&i915->gpu_error.pending_fb_pin);
1885 vma = i915_gem_object_ggtt_pin(dpt->obj, NULL, 0, 4096,
1886 HAS_LMEM(i915) ? 0 : PIN_MAPPABLE);
1890 iomem = i915_vma_pin_iomap(vma);
1891 i915_vma_unpin(vma);
1892 if (IS_ERR(iomem)) {
1903 atomic_dec(&i915->gpu_error.pending_fb_pin);
1904 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
1909 static void intel_dpt_unpin(struct i915_address_space *vm)
1911 struct i915_dpt *dpt = i915_vm_to_dpt(vm);
1913 i915_vma_unpin_iomap(dpt->vma);
1914 i915_vma_put(dpt->vma);
1918 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
1919 struct intel_initial_plane_config *plane_config)
1921 struct drm_device *dev = intel_crtc->base.dev;
1922 struct drm_i915_private *dev_priv = to_i915(dev);
1924 struct drm_plane *primary = intel_crtc->base.primary;
1925 struct drm_plane_state *plane_state = primary->state;
1926 struct intel_plane *intel_plane = to_intel_plane(primary);
1927 struct intel_plane_state *intel_state =
1928 to_intel_plane_state(plane_state);
1929 struct intel_crtc_state *crtc_state =
1930 to_intel_crtc_state(intel_crtc->base.state);
1931 struct drm_framebuffer *fb;
1932 struct i915_vma *vma;
1936 * Disable planes if get_initial_plane_config() failed.
1937 * Make sure things work if the surface base is not page aligned.
1939 if (!plane_config->fb)
1942 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
1943 fb = &plane_config->fb->base;
1944 vma = plane_config->vma;
1949 * Failed to alloc the obj, check to see if we should share
1950 * an fb with another CRTC instead
1952 for_each_crtc(dev, c) {
1953 struct intel_plane_state *state;
1955 if (c == &intel_crtc->base)
1958 if (!to_intel_crtc_state(c->state)->uapi.active)
1961 state = to_intel_plane_state(c->primary->state);
1962 if (!state->ggtt_vma)
1965 if (intel_plane_ggtt_offset(state) == plane_config->base) {
1967 vma = state->ggtt_vma;
1973 * We've failed to reconstruct the BIOS FB. Current display state
1974 * indicates that the primary plane is visible, but has a NULL FB,
1975 * which will lead to problems later if we don't fix it up. The
1976 * simplest solution is to just disable the primary plane now and
1977 * pretend the BIOS never had it enabled.
1979 intel_plane_disable_noatomic(intel_crtc, intel_plane);
1980 if (crtc_state->bigjoiner) {
1981 struct intel_crtc *slave =
1982 crtc_state->bigjoiner_linked_crtc;
1983 intel_plane_disable_noatomic(slave, to_intel_plane(slave->base.primary));
1989 plane_state->rotation = plane_config->rotation;
1990 intel_fb_fill_view(to_intel_framebuffer(fb), plane_state->rotation,
1991 &intel_state->view);
1993 __i915_vma_pin(vma);
1994 intel_state->ggtt_vma = i915_vma_get(vma);
1995 if (intel_plane_uses_fence(intel_state) && i915_vma_pin_fence(vma) == 0)
1997 intel_state->flags |= PLANE_HAS_FENCE;
1999 plane_state->src_x = 0;
2000 plane_state->src_y = 0;
2001 plane_state->src_w = fb->width << 16;
2002 plane_state->src_h = fb->height << 16;
2004 plane_state->crtc_x = 0;
2005 plane_state->crtc_y = 0;
2006 plane_state->crtc_w = fb->width;
2007 plane_state->crtc_h = fb->height;
2009 if (plane_config->tiling)
2010 dev_priv->preserve_bios_swizzle = true;
2012 plane_state->fb = fb;
2013 drm_framebuffer_get(fb);
2015 plane_state->crtc = &intel_crtc->base;
2016 intel_plane_copy_uapi_to_hw_state(intel_state, intel_state,
2019 intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
2021 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2022 &to_intel_frontbuffer(fb)->bits);
2026 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
2030 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
2031 plane_state->view.color_plane[0].offset, 0);
2037 __intel_display_resume(struct drm_device *dev,
2038 struct drm_atomic_state *state,
2039 struct drm_modeset_acquire_ctx *ctx)
2041 struct drm_crtc_state *crtc_state;
2042 struct drm_crtc *crtc;
2045 intel_modeset_setup_hw_state(dev, ctx);
2046 intel_vga_redisable(to_i915(dev));
2052 * We've duplicated the state, pointers to the old state are invalid.
2054 * Don't attempt to use the old state until we commit the duplicated state.
2056 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
2058 * Force recalculation even if we restore
2059 * current state. With fast modeset this may not result
2060 * in a modeset when the state is compatible.
2062 crtc_state->mode_changed = true;
2065 /* ignore any reset values/BIOS leftovers in the WM registers */
2066 if (!HAS_GMCH(to_i915(dev)))
2067 to_intel_atomic_state(state)->skip_intermediate_wm = true;
2069 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
2071 drm_WARN_ON(dev, ret == -EDEADLK);
2075 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
2077 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
2078 intel_has_gpu_reset(&dev_priv->gt));
2081 void intel_display_prepare_reset(struct drm_i915_private *dev_priv)
2083 struct drm_device *dev = &dev_priv->drm;
2084 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
2085 struct drm_atomic_state *state;
2088 if (!HAS_DISPLAY(dev_priv))
2091 /* reset doesn't touch the display */
2092 if (!dev_priv->params.force_reset_modeset_test &&
2093 !gpu_reset_clobbers_display(dev_priv))
2096 /* We have a modeset vs reset deadlock, defensively unbreak it. */
2097 set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
2098 smp_mb__after_atomic();
2099 wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET);
2101 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
2102 drm_dbg_kms(&dev_priv->drm,
2103 "Modeset potentially stuck, unbreaking through wedging\n");
2104 intel_gt_set_wedged(&dev_priv->gt);
2108 * Need mode_config.mutex so that we don't
2109 * trample ongoing ->detect() and whatnot.
2111 mutex_lock(&dev->mode_config.mutex);
2112 drm_modeset_acquire_init(ctx, 0);
2114 ret = drm_modeset_lock_all_ctx(dev, ctx);
2115 if (ret != -EDEADLK)
2118 drm_modeset_backoff(ctx);
2121 * Disabling the crtcs gracefully seems nicer. Also the
2122 * g33 docs say we should at least disable all the planes.
2124 state = drm_atomic_helper_duplicate_state(dev, ctx);
2125 if (IS_ERR(state)) {
2126 ret = PTR_ERR(state);
2127 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n",
2132 ret = drm_atomic_helper_disable_all(dev, ctx);
2134 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
2136 drm_atomic_state_put(state);
2140 dev_priv->modeset_restore_state = state;
2141 state->acquire_ctx = ctx;
2144 void intel_display_finish_reset(struct drm_i915_private *dev_priv)
2146 struct drm_device *dev = &dev_priv->drm;
2147 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
2148 struct drm_atomic_state *state;
2151 if (!HAS_DISPLAY(dev_priv))
2154 /* reset doesn't touch the display */
2155 if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
2158 state = fetch_and_zero(&dev_priv->modeset_restore_state);
2162 /* reset doesn't touch the display */
2163 if (!gpu_reset_clobbers_display(dev_priv)) {
2164 /* for testing only restore the display */
2165 ret = __intel_display_resume(dev, state, ctx);
2167 drm_err(&dev_priv->drm,
2168 "Restoring old state failed with %i\n", ret);
2171 * The display has been reset as well,
2172 * so need a full re-initialization.
2174 intel_pps_unlock_regs_wa(dev_priv);
2175 intel_modeset_init_hw(dev_priv);
2176 intel_init_clock_gating(dev_priv);
2177 intel_hpd_init(dev_priv);
2179 ret = __intel_display_resume(dev, state, ctx);
2181 drm_err(&dev_priv->drm,
2182 "Restoring old state failed with %i\n", ret);
2184 intel_hpd_poll_disable(dev_priv);
2187 drm_atomic_state_put(state);
2189 drm_modeset_drop_locks(ctx);
2190 drm_modeset_acquire_fini(ctx);
2191 mutex_unlock(&dev->mode_config.mutex);
2193 clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
2196 static void icl_set_pipe_chicken(struct intel_crtc *crtc)
2198 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2199 enum pipe pipe = crtc->pipe;
2202 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe));
2205 * Display WA #1153: icl
2206 * enable hardware to bypass the alpha math
2207 * and rounding for per-pixel values 00 and 0xff
2209 tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
2211 * Display WA # 1605353570: icl
2212 * Set the pixel rounding bit to 1 for allowing
2213 * passthrough of Frame buffer pixels unmodified
2216 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
2219 * "The underrun recovery mechanism should be disabled
2220 * when the following is enabled for this pipe:
2222 * Downscaling (this includes YUV420 fullblend)
2227 * FIXME: enable whenever possible...
2229 if (IS_ALDERLAKE_P(dev_priv))
2230 tmp |= UNDERRUN_RECOVERY_DISABLE;
2232 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
2235 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
2237 struct drm_crtc *crtc;
2240 drm_for_each_crtc(crtc, &dev_priv->drm) {
2241 struct drm_crtc_commit *commit;
2242 spin_lock(&crtc->commit_lock);
2243 commit = list_first_entry_or_null(&crtc->commit_list,
2244 struct drm_crtc_commit, commit_entry);
2245 cleanup_done = commit ?
2246 try_wait_for_completion(&commit->cleanup_done) : true;
2247 spin_unlock(&crtc->commit_lock);
2252 drm_crtc_wait_one_vblank(crtc);
2260 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
2264 intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_GATE);
2266 mutex_lock(&dev_priv->sb_lock);
2268 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2269 temp |= SBI_SSCCTL_DISABLE;
2270 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2272 mutex_unlock(&dev_priv->sb_lock);
2275 /* Program iCLKIP clock to the desired frequency */
2276 static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
2278 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2279 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2280 int clock = crtc_state->hw.adjusted_mode.crtc_clock;
2281 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2284 lpt_disable_iclkip(dev_priv);
2286 /* The iCLK virtual clock root frequency is in MHz,
2287 * but the adjusted_mode->crtc_clock in in KHz. To get the
2288 * divisors, it is necessary to divide one by another, so we
2289 * convert the virtual clock precision to KHz here for higher
2292 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
2293 u32 iclk_virtual_root_freq = 172800 * 1000;
2294 u32 iclk_pi_range = 64;
2295 u32 desired_divisor;
2297 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
2299 divsel = (desired_divisor / iclk_pi_range) - 2;
2300 phaseinc = desired_divisor % iclk_pi_range;
2303 * Near 20MHz is a corner case which is
2304 * out of range for the 7-bit divisor
2310 /* This should not happen with any sane values */
2311 drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2312 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2313 drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(phasedir) &
2314 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2316 drm_dbg_kms(&dev_priv->drm,
2317 "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2318 clock, auxdiv, divsel, phasedir, phaseinc);
2320 mutex_lock(&dev_priv->sb_lock);
2322 /* Program SSCDIVINTPHASE6 */
2323 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2324 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2325 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2326 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2327 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2328 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2329 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2330 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2332 /* Program SSCAUXDIV */
2333 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2334 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2335 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2336 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2338 /* Enable modulator and associated divider */
2339 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2340 temp &= ~SBI_SSCCTL_DISABLE;
2341 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2343 mutex_unlock(&dev_priv->sb_lock);
2345 /* Wait for initialization time */
2348 intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2351 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
2353 u32 divsel, phaseinc, auxdiv;
2354 u32 iclk_virtual_root_freq = 172800 * 1000;
2355 u32 iclk_pi_range = 64;
2356 u32 desired_divisor;
2359 if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
2362 mutex_lock(&dev_priv->sb_lock);
2364 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2365 if (temp & SBI_SSCCTL_DISABLE) {
2366 mutex_unlock(&dev_priv->sb_lock);
2370 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2371 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
2372 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
2373 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
2374 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
2376 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2377 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
2378 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
2380 mutex_unlock(&dev_priv->sb_lock);
2382 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
2384 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
2385 desired_divisor << auxdiv);
2388 static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
2389 enum pipe pch_transcoder)
2391 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2392 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2393 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2395 intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
2396 intel_de_read(dev_priv, HTOTAL(cpu_transcoder)));
2397 intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
2398 intel_de_read(dev_priv, HBLANK(cpu_transcoder)));
2399 intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
2400 intel_de_read(dev_priv, HSYNC(cpu_transcoder)));
2402 intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
2403 intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
2404 intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
2405 intel_de_read(dev_priv, VBLANK(cpu_transcoder)));
2406 intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
2407 intel_de_read(dev_priv, VSYNC(cpu_transcoder)));
2408 intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2409 intel_de_read(dev_priv, VSYNCSHIFT(cpu_transcoder)));
2412 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
2416 temp = intel_de_read(dev_priv, SOUTH_CHICKEN1);
2417 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
2420 drm_WARN_ON(&dev_priv->drm,
2421 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) &
2423 drm_WARN_ON(&dev_priv->drm,
2424 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) &
2427 temp &= ~FDI_BC_BIFURCATION_SELECT;
2429 temp |= FDI_BC_BIFURCATION_SELECT;
2431 drm_dbg_kms(&dev_priv->drm, "%sabling fdi C rx\n",
2432 enable ? "en" : "dis");
2433 intel_de_write(dev_priv, SOUTH_CHICKEN1, temp);
2434 intel_de_posting_read(dev_priv, SOUTH_CHICKEN1);
2437 static void ivb_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
2439 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2440 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2442 switch (crtc->pipe) {
2446 if (crtc_state->fdi_lanes > 2)
2447 cpt_set_fdi_bc_bifurcation(dev_priv, false);
2449 cpt_set_fdi_bc_bifurcation(dev_priv, true);
2453 cpt_set_fdi_bc_bifurcation(dev_priv, true);
2462 * Finds the encoder associated with the given CRTC. This can only be
2463 * used when we know that the CRTC isn't feeding multiple encoders!
2465 struct intel_encoder *
2466 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
2467 const struct intel_crtc_state *crtc_state)
2469 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2470 const struct drm_connector_state *connector_state;
2471 const struct drm_connector *connector;
2472 struct intel_encoder *encoder = NULL;
2473 int num_encoders = 0;
2476 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
2477 if (connector_state->crtc != &crtc->base)
2480 encoder = to_intel_encoder(connector_state->best_encoder);
2484 drm_WARN(encoder->base.dev, num_encoders != 1,
2485 "%d encoders for pipe %c\n",
2486 num_encoders, pipe_name(crtc->pipe));
2492 * Enable PCH resources required for PCH ports:
2494 * - FDI training & RX/TX
2495 * - update transcoder timings
2496 * - DP transcoding bits
2499 static void ilk_pch_enable(const struct intel_atomic_state *state,
2500 const struct intel_crtc_state *crtc_state)
2502 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2503 struct drm_device *dev = crtc->base.dev;
2504 struct drm_i915_private *dev_priv = to_i915(dev);
2505 enum pipe pipe = crtc->pipe;
2508 assert_pch_transcoder_disabled(dev_priv, pipe);
2510 if (IS_IVYBRIDGE(dev_priv))
2511 ivb_update_fdi_bc_bifurcation(crtc_state);
2513 /* Write the TU size bits before fdi link training, so that error
2514 * detection works. */
2515 intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
2516 intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2518 /* For PCH output, training FDI link */
2519 dev_priv->display.fdi_link_train(crtc, crtc_state);
2521 /* We need to program the right clock selection before writing the pixel
2522 * mutliplier into the DPLL. */
2523 if (HAS_PCH_CPT(dev_priv)) {
2526 temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
2527 temp |= TRANS_DPLL_ENABLE(pipe);
2528 sel = TRANS_DPLLB_SEL(pipe);
2529 if (crtc_state->shared_dpll ==
2530 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
2534 intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
2537 /* XXX: pch pll's can be enabled any time before we enable the PCH
2538 * transcoder, and we actually should do this to not upset any PCH
2539 * transcoder that already use the clock when we share it.
2541 * Note that enable_shared_dpll tries to do the right thing, but
2542 * get_shared_dpll unconditionally resets the pll - we need that to have
2543 * the right LVDS enable sequence. */
2544 intel_enable_shared_dpll(crtc_state);
2546 /* set transcoder timing, panel must allow it */
2547 assert_panel_unlocked(dev_priv, pipe);
2548 ilk_pch_transcoder_set_timings(crtc_state, pipe);
2550 intel_fdi_normal_train(crtc);
2552 /* For PCH DP, enable TRANS_DP_CTL */
2553 if (HAS_PCH_CPT(dev_priv) &&
2554 intel_crtc_has_dp_encoder(crtc_state)) {
2555 const struct drm_display_mode *adjusted_mode =
2556 &crtc_state->hw.adjusted_mode;
2557 u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
2558 i915_reg_t reg = TRANS_DP_CTL(pipe);
2561 temp = intel_de_read(dev_priv, reg);
2562 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2563 TRANS_DP_SYNC_MASK |
2565 temp |= TRANS_DP_OUTPUT_ENABLE;
2566 temp |= bpc << 9; /* same format but at 11:9 */
2568 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2569 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2570 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2571 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2573 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
2574 drm_WARN_ON(dev, port < PORT_B || port > PORT_D);
2575 temp |= TRANS_DP_PORT_SEL(port);
2577 intel_de_write(dev_priv, reg, temp);
2580 ilk_enable_pch_transcoder(crtc_state);
2583 void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
2585 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2586 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2587 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2589 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
2591 lpt_program_iclkip(crtc_state);
2593 /* Set transcoder timing. */
2594 ilk_pch_transcoder_set_timings(crtc_state, PIPE_A);
2596 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
2599 static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
2602 i915_reg_t dslreg = PIPEDSL(pipe);
2605 temp = intel_de_read(dev_priv, dslreg);
2607 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) {
2608 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5))
2609 drm_err(&dev_priv->drm,
2610 "mode set failed: pipe %c stuck\n",
2615 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
2617 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2618 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2619 const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
2620 enum pipe pipe = crtc->pipe;
2621 int width = drm_rect_width(dst);
2622 int height = drm_rect_height(dst);
2626 if (!crtc_state->pch_pfit.enabled)
2629 /* Force use of hard-coded filter coefficients
2630 * as some pre-programmed values are broken,
2633 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
2634 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
2635 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
2637 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
2639 intel_de_write(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
2640 intel_de_write(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
2643 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
2645 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2646 struct drm_device *dev = crtc->base.dev;
2647 struct drm_i915_private *dev_priv = to_i915(dev);
2649 if (!crtc_state->ips_enabled)
2653 * We can only enable IPS after we enable a plane and wait for a vblank
2654 * This function is called from post_plane_update, which is run after
2657 drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
2659 if (IS_BROADWELL(dev_priv)) {
2660 drm_WARN_ON(dev, sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
2661 IPS_ENABLE | IPS_PCODE_CONTROL));
2662 /* Quoting Art Runyan: "its not safe to expect any particular
2663 * value in IPS_CTL bit 31 after enabling IPS through the
2664 * mailbox." Moreover, the mailbox may return a bogus state,
2665 * so we need to just enable it and continue on.
2668 intel_de_write(dev_priv, IPS_CTL, IPS_ENABLE);
2669 /* The bit only becomes 1 in the next vblank, so this wait here
2670 * is essentially intel_wait_for_vblank. If we don't have this
2671 * and don't wait for vblanks until the end of crtc_enable, then
2672 * the HW state readout code will complain that the expected
2673 * IPS_CTL value is not the one we read. */
2674 if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50))
2675 drm_err(&dev_priv->drm,
2676 "Timed out waiting for IPS enable\n");
2680 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
2682 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2683 struct drm_device *dev = crtc->base.dev;
2684 struct drm_i915_private *dev_priv = to_i915(dev);
2686 if (!crtc_state->ips_enabled)
2689 if (IS_BROADWELL(dev_priv)) {
2691 sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
2693 * Wait for PCODE to finish disabling IPS. The BSpec specified
2694 * 42ms timeout value leads to occasional timeouts so use 100ms
2697 if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100))
2698 drm_err(&dev_priv->drm,
2699 "Timed out waiting for IPS disable\n");
2701 intel_de_write(dev_priv, IPS_CTL, 0);
2702 intel_de_posting_read(dev_priv, IPS_CTL);
2705 /* We need to wait for a vblank before we can disable the plane. */
2706 intel_wait_for_vblank(dev_priv, crtc->pipe);
2709 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
2711 if (intel_crtc->overlay)
2712 (void) intel_overlay_switch_off(intel_crtc->overlay);
2714 /* Let userspace switch the overlay on again. In most cases userspace
2715 * has to recompute where to put it anyway.
2719 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
2720 const struct intel_crtc_state *new_crtc_state)
2722 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
2723 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2725 if (!old_crtc_state->ips_enabled)
2728 if (intel_crtc_needs_modeset(new_crtc_state))
2732 * Workaround : Do not read or write the pipe palette/gamma data while
2733 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
2735 * Disable IPS before we program the LUT.
2737 if (IS_HASWELL(dev_priv) &&
2738 (new_crtc_state->uapi.color_mgmt_changed ||
2739 new_crtc_state->update_pipe) &&
2740 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
2743 return !new_crtc_state->ips_enabled;
2746 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
2747 const struct intel_crtc_state *new_crtc_state)
2749 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
2750 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2752 if (!new_crtc_state->ips_enabled)
2755 if (intel_crtc_needs_modeset(new_crtc_state))
2759 * Workaround : Do not read or write the pipe palette/gamma data while
2760 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
2762 * Re-enable IPS after the LUT has been programmed.
2764 if (IS_HASWELL(dev_priv) &&
2765 (new_crtc_state->uapi.color_mgmt_changed ||
2766 new_crtc_state->update_pipe) &&
2767 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
2771 * We can't read out IPS on broadwell, assume the worst and
2772 * forcibly enable IPS on the first fastset.
2774 if (new_crtc_state->update_pipe && old_crtc_state->inherited)
2777 return !old_crtc_state->ips_enabled;
2780 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
2782 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2784 if (!crtc_state->nv12_planes)
2787 /* WA Display #0827: Gen9:all */
2788 if (DISPLAY_VER(dev_priv) == 9)
2794 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
2796 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2798 /* Wa_2006604312:icl,ehl */
2799 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11)
2805 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
2806 const struct intel_crtc_state *new_crtc_state)
2808 return (!old_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)) &&
2809 new_crtc_state->active_planes;
2812 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
2813 const struct intel_crtc_state *new_crtc_state)
2815 return old_crtc_state->active_planes &&
2816 (!new_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state));
2819 static void intel_post_plane_update(struct intel_atomic_state *state,
2820 struct intel_crtc *crtc)
2822 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2823 const struct intel_crtc_state *old_crtc_state =
2824 intel_atomic_get_old_crtc_state(state, crtc);
2825 const struct intel_crtc_state *new_crtc_state =
2826 intel_atomic_get_new_crtc_state(state, crtc);
2827 enum pipe pipe = crtc->pipe;
2829 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
2831 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
2832 intel_update_watermarks(crtc);
2834 if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
2835 hsw_enable_ips(new_crtc_state);
2837 intel_fbc_post_update(state, crtc);
2839 if (needs_nv12_wa(old_crtc_state) &&
2840 !needs_nv12_wa(new_crtc_state))
2841 skl_wa_827(dev_priv, pipe, false);
2843 if (needs_scalerclk_wa(old_crtc_state) &&
2844 !needs_scalerclk_wa(new_crtc_state))
2845 icl_wa_scalerclkgating(dev_priv, pipe, false);
2848 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state,
2849 struct intel_crtc *crtc)
2851 const struct intel_crtc_state *crtc_state =
2852 intel_atomic_get_new_crtc_state(state, crtc);
2853 u8 update_planes = crtc_state->update_planes;
2854 const struct intel_plane_state *plane_state;
2855 struct intel_plane *plane;
2858 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
2859 if (plane->enable_flip_done &&
2860 plane->pipe == crtc->pipe &&
2861 update_planes & BIT(plane->id))
2862 plane->enable_flip_done(plane);
2866 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state,
2867 struct intel_crtc *crtc)
2869 const struct intel_crtc_state *crtc_state =
2870 intel_atomic_get_new_crtc_state(state, crtc);
2871 u8 update_planes = crtc_state->update_planes;
2872 const struct intel_plane_state *plane_state;
2873 struct intel_plane *plane;
2876 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
2877 if (plane->disable_flip_done &&
2878 plane->pipe == crtc->pipe &&
2879 update_planes & BIT(plane->id))
2880 plane->disable_flip_done(plane);
2884 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
2885 struct intel_crtc *crtc)
2887 struct drm_i915_private *i915 = to_i915(state->base.dev);
2888 const struct intel_crtc_state *old_crtc_state =
2889 intel_atomic_get_old_crtc_state(state, crtc);
2890 const struct intel_crtc_state *new_crtc_state =
2891 intel_atomic_get_new_crtc_state(state, crtc);
2892 u8 update_planes = new_crtc_state->update_planes;
2893 const struct intel_plane_state *old_plane_state;
2894 struct intel_plane *plane;
2895 bool need_vbl_wait = false;
2898 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
2899 if (plane->need_async_flip_disable_wa &&
2900 plane->pipe == crtc->pipe &&
2901 update_planes & BIT(plane->id)) {
2903 * Apart from the async flip bit we want to
2904 * preserve the old state for the plane.
2906 plane->async_flip(plane, old_crtc_state,
2907 old_plane_state, false);
2908 need_vbl_wait = true;
2913 intel_wait_for_vblank(i915, crtc->pipe);
2916 static void intel_pre_plane_update(struct intel_atomic_state *state,
2917 struct intel_crtc *crtc)
2919 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2920 const struct intel_crtc_state *old_crtc_state =
2921 intel_atomic_get_old_crtc_state(state, crtc);
2922 const struct intel_crtc_state *new_crtc_state =
2923 intel_atomic_get_new_crtc_state(state, crtc);
2924 enum pipe pipe = crtc->pipe;
2926 if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
2927 hsw_disable_ips(old_crtc_state);
2929 if (intel_fbc_pre_update(state, crtc))
2930 intel_wait_for_vblank(dev_priv, pipe);
2932 /* Display WA 827 */
2933 if (!needs_nv12_wa(old_crtc_state) &&
2934 needs_nv12_wa(new_crtc_state))
2935 skl_wa_827(dev_priv, pipe, true);
2937 /* Wa_2006604312:icl,ehl */
2938 if (!needs_scalerclk_wa(old_crtc_state) &&
2939 needs_scalerclk_wa(new_crtc_state))
2940 icl_wa_scalerclkgating(dev_priv, pipe, true);
2943 * Vblank time updates from the shadow to live plane control register
2944 * are blocked if the memory self-refresh mode is active at that
2945 * moment. So to make sure the plane gets truly disabled, disable
2946 * first the self-refresh mode. The self-refresh enable bit in turn
2947 * will be checked/applied by the HW only at the next frame start
2948 * event which is after the vblank start event, so we need to have a
2949 * wait-for-vblank between disabling the plane and the pipe.
2951 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
2952 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
2953 intel_wait_for_vblank(dev_priv, pipe);
2956 * IVB workaround: must disable low power watermarks for at least
2957 * one frame before enabling scaling. LP watermarks can be re-enabled
2958 * when scaling is disabled.
2960 * WaCxSRDisabledForSpriteScaling:ivb
2962 if (old_crtc_state->hw.active &&
2963 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
2964 intel_wait_for_vblank(dev_priv, pipe);
2967 * If we're doing a modeset we don't need to do any
2968 * pre-vblank watermark programming here.
2970 if (!intel_crtc_needs_modeset(new_crtc_state)) {
2972 * For platforms that support atomic watermarks, program the
2973 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
2974 * will be the intermediate values that are safe for both pre- and
2975 * post- vblank; when vblank happens, the 'active' values will be set
2976 * to the final 'target' values and we'll do this again to get the
2977 * optimal watermarks. For gen9+ platforms, the values we program here
2978 * will be the final target values which will get automatically latched
2979 * at vblank time; no further programming will be necessary.
2981 * If a platform hasn't been transitioned to atomic watermarks yet,
2982 * we'll continue to update watermarks the old way, if flags tell
2985 if (dev_priv->display.initial_watermarks)
2986 dev_priv->display.initial_watermarks(state, crtc);
2987 else if (new_crtc_state->update_wm_pre)
2988 intel_update_watermarks(crtc);
2992 * Gen2 reports pipe underruns whenever all planes are disabled.
2993 * So disable underrun reporting before all the planes get disabled.
2995 * We do this after .initial_watermarks() so that we have a
2996 * chance of catching underruns with the intermediate watermarks
2997 * vs. the old plane configuration.
2999 if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state))
3000 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
3003 * WA for platforms where async address update enable bit
3004 * is double buffered and only latched at start of vblank.
3006 if (old_crtc_state->uapi.async_flip && !new_crtc_state->uapi.async_flip)
3007 intel_crtc_async_flip_disable_wa(state, crtc);
3010 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
3011 struct intel_crtc *crtc)
3013 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3014 const struct intel_crtc_state *new_crtc_state =
3015 intel_atomic_get_new_crtc_state(state, crtc);
3016 unsigned int update_mask = new_crtc_state->update_planes;
3017 const struct intel_plane_state *old_plane_state;
3018 struct intel_plane *plane;
3019 unsigned fb_bits = 0;
3022 intel_crtc_dpms_overlay_disable(crtc);
3024 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
3025 if (crtc->pipe != plane->pipe ||
3026 !(update_mask & BIT(plane->id)))
3029 intel_disable_plane(plane, new_crtc_state);
3031 if (old_plane_state->uapi.visible)
3032 fb_bits |= plane->frontbuffer_bit;
3035 intel_frontbuffer_flip(dev_priv, fb_bits);
3039 * intel_connector_primary_encoder - get the primary encoder for a connector
3040 * @connector: connector for which to return the encoder
3042 * Returns the primary encoder for a connector. There is a 1:1 mapping from
3043 * all connectors to their encoder, except for DP-MST connectors which have
3044 * both a virtual and a primary encoder. These DP-MST primary encoders can be
3045 * pointed to by as many DP-MST connectors as there are pipes.
3047 static struct intel_encoder *
3048 intel_connector_primary_encoder(struct intel_connector *connector)
3050 struct intel_encoder *encoder;
3052 if (connector->mst_port)
3053 return &dp_to_dig_port(connector->mst_port)->base;
3055 encoder = intel_attached_encoder(connector);
3056 drm_WARN_ON(connector->base.dev, !encoder);
3061 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
3063 struct drm_connector_state *new_conn_state;
3064 struct drm_connector *connector;
3067 for_each_new_connector_in_state(&state->base, connector, new_conn_state,
3069 struct intel_connector *intel_connector;
3070 struct intel_encoder *encoder;
3071 struct intel_crtc *crtc;
3073 if (!intel_connector_needs_modeset(state, connector))
3076 intel_connector = to_intel_connector(connector);
3077 encoder = intel_connector_primary_encoder(intel_connector);
3078 if (!encoder->update_prepare)
3081 crtc = new_conn_state->crtc ?
3082 to_intel_crtc(new_conn_state->crtc) : NULL;
3083 encoder->update_prepare(state, encoder, crtc);
3087 static void intel_encoders_update_complete(struct intel_atomic_state *state)
3089 struct drm_connector_state *new_conn_state;
3090 struct drm_connector *connector;
3093 for_each_new_connector_in_state(&state->base, connector, new_conn_state,
3095 struct intel_connector *intel_connector;
3096 struct intel_encoder *encoder;
3097 struct intel_crtc *crtc;
3099 if (!intel_connector_needs_modeset(state, connector))
3102 intel_connector = to_intel_connector(connector);
3103 encoder = intel_connector_primary_encoder(intel_connector);
3104 if (!encoder->update_complete)
3107 crtc = new_conn_state->crtc ?
3108 to_intel_crtc(new_conn_state->crtc) : NULL;
3109 encoder->update_complete(state, encoder, crtc);
3113 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
3114 struct intel_crtc *crtc)
3116 const struct intel_crtc_state *crtc_state =
3117 intel_atomic_get_new_crtc_state(state, crtc);
3118 const struct drm_connector_state *conn_state;
3119 struct drm_connector *conn;
3122 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3123 struct intel_encoder *encoder =
3124 to_intel_encoder(conn_state->best_encoder);
3126 if (conn_state->crtc != &crtc->base)
3129 if (encoder->pre_pll_enable)
3130 encoder->pre_pll_enable(state, encoder,
3131 crtc_state, conn_state);
3135 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
3136 struct intel_crtc *crtc)
3138 const struct intel_crtc_state *crtc_state =
3139 intel_atomic_get_new_crtc_state(state, crtc);
3140 const struct drm_connector_state *conn_state;
3141 struct drm_connector *conn;
3144 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3145 struct intel_encoder *encoder =
3146 to_intel_encoder(conn_state->best_encoder);
3148 if (conn_state->crtc != &crtc->base)
3151 if (encoder->pre_enable)
3152 encoder->pre_enable(state, encoder,
3153 crtc_state, conn_state);
3157 static void intel_encoders_enable(struct intel_atomic_state *state,
3158 struct intel_crtc *crtc)
3160 const struct intel_crtc_state *crtc_state =
3161 intel_atomic_get_new_crtc_state(state, crtc);
3162 const struct drm_connector_state *conn_state;
3163 struct drm_connector *conn;
3166 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3167 struct intel_encoder *encoder =
3168 to_intel_encoder(conn_state->best_encoder);
3170 if (conn_state->crtc != &crtc->base)
3173 if (encoder->enable)
3174 encoder->enable(state, encoder,
3175 crtc_state, conn_state);
3176 intel_opregion_notify_encoder(encoder, true);
3180 static void intel_encoders_disable(struct intel_atomic_state *state,
3181 struct intel_crtc *crtc)
3183 const struct intel_crtc_state *old_crtc_state =
3184 intel_atomic_get_old_crtc_state(state, crtc);
3185 const struct drm_connector_state *old_conn_state;
3186 struct drm_connector *conn;
3189 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
3190 struct intel_encoder *encoder =
3191 to_intel_encoder(old_conn_state->best_encoder);
3193 if (old_conn_state->crtc != &crtc->base)
3196 intel_opregion_notify_encoder(encoder, false);
3197 if (encoder->disable)
3198 encoder->disable(state, encoder,
3199 old_crtc_state, old_conn_state);
3203 static void intel_encoders_post_disable(struct intel_atomic_state *state,
3204 struct intel_crtc *crtc)
3206 const struct intel_crtc_state *old_crtc_state =
3207 intel_atomic_get_old_crtc_state(state, crtc);
3208 const struct drm_connector_state *old_conn_state;
3209 struct drm_connector *conn;
3212 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
3213 struct intel_encoder *encoder =
3214 to_intel_encoder(old_conn_state->best_encoder);
3216 if (old_conn_state->crtc != &crtc->base)
3219 if (encoder->post_disable)
3220 encoder->post_disable(state, encoder,
3221 old_crtc_state, old_conn_state);
3225 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
3226 struct intel_crtc *crtc)
3228 const struct intel_crtc_state *old_crtc_state =
3229 intel_atomic_get_old_crtc_state(state, crtc);
3230 const struct drm_connector_state *old_conn_state;
3231 struct drm_connector *conn;
3234 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
3235 struct intel_encoder *encoder =
3236 to_intel_encoder(old_conn_state->best_encoder);
3238 if (old_conn_state->crtc != &crtc->base)
3241 if (encoder->post_pll_disable)
3242 encoder->post_pll_disable(state, encoder,
3243 old_crtc_state, old_conn_state);
3247 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
3248 struct intel_crtc *crtc)
3250 const struct intel_crtc_state *crtc_state =
3251 intel_atomic_get_new_crtc_state(state, crtc);
3252 const struct drm_connector_state *conn_state;
3253 struct drm_connector *conn;
3256 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3257 struct intel_encoder *encoder =
3258 to_intel_encoder(conn_state->best_encoder);
3260 if (conn_state->crtc != &crtc->base)
3263 if (encoder->update_pipe)
3264 encoder->update_pipe(state, encoder,
3265 crtc_state, conn_state);
3269 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
3271 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3272 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
3274 plane->disable_plane(plane, crtc_state);
3277 static void ilk_crtc_enable(struct intel_atomic_state *state,
3278 struct intel_crtc *crtc)
3280 const struct intel_crtc_state *new_crtc_state =
3281 intel_atomic_get_new_crtc_state(state, crtc);
3282 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3283 enum pipe pipe = crtc->pipe;
3285 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
3289 * Sometimes spurious CPU pipe underruns happen during FDI
3290 * training, at least with VGA+HDMI cloning. Suppress them.
3292 * On ILK we get an occasional spurious CPU pipe underruns
3293 * between eDP port A enable and vdd enable. Also PCH port
3294 * enable seems to result in the occasional CPU pipe underrun.
3296 * Spurious PCH underruns also occur during PCH enabling.
3298 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
3299 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
3301 if (new_crtc_state->has_pch_encoder)
3302 intel_prepare_shared_dpll(new_crtc_state);
3304 if (intel_crtc_has_dp_encoder(new_crtc_state))
3305 intel_dp_set_m_n(new_crtc_state, M1_N1);
3307 intel_set_transcoder_timings(new_crtc_state);
3308 intel_set_pipe_src_size(new_crtc_state);
3310 if (new_crtc_state->has_pch_encoder)
3311 intel_cpu_transcoder_set_m_n(new_crtc_state,
3312 &new_crtc_state->fdi_m_n, NULL);
3314 ilk_set_pipeconf(new_crtc_state);
3316 crtc->active = true;
3318 intel_encoders_pre_enable(state, crtc);
3320 if (new_crtc_state->has_pch_encoder) {
3321 /* Note: FDI PLL enabling _must_ be done before we enable the
3322 * cpu pipes, hence this is separate from all the other fdi/pch
3324 ilk_fdi_pll_enable(new_crtc_state);
3326 assert_fdi_tx_disabled(dev_priv, pipe);
3327 assert_fdi_rx_disabled(dev_priv, pipe);
3330 ilk_pfit_enable(new_crtc_state);
3333 * On ILK+ LUT must be loaded before the pipe is running but with
3336 intel_color_load_luts(new_crtc_state);
3337 intel_color_commit(new_crtc_state);
3338 /* update DSPCNTR to configure gamma for pipe bottom color */
3339 intel_disable_primary_plane(new_crtc_state);
3341 if (dev_priv->display.initial_watermarks)
3342 dev_priv->display.initial_watermarks(state, crtc);
3343 intel_enable_pipe(new_crtc_state);
3345 if (new_crtc_state->has_pch_encoder)
3346 ilk_pch_enable(state, new_crtc_state);
3348 intel_crtc_vblank_on(new_crtc_state);
3350 intel_encoders_enable(state, crtc);
3352 if (HAS_PCH_CPT(dev_priv))
3353 cpt_verify_modeset(dev_priv, pipe);
3356 * Must wait for vblank to avoid spurious PCH FIFO underruns.
3357 * And a second vblank wait is needed at least on ILK with
3358 * some interlaced HDMI modes. Let's do the double wait always
3359 * in case there are more corner cases we don't know about.
3361 if (new_crtc_state->has_pch_encoder) {
3362 intel_wait_for_vblank(dev_priv, pipe);
3363 intel_wait_for_vblank(dev_priv, pipe);
3365 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3366 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
3369 /* IPS only exists on ULT machines and is tied to pipe A. */
3370 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3372 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
3375 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
3376 enum pipe pipe, bool apply)
3378 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe));
3379 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
3386 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
3389 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
3391 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3392 enum pipe pipe = crtc->pipe;
3395 val = MBUS_DBOX_A_CREDIT(2);
3397 if (DISPLAY_VER(dev_priv) >= 12) {
3398 val |= MBUS_DBOX_BW_CREDIT(2);
3399 val |= MBUS_DBOX_B_CREDIT(12);
3401 val |= MBUS_DBOX_BW_CREDIT(1);
3402 val |= MBUS_DBOX_B_CREDIT(8);
3405 intel_de_write(dev_priv, PIPE_MBUS_DBOX_CTL(pipe), val);
3408 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
3410 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3411 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3413 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),
3414 HSW_LINETIME(crtc_state->linetime) |
3415 HSW_IPS_LINETIME(crtc_state->ips_linetime));
3418 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
3420 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3421 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3422 i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
3425 val = intel_de_read(dev_priv, reg);
3426 val &= ~HSW_FRAME_START_DELAY_MASK;
3427 val |= HSW_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
3428 intel_de_write(dev_priv, reg, val);
3431 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
3432 const struct intel_crtc_state *crtc_state)
3434 struct intel_crtc *master = to_intel_crtc(crtc_state->uapi.crtc);
3435 struct drm_i915_private *dev_priv = to_i915(master->base.dev);
3436 struct intel_crtc_state *master_crtc_state;
3437 struct drm_connector_state *conn_state;
3438 struct drm_connector *conn;
3439 struct intel_encoder *encoder = NULL;
3442 if (crtc_state->bigjoiner_slave)
3443 master = crtc_state->bigjoiner_linked_crtc;
3445 master_crtc_state = intel_atomic_get_new_crtc_state(state, master);
3447 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3448 if (conn_state->crtc != &master->base)
3451 encoder = to_intel_encoder(conn_state->best_encoder);
3455 if (!crtc_state->bigjoiner_slave) {
3456 /* need to enable VDSC, which we skipped in pre-enable */
3457 intel_dsc_enable(encoder, crtc_state);
3460 * Enable sequence steps 1-7 on bigjoiner master
3462 intel_encoders_pre_pll_enable(state, master);
3463 intel_enable_shared_dpll(master_crtc_state);
3464 intel_encoders_pre_enable(state, master);
3466 /* and DSC on slave */
3467 intel_dsc_enable(NULL, crtc_state);
3470 if (DISPLAY_VER(dev_priv) >= 13)
3471 intel_uncompressed_joiner_enable(crtc_state);
3474 static void hsw_crtc_enable(struct intel_atomic_state *state,
3475 struct intel_crtc *crtc)
3477 const struct intel_crtc_state *new_crtc_state =
3478 intel_atomic_get_new_crtc_state(state, crtc);
3479 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3480 enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
3481 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
3482 bool psl_clkgate_wa;
3484 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
3487 if (!new_crtc_state->bigjoiner) {
3488 intel_encoders_pre_pll_enable(state, crtc);
3490 if (new_crtc_state->shared_dpll)
3491 intel_enable_shared_dpll(new_crtc_state);
3493 intel_encoders_pre_enable(state, crtc);
3495 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
3498 intel_set_pipe_src_size(new_crtc_state);
3499 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
3500 bdw_set_pipemisc(new_crtc_state);
3502 if (!new_crtc_state->bigjoiner_slave && !transcoder_is_dsi(cpu_transcoder)) {
3503 intel_set_transcoder_timings(new_crtc_state);
3505 if (cpu_transcoder != TRANSCODER_EDP)
3506 intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
3507 new_crtc_state->pixel_multiplier - 1);
3509 if (new_crtc_state->has_pch_encoder)
3510 intel_cpu_transcoder_set_m_n(new_crtc_state,
3511 &new_crtc_state->fdi_m_n, NULL);
3513 hsw_set_frame_start_delay(new_crtc_state);
3516 if (!transcoder_is_dsi(cpu_transcoder))
3517 hsw_set_pipeconf(new_crtc_state);
3519 crtc->active = true;
3521 /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
3522 psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 &&
3523 new_crtc_state->pch_pfit.enabled;
3525 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
3527 if (DISPLAY_VER(dev_priv) >= 9)
3528 skl_pfit_enable(new_crtc_state);
3530 ilk_pfit_enable(new_crtc_state);
3533 * On ILK+ LUT must be loaded before the pipe is running but with
3536 intel_color_load_luts(new_crtc_state);
3537 intel_color_commit(new_crtc_state);
3538 /* update DSPCNTR to configure gamma/csc for pipe bottom color */
3539 if (DISPLAY_VER(dev_priv) < 9)
3540 intel_disable_primary_plane(new_crtc_state);
3542 hsw_set_linetime_wm(new_crtc_state);
3544 if (DISPLAY_VER(dev_priv) >= 11)
3545 icl_set_pipe_chicken(crtc);
3547 if (dev_priv->display.initial_watermarks)
3548 dev_priv->display.initial_watermarks(state, crtc);
3550 if (DISPLAY_VER(dev_priv) >= 11)
3551 icl_pipe_mbus_enable(crtc);
3553 if (new_crtc_state->bigjoiner_slave)
3554 intel_crtc_vblank_on(new_crtc_state);
3556 intel_encoders_enable(state, crtc);
3558 if (psl_clkgate_wa) {
3559 intel_wait_for_vblank(dev_priv, pipe);
3560 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
3563 /* If we change the relative order between pipe/planes enabling, we need
3564 * to change the workaround. */
3565 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
3566 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
3567 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
3568 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
3572 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
3574 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
3575 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3576 enum pipe pipe = crtc->pipe;
3578 /* To avoid upsetting the power well on haswell only disable the pfit if
3579 * it's in use. The hw state code will make sure we get this right. */
3580 if (!old_crtc_state->pch_pfit.enabled)
3583 intel_de_write(dev_priv, PF_CTL(pipe), 0);
3584 intel_de_write(dev_priv, PF_WIN_POS(pipe), 0);
3585 intel_de_write(dev_priv, PF_WIN_SZ(pipe), 0);
3588 static void ilk_crtc_disable(struct intel_atomic_state *state,
3589 struct intel_crtc *crtc)
3591 const struct intel_crtc_state *old_crtc_state =
3592 intel_atomic_get_old_crtc_state(state, crtc);
3593 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3594 enum pipe pipe = crtc->pipe;
3597 * Sometimes spurious CPU pipe underruns happen when the
3598 * pipe is already disabled, but FDI RX/TX is still enabled.
3599 * Happens at least with VGA+HDMI cloning. Suppress them.
3601 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
3602 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
3604 intel_encoders_disable(state, crtc);
3606 intel_crtc_vblank_off(old_crtc_state);
3608 intel_disable_pipe(old_crtc_state);
3610 ilk_pfit_disable(old_crtc_state);
3612 if (old_crtc_state->has_pch_encoder)
3613 ilk_fdi_disable(crtc);
3615 intel_encoders_post_disable(state, crtc);
3617 if (old_crtc_state->has_pch_encoder) {
3618 ilk_disable_pch_transcoder(dev_priv, pipe);
3620 if (HAS_PCH_CPT(dev_priv)) {
3624 /* disable TRANS_DP_CTL */
3625 reg = TRANS_DP_CTL(pipe);
3626 temp = intel_de_read(dev_priv, reg);
3627 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3628 TRANS_DP_PORT_SEL_MASK);
3629 temp |= TRANS_DP_PORT_SEL_NONE;
3630 intel_de_write(dev_priv, reg, temp);
3632 /* disable DPLL_SEL */
3633 temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
3634 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3635 intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
3638 ilk_fdi_pll_disable(crtc);
3641 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3642 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
3645 static void hsw_crtc_disable(struct intel_atomic_state *state,
3646 struct intel_crtc *crtc)
3649 * FIXME collapse everything to one hook.
3650 * Need care with mst->ddi interactions.
3652 intel_encoders_disable(state, crtc);
3653 intel_encoders_post_disable(state, crtc);
3656 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
3658 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3659 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3661 if (!crtc_state->gmch_pfit.control)
3665 * The panel fitter should only be adjusted whilst the pipe is disabled,
3666 * according to register description and PRM.
3668 drm_WARN_ON(&dev_priv->drm,
3669 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
3670 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
3672 intel_de_write(dev_priv, PFIT_PGM_RATIOS,
3673 crtc_state->gmch_pfit.pgm_ratios);
3674 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
3676 /* Border color in case we don't scale up to the full screen. Black by
3677 * default, change to something else for debugging. */
3678 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
3681 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
3683 if (phy == PHY_NONE)
3685 else if (IS_ALDERLAKE_S(dev_priv))
3686 return phy <= PHY_E;
3687 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
3688 return phy <= PHY_D;
3689 else if (IS_JSL_EHL(dev_priv))
3690 return phy <= PHY_C;
3691 else if (DISPLAY_VER(dev_priv) >= 11)
3692 return phy <= PHY_B;
3697 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
3699 if (IS_ALDERLAKE_P(dev_priv))
3700 return phy >= PHY_F && phy <= PHY_I;
3701 else if (IS_TIGERLAKE(dev_priv))
3702 return phy >= PHY_D && phy <= PHY_I;
3703 else if (IS_ICELAKE(dev_priv))
3704 return phy >= PHY_C && phy <= PHY_F;
3709 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
3711 if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD)
3712 return PHY_D + port - PORT_D_XELPD;
3713 else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1)
3714 return PHY_F + port - PORT_TC1;
3715 else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
3716 return PHY_B + port - PORT_TC1;
3717 else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
3718 return PHY_C + port - PORT_TC1;
3719 else if (IS_JSL_EHL(i915) && port == PORT_D)
3722 return PHY_A + port - PORT_A;
3725 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
3727 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
3728 return TC_PORT_NONE;
3730 if (DISPLAY_VER(dev_priv) >= 12)
3731 return TC_PORT_1 + port - PORT_TC1;
3733 return TC_PORT_1 + port - PORT_C;
3736 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
3740 return POWER_DOMAIN_PORT_DDI_A_LANES;
3742 return POWER_DOMAIN_PORT_DDI_B_LANES;
3744 return POWER_DOMAIN_PORT_DDI_C_LANES;
3746 return POWER_DOMAIN_PORT_DDI_D_LANES;
3748 return POWER_DOMAIN_PORT_DDI_E_LANES;
3750 return POWER_DOMAIN_PORT_DDI_F_LANES;
3752 return POWER_DOMAIN_PORT_DDI_G_LANES;
3754 return POWER_DOMAIN_PORT_DDI_H_LANES;
3756 return POWER_DOMAIN_PORT_DDI_I_LANES;
3759 return POWER_DOMAIN_PORT_OTHER;
3763 enum intel_display_power_domain
3764 intel_aux_power_domain(struct intel_digital_port *dig_port)
3766 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3767 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
3769 if (intel_phy_is_tc(dev_priv, phy) &&
3770 dig_port->tc_mode == TC_PORT_TBT_ALT) {
3771 switch (dig_port->aux_ch) {
3773 return POWER_DOMAIN_AUX_C_TBT;
3775 return POWER_DOMAIN_AUX_D_TBT;
3777 return POWER_DOMAIN_AUX_E_TBT;
3779 return POWER_DOMAIN_AUX_F_TBT;
3781 return POWER_DOMAIN_AUX_G_TBT;
3783 return POWER_DOMAIN_AUX_H_TBT;
3785 return POWER_DOMAIN_AUX_I_TBT;
3787 MISSING_CASE(dig_port->aux_ch);
3788 return POWER_DOMAIN_AUX_C_TBT;
3792 return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
3796 * Converts aux_ch to power_domain without caring about TBT ports for that use
3797 * intel_aux_power_domain()
3799 enum intel_display_power_domain
3800 intel_legacy_aux_to_power_domain(enum aux_ch aux_ch)
3804 return POWER_DOMAIN_AUX_A;
3806 return POWER_DOMAIN_AUX_B;
3808 return POWER_DOMAIN_AUX_C;
3810 return POWER_DOMAIN_AUX_D;
3812 return POWER_DOMAIN_AUX_E;
3814 return POWER_DOMAIN_AUX_F;
3816 return POWER_DOMAIN_AUX_G;
3818 return POWER_DOMAIN_AUX_H;
3820 return POWER_DOMAIN_AUX_I;
3822 MISSING_CASE(aux_ch);
3823 return POWER_DOMAIN_AUX_A;
3827 static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
3829 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3830 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3831 struct drm_encoder *encoder;
3832 enum pipe pipe = crtc->pipe;
3834 enum transcoder transcoder = crtc_state->cpu_transcoder;
3836 if (!crtc_state->hw.active)
3839 mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
3840 mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
3841 if (crtc_state->pch_pfit.enabled ||
3842 crtc_state->pch_pfit.force_thru)
3843 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
3845 drm_for_each_encoder_mask(encoder, &dev_priv->drm,
3846 crtc_state->uapi.encoder_mask) {
3847 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3849 mask |= BIT_ULL(intel_encoder->power_domain);
3852 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
3853 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
3855 if (crtc_state->shared_dpll)
3856 mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
3858 if (crtc_state->dsc.compression_enable)
3859 mask |= BIT_ULL(intel_dsc_power_domain(crtc_state));
3865 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
3867 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3868 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3869 enum intel_display_power_domain domain;
3870 u64 domains, new_domains, old_domains;
3872 domains = get_crtc_power_domains(crtc_state);
3874 new_domains = domains & ~crtc->enabled_power_domains.mask;
3875 old_domains = crtc->enabled_power_domains.mask & ~domains;
3877 for_each_power_domain(domain, new_domains)
3878 intel_display_power_get_in_set(dev_priv,
3879 &crtc->enabled_power_domains,
3885 static void modeset_put_crtc_power_domains(struct intel_crtc *crtc,
3888 intel_display_power_put_mask_in_set(to_i915(crtc->base.dev),
3889 &crtc->enabled_power_domains,
3893 static void valleyview_crtc_enable(struct intel_atomic_state *state,
3894 struct intel_crtc *crtc)
3896 const struct intel_crtc_state *new_crtc_state =
3897 intel_atomic_get_new_crtc_state(state, crtc);
3898 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3899 enum pipe pipe = crtc->pipe;
3901 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
3904 if (intel_crtc_has_dp_encoder(new_crtc_state))
3905 intel_dp_set_m_n(new_crtc_state, M1_N1);
3907 intel_set_transcoder_timings(new_crtc_state);
3908 intel_set_pipe_src_size(new_crtc_state);
3910 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
3911 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
3912 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
3915 i9xx_set_pipeconf(new_crtc_state);
3917 crtc->active = true;
3919 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3921 intel_encoders_pre_pll_enable(state, crtc);
3923 if (IS_CHERRYVIEW(dev_priv)) {
3924 chv_prepare_pll(crtc, new_crtc_state);
3925 chv_enable_pll(crtc, new_crtc_state);
3927 vlv_prepare_pll(crtc, new_crtc_state);
3928 vlv_enable_pll(crtc, new_crtc_state);
3931 intel_encoders_pre_enable(state, crtc);
3933 i9xx_pfit_enable(new_crtc_state);
3935 intel_color_load_luts(new_crtc_state);
3936 intel_color_commit(new_crtc_state);
3937 /* update DSPCNTR to configure gamma for pipe bottom color */
3938 intel_disable_primary_plane(new_crtc_state);
3940 dev_priv->display.initial_watermarks(state, crtc);
3941 intel_enable_pipe(new_crtc_state);
3943 intel_crtc_vblank_on(new_crtc_state);
3945 intel_encoders_enable(state, crtc);
3948 static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
3950 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3951 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3953 intel_de_write(dev_priv, FP0(crtc->pipe),
3954 crtc_state->dpll_hw_state.fp0);
3955 intel_de_write(dev_priv, FP1(crtc->pipe),
3956 crtc_state->dpll_hw_state.fp1);
3959 static void i9xx_crtc_enable(struct intel_atomic_state *state,
3960 struct intel_crtc *crtc)
3962 const struct intel_crtc_state *new_crtc_state =
3963 intel_atomic_get_new_crtc_state(state, crtc);
3964 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3965 enum pipe pipe = crtc->pipe;
3967 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
3970 i9xx_set_pll_dividers(new_crtc_state);
3972 if (intel_crtc_has_dp_encoder(new_crtc_state))
3973 intel_dp_set_m_n(new_crtc_state, M1_N1);
3975 intel_set_transcoder_timings(new_crtc_state);
3976 intel_set_pipe_src_size(new_crtc_state);
3978 i9xx_set_pipeconf(new_crtc_state);
3980 crtc->active = true;
3982 if (DISPLAY_VER(dev_priv) != 2)
3983 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3985 intel_encoders_pre_enable(state, crtc);
3987 i9xx_enable_pll(crtc, new_crtc_state);
3989 i9xx_pfit_enable(new_crtc_state);
3991 intel_color_load_luts(new_crtc_state);
3992 intel_color_commit(new_crtc_state);
3993 /* update DSPCNTR to configure gamma for pipe bottom color */
3994 intel_disable_primary_plane(new_crtc_state);
3996 if (dev_priv->display.initial_watermarks)
3997 dev_priv->display.initial_watermarks(state, crtc);
3999 intel_update_watermarks(crtc);
4000 intel_enable_pipe(new_crtc_state);
4002 intel_crtc_vblank_on(new_crtc_state);
4004 intel_encoders_enable(state, crtc);
4006 /* prevents spurious underruns */
4007 if (DISPLAY_VER(dev_priv) == 2)
4008 intel_wait_for_vblank(dev_priv, pipe);
4011 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
4013 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
4014 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4016 if (!old_crtc_state->gmch_pfit.control)
4019 assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
4021 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
4022 intel_de_read(dev_priv, PFIT_CONTROL));
4023 intel_de_write(dev_priv, PFIT_CONTROL, 0);
4026 static void i9xx_crtc_disable(struct intel_atomic_state *state,
4027 struct intel_crtc *crtc)
4029 struct intel_crtc_state *old_crtc_state =
4030 intel_atomic_get_old_crtc_state(state, crtc);
4031 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4032 enum pipe pipe = crtc->pipe;
4035 * On gen2 planes are double buffered but the pipe isn't, so we must
4036 * wait for planes to fully turn off before disabling the pipe.
4038 if (DISPLAY_VER(dev_priv) == 2)
4039 intel_wait_for_vblank(dev_priv, pipe);
4041 intel_encoders_disable(state, crtc);
4043 intel_crtc_vblank_off(old_crtc_state);
4045 intel_disable_pipe(old_crtc_state);
4047 i9xx_pfit_disable(old_crtc_state);
4049 intel_encoders_post_disable(state, crtc);
4051 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
4052 if (IS_CHERRYVIEW(dev_priv))
4053 chv_disable_pll(dev_priv, pipe);
4054 else if (IS_VALLEYVIEW(dev_priv))
4055 vlv_disable_pll(dev_priv, pipe);
4057 i9xx_disable_pll(old_crtc_state);
4060 intel_encoders_post_pll_disable(state, crtc);
4062 if (DISPLAY_VER(dev_priv) != 2)
4063 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4065 if (!dev_priv->display.initial_watermarks)
4066 intel_update_watermarks(crtc);
4068 /* clock the pipe down to 640x480@60 to potentially save power */
4069 if (IS_I830(dev_priv))
4070 i830_enable_pipe(dev_priv, pipe);
4073 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
4074 struct drm_modeset_acquire_ctx *ctx)
4076 struct intel_encoder *encoder;
4077 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4078 struct intel_bw_state *bw_state =
4079 to_intel_bw_state(dev_priv->bw_obj.state);
4080 struct intel_cdclk_state *cdclk_state =
4081 to_intel_cdclk_state(dev_priv->cdclk.obj.state);
4082 struct intel_dbuf_state *dbuf_state =
4083 to_intel_dbuf_state(dev_priv->dbuf.obj.state);
4084 struct intel_crtc_state *crtc_state =
4085 to_intel_crtc_state(crtc->base.state);
4086 struct intel_plane *plane;
4087 struct drm_atomic_state *state;
4088 struct intel_crtc_state *temp_crtc_state;
4089 enum pipe pipe = crtc->pipe;
4092 if (!crtc_state->hw.active)
4095 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
4096 const struct intel_plane_state *plane_state =
4097 to_intel_plane_state(plane->base.state);
4099 if (plane_state->uapi.visible)
4100 intel_plane_disable_noatomic(crtc, plane);
4103 state = drm_atomic_state_alloc(&dev_priv->drm);
4105 drm_dbg_kms(&dev_priv->drm,
4106 "failed to disable [CRTC:%d:%s], out of memory",
4107 crtc->base.base.id, crtc->base.name);
4111 state->acquire_ctx = ctx;
4113 /* Everything's already locked, -EDEADLK can't happen. */
4114 temp_crtc_state = intel_atomic_get_crtc_state(state, crtc);
4115 ret = drm_atomic_add_affected_connectors(state, &crtc->base);
4117 drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret);
4119 dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc);
4121 drm_atomic_state_put(state);
4123 drm_dbg_kms(&dev_priv->drm,
4124 "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
4125 crtc->base.base.id, crtc->base.name);
4127 crtc->active = false;
4128 crtc->base.enabled = false;
4130 drm_WARN_ON(&dev_priv->drm,
4131 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0);
4132 crtc_state->uapi.active = false;
4133 crtc_state->uapi.connector_mask = 0;
4134 crtc_state->uapi.encoder_mask = 0;
4135 intel_crtc_free_hw_state(crtc_state);
4136 memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));
4138 for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder)
4139 encoder->base.crtc = NULL;
4141 intel_fbc_disable(crtc);
4142 intel_update_watermarks(crtc);
4143 intel_disable_shared_dpll(crtc_state);
4145 intel_display_power_put_all_in_set(dev_priv, &crtc->enabled_power_domains);
4147 dev_priv->active_pipes &= ~BIT(pipe);
4148 cdclk_state->min_cdclk[pipe] = 0;
4149 cdclk_state->min_voltage_level[pipe] = 0;
4150 cdclk_state->active_pipes &= ~BIT(pipe);
4152 dbuf_state->active_pipes &= ~BIT(pipe);
4154 bw_state->data_rate[pipe] = 0;
4155 bw_state->num_active_planes[pipe] = 0;
4159 * turn all crtc's off, but do not adjust state
4160 * This has to be paired with a call to intel_modeset_setup_hw_state.
4162 int intel_display_suspend(struct drm_device *dev)
4164 struct drm_i915_private *dev_priv = to_i915(dev);
4165 struct drm_atomic_state *state;
4168 if (!HAS_DISPLAY(dev_priv))
4171 state = drm_atomic_helper_suspend(dev);
4172 ret = PTR_ERR_OR_ZERO(state);
4174 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
4177 dev_priv->modeset_restore_state = state;
4181 void intel_encoder_destroy(struct drm_encoder *encoder)
4183 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4185 drm_encoder_cleanup(encoder);
4186 kfree(intel_encoder);
4189 /* Cross check the actual hw state with our own modeset state tracking (and it's
4190 * internal consistency). */
4191 static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
4192 struct drm_connector_state *conn_state)
4194 struct intel_connector *connector = to_intel_connector(conn_state->connector);
4195 struct drm_i915_private *i915 = to_i915(connector->base.dev);
4197 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
4198 connector->base.base.id, connector->base.name);
4200 if (connector->get_hw_state(connector)) {
4201 struct intel_encoder *encoder = intel_attached_encoder(connector);
4203 I915_STATE_WARN(!crtc_state,
4204 "connector enabled without attached crtc\n");
4209 I915_STATE_WARN(!crtc_state->hw.active,
4210 "connector is active, but attached crtc isn't\n");
4212 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
4215 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
4216 "atomic encoder doesn't match attached encoder\n");
4218 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
4219 "attached encoder crtc differs from connector crtc\n");
4221 I915_STATE_WARN(crtc_state && crtc_state->hw.active,
4222 "attached crtc is active, but connector isn't\n");
4223 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
4224 "best encoder set without crtc!\n");
4228 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
4230 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4231 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4233 /* IPS only exists on ULT machines and is tied to pipe A. */
4234 if (!hsw_crtc_supports_ips(crtc))
4237 if (!dev_priv->params.enable_ips)
4240 if (crtc_state->pipe_bpp > 24)
4244 * We compare against max which means we must take
4245 * the increased cdclk requirement into account when
4246 * calculating the new cdclk.
4248 * Should measure whether using a lower cdclk w/o IPS
4250 if (IS_BROADWELL(dev_priv) &&
4251 crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
4257 static int hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
4259 struct drm_i915_private *dev_priv =
4260 to_i915(crtc_state->uapi.crtc->dev);
4261 struct intel_atomic_state *state =
4262 to_intel_atomic_state(crtc_state->uapi.state);
4264 crtc_state->ips_enabled = false;
4266 if (!hsw_crtc_state_ips_capable(crtc_state))
4270 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4271 * enabled and disabled dynamically based on package C states,
4272 * user space can't make reliable use of the CRCs, so let's just
4273 * completely disable it.
4275 if (crtc_state->crc_enabled)
4278 /* IPS should be fine as long as at least one plane is enabled. */
4279 if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
4282 if (IS_BROADWELL(dev_priv)) {
4283 const struct intel_cdclk_state *cdclk_state;
4285 cdclk_state = intel_atomic_get_cdclk_state(state);
4286 if (IS_ERR(cdclk_state))
4287 return PTR_ERR(cdclk_state);
4289 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
4290 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
4294 crtc_state->ips_enabled = true;
4299 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
4301 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4303 /* GDG double wide on either pipe, otherwise pipe A only */
4304 return DISPLAY_VER(dev_priv) < 4 &&
4305 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
4308 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
4310 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
4311 struct drm_rect src;
4314 * We only use IF-ID interlacing. If we ever use
4315 * PF-ID we'll need to adjust the pixel_rate here.
4318 if (!crtc_state->pch_pfit.enabled)
4321 drm_rect_init(&src, 0, 0,
4322 crtc_state->pipe_src_w << 16,
4323 crtc_state->pipe_src_h << 16);
4325 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst,
4329 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode,
4330 const struct drm_display_mode *timings)
4332 mode->hdisplay = timings->crtc_hdisplay;
4333 mode->htotal = timings->crtc_htotal;
4334 mode->hsync_start = timings->crtc_hsync_start;
4335 mode->hsync_end = timings->crtc_hsync_end;
4337 mode->vdisplay = timings->crtc_vdisplay;
4338 mode->vtotal = timings->crtc_vtotal;
4339 mode->vsync_start = timings->crtc_vsync_start;
4340 mode->vsync_end = timings->crtc_vsync_end;
4342 mode->flags = timings->flags;
4343 mode->type = DRM_MODE_TYPE_DRIVER;
4345 mode->clock = timings->crtc_clock;
4347 drm_mode_set_name(mode);
4350 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
4352 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4354 if (HAS_GMCH(dev_priv))
4355 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
4356 crtc_state->pixel_rate =
4357 crtc_state->hw.pipe_mode.crtc_clock;
4359 crtc_state->pixel_rate =
4360 ilk_pipe_pixel_rate(crtc_state);
4363 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state)
4365 struct drm_display_mode *mode = &crtc_state->hw.mode;
4366 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
4367 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
4369 drm_mode_copy(pipe_mode, adjusted_mode);
4371 if (crtc_state->bigjoiner) {
4373 * transcoder is programmed to the full mode,
4374 * but pipe timings are half of the transcoder mode
4376 pipe_mode->crtc_hdisplay /= 2;
4377 pipe_mode->crtc_hblank_start /= 2;
4378 pipe_mode->crtc_hblank_end /= 2;
4379 pipe_mode->crtc_hsync_start /= 2;
4380 pipe_mode->crtc_hsync_end /= 2;
4381 pipe_mode->crtc_htotal /= 2;
4382 pipe_mode->crtc_clock /= 2;
4385 if (crtc_state->splitter.enable) {
4386 int n = crtc_state->splitter.link_count;
4387 int overlap = crtc_state->splitter.pixel_overlap;
4390 * eDP MSO uses segment timings from EDID for transcoder
4391 * timings, but full mode for everything else.
4393 * h_full = (h_segment - pixel_overlap) * link_count
4395 pipe_mode->crtc_hdisplay = (pipe_mode->crtc_hdisplay - overlap) * n;
4396 pipe_mode->crtc_hblank_start = (pipe_mode->crtc_hblank_start - overlap) * n;
4397 pipe_mode->crtc_hblank_end = (pipe_mode->crtc_hblank_end - overlap) * n;
4398 pipe_mode->crtc_hsync_start = (pipe_mode->crtc_hsync_start - overlap) * n;
4399 pipe_mode->crtc_hsync_end = (pipe_mode->crtc_hsync_end - overlap) * n;
4400 pipe_mode->crtc_htotal = (pipe_mode->crtc_htotal - overlap) * n;
4401 pipe_mode->crtc_clock *= n;
4403 intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
4404 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode);
4406 intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
4407 intel_mode_from_crtc_timings(adjusted_mode, adjusted_mode);
4410 intel_crtc_compute_pixel_rate(crtc_state);
4412 drm_mode_copy(mode, adjusted_mode);
4413 mode->hdisplay = crtc_state->pipe_src_w << crtc_state->bigjoiner;
4414 mode->vdisplay = crtc_state->pipe_src_h;
4417 static void intel_encoder_get_config(struct intel_encoder *encoder,
4418 struct intel_crtc_state *crtc_state)
4420 encoder->get_config(encoder, crtc_state);
4422 intel_crtc_readout_derived_state(crtc_state);
4425 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4426 struct intel_crtc_state *pipe_config)
4428 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4429 struct drm_display_mode *pipe_mode = &pipe_config->hw.pipe_mode;
4430 int clock_limit = dev_priv->max_dotclk_freq;
4432 drm_mode_copy(pipe_mode, &pipe_config->hw.adjusted_mode);
4434 /* Adjust pipe_mode for bigjoiner, with half the horizontal mode */
4435 if (pipe_config->bigjoiner) {
4436 pipe_mode->crtc_clock /= 2;
4437 pipe_mode->crtc_hdisplay /= 2;
4438 pipe_mode->crtc_hblank_start /= 2;
4439 pipe_mode->crtc_hblank_end /= 2;
4440 pipe_mode->crtc_hsync_start /= 2;
4441 pipe_mode->crtc_hsync_end /= 2;
4442 pipe_mode->crtc_htotal /= 2;
4443 pipe_config->pipe_src_w /= 2;
4446 if (pipe_config->splitter.enable) {
4447 int n = pipe_config->splitter.link_count;
4448 int overlap = pipe_config->splitter.pixel_overlap;
4450 pipe_mode->crtc_hdisplay = (pipe_mode->crtc_hdisplay - overlap) * n;
4451 pipe_mode->crtc_hblank_start = (pipe_mode->crtc_hblank_start - overlap) * n;
4452 pipe_mode->crtc_hblank_end = (pipe_mode->crtc_hblank_end - overlap) * n;
4453 pipe_mode->crtc_hsync_start = (pipe_mode->crtc_hsync_start - overlap) * n;
4454 pipe_mode->crtc_hsync_end = (pipe_mode->crtc_hsync_end - overlap) * n;
4455 pipe_mode->crtc_htotal = (pipe_mode->crtc_htotal - overlap) * n;
4456 pipe_mode->crtc_clock *= n;
4459 intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
4461 if (DISPLAY_VER(dev_priv) < 4) {
4462 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
4465 * Enable double wide mode when the dot clock
4466 * is > 90% of the (display) core speed.
4468 if (intel_crtc_supports_double_wide(crtc) &&
4469 pipe_mode->crtc_clock > clock_limit) {
4470 clock_limit = dev_priv->max_dotclk_freq;
4471 pipe_config->double_wide = true;
4475 if (pipe_mode->crtc_clock > clock_limit) {
4476 drm_dbg_kms(&dev_priv->drm,
4477 "requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
4478 pipe_mode->crtc_clock, clock_limit,
4479 yesno(pipe_config->double_wide));
4484 * Pipe horizontal size must be even in:
4486 * - LVDS dual channel mode
4487 * - Double wide pipe
4489 if (pipe_config->pipe_src_w & 1) {
4490 if (pipe_config->double_wide) {
4491 drm_dbg_kms(&dev_priv->drm,
4492 "Odd pipe source width not supported with double wide pipe\n");
4496 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
4497 intel_is_dual_link_lvds(dev_priv)) {
4498 drm_dbg_kms(&dev_priv->drm,
4499 "Odd pipe source width not supported with dual link LVDS\n");
4504 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4505 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4507 if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) &&
4508 pipe_mode->crtc_hsync_start == pipe_mode->crtc_hdisplay)
4511 intel_crtc_compute_pixel_rate(pipe_config);
4513 if (pipe_config->has_pch_encoder)
4514 return ilk_fdi_compute_config(crtc, pipe_config);
4520 intel_reduce_m_n_ratio(u32 *num, u32 *den)
4522 while (*num > DATA_LINK_M_N_MASK ||
4523 *den > DATA_LINK_M_N_MASK) {
4529 static void compute_m_n(unsigned int m, unsigned int n,
4530 u32 *ret_m, u32 *ret_n,
4534 * Several DP dongles in particular seem to be fussy about
4535 * too large link M/N values. Give N value as 0x8000 that
4536 * should be acceptable by specific devices. 0x8000 is the
4537 * specified fixed N value for asynchronous clock mode,
4538 * which the devices expect also in synchronous clock mode.
4541 *ret_n = DP_LINK_CONSTANT_N_VALUE;
4543 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4545 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
4546 intel_reduce_m_n_ratio(ret_m, ret_n);
4550 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
4551 int pixel_clock, int link_clock,
4552 struct intel_link_m_n *m_n,
4553 bool constant_n, bool fec_enable)
4555 u32 data_clock = bits_per_pixel * pixel_clock;
4558 data_clock = intel_dp_mode_to_fec_clock(data_clock);
4561 compute_m_n(data_clock,
4562 link_clock * nlanes * 8,
4563 &m_n->gmch_m, &m_n->gmch_n,
4566 compute_m_n(pixel_clock, link_clock,
4567 &m_n->link_m, &m_n->link_n,
4571 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
4574 * There may be no VBT; and if the BIOS enabled SSC we can
4575 * just keep using it to avoid unnecessary flicker. Whereas if the
4576 * BIOS isn't using it, don't assume it will work even if the VBT
4577 * indicates as much.
4579 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
4580 bool bios_lvds_use_ssc = intel_de_read(dev_priv,
4584 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
4585 drm_dbg_kms(&dev_priv->drm,
4586 "SSC %s by BIOS, overriding VBT which says %s\n",
4587 enableddisabled(bios_lvds_use_ssc),
4588 enableddisabled(dev_priv->vbt.lvds_use_ssc));
4589 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
4594 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
4595 const struct intel_link_m_n *m_n)
4597 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4598 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4599 enum pipe pipe = crtc->pipe;
4601 intel_de_write(dev_priv, PCH_TRANS_DATA_M1(pipe),
4602 TU_SIZE(m_n->tu) | m_n->gmch_m);
4603 intel_de_write(dev_priv, PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4604 intel_de_write(dev_priv, PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4605 intel_de_write(dev_priv, PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4608 static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
4609 enum transcoder transcoder)
4611 if (IS_HASWELL(dev_priv))
4612 return transcoder == TRANSCODER_EDP;
4615 * Strictly speaking some registers are available before
4616 * gen7, but we only support DRRS on gen7+
4618 return DISPLAY_VER(dev_priv) == 7 || IS_CHERRYVIEW(dev_priv);
4621 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
4622 const struct intel_link_m_n *m_n,
4623 const struct intel_link_m_n *m2_n2)
4625 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4626 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4627 enum pipe pipe = crtc->pipe;
4628 enum transcoder transcoder = crtc_state->cpu_transcoder;
4630 if (DISPLAY_VER(dev_priv) >= 5) {
4631 intel_de_write(dev_priv, PIPE_DATA_M1(transcoder),
4632 TU_SIZE(m_n->tu) | m_n->gmch_m);
4633 intel_de_write(dev_priv, PIPE_DATA_N1(transcoder),
4635 intel_de_write(dev_priv, PIPE_LINK_M1(transcoder),
4637 intel_de_write(dev_priv, PIPE_LINK_N1(transcoder),
4640 * M2_N2 registers are set only if DRRS is supported
4641 * (to make sure the registers are not unnecessarily accessed).
4643 if (m2_n2 && crtc_state->has_drrs &&
4644 transcoder_has_m2_n2(dev_priv, transcoder)) {
4645 intel_de_write(dev_priv, PIPE_DATA_M2(transcoder),
4646 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
4647 intel_de_write(dev_priv, PIPE_DATA_N2(transcoder),
4649 intel_de_write(dev_priv, PIPE_LINK_M2(transcoder),
4651 intel_de_write(dev_priv, PIPE_LINK_N2(transcoder),
4655 intel_de_write(dev_priv, PIPE_DATA_M_G4X(pipe),
4656 TU_SIZE(m_n->tu) | m_n->gmch_m);
4657 intel_de_write(dev_priv, PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4658 intel_de_write(dev_priv, PIPE_LINK_M_G4X(pipe), m_n->link_m);
4659 intel_de_write(dev_priv, PIPE_LINK_N_G4X(pipe), m_n->link_n);
4663 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
4665 const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
4666 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
4669 dp_m_n = &crtc_state->dp_m_n;
4670 dp_m2_n2 = &crtc_state->dp_m2_n2;
4671 } else if (m_n == M2_N2) {
4674 * M2_N2 registers are not supported. Hence m2_n2 divider value
4675 * needs to be programmed into M1_N1.
4677 dp_m_n = &crtc_state->dp_m2_n2;
4679 drm_err(&i915->drm, "Unsupported divider value\n");
4683 if (crtc_state->has_pch_encoder)
4684 intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);
4686 intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
4689 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
4691 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4692 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4693 enum pipe pipe = crtc->pipe;
4694 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4695 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
4696 u32 crtc_vtotal, crtc_vblank_end;
4699 /* We need to be careful not to changed the adjusted mode, for otherwise
4700 * the hw state checker will get angry at the mismatch. */
4701 crtc_vtotal = adjusted_mode->crtc_vtotal;
4702 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4704 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4705 /* the chip adds 2 halflines automatically */
4707 crtc_vblank_end -= 1;
4709 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
4710 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
4712 vsyncshift = adjusted_mode->crtc_hsync_start -
4713 adjusted_mode->crtc_htotal / 2;
4715 vsyncshift += adjusted_mode->crtc_htotal;
4718 if (DISPLAY_VER(dev_priv) > 3)
4719 intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder),
4722 intel_de_write(dev_priv, HTOTAL(cpu_transcoder),
4723 (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16));
4724 intel_de_write(dev_priv, HBLANK(cpu_transcoder),
4725 (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
4726 intel_de_write(dev_priv, HSYNC(cpu_transcoder),
4727 (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
4729 intel_de_write(dev_priv, VTOTAL(cpu_transcoder),
4730 (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16));
4731 intel_de_write(dev_priv, VBLANK(cpu_transcoder),
4732 (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16));
4733 intel_de_write(dev_priv, VSYNC(cpu_transcoder),
4734 (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
4736 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4737 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4738 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4740 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
4741 (pipe == PIPE_B || pipe == PIPE_C))
4742 intel_de_write(dev_priv, VTOTAL(pipe),
4743 intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
4747 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
4749 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4750 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4751 enum pipe pipe = crtc->pipe;
4753 /* pipesrc controls the size that is scaled from, which should
4754 * always be the user's requested size.
4756 intel_de_write(dev_priv, PIPESRC(pipe),
4757 ((crtc_state->pipe_src_w - 1) << 16) | (crtc_state->pipe_src_h - 1));
4760 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
4762 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4763 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4765 if (DISPLAY_VER(dev_priv) == 2)
4768 if (DISPLAY_VER(dev_priv) >= 9 ||
4769 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
4770 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW;
4772 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
4775 static void intel_get_transcoder_timings(struct intel_crtc *crtc,
4776 struct intel_crtc_state *pipe_config)
4778 struct drm_device *dev = crtc->base.dev;
4779 struct drm_i915_private *dev_priv = to_i915(dev);
4780 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4783 tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder));
4784 pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4785 pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4787 if (!transcoder_is_dsi(cpu_transcoder)) {
4788 tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder));
4789 pipe_config->hw.adjusted_mode.crtc_hblank_start =
4791 pipe_config->hw.adjusted_mode.crtc_hblank_end =
4792 ((tmp >> 16) & 0xffff) + 1;
4794 tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder));
4795 pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4796 pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4798 tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder));
4799 pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4800 pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4802 if (!transcoder_is_dsi(cpu_transcoder)) {
4803 tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder));
4804 pipe_config->hw.adjusted_mode.crtc_vblank_start =
4806 pipe_config->hw.adjusted_mode.crtc_vblank_end =
4807 ((tmp >> 16) & 0xffff) + 1;
4809 tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder));
4810 pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4811 pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4813 if (intel_pipe_is_interlaced(pipe_config)) {
4814 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4815 pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
4816 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
4820 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
4821 struct intel_crtc_state *pipe_config)
4823 struct drm_device *dev = crtc->base.dev;
4824 struct drm_i915_private *dev_priv = to_i915(dev);
4827 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
4828 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4829 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4832 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
4834 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4835 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4840 /* we keep both pipes enabled on 830 */
4841 if (IS_I830(dev_priv))
4842 pipeconf |= intel_de_read(dev_priv, PIPECONF(crtc->pipe)) & PIPECONF_ENABLE;
4844 if (crtc_state->double_wide)
4845 pipeconf |= PIPECONF_DOUBLE_WIDE;
4847 /* only g4x and later have fancy bpc/dither controls */
4848 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
4849 IS_CHERRYVIEW(dev_priv)) {
4850 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4851 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
4852 pipeconf |= PIPECONF_DITHER_EN |
4853 PIPECONF_DITHER_TYPE_SP;
4855 switch (crtc_state->pipe_bpp) {
4857 pipeconf |= PIPECONF_6BPC;
4860 pipeconf |= PIPECONF_8BPC;
4863 pipeconf |= PIPECONF_10BPC;
4866 /* Case prevented by intel_choose_pipe_bpp_dither. */
4871 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
4872 if (DISPLAY_VER(dev_priv) < 4 ||
4873 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
4874 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4876 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
4878 pipeconf |= PIPECONF_PROGRESSIVE;
4881 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
4882 crtc_state->limited_color_range)
4883 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4885 pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
4887 pipeconf |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
4889 intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf);
4890 intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe));
4893 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
4895 if (IS_I830(dev_priv))
4898 return DISPLAY_VER(dev_priv) >= 4 ||
4899 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
4902 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
4904 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4905 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4908 if (!i9xx_has_pfit(dev_priv))
4911 tmp = intel_de_read(dev_priv, PFIT_CONTROL);
4912 if (!(tmp & PFIT_ENABLE))
4915 /* Check whether the pfit is attached to our pipe. */
4916 if (DISPLAY_VER(dev_priv) < 4) {
4917 if (crtc->pipe != PIPE_B)
4920 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4924 crtc_state->gmch_pfit.control = tmp;
4925 crtc_state->gmch_pfit.pgm_ratios =
4926 intel_de_read(dev_priv, PFIT_PGM_RATIOS);
4929 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
4930 struct intel_crtc_state *pipe_config)
4932 struct drm_device *dev = crtc->base.dev;
4933 struct drm_i915_private *dev_priv = to_i915(dev);
4934 enum pipe pipe = crtc->pipe;
4937 int refclk = 100000;
4939 /* In case of DSI, DPLL will not be used */
4940 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
4943 vlv_dpio_get(dev_priv);
4944 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
4945 vlv_dpio_put(dev_priv);
4947 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
4948 clock.m2 = mdiv & DPIO_M2DIV_MASK;
4949 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
4950 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
4951 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
4953 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
4956 static void chv_crtc_clock_get(struct intel_crtc *crtc,
4957 struct intel_crtc_state *pipe_config)
4959 struct drm_device *dev = crtc->base.dev;
4960 struct drm_i915_private *dev_priv = to_i915(dev);
4961 enum pipe pipe = crtc->pipe;
4962 enum dpio_channel port = vlv_pipe_to_channel(pipe);
4964 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
4965 int refclk = 100000;
4967 /* In case of DSI, DPLL will not be used */
4968 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
4971 vlv_dpio_get(dev_priv);
4972 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
4973 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
4974 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
4975 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
4976 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
4977 vlv_dpio_put(dev_priv);
4979 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
4980 clock.m2 = (pll_dw0 & 0xff) << 22;
4981 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
4982 clock.m2 |= pll_dw2 & 0x3fffff;
4983 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
4984 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
4985 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
4987 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
4990 static enum intel_output_format
4991 bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
4993 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4996 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
4998 if (tmp & PIPEMISC_YUV420_ENABLE) {
4999 /* We support 4:2:0 in full blend mode only */
5000 drm_WARN_ON(&dev_priv->drm,
5001 (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0);
5003 return INTEL_OUTPUT_FORMAT_YCBCR420;
5004 } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
5005 return INTEL_OUTPUT_FORMAT_YCBCR444;
5007 return INTEL_OUTPUT_FORMAT_RGB;
5011 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
5013 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5014 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
5015 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5016 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
5019 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
5021 if (tmp & DISPPLANE_GAMMA_ENABLE)
5022 crtc_state->gamma_enable = true;
5024 if (!HAS_GMCH(dev_priv) &&
5025 tmp & DISPPLANE_PIPE_CSC_ENABLE)
5026 crtc_state->csc_enable = true;
5029 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5030 struct intel_crtc_state *pipe_config)
5032 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5033 enum intel_display_power_domain power_domain;
5034 intel_wakeref_t wakeref;
5038 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
5039 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
5043 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
5044 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5045 pipe_config->shared_dpll = NULL;
5049 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
5050 if (!(tmp & PIPECONF_ENABLE))
5053 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
5054 IS_CHERRYVIEW(dev_priv)) {
5055 switch (tmp & PIPECONF_BPC_MASK) {
5057 pipe_config->pipe_bpp = 18;
5060 pipe_config->pipe_bpp = 24;
5062 case PIPECONF_10BPC:
5063 pipe_config->pipe_bpp = 30;
5070 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
5071 (tmp & PIPECONF_COLOR_RANGE_SELECT))
5072 pipe_config->limited_color_range = true;
5074 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
5075 PIPECONF_GAMMA_MODE_SHIFT;
5077 if (IS_CHERRYVIEW(dev_priv))
5078 pipe_config->cgm_mode = intel_de_read(dev_priv,
5079 CGM_PIPE_MODE(crtc->pipe));
5081 i9xx_get_pipe_color_config(pipe_config);
5082 intel_color_get_config(pipe_config);
5084 if (DISPLAY_VER(dev_priv) < 4)
5085 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5087 intel_get_transcoder_timings(crtc, pipe_config);
5088 intel_get_pipe_src_size(crtc, pipe_config);
5090 i9xx_get_pfit_config(pipe_config);
5092 if (DISPLAY_VER(dev_priv) >= 4) {
5093 /* No way to read it out on pipes B and C */
5094 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
5095 tmp = dev_priv->chv_dpll_md[crtc->pipe];
5097 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
5098 pipe_config->pixel_multiplier =
5099 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5100 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5101 pipe_config->dpll_hw_state.dpll_md = tmp;
5102 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
5103 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
5104 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe));
5105 pipe_config->pixel_multiplier =
5106 ((tmp & SDVO_MULTIPLIER_MASK)
5107 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5109 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5110 * port and will be fixed up in the encoder->get_config
5112 pipe_config->pixel_multiplier = 1;
5114 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv,
5116 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
5117 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv,
5119 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv,
5122 /* Mask out read-only status bits. */
5123 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5124 DPLL_PORTC_READY_MASK |
5125 DPLL_PORTB_READY_MASK);
5128 if (IS_CHERRYVIEW(dev_priv))
5129 chv_crtc_clock_get(crtc, pipe_config);
5130 else if (IS_VALLEYVIEW(dev_priv))
5131 vlv_crtc_clock_get(crtc, pipe_config);
5133 i9xx_crtc_clock_get(crtc, pipe_config);
5136 * Normally the dotclock is filled in by the encoder .get_config()
5137 * but in case the pipe is enabled w/o any ports we need a sane
5140 pipe_config->hw.adjusted_mode.crtc_clock =
5141 pipe_config->port_clock / pipe_config->pixel_multiplier;
5146 intel_display_power_put(dev_priv, power_domain, wakeref);
5151 static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
5153 struct intel_encoder *encoder;
5156 bool has_lvds = false;
5157 bool has_cpu_edp = false;
5158 bool has_panel = false;
5159 bool has_ck505 = false;
5160 bool can_ssc = false;
5161 bool using_ssc_source = false;
5163 /* We need to take the global config into account */
5164 for_each_intel_encoder(&dev_priv->drm, encoder) {
5165 switch (encoder->type) {
5166 case INTEL_OUTPUT_LVDS:
5170 case INTEL_OUTPUT_EDP:
5172 if (encoder->port == PORT_A)
5180 if (HAS_PCH_IBX(dev_priv)) {
5181 has_ck505 = dev_priv->vbt.display_clock_mode;
5182 can_ssc = has_ck505;
5188 /* Check if any DPLLs are using the SSC source */
5189 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
5190 u32 temp = intel_de_read(dev_priv, PCH_DPLL(i));
5192 if (!(temp & DPLL_VCO_ENABLE))
5195 if ((temp & PLL_REF_INPUT_MASK) ==
5196 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5197 using_ssc_source = true;
5202 drm_dbg_kms(&dev_priv->drm,
5203 "has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
5204 has_panel, has_lvds, has_ck505, using_ssc_source);
5206 /* Ironlake: try to setup display ref clock before DPLL
5207 * enabling. This is only under driver's control after
5208 * PCH B stepping, previous chipset stepping should be
5209 * ignoring this setting.
5211 val = intel_de_read(dev_priv, PCH_DREF_CONTROL);
5213 /* As we must carefully and slowly disable/enable each source in turn,
5214 * compute the final state we want first and check if we need to
5215 * make any changes at all.
5218 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5220 final |= DREF_NONSPREAD_CK505_ENABLE;
5222 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5224 final &= ~DREF_SSC_SOURCE_MASK;
5225 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5226 final &= ~DREF_SSC1_ENABLE;
5229 final |= DREF_SSC_SOURCE_ENABLE;
5231 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5232 final |= DREF_SSC1_ENABLE;
5235 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5236 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5238 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5240 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5241 } else if (using_ssc_source) {
5242 final |= DREF_SSC_SOURCE_ENABLE;
5243 final |= DREF_SSC1_ENABLE;
5249 /* Always enable nonspread source */
5250 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5253 val |= DREF_NONSPREAD_CK505_ENABLE;
5255 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5258 val &= ~DREF_SSC_SOURCE_MASK;
5259 val |= DREF_SSC_SOURCE_ENABLE;
5261 /* SSC must be turned on before enabling the CPU output */
5262 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5263 drm_dbg_kms(&dev_priv->drm, "Using SSC on panel\n");
5264 val |= DREF_SSC1_ENABLE;
5266 val &= ~DREF_SSC1_ENABLE;
5268 /* Get SSC going before enabling the outputs */
5269 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
5270 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
5273 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5275 /* Enable CPU source on CPU attached eDP */
5277 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5278 drm_dbg_kms(&dev_priv->drm,
5279 "Using SSC on eDP\n");
5280 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5282 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5284 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5286 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
5287 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
5290 drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n");
5292 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5294 /* Turn off CPU output */
5295 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5297 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
5298 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
5301 if (!using_ssc_source) {
5302 drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n");
5304 /* Turn off the SSC source */
5305 val &= ~DREF_SSC_SOURCE_MASK;
5306 val |= DREF_SSC_SOURCE_DISABLE;
5309 val &= ~DREF_SSC1_ENABLE;
5311 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
5312 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
5317 BUG_ON(val != final);
5320 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5324 tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
5325 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5326 intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
5328 if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) &
5329 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5330 drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n");
5332 tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
5333 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5334 intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
5336 if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) &
5337 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5338 drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n");
5341 /* WaMPhyProgramming:hsw */
5342 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5346 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5347 tmp &= ~(0xFF << 24);
5348 tmp |= (0x12 << 24);
5349 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5351 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5353 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5355 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5357 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5359 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5360 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5361 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5363 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5364 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5365 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5367 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5370 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5372 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5375 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5377 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5380 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5382 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5385 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5387 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5388 tmp &= ~(0xFF << 16);
5389 tmp |= (0x1C << 16);
5390 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5392 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5393 tmp &= ~(0xFF << 16);
5394 tmp |= (0x1C << 16);
5395 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5397 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5399 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5401 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5403 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5405 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5406 tmp &= ~(0xF << 28);
5408 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5410 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5411 tmp &= ~(0xF << 28);
5413 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5416 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5417 * Programming" based on the parameters passed:
5418 * - Sequence to enable CLKOUT_DP
5419 * - Sequence to enable CLKOUT_DP without spread
5420 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5422 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
5423 bool with_spread, bool with_fdi)
5427 if (drm_WARN(&dev_priv->drm, with_fdi && !with_spread,
5428 "FDI requires downspread\n"))
5430 if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) &&
5431 with_fdi, "LP PCH doesn't have FDI\n"))
5434 mutex_lock(&dev_priv->sb_lock);
5436 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5437 tmp &= ~SBI_SSCCTL_DISABLE;
5438 tmp |= SBI_SSCCTL_PATHALT;
5439 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5444 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5445 tmp &= ~SBI_SSCCTL_PATHALT;
5446 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5449 lpt_reset_fdi_mphy(dev_priv);
5450 lpt_program_fdi_mphy(dev_priv);
5454 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
5455 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5456 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5457 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5459 mutex_unlock(&dev_priv->sb_lock);
5462 /* Sequence to disable CLKOUT_DP */
5463 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
5467 mutex_lock(&dev_priv->sb_lock);
5469 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
5470 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5471 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5472 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5474 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5475 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5476 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5477 tmp |= SBI_SSCCTL_PATHALT;
5478 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5481 tmp |= SBI_SSCCTL_DISABLE;
5482 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5485 mutex_unlock(&dev_priv->sb_lock);
5488 #define BEND_IDX(steps) ((50 + (steps)) / 5)
5490 static const u16 sscdivintphase[] = {
5491 [BEND_IDX( 50)] = 0x3B23,
5492 [BEND_IDX( 45)] = 0x3B23,
5493 [BEND_IDX( 40)] = 0x3C23,
5494 [BEND_IDX( 35)] = 0x3C23,
5495 [BEND_IDX( 30)] = 0x3D23,
5496 [BEND_IDX( 25)] = 0x3D23,
5497 [BEND_IDX( 20)] = 0x3E23,
5498 [BEND_IDX( 15)] = 0x3E23,
5499 [BEND_IDX( 10)] = 0x3F23,
5500 [BEND_IDX( 5)] = 0x3F23,
5501 [BEND_IDX( 0)] = 0x0025,
5502 [BEND_IDX( -5)] = 0x0025,
5503 [BEND_IDX(-10)] = 0x0125,
5504 [BEND_IDX(-15)] = 0x0125,
5505 [BEND_IDX(-20)] = 0x0225,
5506 [BEND_IDX(-25)] = 0x0225,
5507 [BEND_IDX(-30)] = 0x0325,
5508 [BEND_IDX(-35)] = 0x0325,
5509 [BEND_IDX(-40)] = 0x0425,
5510 [BEND_IDX(-45)] = 0x0425,
5511 [BEND_IDX(-50)] = 0x0525,
5516 * steps -50 to 50 inclusive, in steps of 5
5517 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
5518 * change in clock period = -(steps / 10) * 5.787 ps
5520 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
5523 int idx = BEND_IDX(steps);
5525 if (drm_WARN_ON(&dev_priv->drm, steps % 5 != 0))
5528 if (drm_WARN_ON(&dev_priv->drm, idx >= ARRAY_SIZE(sscdivintphase)))
5531 mutex_lock(&dev_priv->sb_lock);
5533 if (steps % 10 != 0)
5537 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
5539 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
5541 tmp |= sscdivintphase[idx];
5542 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
5544 mutex_unlock(&dev_priv->sb_lock);
5549 static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
5551 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
5552 u32 ctl = intel_de_read(dev_priv, SPLL_CTL);
5554 if ((ctl & SPLL_PLL_ENABLE) == 0)
5557 if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC &&
5558 (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
5561 if (IS_BROADWELL(dev_priv) &&
5562 (ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW)
5568 static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
5569 enum intel_dpll_id id)
5571 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
5572 u32 ctl = intel_de_read(dev_priv, WRPLL_CTL(id));
5574 if ((ctl & WRPLL_PLL_ENABLE) == 0)
5577 if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
5580 if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
5581 (ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW &&
5582 (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
5588 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
5590 struct intel_encoder *encoder;
5591 bool has_fdi = false;
5593 for_each_intel_encoder(&dev_priv->drm, encoder) {
5594 switch (encoder->type) {
5595 case INTEL_OUTPUT_ANALOG:
5604 * The BIOS may have decided to use the PCH SSC
5605 * reference so we must not disable it until the
5606 * relevant PLLs have stopped relying on it. We'll
5607 * just leave the PCH SSC reference enabled in case
5608 * any active PLL is using it. It will get disabled
5609 * after runtime suspend if we don't have FDI.
5611 * TODO: Move the whole reference clock handling
5612 * to the modeset sequence proper so that we can
5613 * actually enable/disable/reconfigure these things
5614 * safely. To do that we need to introduce a real
5615 * clock hierarchy. That would also allow us to do
5616 * clock bending finally.
5618 dev_priv->pch_ssc_use = 0;
5620 if (spll_uses_pch_ssc(dev_priv)) {
5621 drm_dbg_kms(&dev_priv->drm, "SPLL using PCH SSC\n");
5622 dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
5625 if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
5626 drm_dbg_kms(&dev_priv->drm, "WRPLL1 using PCH SSC\n");
5627 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
5630 if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
5631 drm_dbg_kms(&dev_priv->drm, "WRPLL2 using PCH SSC\n");
5632 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
5635 if (dev_priv->pch_ssc_use)
5639 lpt_bend_clkout_dp(dev_priv, 0);
5640 lpt_enable_clkout_dp(dev_priv, true, true);
5642 lpt_disable_clkout_dp(dev_priv);
5647 * Initialize reference clocks when the driver loads
5649 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
5651 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
5652 ilk_init_pch_refclk(dev_priv);
5653 else if (HAS_PCH_LPT(dev_priv))
5654 lpt_init_pch_refclk(dev_priv);
5657 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
5659 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5660 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5661 enum pipe pipe = crtc->pipe;
5666 switch (crtc_state->pipe_bpp) {
5668 val |= PIPECONF_6BPC;
5671 val |= PIPECONF_8BPC;
5674 val |= PIPECONF_10BPC;
5677 val |= PIPECONF_12BPC;
5680 /* Case prevented by intel_choose_pipe_bpp_dither. */
5684 if (crtc_state->dither)
5685 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5687 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5688 val |= PIPECONF_INTERLACED_ILK;
5690 val |= PIPECONF_PROGRESSIVE;
5693 * This would end up with an odd purple hue over
5694 * the entire display. Make sure we don't do it.
5696 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
5697 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
5699 if (crtc_state->limited_color_range &&
5700 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
5701 val |= PIPECONF_COLOR_RANGE_SELECT;
5703 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
5704 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
5706 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
5708 val |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
5710 intel_de_write(dev_priv, PIPECONF(pipe), val);
5711 intel_de_posting_read(dev_priv, PIPECONF(pipe));
5714 static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state)
5716 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5717 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5718 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5721 if (IS_HASWELL(dev_priv) && crtc_state->dither)
5722 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5724 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5725 val |= PIPECONF_INTERLACED_ILK;
5727 val |= PIPECONF_PROGRESSIVE;
5729 if (IS_HASWELL(dev_priv) &&
5730 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
5731 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
5733 intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val);
5734 intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder));
5737 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
5739 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5740 const struct intel_crtc_scaler_state *scaler_state =
5741 &crtc_state->scaler_state;
5743 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5747 switch (crtc_state->pipe_bpp) {
5749 val |= PIPEMISC_DITHER_6_BPC;
5752 val |= PIPEMISC_DITHER_8_BPC;
5755 val |= PIPEMISC_DITHER_10_BPC;
5758 val |= PIPEMISC_DITHER_12_BPC;
5761 MISSING_CASE(crtc_state->pipe_bpp);
5765 if (crtc_state->dither)
5766 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
5768 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
5769 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
5770 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
5772 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
5773 val |= PIPEMISC_YUV420_ENABLE |
5774 PIPEMISC_YUV420_MODE_FULL_BLEND;
5776 if (DISPLAY_VER(dev_priv) >= 11 &&
5777 (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
5778 BIT(PLANE_CURSOR))) == 0)
5779 val |= PIPEMISC_HDR_MODE_PRECISION;
5781 if (DISPLAY_VER(dev_priv) >= 12)
5782 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC;
5784 if (IS_ALDERLAKE_P(dev_priv)) {
5785 bool scaler_in_use = false;
5787 for (i = 0; i < crtc->num_scalers; i++) {
5788 if (!scaler_state->scalers[i].in_use)
5791 scaler_in_use = true;
5795 intel_de_rmw(dev_priv, PIPE_MISC2(crtc->pipe),
5796 PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK,
5797 scaler_in_use ? PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN :
5798 PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS);
5801 intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val);
5804 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
5806 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5809 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
5811 switch (tmp & PIPEMISC_DITHER_BPC_MASK) {
5812 case PIPEMISC_DITHER_6_BPC:
5814 case PIPEMISC_DITHER_8_BPC:
5816 case PIPEMISC_DITHER_10_BPC:
5818 case PIPEMISC_DITHER_12_BPC:
5826 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
5829 * Account for spread spectrum to avoid
5830 * oversubscribing the link. Max center spread
5831 * is 2.5%; use 5% for safety's sake.
5833 u32 bps = target_clock * bpp * 21 / 20;
5834 return DIV_ROUND_UP(bps, link_bw * 8);
5837 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
5838 struct intel_link_m_n *m_n)
5840 struct drm_device *dev = crtc->base.dev;
5841 struct drm_i915_private *dev_priv = to_i915(dev);
5842 enum pipe pipe = crtc->pipe;
5844 m_n->link_m = intel_de_read(dev_priv, PCH_TRANS_LINK_M1(pipe));
5845 m_n->link_n = intel_de_read(dev_priv, PCH_TRANS_LINK_N1(pipe));
5846 m_n->gmch_m = intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
5848 m_n->gmch_n = intel_de_read(dev_priv, PCH_TRANS_DATA_N1(pipe));
5849 m_n->tu = ((intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
5850 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5853 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
5854 enum transcoder transcoder,
5855 struct intel_link_m_n *m_n,
5856 struct intel_link_m_n *m2_n2)
5858 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5859 enum pipe pipe = crtc->pipe;
5861 if (DISPLAY_VER(dev_priv) >= 5) {
5862 m_n->link_m = intel_de_read(dev_priv,
5863 PIPE_LINK_M1(transcoder));
5864 m_n->link_n = intel_de_read(dev_priv,
5865 PIPE_LINK_N1(transcoder));
5866 m_n->gmch_m = intel_de_read(dev_priv,
5867 PIPE_DATA_M1(transcoder))
5869 m_n->gmch_n = intel_de_read(dev_priv,
5870 PIPE_DATA_N1(transcoder));
5871 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M1(transcoder))
5872 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5874 if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
5875 m2_n2->link_m = intel_de_read(dev_priv,
5876 PIPE_LINK_M2(transcoder));
5877 m2_n2->link_n = intel_de_read(dev_priv,
5878 PIPE_LINK_N2(transcoder));
5879 m2_n2->gmch_m = intel_de_read(dev_priv,
5880 PIPE_DATA_M2(transcoder))
5882 m2_n2->gmch_n = intel_de_read(dev_priv,
5883 PIPE_DATA_N2(transcoder));
5884 m2_n2->tu = ((intel_de_read(dev_priv, PIPE_DATA_M2(transcoder))
5885 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5888 m_n->link_m = intel_de_read(dev_priv, PIPE_LINK_M_G4X(pipe));
5889 m_n->link_n = intel_de_read(dev_priv, PIPE_LINK_N_G4X(pipe));
5890 m_n->gmch_m = intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
5892 m_n->gmch_n = intel_de_read(dev_priv, PIPE_DATA_N_G4X(pipe));
5893 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
5894 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5898 void intel_dp_get_m_n(struct intel_crtc *crtc,
5899 struct intel_crtc_state *pipe_config)
5901 if (pipe_config->has_pch_encoder)
5902 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
5904 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5905 &pipe_config->dp_m_n,
5906 &pipe_config->dp_m2_n2);
5909 static void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
5910 struct intel_crtc_state *pipe_config)
5912 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5913 &pipe_config->fdi_m_n, NULL);
5916 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state,
5919 drm_rect_init(&crtc_state->pch_pfit.dst,
5920 pos >> 16, pos & 0xffff,
5921 size >> 16, size & 0xffff);
5924 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state)
5926 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5927 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5928 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
5932 /* find scaler attached to this pipe */
5933 for (i = 0; i < crtc->num_scalers; i++) {
5936 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
5937 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)
5941 crtc_state->pch_pfit.enabled = true;
5943 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i));
5944 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
5946 ilk_get_pfit_pos_size(crtc_state, pos, size);
5948 scaler_state->scalers[i].in_use = true;
5952 scaler_state->scaler_id = id;
5954 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
5956 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
5959 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
5961 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5962 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5965 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
5966 if ((ctl & PF_ENABLE) == 0)
5969 crtc_state->pch_pfit.enabled = true;
5971 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
5972 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
5974 ilk_get_pfit_pos_size(crtc_state, pos, size);
5977 * We currently do not free assignements of panel fitters on
5978 * ivb/hsw (since we don't use the higher upscaling modes which
5979 * differentiates them) so just WARN about this case for now.
5981 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 &&
5982 (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe));
5985 static bool ilk_get_pipe_config(struct intel_crtc *crtc,
5986 struct intel_crtc_state *pipe_config)
5988 struct drm_device *dev = crtc->base.dev;
5989 struct drm_i915_private *dev_priv = to_i915(dev);
5990 enum intel_display_power_domain power_domain;
5991 intel_wakeref_t wakeref;
5995 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
5996 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
6000 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6001 pipe_config->shared_dpll = NULL;
6004 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
6005 if (!(tmp & PIPECONF_ENABLE))
6008 switch (tmp & PIPECONF_BPC_MASK) {
6010 pipe_config->pipe_bpp = 18;
6013 pipe_config->pipe_bpp = 24;
6015 case PIPECONF_10BPC:
6016 pipe_config->pipe_bpp = 30;
6018 case PIPECONF_12BPC:
6019 pipe_config->pipe_bpp = 36;
6025 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
6026 pipe_config->limited_color_range = true;
6028 switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
6029 case PIPECONF_OUTPUT_COLORSPACE_YUV601:
6030 case PIPECONF_OUTPUT_COLORSPACE_YUV709:
6031 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
6034 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
6038 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
6039 PIPECONF_GAMMA_MODE_SHIFT;
6041 pipe_config->csc_mode = intel_de_read(dev_priv,
6042 PIPE_CSC_MODE(crtc->pipe));
6044 i9xx_get_pipe_color_config(pipe_config);
6045 intel_color_get_config(pipe_config);
6047 if (intel_de_read(dev_priv, PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6048 struct intel_shared_dpll *pll;
6049 enum intel_dpll_id pll_id;
6052 pipe_config->has_pch_encoder = true;
6054 tmp = intel_de_read(dev_priv, FDI_RX_CTL(crtc->pipe));
6055 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6056 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6058 ilk_get_fdi_m_n_config(crtc, pipe_config);
6060 if (HAS_PCH_IBX(dev_priv)) {
6062 * The pipe->pch transcoder and pch transcoder->pll
6065 pll_id = (enum intel_dpll_id) crtc->pipe;
6067 tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
6068 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6069 pll_id = DPLL_ID_PCH_PLL_B;
6071 pll_id= DPLL_ID_PCH_PLL_A;
6074 pipe_config->shared_dpll =
6075 intel_get_shared_dpll_by_id(dev_priv, pll_id);
6076 pll = pipe_config->shared_dpll;
6078 pll_active = intel_dpll_get_hw_state(dev_priv, pll,
6079 &pipe_config->dpll_hw_state);
6080 drm_WARN_ON(dev, !pll_active);
6082 tmp = pipe_config->dpll_hw_state.dpll;
6083 pipe_config->pixel_multiplier =
6084 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6085 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6087 ilk_pch_clock_get(crtc, pipe_config);
6089 pipe_config->pixel_multiplier = 1;
6092 intel_get_transcoder_timings(crtc, pipe_config);
6093 intel_get_pipe_src_size(crtc, pipe_config);
6095 ilk_get_pfit_config(pipe_config);
6100 intel_display_power_put(dev_priv, power_domain, wakeref);
6105 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
6106 struct intel_crtc_state *pipe_config,
6107 struct intel_display_power_domain_set *power_domain_set)
6109 struct drm_device *dev = crtc->base.dev;
6110 struct drm_i915_private *dev_priv = to_i915(dev);
6111 unsigned long panel_transcoder_mask = BIT(TRANSCODER_EDP);
6112 unsigned long enabled_panel_transcoders = 0;
6113 enum transcoder panel_transcoder;
6116 if (DISPLAY_VER(dev_priv) >= 11)
6117 panel_transcoder_mask |=
6118 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
6121 * The pipe->transcoder mapping is fixed with the exception of the eDP
6122 * and DSI transcoders handled below.
6124 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6127 * XXX: Do intel_display_power_get_if_enabled before reading this (for
6128 * consistency and less surprising code; it's in always on power).
6130 for_each_cpu_transcoder_masked(dev_priv, panel_transcoder,
6131 panel_transcoder_mask) {
6132 bool force_thru = false;
6133 enum pipe trans_pipe;
6135 tmp = intel_de_read(dev_priv,
6136 TRANS_DDI_FUNC_CTL(panel_transcoder));
6137 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
6141 * Log all enabled ones, only use the first one.
6143 * FIXME: This won't work for two separate DSI displays.
6145 enabled_panel_transcoders |= BIT(panel_transcoder);
6146 if (enabled_panel_transcoders != BIT(panel_transcoder))
6149 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6152 "unknown pipe linked to transcoder %s\n",
6153 transcoder_name(panel_transcoder));
6155 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6158 case TRANS_DDI_EDP_INPUT_A_ON:
6159 trans_pipe = PIPE_A;
6161 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6162 trans_pipe = PIPE_B;
6164 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6165 trans_pipe = PIPE_C;
6167 case TRANS_DDI_EDP_INPUT_D_ONOFF:
6168 trans_pipe = PIPE_D;
6172 if (trans_pipe == crtc->pipe) {
6173 pipe_config->cpu_transcoder = panel_transcoder;
6174 pipe_config->pch_pfit.force_thru = force_thru;
6179 * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1
6181 drm_WARN_ON(dev, (enabled_panel_transcoders & BIT(TRANSCODER_EDP)) &&
6182 enabled_panel_transcoders != BIT(TRANSCODER_EDP));
6184 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
6185 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6188 tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder));
6190 return tmp & PIPECONF_ENABLE;
6193 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
6194 struct intel_crtc_state *pipe_config,
6195 struct intel_display_power_domain_set *power_domain_set)
6197 struct drm_device *dev = crtc->base.dev;
6198 struct drm_i915_private *dev_priv = to_i915(dev);
6199 enum transcoder cpu_transcoder;
6203 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
6205 cpu_transcoder = TRANSCODER_DSI_A;
6207 cpu_transcoder = TRANSCODER_DSI_C;
6209 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
6210 POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
6214 * The PLL needs to be enabled with a valid divider
6215 * configuration, otherwise accessing DSI registers will hang
6216 * the machine. See BSpec North Display Engine
6217 * registers/MIPI[BXT]. We can break out here early, since we
6218 * need the same DSI PLL to be enabled for both DSI ports.
6220 if (!bxt_dsi_pll_is_enabled(dev_priv))
6223 /* XXX: this works for video mode only */
6224 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
6225 if (!(tmp & DPI_ENABLE))
6228 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
6229 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
6232 pipe_config->cpu_transcoder = cpu_transcoder;
6236 return transcoder_is_dsi(pipe_config->cpu_transcoder);
6239 static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
6240 struct intel_crtc_state *pipe_config)
6242 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6243 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6247 if (transcoder_is_dsi(cpu_transcoder)) {
6248 port = (cpu_transcoder == TRANSCODER_DSI_A) ?
6251 tmp = intel_de_read(dev_priv,
6252 TRANS_DDI_FUNC_CTL(cpu_transcoder));
6253 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
6255 if (DISPLAY_VER(dev_priv) >= 12)
6256 port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
6258 port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
6262 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6263 * DDI E. So just check whether this pipe is wired to DDI E and whether
6264 * the PCH transcoder is on.
6266 if (DISPLAY_VER(dev_priv) < 9 &&
6267 (port == PORT_E) && intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) {
6268 pipe_config->has_pch_encoder = true;
6270 tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
6271 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6272 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6274 ilk_get_fdi_m_n_config(crtc, pipe_config);
6278 static bool hsw_get_pipe_config(struct intel_crtc *crtc,
6279 struct intel_crtc_state *pipe_config)
6281 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6282 struct intel_display_power_domain_set power_domain_set = { };
6286 if (!intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set,
6287 POWER_DOMAIN_PIPE(crtc->pipe)))
6290 pipe_config->shared_dpll = NULL;
6292 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_set);
6294 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
6295 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_set)) {
6296 drm_WARN_ON(&dev_priv->drm, active);
6300 intel_dsc_get_config(pipe_config);
6301 if (DISPLAY_VER(dev_priv) >= 13 && !pipe_config->dsc.compression_enable)
6302 intel_uncompressed_joiner_get_config(pipe_config);
6305 /* bigjoiner slave doesn't enable transcoder */
6306 if (!pipe_config->bigjoiner_slave)
6310 pipe_config->pixel_multiplier = 1;
6312 /* we cannot read out most state, so don't bother.. */
6313 pipe_config->quirks |= PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE;
6314 } else if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
6315 DISPLAY_VER(dev_priv) >= 11) {
6316 hsw_get_ddi_port_state(crtc, pipe_config);
6317 intel_get_transcoder_timings(crtc, pipe_config);
6320 if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder))
6321 intel_vrr_get_config(crtc, pipe_config);
6323 intel_get_pipe_src_size(crtc, pipe_config);
6325 if (IS_HASWELL(dev_priv)) {
6326 u32 tmp = intel_de_read(dev_priv,
6327 PIPECONF(pipe_config->cpu_transcoder));
6329 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
6330 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
6332 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
6334 pipe_config->output_format =
6335 bdw_get_pipemisc_output_format(crtc);
6338 pipe_config->gamma_mode = intel_de_read(dev_priv,
6339 GAMMA_MODE(crtc->pipe));
6341 pipe_config->csc_mode = intel_de_read(dev_priv,
6342 PIPE_CSC_MODE(crtc->pipe));
6344 if (DISPLAY_VER(dev_priv) >= 9) {
6345 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe));
6347 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
6348 pipe_config->gamma_enable = true;
6350 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
6351 pipe_config->csc_enable = true;
6353 i9xx_get_pipe_color_config(pipe_config);
6356 intel_color_get_config(pipe_config);
6358 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));
6359 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
6360 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
6361 pipe_config->ips_linetime =
6362 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
6364 if (intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set,
6365 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {
6366 if (DISPLAY_VER(dev_priv) >= 9)
6367 skl_get_pfit_config(pipe_config);
6369 ilk_get_pfit_config(pipe_config);
6372 if (hsw_crtc_supports_ips(crtc)) {
6373 if (IS_HASWELL(dev_priv))
6374 pipe_config->ips_enabled = intel_de_read(dev_priv,
6375 IPS_CTL) & IPS_ENABLE;
6378 * We cannot readout IPS state on broadwell, set to
6379 * true so we can set it to a defined state on first
6382 pipe_config->ips_enabled = true;
6386 if (pipe_config->bigjoiner_slave) {
6387 /* Cannot be read out as a slave, set to 0. */
6388 pipe_config->pixel_multiplier = 0;
6389 } else if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
6390 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
6391 pipe_config->pixel_multiplier =
6392 intel_de_read(dev_priv,
6393 PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
6395 pipe_config->pixel_multiplier = 1;
6399 intel_display_power_put_all_in_set(dev_priv, &power_domain_set);
6404 static bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
6406 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6407 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
6409 if (!i915->display.get_pipe_config(crtc, crtc_state))
6412 crtc_state->hw.active = true;
6414 intel_crtc_readout_derived_state(crtc_state);
6419 /* VESA 640x480x72Hz mode to set on the pipe */
6420 static const struct drm_display_mode load_detect_mode = {
6421 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6422 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6425 struct drm_framebuffer *
6426 intel_framebuffer_create(struct drm_i915_gem_object *obj,
6427 struct drm_mode_fb_cmd2 *mode_cmd)
6429 struct intel_framebuffer *intel_fb;
6432 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6434 return ERR_PTR(-ENOMEM);
6436 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
6440 return &intel_fb->base;
6444 return ERR_PTR(ret);
6447 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
6448 struct drm_crtc *crtc)
6450 struct drm_plane *plane;
6451 struct drm_plane_state *plane_state;
6454 ret = drm_atomic_add_affected_planes(state, crtc);
6458 for_each_new_plane_in_state(state, plane, plane_state, i) {
6459 if (plane_state->crtc != crtc)
6462 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
6466 drm_atomic_set_fb_for_plane(plane_state, NULL);
6472 int intel_get_load_detect_pipe(struct drm_connector *connector,
6473 struct intel_load_detect_pipe *old,
6474 struct drm_modeset_acquire_ctx *ctx)
6476 struct intel_crtc *intel_crtc;
6477 struct intel_encoder *intel_encoder =
6478 intel_attached_encoder(to_intel_connector(connector));
6479 struct drm_crtc *possible_crtc;
6480 struct drm_encoder *encoder = &intel_encoder->base;
6481 struct drm_crtc *crtc = NULL;
6482 struct drm_device *dev = encoder->dev;
6483 struct drm_i915_private *dev_priv = to_i915(dev);
6484 struct drm_mode_config *config = &dev->mode_config;
6485 struct drm_atomic_state *state = NULL, *restore_state = NULL;
6486 struct drm_connector_state *connector_state;
6487 struct intel_crtc_state *crtc_state;
6490 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6491 connector->base.id, connector->name,
6492 encoder->base.id, encoder->name);
6494 old->restore_state = NULL;
6496 drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex));
6499 * Algorithm gets a little messy:
6501 * - if the connector already has an assigned crtc, use it (but make
6502 * sure it's on first)
6504 * - try to find the first unused crtc that can drive this connector,
6505 * and use that if we find one
6508 /* See if we already have a CRTC for this connector */
6509 if (connector->state->crtc) {
6510 crtc = connector->state->crtc;
6512 ret = drm_modeset_lock(&crtc->mutex, ctx);
6516 /* Make sure the crtc and connector are running */
6520 /* Find an unused one (if possible) */
6521 for_each_crtc(dev, possible_crtc) {
6523 if (!(encoder->possible_crtcs & (1 << i)))
6526 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
6530 if (possible_crtc->state->enable) {
6531 drm_modeset_unlock(&possible_crtc->mutex);
6535 crtc = possible_crtc;
6540 * If we didn't find an unused CRTC, don't use any.
6543 drm_dbg_kms(&dev_priv->drm,
6544 "no pipe available for load-detect\n");
6550 intel_crtc = to_intel_crtc(crtc);
6552 state = drm_atomic_state_alloc(dev);
6553 restore_state = drm_atomic_state_alloc(dev);
6554 if (!state || !restore_state) {
6559 state->acquire_ctx = ctx;
6560 restore_state->acquire_ctx = ctx;
6562 connector_state = drm_atomic_get_connector_state(state, connector);
6563 if (IS_ERR(connector_state)) {
6564 ret = PTR_ERR(connector_state);
6568 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
6572 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6573 if (IS_ERR(crtc_state)) {
6574 ret = PTR_ERR(crtc_state);
6578 crtc_state->uapi.active = true;
6580 ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi,
6585 ret = intel_modeset_disable_planes(state, crtc);
6589 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
6591 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
6593 ret = drm_atomic_add_affected_planes(restore_state, crtc);
6595 drm_dbg_kms(&dev_priv->drm,
6596 "Failed to create a copy of old state to restore: %i\n",
6601 ret = drm_atomic_commit(state);
6603 drm_dbg_kms(&dev_priv->drm,
6604 "failed to set mode on load-detect pipe\n");
6608 old->restore_state = restore_state;
6609 drm_atomic_state_put(state);
6611 /* let the connector get through one full cycle before testing */
6612 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
6617 drm_atomic_state_put(state);
6620 if (restore_state) {
6621 drm_atomic_state_put(restore_state);
6622 restore_state = NULL;
6625 if (ret == -EDEADLK)
6631 void intel_release_load_detect_pipe(struct drm_connector *connector,
6632 struct intel_load_detect_pipe *old,
6633 struct drm_modeset_acquire_ctx *ctx)
6635 struct intel_encoder *intel_encoder =
6636 intel_attached_encoder(to_intel_connector(connector));
6637 struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev);
6638 struct drm_encoder *encoder = &intel_encoder->base;
6639 struct drm_atomic_state *state = old->restore_state;
6642 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6643 connector->base.id, connector->name,
6644 encoder->base.id, encoder->name);
6649 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
6651 drm_dbg_kms(&i915->drm,
6652 "Couldn't release load detect pipe: %i\n", ret);
6653 drm_atomic_state_put(state);
6656 static int i9xx_pll_refclk(struct drm_device *dev,
6657 const struct intel_crtc_state *pipe_config)
6659 struct drm_i915_private *dev_priv = to_i915(dev);
6660 u32 dpll = pipe_config->dpll_hw_state.dpll;
6662 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
6663 return dev_priv->vbt.lvds_ssc_freq;
6664 else if (HAS_PCH_SPLIT(dev_priv))
6666 else if (DISPLAY_VER(dev_priv) != 2)
6672 /* Returns the clock of the currently programmed mode of the given pipe. */
6673 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
6674 struct intel_crtc_state *pipe_config)
6676 struct drm_device *dev = crtc->base.dev;
6677 struct drm_i915_private *dev_priv = to_i915(dev);
6678 enum pipe pipe = crtc->pipe;
6679 u32 dpll = pipe_config->dpll_hw_state.dpll;
6683 int refclk = i9xx_pll_refclk(dev, pipe_config);
6685 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6686 fp = pipe_config->dpll_hw_state.fp0;
6688 fp = pipe_config->dpll_hw_state.fp1;
6690 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6691 if (IS_PINEVIEW(dev_priv)) {
6692 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6693 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6695 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6696 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6699 if (DISPLAY_VER(dev_priv) != 2) {
6700 if (IS_PINEVIEW(dev_priv))
6701 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6702 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6704 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6705 DPLL_FPA01_P1_POST_DIV_SHIFT);
6707 switch (dpll & DPLL_MODE_MASK) {
6708 case DPLLB_MODE_DAC_SERIAL:
6709 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6712 case DPLLB_MODE_LVDS:
6713 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6717 drm_dbg_kms(&dev_priv->drm,
6718 "Unknown DPLL mode %08x in programmed "
6719 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6723 if (IS_PINEVIEW(dev_priv))
6724 port_clock = pnv_calc_dpll_params(refclk, &clock);
6726 port_clock = i9xx_calc_dpll_params(refclk, &clock);
6728 u32 lvds = IS_I830(dev_priv) ? 0 : intel_de_read(dev_priv,
6730 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
6733 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6734 DPLL_FPA01_P1_POST_DIV_SHIFT);
6736 if (lvds & LVDS_CLKB_POWER_UP)
6741 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6744 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6745 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6747 if (dpll & PLL_P2_DIVIDE_BY_4)
6753 port_clock = i9xx_calc_dpll_params(refclk, &clock);
6757 * This value includes pixel_multiplier. We will use
6758 * port_clock to compute adjusted_mode.crtc_clock in the
6759 * encoder's get_config() function.
6761 pipe_config->port_clock = port_clock;
6764 int intel_dotclock_calculate(int link_freq,
6765 const struct intel_link_m_n *m_n)
6768 * The calculation for the data clock is:
6769 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
6770 * But we want to avoid losing precison if possible, so:
6771 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
6773 * and the link clock is simpler:
6774 * link_clock = (m * link_clock) / n
6780 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
6783 static void ilk_pch_clock_get(struct intel_crtc *crtc,
6784 struct intel_crtc_state *pipe_config)
6786 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6788 /* read out port_clock from the DPLL */
6789 i9xx_crtc_clock_get(crtc, pipe_config);
6792 * In case there is an active pipe without active ports,
6793 * we may need some idea for the dotclock anyway.
6794 * Calculate one based on the FDI configuration.
6796 pipe_config->hw.adjusted_mode.crtc_clock =
6797 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
6798 &pipe_config->fdi_m_n);
6801 /* Returns the currently programmed mode of the given encoder. */
6802 struct drm_display_mode *
6803 intel_encoder_current_mode(struct intel_encoder *encoder)
6805 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6806 struct intel_crtc_state *crtc_state;
6807 struct drm_display_mode *mode;
6808 struct intel_crtc *crtc;
6811 if (!encoder->get_hw_state(encoder, &pipe))
6814 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6816 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6820 crtc_state = intel_crtc_state_alloc(crtc);
6826 if (!intel_crtc_get_pipe_config(crtc_state)) {
6832 intel_encoder_get_config(encoder, crtc_state);
6834 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode);
6842 * intel_wm_need_update - Check whether watermarks need updating
6843 * @cur: current plane state
6844 * @new: new plane state
6846 * Check current plane state versus the new one to determine whether
6847 * watermarks need to be recalculated.
6849 * Returns true or false.
6851 static bool intel_wm_need_update(const struct intel_plane_state *cur,
6852 struct intel_plane_state *new)
6854 /* Update watermarks on tiling or size changes. */
6855 if (new->uapi.visible != cur->uapi.visible)
6858 if (!cur->hw.fb || !new->hw.fb)
6861 if (cur->hw.fb->modifier != new->hw.fb->modifier ||
6862 cur->hw.rotation != new->hw.rotation ||
6863 drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
6864 drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
6865 drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
6866 drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
6872 static bool needs_scaling(const struct intel_plane_state *state)
6874 int src_w = drm_rect_width(&state->uapi.src) >> 16;
6875 int src_h = drm_rect_height(&state->uapi.src) >> 16;
6876 int dst_w = drm_rect_width(&state->uapi.dst);
6877 int dst_h = drm_rect_height(&state->uapi.dst);
6879 return (src_w != dst_w || src_h != dst_h);
6882 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
6883 struct intel_crtc_state *crtc_state,
6884 const struct intel_plane_state *old_plane_state,
6885 struct intel_plane_state *plane_state)
6887 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6888 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
6889 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6890 bool mode_changed = intel_crtc_needs_modeset(crtc_state);
6891 bool was_crtc_enabled = old_crtc_state->hw.active;
6892 bool is_crtc_enabled = crtc_state->hw.active;
6893 bool turn_off, turn_on, visible, was_visible;
6896 if (DISPLAY_VER(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
6897 ret = skl_update_scaler_plane(crtc_state, plane_state);
6902 was_visible = old_plane_state->uapi.visible;
6903 visible = plane_state->uapi.visible;
6905 if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible))
6906 was_visible = false;
6909 * Visibility is calculated as if the crtc was on, but
6910 * after scaler setup everything depends on it being off
6911 * when the crtc isn't active.
6913 * FIXME this is wrong for watermarks. Watermarks should also
6914 * be computed as if the pipe would be active. Perhaps move
6915 * per-plane wm computation to the .check_plane() hook, and
6916 * only combine the results from all planes in the current place?
6918 if (!is_crtc_enabled) {
6919 intel_plane_set_invisible(crtc_state, plane_state);
6923 if (!was_visible && !visible)
6926 turn_off = was_visible && (!visible || mode_changed);
6927 turn_on = visible && (!was_visible || mode_changed);
6929 drm_dbg_atomic(&dev_priv->drm,
6930 "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
6931 crtc->base.base.id, crtc->base.name,
6932 plane->base.base.id, plane->base.name,
6933 was_visible, visible,
6934 turn_off, turn_on, mode_changed);
6937 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
6938 crtc_state->update_wm_pre = true;
6940 /* must disable cxsr around plane enable/disable */
6941 if (plane->id != PLANE_CURSOR)
6942 crtc_state->disable_cxsr = true;
6943 } else if (turn_off) {
6944 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
6945 crtc_state->update_wm_post = true;
6947 /* must disable cxsr around plane enable/disable */
6948 if (plane->id != PLANE_CURSOR)
6949 crtc_state->disable_cxsr = true;
6950 } else if (intel_wm_need_update(old_plane_state, plane_state)) {
6951 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) {
6952 /* FIXME bollocks */
6953 crtc_state->update_wm_pre = true;
6954 crtc_state->update_wm_post = true;
6958 if (visible || was_visible)
6959 crtc_state->fb_bits |= plane->frontbuffer_bit;
6962 * ILK/SNB DVSACNTR/Sprite Enable
6963 * IVB SPR_CTL/Sprite Enable
6964 * "When in Self Refresh Big FIFO mode, a write to enable the
6965 * plane will be internally buffered and delayed while Big FIFO
6968 * Which means that enabling the sprite can take an extra frame
6969 * when we start in big FIFO mode (LP1+). Thus we need to drop
6970 * down to LP0 and wait for vblank in order to make sure the
6971 * sprite gets enabled on the next vblank after the register write.
6972 * Doing otherwise would risk enabling the sprite one frame after
6973 * we've already signalled flip completion. We can resume LP1+
6974 * once the sprite has been enabled.
6977 * WaCxSRDisabledForSpriteScaling:ivb
6978 * IVB SPR_SCALE/Scaling Enable
6979 * "Low Power watermarks must be disabled for at least one
6980 * frame before enabling sprite scaling, and kept disabled
6981 * until sprite scaling is disabled."
6983 * ILK/SNB DVSASCALE/Scaling Enable
6984 * "When in Self Refresh Big FIFO mode, scaling enable will be
6985 * masked off while Big FIFO mode is exiting."
6987 * Despite the w/a only being listed for IVB we assume that
6988 * the ILK/SNB note has similar ramifications, hence we apply
6989 * the w/a on all three platforms.
6991 * With experimental results seems this is needed also for primary
6992 * plane, not only sprite plane.
6994 if (plane->id != PLANE_CURSOR &&
6995 (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv) ||
6996 IS_IVYBRIDGE(dev_priv)) &&
6997 (turn_on || (!needs_scaling(old_plane_state) &&
6998 needs_scaling(plane_state))))
6999 crtc_state->disable_lp_wm = true;
7004 static bool encoders_cloneable(const struct intel_encoder *a,
7005 const struct intel_encoder *b)
7007 /* masks could be asymmetric, so check both ways */
7008 return a == b || (a->cloneable & (1 << b->type) &&
7009 b->cloneable & (1 << a->type));
7012 static bool check_single_encoder_cloning(struct intel_atomic_state *state,
7013 struct intel_crtc *crtc,
7014 struct intel_encoder *encoder)
7016 struct intel_encoder *source_encoder;
7017 struct drm_connector *connector;
7018 struct drm_connector_state *connector_state;
7021 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
7022 if (connector_state->crtc != &crtc->base)
7026 to_intel_encoder(connector_state->best_encoder);
7027 if (!encoders_cloneable(encoder, source_encoder))
7034 static int icl_add_linked_planes(struct intel_atomic_state *state)
7036 struct intel_plane *plane, *linked;
7037 struct intel_plane_state *plane_state, *linked_plane_state;
7040 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
7041 linked = plane_state->planar_linked_plane;
7046 linked_plane_state = intel_atomic_get_plane_state(state, linked);
7047 if (IS_ERR(linked_plane_state))
7048 return PTR_ERR(linked_plane_state);
7050 drm_WARN_ON(state->base.dev,
7051 linked_plane_state->planar_linked_plane != plane);
7052 drm_WARN_ON(state->base.dev,
7053 linked_plane_state->planar_slave == plane_state->planar_slave);
7059 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
7061 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7062 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7063 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
7064 struct intel_plane *plane, *linked;
7065 struct intel_plane_state *plane_state;
7068 if (DISPLAY_VER(dev_priv) < 11)
7072 * Destroy all old plane links and make the slave plane invisible
7073 * in the crtc_state->active_planes mask.
7075 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
7076 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
7079 plane_state->planar_linked_plane = NULL;
7080 if (plane_state->planar_slave && !plane_state->uapi.visible) {
7081 crtc_state->enabled_planes &= ~BIT(plane->id);
7082 crtc_state->active_planes &= ~BIT(plane->id);
7083 crtc_state->update_planes |= BIT(plane->id);
7086 plane_state->planar_slave = false;
7089 if (!crtc_state->nv12_planes)
7092 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
7093 struct intel_plane_state *linked_state = NULL;
7095 if (plane->pipe != crtc->pipe ||
7096 !(crtc_state->nv12_planes & BIT(plane->id)))
7099 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
7100 if (!icl_is_nv12_y_plane(dev_priv, linked->id))
7103 if (crtc_state->active_planes & BIT(linked->id))
7106 linked_state = intel_atomic_get_plane_state(state, linked);
7107 if (IS_ERR(linked_state))
7108 return PTR_ERR(linked_state);
7113 if (!linked_state) {
7114 drm_dbg_kms(&dev_priv->drm,
7115 "Need %d free Y planes for planar YUV\n",
7116 hweight8(crtc_state->nv12_planes));
7121 plane_state->planar_linked_plane = linked;
7123 linked_state->planar_slave = true;
7124 linked_state->planar_linked_plane = plane;
7125 crtc_state->enabled_planes |= BIT(linked->id);
7126 crtc_state->active_planes |= BIT(linked->id);
7127 crtc_state->update_planes |= BIT(linked->id);
7128 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
7129 linked->base.name, plane->base.name);
7131 /* Copy parameters to slave plane */
7132 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
7133 linked_state->color_ctl = plane_state->color_ctl;
7134 linked_state->view = plane_state->view;
7136 intel_plane_copy_hw_state(linked_state, plane_state);
7137 linked_state->uapi.src = plane_state->uapi.src;
7138 linked_state->uapi.dst = plane_state->uapi.dst;
7140 if (icl_is_hdr_plane(dev_priv, plane->id)) {
7141 if (linked->id == PLANE_SPRITE5)
7142 plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
7143 else if (linked->id == PLANE_SPRITE4)
7144 plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
7145 else if (linked->id == PLANE_SPRITE3)
7146 plane_state->cus_ctl |= PLANE_CUS_PLANE_5_RKL;
7147 else if (linked->id == PLANE_SPRITE2)
7148 plane_state->cus_ctl |= PLANE_CUS_PLANE_4_RKL;
7150 MISSING_CASE(linked->id);
7157 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
7159 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
7160 struct intel_atomic_state *state =
7161 to_intel_atomic_state(new_crtc_state->uapi.state);
7162 const struct intel_crtc_state *old_crtc_state =
7163 intel_atomic_get_old_crtc_state(state, crtc);
7165 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
7168 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
7170 const struct drm_display_mode *pipe_mode =
7171 &crtc_state->hw.pipe_mode;
7174 if (!crtc_state->hw.enable)
7177 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
7178 pipe_mode->crtc_clock);
7180 return min(linetime_wm, 0x1ff);
7183 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
7184 const struct intel_cdclk_state *cdclk_state)
7186 const struct drm_display_mode *pipe_mode =
7187 &crtc_state->hw.pipe_mode;
7190 if (!crtc_state->hw.enable)
7193 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
7194 cdclk_state->logical.cdclk);
7196 return min(linetime_wm, 0x1ff);
7199 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
7201 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7202 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7203 const struct drm_display_mode *pipe_mode =
7204 &crtc_state->hw.pipe_mode;
7207 if (!crtc_state->hw.enable)
7210 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8,
7211 crtc_state->pixel_rate);
7213 /* Display WA #1135: BXT:ALL GLK:ALL */
7214 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
7215 dev_priv->ipc_enabled)
7218 return min(linetime_wm, 0x1ff);
7221 static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
7222 struct intel_crtc *crtc)
7224 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7225 struct intel_crtc_state *crtc_state =
7226 intel_atomic_get_new_crtc_state(state, crtc);
7227 const struct intel_cdclk_state *cdclk_state;
7229 if (DISPLAY_VER(dev_priv) >= 9)
7230 crtc_state->linetime = skl_linetime_wm(crtc_state);
7232 crtc_state->linetime = hsw_linetime_wm(crtc_state);
7234 if (!hsw_crtc_supports_ips(crtc))
7237 cdclk_state = intel_atomic_get_cdclk_state(state);
7238 if (IS_ERR(cdclk_state))
7239 return PTR_ERR(cdclk_state);
7241 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
7247 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
7248 struct intel_crtc *crtc)
7250 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7251 struct intel_crtc_state *crtc_state =
7252 intel_atomic_get_new_crtc_state(state, crtc);
7253 bool mode_changed = intel_crtc_needs_modeset(crtc_state);
7256 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) &&
7257 mode_changed && !crtc_state->hw.active)
7258 crtc_state->update_wm_post = true;
7260 if (mode_changed && crtc_state->hw.enable &&
7261 dev_priv->display.crtc_compute_clock &&
7262 !crtc_state->bigjoiner_slave &&
7263 !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
7264 ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
7270 * May need to update pipe gamma enable bits
7271 * when C8 planes are getting enabled/disabled.
7273 if (c8_planes_changed(crtc_state))
7274 crtc_state->uapi.color_mgmt_changed = true;
7276 if (mode_changed || crtc_state->update_pipe ||
7277 crtc_state->uapi.color_mgmt_changed) {
7278 ret = intel_color_check(crtc_state);
7283 if (dev_priv->display.compute_pipe_wm) {
7284 ret = dev_priv->display.compute_pipe_wm(crtc_state);
7286 drm_dbg_kms(&dev_priv->drm,
7287 "Target pipe watermarks are invalid\n");
7292 if (dev_priv->display.compute_intermediate_wm) {
7293 if (drm_WARN_ON(&dev_priv->drm,
7294 !dev_priv->display.compute_pipe_wm))
7298 * Calculate 'intermediate' watermarks that satisfy both the
7299 * old state and the new state. We can program these
7302 ret = dev_priv->display.compute_intermediate_wm(crtc_state);
7304 drm_dbg_kms(&dev_priv->drm,
7305 "No valid intermediate pipe watermarks are possible\n");
7310 if (DISPLAY_VER(dev_priv) >= 9) {
7311 if (mode_changed || crtc_state->update_pipe) {
7312 ret = skl_update_scaler_crtc(crtc_state);
7317 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state);
7322 if (HAS_IPS(dev_priv)) {
7323 ret = hsw_compute_ips_config(crtc_state);
7328 if (DISPLAY_VER(dev_priv) >= 9 ||
7329 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
7330 ret = hsw_compute_linetime_wm(state, crtc);
7336 if (!mode_changed) {
7337 ret = intel_psr2_sel_fetch_update(state, crtc);
7345 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
7347 struct intel_connector *connector;
7348 struct drm_connector_list_iter conn_iter;
7350 drm_connector_list_iter_begin(dev, &conn_iter);
7351 for_each_intel_connector_iter(connector, &conn_iter) {
7352 struct drm_connector_state *conn_state = connector->base.state;
7353 struct intel_encoder *encoder =
7354 to_intel_encoder(connector->base.encoder);
7356 if (conn_state->crtc)
7357 drm_connector_put(&connector->base);
7360 struct intel_crtc *crtc =
7361 to_intel_crtc(encoder->base.crtc);
7362 const struct intel_crtc_state *crtc_state =
7363 to_intel_crtc_state(crtc->base.state);
7365 conn_state->best_encoder = &encoder->base;
7366 conn_state->crtc = &crtc->base;
7367 conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3;
7369 drm_connector_get(&connector->base);
7371 conn_state->best_encoder = NULL;
7372 conn_state->crtc = NULL;
7375 drm_connector_list_iter_end(&conn_iter);
7379 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
7380 struct intel_crtc_state *pipe_config)
7382 struct drm_connector *connector = conn_state->connector;
7383 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
7384 const struct drm_display_info *info = &connector->display_info;
7387 switch (conn_state->max_bpc) {
7401 MISSING_CASE(conn_state->max_bpc);
7405 if (bpp < pipe_config->pipe_bpp) {
7406 drm_dbg_kms(&i915->drm,
7407 "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
7408 "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
7409 connector->base.id, connector->name,
7411 3 * conn_state->max_requested_bpc,
7412 pipe_config->pipe_bpp);
7414 pipe_config->pipe_bpp = bpp;
7421 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7422 struct intel_crtc_state *pipe_config)
7424 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7425 struct drm_atomic_state *state = pipe_config->uapi.state;
7426 struct drm_connector *connector;
7427 struct drm_connector_state *connector_state;
7430 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7431 IS_CHERRYVIEW(dev_priv)))
7433 else if (DISPLAY_VER(dev_priv) >= 5)
7438 pipe_config->pipe_bpp = bpp;
7440 /* Clamp display bpp to connector max bpp */
7441 for_each_new_connector_in_state(state, connector, connector_state, i) {
7444 if (connector_state->crtc != &crtc->base)
7447 ret = compute_sink_pipe_bpp(connector_state, pipe_config);
7455 static void intel_dump_crtc_timings(struct drm_i915_private *i915,
7456 const struct drm_display_mode *mode)
7458 drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, "
7459 "type: 0x%x flags: 0x%x\n",
7461 mode->crtc_hdisplay, mode->crtc_hsync_start,
7462 mode->crtc_hsync_end, mode->crtc_htotal,
7463 mode->crtc_vdisplay, mode->crtc_vsync_start,
7464 mode->crtc_vsync_end, mode->crtc_vtotal,
7465 mode->type, mode->flags);
7469 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
7470 const char *id, unsigned int lane_count,
7471 const struct intel_link_m_n *m_n)
7473 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
7475 drm_dbg_kms(&i915->drm,
7476 "%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7478 m_n->gmch_m, m_n->gmch_n,
7479 m_n->link_m, m_n->link_n, m_n->tu);
7483 intel_dump_infoframe(struct drm_i915_private *dev_priv,
7484 const union hdmi_infoframe *frame)
7486 if (!drm_debug_enabled(DRM_UT_KMS))
7489 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
7493 intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
7494 const struct drm_dp_vsc_sdp *vsc)
7496 if (!drm_debug_enabled(DRM_UT_KMS))
7499 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
7502 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
7504 static const char * const output_type_str[] = {
7505 OUTPUT_TYPE(UNUSED),
7506 OUTPUT_TYPE(ANALOG),
7516 OUTPUT_TYPE(DP_MST),
7521 static void snprintf_output_types(char *buf, size_t len,
7522 unsigned int output_types)
7529 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
7532 if ((output_types & BIT(i)) == 0)
7535 r = snprintf(str, len, "%s%s",
7536 str != buf ? "," : "", output_type_str[i]);
7542 output_types &= ~BIT(i);
7545 WARN_ON_ONCE(output_types != 0);
7548 static const char * const output_format_str[] = {
7549 [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
7550 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
7551 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
7554 static const char *output_formats(enum intel_output_format format)
7556 if (format >= ARRAY_SIZE(output_format_str))
7558 return output_format_str[format];
7561 static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
7563 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
7564 struct drm_i915_private *i915 = to_i915(plane->base.dev);
7565 const struct drm_framebuffer *fb = plane_state->hw.fb;
7568 drm_dbg_kms(&i915->drm,
7569 "[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
7570 plane->base.base.id, plane->base.name,
7571 yesno(plane_state->uapi.visible));
7575 drm_dbg_kms(&i915->drm,
7576 "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %p4cc modifier = 0x%llx, visible: %s\n",
7577 plane->base.base.id, plane->base.name,
7578 fb->base.id, fb->width, fb->height, &fb->format->format,
7579 fb->modifier, yesno(plane_state->uapi.visible));
7580 drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n",
7581 plane_state->hw.rotation, plane_state->scaler_id);
7582 if (plane_state->uapi.visible)
7583 drm_dbg_kms(&i915->drm,
7584 "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
7585 DRM_RECT_FP_ARG(&plane_state->uapi.src),
7586 DRM_RECT_ARG(&plane_state->uapi.dst));
7589 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
7590 struct intel_atomic_state *state,
7591 const char *context)
7593 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
7594 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7595 const struct intel_plane_state *plane_state;
7596 struct intel_plane *plane;
7600 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n",
7601 crtc->base.base.id, crtc->base.name,
7602 yesno(pipe_config->hw.enable), context);
7604 if (!pipe_config->hw.enable)
7607 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
7608 drm_dbg_kms(&dev_priv->drm,
7609 "active: %s, output_types: %s (0x%x), output format: %s\n",
7610 yesno(pipe_config->hw.active),
7611 buf, pipe_config->output_types,
7612 output_formats(pipe_config->output_format));
7614 drm_dbg_kms(&dev_priv->drm,
7615 "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
7616 transcoder_name(pipe_config->cpu_transcoder),
7617 pipe_config->pipe_bpp, pipe_config->dither);
7619 drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n",
7620 transcoder_name(pipe_config->mst_master_transcoder));
7622 drm_dbg_kms(&dev_priv->drm,
7623 "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n",
7624 transcoder_name(pipe_config->master_transcoder),
7625 pipe_config->sync_mode_slaves_mask);
7627 drm_dbg_kms(&dev_priv->drm, "bigjoiner: %s\n",
7628 pipe_config->bigjoiner_slave ? "slave" :
7629 pipe_config->bigjoiner ? "master" : "no");
7631 drm_dbg_kms(&dev_priv->drm, "splitter: %s, link count %d, overlap %d\n",
7632 enableddisabled(pipe_config->splitter.enable),
7633 pipe_config->splitter.link_count,
7634 pipe_config->splitter.pixel_overlap);
7636 if (pipe_config->has_pch_encoder)
7637 intel_dump_m_n_config(pipe_config, "fdi",
7638 pipe_config->fdi_lanes,
7639 &pipe_config->fdi_m_n);
7641 if (intel_crtc_has_dp_encoder(pipe_config)) {
7642 intel_dump_m_n_config(pipe_config, "dp m_n",
7643 pipe_config->lane_count, &pipe_config->dp_m_n);
7644 if (pipe_config->has_drrs)
7645 intel_dump_m_n_config(pipe_config, "dp m2_n2",
7646 pipe_config->lane_count,
7647 &pipe_config->dp_m2_n2);
7650 drm_dbg_kms(&dev_priv->drm,
7651 "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
7652 pipe_config->has_audio, pipe_config->has_infoframe,
7653 pipe_config->infoframes.enable);
7655 if (pipe_config->infoframes.enable &
7656 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
7657 drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n",
7658 pipe_config->infoframes.gcp);
7659 if (pipe_config->infoframes.enable &
7660 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
7661 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
7662 if (pipe_config->infoframes.enable &
7663 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
7664 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
7665 if (pipe_config->infoframes.enable &
7666 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
7667 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
7668 if (pipe_config->infoframes.enable &
7669 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
7670 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
7671 if (pipe_config->infoframes.enable &
7672 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
7673 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
7674 if (pipe_config->infoframes.enable &
7675 intel_hdmi_infoframe_enable(DP_SDP_VSC))
7676 intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
7678 drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
7679 yesno(pipe_config->vrr.enable),
7680 pipe_config->vrr.vmin, pipe_config->vrr.vmax,
7681 pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband,
7682 pipe_config->vrr.flipline,
7683 intel_vrr_vmin_vblank_start(pipe_config),
7684 intel_vrr_vmax_vblank_start(pipe_config));
7686 drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
7687 drm_mode_debug_printmodeline(&pipe_config->hw.mode);
7688 drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n");
7689 drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
7690 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode);
7691 drm_dbg_kms(&dev_priv->drm, "pipe mode:\n");
7692 drm_mode_debug_printmodeline(&pipe_config->hw.pipe_mode);
7693 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode);
7694 drm_dbg_kms(&dev_priv->drm,
7695 "port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
7696 pipe_config->port_clock,
7697 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
7698 pipe_config->pixel_rate);
7700 drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n",
7701 pipe_config->linetime, pipe_config->ips_linetime);
7703 if (DISPLAY_VER(dev_priv) >= 9)
7704 drm_dbg_kms(&dev_priv->drm,
7705 "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
7707 pipe_config->scaler_state.scaler_users,
7708 pipe_config->scaler_state.scaler_id);
7710 if (HAS_GMCH(dev_priv))
7711 drm_dbg_kms(&dev_priv->drm,
7712 "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7713 pipe_config->gmch_pfit.control,
7714 pipe_config->gmch_pfit.pgm_ratios,
7715 pipe_config->gmch_pfit.lvds_border_bits);
7717 drm_dbg_kms(&dev_priv->drm,
7718 "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
7719 DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
7720 enableddisabled(pipe_config->pch_pfit.enabled),
7721 yesno(pipe_config->pch_pfit.force_thru));
7723 drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i\n",
7724 pipe_config->ips_enabled, pipe_config->double_wide);
7726 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
7728 if (IS_CHERRYVIEW(dev_priv))
7729 drm_dbg_kms(&dev_priv->drm,
7730 "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
7731 pipe_config->cgm_mode, pipe_config->gamma_mode,
7732 pipe_config->gamma_enable, pipe_config->csc_enable);
7734 drm_dbg_kms(&dev_priv->drm,
7735 "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
7736 pipe_config->csc_mode, pipe_config->gamma_mode,
7737 pipe_config->gamma_enable, pipe_config->csc_enable);
7739 drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n",
7740 pipe_config->hw.degamma_lut ?
7741 drm_color_lut_size(pipe_config->hw.degamma_lut) : 0,
7742 pipe_config->hw.gamma_lut ?
7743 drm_color_lut_size(pipe_config->hw.gamma_lut) : 0);
7749 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
7750 if (plane->pipe == crtc->pipe)
7751 intel_dump_plane_state(plane_state);
7755 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
7757 struct drm_device *dev = state->base.dev;
7758 struct drm_connector *connector;
7759 struct drm_connector_list_iter conn_iter;
7760 unsigned int used_ports = 0;
7761 unsigned int used_mst_ports = 0;
7765 * We're going to peek into connector->state,
7766 * hence connection_mutex must be held.
7768 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
7771 * Walk the connector list instead of the encoder
7772 * list to detect the problem on ddi platforms
7773 * where there's just one encoder per digital port.
7775 drm_connector_list_iter_begin(dev, &conn_iter);
7776 drm_for_each_connector_iter(connector, &conn_iter) {
7777 struct drm_connector_state *connector_state;
7778 struct intel_encoder *encoder;
7781 drm_atomic_get_new_connector_state(&state->base,
7783 if (!connector_state)
7784 connector_state = connector->state;
7786 if (!connector_state->best_encoder)
7789 encoder = to_intel_encoder(connector_state->best_encoder);
7791 drm_WARN_ON(dev, !connector_state->crtc);
7793 switch (encoder->type) {
7794 case INTEL_OUTPUT_DDI:
7795 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev))))
7798 case INTEL_OUTPUT_DP:
7799 case INTEL_OUTPUT_HDMI:
7800 case INTEL_OUTPUT_EDP:
7801 /* the same port mustn't appear more than once */
7802 if (used_ports & BIT(encoder->port))
7805 used_ports |= BIT(encoder->port);
7807 case INTEL_OUTPUT_DP_MST:
7815 drm_connector_list_iter_end(&conn_iter);
7817 /* can't mix MST and SST/HDMI on the same port */
7818 if (used_ports & used_mst_ports)
7825 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
7826 struct intel_crtc_state *crtc_state)
7828 const struct intel_crtc_state *from_crtc_state = crtc_state;
7830 if (crtc_state->bigjoiner_slave) {
7831 from_crtc_state = intel_atomic_get_new_crtc_state(state,
7832 crtc_state->bigjoiner_linked_crtc);
7834 /* No need to copy state if the master state is unchanged */
7835 if (!from_crtc_state)
7839 intel_crtc_copy_color_blobs(crtc_state, from_crtc_state);
7843 intel_crtc_copy_uapi_to_hw_state(struct intel_atomic_state *state,
7844 struct intel_crtc_state *crtc_state)
7846 crtc_state->hw.enable = crtc_state->uapi.enable;
7847 crtc_state->hw.active = crtc_state->uapi.active;
7848 crtc_state->hw.mode = crtc_state->uapi.mode;
7849 crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
7850 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
7852 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc_state);
7855 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
7857 if (crtc_state->bigjoiner_slave)
7860 crtc_state->uapi.enable = crtc_state->hw.enable;
7861 crtc_state->uapi.active = crtc_state->hw.active;
7862 drm_WARN_ON(crtc_state->uapi.crtc->dev,
7863 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
7865 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
7866 crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter;
7868 /* copy color blobs to uapi */
7869 drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
7870 crtc_state->hw.degamma_lut);
7871 drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
7872 crtc_state->hw.gamma_lut);
7873 drm_property_replace_blob(&crtc_state->uapi.ctm,
7874 crtc_state->hw.ctm);
7878 copy_bigjoiner_crtc_state(struct intel_crtc_state *crtc_state,
7879 const struct intel_crtc_state *from_crtc_state)
7881 struct intel_crtc_state *saved_state;
7882 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7884 saved_state = kmemdup(from_crtc_state, sizeof(*saved_state), GFP_KERNEL);
7888 saved_state->uapi = crtc_state->uapi;
7889 saved_state->scaler_state = crtc_state->scaler_state;
7890 saved_state->shared_dpll = crtc_state->shared_dpll;
7891 saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
7892 saved_state->crc_enabled = crtc_state->crc_enabled;
7894 intel_crtc_free_hw_state(crtc_state);
7895 memcpy(crtc_state, saved_state, sizeof(*crtc_state));
7898 /* Re-init hw state */
7899 memset(&crtc_state->hw, 0, sizeof(saved_state->hw));
7900 crtc_state->hw.enable = from_crtc_state->hw.enable;
7901 crtc_state->hw.active = from_crtc_state->hw.active;
7902 crtc_state->hw.pipe_mode = from_crtc_state->hw.pipe_mode;
7903 crtc_state->hw.adjusted_mode = from_crtc_state->hw.adjusted_mode;
7906 crtc_state->uapi.mode_changed = from_crtc_state->uapi.mode_changed;
7907 crtc_state->uapi.connectors_changed = from_crtc_state->uapi.connectors_changed;
7908 crtc_state->uapi.active_changed = from_crtc_state->uapi.active_changed;
7909 crtc_state->nv12_planes = crtc_state->c8_planes = crtc_state->update_planes = 0;
7910 crtc_state->bigjoiner_linked_crtc = to_intel_crtc(from_crtc_state->uapi.crtc);
7911 crtc_state->bigjoiner_slave = true;
7912 crtc_state->cpu_transcoder = (enum transcoder)crtc->pipe;
7913 crtc_state->has_audio = false;
7919 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
7920 struct intel_crtc_state *crtc_state)
7922 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7923 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7924 struct intel_crtc_state *saved_state;
7926 saved_state = intel_crtc_state_alloc(crtc);
7930 /* free the old crtc_state->hw members */
7931 intel_crtc_free_hw_state(crtc_state);
7933 /* FIXME: before the switch to atomic started, a new pipe_config was
7934 * kzalloc'd. Code that depends on any field being zero should be
7935 * fixed, so that the crtc_state can be safely duplicated. For now,
7936 * only fields that are know to not cause problems are preserved. */
7938 saved_state->uapi = crtc_state->uapi;
7939 saved_state->scaler_state = crtc_state->scaler_state;
7940 saved_state->shared_dpll = crtc_state->shared_dpll;
7941 saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
7942 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
7943 sizeof(saved_state->icl_port_dplls));
7944 saved_state->crc_enabled = crtc_state->crc_enabled;
7945 if (IS_G4X(dev_priv) ||
7946 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7947 saved_state->wm = crtc_state->wm;
7949 memcpy(crtc_state, saved_state, sizeof(*crtc_state));
7952 intel_crtc_copy_uapi_to_hw_state(state, crtc_state);
7958 intel_modeset_pipe_config(struct intel_atomic_state *state,
7959 struct intel_crtc_state *pipe_config)
7961 struct drm_crtc *crtc = pipe_config->uapi.crtc;
7962 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
7963 struct drm_connector *connector;
7964 struct drm_connector_state *connector_state;
7965 int base_bpp, ret, i;
7968 pipe_config->cpu_transcoder =
7969 (enum transcoder) to_intel_crtc(crtc)->pipe;
7972 * Sanitize sync polarity flags based on requested ones. If neither
7973 * positive or negative polarity is requested, treat this as meaning
7974 * negative polarity.
7976 if (!(pipe_config->hw.adjusted_mode.flags &
7977 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
7978 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
7980 if (!(pipe_config->hw.adjusted_mode.flags &
7981 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
7982 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
7984 ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7989 base_bpp = pipe_config->pipe_bpp;
7992 * Determine the real pipe dimensions. Note that stereo modes can
7993 * increase the actual pipe size due to the frame doubling and
7994 * insertion of additional space for blanks between the frame. This
7995 * is stored in the crtc timings. We use the requested mode to do this
7996 * computation to clearly distinguish it from the adjusted mode, which
7997 * can be changed by the connectors in the below retry loop.
7999 drm_mode_get_hv_timing(&pipe_config->hw.mode,
8000 &pipe_config->pipe_src_w,
8001 &pipe_config->pipe_src_h);
8003 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
8004 struct intel_encoder *encoder =
8005 to_intel_encoder(connector_state->best_encoder);
8007 if (connector_state->crtc != crtc)
8010 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
8011 drm_dbg_kms(&i915->drm,
8012 "rejecting invalid cloning configuration\n");
8017 * Determine output_types before calling the .compute_config()
8018 * hooks so that the hooks can use this information safely.
8020 if (encoder->compute_output_type)
8021 pipe_config->output_types |=
8022 BIT(encoder->compute_output_type(encoder, pipe_config,
8025 pipe_config->output_types |= BIT(encoder->type);
8029 /* Ensure the port clock defaults are reset when retrying. */
8030 pipe_config->port_clock = 0;
8031 pipe_config->pixel_multiplier = 1;
8033 /* Fill in default crtc timings, allow encoders to overwrite them. */
8034 drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,
8035 CRTC_STEREO_DOUBLE);
8037 /* Pass our mode to the connectors and the CRTC to give them a chance to
8038 * adjust it according to limitations or connector properties, and also
8039 * a chance to reject the mode entirely.
8041 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
8042 struct intel_encoder *encoder =
8043 to_intel_encoder(connector_state->best_encoder);
8045 if (connector_state->crtc != crtc)
8048 ret = encoder->compute_config(encoder, pipe_config,
8051 if (ret != -EDEADLK)
8052 drm_dbg_kms(&i915->drm,
8053 "Encoder config failure: %d\n",
8059 /* Set default port clock if not overwritten by the encoder. Needs to be
8060 * done afterwards in case the encoder adjusts the mode. */
8061 if (!pipe_config->port_clock)
8062 pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
8063 * pipe_config->pixel_multiplier;
8065 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8066 if (ret == -EDEADLK)
8069 drm_dbg_kms(&i915->drm, "CRTC fixup failed\n");
8073 if (ret == I915_DISPLAY_CONFIG_RETRY) {
8074 if (drm_WARN(&i915->drm, !retry,
8075 "loop in pipe configuration computation\n"))
8078 drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n");
8083 /* Dithering seems to not pass-through bits correctly when it should, so
8084 * only enable it on 6bpc panels and when its not a compliance
8085 * test requesting 6bpc video pattern.
8087 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
8088 !pipe_config->dither_force_disable;
8089 drm_dbg_kms(&i915->drm,
8090 "hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
8091 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8097 intel_modeset_pipe_config_late(struct intel_crtc_state *crtc_state)
8099 struct intel_atomic_state *state =
8100 to_intel_atomic_state(crtc_state->uapi.state);
8101 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8102 struct drm_connector_state *conn_state;
8103 struct drm_connector *connector;
8106 for_each_new_connector_in_state(&state->base, connector,
8108 struct intel_encoder *encoder =
8109 to_intel_encoder(conn_state->best_encoder);
8112 if (conn_state->crtc != &crtc->base ||
8113 !encoder->compute_config_late)
8116 ret = encoder->compute_config_late(encoder, crtc_state,
8125 bool intel_fuzzy_clock_check(int clock1, int clock2)
8129 if (clock1 == clock2)
8132 if (!clock1 || !clock2)
8135 diff = abs(clock1 - clock2);
8137 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8144 intel_compare_m_n(unsigned int m, unsigned int n,
8145 unsigned int m2, unsigned int n2,
8148 if (m == m2 && n == n2)
8151 if (exact || !m || !n || !m2 || !n2)
8154 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
8161 } else if (n < n2) {
8171 return intel_fuzzy_clock_check(m, m2);
8175 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
8176 const struct intel_link_m_n *m2_n2,
8179 return m_n->tu == m2_n2->tu &&
8180 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
8181 m2_n2->gmch_m, m2_n2->gmch_n, exact) &&
8182 intel_compare_m_n(m_n->link_m, m_n->link_n,
8183 m2_n2->link_m, m2_n2->link_n, exact);
8187 intel_compare_infoframe(const union hdmi_infoframe *a,
8188 const union hdmi_infoframe *b)
8190 return memcmp(a, b, sizeof(*a)) == 0;
8194 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
8195 const struct drm_dp_vsc_sdp *b)
8197 return memcmp(a, b, sizeof(*a)) == 0;
8201 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
8202 bool fastset, const char *name,
8203 const union hdmi_infoframe *a,
8204 const union hdmi_infoframe *b)
8207 if (!drm_debug_enabled(DRM_UT_KMS))
8210 drm_dbg_kms(&dev_priv->drm,
8211 "fastset mismatch in %s infoframe\n", name);
8212 drm_dbg_kms(&dev_priv->drm, "expected:\n");
8213 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
8214 drm_dbg_kms(&dev_priv->drm, "found:\n");
8215 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
8217 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name);
8218 drm_err(&dev_priv->drm, "expected:\n");
8219 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
8220 drm_err(&dev_priv->drm, "found:\n");
8221 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
8226 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
8227 bool fastset, const char *name,
8228 const struct drm_dp_vsc_sdp *a,
8229 const struct drm_dp_vsc_sdp *b)
8232 if (!drm_debug_enabled(DRM_UT_KMS))
8235 drm_dbg_kms(&dev_priv->drm,
8236 "fastset mismatch in %s dp sdp\n", name);
8237 drm_dbg_kms(&dev_priv->drm, "expected:\n");
8238 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
8239 drm_dbg_kms(&dev_priv->drm, "found:\n");
8240 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
8242 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name);
8243 drm_err(&dev_priv->drm, "expected:\n");
8244 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
8245 drm_err(&dev_priv->drm, "found:\n");
8246 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
8250 static void __printf(4, 5)
8251 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
8252 const char *name, const char *format, ...)
8254 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
8255 struct va_format vaf;
8258 va_start(args, format);
8263 drm_dbg_kms(&i915->drm,
8264 "[CRTC:%d:%s] fastset mismatch in %s %pV\n",
8265 crtc->base.base.id, crtc->base.name, name, &vaf);
8267 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n",
8268 crtc->base.base.id, crtc->base.name, name, &vaf);
8273 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
8275 if (dev_priv->params.fastboot != -1)
8276 return dev_priv->params.fastboot;
8278 /* Enable fastboot by default on Skylake and newer */
8279 if (DISPLAY_VER(dev_priv) >= 9)
8282 /* Enable fastboot by default on VLV and CHV */
8283 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
8286 /* Disabled by default on all others */
8291 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
8292 const struct intel_crtc_state *pipe_config,
8295 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
8296 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
8299 bool fixup_inherited = fastset &&
8300 current_config->inherited && !pipe_config->inherited;
8302 if (fixup_inherited && !fastboot_enabled(dev_priv)) {
8303 drm_dbg_kms(&dev_priv->drm,
8304 "initial modeset and fastboot not set\n");
8308 #define PIPE_CONF_CHECK_X(name) do { \
8309 if (current_config->name != pipe_config->name) { \
8310 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8311 "(expected 0x%08x, found 0x%08x)", \
8312 current_config->name, \
8313 pipe_config->name); \
8318 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \
8319 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \
8320 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8321 "(expected 0x%08x, found 0x%08x)", \
8322 current_config->name & (mask), \
8323 pipe_config->name & (mask)); \
8328 #define PIPE_CONF_CHECK_I(name) do { \
8329 if (current_config->name != pipe_config->name) { \
8330 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8331 "(expected %i, found %i)", \
8332 current_config->name, \
8333 pipe_config->name); \
8338 #define PIPE_CONF_CHECK_BOOL(name) do { \
8339 if (current_config->name != pipe_config->name) { \
8340 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8341 "(expected %s, found %s)", \
8342 yesno(current_config->name), \
8343 yesno(pipe_config->name)); \
8349 * Checks state where we only read out the enabling, but not the entire
8350 * state itself (like full infoframes or ELD for audio). These states
8351 * require a full modeset on bootup to fix up.
8353 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
8354 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
8355 PIPE_CONF_CHECK_BOOL(name); \
8357 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8358 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
8359 yesno(current_config->name), \
8360 yesno(pipe_config->name)); \
8365 #define PIPE_CONF_CHECK_P(name) do { \
8366 if (current_config->name != pipe_config->name) { \
8367 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8368 "(expected %p, found %p)", \
8369 current_config->name, \
8370 pipe_config->name); \
8375 #define PIPE_CONF_CHECK_M_N(name) do { \
8376 if (!intel_compare_link_m_n(¤t_config->name, \
8377 &pipe_config->name,\
8379 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8380 "(expected tu %i gmch %i/%i link %i/%i, " \
8381 "found tu %i, gmch %i/%i link %i/%i)", \
8382 current_config->name.tu, \
8383 current_config->name.gmch_m, \
8384 current_config->name.gmch_n, \
8385 current_config->name.link_m, \
8386 current_config->name.link_n, \
8387 pipe_config->name.tu, \
8388 pipe_config->name.gmch_m, \
8389 pipe_config->name.gmch_n, \
8390 pipe_config->name.link_m, \
8391 pipe_config->name.link_n); \
8396 /* This is required for BDW+ where there is only one set of registers for
8397 * switching between high and low RR.
8398 * This macro can be used whenever a comparison has to be made between one
8399 * hw state and multiple sw state variables.
8401 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
8402 if (!intel_compare_link_m_n(¤t_config->name, \
8403 &pipe_config->name, !fastset) && \
8404 !intel_compare_link_m_n(¤t_config->alt_name, \
8405 &pipe_config->name, !fastset)) { \
8406 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8407 "(expected tu %i gmch %i/%i link %i/%i, " \
8408 "or tu %i gmch %i/%i link %i/%i, " \
8409 "found tu %i, gmch %i/%i link %i/%i)", \
8410 current_config->name.tu, \
8411 current_config->name.gmch_m, \
8412 current_config->name.gmch_n, \
8413 current_config->name.link_m, \
8414 current_config->name.link_n, \
8415 current_config->alt_name.tu, \
8416 current_config->alt_name.gmch_m, \
8417 current_config->alt_name.gmch_n, \
8418 current_config->alt_name.link_m, \
8419 current_config->alt_name.link_n, \
8420 pipe_config->name.tu, \
8421 pipe_config->name.gmch_m, \
8422 pipe_config->name.gmch_n, \
8423 pipe_config->name.link_m, \
8424 pipe_config->name.link_n); \
8429 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
8430 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8431 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8432 "(%x) (expected %i, found %i)", \
8434 current_config->name & (mask), \
8435 pipe_config->name & (mask)); \
8440 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
8441 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8442 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8443 "(expected %i, found %i)", \
8444 current_config->name, \
8445 pipe_config->name); \
8450 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
8451 if (!intel_compare_infoframe(¤t_config->infoframes.name, \
8452 &pipe_config->infoframes.name)) { \
8453 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
8454 ¤t_config->infoframes.name, \
8455 &pipe_config->infoframes.name); \
8460 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
8461 if (!current_config->has_psr && !pipe_config->has_psr && \
8462 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \
8463 &pipe_config->infoframes.name)) { \
8464 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
8465 ¤t_config->infoframes.name, \
8466 &pipe_config->infoframes.name); \
8471 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
8472 if (current_config->name1 != pipe_config->name1) { \
8473 pipe_config_mismatch(fastset, crtc, __stringify(name1), \
8474 "(expected %i, found %i, won't compare lut values)", \
8475 current_config->name1, \
8476 pipe_config->name1); \
8479 if (!intel_color_lut_equal(current_config->name2, \
8480 pipe_config->name2, pipe_config->name1, \
8482 pipe_config_mismatch(fastset, crtc, __stringify(name2), \
8483 "hw_state doesn't match sw_state"); \
8489 #define PIPE_CONF_QUIRK(quirk) \
8490 ((current_config->quirks | pipe_config->quirks) & (quirk))
8492 PIPE_CONF_CHECK_I(cpu_transcoder);
8494 PIPE_CONF_CHECK_BOOL(has_pch_encoder);
8495 PIPE_CONF_CHECK_I(fdi_lanes);
8496 PIPE_CONF_CHECK_M_N(fdi_m_n);
8498 PIPE_CONF_CHECK_I(lane_count);
8499 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
8501 if (DISPLAY_VER(dev_priv) < 8) {
8502 PIPE_CONF_CHECK_M_N(dp_m_n);
8504 if (current_config->has_drrs)
8505 PIPE_CONF_CHECK_M_N(dp_m2_n2);
8507 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
8509 PIPE_CONF_CHECK_X(output_types);
8511 /* FIXME do the readout properly and get rid of this quirk */
8512 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
8513 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
8514 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal);
8515 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_start);
8516 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_end);
8517 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_start);
8518 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_end);
8520 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vdisplay);
8521 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vtotal);
8522 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_start);
8523 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_end);
8524 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_start);
8525 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_end);
8527 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
8528 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
8529 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
8530 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
8531 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
8532 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
8534 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
8535 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
8536 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
8537 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
8538 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
8539 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
8541 PIPE_CONF_CHECK_I(pixel_multiplier);
8543 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
8544 DRM_MODE_FLAG_INTERLACE);
8546 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8547 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
8548 DRM_MODE_FLAG_PHSYNC);
8549 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
8550 DRM_MODE_FLAG_NHSYNC);
8551 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
8552 DRM_MODE_FLAG_PVSYNC);
8553 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
8554 DRM_MODE_FLAG_NVSYNC);
8558 PIPE_CONF_CHECK_I(output_format);
8559 PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
8560 if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
8561 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
8562 PIPE_CONF_CHECK_BOOL(limited_color_range);
8564 PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
8565 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
8566 PIPE_CONF_CHECK_BOOL(has_infoframe);
8567 /* FIXME do the readout properly and get rid of this quirk */
8568 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE))
8569 PIPE_CONF_CHECK_BOOL(fec_enable);
8571 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
8573 PIPE_CONF_CHECK_X(gmch_pfit.control);
8574 /* pfit ratios are autocomputed by the hw on gen4+ */
8575 if (DISPLAY_VER(dev_priv) < 4)
8576 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
8577 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
8580 * Changing the EDP transcoder input mux
8581 * (A_ONOFF vs. A_ON) requires a full modeset.
8583 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
8586 PIPE_CONF_CHECK_I(pipe_src_w);
8587 PIPE_CONF_CHECK_I(pipe_src_h);
8589 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
8590 if (current_config->pch_pfit.enabled) {
8591 PIPE_CONF_CHECK_I(pch_pfit.dst.x1);
8592 PIPE_CONF_CHECK_I(pch_pfit.dst.y1);
8593 PIPE_CONF_CHECK_I(pch_pfit.dst.x2);
8594 PIPE_CONF_CHECK_I(pch_pfit.dst.y2);
8597 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
8598 /* FIXME do the readout properly and get rid of this quirk */
8599 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE))
8600 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
8602 PIPE_CONF_CHECK_X(gamma_mode);
8603 if (IS_CHERRYVIEW(dev_priv))
8604 PIPE_CONF_CHECK_X(cgm_mode);
8606 PIPE_CONF_CHECK_X(csc_mode);
8607 PIPE_CONF_CHECK_BOOL(gamma_enable);
8608 PIPE_CONF_CHECK_BOOL(csc_enable);
8610 PIPE_CONF_CHECK_I(linetime);
8611 PIPE_CONF_CHECK_I(ips_linetime);
8613 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
8615 PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
8617 PIPE_CONF_CHECK_BOOL(has_psr);
8618 PIPE_CONF_CHECK_BOOL(has_psr2);
8619 PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
8620 PIPE_CONF_CHECK_I(dc3co_exitline);
8623 PIPE_CONF_CHECK_BOOL(double_wide);
8625 PIPE_CONF_CHECK_P(shared_dpll);
8627 /* FIXME do the readout properly and get rid of this quirk */
8628 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
8629 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8630 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8631 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8632 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8633 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
8634 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
8635 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
8636 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
8637 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
8638 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
8639 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
8640 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
8641 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
8642 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
8643 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
8644 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
8645 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
8646 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
8647 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
8648 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
8649 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
8650 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
8651 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
8652 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
8653 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
8654 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
8655 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
8656 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
8657 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
8658 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
8659 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
8661 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
8662 PIPE_CONF_CHECK_X(dsi_pll.div);
8664 if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
8665 PIPE_CONF_CHECK_I(pipe_bpp);
8667 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock);
8668 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
8669 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8671 PIPE_CONF_CHECK_I(min_voltage_level);
8674 if (fastset && (current_config->has_psr || pipe_config->has_psr))
8675 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable,
8676 ~intel_hdmi_infoframe_enable(DP_SDP_VSC));
8678 PIPE_CONF_CHECK_X(infoframes.enable);
8680 PIPE_CONF_CHECK_X(infoframes.gcp);
8681 PIPE_CONF_CHECK_INFOFRAME(avi);
8682 PIPE_CONF_CHECK_INFOFRAME(spd);
8683 PIPE_CONF_CHECK_INFOFRAME(hdmi);
8684 PIPE_CONF_CHECK_INFOFRAME(drm);
8685 PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
8687 PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
8688 PIPE_CONF_CHECK_I(master_transcoder);
8689 PIPE_CONF_CHECK_BOOL(bigjoiner);
8690 PIPE_CONF_CHECK_BOOL(bigjoiner_slave);
8691 PIPE_CONF_CHECK_P(bigjoiner_linked_crtc);
8693 PIPE_CONF_CHECK_I(dsc.compression_enable);
8694 PIPE_CONF_CHECK_I(dsc.dsc_split);
8695 PIPE_CONF_CHECK_I(dsc.compressed_bpp);
8697 PIPE_CONF_CHECK_BOOL(splitter.enable);
8698 PIPE_CONF_CHECK_I(splitter.link_count);
8699 PIPE_CONF_CHECK_I(splitter.pixel_overlap);
8701 PIPE_CONF_CHECK_I(mst_master_transcoder);
8703 PIPE_CONF_CHECK_BOOL(vrr.enable);
8704 PIPE_CONF_CHECK_I(vrr.vmin);
8705 PIPE_CONF_CHECK_I(vrr.vmax);
8706 PIPE_CONF_CHECK_I(vrr.flipline);
8707 PIPE_CONF_CHECK_I(vrr.pipeline_full);
8708 PIPE_CONF_CHECK_I(vrr.guardband);
8710 #undef PIPE_CONF_CHECK_X
8711 #undef PIPE_CONF_CHECK_I
8712 #undef PIPE_CONF_CHECK_BOOL
8713 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
8714 #undef PIPE_CONF_CHECK_P
8715 #undef PIPE_CONF_CHECK_FLAGS
8716 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
8717 #undef PIPE_CONF_CHECK_COLOR_LUT
8718 #undef PIPE_CONF_QUIRK
8723 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
8724 const struct intel_crtc_state *pipe_config)
8726 if (pipe_config->has_pch_encoder) {
8727 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
8728 &pipe_config->fdi_m_n);
8729 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
8732 * FDI already provided one idea for the dotclock.
8733 * Yell if the encoder disagrees.
8735 drm_WARN(&dev_priv->drm,
8736 !intel_fuzzy_clock_check(fdi_dotclock, dotclock),
8737 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
8738 fdi_dotclock, dotclock);
8742 static void verify_wm_state(struct intel_crtc *crtc,
8743 struct intel_crtc_state *new_crtc_state)
8745 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8746 struct skl_hw_state {
8747 struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
8748 struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
8749 struct skl_pipe_wm wm;
8751 const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal;
8752 int level, max_level = ilk_wm_max_level(dev_priv);
8753 struct intel_plane *plane;
8754 u8 hw_enabled_slices;
8756 if (DISPLAY_VER(dev_priv) < 9 || !new_crtc_state->hw.active)
8759 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
8763 skl_pipe_wm_get_hw_state(crtc, &hw->wm);
8765 skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
8767 hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
8769 if (DISPLAY_VER(dev_priv) >= 11 &&
8770 hw_enabled_slices != dev_priv->dbuf.enabled_slices)
8771 drm_err(&dev_priv->drm,
8772 "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n",
8773 dev_priv->dbuf.enabled_slices,
8776 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
8777 const struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
8778 const struct skl_wm_level *hw_wm_level, *sw_wm_level;
8781 for (level = 0; level <= max_level; level++) {
8782 hw_wm_level = &hw->wm.planes[plane->id].wm[level];
8783 sw_wm_level = skl_plane_wm_level(sw_wm, plane->id, level);
8785 if (skl_wm_level_equals(hw_wm_level, sw_wm_level))
8788 drm_err(&dev_priv->drm,
8789 "[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
8790 plane->base.base.id, plane->base.name, level,
8791 sw_wm_level->enable,
8792 sw_wm_level->blocks,
8794 hw_wm_level->enable,
8795 hw_wm_level->blocks,
8796 hw_wm_level->lines);
8799 hw_wm_level = &hw->wm.planes[plane->id].trans_wm;
8800 sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id);
8802 if (!skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
8803 drm_err(&dev_priv->drm,
8804 "[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
8805 plane->base.base.id, plane->base.name,
8806 sw_wm_level->enable,
8807 sw_wm_level->blocks,
8809 hw_wm_level->enable,
8810 hw_wm_level->blocks,
8811 hw_wm_level->lines);
8814 hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0;
8815 sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0;
8817 if (HAS_HW_SAGV_WM(dev_priv) &&
8818 !skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
8819 drm_err(&dev_priv->drm,
8820 "[PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
8821 plane->base.base.id, plane->base.name,
8822 sw_wm_level->enable,
8823 sw_wm_level->blocks,
8825 hw_wm_level->enable,
8826 hw_wm_level->blocks,
8827 hw_wm_level->lines);
8830 hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm;
8831 sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm;
8833 if (HAS_HW_SAGV_WM(dev_priv) &&
8834 !skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
8835 drm_err(&dev_priv->drm,
8836 "[PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
8837 plane->base.base.id, plane->base.name,
8838 sw_wm_level->enable,
8839 sw_wm_level->blocks,
8841 hw_wm_level->enable,
8842 hw_wm_level->blocks,
8843 hw_wm_level->lines);
8847 hw_ddb_entry = &hw->ddb_y[plane->id];
8848 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane->id];
8850 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
8851 drm_err(&dev_priv->drm,
8852 "[PLANE:%d:%s] mismatch in DDB (expected (%u,%u), found (%u,%u))\n",
8853 plane->base.base.id, plane->base.name,
8854 sw_ddb_entry->start, sw_ddb_entry->end,
8855 hw_ddb_entry->start, hw_ddb_entry->end);
8863 verify_connector_state(struct intel_atomic_state *state,
8864 struct intel_crtc *crtc)
8866 struct drm_connector *connector;
8867 struct drm_connector_state *new_conn_state;
8870 for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) {
8871 struct drm_encoder *encoder = connector->encoder;
8872 struct intel_crtc_state *crtc_state = NULL;
8874 if (new_conn_state->crtc != &crtc->base)
8878 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
8880 intel_connector_verify_state(crtc_state, new_conn_state);
8882 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
8883 "connector's atomic encoder doesn't match legacy encoder\n");
8888 verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state)
8890 struct intel_encoder *encoder;
8891 struct drm_connector *connector;
8892 struct drm_connector_state *old_conn_state, *new_conn_state;
8895 for_each_intel_encoder(&dev_priv->drm, encoder) {
8896 bool enabled = false, found = false;
8899 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n",
8900 encoder->base.base.id,
8901 encoder->base.name);
8903 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,
8904 new_conn_state, i) {
8905 if (old_conn_state->best_encoder == &encoder->base)
8908 if (new_conn_state->best_encoder != &encoder->base)
8910 found = enabled = true;
8912 I915_STATE_WARN(new_conn_state->crtc !=
8914 "connector's crtc doesn't match encoder crtc\n");
8920 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8921 "encoder's enabled state mismatch "
8922 "(expected %i, found %i)\n",
8923 !!encoder->base.crtc, enabled);
8925 if (!encoder->base.crtc) {
8928 active = encoder->get_hw_state(encoder, &pipe);
8929 I915_STATE_WARN(active,
8930 "encoder detached but still enabled on pipe %c.\n",
8937 verify_crtc_state(struct intel_crtc *crtc,
8938 struct intel_crtc_state *old_crtc_state,
8939 struct intel_crtc_state *new_crtc_state)
8941 struct drm_device *dev = crtc->base.dev;
8942 struct drm_i915_private *dev_priv = to_i915(dev);
8943 struct intel_encoder *encoder;
8944 struct intel_crtc_state *pipe_config = old_crtc_state;
8945 struct drm_atomic_state *state = old_crtc_state->uapi.state;
8946 struct intel_crtc *master = crtc;
8948 __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
8949 intel_crtc_free_hw_state(old_crtc_state);
8950 intel_crtc_state_reset(old_crtc_state, crtc);
8951 old_crtc_state->uapi.state = state;
8953 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id,
8956 pipe_config->hw.enable = new_crtc_state->hw.enable;
8958 intel_crtc_get_pipe_config(pipe_config);
8960 /* we keep both pipes enabled on 830 */
8961 if (IS_I830(dev_priv) && pipe_config->hw.active)
8962 pipe_config->hw.active = new_crtc_state->hw.active;
8964 I915_STATE_WARN(new_crtc_state->hw.active != pipe_config->hw.active,
8965 "crtc active state doesn't match with hw state "
8966 "(expected %i, found %i)\n",
8967 new_crtc_state->hw.active, pipe_config->hw.active);
8969 I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,
8970 "transitional active state does not match atomic hw state "
8971 "(expected %i, found %i)\n",
8972 new_crtc_state->hw.active, crtc->active);
8974 if (new_crtc_state->bigjoiner_slave)
8975 master = new_crtc_state->bigjoiner_linked_crtc;
8977 for_each_encoder_on_crtc(dev, &master->base, encoder) {
8981 active = encoder->get_hw_state(encoder, &pipe);
8982 I915_STATE_WARN(active != new_crtc_state->hw.active,
8983 "[ENCODER:%i] active %i with crtc active %i\n",
8984 encoder->base.base.id, active,
8985 new_crtc_state->hw.active);
8987 I915_STATE_WARN(active && master->pipe != pipe,
8988 "Encoder connected to wrong pipe %c\n",
8992 intel_encoder_get_config(encoder, pipe_config);
8995 if (!new_crtc_state->hw.active)
8998 intel_pipe_config_sanity_check(dev_priv, pipe_config);
9000 if (!intel_pipe_config_compare(new_crtc_state,
9001 pipe_config, false)) {
9002 I915_STATE_WARN(1, "pipe state doesn't match!\n");
9003 intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
9004 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
9009 intel_verify_planes(struct intel_atomic_state *state)
9011 struct intel_plane *plane;
9012 const struct intel_plane_state *plane_state;
9015 for_each_new_intel_plane_in_state(state, plane,
9017 assert_plane(plane, plane_state->planar_slave ||
9018 plane_state->uapi.visible);
9022 verify_single_dpll_state(struct drm_i915_private *dev_priv,
9023 struct intel_shared_dpll *pll,
9024 struct intel_crtc *crtc,
9025 struct intel_crtc_state *new_crtc_state)
9027 struct intel_dpll_hw_state dpll_hw_state;
9031 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9033 drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name);
9035 active = intel_dpll_get_hw_state(dev_priv, pll, &dpll_hw_state);
9037 if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
9038 I915_STATE_WARN(!pll->on && pll->active_mask,
9039 "pll in active use but not on in sw tracking\n");
9040 I915_STATE_WARN(pll->on && !pll->active_mask,
9041 "pll is on but not used by any active pipe\n");
9042 I915_STATE_WARN(pll->on != active,
9043 "pll on state mismatch (expected %i, found %i)\n",
9048 I915_STATE_WARN(pll->active_mask & ~pll->state.pipe_mask,
9049 "more active pll users than references: 0x%x vs 0x%x\n",
9050 pll->active_mask, pll->state.pipe_mask);
9055 pipe_mask = BIT(crtc->pipe);
9057 if (new_crtc_state->hw.active)
9058 I915_STATE_WARN(!(pll->active_mask & pipe_mask),
9059 "pll active mismatch (expected pipe %c in active mask 0x%x)\n",
9060 pipe_name(crtc->pipe), pll->active_mask);
9062 I915_STATE_WARN(pll->active_mask & pipe_mask,
9063 "pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n",
9064 pipe_name(crtc->pipe), pll->active_mask);
9066 I915_STATE_WARN(!(pll->state.pipe_mask & pipe_mask),
9067 "pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n",
9068 pipe_mask, pll->state.pipe_mask);
9070 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
9072 sizeof(dpll_hw_state)),
9073 "pll hw state mismatch\n");
9077 verify_shared_dpll_state(struct intel_crtc *crtc,
9078 struct intel_crtc_state *old_crtc_state,
9079 struct intel_crtc_state *new_crtc_state)
9081 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9083 if (new_crtc_state->shared_dpll)
9084 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state);
9086 if (old_crtc_state->shared_dpll &&
9087 old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
9088 u8 pipe_mask = BIT(crtc->pipe);
9089 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
9091 I915_STATE_WARN(pll->active_mask & pipe_mask,
9092 "pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",
9093 pipe_name(crtc->pipe), pll->active_mask);
9094 I915_STATE_WARN(pll->state.pipe_mask & pipe_mask,
9095 "pll enabled crtcs mismatch (found %x in enabled mask (0x%x))\n",
9096 pipe_name(crtc->pipe), pll->state.pipe_mask);
9101 intel_modeset_verify_crtc(struct intel_crtc *crtc,
9102 struct intel_atomic_state *state,
9103 struct intel_crtc_state *old_crtc_state,
9104 struct intel_crtc_state *new_crtc_state)
9106 if (!intel_crtc_needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
9109 verify_wm_state(crtc, new_crtc_state);
9110 verify_connector_state(state, crtc);
9111 verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
9112 verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
9116 verify_disabled_dpll_state(struct drm_i915_private *dev_priv)
9120 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++)
9121 verify_single_dpll_state(dev_priv,
9122 &dev_priv->dpll.shared_dplls[i],
9127 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
9128 struct intel_atomic_state *state)
9130 verify_encoder_state(dev_priv, state);
9131 verify_connector_state(state, NULL);
9132 verify_disabled_dpll_state(dev_priv);
9135 int intel_modeset_all_pipes(struct intel_atomic_state *state)
9137 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
9138 struct intel_crtc *crtc;
9141 * Add all pipes to the state, and force
9142 * a modeset on all the active ones.
9144 for_each_intel_crtc(&dev_priv->drm, crtc) {
9145 struct intel_crtc_state *crtc_state;
9148 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
9149 if (IS_ERR(crtc_state))
9150 return PTR_ERR(crtc_state);
9152 if (!crtc_state->hw.active ||
9153 drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
9156 crtc_state->uapi.mode_changed = true;
9158 ret = drm_atomic_add_affected_connectors(&state->base,
9163 ret = intel_atomic_add_affected_planes(state, crtc);
9167 crtc_state->update_planes |= crtc_state->active_planes;
9174 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
9176 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9177 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9178 struct drm_display_mode adjusted_mode =
9179 crtc_state->hw.adjusted_mode;
9181 if (crtc_state->vrr.enable) {
9182 adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax;
9183 adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax;
9184 adjusted_mode.crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
9185 crtc->vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
9188 drm_calc_timestamping_constants(&crtc->base, &adjusted_mode);
9190 crtc->mode_flags = crtc_state->mode_flags;
9193 * The scanline counter increments at the leading edge of hsync.
9195 * On most platforms it starts counting from vtotal-1 on the
9196 * first active line. That means the scanline counter value is
9197 * always one less than what we would expect. Ie. just after
9198 * start of vblank, which also occurs at start of hsync (on the
9199 * last active line), the scanline counter will read vblank_start-1.
9201 * On gen2 the scanline counter starts counting from 1 instead
9202 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
9203 * to keep the value positive), instead of adding one.
9205 * On HSW+ the behaviour of the scanline counter depends on the output
9206 * type. For DP ports it behaves like most other platforms, but on HDMI
9207 * there's an extra 1 line difference. So we need to add two instead of
9210 * On VLV/CHV DSI the scanline counter would appear to increment
9211 * approx. 1/3 of a scanline before start of vblank. Unfortunately
9212 * that means we can't tell whether we're in vblank or not while
9213 * we're on that particular line. We must still set scanline_offset
9214 * to 1 so that the vblank timestamps come out correct when we query
9215 * the scanline counter from within the vblank interrupt handler.
9216 * However if queried just before the start of vblank we'll get an
9217 * answer that's slightly in the future.
9219 if (DISPLAY_VER(dev_priv) == 2) {
9222 vtotal = adjusted_mode.crtc_vtotal;
9223 if (adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9226 crtc->scanline_offset = vtotal - 1;
9227 } else if (HAS_DDI(dev_priv) &&
9228 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
9229 crtc->scanline_offset = 2;
9231 crtc->scanline_offset = 1;
9235 static void intel_modeset_clear_plls(struct intel_atomic_state *state)
9237 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
9238 struct intel_crtc_state *new_crtc_state;
9239 struct intel_crtc *crtc;
9242 if (!dev_priv->display.crtc_compute_clock)
9245 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
9246 if (!intel_crtc_needs_modeset(new_crtc_state))
9249 intel_release_shared_dplls(state, crtc);
9254 * This implements the workaround described in the "notes" section of the mode
9255 * set sequence documentation. When going from no pipes or single pipe to
9256 * multiple pipes, and planes are enabled after the pipe, we need to wait at
9257 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
9259 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
9261 struct intel_crtc_state *crtc_state;
9262 struct intel_crtc *crtc;
9263 struct intel_crtc_state *first_crtc_state = NULL;
9264 struct intel_crtc_state *other_crtc_state = NULL;
9265 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
9268 /* look at all crtc's that are going to be enabled in during modeset */
9269 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
9270 if (!crtc_state->hw.active ||
9271 !intel_crtc_needs_modeset(crtc_state))
9274 if (first_crtc_state) {
9275 other_crtc_state = crtc_state;
9278 first_crtc_state = crtc_state;
9279 first_pipe = crtc->pipe;
9283 /* No workaround needed? */
9284 if (!first_crtc_state)
9287 /* w/a possibly needed, check how many crtc's are already enabled. */
9288 for_each_intel_crtc(state->base.dev, crtc) {
9289 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
9290 if (IS_ERR(crtc_state))
9291 return PTR_ERR(crtc_state);
9293 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
9295 if (!crtc_state->hw.active ||
9296 intel_crtc_needs_modeset(crtc_state))
9299 /* 2 or more enabled crtcs means no need for w/a */
9300 if (enabled_pipe != INVALID_PIPE)
9303 enabled_pipe = crtc->pipe;
9306 if (enabled_pipe != INVALID_PIPE)
9307 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
9308 else if (other_crtc_state)
9309 other_crtc_state->hsw_workaround_pipe = first_pipe;
9314 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
9317 const struct intel_crtc_state *crtc_state;
9318 struct intel_crtc *crtc;
9321 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
9322 if (crtc_state->hw.active)
9323 active_pipes |= BIT(crtc->pipe);
9325 active_pipes &= ~BIT(crtc->pipe);
9328 return active_pipes;
9331 static int intel_modeset_checks(struct intel_atomic_state *state)
9333 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
9335 state->modeset = true;
9337 if (IS_HASWELL(dev_priv))
9338 return hsw_mode_set_planes_workaround(state);
9344 * Handle calculation of various watermark data at the end of the atomic check
9345 * phase. The code here should be run after the per-crtc and per-plane 'check'
9346 * handlers to ensure that all derived state has been updated.
9348 static int calc_watermark_data(struct intel_atomic_state *state)
9350 struct drm_device *dev = state->base.dev;
9351 struct drm_i915_private *dev_priv = to_i915(dev);
9353 /* Is there platform-specific watermark information to calculate? */
9354 if (dev_priv->display.compute_global_watermarks)
9355 return dev_priv->display.compute_global_watermarks(state);
9360 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
9361 struct intel_crtc_state *new_crtc_state)
9363 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
9366 new_crtc_state->uapi.mode_changed = false;
9367 new_crtc_state->update_pipe = true;
9370 static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state,
9371 struct intel_crtc_state *new_crtc_state)
9374 * If we're not doing the full modeset we want to
9375 * keep the current M/N values as they may be
9376 * sufficiently different to the computed values
9377 * to cause problems.
9379 * FIXME: should really copy more fuzzy state here
9381 new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n;
9382 new_crtc_state->dp_m_n = old_crtc_state->dp_m_n;
9383 new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
9384 new_crtc_state->has_drrs = old_crtc_state->has_drrs;
9387 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
9388 struct intel_crtc *crtc,
9391 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
9392 struct intel_plane *plane;
9394 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
9395 struct intel_plane_state *plane_state;
9397 if ((plane_ids_mask & BIT(plane->id)) == 0)
9400 plane_state = intel_atomic_get_plane_state(state, plane);
9401 if (IS_ERR(plane_state))
9402 return PTR_ERR(plane_state);
9408 int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
9409 struct intel_crtc *crtc)
9411 const struct intel_crtc_state *old_crtc_state =
9412 intel_atomic_get_old_crtc_state(state, crtc);
9413 const struct intel_crtc_state *new_crtc_state =
9414 intel_atomic_get_new_crtc_state(state, crtc);
9416 return intel_crtc_add_planes_to_state(state, crtc,
9417 old_crtc_state->enabled_planes |
9418 new_crtc_state->enabled_planes);
9421 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
9423 /* See {hsw,vlv,ivb}_plane_ratio() */
9424 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
9425 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
9426 IS_IVYBRIDGE(dev_priv);
9429 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state,
9430 struct intel_crtc *crtc,
9431 struct intel_crtc *other)
9433 const struct intel_plane_state *plane_state;
9434 struct intel_plane *plane;
9438 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
9439 if (plane->pipe == crtc->pipe)
9440 plane_ids |= BIT(plane->id);
9443 return intel_crtc_add_planes_to_state(state, other, plane_ids);
9446 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state)
9448 const struct intel_crtc_state *crtc_state;
9449 struct intel_crtc *crtc;
9452 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
9455 if (!crtc_state->bigjoiner)
9458 ret = intel_crtc_add_bigjoiner_planes(state, crtc,
9459 crtc_state->bigjoiner_linked_crtc);
9467 static int intel_atomic_check_planes(struct intel_atomic_state *state)
9469 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
9470 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
9471 struct intel_plane_state *plane_state;
9472 struct intel_plane *plane;
9473 struct intel_crtc *crtc;
9476 ret = icl_add_linked_planes(state);
9480 ret = intel_bigjoiner_add_affected_planes(state);
9484 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
9485 ret = intel_plane_atomic_check(state, plane);
9487 drm_dbg_atomic(&dev_priv->drm,
9488 "[PLANE:%d:%s] atomic driver check failed\n",
9489 plane->base.base.id, plane->base.name);
9494 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
9495 new_crtc_state, i) {
9496 u8 old_active_planes, new_active_planes;
9498 ret = icl_check_nv12_planes(new_crtc_state);
9503 * On some platforms the number of active planes affects
9504 * the planes' minimum cdclk calculation. Add such planes
9505 * to the state before we compute the minimum cdclk.
9507 if (!active_planes_affects_min_cdclk(dev_priv))
9510 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
9511 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
9513 if (hweight8(old_active_planes) == hweight8(new_active_planes))
9516 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
9524 static int intel_atomic_check_cdclk(struct intel_atomic_state *state,
9525 bool *need_cdclk_calc)
9527 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
9528 const struct intel_cdclk_state *old_cdclk_state;
9529 const struct intel_cdclk_state *new_cdclk_state;
9530 struct intel_plane_state *plane_state;
9531 struct intel_bw_state *new_bw_state;
9532 struct intel_plane *plane;
9538 * active_planes bitmask has been updated, and potentially
9539 * affected planes are part of the state. We can now
9540 * compute the minimum cdclk for each plane.
9542 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
9543 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc);
9548 old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
9549 new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
9551 if (new_cdclk_state &&
9552 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
9553 *need_cdclk_calc = true;
9555 ret = dev_priv->display.bw_calc_min_cdclk(state);
9559 new_bw_state = intel_atomic_get_new_bw_state(state);
9561 if (!new_cdclk_state || !new_bw_state)
9564 for_each_pipe(dev_priv, pipe) {
9565 min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk);
9568 * Currently do this change only if we need to increase
9570 if (new_bw_state->min_cdclk > min_cdclk)
9571 *need_cdclk_calc = true;
9577 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
9579 struct intel_crtc_state *crtc_state;
9580 struct intel_crtc *crtc;
9583 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
9584 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
9587 ret = intel_crtc_atomic_check(state, crtc);
9589 drm_dbg_atomic(&i915->drm,
9590 "[CRTC:%d:%s] atomic driver check failed\n",
9591 crtc->base.base.id, crtc->base.name);
9599 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
9602 const struct intel_crtc_state *new_crtc_state;
9603 struct intel_crtc *crtc;
9606 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
9607 if (new_crtc_state->hw.enable &&
9608 transcoders & BIT(new_crtc_state->cpu_transcoder) &&
9609 intel_crtc_needs_modeset(new_crtc_state))
9616 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state,
9617 struct intel_crtc *crtc,
9618 struct intel_crtc_state *old_crtc_state,
9619 struct intel_crtc_state *new_crtc_state)
9621 struct intel_crtc_state *slave_crtc_state, *master_crtc_state;
9622 struct intel_crtc *slave, *master;
9624 /* slave being enabled, is master is still claiming this crtc? */
9625 if (old_crtc_state->bigjoiner_slave) {
9627 master = old_crtc_state->bigjoiner_linked_crtc;
9628 master_crtc_state = intel_atomic_get_new_crtc_state(state, master);
9629 if (!master_crtc_state || !intel_crtc_needs_modeset(master_crtc_state))
9633 if (!new_crtc_state->bigjoiner)
9636 slave = intel_dsc_get_bigjoiner_secondary(crtc);
9638 DRM_DEBUG_KMS("[CRTC:%d:%s] Big joiner configuration requires "
9639 "CRTC + 1 to be used, doesn't exist\n",
9640 crtc->base.base.id, crtc->base.name);
9644 new_crtc_state->bigjoiner_linked_crtc = slave;
9645 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave);
9647 if (IS_ERR(slave_crtc_state))
9648 return PTR_ERR(slave_crtc_state);
9650 /* master being enabled, slave was already configured? */
9651 if (slave_crtc_state->uapi.enable)
9654 DRM_DEBUG_KMS("[CRTC:%d:%s] Used as slave for big joiner\n",
9655 slave->base.base.id, slave->base.name);
9657 return copy_bigjoiner_crtc_state(slave_crtc_state, new_crtc_state);
9660 DRM_DEBUG_KMS("[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
9661 "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
9662 slave->base.base.id, slave->base.name,
9663 master->base.base.id, master->base.name);
9667 static void kill_bigjoiner_slave(struct intel_atomic_state *state,
9668 struct intel_crtc_state *master_crtc_state)
9670 struct intel_crtc_state *slave_crtc_state =
9671 intel_atomic_get_new_crtc_state(state, master_crtc_state->bigjoiner_linked_crtc);
9673 slave_crtc_state->bigjoiner = master_crtc_state->bigjoiner = false;
9674 slave_crtc_state->bigjoiner_slave = master_crtc_state->bigjoiner_slave = false;
9675 slave_crtc_state->bigjoiner_linked_crtc = master_crtc_state->bigjoiner_linked_crtc = NULL;
9676 intel_crtc_copy_uapi_to_hw_state(state, slave_crtc_state);
9680 * DOC: asynchronous flip implementation
9682 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
9683 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
9684 * Correspondingly, support is currently added for primary plane only.
9686 * Async flip can only change the plane surface address, so anything else
9687 * changing is rejected from the intel_atomic_check_async() function.
9688 * Once this check is cleared, flip done interrupt is enabled using
9689 * the intel_crtc_enable_flip_done() function.
9691 * As soon as the surface address register is written, flip done interrupt is
9692 * generated and the requested events are sent to the usersapce in the interrupt
9693 * handler itself. The timestamp and sequence sent during the flip done event
9694 * correspond to the last vblank and have no relation to the actual time when
9695 * the flip done event was sent.
9697 static int intel_atomic_check_async(struct intel_atomic_state *state)
9699 struct drm_i915_private *i915 = to_i915(state->base.dev);
9700 const struct intel_crtc_state *old_crtc_state, *new_crtc_state;
9701 const struct intel_plane_state *new_plane_state, *old_plane_state;
9702 struct intel_crtc *crtc;
9703 struct intel_plane *plane;
9706 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
9707 new_crtc_state, i) {
9708 if (intel_crtc_needs_modeset(new_crtc_state)) {
9709 drm_dbg_kms(&i915->drm, "Modeset Required. Async flip not supported\n");
9713 if (!new_crtc_state->hw.active) {
9714 drm_dbg_kms(&i915->drm, "CRTC inactive\n");
9717 if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
9718 drm_dbg_kms(&i915->drm,
9719 "Active planes cannot be changed during async flip\n");
9724 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
9725 new_plane_state, i) {
9727 * TODO: Async flip is only supported through the page flip IOCTL
9728 * as of now. So support currently added for primary plane only.
9729 * Support for other planes on platforms on which supports
9730 * this(vlv/chv and icl+) should be added when async flip is
9731 * enabled in the atomic IOCTL path.
9733 if (!plane->async_flip)
9737 * FIXME: This check is kept generic for all platforms.
9738 * Need to verify this for all gen9 and gen10 platforms to enable
9739 * this selectively if required.
9741 switch (new_plane_state->hw.fb->modifier) {
9742 case I915_FORMAT_MOD_X_TILED:
9743 case I915_FORMAT_MOD_Y_TILED:
9744 case I915_FORMAT_MOD_Yf_TILED:
9747 drm_dbg_kms(&i915->drm,
9748 "Linear memory/CCS does not support async flips\n");
9752 if (old_plane_state->view.color_plane[0].stride !=
9753 new_plane_state->view.color_plane[0].stride) {
9754 drm_dbg_kms(&i915->drm, "Stride cannot be changed in async flip\n");
9758 if (old_plane_state->hw.fb->modifier !=
9759 new_plane_state->hw.fb->modifier) {
9760 drm_dbg_kms(&i915->drm,
9761 "Framebuffer modifiers cannot be changed in async flip\n");
9765 if (old_plane_state->hw.fb->format !=
9766 new_plane_state->hw.fb->format) {
9767 drm_dbg_kms(&i915->drm,
9768 "Framebuffer format cannot be changed in async flip\n");
9772 if (old_plane_state->hw.rotation !=
9773 new_plane_state->hw.rotation) {
9774 drm_dbg_kms(&i915->drm, "Rotation cannot be changed in async flip\n");
9778 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) ||
9779 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) {
9780 drm_dbg_kms(&i915->drm,
9781 "Plane size/co-ordinates cannot be changed in async flip\n");
9785 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
9786 drm_dbg_kms(&i915->drm, "Alpha value cannot be changed in async flip\n");
9790 if (old_plane_state->hw.pixel_blend_mode !=
9791 new_plane_state->hw.pixel_blend_mode) {
9792 drm_dbg_kms(&i915->drm,
9793 "Pixel blend mode cannot be changed in async flip\n");
9797 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
9798 drm_dbg_kms(&i915->drm,
9799 "Color encoding cannot be changed in async flip\n");
9803 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
9804 drm_dbg_kms(&i915->drm, "Color range cannot be changed in async flip\n");
9812 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state)
9814 struct intel_crtc_state *crtc_state;
9815 struct intel_crtc *crtc;
9818 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
9819 struct intel_crtc_state *linked_crtc_state;
9820 struct intel_crtc *linked_crtc;
9823 if (!crtc_state->bigjoiner)
9826 linked_crtc = crtc_state->bigjoiner_linked_crtc;
9827 linked_crtc_state = intel_atomic_get_crtc_state(&state->base, linked_crtc);
9828 if (IS_ERR(linked_crtc_state))
9829 return PTR_ERR(linked_crtc_state);
9831 if (!intel_crtc_needs_modeset(crtc_state))
9834 linked_crtc_state->uapi.mode_changed = true;
9836 ret = drm_atomic_add_affected_connectors(&state->base,
9837 &linked_crtc->base);
9841 ret = intel_atomic_add_affected_planes(state, linked_crtc);
9846 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
9847 /* Kill old bigjoiner link, we may re-establish afterwards */
9848 if (intel_crtc_needs_modeset(crtc_state) &&
9849 crtc_state->bigjoiner && !crtc_state->bigjoiner_slave)
9850 kill_bigjoiner_slave(state, crtc_state);
9857 * intel_atomic_check - validate state object
9859 * @_state: state to validate
9861 static int intel_atomic_check(struct drm_device *dev,
9862 struct drm_atomic_state *_state)
9864 struct drm_i915_private *dev_priv = to_i915(dev);
9865 struct intel_atomic_state *state = to_intel_atomic_state(_state);
9866 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
9867 struct intel_crtc *crtc;
9869 bool any_ms = false;
9871 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
9872 new_crtc_state, i) {
9873 if (new_crtc_state->inherited != old_crtc_state->inherited)
9874 new_crtc_state->uapi.mode_changed = true;
9877 intel_vrr_check_modeset(state);
9879 ret = drm_atomic_helper_check_modeset(dev, &state->base);
9883 ret = intel_bigjoiner_add_affected_crtcs(state);
9887 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
9888 new_crtc_state, i) {
9889 if (!intel_crtc_needs_modeset(new_crtc_state)) {
9891 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, new_crtc_state);
9896 if (!new_crtc_state->uapi.enable) {
9897 if (!new_crtc_state->bigjoiner_slave) {
9898 intel_crtc_copy_uapi_to_hw_state(state, new_crtc_state);
9904 ret = intel_crtc_prepare_cleared_state(state, new_crtc_state);
9908 ret = intel_modeset_pipe_config(state, new_crtc_state);
9912 ret = intel_atomic_check_bigjoiner(state, crtc, old_crtc_state,
9918 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
9919 new_crtc_state, i) {
9920 if (!intel_crtc_needs_modeset(new_crtc_state))
9923 ret = intel_modeset_pipe_config_late(new_crtc_state);
9927 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
9931 * Check if fastset is allowed by external dependencies like other
9932 * pipes and transcoders.
9934 * Right now it only forces a fullmodeset when the MST master
9935 * transcoder did not changed but the pipe of the master transcoder
9936 * needs a fullmodeset so all slaves also needs to do a fullmodeset or
9937 * in case of port synced crtcs, if one of the synced crtcs
9938 * needs a full modeset, all other synced crtcs should be
9939 * forced a full modeset.
9941 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
9942 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state))
9945 if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
9946 enum transcoder master = new_crtc_state->mst_master_transcoder;
9948 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
9949 new_crtc_state->uapi.mode_changed = true;
9950 new_crtc_state->update_pipe = false;
9954 if (is_trans_port_sync_mode(new_crtc_state)) {
9955 u8 trans = new_crtc_state->sync_mode_slaves_mask;
9957 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
9958 trans |= BIT(new_crtc_state->master_transcoder);
9960 if (intel_cpu_transcoders_need_modeset(state, trans)) {
9961 new_crtc_state->uapi.mode_changed = true;
9962 new_crtc_state->update_pipe = false;
9966 if (new_crtc_state->bigjoiner) {
9967 struct intel_crtc_state *linked_crtc_state =
9968 intel_atomic_get_new_crtc_state(state, new_crtc_state->bigjoiner_linked_crtc);
9970 if (intel_crtc_needs_modeset(linked_crtc_state)) {
9971 new_crtc_state->uapi.mode_changed = true;
9972 new_crtc_state->update_pipe = false;
9977 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
9978 new_crtc_state, i) {
9979 if (intel_crtc_needs_modeset(new_crtc_state)) {
9984 if (!new_crtc_state->update_pipe)
9987 intel_crtc_copy_fastset(old_crtc_state, new_crtc_state);
9990 if (any_ms && !check_digital_port_conflicts(state)) {
9991 drm_dbg_kms(&dev_priv->drm,
9992 "rejecting conflicting digital port configuration\n");
9997 ret = drm_dp_mst_atomic_check(&state->base);
10001 ret = intel_atomic_check_planes(state);
10005 intel_fbc_choose_crtc(dev_priv, state);
10006 ret = calc_watermark_data(state);
10010 ret = intel_bw_atomic_check(state);
10014 ret = intel_atomic_check_cdclk(state, &any_ms);
10018 if (intel_any_crtc_needs_modeset(state))
10022 ret = intel_modeset_checks(state);
10026 ret = intel_modeset_calc_cdclk(state);
10030 intel_modeset_clear_plls(state);
10033 ret = intel_atomic_check_crtcs(state);
10037 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10038 new_crtc_state, i) {
10039 if (new_crtc_state->uapi.async_flip) {
10040 ret = intel_atomic_check_async(state);
10045 if (!intel_crtc_needs_modeset(new_crtc_state) &&
10046 !new_crtc_state->update_pipe)
10049 intel_dump_pipe_config(new_crtc_state, state,
10050 intel_crtc_needs_modeset(new_crtc_state) ?
10051 "[modeset]" : "[fastset]");
10057 if (ret == -EDEADLK)
10061 * FIXME would probably be nice to know which crtc specifically
10062 * caused the failure, in cases where we can pinpoint it.
10064 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10066 intel_dump_pipe_config(new_crtc_state, state, "[failed]");
10071 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
10073 struct intel_crtc_state *crtc_state;
10074 struct intel_crtc *crtc;
10077 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
10081 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
10082 bool mode_changed = intel_crtc_needs_modeset(crtc_state);
10084 if (mode_changed || crtc_state->update_pipe ||
10085 crtc_state->uapi.color_mgmt_changed) {
10086 intel_dsb_prepare(crtc_state);
10093 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
10094 struct intel_crtc_state *crtc_state)
10096 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10098 if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes)
10099 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
10101 if (crtc_state->has_pch_encoder) {
10102 enum pipe pch_transcoder =
10103 intel_crtc_pch_transcoder(crtc);
10105 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
10109 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
10110 const struct intel_crtc_state *new_crtc_state)
10112 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
10113 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10116 * Update pipe size and adjust fitter if needed: the reason for this is
10117 * that in compute_mode_changes we check the native mode (not the pfit
10118 * mode) to see if we can flip rather than do a full mode set. In the
10119 * fastboot case, we'll flip, but if we don't update the pipesrc and
10120 * pfit state, we'll end up with a big fb scanned out into the wrong
10123 intel_set_pipe_src_size(new_crtc_state);
10125 /* on skylake this is done by detaching scalers */
10126 if (DISPLAY_VER(dev_priv) >= 9) {
10127 if (new_crtc_state->pch_pfit.enabled)
10128 skl_pfit_enable(new_crtc_state);
10129 } else if (HAS_PCH_SPLIT(dev_priv)) {
10130 if (new_crtc_state->pch_pfit.enabled)
10131 ilk_pfit_enable(new_crtc_state);
10132 else if (old_crtc_state->pch_pfit.enabled)
10133 ilk_pfit_disable(old_crtc_state);
10137 * The register is supposedly single buffered so perhaps
10138 * not 100% correct to do this here. But SKL+ calculate
10139 * this based on the adjust pixel rate so pfit changes do
10140 * affect it and so it must be updated for fastsets.
10141 * HSW/BDW only really need this here for fastboot, after
10142 * that the value should not change without a full modeset.
10144 if (DISPLAY_VER(dev_priv) >= 9 ||
10145 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
10146 hsw_set_linetime_wm(new_crtc_state);
10148 if (DISPLAY_VER(dev_priv) >= 11)
10149 icl_set_pipe_chicken(crtc);
10152 static void commit_pipe_pre_planes(struct intel_atomic_state *state,
10153 struct intel_crtc *crtc)
10155 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
10156 const struct intel_crtc_state *old_crtc_state =
10157 intel_atomic_get_old_crtc_state(state, crtc);
10158 const struct intel_crtc_state *new_crtc_state =
10159 intel_atomic_get_new_crtc_state(state, crtc);
10160 bool modeset = intel_crtc_needs_modeset(new_crtc_state);
10163 * During modesets pipe configuration was programmed as the
10164 * CRTC was enabled.
10167 if (new_crtc_state->uapi.color_mgmt_changed ||
10168 new_crtc_state->update_pipe)
10169 intel_color_commit(new_crtc_state);
10171 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
10172 bdw_set_pipemisc(new_crtc_state);
10174 if (new_crtc_state->update_pipe)
10175 intel_pipe_fastset(old_crtc_state, new_crtc_state);
10177 intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
10180 if (dev_priv->display.atomic_update_watermarks)
10181 dev_priv->display.atomic_update_watermarks(state, crtc);
10184 static void commit_pipe_post_planes(struct intel_atomic_state *state,
10185 struct intel_crtc *crtc)
10187 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
10188 const struct intel_crtc_state *new_crtc_state =
10189 intel_atomic_get_new_crtc_state(state, crtc);
10192 * Disable the scaler(s) after the plane(s) so that we don't
10193 * get a catastrophic underrun even if the two operations
10194 * end up happening in two different frames.
10196 if (DISPLAY_VER(dev_priv) >= 9 &&
10197 !intel_crtc_needs_modeset(new_crtc_state))
10198 skl_detach_scalers(new_crtc_state);
10201 static void intel_enable_crtc(struct intel_atomic_state *state,
10202 struct intel_crtc *crtc)
10204 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
10205 const struct intel_crtc_state *new_crtc_state =
10206 intel_atomic_get_new_crtc_state(state, crtc);
10208 if (!intel_crtc_needs_modeset(new_crtc_state))
10211 intel_crtc_update_active_timings(new_crtc_state);
10213 dev_priv->display.crtc_enable(state, crtc);
10215 if (new_crtc_state->bigjoiner_slave)
10218 /* vblanks work again, re-enable pipe CRC. */
10219 intel_crtc_enable_pipe_crc(crtc);
10222 static void intel_update_crtc(struct intel_atomic_state *state,
10223 struct intel_crtc *crtc)
10225 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
10226 const struct intel_crtc_state *old_crtc_state =
10227 intel_atomic_get_old_crtc_state(state, crtc);
10228 struct intel_crtc_state *new_crtc_state =
10229 intel_atomic_get_new_crtc_state(state, crtc);
10230 bool modeset = intel_crtc_needs_modeset(new_crtc_state);
10233 if (new_crtc_state->preload_luts &&
10234 (new_crtc_state->uapi.color_mgmt_changed ||
10235 new_crtc_state->update_pipe))
10236 intel_color_load_luts(new_crtc_state);
10238 intel_pre_plane_update(state, crtc);
10240 if (new_crtc_state->update_pipe)
10241 intel_encoders_update_pipe(state, crtc);
10244 if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
10245 intel_fbc_disable(crtc);
10247 intel_fbc_enable(state, crtc);
10249 /* Perform vblank evasion around commit operation */
10250 intel_pipe_update_start(new_crtc_state);
10252 commit_pipe_pre_planes(state, crtc);
10254 if (DISPLAY_VER(dev_priv) >= 9)
10255 skl_update_planes_on_crtc(state, crtc);
10257 i9xx_update_planes_on_crtc(state, crtc);
10259 commit_pipe_post_planes(state, crtc);
10261 intel_pipe_update_end(new_crtc_state);
10264 * We usually enable FIFO underrun interrupts as part of the
10265 * CRTC enable sequence during modesets. But when we inherit a
10266 * valid pipe configuration from the BIOS we need to take care
10267 * of enabling them on the CRTC's first fastset.
10269 if (new_crtc_state->update_pipe && !modeset &&
10270 old_crtc_state->inherited)
10271 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
10274 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
10275 struct intel_crtc_state *old_crtc_state,
10276 struct intel_crtc_state *new_crtc_state,
10277 struct intel_crtc *crtc)
10279 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
10281 drm_WARN_ON(&dev_priv->drm, old_crtc_state->bigjoiner_slave);
10283 intel_crtc_disable_planes(state, crtc);
10286 * We still need special handling for disabling bigjoiner master
10287 * and slaves since for slave we do not have encoder or plls
10288 * so we dont need to disable those.
10290 if (old_crtc_state->bigjoiner) {
10291 intel_crtc_disable_planes(state,
10292 old_crtc_state->bigjoiner_linked_crtc);
10293 old_crtc_state->bigjoiner_linked_crtc->active = false;
10297 * We need to disable pipe CRC before disabling the pipe,
10298 * or we race against vblank off.
10300 intel_crtc_disable_pipe_crc(crtc);
10302 dev_priv->display.crtc_disable(state, crtc);
10303 crtc->active = false;
10304 intel_fbc_disable(crtc);
10305 intel_disable_shared_dpll(old_crtc_state);
10307 /* FIXME unify this for all platforms */
10308 if (!new_crtc_state->hw.active &&
10309 !HAS_GMCH(dev_priv) &&
10310 dev_priv->display.initial_watermarks)
10311 dev_priv->display.initial_watermarks(state, crtc);
10314 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
10316 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
10317 struct intel_crtc *crtc;
10321 /* Only disable port sync and MST slaves */
10322 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10323 new_crtc_state, i) {
10324 if (!intel_crtc_needs_modeset(new_crtc_state) || old_crtc_state->bigjoiner)
10327 if (!old_crtc_state->hw.active)
10330 /* In case of Transcoder port Sync master slave CRTCs can be
10331 * assigned in any order and we need to make sure that
10332 * slave CRTCs are disabled first and then master CRTC since
10333 * Slave vblanks are masked till Master Vblanks.
10335 if (!is_trans_port_sync_slave(old_crtc_state) &&
10336 !intel_dp_mst_is_slave_trans(old_crtc_state))
10339 intel_pre_plane_update(state, crtc);
10340 intel_old_crtc_state_disables(state, old_crtc_state,
10341 new_crtc_state, crtc);
10342 handled |= BIT(crtc->pipe);
10345 /* Disable everything else left on */
10346 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10347 new_crtc_state, i) {
10348 if (!intel_crtc_needs_modeset(new_crtc_state) ||
10349 (handled & BIT(crtc->pipe)) ||
10350 old_crtc_state->bigjoiner_slave)
10353 intel_pre_plane_update(state, crtc);
10354 if (old_crtc_state->bigjoiner) {
10355 struct intel_crtc *slave =
10356 old_crtc_state->bigjoiner_linked_crtc;
10358 intel_pre_plane_update(state, slave);
10361 if (old_crtc_state->hw.active)
10362 intel_old_crtc_state_disables(state, old_crtc_state,
10363 new_crtc_state, crtc);
10367 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
10369 struct intel_crtc_state *new_crtc_state;
10370 struct intel_crtc *crtc;
10373 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
10374 if (!new_crtc_state->hw.active)
10377 intel_enable_crtc(state, crtc);
10378 intel_update_crtc(state, crtc);
10382 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
10384 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
10385 struct intel_crtc *crtc;
10386 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
10387 struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
10388 u8 update_pipes = 0, modeset_pipes = 0;
10391 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10392 enum pipe pipe = crtc->pipe;
10394 if (!new_crtc_state->hw.active)
10397 /* ignore allocations for crtc's that have been turned off. */
10398 if (!intel_crtc_needs_modeset(new_crtc_state)) {
10399 entries[pipe] = old_crtc_state->wm.skl.ddb;
10400 update_pipes |= BIT(pipe);
10402 modeset_pipes |= BIT(pipe);
10407 * Whenever the number of active pipes changes, we need to make sure we
10408 * update the pipes in the right order so that their ddb allocations
10409 * never overlap with each other between CRTC updates. Otherwise we'll
10410 * cause pipe underruns and other bad stuff.
10412 * So first lets enable all pipes that do not need a fullmodeset as
10413 * those don't have any external dependency.
10415 while (update_pipes) {
10416 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10417 new_crtc_state, i) {
10418 enum pipe pipe = crtc->pipe;
10420 if ((update_pipes & BIT(pipe)) == 0)
10423 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
10424 entries, I915_MAX_PIPES, pipe))
10427 entries[pipe] = new_crtc_state->wm.skl.ddb;
10428 update_pipes &= ~BIT(pipe);
10430 intel_update_crtc(state, crtc);
10433 * If this is an already active pipe, it's DDB changed,
10434 * and this isn't the last pipe that needs updating
10435 * then we need to wait for a vblank to pass for the
10436 * new ddb allocation to take effect.
10438 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
10439 &old_crtc_state->wm.skl.ddb) &&
10440 (update_pipes | modeset_pipes))
10441 intel_wait_for_vblank(dev_priv, pipe);
10445 update_pipes = modeset_pipes;
10448 * Enable all pipes that needs a modeset and do not depends on other
10451 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
10452 enum pipe pipe = crtc->pipe;
10454 if ((modeset_pipes & BIT(pipe)) == 0)
10457 if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
10458 is_trans_port_sync_master(new_crtc_state) ||
10459 (new_crtc_state->bigjoiner && !new_crtc_state->bigjoiner_slave))
10462 modeset_pipes &= ~BIT(pipe);
10464 intel_enable_crtc(state, crtc);
10468 * Then we enable all remaining pipes that depend on other
10469 * pipes: MST slaves and port sync masters, big joiner master
10471 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
10472 enum pipe pipe = crtc->pipe;
10474 if ((modeset_pipes & BIT(pipe)) == 0)
10477 modeset_pipes &= ~BIT(pipe);
10479 intel_enable_crtc(state, crtc);
10483 * Finally we do the plane updates/etc. for all pipes that got enabled.
10485 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
10486 enum pipe pipe = crtc->pipe;
10488 if ((update_pipes & BIT(pipe)) == 0)
10491 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
10492 entries, I915_MAX_PIPES, pipe));
10494 entries[pipe] = new_crtc_state->wm.skl.ddb;
10495 update_pipes &= ~BIT(pipe);
10497 intel_update_crtc(state, crtc);
10500 drm_WARN_ON(&dev_priv->drm, modeset_pipes);
10501 drm_WARN_ON(&dev_priv->drm, update_pipes);
10504 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
10506 struct intel_atomic_state *state, *next;
10507 struct llist_node *freed;
10509 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
10510 llist_for_each_entry_safe(state, next, freed, freed)
10511 drm_atomic_state_put(&state->base);
10514 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
10516 struct drm_i915_private *dev_priv =
10517 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
10519 intel_atomic_helper_free_state(dev_priv);
10522 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
10524 struct wait_queue_entry wait_fence, wait_reset;
10525 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
10527 init_wait_entry(&wait_fence, 0);
10528 init_wait_entry(&wait_reset, 0);
10530 prepare_to_wait(&intel_state->commit_ready.wait,
10531 &wait_fence, TASK_UNINTERRUPTIBLE);
10532 prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
10533 I915_RESET_MODESET),
10534 &wait_reset, TASK_UNINTERRUPTIBLE);
10537 if (i915_sw_fence_done(&intel_state->commit_ready) ||
10538 test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
10543 finish_wait(&intel_state->commit_ready.wait, &wait_fence);
10544 finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
10545 I915_RESET_MODESET),
10549 static void intel_cleanup_dsbs(struct intel_atomic_state *state)
10551 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
10552 struct intel_crtc *crtc;
10555 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10557 intel_dsb_cleanup(old_crtc_state);
10560 static void intel_atomic_cleanup_work(struct work_struct *work)
10562 struct intel_atomic_state *state =
10563 container_of(work, struct intel_atomic_state, base.commit_work);
10564 struct drm_i915_private *i915 = to_i915(state->base.dev);
10566 intel_cleanup_dsbs(state);
10567 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
10568 drm_atomic_helper_commit_cleanup_done(&state->base);
10569 drm_atomic_state_put(&state->base);
10571 intel_atomic_helper_free_state(i915);
10574 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state)
10576 struct drm_i915_private *i915 = to_i915(state->base.dev);
10577 struct intel_plane *plane;
10578 struct intel_plane_state *plane_state;
10581 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
10582 struct drm_framebuffer *fb = plane_state->hw.fb;
10586 fb->modifier != I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
10590 * The layout of the fast clear color value expected by HW
10591 * (the DRM ABI requiring this value to be located in fb at offset 0 of plane#2):
10592 * - 4 x 4 bytes per-channel value
10593 * (in surface type specific float/int format provided by the fb user)
10594 * - 8 bytes native color value used by the display
10595 * (converted/written by GPU during a fast clear operation using the
10596 * above per-channel values)
10598 * The commit's FB prepare hook already ensured that FB obj is pinned and the
10599 * caller made sure that the object is synced wrt. the related color clear value
10602 ret = i915_gem_object_read_from_page(intel_fb_obj(fb),
10603 fb->offsets[2] + 16,
10604 &plane_state->ccval,
10605 sizeof(plane_state->ccval));
10606 /* The above could only fail if the FB obj has an unexpected backing store type. */
10607 drm_WARN_ON(&i915->drm, ret);
10611 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
10613 struct drm_device *dev = state->base.dev;
10614 struct drm_i915_private *dev_priv = to_i915(dev);
10615 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
10616 struct intel_crtc *crtc;
10617 u64 put_domains[I915_MAX_PIPES] = {};
10618 intel_wakeref_t wakeref = 0;
10621 intel_atomic_commit_fence_wait(state);
10623 drm_atomic_helper_wait_for_dependencies(&state->base);
10625 if (state->modeset)
10626 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
10628 intel_atomic_prepare_plane_clear_colors(state);
10630 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10631 new_crtc_state, i) {
10632 if (intel_crtc_needs_modeset(new_crtc_state) ||
10633 new_crtc_state->update_pipe) {
10635 put_domains[crtc->pipe] =
10636 modeset_get_crtc_power_domains(new_crtc_state);
10640 intel_commit_modeset_disables(state);
10642 /* FIXME: Eventually get rid of our crtc->config pointer */
10643 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
10644 crtc->config = new_crtc_state;
10646 if (state->modeset) {
10647 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
10649 intel_set_cdclk_pre_plane_update(state);
10651 intel_modeset_verify_disabled(dev_priv, state);
10654 intel_sagv_pre_plane_update(state);
10656 /* Complete the events for pipes that have now been disabled */
10657 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
10658 bool modeset = intel_crtc_needs_modeset(new_crtc_state);
10660 /* Complete events for now disable pipes here. */
10661 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
10662 spin_lock_irq(&dev->event_lock);
10663 drm_crtc_send_vblank_event(&crtc->base,
10664 new_crtc_state->uapi.event);
10665 spin_unlock_irq(&dev->event_lock);
10667 new_crtc_state->uapi.event = NULL;
10671 if (state->modeset)
10672 intel_encoders_update_prepare(state);
10674 intel_dbuf_pre_plane_update(state);
10676 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
10677 if (new_crtc_state->uapi.async_flip)
10678 intel_crtc_enable_flip_done(state, crtc);
10681 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10682 dev_priv->display.commit_modeset_enables(state);
10684 if (state->modeset) {
10685 intel_encoders_update_complete(state);
10687 intel_set_cdclk_post_plane_update(state);
10690 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
10691 * already, but still need the state for the delayed optimization. To
10693 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
10694 * - schedule that vblank worker _before_ calling hw_done
10695 * - at the start of commit_tail, cancel it _synchrously
10696 * - switch over to the vblank wait helper in the core after that since
10697 * we don't need out special handling any more.
10699 drm_atomic_helper_wait_for_flip_done(dev, &state->base);
10701 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
10702 if (new_crtc_state->uapi.async_flip)
10703 intel_crtc_disable_flip_done(state, crtc);
10705 if (new_crtc_state->hw.active &&
10706 !intel_crtc_needs_modeset(new_crtc_state) &&
10707 !new_crtc_state->preload_luts &&
10708 (new_crtc_state->uapi.color_mgmt_changed ||
10709 new_crtc_state->update_pipe))
10710 intel_color_load_luts(new_crtc_state);
10714 * Now that the vblank has passed, we can go ahead and program the
10715 * optimal watermarks on platforms that need two-step watermark
10718 * TODO: Move this (and other cleanup) to an async worker eventually.
10720 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10721 new_crtc_state, i) {
10723 * Gen2 reports pipe underruns whenever all planes are disabled.
10724 * So re-enable underrun reporting after some planes get enabled.
10726 * We do this before .optimize_watermarks() so that we have a
10727 * chance of catching underruns with the intermediate watermarks
10728 * vs. the new plane configuration.
10730 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
10731 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
10733 if (dev_priv->display.optimize_watermarks)
10734 dev_priv->display.optimize_watermarks(state, crtc);
10737 intel_dbuf_post_plane_update(state);
10739 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10740 intel_post_plane_update(state, crtc);
10742 modeset_put_crtc_power_domains(crtc, put_domains[crtc->pipe]);
10744 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
10747 * DSB cleanup is done in cleanup_work aligning with framebuffer
10748 * cleanup. So copy and reset the dsb structure to sync with
10749 * commit_done and later do dsb cleanup in cleanup_work.
10751 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb);
10754 /* Underruns don't always raise interrupts, so check manually */
10755 intel_check_cpu_fifo_underruns(dev_priv);
10756 intel_check_pch_fifo_underruns(dev_priv);
10758 if (state->modeset)
10759 intel_verify_planes(state);
10761 intel_sagv_post_plane_update(state);
10763 drm_atomic_helper_commit_hw_done(&state->base);
10765 if (state->modeset) {
10766 /* As one of the primary mmio accessors, KMS has a high
10767 * likelihood of triggering bugs in unclaimed access. After we
10768 * finish modesetting, see if an error has been flagged, and if
10769 * so enable debugging for the next modeset - and hope we catch
10772 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
10773 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
10775 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
10778 * Defer the cleanup of the old state to a separate worker to not
10779 * impede the current task (userspace for blocking modesets) that
10780 * are executed inline. For out-of-line asynchronous modesets/flips,
10781 * deferring to a new worker seems overkill, but we would place a
10782 * schedule point (cond_resched()) here anyway to keep latencies
10785 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
10786 queue_work(system_highpri_wq, &state->base.commit_work);
10789 static void intel_atomic_commit_work(struct work_struct *work)
10791 struct intel_atomic_state *state =
10792 container_of(work, struct intel_atomic_state, base.commit_work);
10794 intel_atomic_commit_tail(state);
10797 static int __i915_sw_fence_call
10798 intel_atomic_commit_ready(struct i915_sw_fence *fence,
10799 enum i915_sw_fence_notify notify)
10801 struct intel_atomic_state *state =
10802 container_of(fence, struct intel_atomic_state, commit_ready);
10805 case FENCE_COMPLETE:
10806 /* we do blocking waits in the worker, nothing to do here */
10810 struct intel_atomic_helper *helper =
10811 &to_i915(state->base.dev)->atomic_helper;
10813 if (llist_add(&state->freed, &helper->free_list))
10814 schedule_work(&helper->free_work);
10819 return NOTIFY_DONE;
10822 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
10824 struct intel_plane_state *old_plane_state, *new_plane_state;
10825 struct intel_plane *plane;
10828 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
10829 new_plane_state, i)
10830 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
10831 to_intel_frontbuffer(new_plane_state->hw.fb),
10832 plane->frontbuffer_bit);
10835 static int intel_atomic_commit(struct drm_device *dev,
10836 struct drm_atomic_state *_state,
10839 struct intel_atomic_state *state = to_intel_atomic_state(_state);
10840 struct drm_i915_private *dev_priv = to_i915(dev);
10843 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
10845 drm_atomic_state_get(&state->base);
10846 i915_sw_fence_init(&state->commit_ready,
10847 intel_atomic_commit_ready);
10850 * The intel_legacy_cursor_update() fast path takes care
10851 * of avoiding the vblank waits for simple cursor
10852 * movement and flips. For cursor on/off and size changes,
10853 * we want to perform the vblank waits so that watermark
10854 * updates happen during the correct frames. Gen9+ have
10855 * double buffered watermarks and so shouldn't need this.
10857 * Unset state->legacy_cursor_update before the call to
10858 * drm_atomic_helper_setup_commit() because otherwise
10859 * drm_atomic_helper_wait_for_flip_done() is a noop and
10860 * we get FIFO underruns because we didn't wait
10863 * FIXME doing watermarks and fb cleanup from a vblank worker
10864 * (assuming we had any) would solve these problems.
10866 if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) {
10867 struct intel_crtc_state *new_crtc_state;
10868 struct intel_crtc *crtc;
10871 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
10872 if (new_crtc_state->wm.need_postvbl_update ||
10873 new_crtc_state->update_wm_post)
10874 state->base.legacy_cursor_update = false;
10877 ret = intel_atomic_prepare_commit(state);
10879 drm_dbg_atomic(&dev_priv->drm,
10880 "Preparing state failed with %i\n", ret);
10881 i915_sw_fence_commit(&state->commit_ready);
10882 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
10886 ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
10888 ret = drm_atomic_helper_swap_state(&state->base, true);
10890 intel_atomic_swap_global_state(state);
10893 struct intel_crtc_state *new_crtc_state;
10894 struct intel_crtc *crtc;
10897 i915_sw_fence_commit(&state->commit_ready);
10899 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
10900 intel_dsb_cleanup(new_crtc_state);
10902 drm_atomic_helper_cleanup_planes(dev, &state->base);
10903 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
10906 intel_shared_dpll_swap_state(state);
10907 intel_atomic_track_fbs(state);
10909 drm_atomic_state_get(&state->base);
10910 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
10912 i915_sw_fence_commit(&state->commit_ready);
10913 if (nonblock && state->modeset) {
10914 queue_work(dev_priv->modeset_wq, &state->base.commit_work);
10915 } else if (nonblock) {
10916 queue_work(dev_priv->flip_wq, &state->base.commit_work);
10918 if (state->modeset)
10919 flush_workqueue(dev_priv->modeset_wq);
10920 intel_atomic_commit_tail(state);
10926 struct wait_rps_boost {
10927 struct wait_queue_entry wait;
10929 struct drm_crtc *crtc;
10930 struct i915_request *request;
10933 static int do_rps_boost(struct wait_queue_entry *_wait,
10934 unsigned mode, int sync, void *key)
10936 struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
10937 struct i915_request *rq = wait->request;
10940 * If we missed the vblank, but the request is already running it
10941 * is reasonable to assume that it will complete before the next
10942 * vblank without our intervention, so leave RPS alone.
10944 if (!i915_request_started(rq))
10945 intel_rps_boost(rq);
10946 i915_request_put(rq);
10948 drm_crtc_vblank_put(wait->crtc);
10950 list_del(&wait->wait.entry);
10955 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
10956 struct dma_fence *fence)
10958 struct wait_rps_boost *wait;
10960 if (!dma_fence_is_i915(fence))
10963 if (DISPLAY_VER(to_i915(crtc->dev)) < 6)
10966 if (drm_crtc_vblank_get(crtc))
10969 wait = kmalloc(sizeof(*wait), GFP_KERNEL);
10971 drm_crtc_vblank_put(crtc);
10975 wait->request = to_request(dma_fence_get(fence));
10978 wait->wait.func = do_rps_boost;
10979 wait->wait.flags = 0;
10981 add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
10984 int intel_plane_pin_fb(struct intel_plane_state *plane_state)
10986 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
10987 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10988 struct drm_framebuffer *fb = plane_state->hw.fb;
10989 struct i915_vma *vma;
10991 plane->id == PLANE_CURSOR &&
10992 INTEL_INFO(dev_priv)->display.cursor_needs_physical;
10994 if (!intel_fb_uses_dpt(fb)) {
10995 vma = intel_pin_and_fence_fb_obj(fb, phys_cursor,
10996 &plane_state->view.gtt,
10997 intel_plane_uses_fence(plane_state),
10998 &plane_state->flags);
11000 return PTR_ERR(vma);
11002 plane_state->ggtt_vma = vma;
11004 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11006 vma = intel_dpt_pin(intel_fb->dpt_vm);
11008 return PTR_ERR(vma);
11010 plane_state->ggtt_vma = vma;
11012 vma = intel_pin_fb_obj_dpt(fb, &plane_state->view.gtt, false,
11013 &plane_state->flags, intel_fb->dpt_vm);
11015 intel_dpt_unpin(intel_fb->dpt_vm);
11016 plane_state->ggtt_vma = NULL;
11017 return PTR_ERR(vma);
11020 plane_state->dpt_vma = vma;
11022 WARN_ON(plane_state->ggtt_vma == plane_state->dpt_vma);
11028 void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
11030 struct drm_framebuffer *fb = old_plane_state->hw.fb;
11031 struct i915_vma *vma;
11033 if (!intel_fb_uses_dpt(fb)) {
11034 vma = fetch_and_zero(&old_plane_state->ggtt_vma);
11036 intel_unpin_fb_vma(vma, old_plane_state->flags);
11038 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11040 vma = fetch_and_zero(&old_plane_state->dpt_vma);
11042 intel_unpin_fb_vma(vma, old_plane_state->flags);
11044 vma = fetch_and_zero(&old_plane_state->ggtt_vma);
11046 intel_dpt_unpin(intel_fb->dpt_vm);
11051 * intel_prepare_plane_fb - Prepare fb for usage on plane
11052 * @_plane: drm plane to prepare for
11053 * @_new_plane_state: the plane state being prepared
11055 * Prepares a framebuffer for usage on a display plane. Generally this
11056 * involves pinning the underlying object and updating the frontbuffer tracking
11057 * bits. Some older platforms need special physical address handling for
11060 * Returns 0 on success, negative error code on failure.
11063 intel_prepare_plane_fb(struct drm_plane *_plane,
11064 struct drm_plane_state *_new_plane_state)
11066 struct i915_sched_attr attr = { .priority = I915_PRIORITY_DISPLAY };
11067 struct intel_plane *plane = to_intel_plane(_plane);
11068 struct intel_plane_state *new_plane_state =
11069 to_intel_plane_state(_new_plane_state);
11070 struct intel_atomic_state *state =
11071 to_intel_atomic_state(new_plane_state->uapi.state);
11072 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11073 const struct intel_plane_state *old_plane_state =
11074 intel_atomic_get_old_plane_state(state, plane);
11075 struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb);
11076 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_plane_state->hw.fb);
11080 const struct intel_crtc_state *crtc_state =
11081 intel_atomic_get_new_crtc_state(state,
11082 to_intel_crtc(old_plane_state->hw.crtc));
11084 /* Big Hammer, we also need to ensure that any pending
11085 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
11086 * current scanout is retired before unpinning the old
11087 * framebuffer. Note that we rely on userspace rendering
11088 * into the buffer attached to the pipe they are waiting
11089 * on. If not, userspace generates a GPU hang with IPEHR
11090 * point to the MI_WAIT_FOR_EVENT.
11092 * This should only fail upon a hung GPU, in which case we
11093 * can safely continue.
11095 if (intel_crtc_needs_modeset(crtc_state)) {
11096 ret = i915_sw_fence_await_reservation(&state->commit_ready,
11097 old_obj->base.resv, NULL,
11105 if (new_plane_state->uapi.fence) { /* explicit fencing */
11106 i915_gem_fence_wait_priority(new_plane_state->uapi.fence,
11108 ret = i915_sw_fence_await_dma_fence(&state->commit_ready,
11109 new_plane_state->uapi.fence,
11110 i915_fence_timeout(dev_priv),
11120 ret = intel_plane_pin_fb(new_plane_state);
11124 i915_gem_object_wait_priority(obj, 0, &attr);
11125 i915_gem_object_flush_frontbuffer(obj, ORIGIN_DIRTYFB);
11127 if (!new_plane_state->uapi.fence) { /* implicit fencing */
11128 struct dma_fence *fence;
11130 ret = i915_sw_fence_await_reservation(&state->commit_ready,
11131 obj->base.resv, NULL,
11133 i915_fence_timeout(dev_priv),
11138 fence = dma_resv_get_excl_unlocked(obj->base.resv);
11140 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
11142 dma_fence_put(fence);
11145 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
11146 new_plane_state->uapi.fence);
11150 * We declare pageflips to be interactive and so merit a small bias
11151 * towards upclocking to deliver the frame on time. By only changing
11152 * the RPS thresholds to sample more regularly and aim for higher
11153 * clocks we can hopefully deliver low power workloads (like kodi)
11154 * that are not quite steady state without resorting to forcing
11155 * maximum clocks following a vblank miss (see do_rps_boost()).
11157 if (!state->rps_interactive) {
11158 intel_rps_mark_interactive(&dev_priv->gt.rps, true);
11159 state->rps_interactive = true;
11165 intel_plane_unpin_fb(new_plane_state);
11171 * intel_cleanup_plane_fb - Cleans up an fb after plane use
11172 * @plane: drm plane to clean up for
11173 * @_old_plane_state: the state from the previous modeset
11175 * Cleans up a framebuffer that has just been removed from a plane.
11178 intel_cleanup_plane_fb(struct drm_plane *plane,
11179 struct drm_plane_state *_old_plane_state)
11181 struct intel_plane_state *old_plane_state =
11182 to_intel_plane_state(_old_plane_state);
11183 struct intel_atomic_state *state =
11184 to_intel_atomic_state(old_plane_state->uapi.state);
11185 struct drm_i915_private *dev_priv = to_i915(plane->dev);
11186 struct drm_i915_gem_object *obj = intel_fb_obj(old_plane_state->hw.fb);
11191 if (state->rps_interactive) {
11192 intel_rps_mark_interactive(&dev_priv->gt.rps, false);
11193 state->rps_interactive = false;
11196 /* Should only be called after a successful intel_prepare_plane_fb()! */
11197 intel_plane_unpin_fb(old_plane_state);
11201 * intel_plane_destroy - destroy a plane
11202 * @plane: plane to destroy
11204 * Common destruction function for all types of planes (primary, cursor,
11207 void intel_plane_destroy(struct drm_plane *plane)
11209 drm_plane_cleanup(plane);
11210 kfree(to_intel_plane(plane));
11213 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv)
11215 struct intel_plane *plane;
11217 for_each_intel_plane(&dev_priv->drm, plane) {
11218 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
11221 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base);
11226 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
11227 struct drm_file *file)
11229 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
11230 struct drm_crtc *drmmode_crtc;
11231 struct intel_crtc *crtc;
11233 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
11237 crtc = to_intel_crtc(drmmode_crtc);
11238 pipe_from_crtc_id->pipe = crtc->pipe;
11243 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
11245 struct drm_device *dev = encoder->base.dev;
11246 struct intel_encoder *source_encoder;
11247 u32 possible_clones = 0;
11249 for_each_intel_encoder(dev, source_encoder) {
11250 if (encoders_cloneable(encoder, source_encoder))
11251 possible_clones |= drm_encoder_mask(&source_encoder->base);
11254 return possible_clones;
11257 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
11259 struct drm_device *dev = encoder->base.dev;
11260 struct intel_crtc *crtc;
11261 u32 possible_crtcs = 0;
11263 for_each_intel_crtc(dev, crtc) {
11264 if (encoder->pipe_mask & BIT(crtc->pipe))
11265 possible_crtcs |= drm_crtc_mask(&crtc->base);
11268 return possible_crtcs;
11271 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
11273 if (!IS_MOBILE(dev_priv))
11276 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)
11279 if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
11285 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
11287 if (DISPLAY_VER(dev_priv) >= 9)
11290 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
11293 if (HAS_PCH_LPT_H(dev_priv) &&
11294 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
11297 /* DDI E can't be used if DDI A requires 4 lanes */
11298 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
11301 if (!dev_priv->vbt.int_crt_support)
11307 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
11309 struct intel_encoder *encoder;
11310 bool dpd_is_edp = false;
11312 intel_pps_unlock_regs_wa(dev_priv);
11314 if (!HAS_DISPLAY(dev_priv))
11317 if (IS_ALDERLAKE_P(dev_priv)) {
11318 intel_ddi_init(dev_priv, PORT_A);
11319 intel_ddi_init(dev_priv, PORT_B);
11320 intel_ddi_init(dev_priv, PORT_TC1);
11321 intel_ddi_init(dev_priv, PORT_TC2);
11322 intel_ddi_init(dev_priv, PORT_TC3);
11323 intel_ddi_init(dev_priv, PORT_TC4);
11324 } else if (IS_ALDERLAKE_S(dev_priv)) {
11325 intel_ddi_init(dev_priv, PORT_A);
11326 intel_ddi_init(dev_priv, PORT_TC1);
11327 intel_ddi_init(dev_priv, PORT_TC2);
11328 intel_ddi_init(dev_priv, PORT_TC3);
11329 intel_ddi_init(dev_priv, PORT_TC4);
11330 } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
11331 intel_ddi_init(dev_priv, PORT_A);
11332 intel_ddi_init(dev_priv, PORT_B);
11333 intel_ddi_init(dev_priv, PORT_TC1);
11334 intel_ddi_init(dev_priv, PORT_TC2);
11335 } else if (DISPLAY_VER(dev_priv) >= 12) {
11336 intel_ddi_init(dev_priv, PORT_A);
11337 intel_ddi_init(dev_priv, PORT_B);
11338 intel_ddi_init(dev_priv, PORT_TC1);
11339 intel_ddi_init(dev_priv, PORT_TC2);
11340 intel_ddi_init(dev_priv, PORT_TC3);
11341 intel_ddi_init(dev_priv, PORT_TC4);
11342 intel_ddi_init(dev_priv, PORT_TC5);
11343 intel_ddi_init(dev_priv, PORT_TC6);
11344 icl_dsi_init(dev_priv);
11345 } else if (IS_JSL_EHL(dev_priv)) {
11346 intel_ddi_init(dev_priv, PORT_A);
11347 intel_ddi_init(dev_priv, PORT_B);
11348 intel_ddi_init(dev_priv, PORT_C);
11349 intel_ddi_init(dev_priv, PORT_D);
11350 icl_dsi_init(dev_priv);
11351 } else if (DISPLAY_VER(dev_priv) == 11) {
11352 intel_ddi_init(dev_priv, PORT_A);
11353 intel_ddi_init(dev_priv, PORT_B);
11354 intel_ddi_init(dev_priv, PORT_C);
11355 intel_ddi_init(dev_priv, PORT_D);
11356 intel_ddi_init(dev_priv, PORT_E);
11357 intel_ddi_init(dev_priv, PORT_F);
11358 icl_dsi_init(dev_priv);
11359 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
11360 intel_ddi_init(dev_priv, PORT_A);
11361 intel_ddi_init(dev_priv, PORT_B);
11362 intel_ddi_init(dev_priv, PORT_C);
11363 vlv_dsi_init(dev_priv);
11364 } else if (DISPLAY_VER(dev_priv) >= 9) {
11365 intel_ddi_init(dev_priv, PORT_A);
11366 intel_ddi_init(dev_priv, PORT_B);
11367 intel_ddi_init(dev_priv, PORT_C);
11368 intel_ddi_init(dev_priv, PORT_D);
11369 intel_ddi_init(dev_priv, PORT_E);
11370 intel_ddi_init(dev_priv, PORT_F);
11371 } else if (HAS_DDI(dev_priv)) {
11374 if (intel_ddi_crt_present(dev_priv))
11375 intel_crt_init(dev_priv);
11377 /* Haswell uses DDI functions to detect digital outputs. */
11378 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
11380 intel_ddi_init(dev_priv, PORT_A);
11382 found = intel_de_read(dev_priv, SFUSE_STRAP);
11383 if (found & SFUSE_STRAP_DDIB_DETECTED)
11384 intel_ddi_init(dev_priv, PORT_B);
11385 if (found & SFUSE_STRAP_DDIC_DETECTED)
11386 intel_ddi_init(dev_priv, PORT_C);
11387 if (found & SFUSE_STRAP_DDID_DETECTED)
11388 intel_ddi_init(dev_priv, PORT_D);
11389 if (found & SFUSE_STRAP_DDIF_DETECTED)
11390 intel_ddi_init(dev_priv, PORT_F);
11391 } else if (HAS_PCH_SPLIT(dev_priv)) {
11395 * intel_edp_init_connector() depends on this completing first,
11396 * to prevent the registration of both eDP and LVDS and the
11397 * incorrect sharing of the PPS.
11399 intel_lvds_init(dev_priv);
11400 intel_crt_init(dev_priv);
11402 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
11404 if (ilk_has_edp_a(dev_priv))
11405 g4x_dp_init(dev_priv, DP_A, PORT_A);
11407 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
11408 /* PCH SDVOB multiplex with HDMIB */
11409 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
11411 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
11412 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
11413 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B);
11416 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
11417 g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
11419 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED)
11420 g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
11422 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
11423 g4x_dp_init(dev_priv, PCH_DP_C, PORT_C);
11425 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
11426 g4x_dp_init(dev_priv, PCH_DP_D, PORT_D);
11427 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
11428 bool has_edp, has_port;
11430 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
11431 intel_crt_init(dev_priv);
11434 * The DP_DETECTED bit is the latched state of the DDC
11435 * SDA pin at boot. However since eDP doesn't require DDC
11436 * (no way to plug in a DP->HDMI dongle) the DDC pins for
11437 * eDP ports may have been muxed to an alternate function.
11438 * Thus we can't rely on the DP_DETECTED bit alone to detect
11439 * eDP ports. Consult the VBT as well as DP_DETECTED to
11440 * detect eDP ports.
11442 * Sadly the straps seem to be missing sometimes even for HDMI
11443 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
11444 * and VBT for the presence of the port. Additionally we can't
11445 * trust the port type the VBT declares as we've seen at least
11446 * HDMI ports that the VBT claim are DP or eDP.
11448 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
11449 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
11450 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
11451 has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B);
11452 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
11453 g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
11455 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
11456 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
11457 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
11458 has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C);
11459 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
11460 g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
11462 if (IS_CHERRYVIEW(dev_priv)) {
11464 * eDP not supported on port D,
11465 * so no need to worry about it
11467 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
11468 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
11469 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D);
11470 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
11471 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
11474 vlv_dsi_init(dev_priv);
11475 } else if (IS_PINEVIEW(dev_priv)) {
11476 intel_lvds_init(dev_priv);
11477 intel_crt_init(dev_priv);
11478 } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) {
11479 bool found = false;
11481 if (IS_MOBILE(dev_priv))
11482 intel_lvds_init(dev_priv);
11484 intel_crt_init(dev_priv);
11486 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
11487 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
11488 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
11489 if (!found && IS_G4X(dev_priv)) {
11490 drm_dbg_kms(&dev_priv->drm,
11491 "probing HDMI on SDVOB\n");
11492 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
11495 if (!found && IS_G4X(dev_priv))
11496 g4x_dp_init(dev_priv, DP_B, PORT_B);
11499 /* Before G4X SDVOC doesn't have its own detect register */
11501 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
11502 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");
11503 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
11506 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) {
11508 if (IS_G4X(dev_priv)) {
11509 drm_dbg_kms(&dev_priv->drm,
11510 "probing HDMI on SDVOC\n");
11511 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
11513 if (IS_G4X(dev_priv))
11514 g4x_dp_init(dev_priv, DP_C, PORT_C);
11517 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED))
11518 g4x_dp_init(dev_priv, DP_D, PORT_D);
11520 if (SUPPORTS_TV(dev_priv))
11521 intel_tv_init(dev_priv);
11522 } else if (DISPLAY_VER(dev_priv) == 2) {
11523 if (IS_I85X(dev_priv))
11524 intel_lvds_init(dev_priv);
11526 intel_crt_init(dev_priv);
11527 intel_dvo_init(dev_priv);
11530 for_each_intel_encoder(&dev_priv->drm, encoder) {
11531 encoder->base.possible_crtcs =
11532 intel_encoder_possible_crtcs(encoder);
11533 encoder->base.possible_clones =
11534 intel_encoder_possible_clones(encoder);
11537 intel_init_pch_refclk(dev_priv);
11539 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
11542 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
11544 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11546 drm_framebuffer_cleanup(fb);
11548 if (intel_fb_uses_dpt(fb))
11549 intel_dpt_destroy(intel_fb->dpt_vm);
11551 intel_frontbuffer_put(intel_fb->frontbuffer);
11556 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
11557 struct drm_file *file,
11558 unsigned int *handle)
11560 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11561 struct drm_i915_private *i915 = to_i915(obj->base.dev);
11563 if (i915_gem_object_is_userptr(obj)) {
11564 drm_dbg(&i915->drm,
11565 "attempting to use a userptr for a framebuffer, denied\n");
11569 return drm_gem_handle_create(file, &obj->base, handle);
11572 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
11573 struct drm_file *file,
11574 unsigned flags, unsigned color,
11575 struct drm_clip_rect *clips,
11576 unsigned num_clips)
11578 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11580 i915_gem_object_flush_if_display(obj);
11581 intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
11586 static const struct drm_framebuffer_funcs intel_fb_funcs = {
11587 .destroy = intel_user_framebuffer_destroy,
11588 .create_handle = intel_user_framebuffer_create_handle,
11589 .dirty = intel_user_framebuffer_dirty,
11592 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
11593 struct drm_i915_gem_object *obj,
11594 struct drm_mode_fb_cmd2 *mode_cmd)
11596 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
11597 struct drm_framebuffer *fb = &intel_fb->base;
11599 unsigned int tiling, stride;
11603 intel_fb->frontbuffer = intel_frontbuffer_get(obj);
11604 if (!intel_fb->frontbuffer)
11607 i915_gem_object_lock(obj, NULL);
11608 tiling = i915_gem_object_get_tiling(obj);
11609 stride = i915_gem_object_get_stride(obj);
11610 i915_gem_object_unlock(obj);
11612 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
11614 * If there's a fence, enforce that
11615 * the fb modifier and tiling mode match.
11617 if (tiling != I915_TILING_NONE &&
11618 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
11619 drm_dbg_kms(&dev_priv->drm,
11620 "tiling_mode doesn't match fb modifier\n");
11624 if (tiling == I915_TILING_X) {
11625 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
11626 } else if (tiling == I915_TILING_Y) {
11627 drm_dbg_kms(&dev_priv->drm,
11628 "No Y tiling for legacy addfb\n");
11633 if (!drm_any_plane_has_format(&dev_priv->drm,
11634 mode_cmd->pixel_format,
11635 mode_cmd->modifier[0])) {
11636 drm_dbg_kms(&dev_priv->drm,
11637 "unsupported pixel format %p4cc / modifier 0x%llx\n",
11638 &mode_cmd->pixel_format, mode_cmd->modifier[0]);
11643 * gen2/3 display engine uses the fence if present,
11644 * so the tiling mode must match the fb modifier exactly.
11646 if (DISPLAY_VER(dev_priv) < 4 &&
11647 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
11648 drm_dbg_kms(&dev_priv->drm,
11649 "tiling_mode must match fb modifier exactly on gen2/3\n");
11653 max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
11654 mode_cmd->modifier[0]);
11655 if (mode_cmd->pitches[0] > max_stride) {
11656 drm_dbg_kms(&dev_priv->drm,
11657 "%s pitch (%u) must be at most %d\n",
11658 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
11659 "tiled" : "linear",
11660 mode_cmd->pitches[0], max_stride);
11665 * If there's a fence, enforce that
11666 * the fb pitch and fence stride match.
11668 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
11669 drm_dbg_kms(&dev_priv->drm,
11670 "pitch (%d) must match tiling stride (%d)\n",
11671 mode_cmd->pitches[0], stride);
11675 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
11676 if (mode_cmd->offsets[0] != 0) {
11677 drm_dbg_kms(&dev_priv->drm,
11678 "plane 0 offset (0x%08x) must be 0\n",
11679 mode_cmd->offsets[0]);
11683 drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
11685 for (i = 0; i < fb->format->num_planes; i++) {
11686 u32 stride_alignment;
11688 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
11689 drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n",
11694 stride_alignment = intel_fb_stride_alignment(fb, i);
11695 if (fb->pitches[i] & (stride_alignment - 1)) {
11696 drm_dbg_kms(&dev_priv->drm,
11697 "plane %d pitch (%d) must be at least %u byte aligned\n",
11698 i, fb->pitches[i], stride_alignment);
11702 if (is_gen12_ccs_plane(fb, i) && !is_gen12_ccs_cc_plane(fb, i)) {
11703 int ccs_aux_stride = gen12_ccs_aux_stride(fb, i);
11705 if (fb->pitches[i] != ccs_aux_stride) {
11706 drm_dbg_kms(&dev_priv->drm,
11707 "ccs aux plane %d pitch (%d) must be %d\n",
11709 fb->pitches[i], ccs_aux_stride);
11714 /* TODO: Add POT stride remapping support for CCS formats as well. */
11715 if (IS_ALDERLAKE_P(dev_priv) &&
11716 mode_cmd->modifier[i] != DRM_FORMAT_MOD_LINEAR &&
11717 !intel_fb_needs_pot_stride_remap(intel_fb) &&
11718 !is_power_of_2(mode_cmd->pitches[i])) {
11719 drm_dbg_kms(&dev_priv->drm,
11720 "plane %d pitch (%d) must be power of two for tiled buffers\n",
11721 i, mode_cmd->pitches[i]);
11725 fb->obj[i] = &obj->base;
11728 ret = intel_fill_fb_info(dev_priv, intel_fb);
11732 if (intel_fb_uses_dpt(fb)) {
11733 struct i915_address_space *vm;
11735 vm = intel_dpt_create(intel_fb);
11741 intel_fb->dpt_vm = vm;
11744 ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
11746 drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret);
11753 intel_frontbuffer_put(intel_fb->frontbuffer);
11757 static struct drm_framebuffer *
11758 intel_user_framebuffer_create(struct drm_device *dev,
11759 struct drm_file *filp,
11760 const struct drm_mode_fb_cmd2 *user_mode_cmd)
11762 struct drm_framebuffer *fb;
11763 struct drm_i915_gem_object *obj;
11764 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
11765 struct drm_i915_private *i915;
11767 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
11769 return ERR_PTR(-ENOENT);
11771 /* object is backed with LMEM for discrete */
11772 i915 = to_i915(obj->base.dev);
11773 if (HAS_LMEM(i915) && !i915_gem_object_is_lmem(obj)) {
11774 /* object is "remote", not in local memory */
11775 i915_gem_object_put(obj);
11776 return ERR_PTR(-EREMOTE);
11779 fb = intel_framebuffer_create(obj, &mode_cmd);
11780 i915_gem_object_put(obj);
11785 static enum drm_mode_status
11786 intel_mode_valid(struct drm_device *dev,
11787 const struct drm_display_mode *mode)
11789 struct drm_i915_private *dev_priv = to_i915(dev);
11790 int hdisplay_max, htotal_max;
11791 int vdisplay_max, vtotal_max;
11794 * Can't reject DBLSCAN here because Xorg ddxen can add piles
11795 * of DBLSCAN modes to the output's mode list when they detect
11796 * the scaling mode property on the connector. And they don't
11797 * ask the kernel to validate those modes in any way until
11798 * modeset time at which point the client gets a protocol error.
11799 * So in order to not upset those clients we silently ignore the
11800 * DBLSCAN flag on such connectors. For other connectors we will
11801 * reject modes with the DBLSCAN flag in encoder->compute_config().
11802 * And we always reject DBLSCAN modes in connector->mode_valid()
11803 * as we never want such modes on the connector's mode list.
11806 if (mode->vscan > 1)
11807 return MODE_NO_VSCAN;
11809 if (mode->flags & DRM_MODE_FLAG_HSKEW)
11810 return MODE_H_ILLEGAL;
11812 if (mode->flags & (DRM_MODE_FLAG_CSYNC |
11813 DRM_MODE_FLAG_NCSYNC |
11814 DRM_MODE_FLAG_PCSYNC))
11817 if (mode->flags & (DRM_MODE_FLAG_BCAST |
11818 DRM_MODE_FLAG_PIXMUX |
11819 DRM_MODE_FLAG_CLKDIV2))
11822 /* Transcoder timing limits */
11823 if (DISPLAY_VER(dev_priv) >= 11) {
11824 hdisplay_max = 16384;
11825 vdisplay_max = 8192;
11826 htotal_max = 16384;
11828 } else if (DISPLAY_VER(dev_priv) >= 9 ||
11829 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
11830 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
11831 vdisplay_max = 4096;
11834 } else if (DISPLAY_VER(dev_priv) >= 3) {
11835 hdisplay_max = 4096;
11836 vdisplay_max = 4096;
11840 hdisplay_max = 2048;
11841 vdisplay_max = 2048;
11846 if (mode->hdisplay > hdisplay_max ||
11847 mode->hsync_start > htotal_max ||
11848 mode->hsync_end > htotal_max ||
11849 mode->htotal > htotal_max)
11850 return MODE_H_ILLEGAL;
11852 if (mode->vdisplay > vdisplay_max ||
11853 mode->vsync_start > vtotal_max ||
11854 mode->vsync_end > vtotal_max ||
11855 mode->vtotal > vtotal_max)
11856 return MODE_V_ILLEGAL;
11858 if (DISPLAY_VER(dev_priv) >= 5) {
11859 if (mode->hdisplay < 64 ||
11860 mode->htotal - mode->hdisplay < 32)
11861 return MODE_H_ILLEGAL;
11863 if (mode->vtotal - mode->vdisplay < 5)
11864 return MODE_V_ILLEGAL;
11866 if (mode->htotal - mode->hdisplay < 32)
11867 return MODE_H_ILLEGAL;
11869 if (mode->vtotal - mode->vdisplay < 3)
11870 return MODE_V_ILLEGAL;
11876 enum drm_mode_status
11877 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
11878 const struct drm_display_mode *mode,
11881 int plane_width_max, plane_height_max;
11884 * intel_mode_valid() should be
11885 * sufficient on older platforms.
11887 if (DISPLAY_VER(dev_priv) < 9)
11891 * Most people will probably want a fullscreen
11892 * plane so let's not advertize modes that are
11893 * too big for that.
11895 if (DISPLAY_VER(dev_priv) >= 11) {
11896 plane_width_max = 5120 << bigjoiner;
11897 plane_height_max = 4320;
11899 plane_width_max = 5120;
11900 plane_height_max = 4096;
11903 if (mode->hdisplay > plane_width_max)
11904 return MODE_H_ILLEGAL;
11906 if (mode->vdisplay > plane_height_max)
11907 return MODE_V_ILLEGAL;
11912 static const struct drm_mode_config_funcs intel_mode_funcs = {
11913 .fb_create = intel_user_framebuffer_create,
11914 .get_format_info = intel_get_format_info,
11915 .output_poll_changed = intel_fbdev_output_poll_changed,
11916 .mode_valid = intel_mode_valid,
11917 .atomic_check = intel_atomic_check,
11918 .atomic_commit = intel_atomic_commit,
11919 .atomic_state_alloc = intel_atomic_state_alloc,
11920 .atomic_state_clear = intel_atomic_state_clear,
11921 .atomic_state_free = intel_atomic_state_free,
11925 * intel_init_display_hooks - initialize the display modesetting hooks
11926 * @dev_priv: device private
11928 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
11930 if (!HAS_DISPLAY(dev_priv))
11933 intel_init_cdclk_hooks(dev_priv);
11934 intel_init_audio_hooks(dev_priv);
11936 intel_dpll_init_clock_hook(dev_priv);
11938 if (DISPLAY_VER(dev_priv) >= 9) {
11939 dev_priv->display.get_pipe_config = hsw_get_pipe_config;
11940 dev_priv->display.crtc_enable = hsw_crtc_enable;
11941 dev_priv->display.crtc_disable = hsw_crtc_disable;
11942 } else if (HAS_DDI(dev_priv)) {
11943 dev_priv->display.get_pipe_config = hsw_get_pipe_config;
11944 dev_priv->display.crtc_enable = hsw_crtc_enable;
11945 dev_priv->display.crtc_disable = hsw_crtc_disable;
11946 } else if (HAS_PCH_SPLIT(dev_priv)) {
11947 dev_priv->display.get_pipe_config = ilk_get_pipe_config;
11948 dev_priv->display.crtc_enable = ilk_crtc_enable;
11949 dev_priv->display.crtc_disable = ilk_crtc_disable;
11950 } else if (IS_CHERRYVIEW(dev_priv) ||
11951 IS_VALLEYVIEW(dev_priv)) {
11952 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11953 dev_priv->display.crtc_enable = valleyview_crtc_enable;
11954 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11956 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11957 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11958 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11961 intel_fdi_init_hook(dev_priv);
11963 if (DISPLAY_VER(dev_priv) >= 9) {
11964 dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables;
11965 dev_priv->display.get_initial_plane_config = skl_get_initial_plane_config;
11967 dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables;
11968 dev_priv->display.get_initial_plane_config = i9xx_get_initial_plane_config;
11973 void intel_modeset_init_hw(struct drm_i915_private *i915)
11975 struct intel_cdclk_state *cdclk_state;
11977 if (!HAS_DISPLAY(i915))
11980 cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state);
11982 intel_update_cdclk(i915);
11983 intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
11984 cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;
11987 static int sanitize_watermarks_add_affected(struct drm_atomic_state *state)
11989 struct drm_plane *plane;
11990 struct intel_crtc *crtc;
11992 for_each_intel_crtc(state->dev, crtc) {
11993 struct intel_crtc_state *crtc_state;
11995 crtc_state = intel_atomic_get_crtc_state(state, crtc);
11996 if (IS_ERR(crtc_state))
11997 return PTR_ERR(crtc_state);
11999 if (crtc_state->hw.active) {
12001 * Preserve the inherited flag to avoid
12002 * taking the full modeset path.
12004 crtc_state->inherited = true;
12008 drm_for_each_plane(plane, state->dev) {
12009 struct drm_plane_state *plane_state;
12011 plane_state = drm_atomic_get_plane_state(state, plane);
12012 if (IS_ERR(plane_state))
12013 return PTR_ERR(plane_state);
12020 * Calculate what we think the watermarks should be for the state we've read
12021 * out of the hardware and then immediately program those watermarks so that
12022 * we ensure the hardware settings match our internal state.
12024 * We can calculate what we think WM's should be by creating a duplicate of the
12025 * current state (which was constructed during hardware readout) and running it
12026 * through the atomic check code to calculate new watermark values in the
12029 static void sanitize_watermarks(struct drm_i915_private *dev_priv)
12031 struct drm_atomic_state *state;
12032 struct intel_atomic_state *intel_state;
12033 struct intel_crtc *crtc;
12034 struct intel_crtc_state *crtc_state;
12035 struct drm_modeset_acquire_ctx ctx;
12039 /* Only supported on platforms that use atomic watermark design */
12040 if (!dev_priv->display.optimize_watermarks)
12043 state = drm_atomic_state_alloc(&dev_priv->drm);
12044 if (drm_WARN_ON(&dev_priv->drm, !state))
12047 intel_state = to_intel_atomic_state(state);
12049 drm_modeset_acquire_init(&ctx, 0);
12052 state->acquire_ctx = &ctx;
12055 * Hardware readout is the only time we don't want to calculate
12056 * intermediate watermarks (since we don't trust the current
12059 if (!HAS_GMCH(dev_priv))
12060 intel_state->skip_intermediate_wm = true;
12062 ret = sanitize_watermarks_add_affected(state);
12066 ret = intel_atomic_check(&dev_priv->drm, state);
12070 /* Write calculated watermark values back */
12071 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
12072 crtc_state->wm.need_postvbl_update = true;
12073 dev_priv->display.optimize_watermarks(intel_state, crtc);
12075 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
12079 if (ret == -EDEADLK) {
12080 drm_atomic_state_clear(state);
12081 drm_modeset_backoff(&ctx);
12086 * If we fail here, it means that the hardware appears to be
12087 * programmed in a way that shouldn't be possible, given our
12088 * understanding of watermark requirements. This might mean a
12089 * mistake in the hardware readout code or a mistake in the
12090 * watermark calculations for a given platform. Raise a WARN
12091 * so that this is noticeable.
12093 * If this actually happens, we'll have to just leave the
12094 * BIOS-programmed watermarks untouched and hope for the best.
12096 drm_WARN(&dev_priv->drm, ret,
12097 "Could not determine valid watermarks for inherited state\n");
12099 drm_atomic_state_put(state);
12101 drm_modeset_drop_locks(&ctx);
12102 drm_modeset_acquire_fini(&ctx);
12105 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
12107 if (IS_IRONLAKE(dev_priv)) {
12109 intel_de_read(dev_priv, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
12111 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
12112 } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
12113 dev_priv->fdi_pll_freq = 270000;
12118 drm_dbg(&dev_priv->drm, "FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
12121 static int intel_initial_commit(struct drm_device *dev)
12123 struct drm_atomic_state *state = NULL;
12124 struct drm_modeset_acquire_ctx ctx;
12125 struct intel_crtc *crtc;
12128 state = drm_atomic_state_alloc(dev);
12132 drm_modeset_acquire_init(&ctx, 0);
12135 state->acquire_ctx = &ctx;
12137 for_each_intel_crtc(dev, crtc) {
12138 struct intel_crtc_state *crtc_state =
12139 intel_atomic_get_crtc_state(state, crtc);
12141 if (IS_ERR(crtc_state)) {
12142 ret = PTR_ERR(crtc_state);
12146 if (crtc_state->hw.active) {
12147 struct intel_encoder *encoder;
12150 * We've not yet detected sink capabilities
12151 * (audio,infoframes,etc.) and thus we don't want to
12152 * force a full state recomputation yet. We want that to
12153 * happen only for the first real commit from userspace.
12154 * So preserve the inherited flag for the time being.
12156 crtc_state->inherited = true;
12158 ret = drm_atomic_add_affected_planes(state, &crtc->base);
12163 * FIXME hack to force a LUT update to avoid the
12164 * plane update forcing the pipe gamma on without
12165 * having a proper LUT loaded. Remove once we
12166 * have readout for pipe gamma enable.
12168 crtc_state->uapi.color_mgmt_changed = true;
12170 for_each_intel_encoder_mask(dev, encoder,
12171 crtc_state->uapi.encoder_mask) {
12172 if (encoder->initial_fastset_check &&
12173 !encoder->initial_fastset_check(encoder, crtc_state)) {
12174 ret = drm_atomic_add_affected_connectors(state,
12183 ret = drm_atomic_commit(state);
12186 if (ret == -EDEADLK) {
12187 drm_atomic_state_clear(state);
12188 drm_modeset_backoff(&ctx);
12192 drm_atomic_state_put(state);
12194 drm_modeset_drop_locks(&ctx);
12195 drm_modeset_acquire_fini(&ctx);
12200 static void intel_mode_config_init(struct drm_i915_private *i915)
12202 struct drm_mode_config *mode_config = &i915->drm.mode_config;
12204 drm_mode_config_init(&i915->drm);
12205 INIT_LIST_HEAD(&i915->global_obj_list);
12207 mode_config->min_width = 0;
12208 mode_config->min_height = 0;
12210 mode_config->preferred_depth = 24;
12211 mode_config->prefer_shadow = 1;
12213 mode_config->funcs = &intel_mode_funcs;
12215 mode_config->async_page_flip = has_async_flips(i915);
12218 * Maximum framebuffer dimensions, chosen to match
12219 * the maximum render engine surface size on gen4+.
12221 if (DISPLAY_VER(i915) >= 7) {
12222 mode_config->max_width = 16384;
12223 mode_config->max_height = 16384;
12224 } else if (DISPLAY_VER(i915) >= 4) {
12225 mode_config->max_width = 8192;
12226 mode_config->max_height = 8192;
12227 } else if (DISPLAY_VER(i915) == 3) {
12228 mode_config->max_width = 4096;
12229 mode_config->max_height = 4096;
12231 mode_config->max_width = 2048;
12232 mode_config->max_height = 2048;
12235 if (IS_I845G(i915) || IS_I865G(i915)) {
12236 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512;
12237 mode_config->cursor_height = 1023;
12238 } else if (IS_I830(i915) || IS_I85X(i915) ||
12239 IS_I915G(i915) || IS_I915GM(i915)) {
12240 mode_config->cursor_width = 64;
12241 mode_config->cursor_height = 64;
12243 mode_config->cursor_width = 256;
12244 mode_config->cursor_height = 256;
12248 static void intel_mode_config_cleanup(struct drm_i915_private *i915)
12250 intel_atomic_global_obj_cleanup(i915);
12251 drm_mode_config_cleanup(&i915->drm);
12254 static void plane_config_fini(struct intel_initial_plane_config *plane_config)
12256 if (plane_config->fb) {
12257 struct drm_framebuffer *fb = &plane_config->fb->base;
12259 /* We may only have the stub and not a full framebuffer */
12260 if (drm_framebuffer_read_refcount(fb))
12261 drm_framebuffer_put(fb);
12266 if (plane_config->vma)
12267 i915_vma_put(plane_config->vma);
12270 /* part #1: call before irq install */
12271 int intel_modeset_init_noirq(struct drm_i915_private *i915)
12275 if (i915_inject_probe_failure(i915))
12278 if (HAS_DISPLAY(i915)) {
12279 ret = drm_vblank_init(&i915->drm,
12280 INTEL_NUM_PIPES(i915));
12285 intel_bios_init(i915);
12287 ret = intel_vga_register(i915);
12291 /* FIXME: completely on the wrong abstraction layer */
12292 intel_power_domains_init_hw(i915, false);
12294 if (!HAS_DISPLAY(i915))
12297 intel_dmc_ucode_init(i915);
12299 i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
12300 i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
12301 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
12303 i915->framestart_delay = 1; /* 1-4 */
12305 i915->window2_delay = 0; /* No DSB so no window2 delay */
12307 intel_mode_config_init(i915);
12309 ret = intel_cdclk_init(i915);
12311 goto cleanup_vga_client_pw_domain_dmc;
12313 ret = intel_dbuf_init(i915);
12315 goto cleanup_vga_client_pw_domain_dmc;
12317 ret = intel_bw_init(i915);
12319 goto cleanup_vga_client_pw_domain_dmc;
12321 init_llist_head(&i915->atomic_helper.free_list);
12322 INIT_WORK(&i915->atomic_helper.free_work,
12323 intel_atomic_helper_free_state_worker);
12325 intel_init_quirks(i915);
12327 intel_fbc_init(i915);
12331 cleanup_vga_client_pw_domain_dmc:
12332 intel_dmc_ucode_fini(i915);
12333 intel_power_domains_driver_remove(i915);
12334 intel_vga_unregister(i915);
12336 intel_bios_driver_remove(i915);
12341 /* part #2: call after irq install, but before gem init */
12342 int intel_modeset_init_nogem(struct drm_i915_private *i915)
12344 struct drm_device *dev = &i915->drm;
12346 struct intel_crtc *crtc;
12349 if (!HAS_DISPLAY(i915))
12352 intel_init_pm(i915);
12354 intel_panel_sanitize_ssc(i915);
12356 intel_pps_setup(i915);
12358 intel_gmbus_setup(i915);
12360 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n",
12361 INTEL_NUM_PIPES(i915),
12362 INTEL_NUM_PIPES(i915) > 1 ? "s" : "");
12364 for_each_pipe(i915, pipe) {
12365 ret = intel_crtc_init(i915, pipe);
12367 intel_mode_config_cleanup(i915);
12372 intel_plane_possible_crtcs_init(i915);
12373 intel_shared_dpll_init(dev);
12374 intel_update_fdi_pll_freq(i915);
12376 intel_update_czclk(i915);
12377 intel_modeset_init_hw(i915);
12378 intel_dpll_update_ref_clks(i915);
12380 intel_hdcp_component_init(i915);
12382 if (i915->max_cdclk_freq == 0)
12383 intel_update_max_cdclk(i915);
12386 * If the platform has HTI, we need to find out whether it has reserved
12387 * any display resources before we create our display outputs.
12389 if (INTEL_INFO(i915)->display.has_hti)
12390 i915->hti_state = intel_de_read(i915, HDPORT_STATE);
12392 /* Just disable it once at startup */
12393 intel_vga_disable(i915);
12394 intel_setup_outputs(i915);
12396 drm_modeset_lock_all(dev);
12397 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
12398 drm_modeset_unlock_all(dev);
12400 for_each_intel_crtc(dev, crtc) {
12401 struct intel_initial_plane_config plane_config = {};
12403 if (!to_intel_crtc_state(crtc->base.state)->uapi.active)
12407 * Note that reserving the BIOS fb up front prevents us
12408 * from stuffing other stolen allocations like the ring
12409 * on top. This prevents some ugliness at boot time, and
12410 * can even allow for smooth boot transitions if the BIOS
12411 * fb is large enough for the active pipe configuration.
12413 i915->display.get_initial_plane_config(crtc, &plane_config);
12416 * If the fb is shared between multiple heads, we'll
12417 * just get the first one.
12419 intel_find_initial_plane_obj(crtc, &plane_config);
12421 plane_config_fini(&plane_config);
12425 * Make sure hardware watermarks really match the state we read out.
12426 * Note that we need to do this after reconstructing the BIOS fb's
12427 * since the watermark calculation done here will use pstate->fb.
12429 if (!HAS_GMCH(i915))
12430 sanitize_watermarks(i915);
12435 /* part #3: call after gem init */
12436 int intel_modeset_init(struct drm_i915_private *i915)
12440 if (!HAS_DISPLAY(i915))
12444 * Force all active planes to recompute their states. So that on
12445 * mode_setcrtc after probe, all the intel_plane_state variables
12446 * are already calculated and there is no assert_plane warnings
12449 ret = intel_initial_commit(&i915->drm);
12451 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret);
12453 intel_overlay_setup(i915);
12455 ret = intel_fbdev_init(&i915->drm);
12459 /* Only enable hotplug handling once the fbdev is fully set up. */
12460 intel_hpd_init(i915);
12461 intel_hpd_poll_disable(i915);
12463 intel_init_ipc(i915);
12468 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
12470 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12471 /* 640x480@60Hz, ~25175 kHz */
12472 struct dpll clock = {
12482 drm_WARN_ON(&dev_priv->drm,
12483 i9xx_calc_dpll_params(48000, &clock) != 25154);
12485 drm_dbg_kms(&dev_priv->drm,
12486 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
12487 pipe_name(pipe), clock.vco, clock.dot);
12489 fp = i9xx_dpll_compute_fp(&clock);
12490 dpll = DPLL_DVO_2X_MODE |
12491 DPLL_VGA_MODE_DIS |
12492 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
12493 PLL_P2_DIVIDE_BY_4 |
12494 PLL_REF_INPUT_DREFCLK |
12497 intel_de_write(dev_priv, FP0(pipe), fp);
12498 intel_de_write(dev_priv, FP1(pipe), fp);
12500 intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
12501 intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
12502 intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
12503 intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
12504 intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
12505 intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
12506 intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
12509 * Apparently we need to have VGA mode enabled prior to changing
12510 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
12511 * dividers, even though the register value does change.
12513 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
12514 intel_de_write(dev_priv, DPLL(pipe), dpll);
12516 /* Wait for the clocks to stabilize. */
12517 intel_de_posting_read(dev_priv, DPLL(pipe));
12520 /* The pixel multiplier can only be updated once the
12521 * DPLL is enabled and the clocks are stable.
12523 * So write it again.
12525 intel_de_write(dev_priv, DPLL(pipe), dpll);
12527 /* We do this three times for luck */
12528 for (i = 0; i < 3 ; i++) {
12529 intel_de_write(dev_priv, DPLL(pipe), dpll);
12530 intel_de_posting_read(dev_priv, DPLL(pipe));
12531 udelay(150); /* wait for warmup */
12534 intel_de_write(dev_priv, PIPECONF(pipe),
12535 PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
12536 intel_de_posting_read(dev_priv, PIPECONF(pipe));
12538 intel_wait_for_pipe_scanline_moving(crtc);
12541 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
12543 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12545 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",
12548 drm_WARN_ON(&dev_priv->drm,
12549 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) &
12550 DISPLAY_PLANE_ENABLE);
12551 drm_WARN_ON(&dev_priv->drm,
12552 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) &
12553 DISPLAY_PLANE_ENABLE);
12554 drm_WARN_ON(&dev_priv->drm,
12555 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) &
12556 DISPLAY_PLANE_ENABLE);
12557 drm_WARN_ON(&dev_priv->drm,
12558 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE);
12559 drm_WARN_ON(&dev_priv->drm,
12560 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE);
12562 intel_de_write(dev_priv, PIPECONF(pipe), 0);
12563 intel_de_posting_read(dev_priv, PIPECONF(pipe));
12565 intel_wait_for_pipe_scanline_stopped(crtc);
12567 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
12568 intel_de_posting_read(dev_priv, DPLL(pipe));
12572 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
12574 struct intel_crtc *crtc;
12576 if (DISPLAY_VER(dev_priv) >= 4)
12579 for_each_intel_crtc(&dev_priv->drm, crtc) {
12580 struct intel_plane *plane =
12581 to_intel_plane(crtc->base.primary);
12582 struct intel_crtc *plane_crtc;
12585 if (!plane->get_hw_state(plane, &pipe))
12588 if (pipe == crtc->pipe)
12591 drm_dbg_kms(&dev_priv->drm,
12592 "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
12593 plane->base.base.id, plane->base.name);
12595 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12596 intel_plane_disable_noatomic(plane_crtc, plane);
12600 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
12602 struct drm_device *dev = crtc->base.dev;
12603 struct intel_encoder *encoder;
12605 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
12611 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
12613 struct drm_device *dev = encoder->base.dev;
12614 struct intel_connector *connector;
12616 for_each_connector_on_encoder(dev, &encoder->base, connector)
12622 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
12623 enum pipe pch_transcoder)
12625 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
12626 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
12629 static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc_state)
12631 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12632 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12633 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
12635 if (DISPLAY_VER(dev_priv) >= 9 ||
12636 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
12637 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
12640 if (transcoder_is_dsi(cpu_transcoder))
12643 val = intel_de_read(dev_priv, reg);
12644 val &= ~HSW_FRAME_START_DELAY_MASK;
12645 val |= HSW_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
12646 intel_de_write(dev_priv, reg, val);
12648 i915_reg_t reg = PIPECONF(cpu_transcoder);
12651 val = intel_de_read(dev_priv, reg);
12652 val &= ~PIPECONF_FRAME_START_DELAY_MASK;
12653 val |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
12654 intel_de_write(dev_priv, reg, val);
12657 if (!crtc_state->has_pch_encoder)
12660 if (HAS_PCH_IBX(dev_priv)) {
12661 i915_reg_t reg = PCH_TRANSCONF(crtc->pipe);
12664 val = intel_de_read(dev_priv, reg);
12665 val &= ~TRANS_FRAME_START_DELAY_MASK;
12666 val |= TRANS_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
12667 intel_de_write(dev_priv, reg, val);
12669 enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc);
12670 i915_reg_t reg = TRANS_CHICKEN2(pch_transcoder);
12673 val = intel_de_read(dev_priv, reg);
12674 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
12675 val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
12676 intel_de_write(dev_priv, reg, val);
12680 static void intel_sanitize_crtc(struct intel_crtc *crtc,
12681 struct drm_modeset_acquire_ctx *ctx)
12683 struct drm_device *dev = crtc->base.dev;
12684 struct drm_i915_private *dev_priv = to_i915(dev);
12685 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
12687 if (crtc_state->hw.active) {
12688 struct intel_plane *plane;
12690 /* Clear any frame start delays used for debugging left by the BIOS */
12691 intel_sanitize_frame_start_delay(crtc_state);
12693 /* Disable everything but the primary plane */
12694 for_each_intel_plane_on_crtc(dev, crtc, plane) {
12695 const struct intel_plane_state *plane_state =
12696 to_intel_plane_state(plane->base.state);
12698 if (plane_state->uapi.visible &&
12699 plane->base.type != DRM_PLANE_TYPE_PRIMARY)
12700 intel_plane_disable_noatomic(crtc, plane);
12704 * Disable any background color set by the BIOS, but enable the
12705 * gamma and CSC to match how we program our planes.
12707 if (DISPLAY_VER(dev_priv) >= 9)
12708 intel_de_write(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe),
12709 SKL_BOTTOM_COLOR_GAMMA_ENABLE | SKL_BOTTOM_COLOR_CSC_ENABLE);
12712 /* Adjust the state of the output pipe according to whether we
12713 * have active connectors/encoders. */
12714 if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) &&
12715 !crtc_state->bigjoiner_slave)
12716 intel_crtc_disable_noatomic(crtc, ctx);
12718 if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
12720 * We start out with underrun reporting disabled to avoid races.
12721 * For correct bookkeeping mark this on active crtcs.
12723 * Also on gmch platforms we dont have any hardware bits to
12724 * disable the underrun reporting. Which means we need to start
12725 * out with underrun reporting disabled also on inactive pipes,
12726 * since otherwise we'll complain about the garbage we read when
12727 * e.g. coming up after runtime pm.
12729 * No protection against concurrent access is required - at
12730 * worst a fifo underrun happens which also sets this to false.
12732 crtc->cpu_fifo_underrun_disabled = true;
12734 * We track the PCH trancoder underrun reporting state
12735 * within the crtc. With crtc for pipe A housing the underrun
12736 * reporting state for PCH transcoder A, crtc for pipe B housing
12737 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
12738 * and marking underrun reporting as disabled for the non-existing
12739 * PCH transcoders B and C would prevent enabling the south
12740 * error interrupt (see cpt_can_enable_serr_int()).
12742 if (has_pch_trancoder(dev_priv, crtc->pipe))
12743 crtc->pch_fifo_underrun_disabled = true;
12747 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
12749 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
12752 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
12753 * the hardware when a high res displays plugged in. DPLL P
12754 * divider is zero, and the pipe timings are bonkers. We'll
12755 * try to disable everything in that case.
12757 * FIXME would be nice to be able to sanitize this state
12758 * without several WARNs, but for now let's take the easy
12761 return IS_SANDYBRIDGE(dev_priv) &&
12762 crtc_state->hw.active &&
12763 crtc_state->shared_dpll &&
12764 crtc_state->port_clock == 0;
12767 static void intel_sanitize_encoder(struct intel_encoder *encoder)
12769 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
12770 struct intel_connector *connector;
12771 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
12772 struct intel_crtc_state *crtc_state = crtc ?
12773 to_intel_crtc_state(crtc->base.state) : NULL;
12775 /* We need to check both for a crtc link (meaning that the
12776 * encoder is active and trying to read from a pipe) and the
12777 * pipe itself being active. */
12778 bool has_active_crtc = crtc_state &&
12779 crtc_state->hw.active;
12781 if (crtc_state && has_bogus_dpll_config(crtc_state)) {
12782 drm_dbg_kms(&dev_priv->drm,
12783 "BIOS has misprogrammed the hardware. Disabling pipe %c\n",
12784 pipe_name(crtc->pipe));
12785 has_active_crtc = false;
12788 connector = intel_encoder_find_connector(encoder);
12789 if (connector && !has_active_crtc) {
12790 drm_dbg_kms(&dev_priv->drm,
12791 "[ENCODER:%d:%s] has active connectors but no active pipe!\n",
12792 encoder->base.base.id,
12793 encoder->base.name);
12795 /* Connector is active, but has no active pipe. This is
12796 * fallout from our resume register restoring. Disable
12797 * the encoder manually again. */
12799 struct drm_encoder *best_encoder;
12801 drm_dbg_kms(&dev_priv->drm,
12802 "[ENCODER:%d:%s] manually disabled\n",
12803 encoder->base.base.id,
12804 encoder->base.name);
12806 /* avoid oopsing in case the hooks consult best_encoder */
12807 best_encoder = connector->base.state->best_encoder;
12808 connector->base.state->best_encoder = &encoder->base;
12810 /* FIXME NULL atomic state passed! */
12811 if (encoder->disable)
12812 encoder->disable(NULL, encoder, crtc_state,
12813 connector->base.state);
12814 if (encoder->post_disable)
12815 encoder->post_disable(NULL, encoder, crtc_state,
12816 connector->base.state);
12818 connector->base.state->best_encoder = best_encoder;
12820 encoder->base.crtc = NULL;
12822 /* Inconsistent output/port/pipe state happens presumably due to
12823 * a bug in one of the get_hw_state functions. Or someplace else
12824 * in our code, like the register restore mess on resume. Clamp
12825 * things to off as a safer default. */
12827 connector->base.dpms = DRM_MODE_DPMS_OFF;
12828 connector->base.encoder = NULL;
12831 /* notify opregion of the sanitized encoder state */
12832 intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
12834 if (HAS_DDI(dev_priv))
12835 intel_ddi_sanitize_encoder_pll_mapping(encoder);
12838 /* FIXME read out full plane state for all planes */
12839 static void readout_plane_state(struct drm_i915_private *dev_priv)
12841 struct intel_plane *plane;
12842 struct intel_crtc *crtc;
12844 for_each_intel_plane(&dev_priv->drm, plane) {
12845 struct intel_plane_state *plane_state =
12846 to_intel_plane_state(plane->base.state);
12847 struct intel_crtc_state *crtc_state;
12848 enum pipe pipe = PIPE_A;
12851 visible = plane->get_hw_state(plane, &pipe);
12853 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12854 crtc_state = to_intel_crtc_state(crtc->base.state);
12856 intel_set_plane_visible(crtc_state, plane_state, visible);
12858 drm_dbg_kms(&dev_priv->drm,
12859 "[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
12860 plane->base.base.id, plane->base.name,
12861 enableddisabled(visible), pipe_name(pipe));
12864 for_each_intel_crtc(&dev_priv->drm, crtc) {
12865 struct intel_crtc_state *crtc_state =
12866 to_intel_crtc_state(crtc->base.state);
12868 fixup_plane_bitmasks(crtc_state);
12872 static void intel_modeset_readout_hw_state(struct drm_device *dev)
12874 struct drm_i915_private *dev_priv = to_i915(dev);
12875 struct intel_cdclk_state *cdclk_state =
12876 to_intel_cdclk_state(dev_priv->cdclk.obj.state);
12877 struct intel_dbuf_state *dbuf_state =
12878 to_intel_dbuf_state(dev_priv->dbuf.obj.state);
12880 struct intel_crtc *crtc;
12881 struct intel_encoder *encoder;
12882 struct intel_connector *connector;
12883 struct drm_connector_list_iter conn_iter;
12884 u8 active_pipes = 0;
12886 for_each_intel_crtc(dev, crtc) {
12887 struct intel_crtc_state *crtc_state =
12888 to_intel_crtc_state(crtc->base.state);
12890 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
12891 intel_crtc_free_hw_state(crtc_state);
12892 intel_crtc_state_reset(crtc_state, crtc);
12894 intel_crtc_get_pipe_config(crtc_state);
12896 crtc_state->hw.enable = crtc_state->hw.active;
12898 crtc->base.enabled = crtc_state->hw.enable;
12899 crtc->active = crtc_state->hw.active;
12901 if (crtc_state->hw.active)
12902 active_pipes |= BIT(crtc->pipe);
12904 drm_dbg_kms(&dev_priv->drm,
12905 "[CRTC:%d:%s] hw state readout: %s\n",
12906 crtc->base.base.id, crtc->base.name,
12907 enableddisabled(crtc_state->hw.active));
12910 dev_priv->active_pipes = cdclk_state->active_pipes =
12911 dbuf_state->active_pipes = active_pipes;
12913 readout_plane_state(dev_priv);
12915 for_each_intel_encoder(dev, encoder) {
12918 if (encoder->get_hw_state(encoder, &pipe)) {
12919 struct intel_crtc_state *crtc_state;
12921 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12922 crtc_state = to_intel_crtc_state(crtc->base.state);
12924 encoder->base.crtc = &crtc->base;
12925 intel_encoder_get_config(encoder, crtc_state);
12926 if (encoder->sync_state)
12927 encoder->sync_state(encoder, crtc_state);
12929 /* read out to slave crtc as well for bigjoiner */
12930 if (crtc_state->bigjoiner) {
12931 /* encoder should read be linked to bigjoiner master */
12932 WARN_ON(crtc_state->bigjoiner_slave);
12934 crtc = crtc_state->bigjoiner_linked_crtc;
12935 crtc_state = to_intel_crtc_state(crtc->base.state);
12936 intel_encoder_get_config(encoder, crtc_state);
12939 encoder->base.crtc = NULL;
12942 drm_dbg_kms(&dev_priv->drm,
12943 "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
12944 encoder->base.base.id, encoder->base.name,
12945 enableddisabled(encoder->base.crtc),
12949 intel_dpll_readout_hw_state(dev_priv);
12951 drm_connector_list_iter_begin(dev, &conn_iter);
12952 for_each_intel_connector_iter(connector, &conn_iter) {
12953 if (connector->get_hw_state(connector)) {
12954 struct intel_crtc_state *crtc_state;
12955 struct intel_crtc *crtc;
12957 connector->base.dpms = DRM_MODE_DPMS_ON;
12959 encoder = intel_attached_encoder(connector);
12960 connector->base.encoder = &encoder->base;
12962 crtc = to_intel_crtc(encoder->base.crtc);
12963 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
12965 if (crtc_state && crtc_state->hw.active) {
12967 * This has to be done during hardware readout
12968 * because anything calling .crtc_disable may
12969 * rely on the connector_mask being accurate.
12971 crtc_state->uapi.connector_mask |=
12972 drm_connector_mask(&connector->base);
12973 crtc_state->uapi.encoder_mask |=
12974 drm_encoder_mask(&encoder->base);
12977 connector->base.dpms = DRM_MODE_DPMS_OFF;
12978 connector->base.encoder = NULL;
12980 drm_dbg_kms(&dev_priv->drm,
12981 "[CONNECTOR:%d:%s] hw state readout: %s\n",
12982 connector->base.base.id, connector->base.name,
12983 enableddisabled(connector->base.encoder));
12985 drm_connector_list_iter_end(&conn_iter);
12987 for_each_intel_crtc(dev, crtc) {
12988 struct intel_bw_state *bw_state =
12989 to_intel_bw_state(dev_priv->bw_obj.state);
12990 struct intel_crtc_state *crtc_state =
12991 to_intel_crtc_state(crtc->base.state);
12992 struct intel_plane *plane;
12995 if (crtc_state->bigjoiner_slave)
12998 if (crtc_state->hw.active) {
13000 * The initial mode needs to be set in order to keep
13001 * the atomic core happy. It wants a valid mode if the
13002 * crtc's enabled, so we do the above call.
13004 * But we don't set all the derived state fully, hence
13005 * set a flag to indicate that a full recalculation is
13006 * needed on the next commit.
13008 crtc_state->inherited = true;
13010 intel_crtc_update_active_timings(crtc_state);
13012 intel_crtc_copy_hw_to_uapi_state(crtc_state);
13015 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
13016 const struct intel_plane_state *plane_state =
13017 to_intel_plane_state(plane->base.state);
13020 * FIXME don't have the fb yet, so can't
13021 * use intel_plane_data_rate() :(
13023 if (plane_state->uapi.visible)
13024 crtc_state->data_rate[plane->id] =
13025 4 * crtc_state->pixel_rate;
13027 * FIXME don't have the fb yet, so can't
13028 * use plane->min_cdclk() :(
13030 if (plane_state->uapi.visible && plane->min_cdclk) {
13031 if (crtc_state->double_wide || DISPLAY_VER(dev_priv) >= 10)
13032 crtc_state->min_cdclk[plane->id] =
13033 DIV_ROUND_UP(crtc_state->pixel_rate, 2);
13035 crtc_state->min_cdclk[plane->id] =
13036 crtc_state->pixel_rate;
13038 drm_dbg_kms(&dev_priv->drm,
13039 "[PLANE:%d:%s] min_cdclk %d kHz\n",
13040 plane->base.base.id, plane->base.name,
13041 crtc_state->min_cdclk[plane->id]);
13044 if (crtc_state->hw.active) {
13045 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
13046 if (drm_WARN_ON(dev, min_cdclk < 0))
13050 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
13051 cdclk_state->min_voltage_level[crtc->pipe] =
13052 crtc_state->min_voltage_level;
13054 intel_bw_crtc_update(bw_state, crtc_state);
13056 intel_pipe_config_sanity_check(dev_priv, crtc_state);
13058 /* discard our incomplete slave state, copy it from master */
13059 if (crtc_state->bigjoiner && crtc_state->hw.active) {
13060 struct intel_crtc *slave = crtc_state->bigjoiner_linked_crtc;
13061 struct intel_crtc_state *slave_crtc_state =
13062 to_intel_crtc_state(slave->base.state);
13064 copy_bigjoiner_crtc_state(slave_crtc_state, crtc_state);
13065 slave->base.mode = crtc->base.mode;
13067 cdclk_state->min_cdclk[slave->pipe] = min_cdclk;
13068 cdclk_state->min_voltage_level[slave->pipe] =
13069 crtc_state->min_voltage_level;
13071 for_each_intel_plane_on_crtc(&dev_priv->drm, slave, plane) {
13072 const struct intel_plane_state *plane_state =
13073 to_intel_plane_state(plane->base.state);
13076 * FIXME don't have the fb yet, so can't
13077 * use intel_plane_data_rate() :(
13079 if (plane_state->uapi.visible)
13080 crtc_state->data_rate[plane->id] =
13081 4 * crtc_state->pixel_rate;
13083 crtc_state->data_rate[plane->id] = 0;
13086 intel_bw_crtc_update(bw_state, slave_crtc_state);
13087 drm_calc_timestamping_constants(&slave->base,
13088 &slave_crtc_state->hw.adjusted_mode);
13094 get_encoder_power_domains(struct drm_i915_private *dev_priv)
13096 struct intel_encoder *encoder;
13098 for_each_intel_encoder(&dev_priv->drm, encoder) {
13099 struct intel_crtc_state *crtc_state;
13101 if (!encoder->get_power_domains)
13105 * MST-primary and inactive encoders don't have a crtc state
13106 * and neither of these require any power domain references.
13108 if (!encoder->base.crtc)
13111 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
13112 encoder->get_power_domains(encoder, crtc_state);
13116 static void intel_early_display_was(struct drm_i915_private *dev_priv)
13119 * Display WA #1185 WaDisableDARBFClkGating:cnl,glk,icl,ehl,tgl
13120 * Also known as Wa_14010480278.
13122 if (IS_DISPLAY_VER(dev_priv, 10, 12))
13123 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0,
13124 intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS);
13126 if (IS_HASWELL(dev_priv)) {
13128 * WaRsPkgCStateDisplayPMReq:hsw
13129 * System hang if this isn't done before disabling all planes!
13131 intel_de_write(dev_priv, CHICKEN_PAR1_1,
13132 intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
13135 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) {
13136 /* Display WA #1142:kbl,cfl,cml */
13137 intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
13138 KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22);
13139 intel_de_rmw(dev_priv, CHICKEN_MISC_2,
13140 KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14,
13141 KBL_ARB_FILL_SPARE_14);
13145 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
13146 enum port port, i915_reg_t hdmi_reg)
13148 u32 val = intel_de_read(dev_priv, hdmi_reg);
13150 if (val & SDVO_ENABLE ||
13151 (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
13154 drm_dbg_kms(&dev_priv->drm,
13155 "Sanitizing transcoder select for HDMI %c\n",
13158 val &= ~SDVO_PIPE_SEL_MASK;
13159 val |= SDVO_PIPE_SEL(PIPE_A);
13161 intel_de_write(dev_priv, hdmi_reg, val);
13164 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
13165 enum port port, i915_reg_t dp_reg)
13167 u32 val = intel_de_read(dev_priv, dp_reg);
13169 if (val & DP_PORT_EN ||
13170 (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
13173 drm_dbg_kms(&dev_priv->drm,
13174 "Sanitizing transcoder select for DP %c\n",
13177 val &= ~DP_PIPE_SEL_MASK;
13178 val |= DP_PIPE_SEL(PIPE_A);
13180 intel_de_write(dev_priv, dp_reg, val);
13183 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
13186 * The BIOS may select transcoder B on some of the PCH
13187 * ports even it doesn't enable the port. This would trip
13188 * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
13189 * Sanitize the transcoder select bits to prevent that. We
13190 * assume that the BIOS never actually enabled the port,
13191 * because if it did we'd actually have to toggle the port
13192 * on and back off to make the transcoder A select stick
13193 * (see. intel_dp_link_down(), intel_disable_hdmi(),
13194 * intel_disable_sdvo()).
13196 ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
13197 ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
13198 ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
13200 /* PCH SDVOB multiplex with HDMIB */
13201 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
13202 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
13203 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
13206 /* Scan out the current hw modeset state,
13207 * and sanitizes it to the current state
13210 intel_modeset_setup_hw_state(struct drm_device *dev,
13211 struct drm_modeset_acquire_ctx *ctx)
13213 struct drm_i915_private *dev_priv = to_i915(dev);
13214 struct intel_encoder *encoder;
13215 struct intel_crtc *crtc;
13216 intel_wakeref_t wakeref;
13218 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
13220 intel_early_display_was(dev_priv);
13221 intel_modeset_readout_hw_state(dev);
13223 /* HW state is read out, now we need to sanitize this mess. */
13225 /* Sanitize the TypeC port mode upfront, encoders depend on this */
13226 for_each_intel_encoder(dev, encoder) {
13227 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
13229 /* We need to sanitize only the MST primary port. */
13230 if (encoder->type != INTEL_OUTPUT_DP_MST &&
13231 intel_phy_is_tc(dev_priv, phy))
13232 intel_tc_port_sanitize(enc_to_dig_port(encoder));
13235 get_encoder_power_domains(dev_priv);
13237 if (HAS_PCH_IBX(dev_priv))
13238 ibx_sanitize_pch_ports(dev_priv);
13241 * intel_sanitize_plane_mapping() may need to do vblank
13242 * waits, so we need vblank interrupts restored beforehand.
13244 for_each_intel_crtc(&dev_priv->drm, crtc) {
13245 struct intel_crtc_state *crtc_state =
13246 to_intel_crtc_state(crtc->base.state);
13248 drm_crtc_vblank_reset(&crtc->base);
13250 if (crtc_state->hw.active)
13251 intel_crtc_vblank_on(crtc_state);
13254 intel_sanitize_plane_mapping(dev_priv);
13256 for_each_intel_encoder(dev, encoder)
13257 intel_sanitize_encoder(encoder);
13259 for_each_intel_crtc(&dev_priv->drm, crtc) {
13260 struct intel_crtc_state *crtc_state =
13261 to_intel_crtc_state(crtc->base.state);
13263 intel_sanitize_crtc(crtc, ctx);
13264 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
13267 intel_modeset_update_connector_atomic_state(dev);
13269 intel_dpll_sanitize_state(dev_priv);
13271 if (IS_G4X(dev_priv)) {
13272 g4x_wm_get_hw_state(dev_priv);
13273 g4x_wm_sanitize(dev_priv);
13274 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
13275 vlv_wm_get_hw_state(dev_priv);
13276 vlv_wm_sanitize(dev_priv);
13277 } else if (DISPLAY_VER(dev_priv) >= 9) {
13278 skl_wm_get_hw_state(dev_priv);
13279 } else if (HAS_PCH_SPLIT(dev_priv)) {
13280 ilk_wm_get_hw_state(dev_priv);
13283 for_each_intel_crtc(dev, crtc) {
13284 struct intel_crtc_state *crtc_state =
13285 to_intel_crtc_state(crtc->base.state);
13288 put_domains = modeset_get_crtc_power_domains(crtc_state);
13289 if (drm_WARN_ON(dev, put_domains))
13290 modeset_put_crtc_power_domains(crtc, put_domains);
13293 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
13296 void intel_display_resume(struct drm_device *dev)
13298 struct drm_i915_private *dev_priv = to_i915(dev);
13299 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
13300 struct drm_modeset_acquire_ctx ctx;
13303 if (!HAS_DISPLAY(dev_priv))
13306 dev_priv->modeset_restore_state = NULL;
13308 state->acquire_ctx = &ctx;
13310 drm_modeset_acquire_init(&ctx, 0);
13313 ret = drm_modeset_lock_all_ctx(dev, &ctx);
13314 if (ret != -EDEADLK)
13317 drm_modeset_backoff(&ctx);
13321 ret = __intel_display_resume(dev, state, &ctx);
13323 intel_enable_ipc(dev_priv);
13324 drm_modeset_drop_locks(&ctx);
13325 drm_modeset_acquire_fini(&ctx);
13328 drm_err(&dev_priv->drm,
13329 "Restoring old state failed with %i\n", ret);
13331 drm_atomic_state_put(state);
13334 static void intel_hpd_poll_fini(struct drm_i915_private *i915)
13336 struct intel_connector *connector;
13337 struct drm_connector_list_iter conn_iter;
13339 /* Kill all the work that may have been queued by hpd. */
13340 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
13341 for_each_intel_connector_iter(connector, &conn_iter) {
13342 if (connector->modeset_retry_work.func)
13343 cancel_work_sync(&connector->modeset_retry_work);
13344 if (connector->hdcp.shim) {
13345 cancel_delayed_work_sync(&connector->hdcp.check_work);
13346 cancel_work_sync(&connector->hdcp.prop_work);
13349 drm_connector_list_iter_end(&conn_iter);
13352 /* part #1: call before irq uninstall */
13353 void intel_modeset_driver_remove(struct drm_i915_private *i915)
13355 if (!HAS_DISPLAY(i915))
13358 flush_workqueue(i915->flip_wq);
13359 flush_workqueue(i915->modeset_wq);
13361 flush_work(&i915->atomic_helper.free_work);
13362 drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list));
13365 /* part #2: call after irq uninstall */
13366 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915)
13368 if (!HAS_DISPLAY(i915))
13372 * Due to the hpd irq storm handling the hotplug work can re-arm the
13373 * poll handlers. Hence disable polling after hpd handling is shut down.
13375 intel_hpd_poll_fini(i915);
13378 * MST topology needs to be suspended so we don't have any calls to
13379 * fbdev after it's finalized. MST will be destroyed later as part of
13380 * drm_mode_config_cleanup()
13382 intel_dp_mst_suspend(i915);
13384 /* poll work can call into fbdev, hence clean that up afterwards */
13385 intel_fbdev_fini(i915);
13387 intel_unregister_dsm_handler();
13389 intel_fbc_global_disable(i915);
13391 /* flush any delayed tasks or pending work */
13392 flush_scheduled_work();
13394 intel_hdcp_component_fini(i915);
13396 intel_mode_config_cleanup(i915);
13398 intel_overlay_cleanup(i915);
13400 intel_gmbus_teardown(i915);
13402 destroy_workqueue(i915->flip_wq);
13403 destroy_workqueue(i915->modeset_wq);
13405 intel_fbc_cleanup_cfb(i915);
13408 /* part #3: call after gem init */
13409 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915)
13411 intel_dmc_ucode_fini(i915);
13413 intel_power_domains_driver_remove(i915);
13415 intel_vga_unregister(i915);
13417 intel_bios_driver_remove(i915);
13420 void intel_display_driver_register(struct drm_i915_private *i915)
13422 if (!HAS_DISPLAY(i915))
13425 intel_display_debugfs_register(i915);
13427 /* Must be done after probing outputs */
13428 intel_opregion_register(i915);
13429 acpi_video_register();
13431 intel_audio_init(i915);
13434 * Some ports require correctly set-up hpd registers for
13435 * detection to work properly (leading to ghost connected
13436 * connector status), e.g. VGA on gm45. Hence we can only set
13437 * up the initial fbdev config after hpd irqs are fully
13438 * enabled. We do it last so that the async config cannot run
13439 * before the connectors are registered.
13441 intel_fbdev_initial_config_async(&i915->drm);
13444 * We need to coordinate the hotplugs with the asynchronous
13445 * fbdev configuration, for which we use the
13446 * fbdev->async_cookie.
13448 drm_kms_helper_poll_init(&i915->drm);
13451 void intel_display_driver_unregister(struct drm_i915_private *i915)
13453 if (!HAS_DISPLAY(i915))
13456 intel_fbdev_unregister(i915);
13457 intel_audio_deinit(i915);
13460 * After flushing the fbdev (incl. a late async config which
13461 * will have delayed queuing of a hotplug event), then flush
13462 * the hotplug events.
13464 drm_kms_helper_poll_fini(&i915->drm);
13465 drm_atomic_helper_shutdown(&i915->drm);
13467 acpi_video_unregister();
13468 intel_opregion_unregister(i915);