2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/i2c.h>
28 #include <linux/input.h>
29 #include <linux/intel-iommu.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/dma-resv.h>
33 #include <linux/slab.h>
35 #include <drm/drm_atomic.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_atomic_uapi.h>
38 #include <drm/drm_damage_helper.h>
39 #include <drm/drm_dp_helper.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_fourcc.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_probe_helper.h>
44 #include <drm/drm_rect.h>
46 #include "display/intel_crt.h"
47 #include "display/intel_ddi.h"
48 #include "display/intel_dp.h"
49 #include "display/intel_dp_mst.h"
50 #include "display/intel_dpll_mgr.h"
51 #include "display/intel_dsi.h"
52 #include "display/intel_dvo.h"
53 #include "display/intel_gmbus.h"
54 #include "display/intel_hdmi.h"
55 #include "display/intel_lvds.h"
56 #include "display/intel_sdvo.h"
57 #include "display/intel_tv.h"
58 #include "display/intel_vdsc.h"
60 #include "gt/intel_rps.h"
63 #include "i915_trace.h"
64 #include "intel_acpi.h"
65 #include "intel_atomic.h"
66 #include "intel_atomic_plane.h"
68 #include "intel_cdclk.h"
69 #include "intel_color.h"
70 #include "intel_csr.h"
71 #include "intel_display_types.h"
72 #include "intel_dp_link_training.h"
73 #include "intel_fbc.h"
74 #include "intel_fbdev.h"
75 #include "intel_fifo_underrun.h"
76 #include "intel_frontbuffer.h"
77 #include "intel_hdcp.h"
78 #include "intel_hotplug.h"
79 #include "intel_overlay.h"
80 #include "intel_pipe_crc.h"
82 #include "intel_psr.h"
83 #include "intel_quirks.h"
84 #include "intel_sideband.h"
85 #include "intel_sprite.h"
87 #include "intel_vga.h"
89 /* Primary plane formats for gen <= 3 */
90 static const u32 i8xx_primary_formats[] = {
97 /* Primary plane formats for ivb (no fp16 due to hw issue) */
98 static const u32 ivb_primary_formats[] = {
103 DRM_FORMAT_XRGB2101010,
104 DRM_FORMAT_XBGR2101010,
107 /* Primary plane formats for gen >= 4, except ivb */
108 static const u32 i965_primary_formats[] = {
113 DRM_FORMAT_XRGB2101010,
114 DRM_FORMAT_XBGR2101010,
115 DRM_FORMAT_XBGR16161616F,
118 /* Primary plane formats for vlv/chv */
119 static const u32 vlv_primary_formats[] = {
126 DRM_FORMAT_XRGB2101010,
127 DRM_FORMAT_XBGR2101010,
128 DRM_FORMAT_ARGB2101010,
129 DRM_FORMAT_ABGR2101010,
130 DRM_FORMAT_XBGR16161616F,
133 static const u64 i9xx_format_modifiers[] = {
134 I915_FORMAT_MOD_X_TILED,
135 DRM_FORMAT_MOD_LINEAR,
136 DRM_FORMAT_MOD_INVALID
140 static const u32 intel_cursor_formats[] = {
144 static const u64 cursor_format_modifiers[] = {
145 DRM_FORMAT_MOD_LINEAR,
146 DRM_FORMAT_MOD_INVALID
149 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
150 struct intel_crtc_state *pipe_config);
151 static void ilk_pch_clock_get(struct intel_crtc *crtc,
152 struct intel_crtc_state *pipe_config);
154 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
155 struct drm_i915_gem_object *obj,
156 struct drm_mode_fb_cmd2 *mode_cmd);
157 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
158 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
159 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
160 const struct intel_link_m_n *m_n,
161 const struct intel_link_m_n *m2_n2);
162 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
163 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
164 static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state);
165 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
166 static void vlv_prepare_pll(struct intel_crtc *crtc,
167 const struct intel_crtc_state *pipe_config);
168 static void chv_prepare_pll(struct intel_crtc *crtc,
169 const struct intel_crtc_state *pipe_config);
170 static void skl_pfit_enable(const struct intel_crtc_state *crtc_state);
171 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
172 static void intel_modeset_setup_hw_state(struct drm_device *dev,
173 struct drm_modeset_acquire_ctx *ctx);
174 static struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc);
179 } dot, vco, n, m, m1, m2, p, p1;
183 int p2_slow, p2_fast;
187 /* returns HPLL frequency in kHz */
188 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
190 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
192 /* Obtain SKU information */
193 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
194 CCK_FUSE_HPLL_FREQ_MASK;
196 return vco_freq[hpll_freq] * 1000;
199 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
200 const char *name, u32 reg, int ref_freq)
205 val = vlv_cck_read(dev_priv, reg);
206 divider = val & CCK_FREQUENCY_VALUES;
208 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
209 (divider << CCK_FREQUENCY_STATUS_SHIFT),
210 "%s change in progress\n", name);
212 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
215 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
216 const char *name, u32 reg)
220 vlv_cck_get(dev_priv);
222 if (dev_priv->hpll_freq == 0)
223 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
225 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
227 vlv_cck_put(dev_priv);
232 static void intel_update_czclk(struct drm_i915_private *dev_priv)
234 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
237 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
238 CCK_CZ_CLOCK_CONTROL);
240 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
241 dev_priv->czclk_freq);
244 /* units of 100MHz */
245 static u32 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
246 const struct intel_crtc_state *pipe_config)
248 if (HAS_DDI(dev_priv))
249 return pipe_config->port_clock; /* SPLL */
251 return dev_priv->fdi_pll_freq;
254 static const struct intel_limit intel_limits_i8xx_dac = {
255 .dot = { .min = 25000, .max = 350000 },
256 .vco = { .min = 908000, .max = 1512000 },
257 .n = { .min = 2, .max = 16 },
258 .m = { .min = 96, .max = 140 },
259 .m1 = { .min = 18, .max = 26 },
260 .m2 = { .min = 6, .max = 16 },
261 .p = { .min = 4, .max = 128 },
262 .p1 = { .min = 2, .max = 33 },
263 .p2 = { .dot_limit = 165000,
264 .p2_slow = 4, .p2_fast = 2 },
267 static const struct intel_limit intel_limits_i8xx_dvo = {
268 .dot = { .min = 25000, .max = 350000 },
269 .vco = { .min = 908000, .max = 1512000 },
270 .n = { .min = 2, .max = 16 },
271 .m = { .min = 96, .max = 140 },
272 .m1 = { .min = 18, .max = 26 },
273 .m2 = { .min = 6, .max = 16 },
274 .p = { .min = 4, .max = 128 },
275 .p1 = { .min = 2, .max = 33 },
276 .p2 = { .dot_limit = 165000,
277 .p2_slow = 4, .p2_fast = 4 },
280 static const struct intel_limit intel_limits_i8xx_lvds = {
281 .dot = { .min = 25000, .max = 350000 },
282 .vco = { .min = 908000, .max = 1512000 },
283 .n = { .min = 2, .max = 16 },
284 .m = { .min = 96, .max = 140 },
285 .m1 = { .min = 18, .max = 26 },
286 .m2 = { .min = 6, .max = 16 },
287 .p = { .min = 4, .max = 128 },
288 .p1 = { .min = 1, .max = 6 },
289 .p2 = { .dot_limit = 165000,
290 .p2_slow = 14, .p2_fast = 7 },
293 static const struct intel_limit intel_limits_i9xx_sdvo = {
294 .dot = { .min = 20000, .max = 400000 },
295 .vco = { .min = 1400000, .max = 2800000 },
296 .n = { .min = 1, .max = 6 },
297 .m = { .min = 70, .max = 120 },
298 .m1 = { .min = 8, .max = 18 },
299 .m2 = { .min = 3, .max = 7 },
300 .p = { .min = 5, .max = 80 },
301 .p1 = { .min = 1, .max = 8 },
302 .p2 = { .dot_limit = 200000,
303 .p2_slow = 10, .p2_fast = 5 },
306 static const struct intel_limit intel_limits_i9xx_lvds = {
307 .dot = { .min = 20000, .max = 400000 },
308 .vco = { .min = 1400000, .max = 2800000 },
309 .n = { .min = 1, .max = 6 },
310 .m = { .min = 70, .max = 120 },
311 .m1 = { .min = 8, .max = 18 },
312 .m2 = { .min = 3, .max = 7 },
313 .p = { .min = 7, .max = 98 },
314 .p1 = { .min = 1, .max = 8 },
315 .p2 = { .dot_limit = 112000,
316 .p2_slow = 14, .p2_fast = 7 },
320 static const struct intel_limit intel_limits_g4x_sdvo = {
321 .dot = { .min = 25000, .max = 270000 },
322 .vco = { .min = 1750000, .max = 3500000},
323 .n = { .min = 1, .max = 4 },
324 .m = { .min = 104, .max = 138 },
325 .m1 = { .min = 17, .max = 23 },
326 .m2 = { .min = 5, .max = 11 },
327 .p = { .min = 10, .max = 30 },
328 .p1 = { .min = 1, .max = 3},
329 .p2 = { .dot_limit = 270000,
335 static const struct intel_limit intel_limits_g4x_hdmi = {
336 .dot = { .min = 22000, .max = 400000 },
337 .vco = { .min = 1750000, .max = 3500000},
338 .n = { .min = 1, .max = 4 },
339 .m = { .min = 104, .max = 138 },
340 .m1 = { .min = 16, .max = 23 },
341 .m2 = { .min = 5, .max = 11 },
342 .p = { .min = 5, .max = 80 },
343 .p1 = { .min = 1, .max = 8},
344 .p2 = { .dot_limit = 165000,
345 .p2_slow = 10, .p2_fast = 5 },
348 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
349 .dot = { .min = 20000, .max = 115000 },
350 .vco = { .min = 1750000, .max = 3500000 },
351 .n = { .min = 1, .max = 3 },
352 .m = { .min = 104, .max = 138 },
353 .m1 = { .min = 17, .max = 23 },
354 .m2 = { .min = 5, .max = 11 },
355 .p = { .min = 28, .max = 112 },
356 .p1 = { .min = 2, .max = 8 },
357 .p2 = { .dot_limit = 0,
358 .p2_slow = 14, .p2_fast = 14
362 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
363 .dot = { .min = 80000, .max = 224000 },
364 .vco = { .min = 1750000, .max = 3500000 },
365 .n = { .min = 1, .max = 3 },
366 .m = { .min = 104, .max = 138 },
367 .m1 = { .min = 17, .max = 23 },
368 .m2 = { .min = 5, .max = 11 },
369 .p = { .min = 14, .max = 42 },
370 .p1 = { .min = 2, .max = 6 },
371 .p2 = { .dot_limit = 0,
372 .p2_slow = 7, .p2_fast = 7
376 static const struct intel_limit pnv_limits_sdvo = {
377 .dot = { .min = 20000, .max = 400000},
378 .vco = { .min = 1700000, .max = 3500000 },
379 /* Pineview's Ncounter is a ring counter */
380 .n = { .min = 3, .max = 6 },
381 .m = { .min = 2, .max = 256 },
382 /* Pineview only has one combined m divider, which we treat as m2. */
383 .m1 = { .min = 0, .max = 0 },
384 .m2 = { .min = 0, .max = 254 },
385 .p = { .min = 5, .max = 80 },
386 .p1 = { .min = 1, .max = 8 },
387 .p2 = { .dot_limit = 200000,
388 .p2_slow = 10, .p2_fast = 5 },
391 static const struct intel_limit pnv_limits_lvds = {
392 .dot = { .min = 20000, .max = 400000 },
393 .vco = { .min = 1700000, .max = 3500000 },
394 .n = { .min = 3, .max = 6 },
395 .m = { .min = 2, .max = 256 },
396 .m1 = { .min = 0, .max = 0 },
397 .m2 = { .min = 0, .max = 254 },
398 .p = { .min = 7, .max = 112 },
399 .p1 = { .min = 1, .max = 8 },
400 .p2 = { .dot_limit = 112000,
401 .p2_slow = 14, .p2_fast = 14 },
404 /* Ironlake / Sandybridge
406 * We calculate clock using (register_value + 2) for N/M1/M2, so here
407 * the range value for them is (actual_value - 2).
409 static const struct intel_limit ilk_limits_dac = {
410 .dot = { .min = 25000, .max = 350000 },
411 .vco = { .min = 1760000, .max = 3510000 },
412 .n = { .min = 1, .max = 5 },
413 .m = { .min = 79, .max = 127 },
414 .m1 = { .min = 12, .max = 22 },
415 .m2 = { .min = 5, .max = 9 },
416 .p = { .min = 5, .max = 80 },
417 .p1 = { .min = 1, .max = 8 },
418 .p2 = { .dot_limit = 225000,
419 .p2_slow = 10, .p2_fast = 5 },
422 static const struct intel_limit ilk_limits_single_lvds = {
423 .dot = { .min = 25000, .max = 350000 },
424 .vco = { .min = 1760000, .max = 3510000 },
425 .n = { .min = 1, .max = 3 },
426 .m = { .min = 79, .max = 118 },
427 .m1 = { .min = 12, .max = 22 },
428 .m2 = { .min = 5, .max = 9 },
429 .p = { .min = 28, .max = 112 },
430 .p1 = { .min = 2, .max = 8 },
431 .p2 = { .dot_limit = 225000,
432 .p2_slow = 14, .p2_fast = 14 },
435 static const struct intel_limit ilk_limits_dual_lvds = {
436 .dot = { .min = 25000, .max = 350000 },
437 .vco = { .min = 1760000, .max = 3510000 },
438 .n = { .min = 1, .max = 3 },
439 .m = { .min = 79, .max = 127 },
440 .m1 = { .min = 12, .max = 22 },
441 .m2 = { .min = 5, .max = 9 },
442 .p = { .min = 14, .max = 56 },
443 .p1 = { .min = 2, .max = 8 },
444 .p2 = { .dot_limit = 225000,
445 .p2_slow = 7, .p2_fast = 7 },
448 /* LVDS 100mhz refclk limits. */
449 static const struct intel_limit ilk_limits_single_lvds_100m = {
450 .dot = { .min = 25000, .max = 350000 },
451 .vco = { .min = 1760000, .max = 3510000 },
452 .n = { .min = 1, .max = 2 },
453 .m = { .min = 79, .max = 126 },
454 .m1 = { .min = 12, .max = 22 },
455 .m2 = { .min = 5, .max = 9 },
456 .p = { .min = 28, .max = 112 },
457 .p1 = { .min = 2, .max = 8 },
458 .p2 = { .dot_limit = 225000,
459 .p2_slow = 14, .p2_fast = 14 },
462 static const struct intel_limit ilk_limits_dual_lvds_100m = {
463 .dot = { .min = 25000, .max = 350000 },
464 .vco = { .min = 1760000, .max = 3510000 },
465 .n = { .min = 1, .max = 3 },
466 .m = { .min = 79, .max = 126 },
467 .m1 = { .min = 12, .max = 22 },
468 .m2 = { .min = 5, .max = 9 },
469 .p = { .min = 14, .max = 42 },
470 .p1 = { .min = 2, .max = 6 },
471 .p2 = { .dot_limit = 225000,
472 .p2_slow = 7, .p2_fast = 7 },
475 static const struct intel_limit intel_limits_vlv = {
477 * These are the data rate limits (measured in fast clocks)
478 * since those are the strictest limits we have. The fast
479 * clock and actual rate limits are more relaxed, so checking
480 * them would make no difference.
482 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
483 .vco = { .min = 4000000, .max = 6000000 },
484 .n = { .min = 1, .max = 7 },
485 .m1 = { .min = 2, .max = 3 },
486 .m2 = { .min = 11, .max = 156 },
487 .p1 = { .min = 2, .max = 3 },
488 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
491 static const struct intel_limit intel_limits_chv = {
493 * These are the data rate limits (measured in fast clocks)
494 * since those are the strictest limits we have. The fast
495 * clock and actual rate limits are more relaxed, so checking
496 * them would make no difference.
498 .dot = { .min = 25000 * 5, .max = 540000 * 5},
499 .vco = { .min = 4800000, .max = 6480000 },
500 .n = { .min = 1, .max = 1 },
501 .m1 = { .min = 2, .max = 2 },
502 .m2 = { .min = 24 << 22, .max = 175 << 22 },
503 .p1 = { .min = 2, .max = 4 },
504 .p2 = { .p2_slow = 1, .p2_fast = 14 },
507 static const struct intel_limit intel_limits_bxt = {
508 /* FIXME: find real dot limits */
509 .dot = { .min = 0, .max = INT_MAX },
510 .vco = { .min = 4800000, .max = 6700000 },
511 .n = { .min = 1, .max = 1 },
512 .m1 = { .min = 2, .max = 2 },
513 /* FIXME: find real m2 limits */
514 .m2 = { .min = 2 << 22, .max = 255 << 22 },
515 .p1 = { .min = 2, .max = 4 },
516 .p2 = { .p2_slow = 1, .p2_fast = 20 },
519 /* WA Display #0827: Gen9:all */
521 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
524 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
525 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS);
527 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
528 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
531 /* Wa_2006604312:icl,ehl */
533 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
537 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
538 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
540 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
541 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
545 needs_modeset(const struct intel_crtc_state *state)
547 return drm_atomic_crtc_needs_modeset(&state->uapi);
551 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
553 return crtc_state->master_transcoder != INVALID_TRANSCODER;
557 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
559 return crtc_state->sync_mode_slaves_mask != 0;
563 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
565 return is_trans_port_sync_master(crtc_state) ||
566 is_trans_port_sync_slave(crtc_state);
570 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
571 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
572 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
573 * The helpers' return value is the rate of the clock that is fed to the
574 * display engine's pipe which can be the above fast dot clock rate or a
575 * divided-down version of it.
577 /* m1 is reserved as 0 in Pineview, n is a ring counter */
578 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
580 clock->m = clock->m2 + 2;
581 clock->p = clock->p1 * clock->p2;
582 if (WARN_ON(clock->n == 0 || clock->p == 0))
584 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
585 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
590 static u32 i9xx_dpll_compute_m(struct dpll *dpll)
592 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
595 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
597 clock->m = i9xx_dpll_compute_m(clock);
598 clock->p = clock->p1 * clock->p2;
599 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
601 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
602 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
607 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
609 clock->m = clock->m1 * clock->m2;
610 clock->p = clock->p1 * clock->p2;
611 if (WARN_ON(clock->n == 0 || clock->p == 0))
613 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
614 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
616 return clock->dot / 5;
619 int chv_calc_dpll_params(int refclk, struct dpll *clock)
621 clock->m = clock->m1 * clock->m2;
622 clock->p = clock->p1 * clock->p2;
623 if (WARN_ON(clock->n == 0 || clock->p == 0))
625 clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
627 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
629 return clock->dot / 5;
633 * Returns whether the given set of divisors are valid for a given refclk with
634 * the given connectors.
636 static bool intel_pll_is_valid(struct drm_i915_private *dev_priv,
637 const struct intel_limit *limit,
638 const struct dpll *clock)
640 if (clock->n < limit->n.min || limit->n.max < clock->n)
642 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
644 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
646 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
649 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
650 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
651 if (clock->m1 <= clock->m2)
654 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
655 !IS_GEN9_LP(dev_priv)) {
656 if (clock->p < limit->p.min || limit->p.max < clock->p)
658 if (clock->m < limit->m.min || limit->m.max < clock->m)
662 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
664 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
665 * connector, etc., rather than just a single range.
667 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
674 i9xx_select_p2_div(const struct intel_limit *limit,
675 const struct intel_crtc_state *crtc_state,
678 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
680 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
682 * For LVDS just rely on its current settings for dual-channel.
683 * We haven't figured out how to reliably set up different
684 * single/dual channel state, if we even can.
686 if (intel_is_dual_link_lvds(dev_priv))
687 return limit->p2.p2_fast;
689 return limit->p2.p2_slow;
691 if (target < limit->p2.dot_limit)
692 return limit->p2.p2_slow;
694 return limit->p2.p2_fast;
699 * Returns a set of divisors for the desired target clock with the given
700 * refclk, or FALSE. The returned values represent the clock equation:
701 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
703 * Target and reference clocks are specified in kHz.
705 * If match_clock is provided, then best_clock P divider must match the P
706 * divider from @match_clock used for LVDS downclocking.
709 i9xx_find_best_dpll(const struct intel_limit *limit,
710 struct intel_crtc_state *crtc_state,
711 int target, int refclk, struct dpll *match_clock,
712 struct dpll *best_clock)
714 struct drm_device *dev = crtc_state->uapi.crtc->dev;
718 memset(best_clock, 0, sizeof(*best_clock));
720 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
722 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
724 for (clock.m2 = limit->m2.min;
725 clock.m2 <= limit->m2.max; clock.m2++) {
726 if (clock.m2 >= clock.m1)
728 for (clock.n = limit->n.min;
729 clock.n <= limit->n.max; clock.n++) {
730 for (clock.p1 = limit->p1.min;
731 clock.p1 <= limit->p1.max; clock.p1++) {
734 i9xx_calc_dpll_params(refclk, &clock);
735 if (!intel_pll_is_valid(to_i915(dev),
740 clock.p != match_clock->p)
743 this_err = abs(clock.dot - target);
744 if (this_err < err) {
753 return (err != target);
757 * Returns a set of divisors for the desired target clock with the given
758 * refclk, or FALSE. The returned values represent the clock equation:
759 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
761 * Target and reference clocks are specified in kHz.
763 * If match_clock is provided, then best_clock P divider must match the P
764 * divider from @match_clock used for LVDS downclocking.
767 pnv_find_best_dpll(const struct intel_limit *limit,
768 struct intel_crtc_state *crtc_state,
769 int target, int refclk, struct dpll *match_clock,
770 struct dpll *best_clock)
772 struct drm_device *dev = crtc_state->uapi.crtc->dev;
776 memset(best_clock, 0, sizeof(*best_clock));
778 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
780 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
782 for (clock.m2 = limit->m2.min;
783 clock.m2 <= limit->m2.max; clock.m2++) {
784 for (clock.n = limit->n.min;
785 clock.n <= limit->n.max; clock.n++) {
786 for (clock.p1 = limit->p1.min;
787 clock.p1 <= limit->p1.max; clock.p1++) {
790 pnv_calc_dpll_params(refclk, &clock);
791 if (!intel_pll_is_valid(to_i915(dev),
796 clock.p != match_clock->p)
799 this_err = abs(clock.dot - target);
800 if (this_err < err) {
809 return (err != target);
813 * Returns a set of divisors for the desired target clock with the given
814 * refclk, or FALSE. The returned values represent the clock equation:
815 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
817 * Target and reference clocks are specified in kHz.
819 * If match_clock is provided, then best_clock P divider must match the P
820 * divider from @match_clock used for LVDS downclocking.
823 g4x_find_best_dpll(const struct intel_limit *limit,
824 struct intel_crtc_state *crtc_state,
825 int target, int refclk, struct dpll *match_clock,
826 struct dpll *best_clock)
828 struct drm_device *dev = crtc_state->uapi.crtc->dev;
832 /* approximately equals target * 0.00585 */
833 int err_most = (target >> 8) + (target >> 9);
835 memset(best_clock, 0, sizeof(*best_clock));
837 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
839 max_n = limit->n.max;
840 /* based on hardware requirement, prefer smaller n to precision */
841 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
842 /* based on hardware requirement, prefere larger m1,m2 */
843 for (clock.m1 = limit->m1.max;
844 clock.m1 >= limit->m1.min; clock.m1--) {
845 for (clock.m2 = limit->m2.max;
846 clock.m2 >= limit->m2.min; clock.m2--) {
847 for (clock.p1 = limit->p1.max;
848 clock.p1 >= limit->p1.min; clock.p1--) {
851 i9xx_calc_dpll_params(refclk, &clock);
852 if (!intel_pll_is_valid(to_i915(dev),
857 this_err = abs(clock.dot - target);
858 if (this_err < err_most) {
872 * Check if the calculated PLL configuration is more optimal compared to the
873 * best configuration and error found so far. Return the calculated error.
875 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
876 const struct dpll *calculated_clock,
877 const struct dpll *best_clock,
878 unsigned int best_error_ppm,
879 unsigned int *error_ppm)
882 * For CHV ignore the error and consider only the P value.
883 * Prefer a bigger P value based on HW requirements.
885 if (IS_CHERRYVIEW(to_i915(dev))) {
888 return calculated_clock->p > best_clock->p;
891 if (drm_WARN_ON_ONCE(dev, !target_freq))
894 *error_ppm = div_u64(1000000ULL *
895 abs(target_freq - calculated_clock->dot),
898 * Prefer a better P value over a better (smaller) error if the error
899 * is small. Ensure this preference for future configurations too by
900 * setting the error to 0.
902 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
908 return *error_ppm + 10 < best_error_ppm;
912 * Returns a set of divisors for the desired target clock with the given
913 * refclk, or FALSE. The returned values represent the clock equation:
914 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
917 vlv_find_best_dpll(const struct intel_limit *limit,
918 struct intel_crtc_state *crtc_state,
919 int target, int refclk, struct dpll *match_clock,
920 struct dpll *best_clock)
922 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
923 struct drm_device *dev = crtc->base.dev;
925 unsigned int bestppm = 1000000;
926 /* min update 19.2 MHz */
927 int max_n = min(limit->n.max, refclk / 19200);
930 target *= 5; /* fast clock */
932 memset(best_clock, 0, sizeof(*best_clock));
934 /* based on hardware requirement, prefer smaller n to precision */
935 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
936 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
937 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
938 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
939 clock.p = clock.p1 * clock.p2;
940 /* based on hardware requirement, prefer bigger m1,m2 values */
941 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
944 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
947 vlv_calc_dpll_params(refclk, &clock);
949 if (!intel_pll_is_valid(to_i915(dev),
954 if (!vlv_PLL_is_optimal(dev, target,
972 * Returns a set of divisors for the desired target clock with the given
973 * refclk, or FALSE. The returned values represent the clock equation:
974 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
977 chv_find_best_dpll(const struct intel_limit *limit,
978 struct intel_crtc_state *crtc_state,
979 int target, int refclk, struct dpll *match_clock,
980 struct dpll *best_clock)
982 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
983 struct drm_device *dev = crtc->base.dev;
984 unsigned int best_error_ppm;
989 memset(best_clock, 0, sizeof(*best_clock));
990 best_error_ppm = 1000000;
993 * Based on hardware doc, the n always set to 1, and m1 always
994 * set to 2. If requires to support 200Mhz refclk, we need to
995 * revisit this because n may not 1 anymore.
997 clock.n = 1, clock.m1 = 2;
998 target *= 5; /* fast clock */
1000 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1001 for (clock.p2 = limit->p2.p2_fast;
1002 clock.p2 >= limit->p2.p2_slow;
1003 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1004 unsigned int error_ppm;
1006 clock.p = clock.p1 * clock.p2;
1008 m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
1011 if (m2 > INT_MAX/clock.m1)
1016 chv_calc_dpll_params(refclk, &clock);
1018 if (!intel_pll_is_valid(to_i915(dev), limit, &clock))
1021 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1022 best_error_ppm, &error_ppm))
1025 *best_clock = clock;
1026 best_error_ppm = error_ppm;
1034 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
1035 struct dpll *best_clock)
1037 int refclk = 100000;
1038 const struct intel_limit *limit = &intel_limits_bxt;
1040 return chv_find_best_dpll(limit, crtc_state,
1041 crtc_state->port_clock, refclk,
1045 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
1048 i915_reg_t reg = PIPEDSL(pipe);
1052 if (IS_GEN(dev_priv, 2))
1053 line_mask = DSL_LINEMASK_GEN2;
1055 line_mask = DSL_LINEMASK_GEN3;
1057 line1 = intel_de_read(dev_priv, reg) & line_mask;
1059 line2 = intel_de_read(dev_priv, reg) & line_mask;
1061 return line1 != line2;
1064 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1066 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1067 enum pipe pipe = crtc->pipe;
1069 /* Wait for the display line to settle/start moving */
1070 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1071 drm_err(&dev_priv->drm,
1072 "pipe %c scanline %s wait timed out\n",
1073 pipe_name(pipe), onoff(state));
1076 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1078 wait_for_pipe_scanline_moving(crtc, false);
1081 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1083 wait_for_pipe_scanline_moving(crtc, true);
1087 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
1089 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1090 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1092 if (INTEL_GEN(dev_priv) >= 4) {
1093 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1094 i915_reg_t reg = PIPECONF(cpu_transcoder);
1096 /* Wait for the Pipe State to go off */
1097 if (intel_de_wait_for_clear(dev_priv, reg,
1098 I965_PIPECONF_ACTIVE, 100))
1099 drm_WARN(&dev_priv->drm, 1,
1100 "pipe_off wait timed out\n");
1102 intel_wait_for_pipe_scanline_stopped(crtc);
1106 /* Only for pre-ILK configs */
1107 void assert_pll(struct drm_i915_private *dev_priv,
1108 enum pipe pipe, bool state)
1113 val = intel_de_read(dev_priv, DPLL(pipe));
1114 cur_state = !!(val & DPLL_VCO_ENABLE);
1115 I915_STATE_WARN(cur_state != state,
1116 "PLL state assertion failure (expected %s, current %s)\n",
1117 onoff(state), onoff(cur_state));
1120 /* XXX: the dsi pll is shared between MIPI DSI ports */
1121 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1126 vlv_cck_get(dev_priv);
1127 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1128 vlv_cck_put(dev_priv);
1130 cur_state = val & DSI_PLL_VCO_EN;
1131 I915_STATE_WARN(cur_state != state,
1132 "DSI PLL state assertion failure (expected %s, current %s)\n",
1133 onoff(state), onoff(cur_state));
1136 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1137 enum pipe pipe, bool state)
1141 if (HAS_DDI(dev_priv)) {
1143 * DDI does not have a specific FDI_TX register.
1145 * FDI is never fed from EDP transcoder
1146 * so pipe->transcoder cast is fine here.
1148 enum transcoder cpu_transcoder = (enum transcoder)pipe;
1149 u32 val = intel_de_read(dev_priv,
1150 TRANS_DDI_FUNC_CTL(cpu_transcoder));
1151 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1153 u32 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe));
1154 cur_state = !!(val & FDI_TX_ENABLE);
1156 I915_STATE_WARN(cur_state != state,
1157 "FDI TX state assertion failure (expected %s, current %s)\n",
1158 onoff(state), onoff(cur_state));
1160 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1161 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1163 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1164 enum pipe pipe, bool state)
1169 val = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
1170 cur_state = !!(val & FDI_RX_ENABLE);
1171 I915_STATE_WARN(cur_state != state,
1172 "FDI RX state assertion failure (expected %s, current %s)\n",
1173 onoff(state), onoff(cur_state));
1175 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1176 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1178 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1183 /* ILK FDI PLL is always enabled */
1184 if (IS_GEN(dev_priv, 5))
1187 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1188 if (HAS_DDI(dev_priv))
1191 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe));
1192 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1195 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1196 enum pipe pipe, bool state)
1201 val = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
1202 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1203 I915_STATE_WARN(cur_state != state,
1204 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1205 onoff(state), onoff(cur_state));
1208 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1212 enum pipe panel_pipe = INVALID_PIPE;
1215 if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv)))
1218 if (HAS_PCH_SPLIT(dev_priv)) {
1221 pp_reg = PP_CONTROL(0);
1222 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1225 case PANEL_PORT_SELECT_LVDS:
1226 intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1228 case PANEL_PORT_SELECT_DPA:
1229 intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1231 case PANEL_PORT_SELECT_DPC:
1232 intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1234 case PANEL_PORT_SELECT_DPD:
1235 intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1238 MISSING_CASE(port_sel);
1241 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1242 /* presumably write lock depends on pipe, not port select */
1243 pp_reg = PP_CONTROL(pipe);
1248 pp_reg = PP_CONTROL(0);
1249 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1251 drm_WARN_ON(&dev_priv->drm,
1252 port_sel != PANEL_PORT_SELECT_LVDS);
1253 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1256 val = intel_de_read(dev_priv, pp_reg);
1257 if (!(val & PANEL_POWER_ON) ||
1258 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1261 I915_STATE_WARN(panel_pipe == pipe && locked,
1262 "panel assertion failure, pipe %c regs locked\n",
1266 void assert_pipe(struct drm_i915_private *dev_priv,
1267 enum transcoder cpu_transcoder, bool state)
1270 enum intel_display_power_domain power_domain;
1271 intel_wakeref_t wakeref;
1273 /* we keep both pipes enabled on 830 */
1274 if (IS_I830(dev_priv))
1277 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1278 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1280 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
1281 cur_state = !!(val & PIPECONF_ENABLE);
1283 intel_display_power_put(dev_priv, power_domain, wakeref);
1288 I915_STATE_WARN(cur_state != state,
1289 "transcoder %s assertion failure (expected %s, current %s)\n",
1290 transcoder_name(cpu_transcoder),
1291 onoff(state), onoff(cur_state));
1294 static void assert_plane(struct intel_plane *plane, bool state)
1299 cur_state = plane->get_hw_state(plane, &pipe);
1301 I915_STATE_WARN(cur_state != state,
1302 "%s assertion failure (expected %s, current %s)\n",
1303 plane->base.name, onoff(state), onoff(cur_state));
1306 #define assert_plane_enabled(p) assert_plane(p, true)
1307 #define assert_plane_disabled(p) assert_plane(p, false)
1309 static void assert_planes_disabled(struct intel_crtc *crtc)
1311 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1312 struct intel_plane *plane;
1314 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1315 assert_plane_disabled(plane);
1318 static void assert_vblank_disabled(struct drm_crtc *crtc)
1320 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1321 drm_crtc_vblank_put(crtc);
1324 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1330 val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe));
1331 enabled = !!(val & TRANS_ENABLE);
1332 I915_STATE_WARN(enabled,
1333 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1337 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1338 enum pipe pipe, enum port port,
1341 enum pipe port_pipe;
1344 state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
1346 I915_STATE_WARN(state && port_pipe == pipe,
1347 "PCH DP %c enabled on transcoder %c, should be disabled\n",
1348 port_name(port), pipe_name(pipe));
1350 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1351 "IBX PCH DP %c still using transcoder B\n",
1355 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1356 enum pipe pipe, enum port port,
1357 i915_reg_t hdmi_reg)
1359 enum pipe port_pipe;
1362 state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
1364 I915_STATE_WARN(state && port_pipe == pipe,
1365 "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
1366 port_name(port), pipe_name(pipe));
1368 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1369 "IBX PCH HDMI %c still using transcoder B\n",
1373 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1376 enum pipe port_pipe;
1378 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
1379 assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
1380 assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
1382 I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
1384 "PCH VGA enabled on transcoder %c, should be disabled\n",
1387 I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
1389 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1392 /* PCH SDVOB multiplex with HDMIB */
1393 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
1394 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
1395 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
1398 static void _vlv_enable_pll(struct intel_crtc *crtc,
1399 const struct intel_crtc_state *pipe_config)
1401 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1402 enum pipe pipe = crtc->pipe;
1404 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1405 intel_de_posting_read(dev_priv, DPLL(pipe));
1408 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1409 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe);
1412 static void vlv_enable_pll(struct intel_crtc *crtc,
1413 const struct intel_crtc_state *pipe_config)
1415 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1416 enum pipe pipe = crtc->pipe;
1418 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
1420 /* PLL is protected by panel, make sure we can write it */
1421 assert_panel_unlocked(dev_priv, pipe);
1423 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1424 _vlv_enable_pll(crtc, pipe_config);
1426 intel_de_write(dev_priv, DPLL_MD(pipe),
1427 pipe_config->dpll_hw_state.dpll_md);
1428 intel_de_posting_read(dev_priv, DPLL_MD(pipe));
1432 static void _chv_enable_pll(struct intel_crtc *crtc,
1433 const struct intel_crtc_state *pipe_config)
1435 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1436 enum pipe pipe = crtc->pipe;
1437 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1440 vlv_dpio_get(dev_priv);
1442 /* Enable back the 10bit clock to display controller */
1443 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1444 tmp |= DPIO_DCLKP_EN;
1445 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1447 vlv_dpio_put(dev_priv);
1450 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1455 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1457 /* Check PLL is locked */
1458 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1459 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe);
1462 static void chv_enable_pll(struct intel_crtc *crtc,
1463 const struct intel_crtc_state *pipe_config)
1465 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1466 enum pipe pipe = crtc->pipe;
1468 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
1470 /* PLL is protected by panel, make sure we can write it */
1471 assert_panel_unlocked(dev_priv, pipe);
1473 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1474 _chv_enable_pll(crtc, pipe_config);
1476 if (pipe != PIPE_A) {
1478 * WaPixelRepeatModeFixForC0:chv
1480 * DPLLCMD is AWOL. Use chicken bits to propagate
1481 * the value from DPLLBMD to either pipe B or C.
1483 intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1484 intel_de_write(dev_priv, DPLL_MD(PIPE_B),
1485 pipe_config->dpll_hw_state.dpll_md);
1486 intel_de_write(dev_priv, CBR4_VLV, 0);
1487 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1490 * DPLLB VGA mode also seems to cause problems.
1491 * We should always have it disabled.
1493 drm_WARN_ON(&dev_priv->drm,
1494 (intel_de_read(dev_priv, DPLL(PIPE_B)) &
1495 DPLL_VGA_MODE_DIS) == 0);
1497 intel_de_write(dev_priv, DPLL_MD(pipe),
1498 pipe_config->dpll_hw_state.dpll_md);
1499 intel_de_posting_read(dev_priv, DPLL_MD(pipe));
1503 static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
1505 if (IS_I830(dev_priv))
1508 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
1511 static void i9xx_enable_pll(struct intel_crtc *crtc,
1512 const struct intel_crtc_state *crtc_state)
1514 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1515 i915_reg_t reg = DPLL(crtc->pipe);
1516 u32 dpll = crtc_state->dpll_hw_state.dpll;
1519 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
1521 /* PLL is protected by panel, make sure we can write it */
1522 if (i9xx_has_pps(dev_priv))
1523 assert_panel_unlocked(dev_priv, crtc->pipe);
1526 * Apparently we need to have VGA mode enabled prior to changing
1527 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1528 * dividers, even though the register value does change.
1530 intel_de_write(dev_priv, reg, dpll & ~DPLL_VGA_MODE_DIS);
1531 intel_de_write(dev_priv, reg, dpll);
1533 /* Wait for the clocks to stabilize. */
1534 intel_de_posting_read(dev_priv, reg);
1537 if (INTEL_GEN(dev_priv) >= 4) {
1538 intel_de_write(dev_priv, DPLL_MD(crtc->pipe),
1539 crtc_state->dpll_hw_state.dpll_md);
1541 /* The pixel multiplier can only be updated once the
1542 * DPLL is enabled and the clocks are stable.
1544 * So write it again.
1546 intel_de_write(dev_priv, reg, dpll);
1549 /* We do this three times for luck */
1550 for (i = 0; i < 3; i++) {
1551 intel_de_write(dev_priv, reg, dpll);
1552 intel_de_posting_read(dev_priv, reg);
1553 udelay(150); /* wait for warmup */
1557 static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
1559 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1560 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1561 enum pipe pipe = crtc->pipe;
1563 /* Don't disable pipe or pipe PLLs if needed */
1564 if (IS_I830(dev_priv))
1567 /* Make sure the pipe isn't still relying on us */
1568 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
1570 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
1571 intel_de_posting_read(dev_priv, DPLL(pipe));
1574 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1578 /* Make sure the pipe isn't still relying on us */
1579 assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
1581 val = DPLL_INTEGRATED_REF_CLK_VLV |
1582 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1584 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1586 intel_de_write(dev_priv, DPLL(pipe), val);
1587 intel_de_posting_read(dev_priv, DPLL(pipe));
1590 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1592 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1595 /* Make sure the pipe isn't still relying on us */
1596 assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
1598 val = DPLL_SSC_REF_CLK_CHV |
1599 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1601 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1603 intel_de_write(dev_priv, DPLL(pipe), val);
1604 intel_de_posting_read(dev_priv, DPLL(pipe));
1606 vlv_dpio_get(dev_priv);
1608 /* Disable 10bit clock to display controller */
1609 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1610 val &= ~DPIO_DCLKP_EN;
1611 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1613 vlv_dpio_put(dev_priv);
1616 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1617 struct intel_digital_port *dig_port,
1618 unsigned int expected_mask)
1621 i915_reg_t dpll_reg;
1623 switch (dig_port->base.port) {
1625 port_mask = DPLL_PORTB_READY_MASK;
1629 port_mask = DPLL_PORTC_READY_MASK;
1631 expected_mask <<= 4;
1634 port_mask = DPLL_PORTD_READY_MASK;
1635 dpll_reg = DPIO_PHY_STATUS;
1641 if (intel_de_wait_for_register(dev_priv, dpll_reg,
1642 port_mask, expected_mask, 1000))
1643 drm_WARN(&dev_priv->drm, 1,
1644 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
1645 dig_port->base.base.base.id, dig_port->base.base.name,
1646 intel_de_read(dev_priv, dpll_reg) & port_mask,
1650 static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
1652 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1653 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1654 enum pipe pipe = crtc->pipe;
1656 u32 val, pipeconf_val;
1658 /* Make sure PCH DPLL is enabled */
1659 assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
1661 /* FDI must be feeding us bits for PCH ports */
1662 assert_fdi_tx_enabled(dev_priv, pipe);
1663 assert_fdi_rx_enabled(dev_priv, pipe);
1665 if (HAS_PCH_CPT(dev_priv)) {
1666 reg = TRANS_CHICKEN2(pipe);
1667 val = intel_de_read(dev_priv, reg);
1669 * Workaround: Set the timing override bit
1670 * before enabling the pch transcoder.
1672 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1673 /* Configure frame start delay to match the CPU */
1674 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1675 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
1676 intel_de_write(dev_priv, reg, val);
1679 reg = PCH_TRANSCONF(pipe);
1680 val = intel_de_read(dev_priv, reg);
1681 pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe));
1683 if (HAS_PCH_IBX(dev_priv)) {
1684 /* Configure frame start delay to match the CPU */
1685 val &= ~TRANS_FRAME_START_DELAY_MASK;
1686 val |= TRANS_FRAME_START_DELAY(0);
1689 * Make the BPC in transcoder be consistent with
1690 * that in pipeconf reg. For HDMI we must use 8bpc
1691 * here for both 8bpc and 12bpc.
1693 val &= ~PIPECONF_BPC_MASK;
1694 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1695 val |= PIPECONF_8BPC;
1697 val |= pipeconf_val & PIPECONF_BPC_MASK;
1700 val &= ~TRANS_INTERLACE_MASK;
1701 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
1702 if (HAS_PCH_IBX(dev_priv) &&
1703 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
1704 val |= TRANS_LEGACY_INTERLACED_ILK;
1706 val |= TRANS_INTERLACED;
1708 val |= TRANS_PROGRESSIVE;
1711 intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
1712 if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
1713 drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",
1717 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1718 enum transcoder cpu_transcoder)
1720 u32 val, pipeconf_val;
1722 /* FDI must be feeding us bits for PCH ports */
1723 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1724 assert_fdi_rx_enabled(dev_priv, PIPE_A);
1726 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
1727 /* Workaround: set timing override bit. */
1728 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1729 /* Configure frame start delay to match the CPU */
1730 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1731 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
1732 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
1735 pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
1737 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1738 PIPECONF_INTERLACED_ILK)
1739 val |= TRANS_INTERLACED;
1741 val |= TRANS_PROGRESSIVE;
1743 intel_de_write(dev_priv, LPT_TRANSCONF, val);
1744 if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
1745 TRANS_STATE_ENABLE, 100))
1746 drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n");
1749 static void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1755 /* FDI relies on the transcoder */
1756 assert_fdi_tx_disabled(dev_priv, pipe);
1757 assert_fdi_rx_disabled(dev_priv, pipe);
1759 /* Ports must be off as well */
1760 assert_pch_ports_disabled(dev_priv, pipe);
1762 reg = PCH_TRANSCONF(pipe);
1763 val = intel_de_read(dev_priv, reg);
1764 val &= ~TRANS_ENABLE;
1765 intel_de_write(dev_priv, reg, val);
1766 /* wait for PCH transcoder off, transcoder state */
1767 if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
1768 drm_err(&dev_priv->drm, "failed to disable transcoder %c\n",
1771 if (HAS_PCH_CPT(dev_priv)) {
1772 /* Workaround: Clear the timing override chicken bit again. */
1773 reg = TRANS_CHICKEN2(pipe);
1774 val = intel_de_read(dev_priv, reg);
1775 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1776 intel_de_write(dev_priv, reg, val);
1780 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1784 val = intel_de_read(dev_priv, LPT_TRANSCONF);
1785 val &= ~TRANS_ENABLE;
1786 intel_de_write(dev_priv, LPT_TRANSCONF, val);
1787 /* wait for PCH transcoder off, transcoder state */
1788 if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
1789 TRANS_STATE_ENABLE, 50))
1790 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
1792 /* Workaround: clear timing override bit. */
1793 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
1794 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1795 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
1798 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1800 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1802 if (HAS_PCH_LPT(dev_priv))
1808 static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
1810 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1813 * On i965gm the hardware frame counter reads
1814 * zero when the TV encoder is enabled :(
1816 if (IS_I965GM(dev_priv) &&
1817 (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)))
1820 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1821 return 0xffffffff; /* full 32 bit counter */
1822 else if (INTEL_GEN(dev_priv) >= 3)
1823 return 0xffffff; /* only 24 bits of frame count */
1825 return 0; /* Gen2 doesn't have a hardware frame counter */
1828 void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
1830 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1832 assert_vblank_disabled(&crtc->base);
1833 drm_crtc_set_max_vblank_count(&crtc->base,
1834 intel_crtc_max_vblank_count(crtc_state));
1835 drm_crtc_vblank_on(&crtc->base);
1838 void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state)
1840 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1842 drm_crtc_vblank_off(&crtc->base);
1843 assert_vblank_disabled(&crtc->base);
1846 void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
1848 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1849 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1850 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1851 enum pipe pipe = crtc->pipe;
1855 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
1857 assert_planes_disabled(crtc);
1860 * A pipe without a PLL won't actually be able to drive bits from
1861 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1864 if (HAS_GMCH(dev_priv)) {
1865 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1866 assert_dsi_pll_enabled(dev_priv);
1868 assert_pll_enabled(dev_priv, pipe);
1870 if (new_crtc_state->has_pch_encoder) {
1871 /* if driving the PCH, we need FDI enabled */
1872 assert_fdi_rx_pll_enabled(dev_priv,
1873 intel_crtc_pch_transcoder(crtc));
1874 assert_fdi_tx_pll_enabled(dev_priv,
1875 (enum pipe) cpu_transcoder);
1877 /* FIXME: assert CPU port conditions for SNB+ */
1880 trace_intel_pipe_enable(crtc);
1882 reg = PIPECONF(cpu_transcoder);
1883 val = intel_de_read(dev_priv, reg);
1884 if (val & PIPECONF_ENABLE) {
1885 /* we keep both pipes enabled on 830 */
1886 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
1890 intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE);
1891 intel_de_posting_read(dev_priv, reg);
1894 * Until the pipe starts PIPEDSL reads will return a stale value,
1895 * which causes an apparent vblank timestamp jump when PIPEDSL
1896 * resets to its proper value. That also messes up the frame count
1897 * when it's derived from the timestamps. So let's wait for the
1898 * pipe to start properly before we call drm_crtc_vblank_on()
1900 if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
1901 intel_wait_for_pipe_scanline_moving(crtc);
1904 void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1906 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1907 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1908 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1909 enum pipe pipe = crtc->pipe;
1913 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));
1916 * Make sure planes won't keep trying to pump pixels to us,
1917 * or we might hang the display.
1919 assert_planes_disabled(crtc);
1921 trace_intel_pipe_disable(crtc);
1923 reg = PIPECONF(cpu_transcoder);
1924 val = intel_de_read(dev_priv, reg);
1925 if ((val & PIPECONF_ENABLE) == 0)
1929 * Double wide has implications for planes
1930 * so best keep it disabled when not needed.
1932 if (old_crtc_state->double_wide)
1933 val &= ~PIPECONF_DOUBLE_WIDE;
1935 /* Don't disable pipe or pipe PLLs if needed */
1936 if (!IS_I830(dev_priv))
1937 val &= ~PIPECONF_ENABLE;
1939 intel_de_write(dev_priv, reg, val);
1940 if ((val & PIPECONF_ENABLE) == 0)
1941 intel_wait_for_pipe_off(old_crtc_state);
1944 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1946 return IS_GEN(dev_priv, 2) ? 2048 : 4096;
1949 static bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
1951 if (!is_ccs_modifier(fb->modifier))
1954 return plane >= fb->format->num_planes / 2;
1957 static bool is_gen12_ccs_modifier(u64 modifier)
1959 return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
1960 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
1964 static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
1966 return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
1969 static bool is_aux_plane(const struct drm_framebuffer *fb, int plane)
1971 if (is_ccs_modifier(fb->modifier))
1972 return is_ccs_plane(fb, plane);
1977 static int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
1979 drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
1980 (main_plane && main_plane >= fb->format->num_planes / 2));
1982 return fb->format->num_planes / 2 + main_plane;
1985 static int ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
1987 drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
1988 ccs_plane < fb->format->num_planes / 2);
1990 return ccs_plane - fb->format->num_planes / 2;
1993 /* Return either the main plane's CCS or - if not a CCS FB - UV plane */
1994 int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
1996 if (is_ccs_modifier(fb->modifier))
1997 return main_to_ccs_plane(fb, main_plane);
2003 intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
2006 return info->is_yuv &&
2007 info->num_planes == (is_ccs_modifier(modifier) ? 4 : 2);
2010 static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb,
2013 return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
2018 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
2020 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2021 unsigned int cpp = fb->format->cpp[color_plane];
2023 switch (fb->modifier) {
2024 case DRM_FORMAT_MOD_LINEAR:
2025 return intel_tile_size(dev_priv);
2026 case I915_FORMAT_MOD_X_TILED:
2027 if (IS_GEN(dev_priv, 2))
2031 case I915_FORMAT_MOD_Y_TILED_CCS:
2032 if (is_ccs_plane(fb, color_plane))
2035 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2036 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2037 if (is_ccs_plane(fb, color_plane))
2040 case I915_FORMAT_MOD_Y_TILED:
2041 if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
2045 case I915_FORMAT_MOD_Yf_TILED_CCS:
2046 if (is_ccs_plane(fb, color_plane))
2049 case I915_FORMAT_MOD_Yf_TILED:
2065 MISSING_CASE(fb->modifier);
2071 intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
2073 if (is_gen12_ccs_plane(fb, color_plane))
2076 return intel_tile_size(to_i915(fb->dev)) /
2077 intel_tile_width_bytes(fb, color_plane);
2080 /* Return the tile dimensions in pixel units */
2081 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
2082 unsigned int *tile_width,
2083 unsigned int *tile_height)
2085 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
2086 unsigned int cpp = fb->format->cpp[color_plane];
2088 *tile_width = tile_width_bytes / cpp;
2089 *tile_height = intel_tile_height(fb, color_plane);
2092 static unsigned int intel_tile_row_size(const struct drm_framebuffer *fb,
2095 unsigned int tile_width, tile_height;
2097 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2099 return fb->pitches[color_plane] * tile_height;
2103 intel_fb_align_height(const struct drm_framebuffer *fb,
2104 int color_plane, unsigned int height)
2106 unsigned int tile_height = intel_tile_height(fb, color_plane);
2108 return ALIGN(height, tile_height);
2111 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2113 unsigned int size = 0;
2116 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2117 size += rot_info->plane[i].width * rot_info->plane[i].height;
2122 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
2124 unsigned int size = 0;
2127 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++)
2128 size += rem_info->plane[i].width * rem_info->plane[i].height;
2134 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2135 const struct drm_framebuffer *fb,
2136 unsigned int rotation)
2138 view->type = I915_GGTT_VIEW_NORMAL;
2139 if (drm_rotation_90_or_270(rotation)) {
2140 view->type = I915_GGTT_VIEW_ROTATED;
2141 view->rotated = to_intel_framebuffer(fb)->rot_info;
2145 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2147 if (IS_I830(dev_priv))
2149 else if (IS_I85X(dev_priv))
2151 else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2157 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2159 if (INTEL_GEN(dev_priv) >= 9)
2161 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2162 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2164 else if (INTEL_GEN(dev_priv) >= 4)
2170 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2173 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2175 /* AUX_DIST needs only 4K alignment */
2176 if ((INTEL_GEN(dev_priv) < 12 && is_aux_plane(fb, color_plane)) ||
2177 is_ccs_plane(fb, color_plane))
2180 switch (fb->modifier) {
2181 case DRM_FORMAT_MOD_LINEAR:
2182 return intel_linear_alignment(dev_priv);
2183 case I915_FORMAT_MOD_X_TILED:
2184 if (INTEL_GEN(dev_priv) >= 9)
2187 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2188 if (is_semiplanar_uv_plane(fb, color_plane))
2189 return intel_tile_row_size(fb, color_plane);
2191 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2193 case I915_FORMAT_MOD_Y_TILED_CCS:
2194 case I915_FORMAT_MOD_Yf_TILED_CCS:
2195 case I915_FORMAT_MOD_Y_TILED:
2196 if (INTEL_GEN(dev_priv) >= 12 &&
2197 is_semiplanar_uv_plane(fb, color_plane))
2198 return intel_tile_row_size(fb, color_plane);
2200 case I915_FORMAT_MOD_Yf_TILED:
2201 return 1 * 1024 * 1024;
2203 MISSING_CASE(fb->modifier);
2208 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
2210 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2211 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2213 return INTEL_GEN(dev_priv) < 4 ||
2215 plane_state->view.type == I915_GGTT_VIEW_NORMAL);
2219 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2220 const struct i915_ggtt_view *view,
2222 unsigned long *out_flags)
2224 struct drm_device *dev = fb->dev;
2225 struct drm_i915_private *dev_priv = to_i915(dev);
2226 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2227 intel_wakeref_t wakeref;
2228 struct i915_vma *vma;
2229 unsigned int pinctl;
2232 if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj)))
2233 return ERR_PTR(-EINVAL);
2235 alignment = intel_surf_alignment(fb, 0);
2236 if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment)))
2237 return ERR_PTR(-EINVAL);
2239 /* Note that the w/a also requires 64 PTE of padding following the
2240 * bo. We currently fill all unused PTE with the shadow page and so
2241 * we should always have valid PTE following the scanout preventing
2244 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2245 alignment = 256 * 1024;
2248 * Global gtt pte registers are special registers which actually forward
2249 * writes to a chunk of system memory. Which means that there is no risk
2250 * that the register values disappear as soon as we call
2251 * intel_runtime_pm_put(), so it is correct to wrap only the
2252 * pin/unpin/fence and not more.
2254 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
2256 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2259 * Valleyview is definitely limited to scanning out the first
2260 * 512MiB. Lets presume this behaviour was inherited from the
2261 * g4x display engine and that all earlier gen are similarly
2262 * limited. Testing suggests that it is a little more
2263 * complicated than this. For example, Cherryview appears quite
2264 * happy to scanout from anywhere within its global aperture.
2267 if (HAS_GMCH(dev_priv))
2268 pinctl |= PIN_MAPPABLE;
2270 vma = i915_gem_object_pin_to_display_plane(obj,
2271 alignment, view, pinctl);
2275 if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
2279 * Install a fence for tiled scan-out. Pre-i965 always needs a
2280 * fence, whereas 965+ only requires a fence if using
2281 * framebuffer compression. For simplicity, we always, when
2282 * possible, install a fence as the cost is not that onerous.
2284 * If we fail to fence the tiled scanout, then either the
2285 * modeset will reject the change (which is highly unlikely as
2286 * the affected systems, all but one, do not have unmappable
2287 * space) or we will not be able to enable full powersaving
2288 * techniques (also likely not to apply due to various limits
2289 * FBC and the like impose on the size of the buffer, which
2290 * presumably we violated anyway with this unmappable buffer).
2291 * Anyway, it is presumably better to stumble onwards with
2292 * something and try to run the system in a "less than optimal"
2293 * mode that matches the user configuration.
2295 ret = i915_vma_pin_fence(vma);
2296 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
2297 i915_gem_object_unpin_from_display_plane(vma);
2302 if (ret == 0 && vma->fence)
2303 *out_flags |= PLANE_HAS_FENCE;
2308 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2309 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
2313 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
2315 i915_gem_object_lock(vma->obj, NULL);
2316 if (flags & PLANE_HAS_FENCE)
2317 i915_vma_unpin_fence(vma);
2318 i915_gem_object_unpin_from_display_plane(vma);
2319 i915_gem_object_unlock(vma->obj);
2324 static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane,
2325 unsigned int rotation)
2327 if (drm_rotation_90_or_270(rotation))
2328 return to_intel_framebuffer(fb)->rotated[color_plane].pitch;
2330 return fb->pitches[color_plane];
2334 * Convert the x/y offsets into a linear offset.
2335 * Only valid with 0/180 degree rotation, which is fine since linear
2336 * offset is only used with linear buffers on pre-hsw and tiled buffers
2337 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2339 u32 intel_fb_xy_to_linear(int x, int y,
2340 const struct intel_plane_state *state,
2343 const struct drm_framebuffer *fb = state->hw.fb;
2344 unsigned int cpp = fb->format->cpp[color_plane];
2345 unsigned int pitch = state->color_plane[color_plane].stride;
2347 return y * pitch + x * cpp;
2351 * Add the x/y offsets derived from fb->offsets[] to the user
2352 * specified plane src x/y offsets. The resulting x/y offsets
2353 * specify the start of scanout from the beginning of the gtt mapping.
2355 void intel_add_fb_offsets(int *x, int *y,
2356 const struct intel_plane_state *state,
2360 *x += state->color_plane[color_plane].x;
2361 *y += state->color_plane[color_plane].y;
2364 static u32 intel_adjust_tile_offset(int *x, int *y,
2365 unsigned int tile_width,
2366 unsigned int tile_height,
2367 unsigned int tile_size,
2368 unsigned int pitch_tiles,
2372 unsigned int pitch_pixels = pitch_tiles * tile_width;
2375 WARN_ON(old_offset & (tile_size - 1));
2376 WARN_ON(new_offset & (tile_size - 1));
2377 WARN_ON(new_offset > old_offset);
2379 tiles = (old_offset - new_offset) / tile_size;
2381 *y += tiles / pitch_tiles * tile_height;
2382 *x += tiles % pitch_tiles * tile_width;
2384 /* minimize x in case it got needlessly big */
2385 *y += *x / pitch_pixels * tile_height;
2391 static bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
2393 return fb->modifier == DRM_FORMAT_MOD_LINEAR ||
2394 is_gen12_ccs_plane(fb, color_plane);
2397 static u32 intel_adjust_aligned_offset(int *x, int *y,
2398 const struct drm_framebuffer *fb,
2400 unsigned int rotation,
2402 u32 old_offset, u32 new_offset)
2404 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2405 unsigned int cpp = fb->format->cpp[color_plane];
2407 drm_WARN_ON(&dev_priv->drm, new_offset > old_offset);
2409 if (!is_surface_linear(fb, color_plane)) {
2410 unsigned int tile_size, tile_width, tile_height;
2411 unsigned int pitch_tiles;
2413 tile_size = intel_tile_size(dev_priv);
2414 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2416 if (drm_rotation_90_or_270(rotation)) {
2417 pitch_tiles = pitch / tile_height;
2418 swap(tile_width, tile_height);
2420 pitch_tiles = pitch / (tile_width * cpp);
2423 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2424 tile_size, pitch_tiles,
2425 old_offset, new_offset);
2427 old_offset += *y * pitch + *x * cpp;
2429 *y = (old_offset - new_offset) / pitch;
2430 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2437 * Adjust the tile offset by moving the difference into
2440 static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
2441 const struct intel_plane_state *state,
2443 u32 old_offset, u32 new_offset)
2445 return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane,
2447 state->color_plane[color_plane].stride,
2448 old_offset, new_offset);
2452 * Computes the aligned offset to the base tile and adjusts
2453 * x, y. bytes per pixel is assumed to be a power-of-two.
2455 * In the 90/270 rotated case, x and y are assumed
2456 * to be already rotated to match the rotated GTT view, and
2457 * pitch is the tile_height aligned framebuffer height.
2459 * This function is used when computing the derived information
2460 * under intel_framebuffer, so using any of that information
2461 * here is not allowed. Anything under drm_framebuffer can be
2462 * used. This is why the user has to pass in the pitch since it
2463 * is specified in the rotated orientation.
2465 static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
2467 const struct drm_framebuffer *fb,
2470 unsigned int rotation,
2473 unsigned int cpp = fb->format->cpp[color_plane];
2474 u32 offset, offset_aligned;
2476 if (!is_surface_linear(fb, color_plane)) {
2477 unsigned int tile_size, tile_width, tile_height;
2478 unsigned int tile_rows, tiles, pitch_tiles;
2480 tile_size = intel_tile_size(dev_priv);
2481 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2483 if (drm_rotation_90_or_270(rotation)) {
2484 pitch_tiles = pitch / tile_height;
2485 swap(tile_width, tile_height);
2487 pitch_tiles = pitch / (tile_width * cpp);
2490 tile_rows = *y / tile_height;
2493 tiles = *x / tile_width;
2496 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2498 offset_aligned = offset;
2500 offset_aligned = rounddown(offset_aligned, alignment);
2502 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2503 tile_size, pitch_tiles,
2504 offset, offset_aligned);
2506 offset = *y * pitch + *x * cpp;
2507 offset_aligned = offset;
2509 offset_aligned = rounddown(offset_aligned, alignment);
2510 *y = (offset % alignment) / pitch;
2511 *x = ((offset % alignment) - *y * pitch) / cpp;
2517 return offset_aligned;
2520 static u32 intel_plane_compute_aligned_offset(int *x, int *y,
2521 const struct intel_plane_state *state,
2524 struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane);
2525 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2526 const struct drm_framebuffer *fb = state->hw.fb;
2527 unsigned int rotation = state->hw.rotation;
2528 int pitch = state->color_plane[color_plane].stride;
2531 if (intel_plane->id == PLANE_CURSOR)
2532 alignment = intel_cursor_alignment(dev_priv);
2534 alignment = intel_surf_alignment(fb, color_plane);
2536 return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane,
2537 pitch, rotation, alignment);
2540 /* Convert the fb->offset[] into x/y offsets */
2541 static int intel_fb_offset_to_xy(int *x, int *y,
2542 const struct drm_framebuffer *fb,
2545 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2546 unsigned int height;
2549 if (INTEL_GEN(dev_priv) >= 12 &&
2550 is_semiplanar_uv_plane(fb, color_plane))
2551 alignment = intel_tile_row_size(fb, color_plane);
2552 else if (fb->modifier != DRM_FORMAT_MOD_LINEAR)
2553 alignment = intel_tile_size(dev_priv);
2557 if (alignment != 0 && fb->offsets[color_plane] % alignment) {
2558 drm_dbg_kms(&dev_priv->drm,
2559 "Misaligned offset 0x%08x for color plane %d\n",
2560 fb->offsets[color_plane], color_plane);
2564 height = drm_framebuffer_plane_height(fb->height, fb, color_plane);
2565 height = ALIGN(height, intel_tile_height(fb, color_plane));
2567 /* Catch potential overflows early */
2568 if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]),
2569 fb->offsets[color_plane])) {
2570 drm_dbg_kms(&dev_priv->drm,
2571 "Bad offset 0x%08x or pitch %d for color plane %d\n",
2572 fb->offsets[color_plane], fb->pitches[color_plane],
2580 intel_adjust_aligned_offset(x, y,
2581 fb, color_plane, DRM_MODE_ROTATE_0,
2582 fb->pitches[color_plane],
2583 fb->offsets[color_plane], 0);
2588 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
2590 switch (fb_modifier) {
2591 case I915_FORMAT_MOD_X_TILED:
2592 return I915_TILING_X;
2593 case I915_FORMAT_MOD_Y_TILED:
2594 case I915_FORMAT_MOD_Y_TILED_CCS:
2595 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2596 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2597 return I915_TILING_Y;
2599 return I915_TILING_NONE;
2604 * From the Sky Lake PRM:
2605 * "The Color Control Surface (CCS) contains the compression status of
2606 * the cache-line pairs. The compression state of the cache-line pair
2607 * is specified by 2 bits in the CCS. Each CCS cache-line represents
2608 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2609 * cache-line-pairs. CCS is always Y tiled."
2611 * Since cache line pairs refers to horizontally adjacent cache lines,
2612 * each cache line in the CCS corresponds to an area of 32x16 cache
2613 * lines on the main surface. Since each pixel is 4 bytes, this gives
2614 * us a ratio of one byte in the CCS for each 8x16 pixels in the
2617 static const struct drm_format_info skl_ccs_formats[] = {
2618 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
2619 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2620 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
2621 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2622 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
2623 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2624 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
2625 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2629 * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
2630 * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
2631 * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
2632 * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
2635 static const struct drm_format_info gen12_ccs_formats[] = {
2636 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
2637 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2638 .hsub = 1, .vsub = 1, },
2639 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
2640 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2641 .hsub = 1, .vsub = 1, },
2642 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
2643 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2644 .hsub = 1, .vsub = 1, .has_alpha = true },
2645 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
2646 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2647 .hsub = 1, .vsub = 1, .has_alpha = true },
2648 { .format = DRM_FORMAT_YUYV, .num_planes = 2,
2649 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2650 .hsub = 2, .vsub = 1, .is_yuv = true },
2651 { .format = DRM_FORMAT_YVYU, .num_planes = 2,
2652 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2653 .hsub = 2, .vsub = 1, .is_yuv = true },
2654 { .format = DRM_FORMAT_UYVY, .num_planes = 2,
2655 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2656 .hsub = 2, .vsub = 1, .is_yuv = true },
2657 { .format = DRM_FORMAT_VYUY, .num_planes = 2,
2658 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2659 .hsub = 2, .vsub = 1, .is_yuv = true },
2660 { .format = DRM_FORMAT_NV12, .num_planes = 4,
2661 .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
2662 .hsub = 2, .vsub = 2, .is_yuv = true },
2663 { .format = DRM_FORMAT_P010, .num_planes = 4,
2664 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2665 .hsub = 2, .vsub = 2, .is_yuv = true },
2666 { .format = DRM_FORMAT_P012, .num_planes = 4,
2667 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2668 .hsub = 2, .vsub = 2, .is_yuv = true },
2669 { .format = DRM_FORMAT_P016, .num_planes = 4,
2670 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2671 .hsub = 2, .vsub = 2, .is_yuv = true },
2674 static const struct drm_format_info *
2675 lookup_format_info(const struct drm_format_info formats[],
2676 int num_formats, u32 format)
2680 for (i = 0; i < num_formats; i++) {
2681 if (formats[i].format == format)
2688 static const struct drm_format_info *
2689 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2691 switch (cmd->modifier[0]) {
2692 case I915_FORMAT_MOD_Y_TILED_CCS:
2693 case I915_FORMAT_MOD_Yf_TILED_CCS:
2694 return lookup_format_info(skl_ccs_formats,
2695 ARRAY_SIZE(skl_ccs_formats),
2697 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2698 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2699 return lookup_format_info(gen12_ccs_formats,
2700 ARRAY_SIZE(gen12_ccs_formats),
2707 bool is_ccs_modifier(u64 modifier)
2709 return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
2710 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
2711 modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2712 modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
2715 static int gen12_ccs_aux_stride(struct drm_framebuffer *fb, int ccs_plane)
2717 return DIV_ROUND_UP(fb->pitches[ccs_to_main_plane(fb, ccs_plane)],
2721 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
2722 u32 pixel_format, u64 modifier)
2724 struct intel_crtc *crtc;
2725 struct intel_plane *plane;
2728 * We assume the primary plane for pipe A has
2729 * the highest stride limits of them all,
2730 * if in case pipe A is disabled, use the first pipe from pipe_mask.
2732 crtc = intel_get_first_crtc(dev_priv);
2736 plane = to_intel_plane(crtc->base.primary);
2738 return plane->max_stride(plane, pixel_format, modifier,
2743 u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
2744 u32 pixel_format, u64 modifier)
2747 * Arbitrary limit for gen4+ chosen to match the
2748 * render engine max stride.
2750 * The new CCS hash mode makes remapping impossible
2752 if (!is_ccs_modifier(modifier)) {
2753 if (INTEL_GEN(dev_priv) >= 7)
2755 else if (INTEL_GEN(dev_priv) >= 4)
2759 return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
2763 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
2765 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2768 if (is_surface_linear(fb, color_plane)) {
2769 u32 max_stride = intel_plane_fb_max_stride(dev_priv,
2774 * To make remapping with linear generally feasible
2775 * we need the stride to be page aligned.
2777 if (fb->pitches[color_plane] > max_stride &&
2778 !is_ccs_modifier(fb->modifier))
2779 return intel_tile_size(dev_priv);
2784 tile_width = intel_tile_width_bytes(fb, color_plane);
2785 if (is_ccs_modifier(fb->modifier)) {
2787 * Display WA #0531: skl,bxt,kbl,glk
2789 * Render decompression and plane width > 3840
2790 * combined with horizontal panning requires the
2791 * plane stride to be a multiple of 4. We'll just
2792 * require the entire fb to accommodate that to avoid
2793 * potential runtime errors at plane configuration time.
2795 if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb->width > 3840)
2798 * The main surface pitch must be padded to a multiple of four
2801 else if (INTEL_GEN(dev_priv) >= 12)
2807 bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
2809 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2810 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2811 const struct drm_framebuffer *fb = plane_state->hw.fb;
2814 /* We don't want to deal with remapping with cursors */
2815 if (plane->id == PLANE_CURSOR)
2819 * The display engine limits already match/exceed the
2820 * render engine limits, so not much point in remapping.
2821 * Would also need to deal with the fence POT alignment
2822 * and gen2 2KiB GTT tile size.
2824 if (INTEL_GEN(dev_priv) < 4)
2828 * The new CCS hash mode isn't compatible with remapping as
2829 * the virtual address of the pages affects the compressed data.
2831 if (is_ccs_modifier(fb->modifier))
2834 /* Linear needs a page aligned stride for remapping */
2835 if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
2836 unsigned int alignment = intel_tile_size(dev_priv) - 1;
2838 for (i = 0; i < fb->format->num_planes; i++) {
2839 if (fb->pitches[i] & alignment)
2847 static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
2849 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2850 const struct drm_framebuffer *fb = plane_state->hw.fb;
2851 unsigned int rotation = plane_state->hw.rotation;
2852 u32 stride, max_stride;
2855 * No remapping for invisible planes since we don't have
2856 * an actual source viewport to remap.
2858 if (!plane_state->uapi.visible)
2861 if (!intel_plane_can_remap(plane_state))
2865 * FIXME: aux plane limits on gen9+ are
2866 * unclear in Bspec, for now no checking.
2868 stride = intel_fb_pitch(fb, 0, rotation);
2869 max_stride = plane->max_stride(plane, fb->format->format,
2870 fb->modifier, rotation);
2872 return stride > max_stride;
2876 intel_fb_plane_get_subsampling(int *hsub, int *vsub,
2877 const struct drm_framebuffer *fb,
2882 if (color_plane == 0) {
2890 * TODO: Deduct the subsampling from the char block for all CCS
2891 * formats and planes.
2893 if (!is_gen12_ccs_plane(fb, color_plane)) {
2894 *hsub = fb->format->hsub;
2895 *vsub = fb->format->vsub;
2900 main_plane = ccs_to_main_plane(fb, color_plane);
2901 *hsub = drm_format_info_block_width(fb->format, color_plane) /
2902 drm_format_info_block_width(fb->format, main_plane);
2905 * The min stride check in the core framebuffer_check() function
2906 * assumes that format->hsub applies to every plane except for the
2907 * first plane. That's incorrect for the CCS AUX plane of the first
2908 * plane, but for the above check to pass we must define the block
2909 * width with that subsampling applied to it. Adjust the width here
2910 * accordingly, so we can calculate the actual subsampling factor.
2912 if (main_plane == 0)
2913 *hsub *= fb->format->hsub;
2918 intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int ccs_plane, int x, int y)
2920 struct drm_i915_private *i915 = to_i915(fb->dev);
2921 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2924 int tile_width, tile_height;
2928 if (!is_ccs_plane(fb, ccs_plane))
2931 intel_tile_dims(fb, ccs_plane, &tile_width, &tile_height);
2932 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
2935 tile_height *= vsub;
2937 ccs_x = (x * hsub) % tile_width;
2938 ccs_y = (y * vsub) % tile_height;
2940 main_plane = ccs_to_main_plane(fb, ccs_plane);
2941 main_x = intel_fb->normal[main_plane].x % tile_width;
2942 main_y = intel_fb->normal[main_plane].y % tile_height;
2945 * CCS doesn't have its own x/y offset register, so the intra CCS tile
2946 * x/y offsets must match between CCS and the main surface.
2948 if (main_x != ccs_x || main_y != ccs_y) {
2949 drm_dbg_kms(&i915->drm,
2950 "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2953 intel_fb->normal[main_plane].x,
2954 intel_fb->normal[main_plane].y,
2963 intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int color_plane)
2965 int main_plane = is_ccs_plane(fb, color_plane) ?
2966 ccs_to_main_plane(fb, color_plane) : 0;
2967 int main_hsub, main_vsub;
2970 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, main_plane);
2971 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
2972 *w = fb->width / main_hsub / hsub;
2973 *h = fb->height / main_vsub / vsub;
2977 * Setup the rotated view for an FB plane and return the size the GTT mapping
2978 * requires for this view.
2981 setup_fb_rotation(int plane, const struct intel_remapped_plane_info *plane_info,
2982 u32 gtt_offset_rotated, int x, int y,
2983 unsigned int width, unsigned int height,
2984 unsigned int tile_size,
2985 unsigned int tile_width, unsigned int tile_height,
2986 struct drm_framebuffer *fb)
2988 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2989 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2990 unsigned int pitch_tiles;
2993 /* Y or Yf modifiers required for 90/270 rotation */
2994 if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
2995 fb->modifier != I915_FORMAT_MOD_Yf_TILED)
2998 if (drm_WARN_ON(fb->dev, plane >= ARRAY_SIZE(rot_info->plane)))
3001 rot_info->plane[plane] = *plane_info;
3003 intel_fb->rotated[plane].pitch = plane_info->height * tile_height;
3005 /* rotate the x/y offsets to match the GTT view */
3006 drm_rect_init(&r, x, y, width, height);
3008 plane_info->width * tile_width,
3009 plane_info->height * tile_height,
3010 DRM_MODE_ROTATE_270);
3014 /* rotate the tile dimensions to match the GTT view */
3015 pitch_tiles = intel_fb->rotated[plane].pitch / tile_height;
3016 swap(tile_width, tile_height);
3019 * We only keep the x/y offsets, so push all of the
3020 * gtt offset into the x/y offsets.
3022 intel_adjust_tile_offset(&x, &y,
3023 tile_width, tile_height,
3024 tile_size, pitch_tiles,
3025 gtt_offset_rotated * tile_size, 0);
3028 * First pixel of the framebuffer from
3029 * the start of the rotated gtt mapping.
3031 intel_fb->rotated[plane].x = x;
3032 intel_fb->rotated[plane].y = y;
3034 return plane_info->width * plane_info->height;
3038 intel_fill_fb_info(struct drm_i915_private *dev_priv,
3039 struct drm_framebuffer *fb)
3041 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3042 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3043 u32 gtt_offset_rotated = 0;
3044 unsigned int max_size = 0;
3045 int i, num_planes = fb->format->num_planes;
3046 unsigned int tile_size = intel_tile_size(dev_priv);
3048 for (i = 0; i < num_planes; i++) {
3049 unsigned int width, height;
3050 unsigned int cpp, size;
3055 cpp = fb->format->cpp[i];
3056 intel_fb_plane_dims(&width, &height, fb, i);
3058 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
3060 drm_dbg_kms(&dev_priv->drm,
3061 "bad fb plane %d offset: 0x%x\n",
3066 ret = intel_fb_check_ccs_xy(fb, i, x, y);
3071 * The fence (if used) is aligned to the start of the object
3072 * so having the framebuffer wrap around across the edge of the
3073 * fenced region doesn't really work. We have no API to configure
3074 * the fence start offset within the object (nor could we probably
3075 * on gen2/3). So it's just easier if we just require that the
3076 * fb layout agrees with the fence layout. We already check that the
3077 * fb stride matches the fence stride elsewhere.
3079 if (i == 0 && i915_gem_object_is_tiled(obj) &&
3080 (x + width) * cpp > fb->pitches[i]) {
3081 drm_dbg_kms(&dev_priv->drm,
3082 "bad fb plane %d offset: 0x%x\n",
3088 * First pixel of the framebuffer from
3089 * the start of the normal gtt mapping.
3091 intel_fb->normal[i].x = x;
3092 intel_fb->normal[i].y = y;
3094 offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i,
3098 offset /= tile_size;
3100 if (!is_surface_linear(fb, i)) {
3101 struct intel_remapped_plane_info plane_info;
3102 unsigned int tile_width, tile_height;
3104 intel_tile_dims(fb, i, &tile_width, &tile_height);
3106 plane_info.offset = offset;
3107 plane_info.stride = DIV_ROUND_UP(fb->pitches[i],
3109 plane_info.width = DIV_ROUND_UP(x + width, tile_width);
3110 plane_info.height = DIV_ROUND_UP(y + height,
3113 /* how many tiles does this plane need */
3114 size = plane_info.stride * plane_info.height;
3116 * If the plane isn't horizontally tile aligned,
3117 * we need one more tile.
3122 gtt_offset_rotated +=
3123 setup_fb_rotation(i, &plane_info,
3125 x, y, width, height,
3127 tile_width, tile_height,
3130 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
3131 x * cpp, tile_size);
3134 /* how many tiles in total needed in the bo */
3135 max_size = max(max_size, offset + size);
3138 if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
3139 drm_dbg_kms(&dev_priv->drm,
3140 "fb too big for bo (need %llu bytes, have %zu bytes)\n",
3141 mul_u32_u32(max_size, tile_size), obj->base.size);
3149 intel_plane_remap_gtt(struct intel_plane_state *plane_state)
3151 struct drm_i915_private *dev_priv =
3152 to_i915(plane_state->uapi.plane->dev);
3153 struct drm_framebuffer *fb = plane_state->hw.fb;
3154 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3155 struct intel_rotation_info *info = &plane_state->view.rotated;
3156 unsigned int rotation = plane_state->hw.rotation;
3157 int i, num_planes = fb->format->num_planes;
3158 unsigned int tile_size = intel_tile_size(dev_priv);
3159 unsigned int src_x, src_y;
3160 unsigned int src_w, src_h;
3163 memset(&plane_state->view, 0, sizeof(plane_state->view));
3164 plane_state->view.type = drm_rotation_90_or_270(rotation) ?
3165 I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED;
3167 src_x = plane_state->uapi.src.x1 >> 16;
3168 src_y = plane_state->uapi.src.y1 >> 16;
3169 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
3170 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
3172 drm_WARN_ON(&dev_priv->drm, is_ccs_modifier(fb->modifier));
3174 /* Make src coordinates relative to the viewport */
3175 drm_rect_translate(&plane_state->uapi.src,
3176 -(src_x << 16), -(src_y << 16));
3178 /* Rotate src coordinates to match rotated GTT view */
3179 if (drm_rotation_90_or_270(rotation))
3180 drm_rect_rotate(&plane_state->uapi.src,
3181 src_w << 16, src_h << 16,
3182 DRM_MODE_ROTATE_270);
3184 for (i = 0; i < num_planes; i++) {
3185 unsigned int hsub = i ? fb->format->hsub : 1;
3186 unsigned int vsub = i ? fb->format->vsub : 1;
3187 unsigned int cpp = fb->format->cpp[i];
3188 unsigned int tile_width, tile_height;
3189 unsigned int width, height;
3190 unsigned int pitch_tiles;
3194 intel_tile_dims(fb, i, &tile_width, &tile_height);
3198 width = src_w / hsub;
3199 height = src_h / vsub;
3202 * First pixel of the src viewport from the
3203 * start of the normal gtt mapping.
3205 x += intel_fb->normal[i].x;
3206 y += intel_fb->normal[i].y;
3208 offset = intel_compute_aligned_offset(dev_priv, &x, &y,
3209 fb, i, fb->pitches[i],
3210 DRM_MODE_ROTATE_0, tile_size);
3211 offset /= tile_size;
3213 drm_WARN_ON(&dev_priv->drm, i >= ARRAY_SIZE(info->plane));
3214 info->plane[i].offset = offset;
3215 info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],
3217 info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
3218 info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
3220 if (drm_rotation_90_or_270(rotation)) {
3223 /* rotate the x/y offsets to match the GTT view */
3224 drm_rect_init(&r, x, y, width, height);
3226 info->plane[i].width * tile_width,
3227 info->plane[i].height * tile_height,
3228 DRM_MODE_ROTATE_270);
3232 pitch_tiles = info->plane[i].height;
3233 plane_state->color_plane[i].stride = pitch_tiles * tile_height;
3235 /* rotate the tile dimensions to match the GTT view */
3236 swap(tile_width, tile_height);
3238 pitch_tiles = info->plane[i].width;
3239 plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp;
3243 * We only keep the x/y offsets, so push all of the
3244 * gtt offset into the x/y offsets.
3246 intel_adjust_tile_offset(&x, &y,
3247 tile_width, tile_height,
3248 tile_size, pitch_tiles,
3249 gtt_offset * tile_size, 0);
3251 gtt_offset += info->plane[i].width * info->plane[i].height;
3253 plane_state->color_plane[i].offset = 0;
3254 plane_state->color_plane[i].x = x;
3255 plane_state->color_plane[i].y = y;
3260 intel_plane_compute_gtt(struct intel_plane_state *plane_state)
3262 const struct intel_framebuffer *fb =
3263 to_intel_framebuffer(plane_state->hw.fb);
3264 unsigned int rotation = plane_state->hw.rotation;
3270 num_planes = fb->base.format->num_planes;
3272 if (intel_plane_needs_remap(plane_state)) {
3273 intel_plane_remap_gtt(plane_state);
3276 * Sometimes even remapping can't overcome
3277 * the stride limitations :( Can happen with
3278 * big plane sizes and suitably misaligned
3281 return intel_plane_check_stride(plane_state);
3284 intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation);
3286 for (i = 0; i < num_planes; i++) {
3287 plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation);
3288 plane_state->color_plane[i].offset = 0;
3290 if (drm_rotation_90_or_270(rotation)) {
3291 plane_state->color_plane[i].x = fb->rotated[i].x;
3292 plane_state->color_plane[i].y = fb->rotated[i].y;
3294 plane_state->color_plane[i].x = fb->normal[i].x;
3295 plane_state->color_plane[i].y = fb->normal[i].y;
3299 /* Rotate src coordinates to match rotated GTT view */
3300 if (drm_rotation_90_or_270(rotation))
3301 drm_rect_rotate(&plane_state->uapi.src,
3302 fb->base.width << 16, fb->base.height << 16,
3303 DRM_MODE_ROTATE_270);
3305 return intel_plane_check_stride(plane_state);
3308 static int i9xx_format_to_fourcc(int format)
3311 case DISPPLANE_8BPP:
3312 return DRM_FORMAT_C8;
3313 case DISPPLANE_BGRA555:
3314 return DRM_FORMAT_ARGB1555;
3315 case DISPPLANE_BGRX555:
3316 return DRM_FORMAT_XRGB1555;
3317 case DISPPLANE_BGRX565:
3318 return DRM_FORMAT_RGB565;
3320 case DISPPLANE_BGRX888:
3321 return DRM_FORMAT_XRGB8888;
3322 case DISPPLANE_RGBX888:
3323 return DRM_FORMAT_XBGR8888;
3324 case DISPPLANE_BGRA888:
3325 return DRM_FORMAT_ARGB8888;
3326 case DISPPLANE_RGBA888:
3327 return DRM_FORMAT_ABGR8888;
3328 case DISPPLANE_BGRX101010:
3329 return DRM_FORMAT_XRGB2101010;
3330 case DISPPLANE_RGBX101010:
3331 return DRM_FORMAT_XBGR2101010;
3332 case DISPPLANE_BGRA101010:
3333 return DRM_FORMAT_ARGB2101010;
3334 case DISPPLANE_RGBA101010:
3335 return DRM_FORMAT_ABGR2101010;
3336 case DISPPLANE_RGBX161616:
3337 return DRM_FORMAT_XBGR16161616F;
3341 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
3344 case PLANE_CTL_FORMAT_RGB_565:
3345 return DRM_FORMAT_RGB565;
3346 case PLANE_CTL_FORMAT_NV12:
3347 return DRM_FORMAT_NV12;
3348 case PLANE_CTL_FORMAT_XYUV:
3349 return DRM_FORMAT_XYUV8888;
3350 case PLANE_CTL_FORMAT_P010:
3351 return DRM_FORMAT_P010;
3352 case PLANE_CTL_FORMAT_P012:
3353 return DRM_FORMAT_P012;
3354 case PLANE_CTL_FORMAT_P016:
3355 return DRM_FORMAT_P016;
3356 case PLANE_CTL_FORMAT_Y210:
3357 return DRM_FORMAT_Y210;
3358 case PLANE_CTL_FORMAT_Y212:
3359 return DRM_FORMAT_Y212;
3360 case PLANE_CTL_FORMAT_Y216:
3361 return DRM_FORMAT_Y216;
3362 case PLANE_CTL_FORMAT_Y410:
3363 return DRM_FORMAT_XVYU2101010;
3364 case PLANE_CTL_FORMAT_Y412:
3365 return DRM_FORMAT_XVYU12_16161616;
3366 case PLANE_CTL_FORMAT_Y416:
3367 return DRM_FORMAT_XVYU16161616;
3369 case PLANE_CTL_FORMAT_XRGB_8888:
3372 return DRM_FORMAT_ABGR8888;
3374 return DRM_FORMAT_XBGR8888;
3377 return DRM_FORMAT_ARGB8888;
3379 return DRM_FORMAT_XRGB8888;
3381 case PLANE_CTL_FORMAT_XRGB_2101010:
3384 return DRM_FORMAT_ABGR2101010;
3386 return DRM_FORMAT_XBGR2101010;
3389 return DRM_FORMAT_ARGB2101010;
3391 return DRM_FORMAT_XRGB2101010;
3393 case PLANE_CTL_FORMAT_XRGB_16161616F:
3396 return DRM_FORMAT_ABGR16161616F;
3398 return DRM_FORMAT_XBGR16161616F;
3401 return DRM_FORMAT_ARGB16161616F;
3403 return DRM_FORMAT_XRGB16161616F;
3408 static struct i915_vma *
3409 initial_plane_vma(struct drm_i915_private *i915,
3410 struct intel_initial_plane_config *plane_config)
3412 struct drm_i915_gem_object *obj;
3413 struct i915_vma *vma;
3416 if (plane_config->size == 0)
3419 base = round_down(plane_config->base,
3420 I915_GTT_MIN_ALIGNMENT);
3421 size = round_up(plane_config->base + plane_config->size,
3422 I915_GTT_MIN_ALIGNMENT);
3426 * If the FB is too big, just don't use it since fbdev is not very
3427 * important and we should probably use that space with FBC or other
3430 if (size * 2 > i915->stolen_usable_size)
3433 obj = i915_gem_object_create_stolen_for_preallocated(i915, base, size);
3438 * Mark it WT ahead of time to avoid changing the
3439 * cache_level during fbdev initialization. The
3440 * unbind there would get stuck waiting for rcu.
3442 i915_gem_object_set_cache_coherency(obj, HAS_WT(i915) ?
3443 I915_CACHE_WT : I915_CACHE_NONE);
3445 switch (plane_config->tiling) {
3446 case I915_TILING_NONE:
3450 obj->tiling_and_stride =
3451 plane_config->fb->base.pitches[0] |
3452 plane_config->tiling;
3455 MISSING_CASE(plane_config->tiling);
3459 vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
3463 if (i915_ggtt_pin(vma, NULL, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base))
3466 if (i915_gem_object_is_tiled(obj) &&
3467 !i915_vma_is_map_and_fenceable(vma))
3473 i915_gem_object_put(obj);
3478 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
3479 struct intel_initial_plane_config *plane_config)
3481 struct drm_device *dev = crtc->base.dev;
3482 struct drm_i915_private *dev_priv = to_i915(dev);
3483 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
3484 struct drm_framebuffer *fb = &plane_config->fb->base;
3485 struct i915_vma *vma;
3487 switch (fb->modifier) {
3488 case DRM_FORMAT_MOD_LINEAR:
3489 case I915_FORMAT_MOD_X_TILED:
3490 case I915_FORMAT_MOD_Y_TILED:
3493 drm_dbg(&dev_priv->drm,
3494 "Unsupported modifier for initial FB: 0x%llx\n",
3499 vma = initial_plane_vma(dev_priv, plane_config);
3503 mode_cmd.pixel_format = fb->format->format;
3504 mode_cmd.width = fb->width;
3505 mode_cmd.height = fb->height;
3506 mode_cmd.pitches[0] = fb->pitches[0];
3507 mode_cmd.modifier[0] = fb->modifier;
3508 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
3510 if (intel_framebuffer_init(to_intel_framebuffer(fb),
3511 vma->obj, &mode_cmd)) {
3512 drm_dbg_kms(&dev_priv->drm, "intel fb init failed\n");
3516 plane_config->vma = vma;
3525 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
3526 struct intel_plane_state *plane_state,
3529 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
3531 plane_state->uapi.visible = visible;
3534 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
3536 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
3539 static void fixup_active_planes(struct intel_crtc_state *crtc_state)
3541 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3542 struct drm_plane *plane;
3545 * Active_planes aliases if multiple "primary" or cursor planes
3546 * have been used on the same (or wrong) pipe. plane_mask uses
3547 * unique ids, hence we can use that to reconstruct active_planes.
3549 crtc_state->active_planes = 0;
3551 drm_for_each_plane_mask(plane, &dev_priv->drm,
3552 crtc_state->uapi.plane_mask)
3553 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
3556 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
3557 struct intel_plane *plane)
3559 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3560 struct intel_crtc_state *crtc_state =
3561 to_intel_crtc_state(crtc->base.state);
3562 struct intel_plane_state *plane_state =
3563 to_intel_plane_state(plane->base.state);
3565 drm_dbg_kms(&dev_priv->drm,
3566 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
3567 plane->base.base.id, plane->base.name,
3568 crtc->base.base.id, crtc->base.name);
3570 intel_set_plane_visible(crtc_state, plane_state, false);
3571 fixup_active_planes(crtc_state);
3572 crtc_state->data_rate[plane->id] = 0;
3573 crtc_state->min_cdclk[plane->id] = 0;
3575 if (plane->id == PLANE_PRIMARY)
3576 hsw_disable_ips(crtc_state);
3579 * Vblank time updates from the shadow to live plane control register
3580 * are blocked if the memory self-refresh mode is active at that
3581 * moment. So to make sure the plane gets truly disabled, disable
3582 * first the self-refresh mode. The self-refresh enable bit in turn
3583 * will be checked/applied by the HW only at the next frame start
3584 * event which is after the vblank start event, so we need to have a
3585 * wait-for-vblank between disabling the plane and the pipe.
3587 if (HAS_GMCH(dev_priv) &&
3588 intel_set_memory_cxsr(dev_priv, false))
3589 intel_wait_for_vblank(dev_priv, crtc->pipe);
3592 * Gen2 reports pipe underruns whenever all planes are disabled.
3593 * So disable underrun reporting before all the planes get disabled.
3595 if (IS_GEN(dev_priv, 2) && !crtc_state->active_planes)
3596 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
3598 intel_disable_plane(plane, crtc_state);
3601 static struct intel_frontbuffer *
3602 to_intel_frontbuffer(struct drm_framebuffer *fb)
3604 return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
3608 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
3609 struct intel_initial_plane_config *plane_config)
3611 struct drm_device *dev = intel_crtc->base.dev;
3612 struct drm_i915_private *dev_priv = to_i915(dev);
3614 struct drm_plane *primary = intel_crtc->base.primary;
3615 struct drm_plane_state *plane_state = primary->state;
3616 struct intel_plane *intel_plane = to_intel_plane(primary);
3617 struct intel_plane_state *intel_state =
3618 to_intel_plane_state(plane_state);
3619 struct drm_framebuffer *fb;
3620 struct i915_vma *vma;
3622 if (!plane_config->fb)
3625 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
3626 fb = &plane_config->fb->base;
3627 vma = plane_config->vma;
3632 * Failed to alloc the obj, check to see if we should share
3633 * an fb with another CRTC instead
3635 for_each_crtc(dev, c) {
3636 struct intel_plane_state *state;
3638 if (c == &intel_crtc->base)
3641 if (!to_intel_crtc(c)->active)
3644 state = to_intel_plane_state(c->primary->state);
3648 if (intel_plane_ggtt_offset(state) == plane_config->base) {
3656 * We've failed to reconstruct the BIOS FB. Current display state
3657 * indicates that the primary plane is visible, but has a NULL FB,
3658 * which will lead to problems later if we don't fix it up. The
3659 * simplest solution is to just disable the primary plane now and
3660 * pretend the BIOS never had it enabled.
3662 intel_plane_disable_noatomic(intel_crtc, intel_plane);
3667 intel_state->hw.rotation = plane_config->rotation;
3668 intel_fill_fb_ggtt_view(&intel_state->view, fb,
3669 intel_state->hw.rotation);
3670 intel_state->color_plane[0].stride =
3671 intel_fb_pitch(fb, 0, intel_state->hw.rotation);
3673 __i915_vma_pin(vma);
3674 intel_state->vma = i915_vma_get(vma);
3675 if (intel_plane_uses_fence(intel_state) && i915_vma_pin_fence(vma) == 0)
3677 intel_state->flags |= PLANE_HAS_FENCE;
3679 plane_state->src_x = 0;
3680 plane_state->src_y = 0;
3681 plane_state->src_w = fb->width << 16;
3682 plane_state->src_h = fb->height << 16;
3684 plane_state->crtc_x = 0;
3685 plane_state->crtc_y = 0;
3686 plane_state->crtc_w = fb->width;
3687 plane_state->crtc_h = fb->height;
3689 intel_state->uapi.src = drm_plane_state_src(plane_state);
3690 intel_state->uapi.dst = drm_plane_state_dest(plane_state);
3692 if (plane_config->tiling)
3693 dev_priv->preserve_bios_swizzle = true;
3695 plane_state->fb = fb;
3696 drm_framebuffer_get(fb);
3698 plane_state->crtc = &intel_crtc->base;
3699 intel_plane_copy_uapi_to_hw_state(intel_state, intel_state);
3701 intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
3703 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
3704 &to_intel_frontbuffer(fb)->bits);
3707 static int skl_max_plane_width(const struct drm_framebuffer *fb,
3709 unsigned int rotation)
3711 int cpp = fb->format->cpp[color_plane];
3713 switch (fb->modifier) {
3714 case DRM_FORMAT_MOD_LINEAR:
3715 case I915_FORMAT_MOD_X_TILED:
3717 * Validated limit is 4k, but has 5k should
3718 * work apart from the following features:
3719 * - Ytile (already limited to 4k)
3720 * - FP16 (already limited to 4k)
3721 * - render compression (already limited to 4k)
3722 * - KVMR sprite and cursor (don't care)
3723 * - horizontal panning (TODO verify this)
3724 * - pipe and plane scaling (TODO verify this)
3730 case I915_FORMAT_MOD_Y_TILED_CCS:
3731 case I915_FORMAT_MOD_Yf_TILED_CCS:
3732 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
3733 /* FIXME AUX plane? */
3734 case I915_FORMAT_MOD_Y_TILED:
3735 case I915_FORMAT_MOD_Yf_TILED:
3741 MISSING_CASE(fb->modifier);
3746 static int glk_max_plane_width(const struct drm_framebuffer *fb,
3748 unsigned int rotation)
3750 int cpp = fb->format->cpp[color_plane];
3752 switch (fb->modifier) {
3753 case DRM_FORMAT_MOD_LINEAR:
3754 case I915_FORMAT_MOD_X_TILED:
3759 case I915_FORMAT_MOD_Y_TILED_CCS:
3760 case I915_FORMAT_MOD_Yf_TILED_CCS:
3761 /* FIXME AUX plane? */
3762 case I915_FORMAT_MOD_Y_TILED:
3763 case I915_FORMAT_MOD_Yf_TILED:
3769 MISSING_CASE(fb->modifier);
3774 static int icl_min_plane_width(const struct drm_framebuffer *fb)
3776 /* Wa_14011264657, Wa_14011050563: gen11+ */
3777 switch (fb->format->format) {
3780 case DRM_FORMAT_RGB565:
3782 case DRM_FORMAT_XRGB8888:
3783 case DRM_FORMAT_XBGR8888:
3784 case DRM_FORMAT_ARGB8888:
3785 case DRM_FORMAT_ABGR8888:
3786 case DRM_FORMAT_XRGB2101010:
3787 case DRM_FORMAT_XBGR2101010:
3788 case DRM_FORMAT_ARGB2101010:
3789 case DRM_FORMAT_ABGR2101010:
3790 case DRM_FORMAT_XVYU2101010:
3791 case DRM_FORMAT_Y212:
3792 case DRM_FORMAT_Y216:
3794 case DRM_FORMAT_NV12:
3796 case DRM_FORMAT_P010:
3797 case DRM_FORMAT_P012:
3798 case DRM_FORMAT_P016:
3800 case DRM_FORMAT_XRGB16161616F:
3801 case DRM_FORMAT_XBGR16161616F:
3802 case DRM_FORMAT_ARGB16161616F:
3803 case DRM_FORMAT_ABGR16161616F:
3804 case DRM_FORMAT_XVYU12_16161616:
3805 case DRM_FORMAT_XVYU16161616:
3812 static int icl_max_plane_width(const struct drm_framebuffer *fb,
3814 unsigned int rotation)
3819 static int skl_max_plane_height(void)
3824 static int icl_max_plane_height(void)
3830 skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
3831 int main_x, int main_y, u32 main_offset,
3834 const struct drm_framebuffer *fb = plane_state->hw.fb;
3835 int aux_x = plane_state->color_plane[ccs_plane].x;
3836 int aux_y = plane_state->color_plane[ccs_plane].y;
3837 u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
3838 u32 alignment = intel_surf_alignment(fb, ccs_plane);
3842 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
3843 while (aux_offset >= main_offset && aux_y <= main_y) {
3846 if (aux_x == main_x && aux_y == main_y)
3849 if (aux_offset == 0)
3854 aux_offset = intel_plane_adjust_aligned_offset(&x, &y,
3860 aux_x = x * hsub + aux_x % hsub;
3861 aux_y = y * vsub + aux_y % vsub;
3864 if (aux_x != main_x || aux_y != main_y)
3867 plane_state->color_plane[ccs_plane].offset = aux_offset;
3868 plane_state->color_plane[ccs_plane].x = aux_x;
3869 plane_state->color_plane[ccs_plane].y = aux_y;
3875 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
3879 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3880 plane_state->color_plane[0].offset, 0);
3885 static int skl_check_main_surface(struct intel_plane_state *plane_state)
3887 struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev);
3888 const struct drm_framebuffer *fb = plane_state->hw.fb;
3889 unsigned int rotation = plane_state->hw.rotation;
3890 int x = plane_state->uapi.src.x1 >> 16;
3891 int y = plane_state->uapi.src.y1 >> 16;
3892 int w = drm_rect_width(&plane_state->uapi.src) >> 16;
3893 int h = drm_rect_height(&plane_state->uapi.src) >> 16;
3894 int max_width, min_width, max_height;
3895 u32 alignment, offset;
3896 int aux_plane = intel_main_to_aux_plane(fb, 0);
3897 u32 aux_offset = plane_state->color_plane[aux_plane].offset;
3899 if (INTEL_GEN(dev_priv) >= 11) {
3900 max_width = icl_max_plane_width(fb, 0, rotation);
3901 min_width = icl_min_plane_width(fb);
3902 } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
3903 max_width = glk_max_plane_width(fb, 0, rotation);
3906 max_width = skl_max_plane_width(fb, 0, rotation);
3910 if (INTEL_GEN(dev_priv) >= 11)
3911 max_height = icl_max_plane_height();
3913 max_height = skl_max_plane_height();
3915 if (w > max_width || w < min_width || h > max_height) {
3916 drm_dbg_kms(&dev_priv->drm,
3917 "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n",
3918 w, h, min_width, max_width, max_height);
3922 intel_add_fb_offsets(&x, &y, plane_state, 0);
3923 offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);
3924 alignment = intel_surf_alignment(fb, 0);
3925 if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment)))
3929 * AUX surface offset is specified as the distance from the
3930 * main surface offset, and it must be non-negative. Make
3931 * sure that is what we will get.
3933 if (offset > aux_offset)
3934 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3935 offset, aux_offset & ~(alignment - 1));
3938 * When using an X-tiled surface, the plane blows up
3939 * if the x offset + width exceed the stride.
3941 * TODO: linear and Y-tiled seem fine, Yf untested,
3943 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3944 int cpp = fb->format->cpp[0];
3946 while ((x + w) * cpp > plane_state->color_plane[0].stride) {
3948 drm_dbg_kms(&dev_priv->drm,
3949 "Unable to find suitable display surface offset due to X-tiling\n");
3953 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3954 offset, offset - alignment);
3959 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3960 * they match with the main surface x/y offsets.
3962 if (is_ccs_modifier(fb->modifier)) {
3963 while (!skl_check_main_ccs_coordinates(plane_state, x, y,
3964 offset, aux_plane)) {
3968 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3969 offset, offset - alignment);
3972 if (x != plane_state->color_plane[aux_plane].x ||
3973 y != plane_state->color_plane[aux_plane].y) {
3974 drm_dbg_kms(&dev_priv->drm,
3975 "Unable to find suitable display surface offset due to CCS\n");
3980 plane_state->color_plane[0].offset = offset;
3981 plane_state->color_plane[0].x = x;
3982 plane_state->color_plane[0].y = y;
3985 * Put the final coordinates back so that the src
3986 * coordinate checks will see the right values.
3988 drm_rect_translate_to(&plane_state->uapi.src,
3994 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3996 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
3997 const struct drm_framebuffer *fb = plane_state->hw.fb;
3998 unsigned int rotation = plane_state->hw.rotation;
4000 int max_width = skl_max_plane_width(fb, uv_plane, rotation);
4001 int max_height = 4096;
4002 int x = plane_state->uapi.src.x1 >> 17;
4003 int y = plane_state->uapi.src.y1 >> 17;
4004 int w = drm_rect_width(&plane_state->uapi.src) >> 17;
4005 int h = drm_rect_height(&plane_state->uapi.src) >> 17;
4008 intel_add_fb_offsets(&x, &y, plane_state, uv_plane);
4009 offset = intel_plane_compute_aligned_offset(&x, &y,
4010 plane_state, uv_plane);
4012 /* FIXME not quite sure how/if these apply to the chroma plane */
4013 if (w > max_width || h > max_height) {
4014 drm_dbg_kms(&i915->drm,
4015 "CbCr source size %dx%d too big (limit %dx%d)\n",
4016 w, h, max_width, max_height);
4020 if (is_ccs_modifier(fb->modifier)) {
4021 int ccs_plane = main_to_ccs_plane(fb, uv_plane);
4022 int aux_offset = plane_state->color_plane[ccs_plane].offset;
4023 int alignment = intel_surf_alignment(fb, uv_plane);
4025 if (offset > aux_offset)
4026 offset = intel_plane_adjust_aligned_offset(&x, &y,
4030 aux_offset & ~(alignment - 1));
4032 while (!skl_check_main_ccs_coordinates(plane_state, x, y,
4033 offset, ccs_plane)) {
4037 offset = intel_plane_adjust_aligned_offset(&x, &y,
4040 offset, offset - alignment);
4043 if (x != plane_state->color_plane[ccs_plane].x ||
4044 y != plane_state->color_plane[ccs_plane].y) {
4045 drm_dbg_kms(&i915->drm,
4046 "Unable to find suitable display surface offset due to CCS\n");
4051 plane_state->color_plane[uv_plane].offset = offset;
4052 plane_state->color_plane[uv_plane].x = x;
4053 plane_state->color_plane[uv_plane].y = y;
4058 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
4060 const struct drm_framebuffer *fb = plane_state->hw.fb;
4061 int src_x = plane_state->uapi.src.x1 >> 16;
4062 int src_y = plane_state->uapi.src.y1 >> 16;
4066 for (ccs_plane = 0; ccs_plane < fb->format->num_planes; ccs_plane++) {
4067 int main_hsub, main_vsub;
4071 if (!is_ccs_plane(fb, ccs_plane))
4074 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb,
4075 ccs_to_main_plane(fb, ccs_plane));
4076 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
4083 intel_add_fb_offsets(&x, &y, plane_state, ccs_plane);
4085 offset = intel_plane_compute_aligned_offset(&x, &y,
4089 plane_state->color_plane[ccs_plane].offset = offset;
4090 plane_state->color_plane[ccs_plane].x = (x * hsub +
4093 plane_state->color_plane[ccs_plane].y = (y * vsub +
4101 int skl_check_plane_surface(struct intel_plane_state *plane_state)
4103 const struct drm_framebuffer *fb = plane_state->hw.fb;
4106 ret = intel_plane_compute_gtt(plane_state);
4110 if (!plane_state->uapi.visible)
4114 * Handle the AUX surface first since the main surface setup depends on
4117 if (is_ccs_modifier(fb->modifier)) {
4118 ret = skl_check_ccs_aux_surface(plane_state);
4123 if (intel_format_info_is_yuv_semiplanar(fb->format,
4125 ret = skl_check_nv12_aux_surface(plane_state);
4130 for (i = fb->format->num_planes; i < ARRAY_SIZE(plane_state->color_plane); i++) {
4131 plane_state->color_plane[i].offset = ~0xfff;
4132 plane_state->color_plane[i].x = 0;
4133 plane_state->color_plane[i].y = 0;
4136 ret = skl_check_main_surface(plane_state);
4143 static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state,
4144 const struct intel_plane_state *plane_state,
4145 unsigned int *num, unsigned int *den)
4147 const struct drm_framebuffer *fb = plane_state->hw.fb;
4148 unsigned int cpp = fb->format->cpp[0];
4151 * g4x bspec says 64bpp pixel rate can't exceed 80%
4152 * of cdclk when the sprite plane is enabled on the
4153 * same pipe. ilk/snb bspec says 64bpp pixel rate is
4154 * never allowed to exceed 80% of cdclk. Let's just go
4155 * with the ilk/snb limit always.
4166 static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
4167 const struct intel_plane_state *plane_state)
4169 unsigned int pixel_rate;
4170 unsigned int num, den;
4173 * Note that crtc_state->pixel_rate accounts for both
4174 * horizontal and vertical panel fitter downscaling factors.
4175 * Pre-HSW bspec tells us to only consider the horizontal
4176 * downscaling factor here. We ignore that and just consider
4177 * both for simplicity.
4179 pixel_rate = crtc_state->pixel_rate;
4181 i9xx_plane_ratio(crtc_state, plane_state, &num, &den);
4183 /* two pixels per clock with double wide pipe */
4184 if (crtc_state->double_wide)
4187 return DIV_ROUND_UP(pixel_rate * num, den);
4191 i9xx_plane_max_stride(struct intel_plane *plane,
4192 u32 pixel_format, u64 modifier,
4193 unsigned int rotation)
4195 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4197 if (!HAS_GMCH(dev_priv)) {
4199 } else if (INTEL_GEN(dev_priv) >= 4) {
4200 if (modifier == I915_FORMAT_MOD_X_TILED)
4204 } else if (INTEL_GEN(dev_priv) >= 3) {
4205 if (modifier == I915_FORMAT_MOD_X_TILED)
4210 if (plane->i9xx_plane == PLANE_C)
4217 static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
4219 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4220 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4223 if (crtc_state->gamma_enable)
4224 dspcntr |= DISPPLANE_GAMMA_ENABLE;
4226 if (crtc_state->csc_enable)
4227 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
4229 if (INTEL_GEN(dev_priv) < 5)
4230 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
4235 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
4236 const struct intel_plane_state *plane_state)
4238 struct drm_i915_private *dev_priv =
4239 to_i915(plane_state->uapi.plane->dev);
4240 const struct drm_framebuffer *fb = plane_state->hw.fb;
4241 unsigned int rotation = plane_state->hw.rotation;
4244 dspcntr = DISPLAY_PLANE_ENABLE;
4246 if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
4247 IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
4248 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
4250 switch (fb->format->format) {
4252 dspcntr |= DISPPLANE_8BPP;
4254 case DRM_FORMAT_XRGB1555:
4255 dspcntr |= DISPPLANE_BGRX555;
4257 case DRM_FORMAT_ARGB1555:
4258 dspcntr |= DISPPLANE_BGRA555;
4260 case DRM_FORMAT_RGB565:
4261 dspcntr |= DISPPLANE_BGRX565;
4263 case DRM_FORMAT_XRGB8888:
4264 dspcntr |= DISPPLANE_BGRX888;
4266 case DRM_FORMAT_XBGR8888:
4267 dspcntr |= DISPPLANE_RGBX888;
4269 case DRM_FORMAT_ARGB8888:
4270 dspcntr |= DISPPLANE_BGRA888;
4272 case DRM_FORMAT_ABGR8888:
4273 dspcntr |= DISPPLANE_RGBA888;
4275 case DRM_FORMAT_XRGB2101010:
4276 dspcntr |= DISPPLANE_BGRX101010;
4278 case DRM_FORMAT_XBGR2101010:
4279 dspcntr |= DISPPLANE_RGBX101010;
4281 case DRM_FORMAT_ARGB2101010:
4282 dspcntr |= DISPPLANE_BGRA101010;
4284 case DRM_FORMAT_ABGR2101010:
4285 dspcntr |= DISPPLANE_RGBA101010;
4287 case DRM_FORMAT_XBGR16161616F:
4288 dspcntr |= DISPPLANE_RGBX161616;
4291 MISSING_CASE(fb->format->format);
4295 if (INTEL_GEN(dev_priv) >= 4 &&
4296 fb->modifier == I915_FORMAT_MOD_X_TILED)
4297 dspcntr |= DISPPLANE_TILED;
4299 if (rotation & DRM_MODE_ROTATE_180)
4300 dspcntr |= DISPPLANE_ROTATE_180;
4302 if (rotation & DRM_MODE_REFLECT_X)
4303 dspcntr |= DISPPLANE_MIRROR;
4308 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
4310 struct drm_i915_private *dev_priv =
4311 to_i915(plane_state->uapi.plane->dev);
4312 const struct drm_framebuffer *fb = plane_state->hw.fb;
4313 int src_x, src_y, src_w;
4317 ret = intel_plane_compute_gtt(plane_state);
4321 if (!plane_state->uapi.visible)
4324 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
4325 src_x = plane_state->uapi.src.x1 >> 16;
4326 src_y = plane_state->uapi.src.y1 >> 16;
4328 /* Undocumented hardware limit on i965/g4x/vlv/chv */
4329 if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048)
4332 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
4334 if (INTEL_GEN(dev_priv) >= 4)
4335 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
4341 * Put the final coordinates back so that the src
4342 * coordinate checks will see the right values.
4344 drm_rect_translate_to(&plane_state->uapi.src,
4345 src_x << 16, src_y << 16);
4347 /* HSW/BDW do this automagically in hardware */
4348 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
4349 unsigned int rotation = plane_state->hw.rotation;
4350 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
4351 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
4353 if (rotation & DRM_MODE_ROTATE_180) {
4356 } else if (rotation & DRM_MODE_REFLECT_X) {
4361 plane_state->color_plane[0].offset = offset;
4362 plane_state->color_plane[0].x = src_x;
4363 plane_state->color_plane[0].y = src_y;
4368 static bool i9xx_plane_has_windowing(struct intel_plane *plane)
4370 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4371 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4373 if (IS_CHERRYVIEW(dev_priv))
4374 return i9xx_plane == PLANE_B;
4375 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
4377 else if (IS_GEN(dev_priv, 4))
4378 return i9xx_plane == PLANE_C;
4380 return i9xx_plane == PLANE_B ||
4381 i9xx_plane == PLANE_C;
4385 i9xx_plane_check(struct intel_crtc_state *crtc_state,
4386 struct intel_plane_state *plane_state)
4388 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
4391 ret = chv_plane_check_rotation(plane_state);
4395 ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
4397 DRM_PLANE_HELPER_NO_SCALING,
4398 DRM_PLANE_HELPER_NO_SCALING,
4399 i9xx_plane_has_windowing(plane),
4404 ret = i9xx_check_plane_surface(plane_state);
4408 if (!plane_state->uapi.visible)
4411 ret = intel_plane_check_src_coordinates(plane_state);
4415 plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
4420 static void i9xx_update_plane(struct intel_plane *plane,
4421 const struct intel_crtc_state *crtc_state,
4422 const struct intel_plane_state *plane_state)
4424 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4425 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4427 int x = plane_state->color_plane[0].x;
4428 int y = plane_state->color_plane[0].y;
4429 int crtc_x = plane_state->uapi.dst.x1;
4430 int crtc_y = plane_state->uapi.dst.y1;
4431 int crtc_w = drm_rect_width(&plane_state->uapi.dst);
4432 int crtc_h = drm_rect_height(&plane_state->uapi.dst);
4433 unsigned long irqflags;
4437 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
4439 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
4441 if (INTEL_GEN(dev_priv) >= 4)
4442 dspaddr_offset = plane_state->color_plane[0].offset;
4444 dspaddr_offset = linear_offset;
4446 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4448 intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane),
4449 plane_state->color_plane[0].stride);
4451 if (INTEL_GEN(dev_priv) < 4) {
4453 * PLANE_A doesn't actually have a full window
4454 * generator but let's assume we still need to
4455 * program whatever is there.
4457 intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),
4458 (crtc_y << 16) | crtc_x);
4459 intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
4460 ((crtc_h - 1) << 16) | (crtc_w - 1));
4461 } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
4462 intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane),
4463 (crtc_y << 16) | crtc_x);
4464 intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane),
4465 ((crtc_h - 1) << 16) | (crtc_w - 1));
4466 intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0);
4469 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
4470 intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane),
4472 } else if (INTEL_GEN(dev_priv) >= 4) {
4473 intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane),
4475 intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane),
4480 * The control register self-arms if the plane was previously
4481 * disabled. Try to make the plane enable atomic by writing
4482 * the control register just before the surface register.
4484 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
4485 if (INTEL_GEN(dev_priv) >= 4)
4486 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
4487 intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
4489 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
4490 intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
4492 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4495 static void i9xx_disable_plane(struct intel_plane *plane,
4496 const struct intel_crtc_state *crtc_state)
4498 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4499 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4500 unsigned long irqflags;
4504 * DSPCNTR pipe gamma enable on g4x+ and pipe csc
4505 * enable on ilk+ affect the pipe bottom color as
4506 * well, so we must configure them even if the plane
4509 * On pre-g4x there is no way to gamma correct the
4510 * pipe bottom color but we'll keep on doing this
4511 * anyway so that the crtc state readout works correctly.
4513 dspcntr = i9xx_plane_ctl_crtc(crtc_state);
4515 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4517 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
4518 if (INTEL_GEN(dev_priv) >= 4)
4519 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0);
4521 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0);
4523 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4526 static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
4529 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4530 enum intel_display_power_domain power_domain;
4531 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4532 intel_wakeref_t wakeref;
4537 * Not 100% correct for planes that can move between pipes,
4538 * but that's only the case for gen2-4 which don't have any
4539 * display power wells.
4541 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
4542 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
4546 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
4548 ret = val & DISPLAY_PLANE_ENABLE;
4550 if (INTEL_GEN(dev_priv) >= 5)
4551 *pipe = plane->pipe;
4553 *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
4554 DISPPLANE_SEL_PIPE_SHIFT;
4556 intel_display_power_put(dev_priv, power_domain, wakeref);
4561 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
4563 struct drm_device *dev = intel_crtc->base.dev;
4564 struct drm_i915_private *dev_priv = to_i915(dev);
4565 unsigned long irqflags;
4567 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4569 intel_de_write_fw(dev_priv, SKL_PS_CTRL(intel_crtc->pipe, id), 0);
4570 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
4571 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
4573 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4577 * This function detaches (aka. unbinds) unused scalers in hardware
4579 static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
4581 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
4582 const struct intel_crtc_scaler_state *scaler_state =
4583 &crtc_state->scaler_state;
4586 /* loop through and disable scalers that aren't in use */
4587 for (i = 0; i < intel_crtc->num_scalers; i++) {
4588 if (!scaler_state->scalers[i].in_use)
4589 skl_detach_scaler(intel_crtc, i);
4593 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
4594 int color_plane, unsigned int rotation)
4597 * The stride is either expressed as a multiple of 64 bytes chunks for
4598 * linear buffers or in number of tiles for tiled buffers.
4600 if (is_surface_linear(fb, color_plane))
4602 else if (drm_rotation_90_or_270(rotation))
4603 return intel_tile_height(fb, color_plane);
4605 return intel_tile_width_bytes(fb, color_plane);
4608 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
4611 const struct drm_framebuffer *fb = plane_state->hw.fb;
4612 unsigned int rotation = plane_state->hw.rotation;
4613 u32 stride = plane_state->color_plane[color_plane].stride;
4615 if (color_plane >= fb->format->num_planes)
4618 return stride / skl_plane_stride_mult(fb, color_plane, rotation);
4621 static u32 skl_plane_ctl_format(u32 pixel_format)
4623 switch (pixel_format) {
4625 return PLANE_CTL_FORMAT_INDEXED;
4626 case DRM_FORMAT_RGB565:
4627 return PLANE_CTL_FORMAT_RGB_565;
4628 case DRM_FORMAT_XBGR8888:
4629 case DRM_FORMAT_ABGR8888:
4630 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
4631 case DRM_FORMAT_XRGB8888:
4632 case DRM_FORMAT_ARGB8888:
4633 return PLANE_CTL_FORMAT_XRGB_8888;
4634 case DRM_FORMAT_XBGR2101010:
4635 case DRM_FORMAT_ABGR2101010:
4636 return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX;
4637 case DRM_FORMAT_XRGB2101010:
4638 case DRM_FORMAT_ARGB2101010:
4639 return PLANE_CTL_FORMAT_XRGB_2101010;
4640 case DRM_FORMAT_XBGR16161616F:
4641 case DRM_FORMAT_ABGR16161616F:
4642 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
4643 case DRM_FORMAT_XRGB16161616F:
4644 case DRM_FORMAT_ARGB16161616F:
4645 return PLANE_CTL_FORMAT_XRGB_16161616F;
4646 case DRM_FORMAT_XYUV8888:
4647 return PLANE_CTL_FORMAT_XYUV;
4648 case DRM_FORMAT_YUYV:
4649 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
4650 case DRM_FORMAT_YVYU:
4651 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
4652 case DRM_FORMAT_UYVY:
4653 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
4654 case DRM_FORMAT_VYUY:
4655 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
4656 case DRM_FORMAT_NV12:
4657 return PLANE_CTL_FORMAT_NV12;
4658 case DRM_FORMAT_P010:
4659 return PLANE_CTL_FORMAT_P010;
4660 case DRM_FORMAT_P012:
4661 return PLANE_CTL_FORMAT_P012;
4662 case DRM_FORMAT_P016:
4663 return PLANE_CTL_FORMAT_P016;
4664 case DRM_FORMAT_Y210:
4665 return PLANE_CTL_FORMAT_Y210;
4666 case DRM_FORMAT_Y212:
4667 return PLANE_CTL_FORMAT_Y212;
4668 case DRM_FORMAT_Y216:
4669 return PLANE_CTL_FORMAT_Y216;
4670 case DRM_FORMAT_XVYU2101010:
4671 return PLANE_CTL_FORMAT_Y410;
4672 case DRM_FORMAT_XVYU12_16161616:
4673 return PLANE_CTL_FORMAT_Y412;
4674 case DRM_FORMAT_XVYU16161616:
4675 return PLANE_CTL_FORMAT_Y416;
4677 MISSING_CASE(pixel_format);
4683 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
4685 if (!plane_state->hw.fb->format->has_alpha)
4686 return PLANE_CTL_ALPHA_DISABLE;
4688 switch (plane_state->hw.pixel_blend_mode) {
4689 case DRM_MODE_BLEND_PIXEL_NONE:
4690 return PLANE_CTL_ALPHA_DISABLE;
4691 case DRM_MODE_BLEND_PREMULTI:
4692 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
4693 case DRM_MODE_BLEND_COVERAGE:
4694 return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
4696 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4697 return PLANE_CTL_ALPHA_DISABLE;
4701 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
4703 if (!plane_state->hw.fb->format->has_alpha)
4704 return PLANE_COLOR_ALPHA_DISABLE;
4706 switch (plane_state->hw.pixel_blend_mode) {
4707 case DRM_MODE_BLEND_PIXEL_NONE:
4708 return PLANE_COLOR_ALPHA_DISABLE;
4709 case DRM_MODE_BLEND_PREMULTI:
4710 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
4711 case DRM_MODE_BLEND_COVERAGE:
4712 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
4714 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4715 return PLANE_COLOR_ALPHA_DISABLE;
4719 static u32 skl_plane_ctl_tiling(u64 fb_modifier)
4721 switch (fb_modifier) {
4722 case DRM_FORMAT_MOD_LINEAR:
4724 case I915_FORMAT_MOD_X_TILED:
4725 return PLANE_CTL_TILED_X;
4726 case I915_FORMAT_MOD_Y_TILED:
4727 return PLANE_CTL_TILED_Y;
4728 case I915_FORMAT_MOD_Y_TILED_CCS:
4729 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4730 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
4731 return PLANE_CTL_TILED_Y |
4732 PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
4733 PLANE_CTL_CLEAR_COLOR_DISABLE;
4734 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
4735 return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
4736 case I915_FORMAT_MOD_Yf_TILED:
4737 return PLANE_CTL_TILED_YF;
4738 case I915_FORMAT_MOD_Yf_TILED_CCS:
4739 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4741 MISSING_CASE(fb_modifier);
4747 static u32 skl_plane_ctl_rotate(unsigned int rotate)
4750 case DRM_MODE_ROTATE_0:
4753 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
4754 * while i915 HW rotation is clockwise, thats why this swapping.
4756 case DRM_MODE_ROTATE_90:
4757 return PLANE_CTL_ROTATE_270;
4758 case DRM_MODE_ROTATE_180:
4759 return PLANE_CTL_ROTATE_180;
4760 case DRM_MODE_ROTATE_270:
4761 return PLANE_CTL_ROTATE_90;
4763 MISSING_CASE(rotate);
4769 static u32 cnl_plane_ctl_flip(unsigned int reflect)
4774 case DRM_MODE_REFLECT_X:
4775 return PLANE_CTL_FLIP_HORIZONTAL;
4776 case DRM_MODE_REFLECT_Y:
4778 MISSING_CASE(reflect);
4784 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
4786 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4789 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4792 if (crtc_state->gamma_enable)
4793 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
4795 if (crtc_state->csc_enable)
4796 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
4801 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
4802 const struct intel_plane_state *plane_state)
4804 struct drm_i915_private *dev_priv =
4805 to_i915(plane_state->uapi.plane->dev);
4806 const struct drm_framebuffer *fb = plane_state->hw.fb;
4807 unsigned int rotation = plane_state->hw.rotation;
4808 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
4811 plane_ctl = PLANE_CTL_ENABLE;
4813 if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
4814 plane_ctl |= skl_plane_ctl_alpha(plane_state);
4815 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
4817 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
4818 plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
4820 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4821 plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
4824 plane_ctl |= skl_plane_ctl_format(fb->format->format);
4825 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
4826 plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
4828 if (INTEL_GEN(dev_priv) >= 10)
4829 plane_ctl |= cnl_plane_ctl_flip(rotation &
4830 DRM_MODE_REFLECT_MASK);
4832 if (key->flags & I915_SET_COLORKEY_DESTINATION)
4833 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
4834 else if (key->flags & I915_SET_COLORKEY_SOURCE)
4835 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
4840 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
4842 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4843 u32 plane_color_ctl = 0;
4845 if (INTEL_GEN(dev_priv) >= 11)
4846 return plane_color_ctl;
4848 if (crtc_state->gamma_enable)
4849 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
4851 if (crtc_state->csc_enable)
4852 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
4854 return plane_color_ctl;
4857 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
4858 const struct intel_plane_state *plane_state)
4860 struct drm_i915_private *dev_priv =
4861 to_i915(plane_state->uapi.plane->dev);
4862 const struct drm_framebuffer *fb = plane_state->hw.fb;
4863 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
4864 u32 plane_color_ctl = 0;
4866 plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
4867 plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
4869 if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
4870 switch (plane_state->hw.color_encoding) {
4871 case DRM_COLOR_YCBCR_BT709:
4872 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
4874 case DRM_COLOR_YCBCR_BT2020:
4876 PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020;
4880 PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601;
4882 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4883 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
4884 } else if (fb->format->is_yuv) {
4885 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
4888 return plane_color_ctl;
4892 __intel_display_resume(struct drm_device *dev,
4893 struct drm_atomic_state *state,
4894 struct drm_modeset_acquire_ctx *ctx)
4896 struct drm_crtc_state *crtc_state;
4897 struct drm_crtc *crtc;
4900 intel_modeset_setup_hw_state(dev, ctx);
4901 intel_vga_redisable(to_i915(dev));
4907 * We've duplicated the state, pointers to the old state are invalid.
4909 * Don't attempt to use the old state until we commit the duplicated state.
4911 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
4913 * Force recalculation even if we restore
4914 * current state. With fast modeset this may not result
4915 * in a modeset when the state is compatible.
4917 crtc_state->mode_changed = true;
4920 /* ignore any reset values/BIOS leftovers in the WM registers */
4921 if (!HAS_GMCH(to_i915(dev)))
4922 to_intel_atomic_state(state)->skip_intermediate_wm = true;
4924 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
4926 drm_WARN_ON(dev, ret == -EDEADLK);
4930 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
4932 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
4933 intel_has_gpu_reset(&dev_priv->gt));
4936 void intel_prepare_reset(struct drm_i915_private *dev_priv)
4938 struct drm_device *dev = &dev_priv->drm;
4939 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4940 struct drm_atomic_state *state;
4943 /* reset doesn't touch the display */
4944 if (!dev_priv->params.force_reset_modeset_test &&
4945 !gpu_reset_clobbers_display(dev_priv))
4948 /* We have a modeset vs reset deadlock, defensively unbreak it. */
4949 set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4950 smp_mb__after_atomic();
4951 wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET);
4953 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
4954 drm_dbg_kms(&dev_priv->drm,
4955 "Modeset potentially stuck, unbreaking through wedging\n");
4956 intel_gt_set_wedged(&dev_priv->gt);
4960 * Need mode_config.mutex so that we don't
4961 * trample ongoing ->detect() and whatnot.
4963 mutex_lock(&dev->mode_config.mutex);
4964 drm_modeset_acquire_init(ctx, 0);
4966 ret = drm_modeset_lock_all_ctx(dev, ctx);
4967 if (ret != -EDEADLK)
4970 drm_modeset_backoff(ctx);
4973 * Disabling the crtcs gracefully seems nicer. Also the
4974 * g33 docs say we should at least disable all the planes.
4976 state = drm_atomic_helper_duplicate_state(dev, ctx);
4977 if (IS_ERR(state)) {
4978 ret = PTR_ERR(state);
4979 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n",
4984 ret = drm_atomic_helper_disable_all(dev, ctx);
4986 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
4988 drm_atomic_state_put(state);
4992 dev_priv->modeset_restore_state = state;
4993 state->acquire_ctx = ctx;
4996 void intel_finish_reset(struct drm_i915_private *dev_priv)
4998 struct drm_device *dev = &dev_priv->drm;
4999 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
5000 struct drm_atomic_state *state;
5003 /* reset doesn't touch the display */
5004 if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
5007 state = fetch_and_zero(&dev_priv->modeset_restore_state);
5011 /* reset doesn't touch the display */
5012 if (!gpu_reset_clobbers_display(dev_priv)) {
5013 /* for testing only restore the display */
5014 ret = __intel_display_resume(dev, state, ctx);
5016 drm_err(&dev_priv->drm,
5017 "Restoring old state failed with %i\n", ret);
5020 * The display has been reset as well,
5021 * so need a full re-initialization.
5023 intel_pps_unlock_regs_wa(dev_priv);
5024 intel_modeset_init_hw(dev_priv);
5025 intel_init_clock_gating(dev_priv);
5027 spin_lock_irq(&dev_priv->irq_lock);
5028 if (dev_priv->display.hpd_irq_setup)
5029 dev_priv->display.hpd_irq_setup(dev_priv);
5030 spin_unlock_irq(&dev_priv->irq_lock);
5032 ret = __intel_display_resume(dev, state, ctx);
5034 drm_err(&dev_priv->drm,
5035 "Restoring old state failed with %i\n", ret);
5037 intel_hpd_init(dev_priv);
5040 drm_atomic_state_put(state);
5042 drm_modeset_drop_locks(ctx);
5043 drm_modeset_acquire_fini(ctx);
5044 mutex_unlock(&dev->mode_config.mutex);
5046 clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
5049 static void icl_set_pipe_chicken(struct intel_crtc *crtc)
5051 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5052 enum pipe pipe = crtc->pipe;
5055 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe));
5058 * Display WA #1153: icl
5059 * enable hardware to bypass the alpha math
5060 * and rounding for per-pixel values 00 and 0xff
5062 tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
5064 * Display WA # 1605353570: icl
5065 * Set the pixel rounding bit to 1 for allowing
5066 * passthrough of Frame buffer pixels unmodified
5069 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
5070 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
5073 static void intel_fdi_normal_train(struct intel_crtc *crtc)
5075 struct drm_device *dev = crtc->base.dev;
5076 struct drm_i915_private *dev_priv = to_i915(dev);
5077 enum pipe pipe = crtc->pipe;
5081 /* enable normal train */
5082 reg = FDI_TX_CTL(pipe);
5083 temp = intel_de_read(dev_priv, reg);
5084 if (IS_IVYBRIDGE(dev_priv)) {
5085 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
5086 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
5088 temp &= ~FDI_LINK_TRAIN_NONE;
5089 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
5091 intel_de_write(dev_priv, reg, temp);
5093 reg = FDI_RX_CTL(pipe);
5094 temp = intel_de_read(dev_priv, reg);
5095 if (HAS_PCH_CPT(dev_priv)) {
5096 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5097 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
5099 temp &= ~FDI_LINK_TRAIN_NONE;
5100 temp |= FDI_LINK_TRAIN_NONE;
5102 intel_de_write(dev_priv, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
5104 /* wait one idle pattern time */
5105 intel_de_posting_read(dev_priv, reg);
5108 /* IVB wants error correction enabled */
5109 if (IS_IVYBRIDGE(dev_priv))
5110 intel_de_write(dev_priv, reg,
5111 intel_de_read(dev_priv, reg) | FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE);
5114 /* The FDI link training functions for ILK/Ibexpeak. */
5115 static void ilk_fdi_link_train(struct intel_crtc *crtc,
5116 const struct intel_crtc_state *crtc_state)
5118 struct drm_device *dev = crtc->base.dev;
5119 struct drm_i915_private *dev_priv = to_i915(dev);
5120 enum pipe pipe = crtc->pipe;
5124 /* FDI needs bits from pipe first */
5125 assert_pipe_enabled(dev_priv, crtc_state->cpu_transcoder);
5127 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5129 reg = FDI_RX_IMR(pipe);
5130 temp = intel_de_read(dev_priv, reg);
5131 temp &= ~FDI_RX_SYMBOL_LOCK;
5132 temp &= ~FDI_RX_BIT_LOCK;
5133 intel_de_write(dev_priv, reg, temp);
5134 intel_de_read(dev_priv, reg);
5137 /* enable CPU FDI TX and PCH FDI RX */
5138 reg = FDI_TX_CTL(pipe);
5139 temp = intel_de_read(dev_priv, reg);
5140 temp &= ~FDI_DP_PORT_WIDTH_MASK;
5141 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5142 temp &= ~FDI_LINK_TRAIN_NONE;
5143 temp |= FDI_LINK_TRAIN_PATTERN_1;
5144 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
5146 reg = FDI_RX_CTL(pipe);
5147 temp = intel_de_read(dev_priv, reg);
5148 temp &= ~FDI_LINK_TRAIN_NONE;
5149 temp |= FDI_LINK_TRAIN_PATTERN_1;
5150 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
5152 intel_de_posting_read(dev_priv, reg);
5155 /* Ironlake workaround, enable clock pointer after FDI enable*/
5156 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
5157 FDI_RX_PHASE_SYNC_POINTER_OVR);
5158 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
5159 FDI_RX_PHASE_SYNC_POINTER_OVR | FDI_RX_PHASE_SYNC_POINTER_EN);
5161 reg = FDI_RX_IIR(pipe);
5162 for (tries = 0; tries < 5; tries++) {
5163 temp = intel_de_read(dev_priv, reg);
5164 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5166 if ((temp & FDI_RX_BIT_LOCK)) {
5167 drm_dbg_kms(&dev_priv->drm, "FDI train 1 done.\n");
5168 intel_de_write(dev_priv, reg, temp | FDI_RX_BIT_LOCK);
5173 drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
5176 reg = FDI_TX_CTL(pipe);
5177 temp = intel_de_read(dev_priv, reg);
5178 temp &= ~FDI_LINK_TRAIN_NONE;
5179 temp |= FDI_LINK_TRAIN_PATTERN_2;
5180 intel_de_write(dev_priv, reg, temp);
5182 reg = FDI_RX_CTL(pipe);
5183 temp = intel_de_read(dev_priv, reg);
5184 temp &= ~FDI_LINK_TRAIN_NONE;
5185 temp |= FDI_LINK_TRAIN_PATTERN_2;
5186 intel_de_write(dev_priv, reg, temp);
5188 intel_de_posting_read(dev_priv, reg);
5191 reg = FDI_RX_IIR(pipe);
5192 for (tries = 0; tries < 5; tries++) {
5193 temp = intel_de_read(dev_priv, reg);
5194 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5196 if (temp & FDI_RX_SYMBOL_LOCK) {
5197 intel_de_write(dev_priv, reg,
5198 temp | FDI_RX_SYMBOL_LOCK);
5199 drm_dbg_kms(&dev_priv->drm, "FDI train 2 done.\n");
5204 drm_err(&dev_priv->drm, "FDI train 2 fail!\n");
5206 drm_dbg_kms(&dev_priv->drm, "FDI train done\n");
5210 static const int snb_b_fdi_train_param[] = {
5211 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
5212 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
5213 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
5214 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
5217 /* The FDI link training functions for SNB/Cougarpoint. */
5218 static void gen6_fdi_link_train(struct intel_crtc *crtc,
5219 const struct intel_crtc_state *crtc_state)
5221 struct drm_device *dev = crtc->base.dev;
5222 struct drm_i915_private *dev_priv = to_i915(dev);
5223 enum pipe pipe = crtc->pipe;
5227 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5229 reg = FDI_RX_IMR(pipe);
5230 temp = intel_de_read(dev_priv, reg);
5231 temp &= ~FDI_RX_SYMBOL_LOCK;
5232 temp &= ~FDI_RX_BIT_LOCK;
5233 intel_de_write(dev_priv, reg, temp);
5235 intel_de_posting_read(dev_priv, reg);
5238 /* enable CPU FDI TX and PCH FDI RX */
5239 reg = FDI_TX_CTL(pipe);
5240 temp = intel_de_read(dev_priv, reg);
5241 temp &= ~FDI_DP_PORT_WIDTH_MASK;
5242 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5243 temp &= ~FDI_LINK_TRAIN_NONE;
5244 temp |= FDI_LINK_TRAIN_PATTERN_1;
5245 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5247 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5248 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
5250 intel_de_write(dev_priv, FDI_RX_MISC(pipe),
5251 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
5253 reg = FDI_RX_CTL(pipe);
5254 temp = intel_de_read(dev_priv, reg);
5255 if (HAS_PCH_CPT(dev_priv)) {
5256 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5257 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5259 temp &= ~FDI_LINK_TRAIN_NONE;
5260 temp |= FDI_LINK_TRAIN_PATTERN_1;
5262 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
5264 intel_de_posting_read(dev_priv, reg);
5267 for (i = 0; i < 4; i++) {
5268 reg = FDI_TX_CTL(pipe);
5269 temp = intel_de_read(dev_priv, reg);
5270 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5271 temp |= snb_b_fdi_train_param[i];
5272 intel_de_write(dev_priv, reg, temp);
5274 intel_de_posting_read(dev_priv, reg);
5277 for (retry = 0; retry < 5; retry++) {
5278 reg = FDI_RX_IIR(pipe);
5279 temp = intel_de_read(dev_priv, reg);
5280 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5281 if (temp & FDI_RX_BIT_LOCK) {
5282 intel_de_write(dev_priv, reg,
5283 temp | FDI_RX_BIT_LOCK);
5284 drm_dbg_kms(&dev_priv->drm,
5285 "FDI train 1 done.\n");
5294 drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
5297 reg = FDI_TX_CTL(pipe);
5298 temp = intel_de_read(dev_priv, reg);
5299 temp &= ~FDI_LINK_TRAIN_NONE;
5300 temp |= FDI_LINK_TRAIN_PATTERN_2;
5301 if (IS_GEN(dev_priv, 6)) {
5302 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5304 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5306 intel_de_write(dev_priv, reg, temp);
5308 reg = FDI_RX_CTL(pipe);
5309 temp = intel_de_read(dev_priv, reg);
5310 if (HAS_PCH_CPT(dev_priv)) {
5311 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5312 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
5314 temp &= ~FDI_LINK_TRAIN_NONE;
5315 temp |= FDI_LINK_TRAIN_PATTERN_2;
5317 intel_de_write(dev_priv, reg, temp);
5319 intel_de_posting_read(dev_priv, reg);
5322 for (i = 0; i < 4; i++) {
5323 reg = FDI_TX_CTL(pipe);
5324 temp = intel_de_read(dev_priv, reg);
5325 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5326 temp |= snb_b_fdi_train_param[i];
5327 intel_de_write(dev_priv, reg, temp);
5329 intel_de_posting_read(dev_priv, reg);
5332 for (retry = 0; retry < 5; retry++) {
5333 reg = FDI_RX_IIR(pipe);
5334 temp = intel_de_read(dev_priv, reg);
5335 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5336 if (temp & FDI_RX_SYMBOL_LOCK) {
5337 intel_de_write(dev_priv, reg,
5338 temp | FDI_RX_SYMBOL_LOCK);
5339 drm_dbg_kms(&dev_priv->drm,
5340 "FDI train 2 done.\n");
5349 drm_err(&dev_priv->drm, "FDI train 2 fail!\n");
5351 drm_dbg_kms(&dev_priv->drm, "FDI train done.\n");
5354 /* Manual link training for Ivy Bridge A0 parts */
5355 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
5356 const struct intel_crtc_state *crtc_state)
5358 struct drm_device *dev = crtc->base.dev;
5359 struct drm_i915_private *dev_priv = to_i915(dev);
5360 enum pipe pipe = crtc->pipe;
5364 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5366 reg = FDI_RX_IMR(pipe);
5367 temp = intel_de_read(dev_priv, reg);
5368 temp &= ~FDI_RX_SYMBOL_LOCK;
5369 temp &= ~FDI_RX_BIT_LOCK;
5370 intel_de_write(dev_priv, reg, temp);
5372 intel_de_posting_read(dev_priv, reg);
5375 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR before link train 0x%x\n",
5376 intel_de_read(dev_priv, FDI_RX_IIR(pipe)));
5378 /* Try each vswing and preemphasis setting twice before moving on */
5379 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
5380 /* disable first in case we need to retry */
5381 reg = FDI_TX_CTL(pipe);
5382 temp = intel_de_read(dev_priv, reg);
5383 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
5384 temp &= ~FDI_TX_ENABLE;
5385 intel_de_write(dev_priv, reg, temp);
5387 reg = FDI_RX_CTL(pipe);
5388 temp = intel_de_read(dev_priv, reg);
5389 temp &= ~FDI_LINK_TRAIN_AUTO;
5390 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5391 temp &= ~FDI_RX_ENABLE;
5392 intel_de_write(dev_priv, reg, temp);
5394 /* enable CPU FDI TX and PCH FDI RX */
5395 reg = FDI_TX_CTL(pipe);
5396 temp = intel_de_read(dev_priv, reg);
5397 temp &= ~FDI_DP_PORT_WIDTH_MASK;
5398 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5399 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
5400 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5401 temp |= snb_b_fdi_train_param[j/2];
5402 temp |= FDI_COMPOSITE_SYNC;
5403 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
5405 intel_de_write(dev_priv, FDI_RX_MISC(pipe),
5406 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
5408 reg = FDI_RX_CTL(pipe);
5409 temp = intel_de_read(dev_priv, reg);
5410 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5411 temp |= FDI_COMPOSITE_SYNC;
5412 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
5414 intel_de_posting_read(dev_priv, reg);
5415 udelay(1); /* should be 0.5us */
5417 for (i = 0; i < 4; i++) {
5418 reg = FDI_RX_IIR(pipe);
5419 temp = intel_de_read(dev_priv, reg);
5420 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5422 if (temp & FDI_RX_BIT_LOCK ||
5423 (intel_de_read(dev_priv, reg) & FDI_RX_BIT_LOCK)) {
5424 intel_de_write(dev_priv, reg,
5425 temp | FDI_RX_BIT_LOCK);
5426 drm_dbg_kms(&dev_priv->drm,
5427 "FDI train 1 done, level %i.\n",
5431 udelay(1); /* should be 0.5us */
5434 drm_dbg_kms(&dev_priv->drm,
5435 "FDI train 1 fail on vswing %d\n", j / 2);
5440 reg = FDI_TX_CTL(pipe);
5441 temp = intel_de_read(dev_priv, reg);
5442 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
5443 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
5444 intel_de_write(dev_priv, reg, temp);
5446 reg = FDI_RX_CTL(pipe);
5447 temp = intel_de_read(dev_priv, reg);
5448 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5449 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
5450 intel_de_write(dev_priv, reg, temp);
5452 intel_de_posting_read(dev_priv, reg);
5453 udelay(2); /* should be 1.5us */
5455 for (i = 0; i < 4; i++) {
5456 reg = FDI_RX_IIR(pipe);
5457 temp = intel_de_read(dev_priv, reg);
5458 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5460 if (temp & FDI_RX_SYMBOL_LOCK ||
5461 (intel_de_read(dev_priv, reg) & FDI_RX_SYMBOL_LOCK)) {
5462 intel_de_write(dev_priv, reg,
5463 temp | FDI_RX_SYMBOL_LOCK);
5464 drm_dbg_kms(&dev_priv->drm,
5465 "FDI train 2 done, level %i.\n",
5469 udelay(2); /* should be 1.5us */
5472 drm_dbg_kms(&dev_priv->drm,
5473 "FDI train 2 fail on vswing %d\n", j / 2);
5477 drm_dbg_kms(&dev_priv->drm, "FDI train done.\n");
5480 static void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
5482 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
5483 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
5484 enum pipe pipe = intel_crtc->pipe;
5488 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5489 reg = FDI_RX_CTL(pipe);
5490 temp = intel_de_read(dev_priv, reg);
5491 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
5492 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5493 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5494 intel_de_write(dev_priv, reg, temp | FDI_RX_PLL_ENABLE);
5496 intel_de_posting_read(dev_priv, reg);
5499 /* Switch from Rawclk to PCDclk */
5500 temp = intel_de_read(dev_priv, reg);
5501 intel_de_write(dev_priv, reg, temp | FDI_PCDCLK);
5503 intel_de_posting_read(dev_priv, reg);
5506 /* Enable CPU FDI TX PLL, always on for Ironlake */
5507 reg = FDI_TX_CTL(pipe);
5508 temp = intel_de_read(dev_priv, reg);
5509 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5510 intel_de_write(dev_priv, reg, temp | FDI_TX_PLL_ENABLE);
5512 intel_de_posting_read(dev_priv, reg);
5517 static void ilk_fdi_pll_disable(struct intel_crtc *intel_crtc)
5519 struct drm_device *dev = intel_crtc->base.dev;
5520 struct drm_i915_private *dev_priv = to_i915(dev);
5521 enum pipe pipe = intel_crtc->pipe;
5525 /* Switch from PCDclk to Rawclk */
5526 reg = FDI_RX_CTL(pipe);
5527 temp = intel_de_read(dev_priv, reg);
5528 intel_de_write(dev_priv, reg, temp & ~FDI_PCDCLK);
5530 /* Disable CPU FDI TX PLL */
5531 reg = FDI_TX_CTL(pipe);
5532 temp = intel_de_read(dev_priv, reg);
5533 intel_de_write(dev_priv, reg, temp & ~FDI_TX_PLL_ENABLE);
5535 intel_de_posting_read(dev_priv, reg);
5538 reg = FDI_RX_CTL(pipe);
5539 temp = intel_de_read(dev_priv, reg);
5540 intel_de_write(dev_priv, reg, temp & ~FDI_RX_PLL_ENABLE);
5542 /* Wait for the clocks to turn off. */
5543 intel_de_posting_read(dev_priv, reg);
5547 static void ilk_fdi_disable(struct intel_crtc *crtc)
5549 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5550 enum pipe pipe = crtc->pipe;
5554 /* disable CPU FDI tx and PCH FDI rx */
5555 reg = FDI_TX_CTL(pipe);
5556 temp = intel_de_read(dev_priv, reg);
5557 intel_de_write(dev_priv, reg, temp & ~FDI_TX_ENABLE);
5558 intel_de_posting_read(dev_priv, reg);
5560 reg = FDI_RX_CTL(pipe);
5561 temp = intel_de_read(dev_priv, reg);
5562 temp &= ~(0x7 << 16);
5563 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5564 intel_de_write(dev_priv, reg, temp & ~FDI_RX_ENABLE);
5566 intel_de_posting_read(dev_priv, reg);
5569 /* Ironlake workaround, disable clock pointer after downing FDI */
5570 if (HAS_PCH_IBX(dev_priv))
5571 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
5572 FDI_RX_PHASE_SYNC_POINTER_OVR);
5574 /* still set train pattern 1 */
5575 reg = FDI_TX_CTL(pipe);
5576 temp = intel_de_read(dev_priv, reg);
5577 temp &= ~FDI_LINK_TRAIN_NONE;
5578 temp |= FDI_LINK_TRAIN_PATTERN_1;
5579 intel_de_write(dev_priv, reg, temp);
5581 reg = FDI_RX_CTL(pipe);
5582 temp = intel_de_read(dev_priv, reg);
5583 if (HAS_PCH_CPT(dev_priv)) {
5584 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5585 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5587 temp &= ~FDI_LINK_TRAIN_NONE;
5588 temp |= FDI_LINK_TRAIN_PATTERN_1;
5590 /* BPC in FDI rx is consistent with that in PIPECONF */
5591 temp &= ~(0x07 << 16);
5592 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5593 intel_de_write(dev_priv, reg, temp);
5595 intel_de_posting_read(dev_priv, reg);
5599 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
5601 struct drm_crtc *crtc;
5604 drm_for_each_crtc(crtc, &dev_priv->drm) {
5605 struct drm_crtc_commit *commit;
5606 spin_lock(&crtc->commit_lock);
5607 commit = list_first_entry_or_null(&crtc->commit_list,
5608 struct drm_crtc_commit, commit_entry);
5609 cleanup_done = commit ?
5610 try_wait_for_completion(&commit->cleanup_done) : true;
5611 spin_unlock(&crtc->commit_lock);
5616 drm_crtc_wait_one_vblank(crtc);
5624 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
5628 intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_GATE);
5630 mutex_lock(&dev_priv->sb_lock);
5632 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5633 temp |= SBI_SSCCTL_DISABLE;
5634 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5636 mutex_unlock(&dev_priv->sb_lock);
5639 /* Program iCLKIP clock to the desired frequency */
5640 static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
5642 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5643 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5644 int clock = crtc_state->hw.adjusted_mode.crtc_clock;
5645 u32 divsel, phaseinc, auxdiv, phasedir = 0;
5648 lpt_disable_iclkip(dev_priv);
5650 /* The iCLK virtual clock root frequency is in MHz,
5651 * but the adjusted_mode->crtc_clock in in KHz. To get the
5652 * divisors, it is necessary to divide one by another, so we
5653 * convert the virtual clock precision to KHz here for higher
5656 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
5657 u32 iclk_virtual_root_freq = 172800 * 1000;
5658 u32 iclk_pi_range = 64;
5659 u32 desired_divisor;
5661 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5663 divsel = (desired_divisor / iclk_pi_range) - 2;
5664 phaseinc = desired_divisor % iclk_pi_range;
5667 * Near 20MHz is a corner case which is
5668 * out of range for the 7-bit divisor
5674 /* This should not happen with any sane values */
5675 drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
5676 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
5677 drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(phasedir) &
5678 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
5680 drm_dbg_kms(&dev_priv->drm,
5681 "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
5682 clock, auxdiv, divsel, phasedir, phaseinc);
5684 mutex_lock(&dev_priv->sb_lock);
5686 /* Program SSCDIVINTPHASE6 */
5687 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5688 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
5689 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
5690 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
5691 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
5692 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
5693 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
5694 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
5696 /* Program SSCAUXDIV */
5697 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5698 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
5699 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
5700 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
5702 /* Enable modulator and associated divider */
5703 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5704 temp &= ~SBI_SSCCTL_DISABLE;
5705 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5707 mutex_unlock(&dev_priv->sb_lock);
5709 /* Wait for initialization time */
5712 intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_UNGATE);
5715 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
5717 u32 divsel, phaseinc, auxdiv;
5718 u32 iclk_virtual_root_freq = 172800 * 1000;
5719 u32 iclk_pi_range = 64;
5720 u32 desired_divisor;
5723 if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
5726 mutex_lock(&dev_priv->sb_lock);
5728 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5729 if (temp & SBI_SSCCTL_DISABLE) {
5730 mutex_unlock(&dev_priv->sb_lock);
5734 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5735 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
5736 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
5737 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
5738 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
5740 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5741 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
5742 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
5744 mutex_unlock(&dev_priv->sb_lock);
5746 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
5748 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5749 desired_divisor << auxdiv);
5752 static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
5753 enum pipe pch_transcoder)
5755 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5756 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5757 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5759 intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
5760 intel_de_read(dev_priv, HTOTAL(cpu_transcoder)));
5761 intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
5762 intel_de_read(dev_priv, HBLANK(cpu_transcoder)));
5763 intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
5764 intel_de_read(dev_priv, HSYNC(cpu_transcoder)));
5766 intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
5767 intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
5768 intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
5769 intel_de_read(dev_priv, VBLANK(cpu_transcoder)));
5770 intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
5771 intel_de_read(dev_priv, VSYNC(cpu_transcoder)));
5772 intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
5773 intel_de_read(dev_priv, VSYNCSHIFT(cpu_transcoder)));
5776 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
5780 temp = intel_de_read(dev_priv, SOUTH_CHICKEN1);
5781 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
5784 drm_WARN_ON(&dev_priv->drm,
5785 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) &
5787 drm_WARN_ON(&dev_priv->drm,
5788 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) &
5791 temp &= ~FDI_BC_BIFURCATION_SELECT;
5793 temp |= FDI_BC_BIFURCATION_SELECT;
5795 drm_dbg_kms(&dev_priv->drm, "%sabling fdi C rx\n",
5796 enable ? "en" : "dis");
5797 intel_de_write(dev_priv, SOUTH_CHICKEN1, temp);
5798 intel_de_posting_read(dev_priv, SOUTH_CHICKEN1);
5801 static void ivb_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
5803 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5804 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5806 switch (crtc->pipe) {
5810 if (crtc_state->fdi_lanes > 2)
5811 cpt_set_fdi_bc_bifurcation(dev_priv, false);
5813 cpt_set_fdi_bc_bifurcation(dev_priv, true);
5817 cpt_set_fdi_bc_bifurcation(dev_priv, true);
5826 * Finds the encoder associated with the given CRTC. This can only be
5827 * used when we know that the CRTC isn't feeding multiple encoders!
5829 static struct intel_encoder *
5830 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
5831 const struct intel_crtc_state *crtc_state)
5833 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5834 const struct drm_connector_state *connector_state;
5835 const struct drm_connector *connector;
5836 struct intel_encoder *encoder = NULL;
5837 int num_encoders = 0;
5840 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
5841 if (connector_state->crtc != &crtc->base)
5844 encoder = to_intel_encoder(connector_state->best_encoder);
5848 drm_WARN(encoder->base.dev, num_encoders != 1,
5849 "%d encoders for pipe %c\n",
5850 num_encoders, pipe_name(crtc->pipe));
5856 * Enable PCH resources required for PCH ports:
5858 * - FDI training & RX/TX
5859 * - update transcoder timings
5860 * - DP transcoding bits
5863 static void ilk_pch_enable(const struct intel_atomic_state *state,
5864 const struct intel_crtc_state *crtc_state)
5866 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5867 struct drm_device *dev = crtc->base.dev;
5868 struct drm_i915_private *dev_priv = to_i915(dev);
5869 enum pipe pipe = crtc->pipe;
5872 assert_pch_transcoder_disabled(dev_priv, pipe);
5874 if (IS_IVYBRIDGE(dev_priv))
5875 ivb_update_fdi_bc_bifurcation(crtc_state);
5877 /* Write the TU size bits before fdi link training, so that error
5878 * detection works. */
5879 intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
5880 intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
5882 /* For PCH output, training FDI link */
5883 dev_priv->display.fdi_link_train(crtc, crtc_state);
5885 /* We need to program the right clock selection before writing the pixel
5886 * mutliplier into the DPLL. */
5887 if (HAS_PCH_CPT(dev_priv)) {
5890 temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
5891 temp |= TRANS_DPLL_ENABLE(pipe);
5892 sel = TRANS_DPLLB_SEL(pipe);
5893 if (crtc_state->shared_dpll ==
5894 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
5898 intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
5901 /* XXX: pch pll's can be enabled any time before we enable the PCH
5902 * transcoder, and we actually should do this to not upset any PCH
5903 * transcoder that already use the clock when we share it.
5905 * Note that enable_shared_dpll tries to do the right thing, but
5906 * get_shared_dpll unconditionally resets the pll - we need that to have
5907 * the right LVDS enable sequence. */
5908 intel_enable_shared_dpll(crtc_state);
5910 /* set transcoder timing, panel must allow it */
5911 assert_panel_unlocked(dev_priv, pipe);
5912 ilk_pch_transcoder_set_timings(crtc_state, pipe);
5914 intel_fdi_normal_train(crtc);
5916 /* For PCH DP, enable TRANS_DP_CTL */
5917 if (HAS_PCH_CPT(dev_priv) &&
5918 intel_crtc_has_dp_encoder(crtc_state)) {
5919 const struct drm_display_mode *adjusted_mode =
5920 &crtc_state->hw.adjusted_mode;
5921 u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5922 i915_reg_t reg = TRANS_DP_CTL(pipe);
5925 temp = intel_de_read(dev_priv, reg);
5926 temp &= ~(TRANS_DP_PORT_SEL_MASK |
5927 TRANS_DP_SYNC_MASK |
5929 temp |= TRANS_DP_OUTPUT_ENABLE;
5930 temp |= bpc << 9; /* same format but at 11:9 */
5932 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
5933 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
5934 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
5935 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
5937 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
5938 drm_WARN_ON(dev, port < PORT_B || port > PORT_D);
5939 temp |= TRANS_DP_PORT_SEL(port);
5941 intel_de_write(dev_priv, reg, temp);
5944 ilk_enable_pch_transcoder(crtc_state);
5947 void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
5949 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5950 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5951 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5953 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
5955 lpt_program_iclkip(crtc_state);
5957 /* Set transcoder timing. */
5958 ilk_pch_transcoder_set_timings(crtc_state, PIPE_A);
5960 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
5963 static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
5966 i915_reg_t dslreg = PIPEDSL(pipe);
5969 temp = intel_de_read(dev_priv, dslreg);
5971 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) {
5972 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5))
5973 drm_err(&dev_priv->drm,
5974 "mode set failed: pipe %c stuck\n",
5980 * The hardware phase 0.0 refers to the center of the pixel.
5981 * We want to start from the top/left edge which is phase
5982 * -0.5. That matches how the hardware calculates the scaling
5983 * factors (from top-left of the first pixel to bottom-right
5984 * of the last pixel, as opposed to the pixel centers).
5986 * For 4:2:0 subsampled chroma planes we obviously have to
5987 * adjust that so that the chroma sample position lands in
5990 * Note that for packed YCbCr 4:2:2 formats there is no way to
5991 * control chroma siting. The hardware simply replicates the
5992 * chroma samples for both of the luma samples, and thus we don't
5993 * actually get the expected MPEG2 chroma siting convention :(
5994 * The same behaviour is observed on pre-SKL platforms as well.
5996 * Theory behind the formula (note that we ignore sub-pixel
5997 * source coordinates):
5998 * s = source sample position
5999 * d = destination sample position
6004 * | | 1.5 (initial phase)
6012 * | -0.375 (initial phase)
6019 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
6021 int phase = -0x8000;
6025 phase += (sub - 1) * 0x8000 / sub;
6027 phase += scale / (2 * sub);
6030 * Hardware initial phase limited to [-0.5:1.5].
6031 * Since the max hardware scale factor is 3.0, we
6032 * should never actually excdeed 1.0 here.
6034 WARN_ON(phase < -0x8000 || phase > 0x18000);
6037 phase = 0x10000 + phase;
6039 trip = PS_PHASE_TRIP;
6041 return ((phase >> 2) & PS_PHASE_MASK) | trip;
6044 #define SKL_MIN_SRC_W 8
6045 #define SKL_MAX_SRC_W 4096
6046 #define SKL_MIN_SRC_H 8
6047 #define SKL_MAX_SRC_H 4096
6048 #define SKL_MIN_DST_W 8
6049 #define SKL_MAX_DST_W 4096
6050 #define SKL_MIN_DST_H 8
6051 #define SKL_MAX_DST_H 4096
6052 #define ICL_MAX_SRC_W 5120
6053 #define ICL_MAX_SRC_H 4096
6054 #define ICL_MAX_DST_W 5120
6055 #define ICL_MAX_DST_H 4096
6056 #define SKL_MIN_YUV_420_SRC_W 16
6057 #define SKL_MIN_YUV_420_SRC_H 16
6060 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
6061 unsigned int scaler_user, int *scaler_id,
6062 int src_w, int src_h, int dst_w, int dst_h,
6063 const struct drm_format_info *format,
6064 u64 modifier, bool need_scaler)
6066 struct intel_crtc_scaler_state *scaler_state =
6067 &crtc_state->scaler_state;
6068 struct intel_crtc *intel_crtc =
6069 to_intel_crtc(crtc_state->uapi.crtc);
6070 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6071 const struct drm_display_mode *adjusted_mode =
6072 &crtc_state->hw.adjusted_mode;
6075 * Src coordinates are already rotated by 270 degrees for
6076 * the 90/270 degree plane rotation cases (to match the
6077 * GTT mapping), hence no need to account for rotation here.
6079 if (src_w != dst_w || src_h != dst_h)
6083 * Scaling/fitting not supported in IF-ID mode in GEN9+
6084 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
6085 * Once NV12 is enabled, handle it here while allocating scaler
6088 if (INTEL_GEN(dev_priv) >= 9 && crtc_state->hw.enable &&
6089 need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6090 drm_dbg_kms(&dev_priv->drm,
6091 "Pipe/Plane scaling not supported with IF-ID mode\n");
6096 * if plane is being disabled or scaler is no more required or force detach
6097 * - free scaler binded to this plane/crtc
6098 * - in order to do this, update crtc->scaler_usage
6100 * Here scaler state in crtc_state is set free so that
6101 * scaler can be assigned to other user. Actual register
6102 * update to free the scaler is done in plane/panel-fit programming.
6103 * For this purpose crtc/plane_state->scaler_id isn't reset here.
6105 if (force_detach || !need_scaler) {
6106 if (*scaler_id >= 0) {
6107 scaler_state->scaler_users &= ~(1 << scaler_user);
6108 scaler_state->scalers[*scaler_id].in_use = 0;
6110 drm_dbg_kms(&dev_priv->drm,
6111 "scaler_user index %u.%u: "
6112 "Staged freeing scaler id %d scaler_users = 0x%x\n",
6113 intel_crtc->pipe, scaler_user, *scaler_id,
6114 scaler_state->scaler_users);
6120 if (format && intel_format_info_is_yuv_semiplanar(format, modifier) &&
6121 (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
6122 drm_dbg_kms(&dev_priv->drm,
6123 "Planar YUV: src dimensions not met\n");
6128 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
6129 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
6130 (INTEL_GEN(dev_priv) >= 11 &&
6131 (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
6132 dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
6133 (INTEL_GEN(dev_priv) < 11 &&
6134 (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
6135 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
6136 drm_dbg_kms(&dev_priv->drm,
6137 "scaler_user index %u.%u: src %ux%u dst %ux%u "
6138 "size is out of scaler range\n",
6139 intel_crtc->pipe, scaler_user, src_w, src_h,
6144 /* mark this plane as a scaler user in crtc_state */
6145 scaler_state->scaler_users |= (1 << scaler_user);
6146 drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: "
6147 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
6148 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
6149 scaler_state->scaler_users);
6154 static int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
6156 const struct drm_display_mode *adjusted_mode =
6157 &crtc_state->hw.adjusted_mode;
6160 if (crtc_state->pch_pfit.enabled) {
6161 width = drm_rect_width(&crtc_state->pch_pfit.dst);
6162 height = drm_rect_height(&crtc_state->pch_pfit.dst);
6164 width = adjusted_mode->crtc_hdisplay;
6165 height = adjusted_mode->crtc_vdisplay;
6168 return skl_update_scaler(crtc_state, !crtc_state->hw.active,
6170 &crtc_state->scaler_state.scaler_id,
6171 crtc_state->pipe_src_w, crtc_state->pipe_src_h,
6172 width, height, NULL, 0,
6173 crtc_state->pch_pfit.enabled);
6177 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
6178 * @crtc_state: crtc's scaler state
6179 * @plane_state: atomic plane state to update
6182 * 0 - scaler_usage updated successfully
6183 * error - requested scaling cannot be supported or other error condition
6185 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
6186 struct intel_plane_state *plane_state)
6188 struct intel_plane *intel_plane =
6189 to_intel_plane(plane_state->uapi.plane);
6190 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
6191 struct drm_framebuffer *fb = plane_state->hw.fb;
6193 bool force_detach = !fb || !plane_state->uapi.visible;
6194 bool need_scaler = false;
6196 /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
6197 if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
6198 fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
6201 ret = skl_update_scaler(crtc_state, force_detach,
6202 drm_plane_index(&intel_plane->base),
6203 &plane_state->scaler_id,
6204 drm_rect_width(&plane_state->uapi.src) >> 16,
6205 drm_rect_height(&plane_state->uapi.src) >> 16,
6206 drm_rect_width(&plane_state->uapi.dst),
6207 drm_rect_height(&plane_state->uapi.dst),
6208 fb ? fb->format : NULL,
6209 fb ? fb->modifier : 0,
6212 if (ret || plane_state->scaler_id < 0)
6215 /* check colorkey */
6216 if (plane_state->ckey.flags) {
6217 drm_dbg_kms(&dev_priv->drm,
6218 "[PLANE:%d:%s] scaling with color key not allowed",
6219 intel_plane->base.base.id,
6220 intel_plane->base.name);
6224 /* Check src format */
6225 switch (fb->format->format) {
6226 case DRM_FORMAT_RGB565:
6227 case DRM_FORMAT_XBGR8888:
6228 case DRM_FORMAT_XRGB8888:
6229 case DRM_FORMAT_ABGR8888:
6230 case DRM_FORMAT_ARGB8888:
6231 case DRM_FORMAT_XRGB2101010:
6232 case DRM_FORMAT_XBGR2101010:
6233 case DRM_FORMAT_ARGB2101010:
6234 case DRM_FORMAT_ABGR2101010:
6235 case DRM_FORMAT_YUYV:
6236 case DRM_FORMAT_YVYU:
6237 case DRM_FORMAT_UYVY:
6238 case DRM_FORMAT_VYUY:
6239 case DRM_FORMAT_NV12:
6240 case DRM_FORMAT_XYUV8888:
6241 case DRM_FORMAT_P010:
6242 case DRM_FORMAT_P012:
6243 case DRM_FORMAT_P016:
6244 case DRM_FORMAT_Y210:
6245 case DRM_FORMAT_Y212:
6246 case DRM_FORMAT_Y216:
6247 case DRM_FORMAT_XVYU2101010:
6248 case DRM_FORMAT_XVYU12_16161616:
6249 case DRM_FORMAT_XVYU16161616:
6251 case DRM_FORMAT_XBGR16161616F:
6252 case DRM_FORMAT_ABGR16161616F:
6253 case DRM_FORMAT_XRGB16161616F:
6254 case DRM_FORMAT_ARGB16161616F:
6255 if (INTEL_GEN(dev_priv) >= 11)
6259 drm_dbg_kms(&dev_priv->drm,
6260 "[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
6261 intel_plane->base.base.id, intel_plane->base.name,
6262 fb->base.id, fb->format->format);
6269 void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state)
6271 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
6274 for (i = 0; i < crtc->num_scalers; i++)
6275 skl_detach_scaler(crtc, i);
6278 static void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
6280 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6281 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6282 const struct intel_crtc_scaler_state *scaler_state =
6283 &crtc_state->scaler_state;
6284 struct drm_rect src = {
6285 .x2 = crtc_state->pipe_src_w << 16,
6286 .y2 = crtc_state->pipe_src_h << 16,
6288 const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
6289 u16 uv_rgb_hphase, uv_rgb_vphase;
6290 enum pipe pipe = crtc->pipe;
6291 int width = drm_rect_width(dst);
6292 int height = drm_rect_height(dst);
6296 unsigned long irqflags;
6299 if (!crtc_state->pch_pfit.enabled)
6302 if (drm_WARN_ON(&dev_priv->drm,
6303 crtc_state->scaler_state.scaler_id < 0))
6306 hscale = drm_rect_calc_hscale(&src, dst, 0, INT_MAX);
6307 vscale = drm_rect_calc_vscale(&src, dst, 0, INT_MAX);
6309 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
6310 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
6312 id = scaler_state->scaler_id;
6314 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
6316 intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
6317 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
6318 intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
6319 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
6320 intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
6321 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
6322 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
6324 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
6325 width << 16 | height);
6327 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
6330 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
6332 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6333 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6334 const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
6335 enum pipe pipe = crtc->pipe;
6336 int width = drm_rect_width(dst);
6337 int height = drm_rect_height(dst);
6341 if (!crtc_state->pch_pfit.enabled)
6344 /* Force use of hard-coded filter coefficients
6345 * as some pre-programmed values are broken,
6348 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
6349 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
6350 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
6352 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
6354 intel_de_write(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
6355 intel_de_write(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
6358 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
6360 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6361 struct drm_device *dev = crtc->base.dev;
6362 struct drm_i915_private *dev_priv = to_i915(dev);
6364 if (!crtc_state->ips_enabled)
6368 * We can only enable IPS after we enable a plane and wait for a vblank
6369 * This function is called from post_plane_update, which is run after
6372 drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
6374 if (IS_BROADWELL(dev_priv)) {
6375 drm_WARN_ON(dev, sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
6376 IPS_ENABLE | IPS_PCODE_CONTROL));
6377 /* Quoting Art Runyan: "its not safe to expect any particular
6378 * value in IPS_CTL bit 31 after enabling IPS through the
6379 * mailbox." Moreover, the mailbox may return a bogus state,
6380 * so we need to just enable it and continue on.
6383 intel_de_write(dev_priv, IPS_CTL, IPS_ENABLE);
6384 /* The bit only becomes 1 in the next vblank, so this wait here
6385 * is essentially intel_wait_for_vblank. If we don't have this
6386 * and don't wait for vblanks until the end of crtc_enable, then
6387 * the HW state readout code will complain that the expected
6388 * IPS_CTL value is not the one we read. */
6389 if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50))
6390 drm_err(&dev_priv->drm,
6391 "Timed out waiting for IPS enable\n");
6395 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
6397 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6398 struct drm_device *dev = crtc->base.dev;
6399 struct drm_i915_private *dev_priv = to_i915(dev);
6401 if (!crtc_state->ips_enabled)
6404 if (IS_BROADWELL(dev_priv)) {
6406 sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
6408 * Wait for PCODE to finish disabling IPS. The BSpec specified
6409 * 42ms timeout value leads to occasional timeouts so use 100ms
6412 if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100))
6413 drm_err(&dev_priv->drm,
6414 "Timed out waiting for IPS disable\n");
6416 intel_de_write(dev_priv, IPS_CTL, 0);
6417 intel_de_posting_read(dev_priv, IPS_CTL);
6420 /* We need to wait for a vblank before we can disable the plane. */
6421 intel_wait_for_vblank(dev_priv, crtc->pipe);
6424 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
6426 if (intel_crtc->overlay)
6427 (void) intel_overlay_switch_off(intel_crtc->overlay);
6429 /* Let userspace switch the overlay on again. In most cases userspace
6430 * has to recompute where to put it anyway.
6434 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
6435 const struct intel_crtc_state *new_crtc_state)
6437 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6438 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6440 if (!old_crtc_state->ips_enabled)
6443 if (needs_modeset(new_crtc_state))
6447 * Workaround : Do not read or write the pipe palette/gamma data while
6448 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6450 * Disable IPS before we program the LUT.
6452 if (IS_HASWELL(dev_priv) &&
6453 (new_crtc_state->uapi.color_mgmt_changed ||
6454 new_crtc_state->update_pipe) &&
6455 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
6458 return !new_crtc_state->ips_enabled;
6461 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
6462 const struct intel_crtc_state *new_crtc_state)
6464 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6465 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6467 if (!new_crtc_state->ips_enabled)
6470 if (needs_modeset(new_crtc_state))
6474 * Workaround : Do not read or write the pipe palette/gamma data while
6475 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6477 * Re-enable IPS after the LUT has been programmed.
6479 if (IS_HASWELL(dev_priv) &&
6480 (new_crtc_state->uapi.color_mgmt_changed ||
6481 new_crtc_state->update_pipe) &&
6482 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
6486 * We can't read out IPS on broadwell, assume the worst and
6487 * forcibly enable IPS on the first fastset.
6489 if (new_crtc_state->update_pipe && old_crtc_state->inherited)
6492 return !old_crtc_state->ips_enabled;
6495 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
6497 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
6499 if (!crtc_state->nv12_planes)
6502 /* WA Display #0827: Gen9:all */
6503 if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
6509 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
6511 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
6513 /* Wa_2006604312:icl,ehl */
6514 if (crtc_state->scaler_state.scaler_users > 0 && IS_GEN(dev_priv, 11))
6520 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
6521 const struct intel_crtc_state *new_crtc_state)
6523 return (!old_crtc_state->active_planes || needs_modeset(new_crtc_state)) &&
6524 new_crtc_state->active_planes;
6527 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
6528 const struct intel_crtc_state *new_crtc_state)
6530 return old_crtc_state->active_planes &&
6531 (!new_crtc_state->active_planes || needs_modeset(new_crtc_state));
6534 static void intel_post_plane_update(struct intel_atomic_state *state,
6535 struct intel_crtc *crtc)
6537 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6538 const struct intel_crtc_state *old_crtc_state =
6539 intel_atomic_get_old_crtc_state(state, crtc);
6540 const struct intel_crtc_state *new_crtc_state =
6541 intel_atomic_get_new_crtc_state(state, crtc);
6542 enum pipe pipe = crtc->pipe;
6544 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
6546 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
6547 intel_update_watermarks(crtc);
6549 if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
6550 hsw_enable_ips(new_crtc_state);
6552 intel_fbc_post_update(state, crtc);
6554 if (needs_nv12_wa(old_crtc_state) &&
6555 !needs_nv12_wa(new_crtc_state))
6556 skl_wa_827(dev_priv, pipe, false);
6558 if (needs_scalerclk_wa(old_crtc_state) &&
6559 !needs_scalerclk_wa(new_crtc_state))
6560 icl_wa_scalerclkgating(dev_priv, pipe, false);
6563 static void intel_pre_plane_update(struct intel_atomic_state *state,
6564 struct intel_crtc *crtc)
6566 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6567 const struct intel_crtc_state *old_crtc_state =
6568 intel_atomic_get_old_crtc_state(state, crtc);
6569 const struct intel_crtc_state *new_crtc_state =
6570 intel_atomic_get_new_crtc_state(state, crtc);
6571 enum pipe pipe = crtc->pipe;
6573 if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
6574 hsw_disable_ips(old_crtc_state);
6576 if (intel_fbc_pre_update(state, crtc))
6577 intel_wait_for_vblank(dev_priv, pipe);
6579 /* Display WA 827 */
6580 if (!needs_nv12_wa(old_crtc_state) &&
6581 needs_nv12_wa(new_crtc_state))
6582 skl_wa_827(dev_priv, pipe, true);
6584 /* Wa_2006604312:icl,ehl */
6585 if (!needs_scalerclk_wa(old_crtc_state) &&
6586 needs_scalerclk_wa(new_crtc_state))
6587 icl_wa_scalerclkgating(dev_priv, pipe, true);
6590 * Vblank time updates from the shadow to live plane control register
6591 * are blocked if the memory self-refresh mode is active at that
6592 * moment. So to make sure the plane gets truly disabled, disable
6593 * first the self-refresh mode. The self-refresh enable bit in turn
6594 * will be checked/applied by the HW only at the next frame start
6595 * event which is after the vblank start event, so we need to have a
6596 * wait-for-vblank between disabling the plane and the pipe.
6598 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
6599 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
6600 intel_wait_for_vblank(dev_priv, pipe);
6603 * IVB workaround: must disable low power watermarks for at least
6604 * one frame before enabling scaling. LP watermarks can be re-enabled
6605 * when scaling is disabled.
6607 * WaCxSRDisabledForSpriteScaling:ivb
6609 if (old_crtc_state->hw.active &&
6610 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
6611 intel_wait_for_vblank(dev_priv, pipe);
6614 * If we're doing a modeset we don't need to do any
6615 * pre-vblank watermark programming here.
6617 if (!needs_modeset(new_crtc_state)) {
6619 * For platforms that support atomic watermarks, program the
6620 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
6621 * will be the intermediate values that are safe for both pre- and
6622 * post- vblank; when vblank happens, the 'active' values will be set
6623 * to the final 'target' values and we'll do this again to get the
6624 * optimal watermarks. For gen9+ platforms, the values we program here
6625 * will be the final target values which will get automatically latched
6626 * at vblank time; no further programming will be necessary.
6628 * If a platform hasn't been transitioned to atomic watermarks yet,
6629 * we'll continue to update watermarks the old way, if flags tell
6632 if (dev_priv->display.initial_watermarks)
6633 dev_priv->display.initial_watermarks(state, crtc);
6634 else if (new_crtc_state->update_wm_pre)
6635 intel_update_watermarks(crtc);
6639 * Gen2 reports pipe underruns whenever all planes are disabled.
6640 * So disable underrun reporting before all the planes get disabled.
6642 * We do this after .initial_watermarks() so that we have a
6643 * chance of catching underruns with the intermediate watermarks
6644 * vs. the old plane configuration.
6646 if (IS_GEN(dev_priv, 2) && planes_disabling(old_crtc_state, new_crtc_state))
6647 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6650 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
6651 struct intel_crtc *crtc)
6653 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6654 const struct intel_crtc_state *new_crtc_state =
6655 intel_atomic_get_new_crtc_state(state, crtc);
6656 unsigned int update_mask = new_crtc_state->update_planes;
6657 const struct intel_plane_state *old_plane_state;
6658 struct intel_plane *plane;
6659 unsigned fb_bits = 0;
6662 intel_crtc_dpms_overlay_disable(crtc);
6664 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
6665 if (crtc->pipe != plane->pipe ||
6666 !(update_mask & BIT(plane->id)))
6669 intel_disable_plane(plane, new_crtc_state);
6671 if (old_plane_state->uapi.visible)
6672 fb_bits |= plane->frontbuffer_bit;
6675 intel_frontbuffer_flip(dev_priv, fb_bits);
6679 * intel_connector_primary_encoder - get the primary encoder for a connector
6680 * @connector: connector for which to return the encoder
6682 * Returns the primary encoder for a connector. There is a 1:1 mapping from
6683 * all connectors to their encoder, except for DP-MST connectors which have
6684 * both a virtual and a primary encoder. These DP-MST primary encoders can be
6685 * pointed to by as many DP-MST connectors as there are pipes.
6687 static struct intel_encoder *
6688 intel_connector_primary_encoder(struct intel_connector *connector)
6690 struct intel_encoder *encoder;
6692 if (connector->mst_port)
6693 return &dp_to_dig_port(connector->mst_port)->base;
6695 encoder = intel_attached_encoder(connector);
6696 drm_WARN_ON(connector->base.dev, !encoder);
6701 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
6703 struct drm_connector_state *new_conn_state;
6704 struct drm_connector *connector;
6707 for_each_new_connector_in_state(&state->base, connector, new_conn_state,
6709 struct intel_connector *intel_connector;
6710 struct intel_encoder *encoder;
6711 struct intel_crtc *crtc;
6713 if (!intel_connector_needs_modeset(state, connector))
6716 intel_connector = to_intel_connector(connector);
6717 encoder = intel_connector_primary_encoder(intel_connector);
6718 if (!encoder->update_prepare)
6721 crtc = new_conn_state->crtc ?
6722 to_intel_crtc(new_conn_state->crtc) : NULL;
6723 encoder->update_prepare(state, encoder, crtc);
6727 static void intel_encoders_update_complete(struct intel_atomic_state *state)
6729 struct drm_connector_state *new_conn_state;
6730 struct drm_connector *connector;
6733 for_each_new_connector_in_state(&state->base, connector, new_conn_state,
6735 struct intel_connector *intel_connector;
6736 struct intel_encoder *encoder;
6737 struct intel_crtc *crtc;
6739 if (!intel_connector_needs_modeset(state, connector))
6742 intel_connector = to_intel_connector(connector);
6743 encoder = intel_connector_primary_encoder(intel_connector);
6744 if (!encoder->update_complete)
6747 crtc = new_conn_state->crtc ?
6748 to_intel_crtc(new_conn_state->crtc) : NULL;
6749 encoder->update_complete(state, encoder, crtc);
6753 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
6754 struct intel_crtc *crtc)
6756 const struct intel_crtc_state *crtc_state =
6757 intel_atomic_get_new_crtc_state(state, crtc);
6758 const struct drm_connector_state *conn_state;
6759 struct drm_connector *conn;
6762 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6763 struct intel_encoder *encoder =
6764 to_intel_encoder(conn_state->best_encoder);
6766 if (conn_state->crtc != &crtc->base)
6769 if (encoder->pre_pll_enable)
6770 encoder->pre_pll_enable(state, encoder,
6771 crtc_state, conn_state);
6775 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
6776 struct intel_crtc *crtc)
6778 const struct intel_crtc_state *crtc_state =
6779 intel_atomic_get_new_crtc_state(state, crtc);
6780 const struct drm_connector_state *conn_state;
6781 struct drm_connector *conn;
6784 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6785 struct intel_encoder *encoder =
6786 to_intel_encoder(conn_state->best_encoder);
6788 if (conn_state->crtc != &crtc->base)
6791 if (encoder->pre_enable)
6792 encoder->pre_enable(state, encoder,
6793 crtc_state, conn_state);
6797 static void intel_encoders_enable(struct intel_atomic_state *state,
6798 struct intel_crtc *crtc)
6800 const struct intel_crtc_state *crtc_state =
6801 intel_atomic_get_new_crtc_state(state, crtc);
6802 const struct drm_connector_state *conn_state;
6803 struct drm_connector *conn;
6806 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6807 struct intel_encoder *encoder =
6808 to_intel_encoder(conn_state->best_encoder);
6810 if (conn_state->crtc != &crtc->base)
6813 if (encoder->enable)
6814 encoder->enable(state, encoder,
6815 crtc_state, conn_state);
6816 intel_opregion_notify_encoder(encoder, true);
6820 static void intel_encoders_disable(struct intel_atomic_state *state,
6821 struct intel_crtc *crtc)
6823 const struct intel_crtc_state *old_crtc_state =
6824 intel_atomic_get_old_crtc_state(state, crtc);
6825 const struct drm_connector_state *old_conn_state;
6826 struct drm_connector *conn;
6829 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6830 struct intel_encoder *encoder =
6831 to_intel_encoder(old_conn_state->best_encoder);
6833 if (old_conn_state->crtc != &crtc->base)
6836 intel_opregion_notify_encoder(encoder, false);
6837 if (encoder->disable)
6838 encoder->disable(state, encoder,
6839 old_crtc_state, old_conn_state);
6843 static void intel_encoders_post_disable(struct intel_atomic_state *state,
6844 struct intel_crtc *crtc)
6846 const struct intel_crtc_state *old_crtc_state =
6847 intel_atomic_get_old_crtc_state(state, crtc);
6848 const struct drm_connector_state *old_conn_state;
6849 struct drm_connector *conn;
6852 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6853 struct intel_encoder *encoder =
6854 to_intel_encoder(old_conn_state->best_encoder);
6856 if (old_conn_state->crtc != &crtc->base)
6859 if (encoder->post_disable)
6860 encoder->post_disable(state, encoder,
6861 old_crtc_state, old_conn_state);
6865 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
6866 struct intel_crtc *crtc)
6868 const struct intel_crtc_state *old_crtc_state =
6869 intel_atomic_get_old_crtc_state(state, crtc);
6870 const struct drm_connector_state *old_conn_state;
6871 struct drm_connector *conn;
6874 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6875 struct intel_encoder *encoder =
6876 to_intel_encoder(old_conn_state->best_encoder);
6878 if (old_conn_state->crtc != &crtc->base)
6881 if (encoder->post_pll_disable)
6882 encoder->post_pll_disable(state, encoder,
6883 old_crtc_state, old_conn_state);
6887 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
6888 struct intel_crtc *crtc)
6890 const struct intel_crtc_state *crtc_state =
6891 intel_atomic_get_new_crtc_state(state, crtc);
6892 const struct drm_connector_state *conn_state;
6893 struct drm_connector *conn;
6896 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6897 struct intel_encoder *encoder =
6898 to_intel_encoder(conn_state->best_encoder);
6900 if (conn_state->crtc != &crtc->base)
6903 if (encoder->update_pipe)
6904 encoder->update_pipe(state, encoder,
6905 crtc_state, conn_state);
6909 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
6911 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6912 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
6914 plane->disable_plane(plane, crtc_state);
6917 static void ilk_crtc_enable(struct intel_atomic_state *state,
6918 struct intel_crtc *crtc)
6920 const struct intel_crtc_state *new_crtc_state =
6921 intel_atomic_get_new_crtc_state(state, crtc);
6922 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6923 enum pipe pipe = crtc->pipe;
6925 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
6929 * Sometimes spurious CPU pipe underruns happen during FDI
6930 * training, at least with VGA+HDMI cloning. Suppress them.
6932 * On ILK we get an occasional spurious CPU pipe underruns
6933 * between eDP port A enable and vdd enable. Also PCH port
6934 * enable seems to result in the occasional CPU pipe underrun.
6936 * Spurious PCH underruns also occur during PCH enabling.
6938 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6939 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
6941 if (new_crtc_state->has_pch_encoder)
6942 intel_prepare_shared_dpll(new_crtc_state);
6944 if (intel_crtc_has_dp_encoder(new_crtc_state))
6945 intel_dp_set_m_n(new_crtc_state, M1_N1);
6947 intel_set_pipe_timings(new_crtc_state);
6948 intel_set_pipe_src_size(new_crtc_state);
6950 if (new_crtc_state->has_pch_encoder)
6951 intel_cpu_transcoder_set_m_n(new_crtc_state,
6952 &new_crtc_state->fdi_m_n, NULL);
6954 ilk_set_pipeconf(new_crtc_state);
6956 crtc->active = true;
6958 intel_encoders_pre_enable(state, crtc);
6960 if (new_crtc_state->has_pch_encoder) {
6961 /* Note: FDI PLL enabling _must_ be done before we enable the
6962 * cpu pipes, hence this is separate from all the other fdi/pch
6964 ilk_fdi_pll_enable(new_crtc_state);
6966 assert_fdi_tx_disabled(dev_priv, pipe);
6967 assert_fdi_rx_disabled(dev_priv, pipe);
6970 ilk_pfit_enable(new_crtc_state);
6973 * On ILK+ LUT must be loaded before the pipe is running but with
6976 intel_color_load_luts(new_crtc_state);
6977 intel_color_commit(new_crtc_state);
6978 /* update DSPCNTR to configure gamma for pipe bottom color */
6979 intel_disable_primary_plane(new_crtc_state);
6981 if (dev_priv->display.initial_watermarks)
6982 dev_priv->display.initial_watermarks(state, crtc);
6983 intel_enable_pipe(new_crtc_state);
6985 if (new_crtc_state->has_pch_encoder)
6986 ilk_pch_enable(state, new_crtc_state);
6988 intel_crtc_vblank_on(new_crtc_state);
6990 intel_encoders_enable(state, crtc);
6992 if (HAS_PCH_CPT(dev_priv))
6993 cpt_verify_modeset(dev_priv, pipe);
6996 * Must wait for vblank to avoid spurious PCH FIFO underruns.
6997 * And a second vblank wait is needed at least on ILK with
6998 * some interlaced HDMI modes. Let's do the double wait always
6999 * in case there are more corner cases we don't know about.
7001 if (new_crtc_state->has_pch_encoder) {
7002 intel_wait_for_vblank(dev_priv, pipe);
7003 intel_wait_for_vblank(dev_priv, pipe);
7005 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7006 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
7009 /* IPS only exists on ULT machines and is tied to pipe A. */
7010 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
7012 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
7015 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
7016 enum pipe pipe, bool apply)
7018 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe));
7019 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
7026 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
7029 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
7031 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7032 enum pipe pipe = crtc->pipe;
7035 val = MBUS_DBOX_A_CREDIT(2);
7037 if (INTEL_GEN(dev_priv) >= 12) {
7038 val |= MBUS_DBOX_BW_CREDIT(2);
7039 val |= MBUS_DBOX_B_CREDIT(12);
7041 val |= MBUS_DBOX_BW_CREDIT(1);
7042 val |= MBUS_DBOX_B_CREDIT(8);
7045 intel_de_write(dev_priv, PIPE_MBUS_DBOX_CTL(pipe), val);
7048 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
7050 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7051 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7053 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),
7054 HSW_LINETIME(crtc_state->linetime) |
7055 HSW_IPS_LINETIME(crtc_state->ips_linetime));
7058 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
7060 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7061 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7062 i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
7065 val = intel_de_read(dev_priv, reg);
7066 val &= ~HSW_FRAME_START_DELAY_MASK;
7067 val |= HSW_FRAME_START_DELAY(0);
7068 intel_de_write(dev_priv, reg, val);
7071 static void hsw_crtc_enable(struct intel_atomic_state *state,
7072 struct intel_crtc *crtc)
7074 const struct intel_crtc_state *new_crtc_state =
7075 intel_atomic_get_new_crtc_state(state, crtc);
7076 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7077 enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
7078 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
7079 bool psl_clkgate_wa;
7081 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7084 intel_encoders_pre_pll_enable(state, crtc);
7086 if (new_crtc_state->shared_dpll)
7087 intel_enable_shared_dpll(new_crtc_state);
7089 intel_encoders_pre_enable(state, crtc);
7091 if (!transcoder_is_dsi(cpu_transcoder))
7092 intel_set_pipe_timings(new_crtc_state);
7094 intel_set_pipe_src_size(new_crtc_state);
7096 if (cpu_transcoder != TRANSCODER_EDP &&
7097 !transcoder_is_dsi(cpu_transcoder))
7098 intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
7099 new_crtc_state->pixel_multiplier - 1);
7101 if (new_crtc_state->has_pch_encoder)
7102 intel_cpu_transcoder_set_m_n(new_crtc_state,
7103 &new_crtc_state->fdi_m_n, NULL);
7105 if (!transcoder_is_dsi(cpu_transcoder)) {
7106 hsw_set_frame_start_delay(new_crtc_state);
7107 hsw_set_pipeconf(new_crtc_state);
7110 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
7111 bdw_set_pipemisc(new_crtc_state);
7113 crtc->active = true;
7115 /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
7116 psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
7117 new_crtc_state->pch_pfit.enabled;
7119 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
7121 if (INTEL_GEN(dev_priv) >= 9)
7122 skl_pfit_enable(new_crtc_state);
7124 ilk_pfit_enable(new_crtc_state);
7127 * On ILK+ LUT must be loaded before the pipe is running but with
7130 intel_color_load_luts(new_crtc_state);
7131 intel_color_commit(new_crtc_state);
7132 /* update DSPCNTR to configure gamma/csc for pipe bottom color */
7133 if (INTEL_GEN(dev_priv) < 9)
7134 intel_disable_primary_plane(new_crtc_state);
7136 hsw_set_linetime_wm(new_crtc_state);
7138 if (INTEL_GEN(dev_priv) >= 11)
7139 icl_set_pipe_chicken(crtc);
7141 if (dev_priv->display.initial_watermarks)
7142 dev_priv->display.initial_watermarks(state, crtc);
7144 if (INTEL_GEN(dev_priv) >= 11)
7145 icl_pipe_mbus_enable(crtc);
7147 intel_encoders_enable(state, crtc);
7149 if (psl_clkgate_wa) {
7150 intel_wait_for_vblank(dev_priv, pipe);
7151 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
7154 /* If we change the relative order between pipe/planes enabling, we need
7155 * to change the workaround. */
7156 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
7157 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
7158 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
7159 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
7163 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
7165 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
7166 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7167 enum pipe pipe = crtc->pipe;
7169 /* To avoid upsetting the power well on haswell only disable the pfit if
7170 * it's in use. The hw state code will make sure we get this right. */
7171 if (!old_crtc_state->pch_pfit.enabled)
7174 intel_de_write(dev_priv, PF_CTL(pipe), 0);
7175 intel_de_write(dev_priv, PF_WIN_POS(pipe), 0);
7176 intel_de_write(dev_priv, PF_WIN_SZ(pipe), 0);
7179 static void ilk_crtc_disable(struct intel_atomic_state *state,
7180 struct intel_crtc *crtc)
7182 const struct intel_crtc_state *old_crtc_state =
7183 intel_atomic_get_old_crtc_state(state, crtc);
7184 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7185 enum pipe pipe = crtc->pipe;
7188 * Sometimes spurious CPU pipe underruns happen when the
7189 * pipe is already disabled, but FDI RX/TX is still enabled.
7190 * Happens at least with VGA+HDMI cloning. Suppress them.
7192 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7193 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
7195 intel_encoders_disable(state, crtc);
7197 intel_crtc_vblank_off(old_crtc_state);
7199 intel_disable_pipe(old_crtc_state);
7201 ilk_pfit_disable(old_crtc_state);
7203 if (old_crtc_state->has_pch_encoder)
7204 ilk_fdi_disable(crtc);
7206 intel_encoders_post_disable(state, crtc);
7208 if (old_crtc_state->has_pch_encoder) {
7209 ilk_disable_pch_transcoder(dev_priv, pipe);
7211 if (HAS_PCH_CPT(dev_priv)) {
7215 /* disable TRANS_DP_CTL */
7216 reg = TRANS_DP_CTL(pipe);
7217 temp = intel_de_read(dev_priv, reg);
7218 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
7219 TRANS_DP_PORT_SEL_MASK);
7220 temp |= TRANS_DP_PORT_SEL_NONE;
7221 intel_de_write(dev_priv, reg, temp);
7223 /* disable DPLL_SEL */
7224 temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
7225 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
7226 intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
7229 ilk_fdi_pll_disable(crtc);
7232 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7233 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
7236 static void hsw_crtc_disable(struct intel_atomic_state *state,
7237 struct intel_crtc *crtc)
7240 * FIXME collapse everything to one hook.
7241 * Need care with mst->ddi interactions.
7243 intel_encoders_disable(state, crtc);
7244 intel_encoders_post_disable(state, crtc);
7247 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
7249 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7250 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7252 if (!crtc_state->gmch_pfit.control)
7256 * The panel fitter should only be adjusted whilst the pipe is disabled,
7257 * according to register description and PRM.
7259 drm_WARN_ON(&dev_priv->drm,
7260 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
7261 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
7263 intel_de_write(dev_priv, PFIT_PGM_RATIOS,
7264 crtc_state->gmch_pfit.pgm_ratios);
7265 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
7267 /* Border color in case we don't scale up to the full screen. Black by
7268 * default, change to something else for debugging. */
7269 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
7272 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
7274 if (phy == PHY_NONE)
7276 else if (IS_ROCKETLAKE(dev_priv))
7277 return phy <= PHY_D;
7278 else if (IS_ELKHARTLAKE(dev_priv))
7279 return phy <= PHY_C;
7280 else if (INTEL_GEN(dev_priv) >= 11)
7281 return phy <= PHY_B;
7286 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
7288 if (IS_ROCKETLAKE(dev_priv))
7290 else if (INTEL_GEN(dev_priv) >= 12)
7291 return phy >= PHY_D && phy <= PHY_I;
7292 else if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
7293 return phy >= PHY_C && phy <= PHY_F;
7298 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
7300 if (IS_ROCKETLAKE(i915) && port >= PORT_D)
7301 return (enum phy)port - 1;
7302 else if (IS_ELKHARTLAKE(i915) && port == PORT_D)
7305 return (enum phy)port;
7308 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
7310 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
7311 return PORT_TC_NONE;
7313 if (INTEL_GEN(dev_priv) >= 12)
7314 return port - PORT_D;
7316 return port - PORT_C;
7319 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
7323 return POWER_DOMAIN_PORT_DDI_A_LANES;
7325 return POWER_DOMAIN_PORT_DDI_B_LANES;
7327 return POWER_DOMAIN_PORT_DDI_C_LANES;
7329 return POWER_DOMAIN_PORT_DDI_D_LANES;
7331 return POWER_DOMAIN_PORT_DDI_E_LANES;
7333 return POWER_DOMAIN_PORT_DDI_F_LANES;
7335 return POWER_DOMAIN_PORT_DDI_G_LANES;
7337 return POWER_DOMAIN_PORT_DDI_H_LANES;
7339 return POWER_DOMAIN_PORT_DDI_I_LANES;
7342 return POWER_DOMAIN_PORT_OTHER;
7346 enum intel_display_power_domain
7347 intel_aux_power_domain(struct intel_digital_port *dig_port)
7349 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
7350 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
7352 if (intel_phy_is_tc(dev_priv, phy) &&
7353 dig_port->tc_mode == TC_PORT_TBT_ALT) {
7354 switch (dig_port->aux_ch) {
7356 return POWER_DOMAIN_AUX_C_TBT;
7358 return POWER_DOMAIN_AUX_D_TBT;
7360 return POWER_DOMAIN_AUX_E_TBT;
7362 return POWER_DOMAIN_AUX_F_TBT;
7364 return POWER_DOMAIN_AUX_G_TBT;
7366 return POWER_DOMAIN_AUX_H_TBT;
7368 return POWER_DOMAIN_AUX_I_TBT;
7370 MISSING_CASE(dig_port->aux_ch);
7371 return POWER_DOMAIN_AUX_C_TBT;
7375 return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
7379 * Converts aux_ch to power_domain without caring about TBT ports for that use
7380 * intel_aux_power_domain()
7382 enum intel_display_power_domain
7383 intel_legacy_aux_to_power_domain(enum aux_ch aux_ch)
7387 return POWER_DOMAIN_AUX_A;
7389 return POWER_DOMAIN_AUX_B;
7391 return POWER_DOMAIN_AUX_C;
7393 return POWER_DOMAIN_AUX_D;
7395 return POWER_DOMAIN_AUX_E;
7397 return POWER_DOMAIN_AUX_F;
7399 return POWER_DOMAIN_AUX_G;
7401 return POWER_DOMAIN_AUX_H;
7403 return POWER_DOMAIN_AUX_I;
7405 MISSING_CASE(aux_ch);
7406 return POWER_DOMAIN_AUX_A;
7410 static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
7412 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7413 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7414 struct drm_encoder *encoder;
7415 enum pipe pipe = crtc->pipe;
7417 enum transcoder transcoder = crtc_state->cpu_transcoder;
7419 if (!crtc_state->hw.active)
7422 mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
7423 mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
7424 if (crtc_state->pch_pfit.enabled ||
7425 crtc_state->pch_pfit.force_thru)
7426 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
7428 drm_for_each_encoder_mask(encoder, &dev_priv->drm,
7429 crtc_state->uapi.encoder_mask) {
7430 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
7432 mask |= BIT_ULL(intel_encoder->power_domain);
7435 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
7436 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
7438 if (crtc_state->shared_dpll)
7439 mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
7445 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
7447 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7448 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7449 enum intel_display_power_domain domain;
7450 u64 domains, new_domains, old_domains;
7452 old_domains = crtc->enabled_power_domains;
7453 crtc->enabled_power_domains = new_domains =
7454 get_crtc_power_domains(crtc_state);
7456 domains = new_domains & ~old_domains;
7458 for_each_power_domain(domain, domains)
7459 intel_display_power_get(dev_priv, domain);
7461 return old_domains & ~new_domains;
7464 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
7467 enum intel_display_power_domain domain;
7469 for_each_power_domain(domain, domains)
7470 intel_display_power_put_unchecked(dev_priv, domain);
7473 static void valleyview_crtc_enable(struct intel_atomic_state *state,
7474 struct intel_crtc *crtc)
7476 const struct intel_crtc_state *new_crtc_state =
7477 intel_atomic_get_new_crtc_state(state, crtc);
7478 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7479 enum pipe pipe = crtc->pipe;
7481 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7484 if (intel_crtc_has_dp_encoder(new_crtc_state))
7485 intel_dp_set_m_n(new_crtc_state, M1_N1);
7487 intel_set_pipe_timings(new_crtc_state);
7488 intel_set_pipe_src_size(new_crtc_state);
7490 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
7491 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
7492 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
7495 i9xx_set_pipeconf(new_crtc_state);
7497 crtc->active = true;
7499 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7501 intel_encoders_pre_pll_enable(state, crtc);
7503 if (IS_CHERRYVIEW(dev_priv)) {
7504 chv_prepare_pll(crtc, new_crtc_state);
7505 chv_enable_pll(crtc, new_crtc_state);
7507 vlv_prepare_pll(crtc, new_crtc_state);
7508 vlv_enable_pll(crtc, new_crtc_state);
7511 intel_encoders_pre_enable(state, crtc);
7513 i9xx_pfit_enable(new_crtc_state);
7515 intel_color_load_luts(new_crtc_state);
7516 intel_color_commit(new_crtc_state);
7517 /* update DSPCNTR to configure gamma for pipe bottom color */
7518 intel_disable_primary_plane(new_crtc_state);
7520 dev_priv->display.initial_watermarks(state, crtc);
7521 intel_enable_pipe(new_crtc_state);
7523 intel_crtc_vblank_on(new_crtc_state);
7525 intel_encoders_enable(state, crtc);
7528 static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
7530 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7531 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7533 intel_de_write(dev_priv, FP0(crtc->pipe),
7534 crtc_state->dpll_hw_state.fp0);
7535 intel_de_write(dev_priv, FP1(crtc->pipe),
7536 crtc_state->dpll_hw_state.fp1);
7539 static void i9xx_crtc_enable(struct intel_atomic_state *state,
7540 struct intel_crtc *crtc)
7542 const struct intel_crtc_state *new_crtc_state =
7543 intel_atomic_get_new_crtc_state(state, crtc);
7544 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7545 enum pipe pipe = crtc->pipe;
7547 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7550 i9xx_set_pll_dividers(new_crtc_state);
7552 if (intel_crtc_has_dp_encoder(new_crtc_state))
7553 intel_dp_set_m_n(new_crtc_state, M1_N1);
7555 intel_set_pipe_timings(new_crtc_state);
7556 intel_set_pipe_src_size(new_crtc_state);
7558 i9xx_set_pipeconf(new_crtc_state);
7560 crtc->active = true;
7562 if (!IS_GEN(dev_priv, 2))
7563 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7565 intel_encoders_pre_enable(state, crtc);
7567 i9xx_enable_pll(crtc, new_crtc_state);
7569 i9xx_pfit_enable(new_crtc_state);
7571 intel_color_load_luts(new_crtc_state);
7572 intel_color_commit(new_crtc_state);
7573 /* update DSPCNTR to configure gamma for pipe bottom color */
7574 intel_disable_primary_plane(new_crtc_state);
7576 if (dev_priv->display.initial_watermarks)
7577 dev_priv->display.initial_watermarks(state, crtc);
7579 intel_update_watermarks(crtc);
7580 intel_enable_pipe(new_crtc_state);
7582 intel_crtc_vblank_on(new_crtc_state);
7584 intel_encoders_enable(state, crtc);
7586 /* prevents spurious underruns */
7587 if (IS_GEN(dev_priv, 2))
7588 intel_wait_for_vblank(dev_priv, pipe);
7591 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
7593 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
7594 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7596 if (!old_crtc_state->gmch_pfit.control)
7599 assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
7601 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
7602 intel_de_read(dev_priv, PFIT_CONTROL));
7603 intel_de_write(dev_priv, PFIT_CONTROL, 0);
7606 static void i9xx_crtc_disable(struct intel_atomic_state *state,
7607 struct intel_crtc *crtc)
7609 struct intel_crtc_state *old_crtc_state =
7610 intel_atomic_get_old_crtc_state(state, crtc);
7611 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7612 enum pipe pipe = crtc->pipe;
7615 * On gen2 planes are double buffered but the pipe isn't, so we must
7616 * wait for planes to fully turn off before disabling the pipe.
7618 if (IS_GEN(dev_priv, 2))
7619 intel_wait_for_vblank(dev_priv, pipe);
7621 intel_encoders_disable(state, crtc);
7623 intel_crtc_vblank_off(old_crtc_state);
7625 intel_disable_pipe(old_crtc_state);
7627 i9xx_pfit_disable(old_crtc_state);
7629 intel_encoders_post_disable(state, crtc);
7631 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
7632 if (IS_CHERRYVIEW(dev_priv))
7633 chv_disable_pll(dev_priv, pipe);
7634 else if (IS_VALLEYVIEW(dev_priv))
7635 vlv_disable_pll(dev_priv, pipe);
7637 i9xx_disable_pll(old_crtc_state);
7640 intel_encoders_post_pll_disable(state, crtc);
7642 if (!IS_GEN(dev_priv, 2))
7643 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7645 if (!dev_priv->display.initial_watermarks)
7646 intel_update_watermarks(crtc);
7648 /* clock the pipe down to 640x480@60 to potentially save power */
7649 if (IS_I830(dev_priv))
7650 i830_enable_pipe(dev_priv, pipe);
7653 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
7654 struct drm_modeset_acquire_ctx *ctx)
7656 struct intel_encoder *encoder;
7657 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7658 struct intel_bw_state *bw_state =
7659 to_intel_bw_state(dev_priv->bw_obj.state);
7660 struct intel_cdclk_state *cdclk_state =
7661 to_intel_cdclk_state(dev_priv->cdclk.obj.state);
7662 struct intel_dbuf_state *dbuf_state =
7663 to_intel_dbuf_state(dev_priv->dbuf.obj.state);
7664 struct intel_crtc_state *crtc_state =
7665 to_intel_crtc_state(crtc->base.state);
7666 enum intel_display_power_domain domain;
7667 struct intel_plane *plane;
7668 struct drm_atomic_state *state;
7669 struct intel_crtc_state *temp_crtc_state;
7670 enum pipe pipe = crtc->pipe;
7674 if (!crtc_state->hw.active)
7677 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
7678 const struct intel_plane_state *plane_state =
7679 to_intel_plane_state(plane->base.state);
7681 if (plane_state->uapi.visible)
7682 intel_plane_disable_noatomic(crtc, plane);
7685 state = drm_atomic_state_alloc(&dev_priv->drm);
7687 drm_dbg_kms(&dev_priv->drm,
7688 "failed to disable [CRTC:%d:%s], out of memory",
7689 crtc->base.base.id, crtc->base.name);
7693 state->acquire_ctx = ctx;
7695 /* Everything's already locked, -EDEADLK can't happen. */
7696 temp_crtc_state = intel_atomic_get_crtc_state(state, crtc);
7697 ret = drm_atomic_add_affected_connectors(state, &crtc->base);
7699 drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret);
7701 dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc);
7703 drm_atomic_state_put(state);
7705 drm_dbg_kms(&dev_priv->drm,
7706 "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
7707 crtc->base.base.id, crtc->base.name);
7709 crtc->active = false;
7710 crtc->base.enabled = false;
7712 drm_WARN_ON(&dev_priv->drm,
7713 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0);
7714 crtc_state->uapi.active = false;
7715 crtc_state->uapi.connector_mask = 0;
7716 crtc_state->uapi.encoder_mask = 0;
7717 intel_crtc_free_hw_state(crtc_state);
7718 memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));
7720 for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder)
7721 encoder->base.crtc = NULL;
7723 intel_fbc_disable(crtc);
7724 intel_update_watermarks(crtc);
7725 intel_disable_shared_dpll(crtc_state);
7727 domains = crtc->enabled_power_domains;
7728 for_each_power_domain(domain, domains)
7729 intel_display_power_put_unchecked(dev_priv, domain);
7730 crtc->enabled_power_domains = 0;
7732 dev_priv->active_pipes &= ~BIT(pipe);
7733 cdclk_state->min_cdclk[pipe] = 0;
7734 cdclk_state->min_voltage_level[pipe] = 0;
7735 cdclk_state->active_pipes &= ~BIT(pipe);
7737 dbuf_state->active_pipes &= ~BIT(pipe);
7739 bw_state->data_rate[pipe] = 0;
7740 bw_state->num_active_planes[pipe] = 0;
7744 * turn all crtc's off, but do not adjust state
7745 * This has to be paired with a call to intel_modeset_setup_hw_state.
7747 int intel_display_suspend(struct drm_device *dev)
7749 struct drm_i915_private *dev_priv = to_i915(dev);
7750 struct drm_atomic_state *state;
7753 state = drm_atomic_helper_suspend(dev);
7754 ret = PTR_ERR_OR_ZERO(state);
7756 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
7759 dev_priv->modeset_restore_state = state;
7763 void intel_encoder_destroy(struct drm_encoder *encoder)
7765 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
7767 drm_encoder_cleanup(encoder);
7768 kfree(intel_encoder);
7771 /* Cross check the actual hw state with our own modeset state tracking (and it's
7772 * internal consistency). */
7773 static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
7774 struct drm_connector_state *conn_state)
7776 struct intel_connector *connector = to_intel_connector(conn_state->connector);
7777 struct drm_i915_private *i915 = to_i915(connector->base.dev);
7779 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
7780 connector->base.base.id, connector->base.name);
7782 if (connector->get_hw_state(connector)) {
7783 struct intel_encoder *encoder = intel_attached_encoder(connector);
7785 I915_STATE_WARN(!crtc_state,
7786 "connector enabled without attached crtc\n");
7791 I915_STATE_WARN(!crtc_state->hw.active,
7792 "connector is active, but attached crtc isn't\n");
7794 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
7797 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
7798 "atomic encoder doesn't match attached encoder\n");
7800 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
7801 "attached encoder crtc differs from connector crtc\n");
7803 I915_STATE_WARN(crtc_state && crtc_state->hw.active,
7804 "attached crtc is active, but connector isn't\n");
7805 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
7806 "best encoder set without crtc!\n");
7810 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7812 if (crtc_state->hw.enable && crtc_state->has_pch_encoder)
7813 return crtc_state->fdi_lanes;
7818 static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7819 struct intel_crtc_state *pipe_config)
7821 struct drm_i915_private *dev_priv = to_i915(dev);
7822 struct drm_atomic_state *state = pipe_config->uapi.state;
7823 struct intel_crtc *other_crtc;
7824 struct intel_crtc_state *other_crtc_state;
7826 drm_dbg_kms(&dev_priv->drm,
7827 "checking fdi config on pipe %c, lanes %i\n",
7828 pipe_name(pipe), pipe_config->fdi_lanes);
7829 if (pipe_config->fdi_lanes > 4) {
7830 drm_dbg_kms(&dev_priv->drm,
7831 "invalid fdi lane config on pipe %c: %i lanes\n",
7832 pipe_name(pipe), pipe_config->fdi_lanes);
7836 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7837 if (pipe_config->fdi_lanes > 2) {
7838 drm_dbg_kms(&dev_priv->drm,
7839 "only 2 lanes on haswell, required: %i lanes\n",
7840 pipe_config->fdi_lanes);
7847 if (INTEL_NUM_PIPES(dev_priv) == 2)
7850 /* Ivybridge 3 pipe is really complicated */
7855 if (pipe_config->fdi_lanes <= 2)
7858 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
7860 intel_atomic_get_crtc_state(state, other_crtc);
7861 if (IS_ERR(other_crtc_state))
7862 return PTR_ERR(other_crtc_state);
7864 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7865 drm_dbg_kms(&dev_priv->drm,
7866 "invalid shared fdi lane config on pipe %c: %i lanes\n",
7867 pipe_name(pipe), pipe_config->fdi_lanes);
7872 if (pipe_config->fdi_lanes > 2) {
7873 drm_dbg_kms(&dev_priv->drm,
7874 "only 2 lanes on pipe %c: required %i lanes\n",
7875 pipe_name(pipe), pipe_config->fdi_lanes);
7879 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
7881 intel_atomic_get_crtc_state(state, other_crtc);
7882 if (IS_ERR(other_crtc_state))
7883 return PTR_ERR(other_crtc_state);
7885 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7886 drm_dbg_kms(&dev_priv->drm,
7887 "fdi link B uses too many lanes to enable link C\n");
7897 static int ilk_fdi_compute_config(struct intel_crtc *intel_crtc,
7898 struct intel_crtc_state *pipe_config)
7900 struct drm_device *dev = intel_crtc->base.dev;
7901 struct drm_i915_private *i915 = to_i915(dev);
7902 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
7903 int lane, link_bw, fdi_dotclock, ret;
7904 bool needs_recompute = false;
7907 /* FDI is a binary signal running at ~2.7GHz, encoding
7908 * each output octet as 10 bits. The actual frequency
7909 * is stored as a divider into a 100MHz clock, and the
7910 * mode pixel clock is stored in units of 1KHz.
7911 * Hence the bw of each lane in terms of the mode signal
7914 link_bw = intel_fdi_link_freq(i915, pipe_config);
7916 fdi_dotclock = adjusted_mode->crtc_clock;
7918 lane = ilk_get_lanes_required(fdi_dotclock, link_bw,
7919 pipe_config->pipe_bpp);
7921 pipe_config->fdi_lanes = lane;
7923 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7924 link_bw, &pipe_config->fdi_m_n, false, false);
7926 ret = ilk_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7927 if (ret == -EDEADLK)
7930 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7931 pipe_config->pipe_bpp -= 2*3;
7932 drm_dbg_kms(&i915->drm,
7933 "fdi link bw constraint, reducing pipe bpp to %i\n",
7934 pipe_config->pipe_bpp);
7935 needs_recompute = true;
7936 pipe_config->bw_constrained = true;
7941 if (needs_recompute)
7947 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
7949 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7950 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7952 /* IPS only exists on ULT machines and is tied to pipe A. */
7953 if (!hsw_crtc_supports_ips(crtc))
7956 if (!dev_priv->params.enable_ips)
7959 if (crtc_state->pipe_bpp > 24)
7963 * We compare against max which means we must take
7964 * the increased cdclk requirement into account when
7965 * calculating the new cdclk.
7967 * Should measure whether using a lower cdclk w/o IPS
7969 if (IS_BROADWELL(dev_priv) &&
7970 crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
7976 static int hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
7978 struct drm_i915_private *dev_priv =
7979 to_i915(crtc_state->uapi.crtc->dev);
7980 struct intel_atomic_state *state =
7981 to_intel_atomic_state(crtc_state->uapi.state);
7983 crtc_state->ips_enabled = false;
7985 if (!hsw_crtc_state_ips_capable(crtc_state))
7989 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
7990 * enabled and disabled dynamically based on package C states,
7991 * user space can't make reliable use of the CRCs, so let's just
7992 * completely disable it.
7994 if (crtc_state->crc_enabled)
7997 /* IPS should be fine as long as at least one plane is enabled. */
7998 if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
8001 if (IS_BROADWELL(dev_priv)) {
8002 const struct intel_cdclk_state *cdclk_state;
8004 cdclk_state = intel_atomic_get_cdclk_state(state);
8005 if (IS_ERR(cdclk_state))
8006 return PTR_ERR(cdclk_state);
8008 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
8009 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
8013 crtc_state->ips_enabled = true;
8018 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
8020 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8022 /* GDG double wide on either pipe, otherwise pipe A only */
8023 return INTEL_GEN(dev_priv) < 4 &&
8024 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
8027 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
8029 u32 pixel_rate = crtc_state->hw.adjusted_mode.crtc_clock;
8030 unsigned int pipe_w, pipe_h, pfit_w, pfit_h;
8033 * We only use IF-ID interlacing. If we ever use
8034 * PF-ID we'll need to adjust the pixel_rate here.
8037 if (!crtc_state->pch_pfit.enabled)
8040 pipe_w = crtc_state->pipe_src_w;
8041 pipe_h = crtc_state->pipe_src_h;
8043 pfit_w = drm_rect_width(&crtc_state->pch_pfit.dst);
8044 pfit_h = drm_rect_height(&crtc_state->pch_pfit.dst);
8046 if (pipe_w < pfit_w)
8048 if (pipe_h < pfit_h)
8051 if (drm_WARN_ON(crtc_state->uapi.crtc->dev,
8052 !pfit_w || !pfit_h))
8055 return div_u64(mul_u32_u32(pixel_rate, pipe_w * pipe_h),
8059 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
8061 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
8063 if (HAS_GMCH(dev_priv))
8064 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
8065 crtc_state->pixel_rate =
8066 crtc_state->hw.adjusted_mode.crtc_clock;
8068 crtc_state->pixel_rate =
8069 ilk_pipe_pixel_rate(crtc_state);
8072 static int intel_crtc_compute_config(struct intel_crtc *crtc,
8073 struct intel_crtc_state *pipe_config)
8075 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8076 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
8077 int clock_limit = dev_priv->max_dotclk_freq;
8079 if (INTEL_GEN(dev_priv) < 4) {
8080 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
8083 * Enable double wide mode when the dot clock
8084 * is > 90% of the (display) core speed.
8086 if (intel_crtc_supports_double_wide(crtc) &&
8087 adjusted_mode->crtc_clock > clock_limit) {
8088 clock_limit = dev_priv->max_dotclk_freq;
8089 pipe_config->double_wide = true;
8093 if (adjusted_mode->crtc_clock > clock_limit) {
8094 drm_dbg_kms(&dev_priv->drm,
8095 "requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
8096 adjusted_mode->crtc_clock, clock_limit,
8097 yesno(pipe_config->double_wide));
8101 if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
8102 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
8103 pipe_config->hw.ctm) {
8105 * There is only one pipe CSC unit per pipe, and we need that
8106 * for output conversion from RGB->YCBCR. So if CTM is already
8107 * applied we can't support YCBCR420 output.
8109 drm_dbg_kms(&dev_priv->drm,
8110 "YCBCR420 and CTM together are not possible\n");
8115 * Pipe horizontal size must be even in:
8117 * - LVDS dual channel mode
8118 * - Double wide pipe
8120 if (pipe_config->pipe_src_w & 1) {
8121 if (pipe_config->double_wide) {
8122 drm_dbg_kms(&dev_priv->drm,
8123 "Odd pipe source width not supported with double wide pipe\n");
8127 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
8128 intel_is_dual_link_lvds(dev_priv)) {
8129 drm_dbg_kms(&dev_priv->drm,
8130 "Odd pipe source width not supported with dual link LVDS\n");
8135 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
8136 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
8138 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
8139 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
8142 intel_crtc_compute_pixel_rate(pipe_config);
8144 if (pipe_config->has_pch_encoder)
8145 return ilk_fdi_compute_config(crtc, pipe_config);
8151 intel_reduce_m_n_ratio(u32 *num, u32 *den)
8153 while (*num > DATA_LINK_M_N_MASK ||
8154 *den > DATA_LINK_M_N_MASK) {
8160 static void compute_m_n(unsigned int m, unsigned int n,
8161 u32 *ret_m, u32 *ret_n,
8165 * Several DP dongles in particular seem to be fussy about
8166 * too large link M/N values. Give N value as 0x8000 that
8167 * should be acceptable by specific devices. 0x8000 is the
8168 * specified fixed N value for asynchronous clock mode,
8169 * which the devices expect also in synchronous clock mode.
8172 *ret_n = DP_LINK_CONSTANT_N_VALUE;
8174 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
8176 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
8177 intel_reduce_m_n_ratio(ret_m, ret_n);
8181 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
8182 int pixel_clock, int link_clock,
8183 struct intel_link_m_n *m_n,
8184 bool constant_n, bool fec_enable)
8186 u32 data_clock = bits_per_pixel * pixel_clock;
8189 data_clock = intel_dp_mode_to_fec_clock(data_clock);
8192 compute_m_n(data_clock,
8193 link_clock * nlanes * 8,
8194 &m_n->gmch_m, &m_n->gmch_n,
8197 compute_m_n(pixel_clock, link_clock,
8198 &m_n->link_m, &m_n->link_n,
8202 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
8205 * There may be no VBT; and if the BIOS enabled SSC we can
8206 * just keep using it to avoid unnecessary flicker. Whereas if the
8207 * BIOS isn't using it, don't assume it will work even if the VBT
8208 * indicates as much.
8210 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
8211 bool bios_lvds_use_ssc = intel_de_read(dev_priv,
8215 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
8216 drm_dbg_kms(&dev_priv->drm,
8217 "SSC %s by BIOS, overriding VBT which says %s\n",
8218 enableddisabled(bios_lvds_use_ssc),
8219 enableddisabled(dev_priv->vbt.lvds_use_ssc));
8220 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
8225 static bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
8227 if (dev_priv->params.panel_use_ssc >= 0)
8228 return dev_priv->params.panel_use_ssc != 0;
8229 return dev_priv->vbt.lvds_use_ssc
8230 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
8233 static u32 pnv_dpll_compute_fp(struct dpll *dpll)
8235 return (1 << dpll->n) << 16 | dpll->m2;
8238 static u32 i9xx_dpll_compute_fp(struct dpll *dpll)
8240 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
8243 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
8244 struct intel_crtc_state *crtc_state,
8245 struct dpll *reduced_clock)
8247 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8250 if (IS_PINEVIEW(dev_priv)) {
8251 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
8253 fp2 = pnv_dpll_compute_fp(reduced_clock);
8255 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8257 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8260 crtc_state->dpll_hw_state.fp0 = fp;
8262 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8264 crtc_state->dpll_hw_state.fp1 = fp2;
8266 crtc_state->dpll_hw_state.fp1 = fp;
8270 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
8276 * PLLB opamp always calibrates to max value of 0x3f, force enable it
8277 * and set it to a reasonable value instead.
8279 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
8280 reg_val &= 0xffffff00;
8281 reg_val |= 0x00000030;
8282 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
8284 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
8285 reg_val &= 0x00ffffff;
8286 reg_val |= 0x8c000000;
8287 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
8289 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
8290 reg_val &= 0xffffff00;
8291 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
8293 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
8294 reg_val &= 0x00ffffff;
8295 reg_val |= 0xb0000000;
8296 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
8299 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
8300 const struct intel_link_m_n *m_n)
8302 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8303 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8304 enum pipe pipe = crtc->pipe;
8306 intel_de_write(dev_priv, PCH_TRANS_DATA_M1(pipe),
8307 TU_SIZE(m_n->tu) | m_n->gmch_m);
8308 intel_de_write(dev_priv, PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
8309 intel_de_write(dev_priv, PCH_TRANS_LINK_M1(pipe), m_n->link_m);
8310 intel_de_write(dev_priv, PCH_TRANS_LINK_N1(pipe), m_n->link_n);
8313 static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
8314 enum transcoder transcoder)
8316 if (IS_HASWELL(dev_priv))
8317 return transcoder == TRANSCODER_EDP;
8320 * Strictly speaking some registers are available before
8321 * gen7, but we only support DRRS on gen7+
8323 return IS_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv);
8326 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
8327 const struct intel_link_m_n *m_n,
8328 const struct intel_link_m_n *m2_n2)
8330 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8331 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8332 enum pipe pipe = crtc->pipe;
8333 enum transcoder transcoder = crtc_state->cpu_transcoder;
8335 if (INTEL_GEN(dev_priv) >= 5) {
8336 intel_de_write(dev_priv, PIPE_DATA_M1(transcoder),
8337 TU_SIZE(m_n->tu) | m_n->gmch_m);
8338 intel_de_write(dev_priv, PIPE_DATA_N1(transcoder),
8340 intel_de_write(dev_priv, PIPE_LINK_M1(transcoder),
8342 intel_de_write(dev_priv, PIPE_LINK_N1(transcoder),
8345 * M2_N2 registers are set only if DRRS is supported
8346 * (to make sure the registers are not unnecessarily accessed).
8348 if (m2_n2 && crtc_state->has_drrs &&
8349 transcoder_has_m2_n2(dev_priv, transcoder)) {
8350 intel_de_write(dev_priv, PIPE_DATA_M2(transcoder),
8351 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
8352 intel_de_write(dev_priv, PIPE_DATA_N2(transcoder),
8354 intel_de_write(dev_priv, PIPE_LINK_M2(transcoder),
8356 intel_de_write(dev_priv, PIPE_LINK_N2(transcoder),
8360 intel_de_write(dev_priv, PIPE_DATA_M_G4X(pipe),
8361 TU_SIZE(m_n->tu) | m_n->gmch_m);
8362 intel_de_write(dev_priv, PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
8363 intel_de_write(dev_priv, PIPE_LINK_M_G4X(pipe), m_n->link_m);
8364 intel_de_write(dev_priv, PIPE_LINK_N_G4X(pipe), m_n->link_n);
8368 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
8370 const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
8371 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
8374 dp_m_n = &crtc_state->dp_m_n;
8375 dp_m2_n2 = &crtc_state->dp_m2_n2;
8376 } else if (m_n == M2_N2) {
8379 * M2_N2 registers are not supported. Hence m2_n2 divider value
8380 * needs to be programmed into M1_N1.
8382 dp_m_n = &crtc_state->dp_m2_n2;
8384 drm_err(&i915->drm, "Unsupported divider value\n");
8388 if (crtc_state->has_pch_encoder)
8389 intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);
8391 intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
8394 static void vlv_compute_dpll(struct intel_crtc *crtc,
8395 struct intel_crtc_state *pipe_config)
8397 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
8398 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
8399 if (crtc->pipe != PIPE_A)
8400 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
8402 /* DPLL not used with DSI, but still need the rest set up */
8403 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
8404 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
8405 DPLL_EXT_BUFFER_ENABLE_VLV;
8407 pipe_config->dpll_hw_state.dpll_md =
8408 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8411 static void chv_compute_dpll(struct intel_crtc *crtc,
8412 struct intel_crtc_state *pipe_config)
8414 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
8415 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
8416 if (crtc->pipe != PIPE_A)
8417 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
8419 /* DPLL not used with DSI, but still need the rest set up */
8420 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
8421 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
8423 pipe_config->dpll_hw_state.dpll_md =
8424 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8427 static void vlv_prepare_pll(struct intel_crtc *crtc,
8428 const struct intel_crtc_state *pipe_config)
8430 struct drm_device *dev = crtc->base.dev;
8431 struct drm_i915_private *dev_priv = to_i915(dev);
8432 enum pipe pipe = crtc->pipe;
8434 u32 bestn, bestm1, bestm2, bestp1, bestp2;
8435 u32 coreclk, reg_val;
8438 intel_de_write(dev_priv, DPLL(pipe),
8439 pipe_config->dpll_hw_state.dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
8441 /* No need to actually set up the DPLL with DSI */
8442 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8445 vlv_dpio_get(dev_priv);
8447 bestn = pipe_config->dpll.n;
8448 bestm1 = pipe_config->dpll.m1;
8449 bestm2 = pipe_config->dpll.m2;
8450 bestp1 = pipe_config->dpll.p1;
8451 bestp2 = pipe_config->dpll.p2;
8453 /* See eDP HDMI DPIO driver vbios notes doc */
8455 /* PLL B needs special handling */
8457 vlv_pllb_recal_opamp(dev_priv, pipe);
8459 /* Set up Tx target for periodic Rcomp update */
8460 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
8462 /* Disable target IRef on PLL */
8463 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
8464 reg_val &= 0x00ffffff;
8465 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
8467 /* Disable fast lock */
8468 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
8470 /* Set idtafcrecal before PLL is enabled */
8471 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
8472 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
8473 mdiv |= ((bestn << DPIO_N_SHIFT));
8474 mdiv |= (1 << DPIO_K_SHIFT);
8477 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
8478 * but we don't support that).
8479 * Note: don't use the DAC post divider as it seems unstable.
8481 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
8482 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
8484 mdiv |= DPIO_ENABLE_CALIBRATION;
8485 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
8487 /* Set HBR and RBR LPF coefficients */
8488 if (pipe_config->port_clock == 162000 ||
8489 intel_crtc_has_type(pipe_config, INTEL_OUTPUT_ANALOG) ||
8490 intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
8491 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
8494 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
8497 if (intel_crtc_has_dp_encoder(pipe_config)) {
8498 /* Use SSC source */
8500 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8503 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8505 } else { /* HDMI or VGA */
8506 /* Use bend source */
8508 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8511 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8515 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
8516 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
8517 if (intel_crtc_has_dp_encoder(pipe_config))
8518 coreclk |= 0x01000000;
8519 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
8521 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
8523 vlv_dpio_put(dev_priv);
8526 static void chv_prepare_pll(struct intel_crtc *crtc,
8527 const struct intel_crtc_state *pipe_config)
8529 struct drm_device *dev = crtc->base.dev;
8530 struct drm_i915_private *dev_priv = to_i915(dev);
8531 enum pipe pipe = crtc->pipe;
8532 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8533 u32 loopfilter, tribuf_calcntr;
8534 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
8538 /* Enable Refclk and SSC */
8539 intel_de_write(dev_priv, DPLL(pipe),
8540 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
8542 /* No need to actually set up the DPLL with DSI */
8543 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8546 bestn = pipe_config->dpll.n;
8547 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
8548 bestm1 = pipe_config->dpll.m1;
8549 bestm2 = pipe_config->dpll.m2 >> 22;
8550 bestp1 = pipe_config->dpll.p1;
8551 bestp2 = pipe_config->dpll.p2;
8552 vco = pipe_config->dpll.vco;
8556 vlv_dpio_get(dev_priv);
8558 /* p1 and p2 divider */
8559 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
8560 5 << DPIO_CHV_S1_DIV_SHIFT |
8561 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
8562 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
8563 1 << DPIO_CHV_K_DIV_SHIFT);
8565 /* Feedback post-divider - m2 */
8566 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
8568 /* Feedback refclk divider - n and m1 */
8569 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8570 DPIO_CHV_M1_DIV_BY_2 |
8571 1 << DPIO_CHV_N_DIV_SHIFT);
8573 /* M2 fraction division */
8574 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8576 /* M2 fraction division enable */
8577 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8578 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8579 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8581 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8582 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8584 /* Program digital lock detect threshold */
8585 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8586 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8587 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8588 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8590 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8591 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8594 if (vco == 5400000) {
8595 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8596 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8597 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8598 tribuf_calcntr = 0x9;
8599 } else if (vco <= 6200000) {
8600 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8601 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8602 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8603 tribuf_calcntr = 0x9;
8604 } else if (vco <= 6480000) {
8605 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8606 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8607 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8608 tribuf_calcntr = 0x8;
8610 /* Not supported. Apply the same limits as in the max case */
8611 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8612 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8613 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8616 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8618 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8619 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8620 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8621 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8624 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8625 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8628 vlv_dpio_put(dev_priv);
8632 * vlv_force_pll_on - forcibly enable just the PLL
8633 * @dev_priv: i915 private structure
8634 * @pipe: pipe PLL to enable
8635 * @dpll: PLL configuration
8637 * Enable the PLL for @pipe using the supplied @dpll config. To be used
8638 * in cases where we need the PLL enabled even when @pipe is not going to
8641 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
8642 const struct dpll *dpll)
8644 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
8645 struct intel_crtc_state *pipe_config;
8647 pipe_config = intel_crtc_state_alloc(crtc);
8651 pipe_config->cpu_transcoder = (enum transcoder)pipe;
8652 pipe_config->pixel_multiplier = 1;
8653 pipe_config->dpll = *dpll;
8655 if (IS_CHERRYVIEW(dev_priv)) {
8656 chv_compute_dpll(crtc, pipe_config);
8657 chv_prepare_pll(crtc, pipe_config);
8658 chv_enable_pll(crtc, pipe_config);
8660 vlv_compute_dpll(crtc, pipe_config);
8661 vlv_prepare_pll(crtc, pipe_config);
8662 vlv_enable_pll(crtc, pipe_config);
8671 * vlv_force_pll_off - forcibly disable just the PLL
8672 * @dev_priv: i915 private structure
8673 * @pipe: pipe PLL to disable
8675 * Disable the PLL for @pipe. To be used in cases where we need
8676 * the PLL enabled even when @pipe is not going to be enabled.
8678 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
8680 if (IS_CHERRYVIEW(dev_priv))
8681 chv_disable_pll(dev_priv, pipe);
8683 vlv_disable_pll(dev_priv, pipe);
8686 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8687 struct intel_crtc_state *crtc_state,
8688 struct dpll *reduced_clock)
8690 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8692 struct dpll *clock = &crtc_state->dpll;
8694 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8696 dpll = DPLL_VGA_MODE_DIS;
8698 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8699 dpll |= DPLLB_MODE_LVDS;
8701 dpll |= DPLLB_MODE_DAC_SERIAL;
8703 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8704 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8705 dpll |= (crtc_state->pixel_multiplier - 1)
8706 << SDVO_MULTIPLIER_SHIFT_HIRES;
8709 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8710 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8711 dpll |= DPLL_SDVO_HIGH_SPEED;
8713 if (intel_crtc_has_dp_encoder(crtc_state))
8714 dpll |= DPLL_SDVO_HIGH_SPEED;
8716 /* compute bitmask from p1 value */
8717 if (IS_PINEVIEW(dev_priv))
8718 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8720 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8721 if (IS_G4X(dev_priv) && reduced_clock)
8722 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8724 switch (clock->p2) {
8726 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8729 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8732 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8735 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8738 if (INTEL_GEN(dev_priv) >= 4)
8739 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8741 if (crtc_state->sdvo_tv_clock)
8742 dpll |= PLL_REF_INPUT_TVCLKINBC;
8743 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8744 intel_panel_use_ssc(dev_priv))
8745 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8747 dpll |= PLL_REF_INPUT_DREFCLK;
8749 dpll |= DPLL_VCO_ENABLE;
8750 crtc_state->dpll_hw_state.dpll = dpll;
8752 if (INTEL_GEN(dev_priv) >= 4) {
8753 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8754 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8755 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8759 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8760 struct intel_crtc_state *crtc_state,
8761 struct dpll *reduced_clock)
8763 struct drm_device *dev = crtc->base.dev;
8764 struct drm_i915_private *dev_priv = to_i915(dev);
8766 struct dpll *clock = &crtc_state->dpll;
8768 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8770 dpll = DPLL_VGA_MODE_DIS;
8772 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8773 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8776 dpll |= PLL_P1_DIVIDE_BY_TWO;
8778 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8780 dpll |= PLL_P2_DIVIDE_BY_4;
8785 * "[Almador Errata}: For the correct operation of the muxed DVO pins
8786 * (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
8787 * GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
8788 * Enable) must be set to “1” in both the DPLL A Control Register
8789 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
8791 * For simplicity We simply keep both bits always enabled in
8792 * both DPLLS. The spec says we should disable the DVO 2X clock
8793 * when not needed, but this seems to work fine in practice.
8795 if (IS_I830(dev_priv) ||
8796 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8797 dpll |= DPLL_DVO_2X_MODE;
8799 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8800 intel_panel_use_ssc(dev_priv))
8801 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8803 dpll |= PLL_REF_INPUT_DREFCLK;
8805 dpll |= DPLL_VCO_ENABLE;
8806 crtc_state->dpll_hw_state.dpll = dpll;
8809 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
8811 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8812 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8813 enum pipe pipe = crtc->pipe;
8814 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8815 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
8816 u32 crtc_vtotal, crtc_vblank_end;
8819 /* We need to be careful not to changed the adjusted mode, for otherwise
8820 * the hw state checker will get angry at the mismatch. */
8821 crtc_vtotal = adjusted_mode->crtc_vtotal;
8822 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8824 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8825 /* the chip adds 2 halflines automatically */
8827 crtc_vblank_end -= 1;
8829 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
8830 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8832 vsyncshift = adjusted_mode->crtc_hsync_start -
8833 adjusted_mode->crtc_htotal / 2;
8835 vsyncshift += adjusted_mode->crtc_htotal;
8838 if (INTEL_GEN(dev_priv) > 3)
8839 intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder),
8842 intel_de_write(dev_priv, HTOTAL(cpu_transcoder),
8843 (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16));
8844 intel_de_write(dev_priv, HBLANK(cpu_transcoder),
8845 (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
8846 intel_de_write(dev_priv, HSYNC(cpu_transcoder),
8847 (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
8849 intel_de_write(dev_priv, VTOTAL(cpu_transcoder),
8850 (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16));
8851 intel_de_write(dev_priv, VBLANK(cpu_transcoder),
8852 (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16));
8853 intel_de_write(dev_priv, VSYNC(cpu_transcoder),
8854 (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
8856 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8857 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8858 * documented on the DDI_FUNC_CTL register description, EDP Input Select
8860 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
8861 (pipe == PIPE_B || pipe == PIPE_C))
8862 intel_de_write(dev_priv, VTOTAL(pipe),
8863 intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
8867 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
8869 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8870 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8871 enum pipe pipe = crtc->pipe;
8873 /* pipesrc controls the size that is scaled from, which should
8874 * always be the user's requested size.
8876 intel_de_write(dev_priv, PIPESRC(pipe),
8877 ((crtc_state->pipe_src_w - 1) << 16) | (crtc_state->pipe_src_h - 1));
8880 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
8882 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
8883 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8885 if (IS_GEN(dev_priv, 2))
8888 if (INTEL_GEN(dev_priv) >= 9 ||
8889 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
8890 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW;
8892 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
8895 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8896 struct intel_crtc_state *pipe_config)
8898 struct drm_device *dev = crtc->base.dev;
8899 struct drm_i915_private *dev_priv = to_i915(dev);
8900 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8903 tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder));
8904 pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8905 pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8907 if (!transcoder_is_dsi(cpu_transcoder)) {
8908 tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder));
8909 pipe_config->hw.adjusted_mode.crtc_hblank_start =
8911 pipe_config->hw.adjusted_mode.crtc_hblank_end =
8912 ((tmp >> 16) & 0xffff) + 1;
8914 tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder));
8915 pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8916 pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8918 tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder));
8919 pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8920 pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8922 if (!transcoder_is_dsi(cpu_transcoder)) {
8923 tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder));
8924 pipe_config->hw.adjusted_mode.crtc_vblank_start =
8926 pipe_config->hw.adjusted_mode.crtc_vblank_end =
8927 ((tmp >> 16) & 0xffff) + 1;
8929 tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder));
8930 pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8931 pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8933 if (intel_pipe_is_interlaced(pipe_config)) {
8934 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8935 pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
8936 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
8940 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8941 struct intel_crtc_state *pipe_config)
8943 struct drm_device *dev = crtc->base.dev;
8944 struct drm_i915_private *dev_priv = to_i915(dev);
8947 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
8948 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8949 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8951 pipe_config->hw.mode.vdisplay = pipe_config->pipe_src_h;
8952 pipe_config->hw.mode.hdisplay = pipe_config->pipe_src_w;
8955 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8956 struct intel_crtc_state *pipe_config)
8958 mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay;
8959 mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal;
8960 mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start;
8961 mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end;
8963 mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay;
8964 mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal;
8965 mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start;
8966 mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end;
8968 mode->flags = pipe_config->hw.adjusted_mode.flags;
8969 mode->type = DRM_MODE_TYPE_DRIVER;
8971 mode->clock = pipe_config->hw.adjusted_mode.crtc_clock;
8973 drm_mode_set_name(mode);
8976 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
8978 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8979 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8984 /* we keep both pipes enabled on 830 */
8985 if (IS_I830(dev_priv))
8986 pipeconf |= intel_de_read(dev_priv, PIPECONF(crtc->pipe)) & PIPECONF_ENABLE;
8988 if (crtc_state->double_wide)
8989 pipeconf |= PIPECONF_DOUBLE_WIDE;
8991 /* only g4x and later have fancy bpc/dither controls */
8992 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8993 IS_CHERRYVIEW(dev_priv)) {
8994 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8995 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
8996 pipeconf |= PIPECONF_DITHER_EN |
8997 PIPECONF_DITHER_TYPE_SP;
8999 switch (crtc_state->pipe_bpp) {
9001 pipeconf |= PIPECONF_6BPC;
9004 pipeconf |= PIPECONF_8BPC;
9007 pipeconf |= PIPECONF_10BPC;
9010 /* Case prevented by intel_choose_pipe_bpp_dither. */
9015 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
9016 if (INTEL_GEN(dev_priv) < 4 ||
9017 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
9018 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
9020 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
9022 pipeconf |= PIPECONF_PROGRESSIVE;
9025 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
9026 crtc_state->limited_color_range)
9027 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9029 pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
9031 pipeconf |= PIPECONF_FRAME_START_DELAY(0);
9033 intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf);
9034 intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe));
9037 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
9038 struct intel_crtc_state *crtc_state)
9040 struct drm_device *dev = crtc->base.dev;
9041 struct drm_i915_private *dev_priv = to_i915(dev);
9042 const struct intel_limit *limit;
9045 memset(&crtc_state->dpll_hw_state, 0,
9046 sizeof(crtc_state->dpll_hw_state));
9048 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9049 if (intel_panel_use_ssc(dev_priv)) {
9050 refclk = dev_priv->vbt.lvds_ssc_freq;
9051 drm_dbg_kms(&dev_priv->drm,
9052 "using SSC reference clock of %d kHz\n",
9056 limit = &intel_limits_i8xx_lvds;
9057 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
9058 limit = &intel_limits_i8xx_dvo;
9060 limit = &intel_limits_i8xx_dac;
9063 if (!crtc_state->clock_set &&
9064 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9065 refclk, NULL, &crtc_state->dpll)) {
9066 drm_err(&dev_priv->drm,
9067 "Couldn't find PLL settings for mode!\n");
9071 i8xx_compute_dpll(crtc, crtc_state, NULL);
9076 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
9077 struct intel_crtc_state *crtc_state)
9079 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9080 const struct intel_limit *limit;
9083 memset(&crtc_state->dpll_hw_state, 0,
9084 sizeof(crtc_state->dpll_hw_state));
9086 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9087 if (intel_panel_use_ssc(dev_priv)) {
9088 refclk = dev_priv->vbt.lvds_ssc_freq;
9089 drm_dbg_kms(&dev_priv->drm,
9090 "using SSC reference clock of %d kHz\n",
9094 if (intel_is_dual_link_lvds(dev_priv))
9095 limit = &intel_limits_g4x_dual_channel_lvds;
9097 limit = &intel_limits_g4x_single_channel_lvds;
9098 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
9099 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
9100 limit = &intel_limits_g4x_hdmi;
9101 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
9102 limit = &intel_limits_g4x_sdvo;
9104 /* The option is for other outputs */
9105 limit = &intel_limits_i9xx_sdvo;
9108 if (!crtc_state->clock_set &&
9109 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9110 refclk, NULL, &crtc_state->dpll)) {
9111 drm_err(&dev_priv->drm,
9112 "Couldn't find PLL settings for mode!\n");
9116 i9xx_compute_dpll(crtc, crtc_state, NULL);
9121 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
9122 struct intel_crtc_state *crtc_state)
9124 struct drm_device *dev = crtc->base.dev;
9125 struct drm_i915_private *dev_priv = to_i915(dev);
9126 const struct intel_limit *limit;
9129 memset(&crtc_state->dpll_hw_state, 0,
9130 sizeof(crtc_state->dpll_hw_state));
9132 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9133 if (intel_panel_use_ssc(dev_priv)) {
9134 refclk = dev_priv->vbt.lvds_ssc_freq;
9135 drm_dbg_kms(&dev_priv->drm,
9136 "using SSC reference clock of %d kHz\n",
9140 limit = &pnv_limits_lvds;
9142 limit = &pnv_limits_sdvo;
9145 if (!crtc_state->clock_set &&
9146 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9147 refclk, NULL, &crtc_state->dpll)) {
9148 drm_err(&dev_priv->drm,
9149 "Couldn't find PLL settings for mode!\n");
9153 i9xx_compute_dpll(crtc, crtc_state, NULL);
9158 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
9159 struct intel_crtc_state *crtc_state)
9161 struct drm_device *dev = crtc->base.dev;
9162 struct drm_i915_private *dev_priv = to_i915(dev);
9163 const struct intel_limit *limit;
9166 memset(&crtc_state->dpll_hw_state, 0,
9167 sizeof(crtc_state->dpll_hw_state));
9169 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9170 if (intel_panel_use_ssc(dev_priv)) {
9171 refclk = dev_priv->vbt.lvds_ssc_freq;
9172 drm_dbg_kms(&dev_priv->drm,
9173 "using SSC reference clock of %d kHz\n",
9177 limit = &intel_limits_i9xx_lvds;
9179 limit = &intel_limits_i9xx_sdvo;
9182 if (!crtc_state->clock_set &&
9183 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9184 refclk, NULL, &crtc_state->dpll)) {
9185 drm_err(&dev_priv->drm,
9186 "Couldn't find PLL settings for mode!\n");
9190 i9xx_compute_dpll(crtc, crtc_state, NULL);
9195 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
9196 struct intel_crtc_state *crtc_state)
9198 int refclk = 100000;
9199 const struct intel_limit *limit = &intel_limits_chv;
9200 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
9202 memset(&crtc_state->dpll_hw_state, 0,
9203 sizeof(crtc_state->dpll_hw_state));
9205 if (!crtc_state->clock_set &&
9206 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9207 refclk, NULL, &crtc_state->dpll)) {
9208 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n");
9212 chv_compute_dpll(crtc, crtc_state);
9217 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
9218 struct intel_crtc_state *crtc_state)
9220 int refclk = 100000;
9221 const struct intel_limit *limit = &intel_limits_vlv;
9222 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
9224 memset(&crtc_state->dpll_hw_state, 0,
9225 sizeof(crtc_state->dpll_hw_state));
9227 if (!crtc_state->clock_set &&
9228 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9229 refclk, NULL, &crtc_state->dpll)) {
9230 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n");
9234 vlv_compute_dpll(crtc, crtc_state);
9239 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
9241 if (IS_I830(dev_priv))
9244 return INTEL_GEN(dev_priv) >= 4 ||
9245 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
9248 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
9250 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9251 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9254 if (!i9xx_has_pfit(dev_priv))
9257 tmp = intel_de_read(dev_priv, PFIT_CONTROL);
9258 if (!(tmp & PFIT_ENABLE))
9261 /* Check whether the pfit is attached to our pipe. */
9262 if (INTEL_GEN(dev_priv) < 4) {
9263 if (crtc->pipe != PIPE_B)
9266 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
9270 crtc_state->gmch_pfit.control = tmp;
9271 crtc_state->gmch_pfit.pgm_ratios =
9272 intel_de_read(dev_priv, PFIT_PGM_RATIOS);
9275 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
9276 struct intel_crtc_state *pipe_config)
9278 struct drm_device *dev = crtc->base.dev;
9279 struct drm_i915_private *dev_priv = to_i915(dev);
9280 enum pipe pipe = crtc->pipe;
9283 int refclk = 100000;
9285 /* In case of DSI, DPLL will not be used */
9286 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
9289 vlv_dpio_get(dev_priv);
9290 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
9291 vlv_dpio_put(dev_priv);
9293 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
9294 clock.m2 = mdiv & DPIO_M2DIV_MASK;
9295 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
9296 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
9297 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
9299 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
9303 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
9304 struct intel_initial_plane_config *plane_config)
9306 struct drm_device *dev = crtc->base.dev;
9307 struct drm_i915_private *dev_priv = to_i915(dev);
9308 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
9309 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
9311 u32 val, base, offset;
9312 int fourcc, pixel_format;
9313 unsigned int aligned_height;
9314 struct drm_framebuffer *fb;
9315 struct intel_framebuffer *intel_fb;
9317 if (!plane->get_hw_state(plane, &pipe))
9320 drm_WARN_ON(dev, pipe != crtc->pipe);
9322 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9324 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
9328 fb = &intel_fb->base;
9332 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
9334 if (INTEL_GEN(dev_priv) >= 4) {
9335 if (val & DISPPLANE_TILED) {
9336 plane_config->tiling = I915_TILING_X;
9337 fb->modifier = I915_FORMAT_MOD_X_TILED;
9340 if (val & DISPPLANE_ROTATE_180)
9341 plane_config->rotation = DRM_MODE_ROTATE_180;
9344 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
9345 val & DISPPLANE_MIRROR)
9346 plane_config->rotation |= DRM_MODE_REFLECT_X;
9348 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9349 fourcc = i9xx_format_to_fourcc(pixel_format);
9350 fb->format = drm_format_info(fourcc);
9352 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
9353 offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));
9354 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
9355 } else if (INTEL_GEN(dev_priv) >= 4) {
9356 if (plane_config->tiling)
9357 offset = intel_de_read(dev_priv,
9358 DSPTILEOFF(i9xx_plane));
9360 offset = intel_de_read(dev_priv,
9361 DSPLINOFF(i9xx_plane));
9362 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
9364 base = intel_de_read(dev_priv, DSPADDR(i9xx_plane));
9366 plane_config->base = base;
9368 val = intel_de_read(dev_priv, PIPESRC(pipe));
9369 fb->width = ((val >> 16) & 0xfff) + 1;
9370 fb->height = ((val >> 0) & 0xfff) + 1;
9372 val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane));
9373 fb->pitches[0] = val & 0xffffffc0;
9375 aligned_height = intel_fb_align_height(fb, 0, fb->height);
9377 plane_config->size = fb->pitches[0] * aligned_height;
9379 drm_dbg_kms(&dev_priv->drm,
9380 "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9381 crtc->base.name, plane->base.name, fb->width, fb->height,
9382 fb->format->cpp[0] * 8, base, fb->pitches[0],
9383 plane_config->size);
9385 plane_config->fb = intel_fb;
9388 static void chv_crtc_clock_get(struct intel_crtc *crtc,
9389 struct intel_crtc_state *pipe_config)
9391 struct drm_device *dev = crtc->base.dev;
9392 struct drm_i915_private *dev_priv = to_i915(dev);
9393 enum pipe pipe = crtc->pipe;
9394 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9396 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
9397 int refclk = 100000;
9399 /* In case of DSI, DPLL will not be used */
9400 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
9403 vlv_dpio_get(dev_priv);
9404 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
9405 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
9406 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
9407 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
9408 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
9409 vlv_dpio_put(dev_priv);
9411 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
9412 clock.m2 = (pll_dw0 & 0xff) << 22;
9413 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
9414 clock.m2 |= pll_dw2 & 0x3fffff;
9415 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
9416 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
9417 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
9419 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
9422 static enum intel_output_format
9423 bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
9425 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9428 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
9430 if (tmp & PIPEMISC_YUV420_ENABLE) {
9431 /* We support 4:2:0 in full blend mode only */
9432 drm_WARN_ON(&dev_priv->drm,
9433 (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0);
9435 return INTEL_OUTPUT_FORMAT_YCBCR420;
9436 } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
9437 return INTEL_OUTPUT_FORMAT_YCBCR444;
9439 return INTEL_OUTPUT_FORMAT_RGB;
9443 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
9445 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9446 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
9447 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9448 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
9451 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
9453 if (tmp & DISPPLANE_GAMMA_ENABLE)
9454 crtc_state->gamma_enable = true;
9456 if (!HAS_GMCH(dev_priv) &&
9457 tmp & DISPPLANE_PIPE_CSC_ENABLE)
9458 crtc_state->csc_enable = true;
9461 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
9462 struct intel_crtc_state *pipe_config)
9464 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9465 enum intel_display_power_domain power_domain;
9466 intel_wakeref_t wakeref;
9470 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9471 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
9475 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
9476 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9477 pipe_config->shared_dpll = NULL;
9481 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
9482 if (!(tmp & PIPECONF_ENABLE))
9485 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
9486 IS_CHERRYVIEW(dev_priv)) {
9487 switch (tmp & PIPECONF_BPC_MASK) {
9489 pipe_config->pipe_bpp = 18;
9492 pipe_config->pipe_bpp = 24;
9494 case PIPECONF_10BPC:
9495 pipe_config->pipe_bpp = 30;
9502 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
9503 (tmp & PIPECONF_COLOR_RANGE_SELECT))
9504 pipe_config->limited_color_range = true;
9506 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
9507 PIPECONF_GAMMA_MODE_SHIFT;
9509 if (IS_CHERRYVIEW(dev_priv))
9510 pipe_config->cgm_mode = intel_de_read(dev_priv,
9511 CGM_PIPE_MODE(crtc->pipe));
9513 i9xx_get_pipe_color_config(pipe_config);
9514 intel_color_get_config(pipe_config);
9516 if (INTEL_GEN(dev_priv) < 4)
9517 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
9519 intel_get_pipe_timings(crtc, pipe_config);
9520 intel_get_pipe_src_size(crtc, pipe_config);
9522 i9xx_get_pfit_config(pipe_config);
9524 if (INTEL_GEN(dev_priv) >= 4) {
9525 /* No way to read it out on pipes B and C */
9526 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
9527 tmp = dev_priv->chv_dpll_md[crtc->pipe];
9529 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
9530 pipe_config->pixel_multiplier =
9531 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
9532 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
9533 pipe_config->dpll_hw_state.dpll_md = tmp;
9534 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
9535 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
9536 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe));
9537 pipe_config->pixel_multiplier =
9538 ((tmp & SDVO_MULTIPLIER_MASK)
9539 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
9541 /* Note that on i915G/GM the pixel multiplier is in the sdvo
9542 * port and will be fixed up in the encoder->get_config
9544 pipe_config->pixel_multiplier = 1;
9546 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv,
9548 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
9549 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv,
9551 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv,
9554 /* Mask out read-only status bits. */
9555 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
9556 DPLL_PORTC_READY_MASK |
9557 DPLL_PORTB_READY_MASK);
9560 if (IS_CHERRYVIEW(dev_priv))
9561 chv_crtc_clock_get(crtc, pipe_config);
9562 else if (IS_VALLEYVIEW(dev_priv))
9563 vlv_crtc_clock_get(crtc, pipe_config);
9565 i9xx_crtc_clock_get(crtc, pipe_config);
9568 * Normally the dotclock is filled in by the encoder .get_config()
9569 * but in case the pipe is enabled w/o any ports we need a sane
9572 pipe_config->hw.adjusted_mode.crtc_clock =
9573 pipe_config->port_clock / pipe_config->pixel_multiplier;
9578 intel_display_power_put(dev_priv, power_domain, wakeref);
9583 static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
9585 struct intel_encoder *encoder;
9588 bool has_lvds = false;
9589 bool has_cpu_edp = false;
9590 bool has_panel = false;
9591 bool has_ck505 = false;
9592 bool can_ssc = false;
9593 bool using_ssc_source = false;
9595 /* We need to take the global config into account */
9596 for_each_intel_encoder(&dev_priv->drm, encoder) {
9597 switch (encoder->type) {
9598 case INTEL_OUTPUT_LVDS:
9602 case INTEL_OUTPUT_EDP:
9604 if (encoder->port == PORT_A)
9612 if (HAS_PCH_IBX(dev_priv)) {
9613 has_ck505 = dev_priv->vbt.display_clock_mode;
9614 can_ssc = has_ck505;
9620 /* Check if any DPLLs are using the SSC source */
9621 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
9622 u32 temp = intel_de_read(dev_priv, PCH_DPLL(i));
9624 if (!(temp & DPLL_VCO_ENABLE))
9627 if ((temp & PLL_REF_INPUT_MASK) ==
9628 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
9629 using_ssc_source = true;
9634 drm_dbg_kms(&dev_priv->drm,
9635 "has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
9636 has_panel, has_lvds, has_ck505, using_ssc_source);
9638 /* Ironlake: try to setup display ref clock before DPLL
9639 * enabling. This is only under driver's control after
9640 * PCH B stepping, previous chipset stepping should be
9641 * ignoring this setting.
9643 val = intel_de_read(dev_priv, PCH_DREF_CONTROL);
9645 /* As we must carefully and slowly disable/enable each source in turn,
9646 * compute the final state we want first and check if we need to
9647 * make any changes at all.
9650 final &= ~DREF_NONSPREAD_SOURCE_MASK;
9652 final |= DREF_NONSPREAD_CK505_ENABLE;
9654 final |= DREF_NONSPREAD_SOURCE_ENABLE;
9656 final &= ~DREF_SSC_SOURCE_MASK;
9657 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9658 final &= ~DREF_SSC1_ENABLE;
9661 final |= DREF_SSC_SOURCE_ENABLE;
9663 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9664 final |= DREF_SSC1_ENABLE;
9667 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9668 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9670 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9672 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9673 } else if (using_ssc_source) {
9674 final |= DREF_SSC_SOURCE_ENABLE;
9675 final |= DREF_SSC1_ENABLE;
9681 /* Always enable nonspread source */
9682 val &= ~DREF_NONSPREAD_SOURCE_MASK;
9685 val |= DREF_NONSPREAD_CK505_ENABLE;
9687 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9690 val &= ~DREF_SSC_SOURCE_MASK;
9691 val |= DREF_SSC_SOURCE_ENABLE;
9693 /* SSC must be turned on before enabling the CPU output */
9694 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9695 drm_dbg_kms(&dev_priv->drm, "Using SSC on panel\n");
9696 val |= DREF_SSC1_ENABLE;
9698 val &= ~DREF_SSC1_ENABLE;
9700 /* Get SSC going before enabling the outputs */
9701 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9702 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9705 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9707 /* Enable CPU source on CPU attached eDP */
9709 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9710 drm_dbg_kms(&dev_priv->drm,
9711 "Using SSC on eDP\n");
9712 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9714 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9716 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9718 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9719 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9722 drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n");
9724 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9726 /* Turn off CPU output */
9727 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9729 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9730 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9733 if (!using_ssc_source) {
9734 drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n");
9736 /* Turn off the SSC source */
9737 val &= ~DREF_SSC_SOURCE_MASK;
9738 val |= DREF_SSC_SOURCE_DISABLE;
9741 val &= ~DREF_SSC1_ENABLE;
9743 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9744 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9749 BUG_ON(val != final);
9752 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9756 tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
9757 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9758 intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
9760 if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) &
9761 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9762 drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n");
9764 tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
9765 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9766 intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
9768 if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) &
9769 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9770 drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n");
9773 /* WaMPhyProgramming:hsw */
9774 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9778 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9779 tmp &= ~(0xFF << 24);
9780 tmp |= (0x12 << 24);
9781 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9783 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9785 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9787 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9789 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9791 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9792 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9793 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9795 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9796 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9797 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9799 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9802 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9804 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9807 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9809 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9812 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9814 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9817 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9819 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9820 tmp &= ~(0xFF << 16);
9821 tmp |= (0x1C << 16);
9822 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9824 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9825 tmp &= ~(0xFF << 16);
9826 tmp |= (0x1C << 16);
9827 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9829 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9831 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9833 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9835 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9837 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9838 tmp &= ~(0xF << 28);
9840 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9842 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9843 tmp &= ~(0xF << 28);
9845 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9848 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9849 * Programming" based on the parameters passed:
9850 * - Sequence to enable CLKOUT_DP
9851 * - Sequence to enable CLKOUT_DP without spread
9852 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9854 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
9855 bool with_spread, bool with_fdi)
9859 if (drm_WARN(&dev_priv->drm, with_fdi && !with_spread,
9860 "FDI requires downspread\n"))
9862 if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) &&
9863 with_fdi, "LP PCH doesn't have FDI\n"))
9866 mutex_lock(&dev_priv->sb_lock);
9868 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9869 tmp &= ~SBI_SSCCTL_DISABLE;
9870 tmp |= SBI_SSCCTL_PATHALT;
9871 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9876 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9877 tmp &= ~SBI_SSCCTL_PATHALT;
9878 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9881 lpt_reset_fdi_mphy(dev_priv);
9882 lpt_program_fdi_mphy(dev_priv);
9886 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9887 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9888 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9889 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9891 mutex_unlock(&dev_priv->sb_lock);
9894 /* Sequence to disable CLKOUT_DP */
9895 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
9899 mutex_lock(&dev_priv->sb_lock);
9901 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9902 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9903 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9904 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9906 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9907 if (!(tmp & SBI_SSCCTL_DISABLE)) {
9908 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9909 tmp |= SBI_SSCCTL_PATHALT;
9910 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9913 tmp |= SBI_SSCCTL_DISABLE;
9914 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9917 mutex_unlock(&dev_priv->sb_lock);
9920 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9922 static const u16 sscdivintphase[] = {
9923 [BEND_IDX( 50)] = 0x3B23,
9924 [BEND_IDX( 45)] = 0x3B23,
9925 [BEND_IDX( 40)] = 0x3C23,
9926 [BEND_IDX( 35)] = 0x3C23,
9927 [BEND_IDX( 30)] = 0x3D23,
9928 [BEND_IDX( 25)] = 0x3D23,
9929 [BEND_IDX( 20)] = 0x3E23,
9930 [BEND_IDX( 15)] = 0x3E23,
9931 [BEND_IDX( 10)] = 0x3F23,
9932 [BEND_IDX( 5)] = 0x3F23,
9933 [BEND_IDX( 0)] = 0x0025,
9934 [BEND_IDX( -5)] = 0x0025,
9935 [BEND_IDX(-10)] = 0x0125,
9936 [BEND_IDX(-15)] = 0x0125,
9937 [BEND_IDX(-20)] = 0x0225,
9938 [BEND_IDX(-25)] = 0x0225,
9939 [BEND_IDX(-30)] = 0x0325,
9940 [BEND_IDX(-35)] = 0x0325,
9941 [BEND_IDX(-40)] = 0x0425,
9942 [BEND_IDX(-45)] = 0x0425,
9943 [BEND_IDX(-50)] = 0x0525,
9948 * steps -50 to 50 inclusive, in steps of 5
9949 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9950 * change in clock period = -(steps / 10) * 5.787 ps
9952 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9955 int idx = BEND_IDX(steps);
9957 if (drm_WARN_ON(&dev_priv->drm, steps % 5 != 0))
9960 if (drm_WARN_ON(&dev_priv->drm, idx >= ARRAY_SIZE(sscdivintphase)))
9963 mutex_lock(&dev_priv->sb_lock);
9965 if (steps % 10 != 0)
9969 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9971 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9973 tmp |= sscdivintphase[idx];
9974 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9976 mutex_unlock(&dev_priv->sb_lock);
9981 static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
9983 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
9984 u32 ctl = intel_de_read(dev_priv, SPLL_CTL);
9986 if ((ctl & SPLL_PLL_ENABLE) == 0)
9989 if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC &&
9990 (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
9993 if (IS_BROADWELL(dev_priv) &&
9994 (ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW)
10000 static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
10001 enum intel_dpll_id id)
10003 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
10004 u32 ctl = intel_de_read(dev_priv, WRPLL_CTL(id));
10006 if ((ctl & WRPLL_PLL_ENABLE) == 0)
10009 if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
10012 if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
10013 (ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW &&
10014 (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
10020 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
10022 struct intel_encoder *encoder;
10023 bool has_fdi = false;
10025 for_each_intel_encoder(&dev_priv->drm, encoder) {
10026 switch (encoder->type) {
10027 case INTEL_OUTPUT_ANALOG:
10036 * The BIOS may have decided to use the PCH SSC
10037 * reference so we must not disable it until the
10038 * relevant PLLs have stopped relying on it. We'll
10039 * just leave the PCH SSC reference enabled in case
10040 * any active PLL is using it. It will get disabled
10041 * after runtime suspend if we don't have FDI.
10043 * TODO: Move the whole reference clock handling
10044 * to the modeset sequence proper so that we can
10045 * actually enable/disable/reconfigure these things
10046 * safely. To do that we need to introduce a real
10047 * clock hierarchy. That would also allow us to do
10048 * clock bending finally.
10050 dev_priv->pch_ssc_use = 0;
10052 if (spll_uses_pch_ssc(dev_priv)) {
10053 drm_dbg_kms(&dev_priv->drm, "SPLL using PCH SSC\n");
10054 dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
10057 if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
10058 drm_dbg_kms(&dev_priv->drm, "WRPLL1 using PCH SSC\n");
10059 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
10062 if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
10063 drm_dbg_kms(&dev_priv->drm, "WRPLL2 using PCH SSC\n");
10064 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
10067 if (dev_priv->pch_ssc_use)
10071 lpt_bend_clkout_dp(dev_priv, 0);
10072 lpt_enable_clkout_dp(dev_priv, true, true);
10074 lpt_disable_clkout_dp(dev_priv);
10079 * Initialize reference clocks when the driver loads
10081 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
10083 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
10084 ilk_init_pch_refclk(dev_priv);
10085 else if (HAS_PCH_LPT(dev_priv))
10086 lpt_init_pch_refclk(dev_priv);
10089 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
10091 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10092 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10093 enum pipe pipe = crtc->pipe;
10098 switch (crtc_state->pipe_bpp) {
10100 val |= PIPECONF_6BPC;
10103 val |= PIPECONF_8BPC;
10106 val |= PIPECONF_10BPC;
10109 val |= PIPECONF_12BPC;
10112 /* Case prevented by intel_choose_pipe_bpp_dither. */
10116 if (crtc_state->dither)
10117 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
10119 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
10120 val |= PIPECONF_INTERLACED_ILK;
10122 val |= PIPECONF_PROGRESSIVE;
10125 * This would end up with an odd purple hue over
10126 * the entire display. Make sure we don't do it.
10128 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
10129 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
10131 if (crtc_state->limited_color_range &&
10132 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
10133 val |= PIPECONF_COLOR_RANGE_SELECT;
10135 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
10136 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
10138 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
10140 val |= PIPECONF_FRAME_START_DELAY(0);
10142 intel_de_write(dev_priv, PIPECONF(pipe), val);
10143 intel_de_posting_read(dev_priv, PIPECONF(pipe));
10146 static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state)
10148 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10149 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10150 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
10153 if (IS_HASWELL(dev_priv) && crtc_state->dither)
10154 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
10156 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
10157 val |= PIPECONF_INTERLACED_ILK;
10159 val |= PIPECONF_PROGRESSIVE;
10161 if (IS_HASWELL(dev_priv) &&
10162 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
10163 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
10165 intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val);
10166 intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder));
10169 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
10171 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10172 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10175 switch (crtc_state->pipe_bpp) {
10177 val |= PIPEMISC_DITHER_6_BPC;
10180 val |= PIPEMISC_DITHER_8_BPC;
10183 val |= PIPEMISC_DITHER_10_BPC;
10186 val |= PIPEMISC_DITHER_12_BPC;
10189 MISSING_CASE(crtc_state->pipe_bpp);
10193 if (crtc_state->dither)
10194 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
10196 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
10197 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
10198 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
10200 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
10201 val |= PIPEMISC_YUV420_ENABLE |
10202 PIPEMISC_YUV420_MODE_FULL_BLEND;
10204 if (INTEL_GEN(dev_priv) >= 11 &&
10205 (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
10206 BIT(PLANE_CURSOR))) == 0)
10207 val |= PIPEMISC_HDR_MODE_PRECISION;
10209 if (INTEL_GEN(dev_priv) >= 12)
10210 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC;
10212 intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val);
10215 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
10217 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10220 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
10222 switch (tmp & PIPEMISC_DITHER_BPC_MASK) {
10223 case PIPEMISC_DITHER_6_BPC:
10225 case PIPEMISC_DITHER_8_BPC:
10227 case PIPEMISC_DITHER_10_BPC:
10229 case PIPEMISC_DITHER_12_BPC:
10237 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
10240 * Account for spread spectrum to avoid
10241 * oversubscribing the link. Max center spread
10242 * is 2.5%; use 5% for safety's sake.
10244 u32 bps = target_clock * bpp * 21 / 20;
10245 return DIV_ROUND_UP(bps, link_bw * 8);
10248 static bool ilk_needs_fb_cb_tune(struct dpll *dpll, int factor)
10250 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
10253 static void ilk_compute_dpll(struct intel_crtc *crtc,
10254 struct intel_crtc_state *crtc_state,
10255 struct dpll *reduced_clock)
10257 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10261 /* Enable autotuning of the PLL clock (if permissible) */
10263 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
10264 if ((intel_panel_use_ssc(dev_priv) &&
10265 dev_priv->vbt.lvds_ssc_freq == 100000) ||
10266 (HAS_PCH_IBX(dev_priv) &&
10267 intel_is_dual_link_lvds(dev_priv)))
10269 } else if (crtc_state->sdvo_tv_clock) {
10273 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
10275 if (ilk_needs_fb_cb_tune(&crtc_state->dpll, factor))
10278 if (reduced_clock) {
10279 fp2 = i9xx_dpll_compute_fp(reduced_clock);
10281 if (reduced_clock->m < factor * reduced_clock->n)
10289 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
10290 dpll |= DPLLB_MODE_LVDS;
10292 dpll |= DPLLB_MODE_DAC_SERIAL;
10294 dpll |= (crtc_state->pixel_multiplier - 1)
10295 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
10297 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
10298 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
10299 dpll |= DPLL_SDVO_HIGH_SPEED;
10301 if (intel_crtc_has_dp_encoder(crtc_state))
10302 dpll |= DPLL_SDVO_HIGH_SPEED;
10305 * The high speed IO clock is only really required for
10306 * SDVO/HDMI/DP, but we also enable it for CRT to make it
10307 * possible to share the DPLL between CRT and HDMI. Enabling
10308 * the clock needlessly does no real harm, except use up a
10309 * bit of power potentially.
10311 * We'll limit this to IVB with 3 pipes, since it has only two
10312 * DPLLs and so DPLL sharing is the only way to get three pipes
10313 * driving PCH ports at the same time. On SNB we could do this,
10314 * and potentially avoid enabling the second DPLL, but it's not
10315 * clear if it''s a win or loss power wise. No point in doing
10316 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
10318 if (INTEL_NUM_PIPES(dev_priv) == 3 &&
10319 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
10320 dpll |= DPLL_SDVO_HIGH_SPEED;
10322 /* compute bitmask from p1 value */
10323 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
10325 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
10327 switch (crtc_state->dpll.p2) {
10329 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
10332 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
10335 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
10338 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
10342 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
10343 intel_panel_use_ssc(dev_priv))
10344 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
10346 dpll |= PLL_REF_INPUT_DREFCLK;
10348 dpll |= DPLL_VCO_ENABLE;
10350 crtc_state->dpll_hw_state.dpll = dpll;
10351 crtc_state->dpll_hw_state.fp0 = fp;
10352 crtc_state->dpll_hw_state.fp1 = fp2;
10355 static int ilk_crtc_compute_clock(struct intel_crtc *crtc,
10356 struct intel_crtc_state *crtc_state)
10358 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10359 struct intel_atomic_state *state =
10360 to_intel_atomic_state(crtc_state->uapi.state);
10361 const struct intel_limit *limit;
10362 int refclk = 120000;
10364 memset(&crtc_state->dpll_hw_state, 0,
10365 sizeof(crtc_state->dpll_hw_state));
10367 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
10368 if (!crtc_state->has_pch_encoder)
10371 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
10372 if (intel_panel_use_ssc(dev_priv)) {
10373 drm_dbg_kms(&dev_priv->drm,
10374 "using SSC reference clock of %d kHz\n",
10375 dev_priv->vbt.lvds_ssc_freq);
10376 refclk = dev_priv->vbt.lvds_ssc_freq;
10379 if (intel_is_dual_link_lvds(dev_priv)) {
10380 if (refclk == 100000)
10381 limit = &ilk_limits_dual_lvds_100m;
10383 limit = &ilk_limits_dual_lvds;
10385 if (refclk == 100000)
10386 limit = &ilk_limits_single_lvds_100m;
10388 limit = &ilk_limits_single_lvds;
10391 limit = &ilk_limits_dac;
10394 if (!crtc_state->clock_set &&
10395 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
10396 refclk, NULL, &crtc_state->dpll)) {
10397 drm_err(&dev_priv->drm,
10398 "Couldn't find PLL settings for mode!\n");
10402 ilk_compute_dpll(crtc, crtc_state, NULL);
10404 if (!intel_reserve_shared_dplls(state, crtc, NULL)) {
10405 drm_dbg_kms(&dev_priv->drm,
10406 "failed to find PLL for pipe %c\n",
10407 pipe_name(crtc->pipe));
10414 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
10415 struct intel_link_m_n *m_n)
10417 struct drm_device *dev = crtc->base.dev;
10418 struct drm_i915_private *dev_priv = to_i915(dev);
10419 enum pipe pipe = crtc->pipe;
10421 m_n->link_m = intel_de_read(dev_priv, PCH_TRANS_LINK_M1(pipe));
10422 m_n->link_n = intel_de_read(dev_priv, PCH_TRANS_LINK_N1(pipe));
10423 m_n->gmch_m = intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
10425 m_n->gmch_n = intel_de_read(dev_priv, PCH_TRANS_DATA_N1(pipe));
10426 m_n->tu = ((intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
10427 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10430 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
10431 enum transcoder transcoder,
10432 struct intel_link_m_n *m_n,
10433 struct intel_link_m_n *m2_n2)
10435 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10436 enum pipe pipe = crtc->pipe;
10438 if (INTEL_GEN(dev_priv) >= 5) {
10439 m_n->link_m = intel_de_read(dev_priv,
10440 PIPE_LINK_M1(transcoder));
10441 m_n->link_n = intel_de_read(dev_priv,
10442 PIPE_LINK_N1(transcoder));
10443 m_n->gmch_m = intel_de_read(dev_priv,
10444 PIPE_DATA_M1(transcoder))
10446 m_n->gmch_n = intel_de_read(dev_priv,
10447 PIPE_DATA_N1(transcoder));
10448 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M1(transcoder))
10449 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10451 if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
10452 m2_n2->link_m = intel_de_read(dev_priv,
10453 PIPE_LINK_M2(transcoder));
10454 m2_n2->link_n = intel_de_read(dev_priv,
10455 PIPE_LINK_N2(transcoder));
10456 m2_n2->gmch_m = intel_de_read(dev_priv,
10457 PIPE_DATA_M2(transcoder))
10459 m2_n2->gmch_n = intel_de_read(dev_priv,
10460 PIPE_DATA_N2(transcoder));
10461 m2_n2->tu = ((intel_de_read(dev_priv, PIPE_DATA_M2(transcoder))
10462 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10465 m_n->link_m = intel_de_read(dev_priv, PIPE_LINK_M_G4X(pipe));
10466 m_n->link_n = intel_de_read(dev_priv, PIPE_LINK_N_G4X(pipe));
10467 m_n->gmch_m = intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
10469 m_n->gmch_n = intel_de_read(dev_priv, PIPE_DATA_N_G4X(pipe));
10470 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
10471 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10475 void intel_dp_get_m_n(struct intel_crtc *crtc,
10476 struct intel_crtc_state *pipe_config)
10478 if (pipe_config->has_pch_encoder)
10479 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
10481 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
10482 &pipe_config->dp_m_n,
10483 &pipe_config->dp_m2_n2);
10486 static void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
10487 struct intel_crtc_state *pipe_config)
10489 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
10490 &pipe_config->fdi_m_n, NULL);
10493 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state,
10496 drm_rect_init(&crtc_state->pch_pfit.dst,
10497 pos >> 16, pos & 0xffff,
10498 size >> 16, size & 0xffff);
10501 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state)
10503 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10504 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10505 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
10509 /* find scaler attached to this pipe */
10510 for (i = 0; i < crtc->num_scalers; i++) {
10511 u32 ctl, pos, size;
10513 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
10514 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)
10518 crtc_state->pch_pfit.enabled = true;
10520 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i));
10521 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
10523 ilk_get_pfit_pos_size(crtc_state, pos, size);
10525 scaler_state->scalers[i].in_use = true;
10529 scaler_state->scaler_id = id;
10531 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
10533 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
10537 skl_get_initial_plane_config(struct intel_crtc *crtc,
10538 struct intel_initial_plane_config *plane_config)
10540 struct drm_device *dev = crtc->base.dev;
10541 struct drm_i915_private *dev_priv = to_i915(dev);
10542 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
10543 enum plane_id plane_id = plane->id;
10545 u32 val, base, offset, stride_mult, tiling, alpha;
10546 int fourcc, pixel_format;
10547 unsigned int aligned_height;
10548 struct drm_framebuffer *fb;
10549 struct intel_framebuffer *intel_fb;
10551 if (!plane->get_hw_state(plane, &pipe))
10554 drm_WARN_ON(dev, pipe != crtc->pipe);
10556 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10558 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
10562 fb = &intel_fb->base;
10566 val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id));
10568 if (INTEL_GEN(dev_priv) >= 11)
10569 pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
10571 pixel_format = val & PLANE_CTL_FORMAT_MASK;
10573 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
10574 alpha = intel_de_read(dev_priv,
10575 PLANE_COLOR_CTL(pipe, plane_id));
10576 alpha &= PLANE_COLOR_ALPHA_MASK;
10578 alpha = val & PLANE_CTL_ALPHA_MASK;
10581 fourcc = skl_format_to_fourcc(pixel_format,
10582 val & PLANE_CTL_ORDER_RGBX, alpha);
10583 fb->format = drm_format_info(fourcc);
10585 tiling = val & PLANE_CTL_TILED_MASK;
10587 case PLANE_CTL_TILED_LINEAR:
10588 fb->modifier = DRM_FORMAT_MOD_LINEAR;
10590 case PLANE_CTL_TILED_X:
10591 plane_config->tiling = I915_TILING_X;
10592 fb->modifier = I915_FORMAT_MOD_X_TILED;
10594 case PLANE_CTL_TILED_Y:
10595 plane_config->tiling = I915_TILING_Y;
10596 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
10597 fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
10598 I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
10599 I915_FORMAT_MOD_Y_TILED_CCS;
10600 else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
10601 fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
10603 fb->modifier = I915_FORMAT_MOD_Y_TILED;
10605 case PLANE_CTL_TILED_YF:
10606 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
10607 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
10609 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
10612 MISSING_CASE(tiling);
10617 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
10618 * while i915 HW rotation is clockwise, thats why this swapping.
10620 switch (val & PLANE_CTL_ROTATE_MASK) {
10621 case PLANE_CTL_ROTATE_0:
10622 plane_config->rotation = DRM_MODE_ROTATE_0;
10624 case PLANE_CTL_ROTATE_90:
10625 plane_config->rotation = DRM_MODE_ROTATE_270;
10627 case PLANE_CTL_ROTATE_180:
10628 plane_config->rotation = DRM_MODE_ROTATE_180;
10630 case PLANE_CTL_ROTATE_270:
10631 plane_config->rotation = DRM_MODE_ROTATE_90;
10635 if (INTEL_GEN(dev_priv) >= 10 &&
10636 val & PLANE_CTL_FLIP_HORIZONTAL)
10637 plane_config->rotation |= DRM_MODE_REFLECT_X;
10639 /* 90/270 degree rotation would require extra work */
10640 if (drm_rotation_90_or_270(plane_config->rotation))
10643 base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xfffff000;
10644 plane_config->base = base;
10646 offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id));
10648 val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id));
10649 fb->height = ((val >> 16) & 0xffff) + 1;
10650 fb->width = ((val >> 0) & 0xffff) + 1;
10652 val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
10653 stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
10654 fb->pitches[0] = (val & 0x3ff) * stride_mult;
10656 aligned_height = intel_fb_align_height(fb, 0, fb->height);
10658 plane_config->size = fb->pitches[0] * aligned_height;
10660 drm_dbg_kms(&dev_priv->drm,
10661 "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
10662 crtc->base.name, plane->base.name, fb->width, fb->height,
10663 fb->format->cpp[0] * 8, base, fb->pitches[0],
10664 plane_config->size);
10666 plane_config->fb = intel_fb;
10673 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
10675 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10676 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10677 u32 ctl, pos, size;
10679 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
10680 if ((ctl & PF_ENABLE) == 0)
10683 crtc_state->pch_pfit.enabled = true;
10685 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
10686 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
10688 ilk_get_pfit_pos_size(crtc_state, pos, size);
10691 * We currently do not free assignements of panel fitters on
10692 * ivb/hsw (since we don't use the higher upscaling modes which
10693 * differentiates them) so just WARN about this case for now.
10695 drm_WARN_ON(&dev_priv->drm, IS_GEN(dev_priv, 7) &&
10696 (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe));
10699 static bool ilk_get_pipe_config(struct intel_crtc *crtc,
10700 struct intel_crtc_state *pipe_config)
10702 struct drm_device *dev = crtc->base.dev;
10703 struct drm_i915_private *dev_priv = to_i915(dev);
10704 enum intel_display_power_domain power_domain;
10705 intel_wakeref_t wakeref;
10709 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10710 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
10714 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10715 pipe_config->shared_dpll = NULL;
10718 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
10719 if (!(tmp & PIPECONF_ENABLE))
10722 switch (tmp & PIPECONF_BPC_MASK) {
10723 case PIPECONF_6BPC:
10724 pipe_config->pipe_bpp = 18;
10726 case PIPECONF_8BPC:
10727 pipe_config->pipe_bpp = 24;
10729 case PIPECONF_10BPC:
10730 pipe_config->pipe_bpp = 30;
10732 case PIPECONF_12BPC:
10733 pipe_config->pipe_bpp = 36;
10739 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
10740 pipe_config->limited_color_range = true;
10742 switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
10743 case PIPECONF_OUTPUT_COLORSPACE_YUV601:
10744 case PIPECONF_OUTPUT_COLORSPACE_YUV709:
10745 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
10748 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
10752 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
10753 PIPECONF_GAMMA_MODE_SHIFT;
10755 pipe_config->csc_mode = intel_de_read(dev_priv,
10756 PIPE_CSC_MODE(crtc->pipe));
10758 i9xx_get_pipe_color_config(pipe_config);
10759 intel_color_get_config(pipe_config);
10761 if (intel_de_read(dev_priv, PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
10762 struct intel_shared_dpll *pll;
10763 enum intel_dpll_id pll_id;
10765 pipe_config->has_pch_encoder = true;
10767 tmp = intel_de_read(dev_priv, FDI_RX_CTL(crtc->pipe));
10768 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10769 FDI_DP_PORT_WIDTH_SHIFT) + 1;
10771 ilk_get_fdi_m_n_config(crtc, pipe_config);
10773 if (HAS_PCH_IBX(dev_priv)) {
10775 * The pipe->pch transcoder and pch transcoder->pll
10776 * mapping is fixed.
10778 pll_id = (enum intel_dpll_id) crtc->pipe;
10780 tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
10781 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
10782 pll_id = DPLL_ID_PCH_PLL_B;
10784 pll_id= DPLL_ID_PCH_PLL_A;
10787 pipe_config->shared_dpll =
10788 intel_get_shared_dpll_by_id(dev_priv, pll_id);
10789 pll = pipe_config->shared_dpll;
10791 drm_WARN_ON(dev, !pll->info->funcs->get_hw_state(dev_priv, pll,
10792 &pipe_config->dpll_hw_state));
10794 tmp = pipe_config->dpll_hw_state.dpll;
10795 pipe_config->pixel_multiplier =
10796 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
10797 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
10799 ilk_pch_clock_get(crtc, pipe_config);
10801 pipe_config->pixel_multiplier = 1;
10804 intel_get_pipe_timings(crtc, pipe_config);
10805 intel_get_pipe_src_size(crtc, pipe_config);
10807 ilk_get_pfit_config(pipe_config);
10812 intel_display_power_put(dev_priv, power_domain, wakeref);
10817 static int hsw_crtc_compute_clock(struct intel_crtc *crtc,
10818 struct intel_crtc_state *crtc_state)
10820 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10821 struct intel_atomic_state *state =
10822 to_intel_atomic_state(crtc_state->uapi.state);
10824 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
10825 INTEL_GEN(dev_priv) >= 11) {
10826 struct intel_encoder *encoder =
10827 intel_get_crtc_new_encoder(state, crtc_state);
10829 if (!intel_reserve_shared_dplls(state, crtc, encoder)) {
10830 drm_dbg_kms(&dev_priv->drm,
10831 "failed to find PLL for pipe %c\n",
10832 pipe_name(crtc->pipe));
10840 static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10841 struct intel_crtc_state *pipe_config)
10843 enum intel_dpll_id id;
10846 temp = intel_de_read(dev_priv, DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
10847 id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
10849 if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL2))
10852 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10855 static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10856 struct intel_crtc_state *pipe_config)
10858 enum phy phy = intel_port_to_phy(dev_priv, port);
10859 enum icl_port_dpll_id port_dpll_id;
10860 enum intel_dpll_id id;
10863 if (intel_phy_is_combo(dev_priv, phy)) {
10866 if (IS_ROCKETLAKE(dev_priv)) {
10867 mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
10868 shift = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
10870 mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
10871 shift = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
10874 temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & mask;
10875 id = temp >> shift;
10876 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10877 } else if (intel_phy_is_tc(dev_priv, phy)) {
10878 u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
10880 if (clk_sel == DDI_CLK_SEL_MG) {
10881 id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
10883 port_dpll_id = ICL_PORT_DPLL_MG_PHY;
10885 drm_WARN_ON(&dev_priv->drm,
10886 clk_sel < DDI_CLK_SEL_TBT_162);
10887 id = DPLL_ID_ICL_TBTPLL;
10888 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10891 drm_WARN(&dev_priv->drm, 1, "Invalid port %x\n", port);
10895 pipe_config->icl_port_dplls[port_dpll_id].pll =
10896 intel_get_shared_dpll_by_id(dev_priv, id);
10898 icl_set_active_port_dpll(pipe_config, port_dpll_id);
10901 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10903 struct intel_crtc_state *pipe_config)
10905 enum intel_dpll_id id;
10909 id = DPLL_ID_SKL_DPLL0;
10912 id = DPLL_ID_SKL_DPLL1;
10915 id = DPLL_ID_SKL_DPLL2;
10918 drm_err(&dev_priv->drm, "Incorrect port type\n");
10922 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10925 static void skl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10926 struct intel_crtc_state *pipe_config)
10928 enum intel_dpll_id id;
10931 temp = intel_de_read(dev_priv, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10932 id = temp >> (port * 3 + 1);
10934 if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL3))
10937 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10940 static void hsw_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10941 struct intel_crtc_state *pipe_config)
10943 enum intel_dpll_id id;
10944 u32 ddi_pll_sel = intel_de_read(dev_priv, PORT_CLK_SEL(port));
10946 switch (ddi_pll_sel) {
10947 case PORT_CLK_SEL_WRPLL1:
10948 id = DPLL_ID_WRPLL1;
10950 case PORT_CLK_SEL_WRPLL2:
10951 id = DPLL_ID_WRPLL2;
10953 case PORT_CLK_SEL_SPLL:
10956 case PORT_CLK_SEL_LCPLL_810:
10957 id = DPLL_ID_LCPLL_810;
10959 case PORT_CLK_SEL_LCPLL_1350:
10960 id = DPLL_ID_LCPLL_1350;
10962 case PORT_CLK_SEL_LCPLL_2700:
10963 id = DPLL_ID_LCPLL_2700;
10966 MISSING_CASE(ddi_pll_sel);
10968 case PORT_CLK_SEL_NONE:
10972 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10975 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10976 struct intel_crtc_state *pipe_config,
10977 u64 *power_domain_mask,
10978 intel_wakeref_t *wakerefs)
10980 struct drm_device *dev = crtc->base.dev;
10981 struct drm_i915_private *dev_priv = to_i915(dev);
10982 enum intel_display_power_domain power_domain;
10983 unsigned long panel_transcoder_mask = BIT(TRANSCODER_EDP);
10984 unsigned long enabled_panel_transcoders = 0;
10985 enum transcoder panel_transcoder;
10986 intel_wakeref_t wf;
10989 if (INTEL_GEN(dev_priv) >= 11)
10990 panel_transcoder_mask |=
10991 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
10994 * The pipe->transcoder mapping is fixed with the exception of the eDP
10995 * and DSI transcoders handled below.
10997 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
11000 * XXX: Do intel_display_power_get_if_enabled before reading this (for
11001 * consistency and less surprising code; it's in always on power).
11003 for_each_cpu_transcoder_masked(dev_priv, panel_transcoder,
11004 panel_transcoder_mask) {
11005 bool force_thru = false;
11006 enum pipe trans_pipe;
11008 tmp = intel_de_read(dev_priv,
11009 TRANS_DDI_FUNC_CTL(panel_transcoder));
11010 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
11014 * Log all enabled ones, only use the first one.
11016 * FIXME: This won't work for two separate DSI displays.
11018 enabled_panel_transcoders |= BIT(panel_transcoder);
11019 if (enabled_panel_transcoders != BIT(panel_transcoder))
11022 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
11025 "unknown pipe linked to transcoder %s\n",
11026 transcoder_name(panel_transcoder));
11028 case TRANS_DDI_EDP_INPUT_A_ONOFF:
11031 case TRANS_DDI_EDP_INPUT_A_ON:
11032 trans_pipe = PIPE_A;
11034 case TRANS_DDI_EDP_INPUT_B_ONOFF:
11035 trans_pipe = PIPE_B;
11037 case TRANS_DDI_EDP_INPUT_C_ONOFF:
11038 trans_pipe = PIPE_C;
11040 case TRANS_DDI_EDP_INPUT_D_ONOFF:
11041 trans_pipe = PIPE_D;
11045 if (trans_pipe == crtc->pipe) {
11046 pipe_config->cpu_transcoder = panel_transcoder;
11047 pipe_config->pch_pfit.force_thru = force_thru;
11052 * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1
11054 drm_WARN_ON(dev, (enabled_panel_transcoders & BIT(TRANSCODER_EDP)) &&
11055 enabled_panel_transcoders != BIT(TRANSCODER_EDP));
11057 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
11058 drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain));
11060 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11064 wakerefs[power_domain] = wf;
11065 *power_domain_mask |= BIT_ULL(power_domain);
11067 tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder));
11069 return tmp & PIPECONF_ENABLE;
11072 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
11073 struct intel_crtc_state *pipe_config,
11074 u64 *power_domain_mask,
11075 intel_wakeref_t *wakerefs)
11077 struct drm_device *dev = crtc->base.dev;
11078 struct drm_i915_private *dev_priv = to_i915(dev);
11079 enum intel_display_power_domain power_domain;
11080 enum transcoder cpu_transcoder;
11081 intel_wakeref_t wf;
11085 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
11086 if (port == PORT_A)
11087 cpu_transcoder = TRANSCODER_DSI_A;
11089 cpu_transcoder = TRANSCODER_DSI_C;
11091 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
11092 drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain));
11094 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11098 wakerefs[power_domain] = wf;
11099 *power_domain_mask |= BIT_ULL(power_domain);
11102 * The PLL needs to be enabled with a valid divider
11103 * configuration, otherwise accessing DSI registers will hang
11104 * the machine. See BSpec North Display Engine
11105 * registers/MIPI[BXT]. We can break out here early, since we
11106 * need the same DSI PLL to be enabled for both DSI ports.
11108 if (!bxt_dsi_pll_is_enabled(dev_priv))
11111 /* XXX: this works for video mode only */
11112 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
11113 if (!(tmp & DPI_ENABLE))
11116 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
11117 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
11120 pipe_config->cpu_transcoder = cpu_transcoder;
11124 return transcoder_is_dsi(pipe_config->cpu_transcoder);
11127 static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
11128 struct intel_crtc_state *pipe_config)
11130 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11131 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
11132 struct intel_shared_dpll *pll;
11136 if (transcoder_is_dsi(cpu_transcoder)) {
11137 port = (cpu_transcoder == TRANSCODER_DSI_A) ?
11140 tmp = intel_de_read(dev_priv,
11141 TRANS_DDI_FUNC_CTL(cpu_transcoder));
11142 if (INTEL_GEN(dev_priv) >= 12)
11143 port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
11145 port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
11148 if (INTEL_GEN(dev_priv) >= 11)
11149 icl_get_ddi_pll(dev_priv, port, pipe_config);
11150 else if (IS_CANNONLAKE(dev_priv))
11151 cnl_get_ddi_pll(dev_priv, port, pipe_config);
11152 else if (IS_GEN9_BC(dev_priv))
11153 skl_get_ddi_pll(dev_priv, port, pipe_config);
11154 else if (IS_GEN9_LP(dev_priv))
11155 bxt_get_ddi_pll(dev_priv, port, pipe_config);
11157 hsw_get_ddi_pll(dev_priv, port, pipe_config);
11159 pll = pipe_config->shared_dpll;
11161 drm_WARN_ON(&dev_priv->drm,
11162 !pll->info->funcs->get_hw_state(dev_priv, pll,
11163 &pipe_config->dpll_hw_state));
11167 * Haswell has only FDI/PCH transcoder A. It is which is connected to
11168 * DDI E. So just check whether this pipe is wired to DDI E and whether
11169 * the PCH transcoder is on.
11171 if (INTEL_GEN(dev_priv) < 9 &&
11172 (port == PORT_E) && intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) {
11173 pipe_config->has_pch_encoder = true;
11175 tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
11176 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
11177 FDI_DP_PORT_WIDTH_SHIFT) + 1;
11179 ilk_get_fdi_m_n_config(crtc, pipe_config);
11183 static bool hsw_get_pipe_config(struct intel_crtc *crtc,
11184 struct intel_crtc_state *pipe_config)
11186 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11187 intel_wakeref_t wakerefs[POWER_DOMAIN_NUM], wf;
11188 enum intel_display_power_domain power_domain;
11189 u64 power_domain_mask;
11193 pipe_config->master_transcoder = INVALID_TRANSCODER;
11195 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
11196 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11200 wakerefs[power_domain] = wf;
11201 power_domain_mask = BIT_ULL(power_domain);
11203 pipe_config->shared_dpll = NULL;
11205 active = hsw_get_transcoder_state(crtc, pipe_config,
11206 &power_domain_mask, wakerefs);
11208 if (IS_GEN9_LP(dev_priv) &&
11209 bxt_get_dsi_transcoder_state(crtc, pipe_config,
11210 &power_domain_mask, wakerefs)) {
11211 drm_WARN_ON(&dev_priv->drm, active);
11218 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
11219 INTEL_GEN(dev_priv) >= 11) {
11220 hsw_get_ddi_port_state(crtc, pipe_config);
11221 intel_get_pipe_timings(crtc, pipe_config);
11224 intel_get_pipe_src_size(crtc, pipe_config);
11226 if (IS_HASWELL(dev_priv)) {
11227 u32 tmp = intel_de_read(dev_priv,
11228 PIPECONF(pipe_config->cpu_transcoder));
11230 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
11231 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
11233 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
11235 pipe_config->output_format =
11236 bdw_get_pipemisc_output_format(crtc);
11239 * Currently there is no interface defined to
11240 * check user preference between RGB/YCBCR444
11241 * or YCBCR420. So the only possible case for
11242 * YCBCR444 usage is driving YCBCR420 output
11243 * with LSPCON, when pipe is configured for
11244 * YCBCR444 output and LSPCON takes care of
11247 pipe_config->lspcon_downsampling =
11248 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444;
11251 pipe_config->gamma_mode = intel_de_read(dev_priv,
11252 GAMMA_MODE(crtc->pipe));
11254 pipe_config->csc_mode = intel_de_read(dev_priv,
11255 PIPE_CSC_MODE(crtc->pipe));
11257 if (INTEL_GEN(dev_priv) >= 9) {
11258 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe));
11260 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
11261 pipe_config->gamma_enable = true;
11263 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
11264 pipe_config->csc_enable = true;
11266 i9xx_get_pipe_color_config(pipe_config);
11269 intel_color_get_config(pipe_config);
11271 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));
11272 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
11273 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
11274 pipe_config->ips_linetime =
11275 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
11277 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
11278 drm_WARN_ON(&dev_priv->drm, power_domain_mask & BIT_ULL(power_domain));
11280 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11282 wakerefs[power_domain] = wf;
11283 power_domain_mask |= BIT_ULL(power_domain);
11285 if (INTEL_GEN(dev_priv) >= 9)
11286 skl_get_pfit_config(pipe_config);
11288 ilk_get_pfit_config(pipe_config);
11291 if (hsw_crtc_supports_ips(crtc)) {
11292 if (IS_HASWELL(dev_priv))
11293 pipe_config->ips_enabled = intel_de_read(dev_priv,
11294 IPS_CTL) & IPS_ENABLE;
11297 * We cannot readout IPS state on broadwell, set to
11298 * true so we can set it to a defined state on first
11301 pipe_config->ips_enabled = true;
11305 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
11306 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
11307 pipe_config->pixel_multiplier =
11308 intel_de_read(dev_priv,
11309 PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
11311 pipe_config->pixel_multiplier = 1;
11315 for_each_power_domain(power_domain, power_domain_mask)
11316 intel_display_power_put(dev_priv,
11317 power_domain, wakerefs[power_domain]);
11322 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
11324 struct drm_i915_private *dev_priv =
11325 to_i915(plane_state->uapi.plane->dev);
11326 const struct drm_framebuffer *fb = plane_state->hw.fb;
11327 const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11330 if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
11331 base = sg_dma_address(obj->mm.pages->sgl);
11333 base = intel_plane_ggtt_offset(plane_state);
11335 return base + plane_state->color_plane[0].offset;
11338 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
11340 int x = plane_state->uapi.dst.x1;
11341 int y = plane_state->uapi.dst.y1;
11345 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
11348 pos |= x << CURSOR_X_SHIFT;
11351 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
11354 pos |= y << CURSOR_Y_SHIFT;
11359 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
11361 const struct drm_mode_config *config =
11362 &plane_state->uapi.plane->dev->mode_config;
11363 int width = drm_rect_width(&plane_state->uapi.dst);
11364 int height = drm_rect_height(&plane_state->uapi.dst);
11366 return width > 0 && width <= config->cursor_width &&
11367 height > 0 && height <= config->cursor_height;
11370 static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
11372 struct drm_i915_private *dev_priv =
11373 to_i915(plane_state->uapi.plane->dev);
11374 unsigned int rotation = plane_state->hw.rotation;
11379 ret = intel_plane_compute_gtt(plane_state);
11383 if (!plane_state->uapi.visible)
11386 src_x = plane_state->uapi.src.x1 >> 16;
11387 src_y = plane_state->uapi.src.y1 >> 16;
11389 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
11390 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
11393 if (src_x != 0 || src_y != 0) {
11394 drm_dbg_kms(&dev_priv->drm,
11395 "Arbitrary cursor panning not supported\n");
11400 * Put the final coordinates back so that the src
11401 * coordinate checks will see the right values.
11403 drm_rect_translate_to(&plane_state->uapi.src,
11404 src_x << 16, src_y << 16);
11406 /* ILK+ do this automagically in hardware */
11407 if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) {
11408 const struct drm_framebuffer *fb = plane_state->hw.fb;
11409 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
11410 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
11412 offset += (src_h * src_w - 1) * fb->format->cpp[0];
11415 plane_state->color_plane[0].offset = offset;
11416 plane_state->color_plane[0].x = src_x;
11417 plane_state->color_plane[0].y = src_y;
11422 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
11423 struct intel_plane_state *plane_state)
11425 const struct drm_framebuffer *fb = plane_state->hw.fb;
11426 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
11429 if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
11430 drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n");
11434 ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
11436 DRM_PLANE_HELPER_NO_SCALING,
11437 DRM_PLANE_HELPER_NO_SCALING,
11442 /* Use the unclipped src/dst rectangles, which we program to hw */
11443 plane_state->uapi.src = drm_plane_state_src(&plane_state->uapi);
11444 plane_state->uapi.dst = drm_plane_state_dest(&plane_state->uapi);
11446 ret = intel_cursor_check_surface(plane_state);
11450 if (!plane_state->uapi.visible)
11453 ret = intel_plane_check_src_coordinates(plane_state);
11460 static unsigned int
11461 i845_cursor_max_stride(struct intel_plane *plane,
11462 u32 pixel_format, u64 modifier,
11463 unsigned int rotation)
11468 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
11472 if (crtc_state->gamma_enable)
11473 cntl |= CURSOR_GAMMA_ENABLE;
11478 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
11479 const struct intel_plane_state *plane_state)
11481 return CURSOR_ENABLE |
11482 CURSOR_FORMAT_ARGB |
11483 CURSOR_STRIDE(plane_state->color_plane[0].stride);
11486 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
11488 int width = drm_rect_width(&plane_state->uapi.dst);
11491 * 845g/865g are only limited by the width of their cursors,
11492 * the height is arbitrary up to the precision of the register.
11494 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
11497 static int i845_check_cursor(struct intel_crtc_state *crtc_state,
11498 struct intel_plane_state *plane_state)
11500 const struct drm_framebuffer *fb = plane_state->hw.fb;
11501 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
11504 ret = intel_check_cursor(crtc_state, plane_state);
11508 /* if we want to turn off the cursor ignore width and height */
11512 /* Check for which cursor types we support */
11513 if (!i845_cursor_size_ok(plane_state)) {
11514 drm_dbg_kms(&i915->drm,
11515 "Cursor dimension %dx%d not supported\n",
11516 drm_rect_width(&plane_state->uapi.dst),
11517 drm_rect_height(&plane_state->uapi.dst));
11521 drm_WARN_ON(&i915->drm, plane_state->uapi.visible &&
11522 plane_state->color_plane[0].stride != fb->pitches[0]);
11524 switch (fb->pitches[0]) {
11531 drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n",
11536 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
11541 static void i845_update_cursor(struct intel_plane *plane,
11542 const struct intel_crtc_state *crtc_state,
11543 const struct intel_plane_state *plane_state)
11545 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11546 u32 cntl = 0, base = 0, pos = 0, size = 0;
11547 unsigned long irqflags;
11549 if (plane_state && plane_state->uapi.visible) {
11550 unsigned int width = drm_rect_width(&plane_state->uapi.dst);
11551 unsigned int height = drm_rect_height(&plane_state->uapi.dst);
11553 cntl = plane_state->ctl |
11554 i845_cursor_ctl_crtc(crtc_state);
11556 size = (height << 12) | width;
11558 base = intel_cursor_base(plane_state);
11559 pos = intel_cursor_position(plane_state);
11562 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11564 /* On these chipsets we can only modify the base/size/stride
11565 * whilst the cursor is disabled.
11567 if (plane->cursor.base != base ||
11568 plane->cursor.size != size ||
11569 plane->cursor.cntl != cntl) {
11570 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0);
11571 intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base);
11572 intel_de_write_fw(dev_priv, CURSIZE, size);
11573 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
11574 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl);
11576 plane->cursor.base = base;
11577 plane->cursor.size = size;
11578 plane->cursor.cntl = cntl;
11580 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
11583 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11586 static void i845_disable_cursor(struct intel_plane *plane,
11587 const struct intel_crtc_state *crtc_state)
11589 i845_update_cursor(plane, crtc_state, NULL);
11592 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
11595 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11596 enum intel_display_power_domain power_domain;
11597 intel_wakeref_t wakeref;
11600 power_domain = POWER_DOMAIN_PIPE(PIPE_A);
11601 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11605 ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE;
11609 intel_display_power_put(dev_priv, power_domain, wakeref);
11614 static unsigned int
11615 i9xx_cursor_max_stride(struct intel_plane *plane,
11616 u32 pixel_format, u64 modifier,
11617 unsigned int rotation)
11619 return plane->base.dev->mode_config.cursor_width * 4;
11622 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
11624 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
11625 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11628 if (INTEL_GEN(dev_priv) >= 11)
11631 if (crtc_state->gamma_enable)
11632 cntl = MCURSOR_GAMMA_ENABLE;
11634 if (crtc_state->csc_enable)
11635 cntl |= MCURSOR_PIPE_CSC_ENABLE;
11637 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11638 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
11643 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
11644 const struct intel_plane_state *plane_state)
11646 struct drm_i915_private *dev_priv =
11647 to_i915(plane_state->uapi.plane->dev);
11650 if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
11651 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
11653 switch (drm_rect_width(&plane_state->uapi.dst)) {
11655 cntl |= MCURSOR_MODE_64_ARGB_AX;
11658 cntl |= MCURSOR_MODE_128_ARGB_AX;
11661 cntl |= MCURSOR_MODE_256_ARGB_AX;
11664 MISSING_CASE(drm_rect_width(&plane_state->uapi.dst));
11668 if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)
11669 cntl |= MCURSOR_ROTATE_180;
11674 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
11676 struct drm_i915_private *dev_priv =
11677 to_i915(plane_state->uapi.plane->dev);
11678 int width = drm_rect_width(&plane_state->uapi.dst);
11679 int height = drm_rect_height(&plane_state->uapi.dst);
11681 if (!intel_cursor_size_ok(plane_state))
11684 /* Cursor width is limited to a few power-of-two sizes */
11695 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
11696 * height from 8 lines up to the cursor width, when the
11697 * cursor is not rotated. Everything else requires square
11700 if (HAS_CUR_FBC(dev_priv) &&
11701 plane_state->hw.rotation & DRM_MODE_ROTATE_0) {
11702 if (height < 8 || height > width)
11705 if (height != width)
11712 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
11713 struct intel_plane_state *plane_state)
11715 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
11716 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11717 const struct drm_framebuffer *fb = plane_state->hw.fb;
11718 enum pipe pipe = plane->pipe;
11721 ret = intel_check_cursor(crtc_state, plane_state);
11725 /* if we want to turn off the cursor ignore width and height */
11729 /* Check for which cursor types we support */
11730 if (!i9xx_cursor_size_ok(plane_state)) {
11731 drm_dbg(&dev_priv->drm,
11732 "Cursor dimension %dx%d not supported\n",
11733 drm_rect_width(&plane_state->uapi.dst),
11734 drm_rect_height(&plane_state->uapi.dst));
11738 drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible &&
11739 plane_state->color_plane[0].stride != fb->pitches[0]);
11741 if (fb->pitches[0] !=
11742 drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) {
11743 drm_dbg_kms(&dev_priv->drm,
11744 "Invalid cursor stride (%u) (cursor width %d)\n",
11746 drm_rect_width(&plane_state->uapi.dst));
11751 * There's something wrong with the cursor on CHV pipe C.
11752 * If it straddles the left edge of the screen then
11753 * moving it away from the edge or disabling it often
11754 * results in a pipe underrun, and often that can lead to
11755 * dead pipe (constant underrun reported, and it scans
11756 * out just a solid color). To recover from that, the
11757 * display power well must be turned off and on again.
11758 * Refuse the put the cursor into that compromised position.
11760 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
11761 plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) {
11762 drm_dbg_kms(&dev_priv->drm,
11763 "CHV cursor C not allowed to straddle the left screen edge\n");
11767 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
11772 static void i9xx_update_cursor(struct intel_plane *plane,
11773 const struct intel_crtc_state *crtc_state,
11774 const struct intel_plane_state *plane_state)
11776 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11777 enum pipe pipe = plane->pipe;
11778 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
11779 unsigned long irqflags;
11781 if (plane_state && plane_state->uapi.visible) {
11782 unsigned width = drm_rect_width(&plane_state->uapi.dst);
11783 unsigned height = drm_rect_height(&plane_state->uapi.dst);
11785 cntl = plane_state->ctl |
11786 i9xx_cursor_ctl_crtc(crtc_state);
11788 if (width != height)
11789 fbc_ctl = CUR_FBC_CTL_EN | (height - 1);
11791 base = intel_cursor_base(plane_state);
11792 pos = intel_cursor_position(plane_state);
11795 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11798 * On some platforms writing CURCNTR first will also
11799 * cause CURPOS to be armed by the CURBASE write.
11800 * Without the CURCNTR write the CURPOS write would
11801 * arm itself. Thus we always update CURCNTR before
11804 * On other platforms CURPOS always requires the
11805 * CURBASE write to arm the update. Additonally
11806 * a write to any of the cursor register will cancel
11807 * an already armed cursor update. Thus leaving out
11808 * the CURBASE write after CURPOS could lead to a
11809 * cursor that doesn't appear to move, or even change
11810 * shape. Thus we always write CURBASE.
11812 * The other registers are armed by by the CURBASE write
11813 * except when the plane is getting enabled at which time
11814 * the CURCNTR write arms the update.
11817 if (INTEL_GEN(dev_priv) >= 9)
11818 skl_write_cursor_wm(plane, crtc_state);
11820 if (plane->cursor.base != base ||
11821 plane->cursor.size != fbc_ctl ||
11822 plane->cursor.cntl != cntl) {
11823 if (HAS_CUR_FBC(dev_priv))
11824 intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe),
11826 intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl);
11827 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
11828 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
11830 plane->cursor.base = base;
11831 plane->cursor.size = fbc_ctl;
11832 plane->cursor.cntl = cntl;
11834 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
11835 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
11838 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11841 static void i9xx_disable_cursor(struct intel_plane *plane,
11842 const struct intel_crtc_state *crtc_state)
11844 i9xx_update_cursor(plane, crtc_state, NULL);
11847 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
11850 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11851 enum intel_display_power_domain power_domain;
11852 intel_wakeref_t wakeref;
11857 * Not 100% correct for planes that can move between pipes,
11858 * but that's only the case for gen2-3 which don't have any
11859 * display power wells.
11861 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
11862 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11866 val = intel_de_read(dev_priv, CURCNTR(plane->pipe));
11868 ret = val & MCURSOR_MODE;
11870 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
11871 *pipe = plane->pipe;
11873 *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
11874 MCURSOR_PIPE_SELECT_SHIFT;
11876 intel_display_power_put(dev_priv, power_domain, wakeref);
11881 /* VESA 640x480x72Hz mode to set on the pipe */
11882 static const struct drm_display_mode load_detect_mode = {
11883 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
11884 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
11887 struct drm_framebuffer *
11888 intel_framebuffer_create(struct drm_i915_gem_object *obj,
11889 struct drm_mode_fb_cmd2 *mode_cmd)
11891 struct intel_framebuffer *intel_fb;
11894 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
11896 return ERR_PTR(-ENOMEM);
11898 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
11902 return &intel_fb->base;
11906 return ERR_PTR(ret);
11909 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
11910 struct drm_crtc *crtc)
11912 struct drm_plane *plane;
11913 struct drm_plane_state *plane_state;
11916 ret = drm_atomic_add_affected_planes(state, crtc);
11920 for_each_new_plane_in_state(state, plane, plane_state, i) {
11921 if (plane_state->crtc != crtc)
11924 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
11928 drm_atomic_set_fb_for_plane(plane_state, NULL);
11934 int intel_get_load_detect_pipe(struct drm_connector *connector,
11935 struct intel_load_detect_pipe *old,
11936 struct drm_modeset_acquire_ctx *ctx)
11938 struct intel_crtc *intel_crtc;
11939 struct intel_encoder *intel_encoder =
11940 intel_attached_encoder(to_intel_connector(connector));
11941 struct drm_crtc *possible_crtc;
11942 struct drm_encoder *encoder = &intel_encoder->base;
11943 struct drm_crtc *crtc = NULL;
11944 struct drm_device *dev = encoder->dev;
11945 struct drm_i915_private *dev_priv = to_i915(dev);
11946 struct drm_mode_config *config = &dev->mode_config;
11947 struct drm_atomic_state *state = NULL, *restore_state = NULL;
11948 struct drm_connector_state *connector_state;
11949 struct intel_crtc_state *crtc_state;
11952 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11953 connector->base.id, connector->name,
11954 encoder->base.id, encoder->name);
11956 old->restore_state = NULL;
11958 drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex));
11961 * Algorithm gets a little messy:
11963 * - if the connector already has an assigned crtc, use it (but make
11964 * sure it's on first)
11966 * - try to find the first unused crtc that can drive this connector,
11967 * and use that if we find one
11970 /* See if we already have a CRTC for this connector */
11971 if (connector->state->crtc) {
11972 crtc = connector->state->crtc;
11974 ret = drm_modeset_lock(&crtc->mutex, ctx);
11978 /* Make sure the crtc and connector are running */
11982 /* Find an unused one (if possible) */
11983 for_each_crtc(dev, possible_crtc) {
11985 if (!(encoder->possible_crtcs & (1 << i)))
11988 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11992 if (possible_crtc->state->enable) {
11993 drm_modeset_unlock(&possible_crtc->mutex);
11997 crtc = possible_crtc;
12002 * If we didn't find an unused CRTC, don't use any.
12005 drm_dbg_kms(&dev_priv->drm,
12006 "no pipe available for load-detect\n");
12012 intel_crtc = to_intel_crtc(crtc);
12014 state = drm_atomic_state_alloc(dev);
12015 restore_state = drm_atomic_state_alloc(dev);
12016 if (!state || !restore_state) {
12021 state->acquire_ctx = ctx;
12022 restore_state->acquire_ctx = ctx;
12024 connector_state = drm_atomic_get_connector_state(state, connector);
12025 if (IS_ERR(connector_state)) {
12026 ret = PTR_ERR(connector_state);
12030 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
12034 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
12035 if (IS_ERR(crtc_state)) {
12036 ret = PTR_ERR(crtc_state);
12040 crtc_state->uapi.active = true;
12042 ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi,
12043 &load_detect_mode);
12047 ret = intel_modeset_disable_planes(state, crtc);
12051 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
12053 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
12055 ret = drm_atomic_add_affected_planes(restore_state, crtc);
12057 drm_dbg_kms(&dev_priv->drm,
12058 "Failed to create a copy of old state to restore: %i\n",
12063 ret = drm_atomic_commit(state);
12065 drm_dbg_kms(&dev_priv->drm,
12066 "failed to set mode on load-detect pipe\n");
12070 old->restore_state = restore_state;
12071 drm_atomic_state_put(state);
12073 /* let the connector get through one full cycle before testing */
12074 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
12079 drm_atomic_state_put(state);
12082 if (restore_state) {
12083 drm_atomic_state_put(restore_state);
12084 restore_state = NULL;
12087 if (ret == -EDEADLK)
12093 void intel_release_load_detect_pipe(struct drm_connector *connector,
12094 struct intel_load_detect_pipe *old,
12095 struct drm_modeset_acquire_ctx *ctx)
12097 struct intel_encoder *intel_encoder =
12098 intel_attached_encoder(to_intel_connector(connector));
12099 struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev);
12100 struct drm_encoder *encoder = &intel_encoder->base;
12101 struct drm_atomic_state *state = old->restore_state;
12104 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
12105 connector->base.id, connector->name,
12106 encoder->base.id, encoder->name);
12111 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
12113 drm_dbg_kms(&i915->drm,
12114 "Couldn't release load detect pipe: %i\n", ret);
12115 drm_atomic_state_put(state);
12118 static int i9xx_pll_refclk(struct drm_device *dev,
12119 const struct intel_crtc_state *pipe_config)
12121 struct drm_i915_private *dev_priv = to_i915(dev);
12122 u32 dpll = pipe_config->dpll_hw_state.dpll;
12124 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
12125 return dev_priv->vbt.lvds_ssc_freq;
12126 else if (HAS_PCH_SPLIT(dev_priv))
12128 else if (!IS_GEN(dev_priv, 2))
12134 /* Returns the clock of the currently programmed mode of the given pipe. */
12135 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
12136 struct intel_crtc_state *pipe_config)
12138 struct drm_device *dev = crtc->base.dev;
12139 struct drm_i915_private *dev_priv = to_i915(dev);
12140 enum pipe pipe = crtc->pipe;
12141 u32 dpll = pipe_config->dpll_hw_state.dpll;
12145 int refclk = i9xx_pll_refclk(dev, pipe_config);
12147 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
12148 fp = pipe_config->dpll_hw_state.fp0;
12150 fp = pipe_config->dpll_hw_state.fp1;
12152 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
12153 if (IS_PINEVIEW(dev_priv)) {
12154 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
12155 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
12157 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
12158 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
12161 if (!IS_GEN(dev_priv, 2)) {
12162 if (IS_PINEVIEW(dev_priv))
12163 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
12164 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
12166 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
12167 DPLL_FPA01_P1_POST_DIV_SHIFT);
12169 switch (dpll & DPLL_MODE_MASK) {
12170 case DPLLB_MODE_DAC_SERIAL:
12171 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
12174 case DPLLB_MODE_LVDS:
12175 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
12179 drm_dbg_kms(&dev_priv->drm,
12180 "Unknown DPLL mode %08x in programmed "
12181 "mode\n", (int)(dpll & DPLL_MODE_MASK));
12185 if (IS_PINEVIEW(dev_priv))
12186 port_clock = pnv_calc_dpll_params(refclk, &clock);
12188 port_clock = i9xx_calc_dpll_params(refclk, &clock);
12190 u32 lvds = IS_I830(dev_priv) ? 0 : intel_de_read(dev_priv,
12192 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
12195 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
12196 DPLL_FPA01_P1_POST_DIV_SHIFT);
12198 if (lvds & LVDS_CLKB_POWER_UP)
12203 if (dpll & PLL_P1_DIVIDE_BY_TWO)
12206 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
12207 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
12209 if (dpll & PLL_P2_DIVIDE_BY_4)
12215 port_clock = i9xx_calc_dpll_params(refclk, &clock);
12219 * This value includes pixel_multiplier. We will use
12220 * port_clock to compute adjusted_mode.crtc_clock in the
12221 * encoder's get_config() function.
12223 pipe_config->port_clock = port_clock;
12226 int intel_dotclock_calculate(int link_freq,
12227 const struct intel_link_m_n *m_n)
12230 * The calculation for the data clock is:
12231 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
12232 * But we want to avoid losing precison if possible, so:
12233 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
12235 * and the link clock is simpler:
12236 * link_clock = (m * link_clock) / n
12242 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
12245 static void ilk_pch_clock_get(struct intel_crtc *crtc,
12246 struct intel_crtc_state *pipe_config)
12248 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12250 /* read out port_clock from the DPLL */
12251 i9xx_crtc_clock_get(crtc, pipe_config);
12254 * In case there is an active pipe without active ports,
12255 * we may need some idea for the dotclock anyway.
12256 * Calculate one based on the FDI configuration.
12258 pipe_config->hw.adjusted_mode.crtc_clock =
12259 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12260 &pipe_config->fdi_m_n);
12263 static void intel_crtc_state_reset(struct intel_crtc_state *crtc_state,
12264 struct intel_crtc *crtc)
12266 memset(crtc_state, 0, sizeof(*crtc_state));
12268 __drm_atomic_helper_crtc_state_reset(&crtc_state->uapi, &crtc->base);
12270 crtc_state->cpu_transcoder = INVALID_TRANSCODER;
12271 crtc_state->master_transcoder = INVALID_TRANSCODER;
12272 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
12273 crtc_state->output_format = INTEL_OUTPUT_FORMAT_INVALID;
12274 crtc_state->scaler_state.scaler_id = -1;
12275 crtc_state->mst_master_transcoder = INVALID_TRANSCODER;
12278 static struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc)
12280 struct intel_crtc_state *crtc_state;
12282 crtc_state = kmalloc(sizeof(*crtc_state), GFP_KERNEL);
12285 intel_crtc_state_reset(crtc_state, crtc);
12290 /* Returns the currently programmed mode of the given encoder. */
12291 struct drm_display_mode *
12292 intel_encoder_current_mode(struct intel_encoder *encoder)
12294 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
12295 struct intel_crtc_state *crtc_state;
12296 struct drm_display_mode *mode;
12297 struct intel_crtc *crtc;
12300 if (!encoder->get_hw_state(encoder, &pipe))
12303 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12305 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
12309 crtc_state = intel_crtc_state_alloc(crtc);
12315 if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
12321 encoder->get_config(encoder, crtc_state);
12323 intel_mode_from_pipe_config(mode, crtc_state);
12330 static void intel_crtc_destroy(struct drm_crtc *crtc)
12332 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12334 drm_crtc_cleanup(crtc);
12339 * intel_wm_need_update - Check whether watermarks need updating
12340 * @cur: current plane state
12341 * @new: new plane state
12343 * Check current plane state versus the new one to determine whether
12344 * watermarks need to be recalculated.
12346 * Returns true or false.
12348 static bool intel_wm_need_update(const struct intel_plane_state *cur,
12349 struct intel_plane_state *new)
12351 /* Update watermarks on tiling or size changes. */
12352 if (new->uapi.visible != cur->uapi.visible)
12355 if (!cur->hw.fb || !new->hw.fb)
12358 if (cur->hw.fb->modifier != new->hw.fb->modifier ||
12359 cur->hw.rotation != new->hw.rotation ||
12360 drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
12361 drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
12362 drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
12363 drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
12369 static bool needs_scaling(const struct intel_plane_state *state)
12371 int src_w = drm_rect_width(&state->uapi.src) >> 16;
12372 int src_h = drm_rect_height(&state->uapi.src) >> 16;
12373 int dst_w = drm_rect_width(&state->uapi.dst);
12374 int dst_h = drm_rect_height(&state->uapi.dst);
12376 return (src_w != dst_w || src_h != dst_h);
12379 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
12380 struct intel_crtc_state *crtc_state,
12381 const struct intel_plane_state *old_plane_state,
12382 struct intel_plane_state *plane_state)
12384 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12385 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
12386 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12387 bool mode_changed = needs_modeset(crtc_state);
12388 bool was_crtc_enabled = old_crtc_state->hw.active;
12389 bool is_crtc_enabled = crtc_state->hw.active;
12390 bool turn_off, turn_on, visible, was_visible;
12393 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
12394 ret = skl_update_scaler_plane(crtc_state, plane_state);
12399 was_visible = old_plane_state->uapi.visible;
12400 visible = plane_state->uapi.visible;
12402 if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible))
12403 was_visible = false;
12406 * Visibility is calculated as if the crtc was on, but
12407 * after scaler setup everything depends on it being off
12408 * when the crtc isn't active.
12410 * FIXME this is wrong for watermarks. Watermarks should also
12411 * be computed as if the pipe would be active. Perhaps move
12412 * per-plane wm computation to the .check_plane() hook, and
12413 * only combine the results from all planes in the current place?
12415 if (!is_crtc_enabled) {
12416 intel_plane_set_invisible(crtc_state, plane_state);
12420 if (!was_visible && !visible)
12423 turn_off = was_visible && (!visible || mode_changed);
12424 turn_on = visible && (!was_visible || mode_changed);
12426 drm_dbg_atomic(&dev_priv->drm,
12427 "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12428 crtc->base.base.id, crtc->base.name,
12429 plane->base.base.id, plane->base.name,
12430 was_visible, visible,
12431 turn_off, turn_on, mode_changed);
12434 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
12435 crtc_state->update_wm_pre = true;
12437 /* must disable cxsr around plane enable/disable */
12438 if (plane->id != PLANE_CURSOR)
12439 crtc_state->disable_cxsr = true;
12440 } else if (turn_off) {
12441 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
12442 crtc_state->update_wm_post = true;
12444 /* must disable cxsr around plane enable/disable */
12445 if (plane->id != PLANE_CURSOR)
12446 crtc_state->disable_cxsr = true;
12447 } else if (intel_wm_need_update(old_plane_state, plane_state)) {
12448 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
12449 /* FIXME bollocks */
12450 crtc_state->update_wm_pre = true;
12451 crtc_state->update_wm_post = true;
12455 if (visible || was_visible)
12456 crtc_state->fb_bits |= plane->frontbuffer_bit;
12459 * ILK/SNB DVSACNTR/Sprite Enable
12460 * IVB SPR_CTL/Sprite Enable
12461 * "When in Self Refresh Big FIFO mode, a write to enable the
12462 * plane will be internally buffered and delayed while Big FIFO
12463 * mode is exiting."
12465 * Which means that enabling the sprite can take an extra frame
12466 * when we start in big FIFO mode (LP1+). Thus we need to drop
12467 * down to LP0 and wait for vblank in order to make sure the
12468 * sprite gets enabled on the next vblank after the register write.
12469 * Doing otherwise would risk enabling the sprite one frame after
12470 * we've already signalled flip completion. We can resume LP1+
12471 * once the sprite has been enabled.
12474 * WaCxSRDisabledForSpriteScaling:ivb
12475 * IVB SPR_SCALE/Scaling Enable
12476 * "Low Power watermarks must be disabled for at least one
12477 * frame before enabling sprite scaling, and kept disabled
12478 * until sprite scaling is disabled."
12480 * ILK/SNB DVSASCALE/Scaling Enable
12481 * "When in Self Refresh Big FIFO mode, scaling enable will be
12482 * masked off while Big FIFO mode is exiting."
12484 * Despite the w/a only being listed for IVB we assume that
12485 * the ILK/SNB note has similar ramifications, hence we apply
12486 * the w/a on all three platforms.
12488 * With experimental results seems this is needed also for primary
12489 * plane, not only sprite plane.
12491 if (plane->id != PLANE_CURSOR &&
12492 (IS_GEN_RANGE(dev_priv, 5, 6) ||
12493 IS_IVYBRIDGE(dev_priv)) &&
12494 (turn_on || (!needs_scaling(old_plane_state) &&
12495 needs_scaling(plane_state))))
12496 crtc_state->disable_lp_wm = true;
12501 static bool encoders_cloneable(const struct intel_encoder *a,
12502 const struct intel_encoder *b)
12504 /* masks could be asymmetric, so check both ways */
12505 return a == b || (a->cloneable & (1 << b->type) &&
12506 b->cloneable & (1 << a->type));
12509 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12510 struct intel_crtc *crtc,
12511 struct intel_encoder *encoder)
12513 struct intel_encoder *source_encoder;
12514 struct drm_connector *connector;
12515 struct drm_connector_state *connector_state;
12518 for_each_new_connector_in_state(state, connector, connector_state, i) {
12519 if (connector_state->crtc != &crtc->base)
12523 to_intel_encoder(connector_state->best_encoder);
12524 if (!encoders_cloneable(encoder, source_encoder))
12531 static int icl_add_linked_planes(struct intel_atomic_state *state)
12533 struct intel_plane *plane, *linked;
12534 struct intel_plane_state *plane_state, *linked_plane_state;
12537 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12538 linked = plane_state->planar_linked_plane;
12543 linked_plane_state = intel_atomic_get_plane_state(state, linked);
12544 if (IS_ERR(linked_plane_state))
12545 return PTR_ERR(linked_plane_state);
12547 drm_WARN_ON(state->base.dev,
12548 linked_plane_state->planar_linked_plane != plane);
12549 drm_WARN_ON(state->base.dev,
12550 linked_plane_state->planar_slave == plane_state->planar_slave);
12556 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
12558 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12559 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12560 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
12561 struct intel_plane *plane, *linked;
12562 struct intel_plane_state *plane_state;
12565 if (INTEL_GEN(dev_priv) < 11)
12569 * Destroy all old plane links and make the slave plane invisible
12570 * in the crtc_state->active_planes mask.
12572 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12573 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
12576 plane_state->planar_linked_plane = NULL;
12577 if (plane_state->planar_slave && !plane_state->uapi.visible) {
12578 crtc_state->active_planes &= ~BIT(plane->id);
12579 crtc_state->update_planes |= BIT(plane->id);
12582 plane_state->planar_slave = false;
12585 if (!crtc_state->nv12_planes)
12588 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12589 struct intel_plane_state *linked_state = NULL;
12591 if (plane->pipe != crtc->pipe ||
12592 !(crtc_state->nv12_planes & BIT(plane->id)))
12595 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
12596 if (!icl_is_nv12_y_plane(dev_priv, linked->id))
12599 if (crtc_state->active_planes & BIT(linked->id))
12602 linked_state = intel_atomic_get_plane_state(state, linked);
12603 if (IS_ERR(linked_state))
12604 return PTR_ERR(linked_state);
12609 if (!linked_state) {
12610 drm_dbg_kms(&dev_priv->drm,
12611 "Need %d free Y planes for planar YUV\n",
12612 hweight8(crtc_state->nv12_planes));
12617 plane_state->planar_linked_plane = linked;
12619 linked_state->planar_slave = true;
12620 linked_state->planar_linked_plane = plane;
12621 crtc_state->active_planes |= BIT(linked->id);
12622 crtc_state->update_planes |= BIT(linked->id);
12623 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
12624 linked->base.name, plane->base.name);
12626 /* Copy parameters to slave plane */
12627 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
12628 linked_state->color_ctl = plane_state->color_ctl;
12629 linked_state->view = plane_state->view;
12630 memcpy(linked_state->color_plane, plane_state->color_plane,
12631 sizeof(linked_state->color_plane));
12633 intel_plane_copy_uapi_to_hw_state(linked_state, plane_state);
12634 linked_state->uapi.src = plane_state->uapi.src;
12635 linked_state->uapi.dst = plane_state->uapi.dst;
12637 if (icl_is_hdr_plane(dev_priv, plane->id)) {
12638 if (linked->id == PLANE_SPRITE5)
12639 plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
12640 else if (linked->id == PLANE_SPRITE4)
12641 plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
12642 else if (linked->id == PLANE_SPRITE3)
12643 plane_state->cus_ctl |= PLANE_CUS_PLANE_5_RKL;
12644 else if (linked->id == PLANE_SPRITE2)
12645 plane_state->cus_ctl |= PLANE_CUS_PLANE_4_RKL;
12647 MISSING_CASE(linked->id);
12654 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
12656 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
12657 struct intel_atomic_state *state =
12658 to_intel_atomic_state(new_crtc_state->uapi.state);
12659 const struct intel_crtc_state *old_crtc_state =
12660 intel_atomic_get_old_crtc_state(state, crtc);
12662 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
12665 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
12667 const struct drm_display_mode *adjusted_mode =
12668 &crtc_state->hw.adjusted_mode;
12671 if (!crtc_state->hw.enable)
12674 linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
12675 adjusted_mode->crtc_clock);
12677 return min(linetime_wm, 0x1ff);
12680 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
12681 const struct intel_cdclk_state *cdclk_state)
12683 const struct drm_display_mode *adjusted_mode =
12684 &crtc_state->hw.adjusted_mode;
12687 if (!crtc_state->hw.enable)
12690 linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
12691 cdclk_state->logical.cdclk);
12693 return min(linetime_wm, 0x1ff);
12696 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
12698 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12699 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12700 const struct drm_display_mode *adjusted_mode =
12701 &crtc_state->hw.adjusted_mode;
12704 if (!crtc_state->hw.enable)
12707 linetime_wm = DIV_ROUND_UP(adjusted_mode->crtc_htotal * 1000 * 8,
12708 crtc_state->pixel_rate);
12710 /* Display WA #1135: BXT:ALL GLK:ALL */
12711 if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled)
12714 return min(linetime_wm, 0x1ff);
12717 static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
12718 struct intel_crtc *crtc)
12720 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12721 struct intel_crtc_state *crtc_state =
12722 intel_atomic_get_new_crtc_state(state, crtc);
12723 const struct intel_cdclk_state *cdclk_state;
12725 if (INTEL_GEN(dev_priv) >= 9)
12726 crtc_state->linetime = skl_linetime_wm(crtc_state);
12728 crtc_state->linetime = hsw_linetime_wm(crtc_state);
12730 if (!hsw_crtc_supports_ips(crtc))
12733 cdclk_state = intel_atomic_get_cdclk_state(state);
12734 if (IS_ERR(cdclk_state))
12735 return PTR_ERR(cdclk_state);
12737 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
12743 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
12744 struct intel_crtc *crtc)
12746 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12747 struct intel_crtc_state *crtc_state =
12748 intel_atomic_get_new_crtc_state(state, crtc);
12749 bool mode_changed = needs_modeset(crtc_state);
12752 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
12753 mode_changed && !crtc_state->hw.active)
12754 crtc_state->update_wm_post = true;
12756 if (mode_changed && crtc_state->hw.enable &&
12757 dev_priv->display.crtc_compute_clock &&
12758 !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
12759 ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
12765 * May need to update pipe gamma enable bits
12766 * when C8 planes are getting enabled/disabled.
12768 if (c8_planes_changed(crtc_state))
12769 crtc_state->uapi.color_mgmt_changed = true;
12771 if (mode_changed || crtc_state->update_pipe ||
12772 crtc_state->uapi.color_mgmt_changed) {
12773 ret = intel_color_check(crtc_state);
12778 if (dev_priv->display.compute_pipe_wm) {
12779 ret = dev_priv->display.compute_pipe_wm(crtc_state);
12781 drm_dbg_kms(&dev_priv->drm,
12782 "Target pipe watermarks are invalid\n");
12787 if (dev_priv->display.compute_intermediate_wm) {
12788 if (drm_WARN_ON(&dev_priv->drm,
12789 !dev_priv->display.compute_pipe_wm))
12793 * Calculate 'intermediate' watermarks that satisfy both the
12794 * old state and the new state. We can program these
12797 ret = dev_priv->display.compute_intermediate_wm(crtc_state);
12799 drm_dbg_kms(&dev_priv->drm,
12800 "No valid intermediate pipe watermarks are possible\n");
12805 if (INTEL_GEN(dev_priv) >= 9) {
12806 if (mode_changed || crtc_state->update_pipe) {
12807 ret = skl_update_scaler_crtc(crtc_state);
12812 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state);
12817 if (HAS_IPS(dev_priv)) {
12818 ret = hsw_compute_ips_config(crtc_state);
12823 if (INTEL_GEN(dev_priv) >= 9 ||
12824 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
12825 ret = hsw_compute_linetime_wm(state, crtc);
12832 intel_psr2_sel_fetch_update(state, crtc);
12837 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12839 struct intel_connector *connector;
12840 struct drm_connector_list_iter conn_iter;
12842 drm_connector_list_iter_begin(dev, &conn_iter);
12843 for_each_intel_connector_iter(connector, &conn_iter) {
12844 if (connector->base.state->crtc)
12845 drm_connector_put(&connector->base);
12847 if (connector->base.encoder) {
12848 connector->base.state->best_encoder =
12849 connector->base.encoder;
12850 connector->base.state->crtc =
12851 connector->base.encoder->crtc;
12853 drm_connector_get(&connector->base);
12855 connector->base.state->best_encoder = NULL;
12856 connector->base.state->crtc = NULL;
12859 drm_connector_list_iter_end(&conn_iter);
12863 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
12864 struct intel_crtc_state *pipe_config)
12866 struct drm_connector *connector = conn_state->connector;
12867 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
12868 const struct drm_display_info *info = &connector->display_info;
12871 switch (conn_state->max_bpc) {
12888 if (bpp < pipe_config->pipe_bpp) {
12889 drm_dbg_kms(&i915->drm,
12890 "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
12891 "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
12892 connector->base.id, connector->name,
12893 bpp, 3 * info->bpc,
12894 3 * conn_state->max_requested_bpc,
12895 pipe_config->pipe_bpp);
12897 pipe_config->pipe_bpp = bpp;
12904 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12905 struct intel_crtc_state *pipe_config)
12907 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12908 struct drm_atomic_state *state = pipe_config->uapi.state;
12909 struct drm_connector *connector;
12910 struct drm_connector_state *connector_state;
12913 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
12914 IS_CHERRYVIEW(dev_priv)))
12916 else if (INTEL_GEN(dev_priv) >= 5)
12921 pipe_config->pipe_bpp = bpp;
12923 /* Clamp display bpp to connector max bpp */
12924 for_each_new_connector_in_state(state, connector, connector_state, i) {
12927 if (connector_state->crtc != &crtc->base)
12930 ret = compute_sink_pipe_bpp(connector_state, pipe_config);
12938 static void intel_dump_crtc_timings(struct drm_i915_private *i915,
12939 const struct drm_display_mode *mode)
12941 drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, "
12942 "type: 0x%x flags: 0x%x\n",
12944 mode->crtc_hdisplay, mode->crtc_hsync_start,
12945 mode->crtc_hsync_end, mode->crtc_htotal,
12946 mode->crtc_vdisplay, mode->crtc_vsync_start,
12947 mode->crtc_vsync_end, mode->crtc_vtotal,
12948 mode->type, mode->flags);
12952 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
12953 const char *id, unsigned int lane_count,
12954 const struct intel_link_m_n *m_n)
12956 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
12958 drm_dbg_kms(&i915->drm,
12959 "%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12961 m_n->gmch_m, m_n->gmch_n,
12962 m_n->link_m, m_n->link_n, m_n->tu);
12966 intel_dump_infoframe(struct drm_i915_private *dev_priv,
12967 const union hdmi_infoframe *frame)
12969 if (!drm_debug_enabled(DRM_UT_KMS))
12972 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
12976 intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
12977 const struct drm_dp_vsc_sdp *vsc)
12979 if (!drm_debug_enabled(DRM_UT_KMS))
12982 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
12985 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
12987 static const char * const output_type_str[] = {
12988 OUTPUT_TYPE(UNUSED),
12989 OUTPUT_TYPE(ANALOG),
12993 OUTPUT_TYPE(TVOUT),
12999 OUTPUT_TYPE(DP_MST),
13004 static void snprintf_output_types(char *buf, size_t len,
13005 unsigned int output_types)
13012 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
13015 if ((output_types & BIT(i)) == 0)
13018 r = snprintf(str, len, "%s%s",
13019 str != buf ? "," : "", output_type_str[i]);
13025 output_types &= ~BIT(i);
13028 WARN_ON_ONCE(output_types != 0);
13031 static const char * const output_format_str[] = {
13032 [INTEL_OUTPUT_FORMAT_INVALID] = "Invalid",
13033 [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
13034 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
13035 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
13038 static const char *output_formats(enum intel_output_format format)
13040 if (format >= ARRAY_SIZE(output_format_str))
13041 format = INTEL_OUTPUT_FORMAT_INVALID;
13042 return output_format_str[format];
13045 static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
13047 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
13048 struct drm_i915_private *i915 = to_i915(plane->base.dev);
13049 const struct drm_framebuffer *fb = plane_state->hw.fb;
13050 struct drm_format_name_buf format_name;
13053 drm_dbg_kms(&i915->drm,
13054 "[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
13055 plane->base.base.id, plane->base.name,
13056 yesno(plane_state->uapi.visible));
13060 drm_dbg_kms(&i915->drm,
13061 "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s, visible: %s\n",
13062 plane->base.base.id, plane->base.name,
13063 fb->base.id, fb->width, fb->height,
13064 drm_get_format_name(fb->format->format, &format_name),
13065 yesno(plane_state->uapi.visible));
13066 drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n",
13067 plane_state->hw.rotation, plane_state->scaler_id);
13068 if (plane_state->uapi.visible)
13069 drm_dbg_kms(&i915->drm,
13070 "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
13071 DRM_RECT_FP_ARG(&plane_state->uapi.src),
13072 DRM_RECT_ARG(&plane_state->uapi.dst));
13075 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
13076 struct intel_atomic_state *state,
13077 const char *context)
13079 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
13080 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13081 const struct intel_plane_state *plane_state;
13082 struct intel_plane *plane;
13086 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n",
13087 crtc->base.base.id, crtc->base.name,
13088 yesno(pipe_config->hw.enable), context);
13090 if (!pipe_config->hw.enable)
13093 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
13094 drm_dbg_kms(&dev_priv->drm,
13095 "active: %s, output_types: %s (0x%x), output format: %s\n",
13096 yesno(pipe_config->hw.active),
13097 buf, pipe_config->output_types,
13098 output_formats(pipe_config->output_format));
13100 drm_dbg_kms(&dev_priv->drm,
13101 "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
13102 transcoder_name(pipe_config->cpu_transcoder),
13103 pipe_config->pipe_bpp, pipe_config->dither);
13105 drm_dbg_kms(&dev_priv->drm,
13106 "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n",
13107 transcoder_name(pipe_config->master_transcoder),
13108 pipe_config->sync_mode_slaves_mask);
13110 if (pipe_config->has_pch_encoder)
13111 intel_dump_m_n_config(pipe_config, "fdi",
13112 pipe_config->fdi_lanes,
13113 &pipe_config->fdi_m_n);
13115 if (intel_crtc_has_dp_encoder(pipe_config)) {
13116 intel_dump_m_n_config(pipe_config, "dp m_n",
13117 pipe_config->lane_count, &pipe_config->dp_m_n);
13118 if (pipe_config->has_drrs)
13119 intel_dump_m_n_config(pipe_config, "dp m2_n2",
13120 pipe_config->lane_count,
13121 &pipe_config->dp_m2_n2);
13124 drm_dbg_kms(&dev_priv->drm,
13125 "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
13126 pipe_config->has_audio, pipe_config->has_infoframe,
13127 pipe_config->infoframes.enable);
13129 if (pipe_config->infoframes.enable &
13130 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
13131 drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n",
13132 pipe_config->infoframes.gcp);
13133 if (pipe_config->infoframes.enable &
13134 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
13135 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
13136 if (pipe_config->infoframes.enable &
13137 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
13138 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
13139 if (pipe_config->infoframes.enable &
13140 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
13141 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
13142 if (pipe_config->infoframes.enable &
13143 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
13144 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
13145 if (pipe_config->infoframes.enable &
13146 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
13147 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
13148 if (pipe_config->infoframes.enable &
13149 intel_hdmi_infoframe_enable(DP_SDP_VSC))
13150 intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
13152 drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
13153 drm_mode_debug_printmodeline(&pipe_config->hw.mode);
13154 drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n");
13155 drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
13156 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode);
13157 drm_dbg_kms(&dev_priv->drm,
13158 "port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
13159 pipe_config->port_clock,
13160 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
13161 pipe_config->pixel_rate);
13163 drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n",
13164 pipe_config->linetime, pipe_config->ips_linetime);
13166 if (INTEL_GEN(dev_priv) >= 9)
13167 drm_dbg_kms(&dev_priv->drm,
13168 "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
13170 pipe_config->scaler_state.scaler_users,
13171 pipe_config->scaler_state.scaler_id);
13173 if (HAS_GMCH(dev_priv))
13174 drm_dbg_kms(&dev_priv->drm,
13175 "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
13176 pipe_config->gmch_pfit.control,
13177 pipe_config->gmch_pfit.pgm_ratios,
13178 pipe_config->gmch_pfit.lvds_border_bits);
13180 drm_dbg_kms(&dev_priv->drm,
13181 "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
13182 DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
13183 enableddisabled(pipe_config->pch_pfit.enabled),
13184 yesno(pipe_config->pch_pfit.force_thru));
13186 drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i\n",
13187 pipe_config->ips_enabled, pipe_config->double_wide);
13189 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
13191 if (IS_CHERRYVIEW(dev_priv))
13192 drm_dbg_kms(&dev_priv->drm,
13193 "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
13194 pipe_config->cgm_mode, pipe_config->gamma_mode,
13195 pipe_config->gamma_enable, pipe_config->csc_enable);
13197 drm_dbg_kms(&dev_priv->drm,
13198 "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
13199 pipe_config->csc_mode, pipe_config->gamma_mode,
13200 pipe_config->gamma_enable, pipe_config->csc_enable);
13202 drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n",
13203 transcoder_name(pipe_config->mst_master_transcoder));
13209 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
13210 if (plane->pipe == crtc->pipe)
13211 intel_dump_plane_state(plane_state);
13215 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
13217 struct drm_device *dev = state->base.dev;
13218 struct drm_connector *connector;
13219 struct drm_connector_list_iter conn_iter;
13220 unsigned int used_ports = 0;
13221 unsigned int used_mst_ports = 0;
13225 * We're going to peek into connector->state,
13226 * hence connection_mutex must be held.
13228 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
13231 * Walk the connector list instead of the encoder
13232 * list to detect the problem on ddi platforms
13233 * where there's just one encoder per digital port.
13235 drm_connector_list_iter_begin(dev, &conn_iter);
13236 drm_for_each_connector_iter(connector, &conn_iter) {
13237 struct drm_connector_state *connector_state;
13238 struct intel_encoder *encoder;
13241 drm_atomic_get_new_connector_state(&state->base,
13243 if (!connector_state)
13244 connector_state = connector->state;
13246 if (!connector_state->best_encoder)
13249 encoder = to_intel_encoder(connector_state->best_encoder);
13251 drm_WARN_ON(dev, !connector_state->crtc);
13253 switch (encoder->type) {
13254 case INTEL_OUTPUT_DDI:
13255 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev))))
13258 case INTEL_OUTPUT_DP:
13259 case INTEL_OUTPUT_HDMI:
13260 case INTEL_OUTPUT_EDP:
13261 /* the same port mustn't appear more than once */
13262 if (used_ports & BIT(encoder->port))
13265 used_ports |= BIT(encoder->port);
13267 case INTEL_OUTPUT_DP_MST:
13269 1 << encoder->port;
13275 drm_connector_list_iter_end(&conn_iter);
13277 /* can't mix MST and SST/HDMI on the same port */
13278 if (used_ports & used_mst_ports)
13285 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_crtc_state *crtc_state)
13287 intel_crtc_copy_color_blobs(crtc_state);
13291 intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
13293 crtc_state->hw.enable = crtc_state->uapi.enable;
13294 crtc_state->hw.active = crtc_state->uapi.active;
13295 crtc_state->hw.mode = crtc_state->uapi.mode;
13296 crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
13297 intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
13300 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
13302 crtc_state->uapi.enable = crtc_state->hw.enable;
13303 crtc_state->uapi.active = crtc_state->hw.active;
13304 drm_WARN_ON(crtc_state->uapi.crtc->dev,
13305 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
13307 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
13309 /* copy color blobs to uapi */
13310 drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
13311 crtc_state->hw.degamma_lut);
13312 drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
13313 crtc_state->hw.gamma_lut);
13314 drm_property_replace_blob(&crtc_state->uapi.ctm,
13315 crtc_state->hw.ctm);
13319 intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
13321 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
13322 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13323 struct intel_crtc_state *saved_state;
13325 saved_state = intel_crtc_state_alloc(crtc);
13329 /* free the old crtc_state->hw members */
13330 intel_crtc_free_hw_state(crtc_state);
13332 /* FIXME: before the switch to atomic started, a new pipe_config was
13333 * kzalloc'd. Code that depends on any field being zero should be
13334 * fixed, so that the crtc_state can be safely duplicated. For now,
13335 * only fields that are know to not cause problems are preserved. */
13337 saved_state->uapi = crtc_state->uapi;
13338 saved_state->scaler_state = crtc_state->scaler_state;
13339 saved_state->shared_dpll = crtc_state->shared_dpll;
13340 saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
13341 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
13342 sizeof(saved_state->icl_port_dplls));
13343 saved_state->crc_enabled = crtc_state->crc_enabled;
13344 if (IS_G4X(dev_priv) ||
13345 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13346 saved_state->wm = crtc_state->wm;
13348 memcpy(crtc_state, saved_state, sizeof(*crtc_state));
13349 kfree(saved_state);
13351 intel_crtc_copy_uapi_to_hw_state(crtc_state);
13357 intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
13359 struct drm_crtc *crtc = pipe_config->uapi.crtc;
13360 struct drm_atomic_state *state = pipe_config->uapi.state;
13361 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
13362 struct drm_connector *connector;
13363 struct drm_connector_state *connector_state;
13364 int base_bpp, ret, i;
13367 pipe_config->cpu_transcoder =
13368 (enum transcoder) to_intel_crtc(crtc)->pipe;
13371 * Sanitize sync polarity flags based on requested ones. If neither
13372 * positive or negative polarity is requested, treat this as meaning
13373 * negative polarity.
13375 if (!(pipe_config->hw.adjusted_mode.flags &
13376 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
13377 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
13379 if (!(pipe_config->hw.adjusted_mode.flags &
13380 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
13381 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
13383 ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
13388 base_bpp = pipe_config->pipe_bpp;
13391 * Determine the real pipe dimensions. Note that stereo modes can
13392 * increase the actual pipe size due to the frame doubling and
13393 * insertion of additional space for blanks between the frame. This
13394 * is stored in the crtc timings. We use the requested mode to do this
13395 * computation to clearly distinguish it from the adjusted mode, which
13396 * can be changed by the connectors in the below retry loop.
13398 drm_mode_get_hv_timing(&pipe_config->hw.mode,
13399 &pipe_config->pipe_src_w,
13400 &pipe_config->pipe_src_h);
13402 for_each_new_connector_in_state(state, connector, connector_state, i) {
13403 struct intel_encoder *encoder =
13404 to_intel_encoder(connector_state->best_encoder);
13406 if (connector_state->crtc != crtc)
13409 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
13410 drm_dbg_kms(&i915->drm,
13411 "rejecting invalid cloning configuration\n");
13416 * Determine output_types before calling the .compute_config()
13417 * hooks so that the hooks can use this information safely.
13419 if (encoder->compute_output_type)
13420 pipe_config->output_types |=
13421 BIT(encoder->compute_output_type(encoder, pipe_config,
13424 pipe_config->output_types |= BIT(encoder->type);
13428 /* Ensure the port clock defaults are reset when retrying. */
13429 pipe_config->port_clock = 0;
13430 pipe_config->pixel_multiplier = 1;
13432 /* Fill in default crtc timings, allow encoders to overwrite them. */
13433 drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,
13434 CRTC_STEREO_DOUBLE);
13436 /* Pass our mode to the connectors and the CRTC to give them a chance to
13437 * adjust it according to limitations or connector properties, and also
13438 * a chance to reject the mode entirely.
13440 for_each_new_connector_in_state(state, connector, connector_state, i) {
13441 struct intel_encoder *encoder =
13442 to_intel_encoder(connector_state->best_encoder);
13444 if (connector_state->crtc != crtc)
13447 ret = encoder->compute_config(encoder, pipe_config,
13450 if (ret != -EDEADLK)
13451 drm_dbg_kms(&i915->drm,
13452 "Encoder config failure: %d\n",
13458 /* Set default port clock if not overwritten by the encoder. Needs to be
13459 * done afterwards in case the encoder adjusts the mode. */
13460 if (!pipe_config->port_clock)
13461 pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
13462 * pipe_config->pixel_multiplier;
13464 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
13465 if (ret == -EDEADLK)
13468 drm_dbg_kms(&i915->drm, "CRTC fixup failed\n");
13472 if (ret == RETRY) {
13473 if (drm_WARN(&i915->drm, !retry,
13474 "loop in pipe configuration computation\n"))
13477 drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n");
13479 goto encoder_retry;
13482 /* Dithering seems to not pass-through bits correctly when it should, so
13483 * only enable it on 6bpc panels and when its not a compliance
13484 * test requesting 6bpc video pattern.
13486 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
13487 !pipe_config->dither_force_disable;
13488 drm_dbg_kms(&i915->drm,
13489 "hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
13490 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
13496 intel_modeset_pipe_config_late(struct intel_crtc_state *crtc_state)
13498 struct intel_atomic_state *state =
13499 to_intel_atomic_state(crtc_state->uapi.state);
13500 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
13501 struct drm_connector_state *conn_state;
13502 struct drm_connector *connector;
13505 for_each_new_connector_in_state(&state->base, connector,
13507 struct intel_encoder *encoder =
13508 to_intel_encoder(conn_state->best_encoder);
13511 if (conn_state->crtc != &crtc->base ||
13512 !encoder->compute_config_late)
13515 ret = encoder->compute_config_late(encoder, crtc_state,
13524 bool intel_fuzzy_clock_check(int clock1, int clock2)
13528 if (clock1 == clock2)
13531 if (!clock1 || !clock2)
13534 diff = abs(clock1 - clock2);
13536 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
13543 intel_compare_m_n(unsigned int m, unsigned int n,
13544 unsigned int m2, unsigned int n2,
13547 if (m == m2 && n == n2)
13550 if (exact || !m || !n || !m2 || !n2)
13553 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
13560 } else if (n < n2) {
13570 return intel_fuzzy_clock_check(m, m2);
13574 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
13575 const struct intel_link_m_n *m2_n2,
13578 return m_n->tu == m2_n2->tu &&
13579 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
13580 m2_n2->gmch_m, m2_n2->gmch_n, exact) &&
13581 intel_compare_m_n(m_n->link_m, m_n->link_n,
13582 m2_n2->link_m, m2_n2->link_n, exact);
13586 intel_compare_infoframe(const union hdmi_infoframe *a,
13587 const union hdmi_infoframe *b)
13589 return memcmp(a, b, sizeof(*a)) == 0;
13593 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
13594 const struct drm_dp_vsc_sdp *b)
13596 return memcmp(a, b, sizeof(*a)) == 0;
13600 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
13601 bool fastset, const char *name,
13602 const union hdmi_infoframe *a,
13603 const union hdmi_infoframe *b)
13606 if (!drm_debug_enabled(DRM_UT_KMS))
13609 drm_dbg_kms(&dev_priv->drm,
13610 "fastset mismatch in %s infoframe\n", name);
13611 drm_dbg_kms(&dev_priv->drm, "expected:\n");
13612 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
13613 drm_dbg_kms(&dev_priv->drm, "found:\n");
13614 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
13616 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name);
13617 drm_err(&dev_priv->drm, "expected:\n");
13618 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
13619 drm_err(&dev_priv->drm, "found:\n");
13620 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
13625 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
13626 bool fastset, const char *name,
13627 const struct drm_dp_vsc_sdp *a,
13628 const struct drm_dp_vsc_sdp *b)
13631 if (!drm_debug_enabled(DRM_UT_KMS))
13634 drm_dbg_kms(&dev_priv->drm,
13635 "fastset mismatch in %s dp sdp\n", name);
13636 drm_dbg_kms(&dev_priv->drm, "expected:\n");
13637 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
13638 drm_dbg_kms(&dev_priv->drm, "found:\n");
13639 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
13641 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name);
13642 drm_err(&dev_priv->drm, "expected:\n");
13643 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
13644 drm_err(&dev_priv->drm, "found:\n");
13645 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
13649 static void __printf(4, 5)
13650 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
13651 const char *name, const char *format, ...)
13653 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
13654 struct va_format vaf;
13657 va_start(args, format);
13662 drm_dbg_kms(&i915->drm,
13663 "[CRTC:%d:%s] fastset mismatch in %s %pV\n",
13664 crtc->base.base.id, crtc->base.name, name, &vaf);
13666 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n",
13667 crtc->base.base.id, crtc->base.name, name, &vaf);
13672 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
13674 if (dev_priv->params.fastboot != -1)
13675 return dev_priv->params.fastboot;
13677 /* Enable fastboot by default on Skylake and newer */
13678 if (INTEL_GEN(dev_priv) >= 9)
13681 /* Enable fastboot by default on VLV and CHV */
13682 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13685 /* Disabled by default on all others */
13690 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
13691 const struct intel_crtc_state *pipe_config,
13694 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
13695 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
13698 bool fixup_inherited = fastset &&
13699 current_config->inherited && !pipe_config->inherited;
13701 if (fixup_inherited && !fastboot_enabled(dev_priv)) {
13702 drm_dbg_kms(&dev_priv->drm,
13703 "initial modeset and fastboot not set\n");
13707 #define PIPE_CONF_CHECK_X(name) do { \
13708 if (current_config->name != pipe_config->name) { \
13709 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13710 "(expected 0x%08x, found 0x%08x)", \
13711 current_config->name, \
13712 pipe_config->name); \
13717 #define PIPE_CONF_CHECK_I(name) do { \
13718 if (current_config->name != pipe_config->name) { \
13719 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13720 "(expected %i, found %i)", \
13721 current_config->name, \
13722 pipe_config->name); \
13727 #define PIPE_CONF_CHECK_BOOL(name) do { \
13728 if (current_config->name != pipe_config->name) { \
13729 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13730 "(expected %s, found %s)", \
13731 yesno(current_config->name), \
13732 yesno(pipe_config->name)); \
13738 * Checks state where we only read out the enabling, but not the entire
13739 * state itself (like full infoframes or ELD for audio). These states
13740 * require a full modeset on bootup to fix up.
13742 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
13743 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
13744 PIPE_CONF_CHECK_BOOL(name); \
13746 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13747 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
13748 yesno(current_config->name), \
13749 yesno(pipe_config->name)); \
13754 #define PIPE_CONF_CHECK_P(name) do { \
13755 if (current_config->name != pipe_config->name) { \
13756 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13757 "(expected %p, found %p)", \
13758 current_config->name, \
13759 pipe_config->name); \
13764 #define PIPE_CONF_CHECK_M_N(name) do { \
13765 if (!intel_compare_link_m_n(¤t_config->name, \
13766 &pipe_config->name,\
13768 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13769 "(expected tu %i gmch %i/%i link %i/%i, " \
13770 "found tu %i, gmch %i/%i link %i/%i)", \
13771 current_config->name.tu, \
13772 current_config->name.gmch_m, \
13773 current_config->name.gmch_n, \
13774 current_config->name.link_m, \
13775 current_config->name.link_n, \
13776 pipe_config->name.tu, \
13777 pipe_config->name.gmch_m, \
13778 pipe_config->name.gmch_n, \
13779 pipe_config->name.link_m, \
13780 pipe_config->name.link_n); \
13785 /* This is required for BDW+ where there is only one set of registers for
13786 * switching between high and low RR.
13787 * This macro can be used whenever a comparison has to be made between one
13788 * hw state and multiple sw state variables.
13790 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
13791 if (!intel_compare_link_m_n(¤t_config->name, \
13792 &pipe_config->name, !fastset) && \
13793 !intel_compare_link_m_n(¤t_config->alt_name, \
13794 &pipe_config->name, !fastset)) { \
13795 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13796 "(expected tu %i gmch %i/%i link %i/%i, " \
13797 "or tu %i gmch %i/%i link %i/%i, " \
13798 "found tu %i, gmch %i/%i link %i/%i)", \
13799 current_config->name.tu, \
13800 current_config->name.gmch_m, \
13801 current_config->name.gmch_n, \
13802 current_config->name.link_m, \
13803 current_config->name.link_n, \
13804 current_config->alt_name.tu, \
13805 current_config->alt_name.gmch_m, \
13806 current_config->alt_name.gmch_n, \
13807 current_config->alt_name.link_m, \
13808 current_config->alt_name.link_n, \
13809 pipe_config->name.tu, \
13810 pipe_config->name.gmch_m, \
13811 pipe_config->name.gmch_n, \
13812 pipe_config->name.link_m, \
13813 pipe_config->name.link_n); \
13818 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
13819 if ((current_config->name ^ pipe_config->name) & (mask)) { \
13820 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13821 "(%x) (expected %i, found %i)", \
13823 current_config->name & (mask), \
13824 pipe_config->name & (mask)); \
13829 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
13830 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13831 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13832 "(expected %i, found %i)", \
13833 current_config->name, \
13834 pipe_config->name); \
13839 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
13840 if (!intel_compare_infoframe(¤t_config->infoframes.name, \
13841 &pipe_config->infoframes.name)) { \
13842 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
13843 ¤t_config->infoframes.name, \
13844 &pipe_config->infoframes.name); \
13849 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
13850 if (!current_config->has_psr && !pipe_config->has_psr && \
13851 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \
13852 &pipe_config->infoframes.name)) { \
13853 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
13854 ¤t_config->infoframes.name, \
13855 &pipe_config->infoframes.name); \
13860 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
13861 if (current_config->name1 != pipe_config->name1) { \
13862 pipe_config_mismatch(fastset, crtc, __stringify(name1), \
13863 "(expected %i, found %i, won't compare lut values)", \
13864 current_config->name1, \
13865 pipe_config->name1); \
13868 if (!intel_color_lut_equal(current_config->name2, \
13869 pipe_config->name2, pipe_config->name1, \
13870 bit_precision)) { \
13871 pipe_config_mismatch(fastset, crtc, __stringify(name2), \
13872 "hw_state doesn't match sw_state"); \
13878 #define PIPE_CONF_QUIRK(quirk) \
13879 ((current_config->quirks | pipe_config->quirks) & (quirk))
13881 PIPE_CONF_CHECK_I(cpu_transcoder);
13883 PIPE_CONF_CHECK_BOOL(has_pch_encoder);
13884 PIPE_CONF_CHECK_I(fdi_lanes);
13885 PIPE_CONF_CHECK_M_N(fdi_m_n);
13887 PIPE_CONF_CHECK_I(lane_count);
13888 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13890 if (INTEL_GEN(dev_priv) < 8) {
13891 PIPE_CONF_CHECK_M_N(dp_m_n);
13893 if (current_config->has_drrs)
13894 PIPE_CONF_CHECK_M_N(dp_m2_n2);
13896 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13898 PIPE_CONF_CHECK_X(output_types);
13900 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
13901 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
13902 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
13903 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
13904 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
13905 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
13907 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
13908 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
13909 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
13910 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
13911 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
13912 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
13914 PIPE_CONF_CHECK_I(pixel_multiplier);
13915 PIPE_CONF_CHECK_I(output_format);
13916 PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
13917 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
13918 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13919 PIPE_CONF_CHECK_BOOL(limited_color_range);
13921 PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
13922 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
13923 PIPE_CONF_CHECK_BOOL(has_infoframe);
13924 PIPE_CONF_CHECK_BOOL(fec_enable);
13926 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
13928 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13929 DRM_MODE_FLAG_INTERLACE);
13931 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13932 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13933 DRM_MODE_FLAG_PHSYNC);
13934 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13935 DRM_MODE_FLAG_NHSYNC);
13936 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13937 DRM_MODE_FLAG_PVSYNC);
13938 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13939 DRM_MODE_FLAG_NVSYNC);
13942 PIPE_CONF_CHECK_X(gmch_pfit.control);
13943 /* pfit ratios are autocomputed by the hw on gen4+ */
13944 if (INTEL_GEN(dev_priv) < 4)
13945 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13946 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13949 * Changing the EDP transcoder input mux
13950 * (A_ONOFF vs. A_ON) requires a full modeset.
13952 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
13955 PIPE_CONF_CHECK_I(pipe_src_w);
13956 PIPE_CONF_CHECK_I(pipe_src_h);
13958 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
13959 if (current_config->pch_pfit.enabled) {
13960 PIPE_CONF_CHECK_I(pch_pfit.dst.x1);
13961 PIPE_CONF_CHECK_I(pch_pfit.dst.y1);
13962 PIPE_CONF_CHECK_I(pch_pfit.dst.x2);
13963 PIPE_CONF_CHECK_I(pch_pfit.dst.y2);
13966 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13967 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
13969 PIPE_CONF_CHECK_X(gamma_mode);
13970 if (IS_CHERRYVIEW(dev_priv))
13971 PIPE_CONF_CHECK_X(cgm_mode);
13973 PIPE_CONF_CHECK_X(csc_mode);
13974 PIPE_CONF_CHECK_BOOL(gamma_enable);
13975 PIPE_CONF_CHECK_BOOL(csc_enable);
13977 PIPE_CONF_CHECK_I(linetime);
13978 PIPE_CONF_CHECK_I(ips_linetime);
13980 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
13982 PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
13985 PIPE_CONF_CHECK_BOOL(double_wide);
13987 PIPE_CONF_CHECK_P(shared_dpll);
13988 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13989 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13990 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13991 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13992 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13993 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13994 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13995 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13996 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13997 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
13998 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
13999 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
14000 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
14001 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
14002 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
14003 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
14004 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
14005 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
14006 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
14007 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
14008 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
14009 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
14010 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
14011 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
14012 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
14013 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
14014 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
14015 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
14016 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
14017 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
14018 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
14020 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
14021 PIPE_CONF_CHECK_X(dsi_pll.div);
14023 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
14024 PIPE_CONF_CHECK_I(pipe_bpp);
14026 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
14027 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
14029 PIPE_CONF_CHECK_I(min_voltage_level);
14031 PIPE_CONF_CHECK_X(infoframes.enable);
14032 PIPE_CONF_CHECK_X(infoframes.gcp);
14033 PIPE_CONF_CHECK_INFOFRAME(avi);
14034 PIPE_CONF_CHECK_INFOFRAME(spd);
14035 PIPE_CONF_CHECK_INFOFRAME(hdmi);
14036 PIPE_CONF_CHECK_INFOFRAME(drm);
14037 PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
14039 PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
14040 PIPE_CONF_CHECK_I(master_transcoder);
14042 PIPE_CONF_CHECK_I(dsc.compression_enable);
14043 PIPE_CONF_CHECK_I(dsc.dsc_split);
14044 PIPE_CONF_CHECK_I(dsc.compressed_bpp);
14046 PIPE_CONF_CHECK_I(mst_master_transcoder);
14048 #undef PIPE_CONF_CHECK_X
14049 #undef PIPE_CONF_CHECK_I
14050 #undef PIPE_CONF_CHECK_BOOL
14051 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
14052 #undef PIPE_CONF_CHECK_P
14053 #undef PIPE_CONF_CHECK_FLAGS
14054 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
14055 #undef PIPE_CONF_CHECK_COLOR_LUT
14056 #undef PIPE_CONF_QUIRK
14061 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
14062 const struct intel_crtc_state *pipe_config)
14064 if (pipe_config->has_pch_encoder) {
14065 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
14066 &pipe_config->fdi_m_n);
14067 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
14070 * FDI already provided one idea for the dotclock.
14071 * Yell if the encoder disagrees.
14073 drm_WARN(&dev_priv->drm,
14074 !intel_fuzzy_clock_check(fdi_dotclock, dotclock),
14075 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
14076 fdi_dotclock, dotclock);
14080 static void verify_wm_state(struct intel_crtc *crtc,
14081 struct intel_crtc_state *new_crtc_state)
14083 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14084 struct skl_hw_state {
14085 struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
14086 struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
14087 struct skl_pipe_wm wm;
14089 struct skl_pipe_wm *sw_wm;
14090 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
14091 u8 hw_enabled_slices;
14092 const enum pipe pipe = crtc->pipe;
14093 int plane, level, max_level = ilk_wm_max_level(dev_priv);
14095 if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active)
14098 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
14102 skl_pipe_wm_get_hw_state(crtc, &hw->wm);
14103 sw_wm = &new_crtc_state->wm.skl.optimal;
14105 skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
14107 hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
14109 if (INTEL_GEN(dev_priv) >= 11 &&
14110 hw_enabled_slices != dev_priv->dbuf.enabled_slices)
14111 drm_err(&dev_priv->drm,
14112 "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n",
14113 dev_priv->dbuf.enabled_slices,
14114 hw_enabled_slices);
14117 for_each_universal_plane(dev_priv, pipe, plane) {
14118 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
14120 hw_plane_wm = &hw->wm.planes[plane];
14121 sw_plane_wm = &sw_wm->planes[plane];
14124 for (level = 0; level <= max_level; level++) {
14125 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
14126 &sw_plane_wm->wm[level]) ||
14127 (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
14128 &sw_plane_wm->sagv_wm0)))
14131 drm_err(&dev_priv->drm,
14132 "mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14133 pipe_name(pipe), plane + 1, level,
14134 sw_plane_wm->wm[level].plane_en,
14135 sw_plane_wm->wm[level].plane_res_b,
14136 sw_plane_wm->wm[level].plane_res_l,
14137 hw_plane_wm->wm[level].plane_en,
14138 hw_plane_wm->wm[level].plane_res_b,
14139 hw_plane_wm->wm[level].plane_res_l);
14142 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
14143 &sw_plane_wm->trans_wm)) {
14144 drm_err(&dev_priv->drm,
14145 "mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14146 pipe_name(pipe), plane + 1,
14147 sw_plane_wm->trans_wm.plane_en,
14148 sw_plane_wm->trans_wm.plane_res_b,
14149 sw_plane_wm->trans_wm.plane_res_l,
14150 hw_plane_wm->trans_wm.plane_en,
14151 hw_plane_wm->trans_wm.plane_res_b,
14152 hw_plane_wm->trans_wm.plane_res_l);
14156 hw_ddb_entry = &hw->ddb_y[plane];
14157 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane];
14159 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
14160 drm_err(&dev_priv->drm,
14161 "mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
14162 pipe_name(pipe), plane + 1,
14163 sw_ddb_entry->start, sw_ddb_entry->end,
14164 hw_ddb_entry->start, hw_ddb_entry->end);
14170 * If the cursor plane isn't active, we may not have updated it's ddb
14171 * allocation. In that case since the ddb allocation will be updated
14172 * once the plane becomes visible, we can skip this check
14175 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
14177 hw_plane_wm = &hw->wm.planes[PLANE_CURSOR];
14178 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
14181 for (level = 0; level <= max_level; level++) {
14182 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
14183 &sw_plane_wm->wm[level]) ||
14184 (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
14185 &sw_plane_wm->sagv_wm0)))
14188 drm_err(&dev_priv->drm,
14189 "mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14190 pipe_name(pipe), level,
14191 sw_plane_wm->wm[level].plane_en,
14192 sw_plane_wm->wm[level].plane_res_b,
14193 sw_plane_wm->wm[level].plane_res_l,
14194 hw_plane_wm->wm[level].plane_en,
14195 hw_plane_wm->wm[level].plane_res_b,
14196 hw_plane_wm->wm[level].plane_res_l);
14199 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
14200 &sw_plane_wm->trans_wm)) {
14201 drm_err(&dev_priv->drm,
14202 "mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14204 sw_plane_wm->trans_wm.plane_en,
14205 sw_plane_wm->trans_wm.plane_res_b,
14206 sw_plane_wm->trans_wm.plane_res_l,
14207 hw_plane_wm->trans_wm.plane_en,
14208 hw_plane_wm->trans_wm.plane_res_b,
14209 hw_plane_wm->trans_wm.plane_res_l);
14213 hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR];
14214 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
14216 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
14217 drm_err(&dev_priv->drm,
14218 "mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
14220 sw_ddb_entry->start, sw_ddb_entry->end,
14221 hw_ddb_entry->start, hw_ddb_entry->end);
14229 verify_connector_state(struct intel_atomic_state *state,
14230 struct intel_crtc *crtc)
14232 struct drm_connector *connector;
14233 struct drm_connector_state *new_conn_state;
14236 for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) {
14237 struct drm_encoder *encoder = connector->encoder;
14238 struct intel_crtc_state *crtc_state = NULL;
14240 if (new_conn_state->crtc != &crtc->base)
14244 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
14246 intel_connector_verify_state(crtc_state, new_conn_state);
14248 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
14249 "connector's atomic encoder doesn't match legacy encoder\n");
14254 verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state)
14256 struct intel_encoder *encoder;
14257 struct drm_connector *connector;
14258 struct drm_connector_state *old_conn_state, *new_conn_state;
14261 for_each_intel_encoder(&dev_priv->drm, encoder) {
14262 bool enabled = false, found = false;
14265 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n",
14266 encoder->base.base.id,
14267 encoder->base.name);
14269 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,
14270 new_conn_state, i) {
14271 if (old_conn_state->best_encoder == &encoder->base)
14274 if (new_conn_state->best_encoder != &encoder->base)
14276 found = enabled = true;
14278 I915_STATE_WARN(new_conn_state->crtc !=
14279 encoder->base.crtc,
14280 "connector's crtc doesn't match encoder crtc\n");
14286 I915_STATE_WARN(!!encoder->base.crtc != enabled,
14287 "encoder's enabled state mismatch "
14288 "(expected %i, found %i)\n",
14289 !!encoder->base.crtc, enabled);
14291 if (!encoder->base.crtc) {
14294 active = encoder->get_hw_state(encoder, &pipe);
14295 I915_STATE_WARN(active,
14296 "encoder detached but still enabled on pipe %c.\n",
14303 verify_crtc_state(struct intel_crtc *crtc,
14304 struct intel_crtc_state *old_crtc_state,
14305 struct intel_crtc_state *new_crtc_state)
14307 struct drm_device *dev = crtc->base.dev;
14308 struct drm_i915_private *dev_priv = to_i915(dev);
14309 struct intel_encoder *encoder;
14310 struct intel_crtc_state *pipe_config = old_crtc_state;
14311 struct drm_atomic_state *state = old_crtc_state->uapi.state;
14313 __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
14314 intel_crtc_free_hw_state(old_crtc_state);
14315 intel_crtc_state_reset(old_crtc_state, crtc);
14316 old_crtc_state->uapi.state = state;
14318 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id,
14321 pipe_config->hw.enable = new_crtc_state->hw.enable;
14323 pipe_config->hw.active =
14324 dev_priv->display.get_pipe_config(crtc, pipe_config);
14326 /* we keep both pipes enabled on 830 */
14327 if (IS_I830(dev_priv) && pipe_config->hw.active)
14328 pipe_config->hw.active = new_crtc_state->hw.active;
14330 I915_STATE_WARN(new_crtc_state->hw.active != pipe_config->hw.active,
14331 "crtc active state doesn't match with hw state "
14332 "(expected %i, found %i)\n",
14333 new_crtc_state->hw.active, pipe_config->hw.active);
14335 I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,
14336 "transitional active state does not match atomic hw state "
14337 "(expected %i, found %i)\n",
14338 new_crtc_state->hw.active, crtc->active);
14340 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14344 active = encoder->get_hw_state(encoder, &pipe);
14345 I915_STATE_WARN(active != new_crtc_state->hw.active,
14346 "[ENCODER:%i] active %i with crtc active %i\n",
14347 encoder->base.base.id, active,
14348 new_crtc_state->hw.active);
14350 I915_STATE_WARN(active && crtc->pipe != pipe,
14351 "Encoder connected to wrong pipe %c\n",
14355 encoder->get_config(encoder, pipe_config);
14358 intel_crtc_compute_pixel_rate(pipe_config);
14360 if (!new_crtc_state->hw.active)
14363 intel_pipe_config_sanity_check(dev_priv, pipe_config);
14365 if (!intel_pipe_config_compare(new_crtc_state,
14366 pipe_config, false)) {
14367 I915_STATE_WARN(1, "pipe state doesn't match!\n");
14368 intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
14369 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
14374 intel_verify_planes(struct intel_atomic_state *state)
14376 struct intel_plane *plane;
14377 const struct intel_plane_state *plane_state;
14380 for_each_new_intel_plane_in_state(state, plane,
14382 assert_plane(plane, plane_state->planar_slave ||
14383 plane_state->uapi.visible);
14387 verify_single_dpll_state(struct drm_i915_private *dev_priv,
14388 struct intel_shared_dpll *pll,
14389 struct intel_crtc *crtc,
14390 struct intel_crtc_state *new_crtc_state)
14392 struct intel_dpll_hw_state dpll_hw_state;
14393 unsigned int crtc_mask;
14396 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
14398 drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name);
14400 active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
14402 if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
14403 I915_STATE_WARN(!pll->on && pll->active_mask,
14404 "pll in active use but not on in sw tracking\n");
14405 I915_STATE_WARN(pll->on && !pll->active_mask,
14406 "pll is on but not used by any active crtc\n");
14407 I915_STATE_WARN(pll->on != active,
14408 "pll on state mismatch (expected %i, found %i)\n",
14413 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
14414 "more active pll users than references: %x vs %x\n",
14415 pll->active_mask, pll->state.crtc_mask);
14420 crtc_mask = drm_crtc_mask(&crtc->base);
14422 if (new_crtc_state->hw.active)
14423 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
14424 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
14425 pipe_name(crtc->pipe), pll->active_mask);
14427 I915_STATE_WARN(pll->active_mask & crtc_mask,
14428 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
14429 pipe_name(crtc->pipe), pll->active_mask);
14431 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
14432 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
14433 crtc_mask, pll->state.crtc_mask);
14435 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
14437 sizeof(dpll_hw_state)),
14438 "pll hw state mismatch\n");
14442 verify_shared_dpll_state(struct intel_crtc *crtc,
14443 struct intel_crtc_state *old_crtc_state,
14444 struct intel_crtc_state *new_crtc_state)
14446 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14448 if (new_crtc_state->shared_dpll)
14449 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state);
14451 if (old_crtc_state->shared_dpll &&
14452 old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
14453 unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
14454 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
14456 I915_STATE_WARN(pll->active_mask & crtc_mask,
14457 "pll active mismatch (didn't expect pipe %c in active mask)\n",
14458 pipe_name(crtc->pipe));
14459 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
14460 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
14461 pipe_name(crtc->pipe));
14466 intel_modeset_verify_crtc(struct intel_crtc *crtc,
14467 struct intel_atomic_state *state,
14468 struct intel_crtc_state *old_crtc_state,
14469 struct intel_crtc_state *new_crtc_state)
14471 if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
14474 verify_wm_state(crtc, new_crtc_state);
14475 verify_connector_state(state, crtc);
14476 verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
14477 verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
14481 verify_disabled_dpll_state(struct drm_i915_private *dev_priv)
14485 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++)
14486 verify_single_dpll_state(dev_priv,
14487 &dev_priv->dpll.shared_dplls[i],
14492 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
14493 struct intel_atomic_state *state)
14495 verify_encoder_state(dev_priv, state);
14496 verify_connector_state(state, NULL);
14497 verify_disabled_dpll_state(dev_priv);
14501 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
14503 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
14504 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14505 const struct drm_display_mode *adjusted_mode =
14506 &crtc_state->hw.adjusted_mode;
14508 drm_calc_timestamping_constants(&crtc->base, adjusted_mode);
14510 crtc->mode_flags = crtc_state->mode_flags;
14513 * The scanline counter increments at the leading edge of hsync.
14515 * On most platforms it starts counting from vtotal-1 on the
14516 * first active line. That means the scanline counter value is
14517 * always one less than what we would expect. Ie. just after
14518 * start of vblank, which also occurs at start of hsync (on the
14519 * last active line), the scanline counter will read vblank_start-1.
14521 * On gen2 the scanline counter starts counting from 1 instead
14522 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
14523 * to keep the value positive), instead of adding one.
14525 * On HSW+ the behaviour of the scanline counter depends on the output
14526 * type. For DP ports it behaves like most other platforms, but on HDMI
14527 * there's an extra 1 line difference. So we need to add two instead of
14528 * one to the value.
14530 * On VLV/CHV DSI the scanline counter would appear to increment
14531 * approx. 1/3 of a scanline before start of vblank. Unfortunately
14532 * that means we can't tell whether we're in vblank or not while
14533 * we're on that particular line. We must still set scanline_offset
14534 * to 1 so that the vblank timestamps come out correct when we query
14535 * the scanline counter from within the vblank interrupt handler.
14536 * However if queried just before the start of vblank we'll get an
14537 * answer that's slightly in the future.
14539 if (IS_GEN(dev_priv, 2)) {
14542 vtotal = adjusted_mode->crtc_vtotal;
14543 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
14546 crtc->scanline_offset = vtotal - 1;
14547 } else if (HAS_DDI(dev_priv) &&
14548 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
14549 crtc->scanline_offset = 2;
14551 crtc->scanline_offset = 1;
14555 static void intel_modeset_clear_plls(struct intel_atomic_state *state)
14557 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14558 struct intel_crtc_state *new_crtc_state;
14559 struct intel_crtc *crtc;
14562 if (!dev_priv->display.crtc_compute_clock)
14565 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14566 if (!needs_modeset(new_crtc_state))
14569 intel_release_shared_dplls(state, crtc);
14574 * This implements the workaround described in the "notes" section of the mode
14575 * set sequence documentation. When going from no pipes or single pipe to
14576 * multiple pipes, and planes are enabled after the pipe, we need to wait at
14577 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
14579 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
14581 struct intel_crtc_state *crtc_state;
14582 struct intel_crtc *crtc;
14583 struct intel_crtc_state *first_crtc_state = NULL;
14584 struct intel_crtc_state *other_crtc_state = NULL;
14585 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
14588 /* look at all crtc's that are going to be enabled in during modeset */
14589 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14590 if (!crtc_state->hw.active ||
14591 !needs_modeset(crtc_state))
14594 if (first_crtc_state) {
14595 other_crtc_state = crtc_state;
14598 first_crtc_state = crtc_state;
14599 first_pipe = crtc->pipe;
14603 /* No workaround needed? */
14604 if (!first_crtc_state)
14607 /* w/a possibly needed, check how many crtc's are already enabled. */
14608 for_each_intel_crtc(state->base.dev, crtc) {
14609 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
14610 if (IS_ERR(crtc_state))
14611 return PTR_ERR(crtc_state);
14613 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
14615 if (!crtc_state->hw.active ||
14616 needs_modeset(crtc_state))
14619 /* 2 or more enabled crtcs means no need for w/a */
14620 if (enabled_pipe != INVALID_PIPE)
14623 enabled_pipe = crtc->pipe;
14626 if (enabled_pipe != INVALID_PIPE)
14627 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
14628 else if (other_crtc_state)
14629 other_crtc_state->hsw_workaround_pipe = first_pipe;
14634 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
14637 const struct intel_crtc_state *crtc_state;
14638 struct intel_crtc *crtc;
14641 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14642 if (crtc_state->hw.active)
14643 active_pipes |= BIT(crtc->pipe);
14645 active_pipes &= ~BIT(crtc->pipe);
14648 return active_pipes;
14651 static int intel_modeset_checks(struct intel_atomic_state *state)
14653 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14655 state->modeset = true;
14657 if (IS_HASWELL(dev_priv))
14658 return hsw_mode_set_planes_workaround(state);
14664 * Handle calculation of various watermark data at the end of the atomic check
14665 * phase. The code here should be run after the per-crtc and per-plane 'check'
14666 * handlers to ensure that all derived state has been updated.
14668 static int calc_watermark_data(struct intel_atomic_state *state)
14670 struct drm_device *dev = state->base.dev;
14671 struct drm_i915_private *dev_priv = to_i915(dev);
14673 /* Is there platform-specific watermark information to calculate? */
14674 if (dev_priv->display.compute_global_watermarks)
14675 return dev_priv->display.compute_global_watermarks(state);
14680 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
14681 struct intel_crtc_state *new_crtc_state)
14683 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
14686 new_crtc_state->uapi.mode_changed = false;
14687 new_crtc_state->update_pipe = true;
14690 static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state,
14691 struct intel_crtc_state *new_crtc_state)
14694 * If we're not doing the full modeset we want to
14695 * keep the current M/N values as they may be
14696 * sufficiently different to the computed values
14697 * to cause problems.
14699 * FIXME: should really copy more fuzzy state here
14701 new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n;
14702 new_crtc_state->dp_m_n = old_crtc_state->dp_m_n;
14703 new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
14704 new_crtc_state->has_drrs = old_crtc_state->has_drrs;
14707 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
14708 struct intel_crtc *crtc,
14711 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14712 struct intel_plane *plane;
14714 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
14715 struct intel_plane_state *plane_state;
14717 if ((plane_ids_mask & BIT(plane->id)) == 0)
14720 plane_state = intel_atomic_get_plane_state(state, plane);
14721 if (IS_ERR(plane_state))
14722 return PTR_ERR(plane_state);
14728 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
14730 /* See {hsw,vlv,ivb}_plane_ratio() */
14731 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
14732 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
14733 IS_IVYBRIDGE(dev_priv) || (INTEL_GEN(dev_priv) >= 11);
14736 static int intel_atomic_check_planes(struct intel_atomic_state *state)
14738 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14739 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14740 struct intel_plane_state *plane_state;
14741 struct intel_plane *plane;
14742 struct intel_crtc *crtc;
14745 ret = icl_add_linked_planes(state);
14749 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
14750 ret = intel_plane_atomic_check(state, plane);
14752 drm_dbg_atomic(&dev_priv->drm,
14753 "[PLANE:%d:%s] atomic driver check failed\n",
14754 plane->base.base.id, plane->base.name);
14759 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14760 new_crtc_state, i) {
14761 u8 old_active_planes, new_active_planes;
14763 ret = icl_check_nv12_planes(new_crtc_state);
14768 * On some platforms the number of active planes affects
14769 * the planes' minimum cdclk calculation. Add such planes
14770 * to the state before we compute the minimum cdclk.
14772 if (!active_planes_affects_min_cdclk(dev_priv))
14775 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
14776 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
14779 * Not only the number of planes, but if the plane configuration had
14780 * changed might already mean we need to recompute min CDCLK,
14781 * because different planes might consume different amount of Dbuf bandwidth
14782 * according to formula: Bw per plane = Pixel rate * bpp * pipe/plane scale factor
14784 if (old_active_planes == new_active_planes)
14787 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
14795 static int intel_atomic_check_cdclk(struct intel_atomic_state *state,
14796 bool *need_cdclk_calc)
14798 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14799 const struct intel_cdclk_state *old_cdclk_state;
14800 const struct intel_cdclk_state *new_cdclk_state;
14801 struct intel_plane_state *plane_state;
14802 struct intel_bw_state *new_bw_state;
14803 struct intel_plane *plane;
14809 * active_planes bitmask has been updated, and potentially
14810 * affected planes are part of the state. We can now
14811 * compute the minimum cdclk for each plane.
14813 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
14814 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc);
14819 old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
14820 new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
14822 if (new_cdclk_state &&
14823 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
14824 *need_cdclk_calc = true;
14826 ret = dev_priv->display.bw_calc_min_cdclk(state);
14830 new_bw_state = intel_atomic_get_new_bw_state(state);
14832 if (!new_cdclk_state || !new_bw_state)
14835 for_each_pipe(dev_priv, pipe) {
14836 min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk);
14839 * Currently do this change only if we need to increase
14841 if (new_bw_state->min_cdclk > min_cdclk)
14842 *need_cdclk_calc = true;
14848 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
14850 struct intel_crtc_state *crtc_state;
14851 struct intel_crtc *crtc;
14854 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14855 int ret = intel_crtc_atomic_check(state, crtc);
14856 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
14858 drm_dbg_atomic(&i915->drm,
14859 "[CRTC:%d:%s] atomic driver check failed\n",
14860 crtc->base.base.id, crtc->base.name);
14868 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
14871 const struct intel_crtc_state *new_crtc_state;
14872 struct intel_crtc *crtc;
14875 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14876 if (new_crtc_state->hw.enable &&
14877 transcoders & BIT(new_crtc_state->cpu_transcoder) &&
14878 needs_modeset(new_crtc_state))
14886 * intel_atomic_check - validate state object
14888 * @_state: state to validate
14890 static int intel_atomic_check(struct drm_device *dev,
14891 struct drm_atomic_state *_state)
14893 struct drm_i915_private *dev_priv = to_i915(dev);
14894 struct intel_atomic_state *state = to_intel_atomic_state(_state);
14895 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14896 struct intel_crtc *crtc;
14898 bool any_ms = false;
14900 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14901 new_crtc_state, i) {
14902 if (new_crtc_state->inherited != old_crtc_state->inherited)
14903 new_crtc_state->uapi.mode_changed = true;
14906 ret = drm_atomic_helper_check_modeset(dev, &state->base);
14910 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14911 new_crtc_state, i) {
14912 if (!needs_modeset(new_crtc_state)) {
14914 intel_crtc_copy_uapi_to_hw_state_nomodeset(new_crtc_state);
14919 ret = intel_crtc_prepare_cleared_state(new_crtc_state);
14923 if (!new_crtc_state->hw.enable)
14926 ret = intel_modeset_pipe_config(new_crtc_state);
14931 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14932 new_crtc_state, i) {
14933 if (!needs_modeset(new_crtc_state))
14936 ret = intel_modeset_pipe_config_late(new_crtc_state);
14940 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
14944 * Check if fastset is allowed by external dependencies like other
14945 * pipes and transcoders.
14947 * Right now it only forces a fullmodeset when the MST master
14948 * transcoder did not changed but the pipe of the master transcoder
14949 * needs a fullmodeset so all slaves also needs to do a fullmodeset or
14950 * in case of port synced crtcs, if one of the synced crtcs
14951 * needs a full modeset, all other synced crtcs should be
14952 * forced a full modeset.
14954 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14955 if (!new_crtc_state->hw.enable || needs_modeset(new_crtc_state))
14958 if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
14959 enum transcoder master = new_crtc_state->mst_master_transcoder;
14961 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
14962 new_crtc_state->uapi.mode_changed = true;
14963 new_crtc_state->update_pipe = false;
14967 if (is_trans_port_sync_mode(new_crtc_state)) {
14968 u8 trans = new_crtc_state->sync_mode_slaves_mask;
14970 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
14971 trans |= BIT(new_crtc_state->master_transcoder);
14973 if (intel_cpu_transcoders_need_modeset(state, trans)) {
14974 new_crtc_state->uapi.mode_changed = true;
14975 new_crtc_state->update_pipe = false;
14980 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14981 new_crtc_state, i) {
14982 if (needs_modeset(new_crtc_state)) {
14987 if (!new_crtc_state->update_pipe)
14990 intel_crtc_copy_fastset(old_crtc_state, new_crtc_state);
14993 if (any_ms && !check_digital_port_conflicts(state)) {
14994 drm_dbg_kms(&dev_priv->drm,
14995 "rejecting conflicting digital port configuration\n");
15000 ret = drm_dp_mst_atomic_check(&state->base);
15004 ret = intel_atomic_check_planes(state);
15009 * distrust_bios_wm will force a full dbuf recomputation
15010 * but the hardware state will only get updated accordingly
15011 * if state->modeset==true. Hence distrust_bios_wm==true &&
15012 * state->modeset==false is an invalid combination which
15013 * would cause the hardware and software dbuf state to get
15014 * out of sync. We must prevent that.
15016 * FIXME clean up this mess and introduce better
15017 * state tracking for dbuf.
15019 if (dev_priv->wm.distrust_bios_wm)
15022 intel_fbc_choose_crtc(dev_priv, state);
15023 ret = calc_watermark_data(state);
15027 ret = intel_bw_atomic_check(state);
15031 ret = intel_atomic_check_cdclk(state, &any_ms);
15036 ret = intel_modeset_checks(state);
15040 ret = intel_modeset_calc_cdclk(state);
15044 intel_modeset_clear_plls(state);
15047 ret = intel_atomic_check_crtcs(state);
15051 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15052 new_crtc_state, i) {
15053 if (!needs_modeset(new_crtc_state) &&
15054 !new_crtc_state->update_pipe)
15057 intel_dump_pipe_config(new_crtc_state, state,
15058 needs_modeset(new_crtc_state) ?
15059 "[modeset]" : "[fastset]");
15065 if (ret == -EDEADLK)
15069 * FIXME would probably be nice to know which crtc specifically
15070 * caused the failure, in cases where we can pinpoint it.
15072 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15074 intel_dump_pipe_config(new_crtc_state, state, "[failed]");
15079 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
15081 struct intel_crtc_state *crtc_state;
15082 struct intel_crtc *crtc;
15085 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
15089 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
15090 bool mode_changed = needs_modeset(crtc_state);
15092 if (mode_changed || crtc_state->update_pipe ||
15093 crtc_state->uapi.color_mgmt_changed) {
15094 intel_dsb_prepare(crtc_state);
15101 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
15103 struct drm_device *dev = crtc->base.dev;
15104 struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)];
15106 if (!vblank->max_vblank_count)
15107 return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
15109 return crtc->base.funcs->get_vblank_counter(&crtc->base);
15112 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
15113 struct intel_crtc_state *crtc_state)
15115 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15117 if (!IS_GEN(dev_priv, 2) || crtc_state->active_planes)
15118 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
15120 if (crtc_state->has_pch_encoder) {
15121 enum pipe pch_transcoder =
15122 intel_crtc_pch_transcoder(crtc);
15124 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
15128 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
15129 const struct intel_crtc_state *new_crtc_state)
15131 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
15132 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15135 * Update pipe size and adjust fitter if needed: the reason for this is
15136 * that in compute_mode_changes we check the native mode (not the pfit
15137 * mode) to see if we can flip rather than do a full mode set. In the
15138 * fastboot case, we'll flip, but if we don't update the pipesrc and
15139 * pfit state, we'll end up with a big fb scanned out into the wrong
15142 intel_set_pipe_src_size(new_crtc_state);
15144 /* on skylake this is done by detaching scalers */
15145 if (INTEL_GEN(dev_priv) >= 9) {
15146 skl_detach_scalers(new_crtc_state);
15148 if (new_crtc_state->pch_pfit.enabled)
15149 skl_pfit_enable(new_crtc_state);
15150 } else if (HAS_PCH_SPLIT(dev_priv)) {
15151 if (new_crtc_state->pch_pfit.enabled)
15152 ilk_pfit_enable(new_crtc_state);
15153 else if (old_crtc_state->pch_pfit.enabled)
15154 ilk_pfit_disable(old_crtc_state);
15158 * The register is supposedly single buffered so perhaps
15159 * not 100% correct to do this here. But SKL+ calculate
15160 * this based on the adjust pixel rate so pfit changes do
15161 * affect it and so it must be updated for fastsets.
15162 * HSW/BDW only really need this here for fastboot, after
15163 * that the value should not change without a full modeset.
15165 if (INTEL_GEN(dev_priv) >= 9 ||
15166 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
15167 hsw_set_linetime_wm(new_crtc_state);
15169 if (INTEL_GEN(dev_priv) >= 11)
15170 icl_set_pipe_chicken(crtc);
15173 static void commit_pipe_config(struct intel_atomic_state *state,
15174 struct intel_crtc *crtc)
15176 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15177 const struct intel_crtc_state *old_crtc_state =
15178 intel_atomic_get_old_crtc_state(state, crtc);
15179 const struct intel_crtc_state *new_crtc_state =
15180 intel_atomic_get_new_crtc_state(state, crtc);
15181 bool modeset = needs_modeset(new_crtc_state);
15184 * During modesets pipe configuration was programmed as the
15185 * CRTC was enabled.
15188 if (new_crtc_state->uapi.color_mgmt_changed ||
15189 new_crtc_state->update_pipe)
15190 intel_color_commit(new_crtc_state);
15192 if (INTEL_GEN(dev_priv) >= 9)
15193 skl_detach_scalers(new_crtc_state);
15195 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
15196 bdw_set_pipemisc(new_crtc_state);
15198 if (new_crtc_state->update_pipe)
15199 intel_pipe_fastset(old_crtc_state, new_crtc_state);
15201 intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
15204 if (dev_priv->display.atomic_update_watermarks)
15205 dev_priv->display.atomic_update_watermarks(state, crtc);
15208 static void intel_enable_crtc(struct intel_atomic_state *state,
15209 struct intel_crtc *crtc)
15211 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15212 const struct intel_crtc_state *new_crtc_state =
15213 intel_atomic_get_new_crtc_state(state, crtc);
15215 if (!needs_modeset(new_crtc_state))
15218 intel_crtc_update_active_timings(new_crtc_state);
15220 dev_priv->display.crtc_enable(state, crtc);
15222 /* vblanks work again, re-enable pipe CRC. */
15223 intel_crtc_enable_pipe_crc(crtc);
15226 static void intel_update_crtc(struct intel_atomic_state *state,
15227 struct intel_crtc *crtc)
15229 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15230 const struct intel_crtc_state *old_crtc_state =
15231 intel_atomic_get_old_crtc_state(state, crtc);
15232 struct intel_crtc_state *new_crtc_state =
15233 intel_atomic_get_new_crtc_state(state, crtc);
15234 bool modeset = needs_modeset(new_crtc_state);
15237 if (new_crtc_state->preload_luts &&
15238 (new_crtc_state->uapi.color_mgmt_changed ||
15239 new_crtc_state->update_pipe))
15240 intel_color_load_luts(new_crtc_state);
15242 intel_pre_plane_update(state, crtc);
15244 if (new_crtc_state->update_pipe)
15245 intel_encoders_update_pipe(state, crtc);
15248 if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
15249 intel_fbc_disable(crtc);
15251 intel_fbc_enable(state, crtc);
15253 /* Perform vblank evasion around commit operation */
15254 intel_pipe_update_start(new_crtc_state);
15256 commit_pipe_config(state, crtc);
15258 if (INTEL_GEN(dev_priv) >= 9)
15259 skl_update_planes_on_crtc(state, crtc);
15261 i9xx_update_planes_on_crtc(state, crtc);
15263 intel_pipe_update_end(new_crtc_state);
15266 * We usually enable FIFO underrun interrupts as part of the
15267 * CRTC enable sequence during modesets. But when we inherit a
15268 * valid pipe configuration from the BIOS we need to take care
15269 * of enabling them on the CRTC's first fastset.
15271 if (new_crtc_state->update_pipe && !modeset &&
15272 old_crtc_state->inherited)
15273 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
15277 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
15278 struct intel_crtc_state *old_crtc_state,
15279 struct intel_crtc_state *new_crtc_state,
15280 struct intel_crtc *crtc)
15282 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15284 intel_crtc_disable_planes(state, crtc);
15287 * We need to disable pipe CRC before disabling the pipe,
15288 * or we race against vblank off.
15290 intel_crtc_disable_pipe_crc(crtc);
15292 dev_priv->display.crtc_disable(state, crtc);
15293 crtc->active = false;
15294 intel_fbc_disable(crtc);
15295 intel_disable_shared_dpll(old_crtc_state);
15297 /* FIXME unify this for all platforms */
15298 if (!new_crtc_state->hw.active &&
15299 !HAS_GMCH(dev_priv) &&
15300 dev_priv->display.initial_watermarks)
15301 dev_priv->display.initial_watermarks(state, crtc);
15304 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
15306 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
15307 struct intel_crtc *crtc;
15311 /* Only disable port sync and MST slaves */
15312 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15313 new_crtc_state, i) {
15314 if (!needs_modeset(new_crtc_state))
15317 if (!old_crtc_state->hw.active)
15320 /* In case of Transcoder port Sync master slave CRTCs can be
15321 * assigned in any order and we need to make sure that
15322 * slave CRTCs are disabled first and then master CRTC since
15323 * Slave vblanks are masked till Master Vblanks.
15325 if (!is_trans_port_sync_slave(old_crtc_state) &&
15326 !intel_dp_mst_is_slave_trans(old_crtc_state))
15329 intel_pre_plane_update(state, crtc);
15330 intel_old_crtc_state_disables(state, old_crtc_state,
15331 new_crtc_state, crtc);
15332 handled |= BIT(crtc->pipe);
15335 /* Disable everything else left on */
15336 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15337 new_crtc_state, i) {
15338 if (!needs_modeset(new_crtc_state) ||
15339 (handled & BIT(crtc->pipe)))
15342 intel_pre_plane_update(state, crtc);
15343 if (old_crtc_state->hw.active)
15344 intel_old_crtc_state_disables(state, old_crtc_state,
15345 new_crtc_state, crtc);
15349 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
15351 struct intel_crtc_state *new_crtc_state;
15352 struct intel_crtc *crtc;
15355 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15356 if (!new_crtc_state->hw.active)
15359 intel_enable_crtc(state, crtc);
15360 intel_update_crtc(state, crtc);
15364 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
15366 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15367 struct intel_crtc *crtc;
15368 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
15369 struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
15370 u8 update_pipes = 0, modeset_pipes = 0;
15373 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
15374 enum pipe pipe = crtc->pipe;
15376 if (!new_crtc_state->hw.active)
15379 /* ignore allocations for crtc's that have been turned off. */
15380 if (!needs_modeset(new_crtc_state)) {
15381 entries[pipe] = old_crtc_state->wm.skl.ddb;
15382 update_pipes |= BIT(pipe);
15384 modeset_pipes |= BIT(pipe);
15389 * Whenever the number of active pipes changes, we need to make sure we
15390 * update the pipes in the right order so that their ddb allocations
15391 * never overlap with each other between CRTC updates. Otherwise we'll
15392 * cause pipe underruns and other bad stuff.
15394 * So first lets enable all pipes that do not need a fullmodeset as
15395 * those don't have any external dependency.
15397 while (update_pipes) {
15398 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15399 new_crtc_state, i) {
15400 enum pipe pipe = crtc->pipe;
15402 if ((update_pipes & BIT(pipe)) == 0)
15405 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
15406 entries, I915_MAX_PIPES, pipe))
15409 entries[pipe] = new_crtc_state->wm.skl.ddb;
15410 update_pipes &= ~BIT(pipe);
15412 intel_update_crtc(state, crtc);
15415 * If this is an already active pipe, it's DDB changed,
15416 * and this isn't the last pipe that needs updating
15417 * then we need to wait for a vblank to pass for the
15418 * new ddb allocation to take effect.
15420 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
15421 &old_crtc_state->wm.skl.ddb) &&
15422 (update_pipes | modeset_pipes))
15423 intel_wait_for_vblank(dev_priv, pipe);
15427 update_pipes = modeset_pipes;
15430 * Enable all pipes that needs a modeset and do not depends on other
15433 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15434 enum pipe pipe = crtc->pipe;
15436 if ((modeset_pipes & BIT(pipe)) == 0)
15439 if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
15440 is_trans_port_sync_master(new_crtc_state))
15443 modeset_pipes &= ~BIT(pipe);
15445 intel_enable_crtc(state, crtc);
15449 * Then we enable all remaining pipes that depend on other
15450 * pipes: MST slaves and port sync masters.
15452 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15453 enum pipe pipe = crtc->pipe;
15455 if ((modeset_pipes & BIT(pipe)) == 0)
15458 modeset_pipes &= ~BIT(pipe);
15460 intel_enable_crtc(state, crtc);
15464 * Finally we do the plane updates/etc. for all pipes that got enabled.
15466 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15467 enum pipe pipe = crtc->pipe;
15469 if ((update_pipes & BIT(pipe)) == 0)
15472 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
15473 entries, I915_MAX_PIPES, pipe));
15475 entries[pipe] = new_crtc_state->wm.skl.ddb;
15476 update_pipes &= ~BIT(pipe);
15478 intel_update_crtc(state, crtc);
15481 drm_WARN_ON(&dev_priv->drm, modeset_pipes);
15482 drm_WARN_ON(&dev_priv->drm, update_pipes);
15485 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
15487 struct intel_atomic_state *state, *next;
15488 struct llist_node *freed;
15490 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
15491 llist_for_each_entry_safe(state, next, freed, freed)
15492 drm_atomic_state_put(&state->base);
15495 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
15497 struct drm_i915_private *dev_priv =
15498 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
15500 intel_atomic_helper_free_state(dev_priv);
15503 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
15505 struct wait_queue_entry wait_fence, wait_reset;
15506 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
15508 init_wait_entry(&wait_fence, 0);
15509 init_wait_entry(&wait_reset, 0);
15511 prepare_to_wait(&intel_state->commit_ready.wait,
15512 &wait_fence, TASK_UNINTERRUPTIBLE);
15513 prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
15514 I915_RESET_MODESET),
15515 &wait_reset, TASK_UNINTERRUPTIBLE);
15518 if (i915_sw_fence_done(&intel_state->commit_ready) ||
15519 test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
15524 finish_wait(&intel_state->commit_ready.wait, &wait_fence);
15525 finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
15526 I915_RESET_MODESET),
15530 static void intel_cleanup_dsbs(struct intel_atomic_state *state)
15532 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
15533 struct intel_crtc *crtc;
15536 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15538 intel_dsb_cleanup(old_crtc_state);
15541 static void intel_atomic_cleanup_work(struct work_struct *work)
15543 struct intel_atomic_state *state =
15544 container_of(work, struct intel_atomic_state, base.commit_work);
15545 struct drm_i915_private *i915 = to_i915(state->base.dev);
15547 intel_cleanup_dsbs(state);
15548 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
15549 drm_atomic_helper_commit_cleanup_done(&state->base);
15550 drm_atomic_state_put(&state->base);
15552 intel_atomic_helper_free_state(i915);
15555 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
15557 struct drm_device *dev = state->base.dev;
15558 struct drm_i915_private *dev_priv = to_i915(dev);
15559 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
15560 struct intel_crtc *crtc;
15561 u64 put_domains[I915_MAX_PIPES] = {};
15562 intel_wakeref_t wakeref = 0;
15565 intel_atomic_commit_fence_wait(state);
15567 drm_atomic_helper_wait_for_dependencies(&state->base);
15569 if (state->modeset)
15570 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
15572 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15573 new_crtc_state, i) {
15574 if (needs_modeset(new_crtc_state) ||
15575 new_crtc_state->update_pipe) {
15577 put_domains[crtc->pipe] =
15578 modeset_get_crtc_power_domains(new_crtc_state);
15582 intel_commit_modeset_disables(state);
15584 /* FIXME: Eventually get rid of our crtc->config pointer */
15585 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
15586 crtc->config = new_crtc_state;
15588 if (state->modeset) {
15589 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
15591 intel_set_cdclk_pre_plane_update(state);
15593 intel_modeset_verify_disabled(dev_priv, state);
15596 intel_sagv_pre_plane_update(state);
15598 /* Complete the events for pipes that have now been disabled */
15599 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15600 bool modeset = needs_modeset(new_crtc_state);
15602 /* Complete events for now disable pipes here. */
15603 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
15604 spin_lock_irq(&dev->event_lock);
15605 drm_crtc_send_vblank_event(&crtc->base,
15606 new_crtc_state->uapi.event);
15607 spin_unlock_irq(&dev->event_lock);
15609 new_crtc_state->uapi.event = NULL;
15613 if (state->modeset)
15614 intel_encoders_update_prepare(state);
15616 intel_dbuf_pre_plane_update(state);
15618 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
15619 dev_priv->display.commit_modeset_enables(state);
15621 if (state->modeset) {
15622 intel_encoders_update_complete(state);
15624 intel_set_cdclk_post_plane_update(state);
15627 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
15628 * already, but still need the state for the delayed optimization. To
15630 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
15631 * - schedule that vblank worker _before_ calling hw_done
15632 * - at the start of commit_tail, cancel it _synchrously
15633 * - switch over to the vblank wait helper in the core after that since
15634 * we don't need out special handling any more.
15636 drm_atomic_helper_wait_for_flip_done(dev, &state->base);
15638 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15639 if (new_crtc_state->hw.active &&
15640 !needs_modeset(new_crtc_state) &&
15641 !new_crtc_state->preload_luts &&
15642 (new_crtc_state->uapi.color_mgmt_changed ||
15643 new_crtc_state->update_pipe))
15644 intel_color_load_luts(new_crtc_state);
15648 * Now that the vblank has passed, we can go ahead and program the
15649 * optimal watermarks on platforms that need two-step watermark
15652 * TODO: Move this (and other cleanup) to an async worker eventually.
15654 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15655 new_crtc_state, i) {
15657 * Gen2 reports pipe underruns whenever all planes are disabled.
15658 * So re-enable underrun reporting after some planes get enabled.
15660 * We do this before .optimize_watermarks() so that we have a
15661 * chance of catching underruns with the intermediate watermarks
15662 * vs. the new plane configuration.
15664 if (IS_GEN(dev_priv, 2) && planes_enabling(old_crtc_state, new_crtc_state))
15665 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
15667 if (dev_priv->display.optimize_watermarks)
15668 dev_priv->display.optimize_watermarks(state, crtc);
15671 intel_dbuf_post_plane_update(state);
15673 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
15674 intel_post_plane_update(state, crtc);
15676 if (put_domains[i])
15677 modeset_put_power_domains(dev_priv, put_domains[i]);
15679 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
15682 * DSB cleanup is done in cleanup_work aligning with framebuffer
15683 * cleanup. So copy and reset the dsb structure to sync with
15684 * commit_done and later do dsb cleanup in cleanup_work.
15686 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb);
15689 /* Underruns don't always raise interrupts, so check manually */
15690 intel_check_cpu_fifo_underruns(dev_priv);
15691 intel_check_pch_fifo_underruns(dev_priv);
15693 if (state->modeset)
15694 intel_verify_planes(state);
15696 intel_sagv_post_plane_update(state);
15698 drm_atomic_helper_commit_hw_done(&state->base);
15700 if (state->modeset) {
15701 /* As one of the primary mmio accessors, KMS has a high
15702 * likelihood of triggering bugs in unclaimed access. After we
15703 * finish modesetting, see if an error has been flagged, and if
15704 * so enable debugging for the next modeset - and hope we catch
15707 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
15708 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
15710 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
15713 * Defer the cleanup of the old state to a separate worker to not
15714 * impede the current task (userspace for blocking modesets) that
15715 * are executed inline. For out-of-line asynchronous modesets/flips,
15716 * deferring to a new worker seems overkill, but we would place a
15717 * schedule point (cond_resched()) here anyway to keep latencies
15720 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
15721 queue_work(system_highpri_wq, &state->base.commit_work);
15724 static void intel_atomic_commit_work(struct work_struct *work)
15726 struct intel_atomic_state *state =
15727 container_of(work, struct intel_atomic_state, base.commit_work);
15729 intel_atomic_commit_tail(state);
15732 static int __i915_sw_fence_call
15733 intel_atomic_commit_ready(struct i915_sw_fence *fence,
15734 enum i915_sw_fence_notify notify)
15736 struct intel_atomic_state *state =
15737 container_of(fence, struct intel_atomic_state, commit_ready);
15740 case FENCE_COMPLETE:
15741 /* we do blocking waits in the worker, nothing to do here */
15745 struct intel_atomic_helper *helper =
15746 &to_i915(state->base.dev)->atomic_helper;
15748 if (llist_add(&state->freed, &helper->free_list))
15749 schedule_work(&helper->free_work);
15754 return NOTIFY_DONE;
15757 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
15759 struct intel_plane_state *old_plane_state, *new_plane_state;
15760 struct intel_plane *plane;
15763 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
15764 new_plane_state, i)
15765 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
15766 to_intel_frontbuffer(new_plane_state->hw.fb),
15767 plane->frontbuffer_bit);
15770 static int intel_atomic_commit(struct drm_device *dev,
15771 struct drm_atomic_state *_state,
15774 struct intel_atomic_state *state = to_intel_atomic_state(_state);
15775 struct drm_i915_private *dev_priv = to_i915(dev);
15778 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
15780 drm_atomic_state_get(&state->base);
15781 i915_sw_fence_init(&state->commit_ready,
15782 intel_atomic_commit_ready);
15785 * The intel_legacy_cursor_update() fast path takes care
15786 * of avoiding the vblank waits for simple cursor
15787 * movement and flips. For cursor on/off and size changes,
15788 * we want to perform the vblank waits so that watermark
15789 * updates happen during the correct frames. Gen9+ have
15790 * double buffered watermarks and so shouldn't need this.
15792 * Unset state->legacy_cursor_update before the call to
15793 * drm_atomic_helper_setup_commit() because otherwise
15794 * drm_atomic_helper_wait_for_flip_done() is a noop and
15795 * we get FIFO underruns because we didn't wait
15798 * FIXME doing watermarks and fb cleanup from a vblank worker
15799 * (assuming we had any) would solve these problems.
15801 if (INTEL_GEN(dev_priv) < 9 && state->base.legacy_cursor_update) {
15802 struct intel_crtc_state *new_crtc_state;
15803 struct intel_crtc *crtc;
15806 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
15807 if (new_crtc_state->wm.need_postvbl_update ||
15808 new_crtc_state->update_wm_post)
15809 state->base.legacy_cursor_update = false;
15812 ret = intel_atomic_prepare_commit(state);
15814 drm_dbg_atomic(&dev_priv->drm,
15815 "Preparing state failed with %i\n", ret);
15816 i915_sw_fence_commit(&state->commit_ready);
15817 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
15821 ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
15823 ret = drm_atomic_helper_swap_state(&state->base, true);
15825 intel_atomic_swap_global_state(state);
15828 struct intel_crtc_state *new_crtc_state;
15829 struct intel_crtc *crtc;
15832 i915_sw_fence_commit(&state->commit_ready);
15834 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
15835 intel_dsb_cleanup(new_crtc_state);
15837 drm_atomic_helper_cleanup_planes(dev, &state->base);
15838 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
15841 dev_priv->wm.distrust_bios_wm = false;
15842 intel_shared_dpll_swap_state(state);
15843 intel_atomic_track_fbs(state);
15845 drm_atomic_state_get(&state->base);
15846 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
15848 i915_sw_fence_commit(&state->commit_ready);
15849 if (nonblock && state->modeset) {
15850 queue_work(dev_priv->modeset_wq, &state->base.commit_work);
15851 } else if (nonblock) {
15852 queue_work(dev_priv->flip_wq, &state->base.commit_work);
15854 if (state->modeset)
15855 flush_workqueue(dev_priv->modeset_wq);
15856 intel_atomic_commit_tail(state);
15862 struct wait_rps_boost {
15863 struct wait_queue_entry wait;
15865 struct drm_crtc *crtc;
15866 struct i915_request *request;
15869 static int do_rps_boost(struct wait_queue_entry *_wait,
15870 unsigned mode, int sync, void *key)
15872 struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
15873 struct i915_request *rq = wait->request;
15876 * If we missed the vblank, but the request is already running it
15877 * is reasonable to assume that it will complete before the next
15878 * vblank without our intervention, so leave RPS alone.
15880 if (!i915_request_started(rq))
15881 intel_rps_boost(rq);
15882 i915_request_put(rq);
15884 drm_crtc_vblank_put(wait->crtc);
15886 list_del(&wait->wait.entry);
15891 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
15892 struct dma_fence *fence)
15894 struct wait_rps_boost *wait;
15896 if (!dma_fence_is_i915(fence))
15899 if (INTEL_GEN(to_i915(crtc->dev)) < 6)
15902 if (drm_crtc_vblank_get(crtc))
15905 wait = kmalloc(sizeof(*wait), GFP_KERNEL);
15907 drm_crtc_vblank_put(crtc);
15911 wait->request = to_request(dma_fence_get(fence));
15914 wait->wait.func = do_rps_boost;
15915 wait->wait.flags = 0;
15917 add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
15920 static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
15922 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
15923 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15924 struct drm_framebuffer *fb = plane_state->hw.fb;
15925 struct i915_vma *vma;
15927 if (plane->id == PLANE_CURSOR &&
15928 INTEL_INFO(dev_priv)->display.cursor_needs_physical) {
15929 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15930 const int align = intel_cursor_alignment(dev_priv);
15933 err = i915_gem_object_attach_phys(obj, align);
15938 vma = intel_pin_and_fence_fb_obj(fb,
15939 &plane_state->view,
15940 intel_plane_uses_fence(plane_state),
15941 &plane_state->flags);
15943 return PTR_ERR(vma);
15945 plane_state->vma = vma;
15950 static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
15952 struct i915_vma *vma;
15954 vma = fetch_and_zero(&old_plane_state->vma);
15956 intel_unpin_fb_vma(vma, old_plane_state->flags);
15959 static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
15961 struct i915_sched_attr attr = {
15962 .priority = I915_USER_PRIORITY(I915_PRIORITY_DISPLAY),
15965 i915_gem_object_wait_priority(obj, 0, &attr);
15969 * intel_prepare_plane_fb - Prepare fb for usage on plane
15970 * @_plane: drm plane to prepare for
15971 * @_new_plane_state: the plane state being prepared
15973 * Prepares a framebuffer for usage on a display plane. Generally this
15974 * involves pinning the underlying object and updating the frontbuffer tracking
15975 * bits. Some older platforms need special physical address handling for
15978 * Returns 0 on success, negative error code on failure.
15981 intel_prepare_plane_fb(struct drm_plane *_plane,
15982 struct drm_plane_state *_new_plane_state)
15984 struct intel_plane *plane = to_intel_plane(_plane);
15985 struct intel_plane_state *new_plane_state =
15986 to_intel_plane_state(_new_plane_state);
15987 struct intel_atomic_state *state =
15988 to_intel_atomic_state(new_plane_state->uapi.state);
15989 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15990 const struct intel_plane_state *old_plane_state =
15991 intel_atomic_get_old_plane_state(state, plane);
15992 struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb);
15993 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_plane_state->hw.fb);
15997 const struct intel_crtc_state *crtc_state =
15998 intel_atomic_get_new_crtc_state(state,
15999 to_intel_crtc(old_plane_state->hw.crtc));
16001 /* Big Hammer, we also need to ensure that any pending
16002 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
16003 * current scanout is retired before unpinning the old
16004 * framebuffer. Note that we rely on userspace rendering
16005 * into the buffer attached to the pipe they are waiting
16006 * on. If not, userspace generates a GPU hang with IPEHR
16007 * point to the MI_WAIT_FOR_EVENT.
16009 * This should only fail upon a hung GPU, in which case we
16010 * can safely continue.
16012 if (needs_modeset(crtc_state)) {
16013 ret = i915_sw_fence_await_reservation(&state->commit_ready,
16014 old_obj->base.resv, NULL,
16022 if (new_plane_state->uapi.fence) { /* explicit fencing */
16023 ret = i915_sw_fence_await_dma_fence(&state->commit_ready,
16024 new_plane_state->uapi.fence,
16025 i915_fence_timeout(dev_priv),
16034 ret = i915_gem_object_pin_pages(obj);
16038 ret = intel_plane_pin_fb(new_plane_state);
16040 i915_gem_object_unpin_pages(obj);
16044 fb_obj_bump_render_priority(obj);
16045 i915_gem_object_flush_frontbuffer(obj, ORIGIN_DIRTYFB);
16047 if (!new_plane_state->uapi.fence) { /* implicit fencing */
16048 struct dma_fence *fence;
16050 ret = i915_sw_fence_await_reservation(&state->commit_ready,
16051 obj->base.resv, NULL,
16053 i915_fence_timeout(dev_priv),
16058 fence = dma_resv_get_excl_rcu(obj->base.resv);
16060 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
16062 dma_fence_put(fence);
16065 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
16066 new_plane_state->uapi.fence);
16070 * We declare pageflips to be interactive and so merit a small bias
16071 * towards upclocking to deliver the frame on time. By only changing
16072 * the RPS thresholds to sample more regularly and aim for higher
16073 * clocks we can hopefully deliver low power workloads (like kodi)
16074 * that are not quite steady state without resorting to forcing
16075 * maximum clocks following a vblank miss (see do_rps_boost()).
16077 if (!state->rps_interactive) {
16078 intel_rps_mark_interactive(&dev_priv->gt.rps, true);
16079 state->rps_interactive = true;
16085 intel_plane_unpin_fb(new_plane_state);
16091 * intel_cleanup_plane_fb - Cleans up an fb after plane use
16092 * @plane: drm plane to clean up for
16093 * @_old_plane_state: the state from the previous modeset
16095 * Cleans up a framebuffer that has just been removed from a plane.
16098 intel_cleanup_plane_fb(struct drm_plane *plane,
16099 struct drm_plane_state *_old_plane_state)
16101 struct intel_plane_state *old_plane_state =
16102 to_intel_plane_state(_old_plane_state);
16103 struct intel_atomic_state *state =
16104 to_intel_atomic_state(old_plane_state->uapi.state);
16105 struct drm_i915_private *dev_priv = to_i915(plane->dev);
16106 struct drm_i915_gem_object *obj = intel_fb_obj(old_plane_state->hw.fb);
16111 if (state->rps_interactive) {
16112 intel_rps_mark_interactive(&dev_priv->gt.rps, false);
16113 state->rps_interactive = false;
16116 /* Should only be called after a successful intel_prepare_plane_fb()! */
16117 intel_plane_unpin_fb(old_plane_state);
16121 * intel_plane_destroy - destroy a plane
16122 * @plane: plane to destroy
16124 * Common destruction function for all types of planes (primary, cursor,
16127 void intel_plane_destroy(struct drm_plane *plane)
16129 drm_plane_cleanup(plane);
16130 kfree(to_intel_plane(plane));
16133 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
16134 u32 format, u64 modifier)
16136 switch (modifier) {
16137 case DRM_FORMAT_MOD_LINEAR:
16138 case I915_FORMAT_MOD_X_TILED:
16145 case DRM_FORMAT_C8:
16146 case DRM_FORMAT_RGB565:
16147 case DRM_FORMAT_XRGB1555:
16148 case DRM_FORMAT_XRGB8888:
16149 return modifier == DRM_FORMAT_MOD_LINEAR ||
16150 modifier == I915_FORMAT_MOD_X_TILED;
16156 static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
16157 u32 format, u64 modifier)
16159 switch (modifier) {
16160 case DRM_FORMAT_MOD_LINEAR:
16161 case I915_FORMAT_MOD_X_TILED:
16168 case DRM_FORMAT_C8:
16169 case DRM_FORMAT_RGB565:
16170 case DRM_FORMAT_XRGB8888:
16171 case DRM_FORMAT_XBGR8888:
16172 case DRM_FORMAT_ARGB8888:
16173 case DRM_FORMAT_ABGR8888:
16174 case DRM_FORMAT_XRGB2101010:
16175 case DRM_FORMAT_XBGR2101010:
16176 case DRM_FORMAT_ARGB2101010:
16177 case DRM_FORMAT_ABGR2101010:
16178 case DRM_FORMAT_XBGR16161616F:
16179 return modifier == DRM_FORMAT_MOD_LINEAR ||
16180 modifier == I915_FORMAT_MOD_X_TILED;
16186 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
16187 u32 format, u64 modifier)
16189 return modifier == DRM_FORMAT_MOD_LINEAR &&
16190 format == DRM_FORMAT_ARGB8888;
16193 static const struct drm_plane_funcs i965_plane_funcs = {
16194 .update_plane = drm_atomic_helper_update_plane,
16195 .disable_plane = drm_atomic_helper_disable_plane,
16196 .destroy = intel_plane_destroy,
16197 .atomic_duplicate_state = intel_plane_duplicate_state,
16198 .atomic_destroy_state = intel_plane_destroy_state,
16199 .format_mod_supported = i965_plane_format_mod_supported,
16202 static const struct drm_plane_funcs i8xx_plane_funcs = {
16203 .update_plane = drm_atomic_helper_update_plane,
16204 .disable_plane = drm_atomic_helper_disable_plane,
16205 .destroy = intel_plane_destroy,
16206 .atomic_duplicate_state = intel_plane_duplicate_state,
16207 .atomic_destroy_state = intel_plane_destroy_state,
16208 .format_mod_supported = i8xx_plane_format_mod_supported,
16212 intel_legacy_cursor_update(struct drm_plane *_plane,
16213 struct drm_crtc *_crtc,
16214 struct drm_framebuffer *fb,
16215 int crtc_x, int crtc_y,
16216 unsigned int crtc_w, unsigned int crtc_h,
16217 u32 src_x, u32 src_y,
16218 u32 src_w, u32 src_h,
16219 struct drm_modeset_acquire_ctx *ctx)
16221 struct intel_plane *plane = to_intel_plane(_plane);
16222 struct intel_crtc *crtc = to_intel_crtc(_crtc);
16223 struct intel_plane_state *old_plane_state =
16224 to_intel_plane_state(plane->base.state);
16225 struct intel_plane_state *new_plane_state;
16226 struct intel_crtc_state *crtc_state =
16227 to_intel_crtc_state(crtc->base.state);
16228 struct intel_crtc_state *new_crtc_state;
16232 * When crtc is inactive or there is a modeset pending,
16233 * wait for it to complete in the slowpath
16235 if (!crtc_state->hw.active || needs_modeset(crtc_state) ||
16236 crtc_state->update_pipe)
16240 * Don't do an async update if there is an outstanding commit modifying
16241 * the plane. This prevents our async update's changes from getting
16242 * overridden by a previous synchronous update's state.
16244 if (old_plane_state->uapi.commit &&
16245 !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done))
16249 * If any parameters change that may affect watermarks,
16250 * take the slowpath. Only changing fb or position should be
16253 if (old_plane_state->uapi.crtc != &crtc->base ||
16254 old_plane_state->uapi.src_w != src_w ||
16255 old_plane_state->uapi.src_h != src_h ||
16256 old_plane_state->uapi.crtc_w != crtc_w ||
16257 old_plane_state->uapi.crtc_h != crtc_h ||
16258 !old_plane_state->uapi.fb != !fb)
16261 new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base));
16262 if (!new_plane_state)
16265 new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base));
16266 if (!new_crtc_state) {
16271 drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb);
16273 new_plane_state->uapi.src_x = src_x;
16274 new_plane_state->uapi.src_y = src_y;
16275 new_plane_state->uapi.src_w = src_w;
16276 new_plane_state->uapi.src_h = src_h;
16277 new_plane_state->uapi.crtc_x = crtc_x;
16278 new_plane_state->uapi.crtc_y = crtc_y;
16279 new_plane_state->uapi.crtc_w = crtc_w;
16280 new_plane_state->uapi.crtc_h = crtc_h;
16282 intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state);
16284 ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
16285 old_plane_state, new_plane_state);
16289 ret = intel_plane_pin_fb(new_plane_state);
16293 intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb),
16295 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
16296 to_intel_frontbuffer(new_plane_state->hw.fb),
16297 plane->frontbuffer_bit);
16299 /* Swap plane state */
16300 plane->base.state = &new_plane_state->uapi;
16303 * We cannot swap crtc_state as it may be in use by an atomic commit or
16304 * page flip that's running simultaneously. If we swap crtc_state and
16305 * destroy the old state, we will cause a use-after-free there.
16307 * Only update active_planes, which is needed for our internal
16308 * bookkeeping. Either value will do the right thing when updating
16309 * planes atomically. If the cursor was part of the atomic update then
16310 * we would have taken the slowpath.
16312 crtc_state->active_planes = new_crtc_state->active_planes;
16314 if (new_plane_state->uapi.visible)
16315 intel_update_plane(plane, crtc_state, new_plane_state);
16317 intel_disable_plane(plane, crtc_state);
16319 intel_plane_unpin_fb(old_plane_state);
16322 if (new_crtc_state)
16323 intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
16325 intel_plane_destroy_state(&plane->base, &new_plane_state->uapi);
16327 intel_plane_destroy_state(&plane->base, &old_plane_state->uapi);
16331 return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb,
16332 crtc_x, crtc_y, crtc_w, crtc_h,
16333 src_x, src_y, src_w, src_h, ctx);
16336 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
16337 .update_plane = intel_legacy_cursor_update,
16338 .disable_plane = drm_atomic_helper_disable_plane,
16339 .destroy = intel_plane_destroy,
16340 .atomic_duplicate_state = intel_plane_duplicate_state,
16341 .atomic_destroy_state = intel_plane_destroy_state,
16342 .format_mod_supported = intel_cursor_format_mod_supported,
16345 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
16346 enum i9xx_plane_id i9xx_plane)
16348 if (!HAS_FBC(dev_priv))
16351 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
16352 return i9xx_plane == PLANE_A; /* tied to pipe A */
16353 else if (IS_IVYBRIDGE(dev_priv))
16354 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
16355 i9xx_plane == PLANE_C;
16356 else if (INTEL_GEN(dev_priv) >= 4)
16357 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
16359 return i9xx_plane == PLANE_A;
16362 static struct intel_plane *
16363 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
16365 struct intel_plane *plane;
16366 const struct drm_plane_funcs *plane_funcs;
16367 unsigned int supported_rotations;
16368 const u32 *formats;
16372 if (INTEL_GEN(dev_priv) >= 9)
16373 return skl_universal_plane_create(dev_priv, pipe,
16376 plane = intel_plane_alloc();
16380 plane->pipe = pipe;
16382 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
16383 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
16385 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4 &&
16386 INTEL_NUM_PIPES(dev_priv) == 2)
16387 plane->i9xx_plane = (enum i9xx_plane_id) !pipe;
16389 plane->i9xx_plane = (enum i9xx_plane_id) pipe;
16390 plane->id = PLANE_PRIMARY;
16391 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
16393 plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane);
16394 if (plane->has_fbc) {
16395 struct intel_fbc *fbc = &dev_priv->fbc;
16397 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
16400 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16401 formats = vlv_primary_formats;
16402 num_formats = ARRAY_SIZE(vlv_primary_formats);
16403 } else if (INTEL_GEN(dev_priv) >= 4) {
16405 * WaFP16GammaEnabling:ivb
16406 * "Workaround : When using the 64-bit format, the plane
16407 * output on each color channel has one quarter amplitude.
16408 * It can be brought up to full amplitude by using pipe
16409 * gamma correction or pipe color space conversion to
16410 * multiply the plane output by four."
16412 * There is no dedicated plane gamma for the primary plane,
16413 * and using the pipe gamma/csc could conflict with other
16414 * planes, so we choose not to expose fp16 on IVB primary
16415 * planes. HSW primary planes no longer have this problem.
16417 if (IS_IVYBRIDGE(dev_priv)) {
16418 formats = ivb_primary_formats;
16419 num_formats = ARRAY_SIZE(ivb_primary_formats);
16421 formats = i965_primary_formats;
16422 num_formats = ARRAY_SIZE(i965_primary_formats);
16425 formats = i8xx_primary_formats;
16426 num_formats = ARRAY_SIZE(i8xx_primary_formats);
16429 if (INTEL_GEN(dev_priv) >= 4)
16430 plane_funcs = &i965_plane_funcs;
16432 plane_funcs = &i8xx_plane_funcs;
16434 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16435 plane->min_cdclk = vlv_plane_min_cdclk;
16436 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
16437 plane->min_cdclk = hsw_plane_min_cdclk;
16438 else if (IS_IVYBRIDGE(dev_priv))
16439 plane->min_cdclk = ivb_plane_min_cdclk;
16441 plane->min_cdclk = i9xx_plane_min_cdclk;
16443 plane->max_stride = i9xx_plane_max_stride;
16444 plane->update_plane = i9xx_update_plane;
16445 plane->disable_plane = i9xx_disable_plane;
16446 plane->get_hw_state = i9xx_plane_get_hw_state;
16447 plane->check_plane = i9xx_plane_check;
16449 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
16450 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
16452 formats, num_formats,
16453 i9xx_format_modifiers,
16454 DRM_PLANE_TYPE_PRIMARY,
16455 "primary %c", pipe_name(pipe));
16457 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
16459 formats, num_formats,
16460 i9xx_format_modifiers,
16461 DRM_PLANE_TYPE_PRIMARY,
16463 plane_name(plane->i9xx_plane));
16467 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
16468 supported_rotations =
16469 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
16470 DRM_MODE_REFLECT_X;
16471 } else if (INTEL_GEN(dev_priv) >= 4) {
16472 supported_rotations =
16473 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
16475 supported_rotations = DRM_MODE_ROTATE_0;
16478 if (INTEL_GEN(dev_priv) >= 4)
16479 drm_plane_create_rotation_property(&plane->base,
16481 supported_rotations);
16484 drm_plane_create_zpos_immutable_property(&plane->base, zpos);
16486 drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
16491 intel_plane_free(plane);
16493 return ERR_PTR(ret);
16496 static struct intel_plane *
16497 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
16500 struct intel_plane *cursor;
16503 cursor = intel_plane_alloc();
16504 if (IS_ERR(cursor))
16507 cursor->pipe = pipe;
16508 cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
16509 cursor->id = PLANE_CURSOR;
16510 cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
16512 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
16513 cursor->max_stride = i845_cursor_max_stride;
16514 cursor->update_plane = i845_update_cursor;
16515 cursor->disable_plane = i845_disable_cursor;
16516 cursor->get_hw_state = i845_cursor_get_hw_state;
16517 cursor->check_plane = i845_check_cursor;
16519 cursor->max_stride = i9xx_cursor_max_stride;
16520 cursor->update_plane = i9xx_update_cursor;
16521 cursor->disable_plane = i9xx_disable_cursor;
16522 cursor->get_hw_state = i9xx_cursor_get_hw_state;
16523 cursor->check_plane = i9xx_check_cursor;
16526 cursor->cursor.base = ~0;
16527 cursor->cursor.cntl = ~0;
16529 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
16530 cursor->cursor.size = ~0;
16532 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
16533 0, &intel_cursor_plane_funcs,
16534 intel_cursor_formats,
16535 ARRAY_SIZE(intel_cursor_formats),
16536 cursor_format_modifiers,
16537 DRM_PLANE_TYPE_CURSOR,
16538 "cursor %c", pipe_name(pipe));
16542 if (INTEL_GEN(dev_priv) >= 4)
16543 drm_plane_create_rotation_property(&cursor->base,
16545 DRM_MODE_ROTATE_0 |
16546 DRM_MODE_ROTATE_180);
16548 zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
16549 drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
16551 if (INTEL_GEN(dev_priv) >= 12)
16552 drm_plane_enable_fb_damage_clips(&cursor->base);
16554 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
16559 intel_plane_free(cursor);
16561 return ERR_PTR(ret);
16564 #define INTEL_CRTC_FUNCS \
16565 .gamma_set = drm_atomic_helper_legacy_gamma_set, \
16566 .set_config = drm_atomic_helper_set_config, \
16567 .destroy = intel_crtc_destroy, \
16568 .page_flip = drm_atomic_helper_page_flip, \
16569 .atomic_duplicate_state = intel_crtc_duplicate_state, \
16570 .atomic_destroy_state = intel_crtc_destroy_state, \
16571 .set_crc_source = intel_crtc_set_crc_source, \
16572 .verify_crc_source = intel_crtc_verify_crc_source, \
16573 .get_crc_sources = intel_crtc_get_crc_sources
16575 static const struct drm_crtc_funcs bdw_crtc_funcs = {
16578 .get_vblank_counter = g4x_get_vblank_counter,
16579 .enable_vblank = bdw_enable_vblank,
16580 .disable_vblank = bdw_disable_vblank,
16581 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16584 static const struct drm_crtc_funcs ilk_crtc_funcs = {
16587 .get_vblank_counter = g4x_get_vblank_counter,
16588 .enable_vblank = ilk_enable_vblank,
16589 .disable_vblank = ilk_disable_vblank,
16590 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16593 static const struct drm_crtc_funcs g4x_crtc_funcs = {
16596 .get_vblank_counter = g4x_get_vblank_counter,
16597 .enable_vblank = i965_enable_vblank,
16598 .disable_vblank = i965_disable_vblank,
16599 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16602 static const struct drm_crtc_funcs i965_crtc_funcs = {
16605 .get_vblank_counter = i915_get_vblank_counter,
16606 .enable_vblank = i965_enable_vblank,
16607 .disable_vblank = i965_disable_vblank,
16608 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16611 static const struct drm_crtc_funcs i915gm_crtc_funcs = {
16614 .get_vblank_counter = i915_get_vblank_counter,
16615 .enable_vblank = i915gm_enable_vblank,
16616 .disable_vblank = i915gm_disable_vblank,
16617 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16620 static const struct drm_crtc_funcs i915_crtc_funcs = {
16623 .get_vblank_counter = i915_get_vblank_counter,
16624 .enable_vblank = i8xx_enable_vblank,
16625 .disable_vblank = i8xx_disable_vblank,
16626 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16629 static const struct drm_crtc_funcs i8xx_crtc_funcs = {
16632 /* no hw vblank counter */
16633 .enable_vblank = i8xx_enable_vblank,
16634 .disable_vblank = i8xx_disable_vblank,
16635 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16638 static struct intel_crtc *intel_crtc_alloc(void)
16640 struct intel_crtc_state *crtc_state;
16641 struct intel_crtc *crtc;
16643 crtc = kzalloc(sizeof(*crtc), GFP_KERNEL);
16645 return ERR_PTR(-ENOMEM);
16647 crtc_state = intel_crtc_state_alloc(crtc);
16650 return ERR_PTR(-ENOMEM);
16653 crtc->base.state = &crtc_state->uapi;
16654 crtc->config = crtc_state;
16659 static void intel_crtc_free(struct intel_crtc *crtc)
16661 intel_crtc_destroy_state(&crtc->base, crtc->base.state);
16665 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv)
16667 struct intel_plane *plane;
16669 for_each_intel_plane(&dev_priv->drm, plane) {
16670 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
16673 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base);
16677 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
16679 struct intel_plane *primary, *cursor;
16680 const struct drm_crtc_funcs *funcs;
16681 struct intel_crtc *crtc;
16684 crtc = intel_crtc_alloc();
16686 return PTR_ERR(crtc);
16689 crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[pipe];
16691 primary = intel_primary_plane_create(dev_priv, pipe);
16692 if (IS_ERR(primary)) {
16693 ret = PTR_ERR(primary);
16696 crtc->plane_ids_mask |= BIT(primary->id);
16698 for_each_sprite(dev_priv, pipe, sprite) {
16699 struct intel_plane *plane;
16701 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
16702 if (IS_ERR(plane)) {
16703 ret = PTR_ERR(plane);
16706 crtc->plane_ids_mask |= BIT(plane->id);
16709 cursor = intel_cursor_plane_create(dev_priv, pipe);
16710 if (IS_ERR(cursor)) {
16711 ret = PTR_ERR(cursor);
16714 crtc->plane_ids_mask |= BIT(cursor->id);
16716 if (HAS_GMCH(dev_priv)) {
16717 if (IS_CHERRYVIEW(dev_priv) ||
16718 IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv))
16719 funcs = &g4x_crtc_funcs;
16720 else if (IS_GEN(dev_priv, 4))
16721 funcs = &i965_crtc_funcs;
16722 else if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv))
16723 funcs = &i915gm_crtc_funcs;
16724 else if (IS_GEN(dev_priv, 3))
16725 funcs = &i915_crtc_funcs;
16727 funcs = &i8xx_crtc_funcs;
16729 if (INTEL_GEN(dev_priv) >= 8)
16730 funcs = &bdw_crtc_funcs;
16732 funcs = &ilk_crtc_funcs;
16735 ret = drm_crtc_init_with_planes(&dev_priv->drm, &crtc->base,
16736 &primary->base, &cursor->base,
16737 funcs, "pipe %c", pipe_name(pipe));
16741 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
16742 dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
16743 dev_priv->pipe_to_crtc_mapping[pipe] = crtc;
16745 if (INTEL_GEN(dev_priv) < 9) {
16746 enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
16748 BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
16749 dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
16750 dev_priv->plane_to_crtc_mapping[i9xx_plane] = crtc;
16753 intel_color_init(crtc);
16755 intel_crtc_crc_init(crtc);
16757 drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) != crtc->pipe);
16762 intel_crtc_free(crtc);
16767 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
16768 struct drm_file *file)
16770 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
16771 struct drm_crtc *drmmode_crtc;
16772 struct intel_crtc *crtc;
16774 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
16778 crtc = to_intel_crtc(drmmode_crtc);
16779 pipe_from_crtc_id->pipe = crtc->pipe;
16784 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
16786 struct drm_device *dev = encoder->base.dev;
16787 struct intel_encoder *source_encoder;
16788 u32 possible_clones = 0;
16790 for_each_intel_encoder(dev, source_encoder) {
16791 if (encoders_cloneable(encoder, source_encoder))
16792 possible_clones |= drm_encoder_mask(&source_encoder->base);
16795 return possible_clones;
16798 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
16800 struct drm_device *dev = encoder->base.dev;
16801 struct intel_crtc *crtc;
16802 u32 possible_crtcs = 0;
16804 for_each_intel_crtc(dev, crtc) {
16805 if (encoder->pipe_mask & BIT(crtc->pipe))
16806 possible_crtcs |= drm_crtc_mask(&crtc->base);
16809 return possible_crtcs;
16812 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
16814 if (!IS_MOBILE(dev_priv))
16817 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)
16820 if (IS_GEN(dev_priv, 5) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
16826 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
16828 if (INTEL_GEN(dev_priv) >= 9)
16831 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
16834 if (HAS_PCH_LPT_H(dev_priv) &&
16835 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
16838 /* DDI E can't be used if DDI A requires 4 lanes */
16839 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
16842 if (!dev_priv->vbt.int_crt_support)
16848 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
16853 if (HAS_DDI(dev_priv))
16856 * This w/a is needed at least on CPT/PPT, but to be sure apply it
16857 * everywhere where registers can be write protected.
16859 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16864 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
16865 u32 val = intel_de_read(dev_priv, PP_CONTROL(pps_idx));
16867 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
16868 intel_de_write(dev_priv, PP_CONTROL(pps_idx), val);
16872 static void intel_pps_init(struct drm_i915_private *dev_priv)
16874 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
16875 dev_priv->pps_mmio_base = PCH_PPS_BASE;
16876 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16877 dev_priv->pps_mmio_base = VLV_PPS_BASE;
16879 dev_priv->pps_mmio_base = PPS_BASE;
16881 intel_pps_unlock_regs_wa(dev_priv);
16884 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
16886 struct intel_encoder *encoder;
16887 bool dpd_is_edp = false;
16889 intel_pps_init(dev_priv);
16891 if (!HAS_DISPLAY(dev_priv))
16894 if (IS_ROCKETLAKE(dev_priv)) {
16895 intel_ddi_init(dev_priv, PORT_A);
16896 intel_ddi_init(dev_priv, PORT_B);
16897 intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */
16898 intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */
16899 } else if (INTEL_GEN(dev_priv) >= 12) {
16900 intel_ddi_init(dev_priv, PORT_A);
16901 intel_ddi_init(dev_priv, PORT_B);
16902 intel_ddi_init(dev_priv, PORT_D);
16903 intel_ddi_init(dev_priv, PORT_E);
16904 intel_ddi_init(dev_priv, PORT_F);
16905 intel_ddi_init(dev_priv, PORT_G);
16906 intel_ddi_init(dev_priv, PORT_H);
16907 intel_ddi_init(dev_priv, PORT_I);
16908 icl_dsi_init(dev_priv);
16909 } else if (IS_ELKHARTLAKE(dev_priv)) {
16910 intel_ddi_init(dev_priv, PORT_A);
16911 intel_ddi_init(dev_priv, PORT_B);
16912 intel_ddi_init(dev_priv, PORT_C);
16913 intel_ddi_init(dev_priv, PORT_D);
16914 icl_dsi_init(dev_priv);
16915 } else if (IS_GEN(dev_priv, 11)) {
16916 intel_ddi_init(dev_priv, PORT_A);
16917 intel_ddi_init(dev_priv, PORT_B);
16918 intel_ddi_init(dev_priv, PORT_C);
16919 intel_ddi_init(dev_priv, PORT_D);
16920 intel_ddi_init(dev_priv, PORT_E);
16922 * On some ICL SKUs port F is not present. No strap bits for
16923 * this, so rely on VBT.
16924 * Work around broken VBTs on SKUs known to have no port F.
16926 if (IS_ICL_WITH_PORT_F(dev_priv) &&
16927 intel_bios_is_port_present(dev_priv, PORT_F))
16928 intel_ddi_init(dev_priv, PORT_F);
16930 icl_dsi_init(dev_priv);
16931 } else if (IS_GEN9_LP(dev_priv)) {
16933 * FIXME: Broxton doesn't support port detection via the
16934 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
16935 * detect the ports.
16937 intel_ddi_init(dev_priv, PORT_A);
16938 intel_ddi_init(dev_priv, PORT_B);
16939 intel_ddi_init(dev_priv, PORT_C);
16941 vlv_dsi_init(dev_priv);
16942 } else if (HAS_DDI(dev_priv)) {
16945 if (intel_ddi_crt_present(dev_priv))
16946 intel_crt_init(dev_priv);
16949 * Haswell uses DDI functions to detect digital outputs.
16950 * On SKL pre-D0 the strap isn't connected, so we assume
16953 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
16954 /* WaIgnoreDDIAStrap: skl */
16955 if (found || IS_GEN9_BC(dev_priv))
16956 intel_ddi_init(dev_priv, PORT_A);
16958 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
16960 found = intel_de_read(dev_priv, SFUSE_STRAP);
16962 if (found & SFUSE_STRAP_DDIB_DETECTED)
16963 intel_ddi_init(dev_priv, PORT_B);
16964 if (found & SFUSE_STRAP_DDIC_DETECTED)
16965 intel_ddi_init(dev_priv, PORT_C);
16966 if (found & SFUSE_STRAP_DDID_DETECTED)
16967 intel_ddi_init(dev_priv, PORT_D);
16968 if (found & SFUSE_STRAP_DDIF_DETECTED)
16969 intel_ddi_init(dev_priv, PORT_F);
16971 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
16973 if (IS_GEN9_BC(dev_priv) &&
16974 intel_bios_is_port_present(dev_priv, PORT_E))
16975 intel_ddi_init(dev_priv, PORT_E);
16977 } else if (HAS_PCH_SPLIT(dev_priv)) {
16981 * intel_edp_init_connector() depends on this completing first,
16982 * to prevent the registration of both eDP and LVDS and the
16983 * incorrect sharing of the PPS.
16985 intel_lvds_init(dev_priv);
16986 intel_crt_init(dev_priv);
16988 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
16990 if (ilk_has_edp_a(dev_priv))
16991 intel_dp_init(dev_priv, DP_A, PORT_A);
16993 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
16994 /* PCH SDVOB multiplex with HDMIB */
16995 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
16997 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
16998 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
16999 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
17002 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
17003 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
17005 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED)
17006 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
17008 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
17009 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
17011 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
17012 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
17013 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
17014 bool has_edp, has_port;
17016 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
17017 intel_crt_init(dev_priv);
17020 * The DP_DETECTED bit is the latched state of the DDC
17021 * SDA pin at boot. However since eDP doesn't require DDC
17022 * (no way to plug in a DP->HDMI dongle) the DDC pins for
17023 * eDP ports may have been muxed to an alternate function.
17024 * Thus we can't rely on the DP_DETECTED bit alone to detect
17025 * eDP ports. Consult the VBT as well as DP_DETECTED to
17026 * detect eDP ports.
17028 * Sadly the straps seem to be missing sometimes even for HDMI
17029 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
17030 * and VBT for the presence of the port. Additionally we can't
17031 * trust the port type the VBT declares as we've seen at least
17032 * HDMI ports that the VBT claim are DP or eDP.
17034 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
17035 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
17036 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
17037 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
17038 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
17039 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
17041 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
17042 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
17043 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
17044 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
17045 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
17046 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
17048 if (IS_CHERRYVIEW(dev_priv)) {
17050 * eDP not supported on port D,
17051 * so no need to worry about it
17053 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
17054 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
17055 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
17056 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
17057 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
17060 vlv_dsi_init(dev_priv);
17061 } else if (IS_PINEVIEW(dev_priv)) {
17062 intel_lvds_init(dev_priv);
17063 intel_crt_init(dev_priv);
17064 } else if (IS_GEN_RANGE(dev_priv, 3, 4)) {
17065 bool found = false;
17067 if (IS_MOBILE(dev_priv))
17068 intel_lvds_init(dev_priv);
17070 intel_crt_init(dev_priv);
17072 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
17073 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
17074 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
17075 if (!found && IS_G4X(dev_priv)) {
17076 drm_dbg_kms(&dev_priv->drm,
17077 "probing HDMI on SDVOB\n");
17078 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
17081 if (!found && IS_G4X(dev_priv))
17082 intel_dp_init(dev_priv, DP_B, PORT_B);
17085 /* Before G4X SDVOC doesn't have its own detect register */
17087 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
17088 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");
17089 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
17092 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) {
17094 if (IS_G4X(dev_priv)) {
17095 drm_dbg_kms(&dev_priv->drm,
17096 "probing HDMI on SDVOC\n");
17097 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
17099 if (IS_G4X(dev_priv))
17100 intel_dp_init(dev_priv, DP_C, PORT_C);
17103 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED))
17104 intel_dp_init(dev_priv, DP_D, PORT_D);
17106 if (SUPPORTS_TV(dev_priv))
17107 intel_tv_init(dev_priv);
17108 } else if (IS_GEN(dev_priv, 2)) {
17109 if (IS_I85X(dev_priv))
17110 intel_lvds_init(dev_priv);
17112 intel_crt_init(dev_priv);
17113 intel_dvo_init(dev_priv);
17116 intel_psr_init(dev_priv);
17118 for_each_intel_encoder(&dev_priv->drm, encoder) {
17119 encoder->base.possible_crtcs =
17120 intel_encoder_possible_crtcs(encoder);
17121 encoder->base.possible_clones =
17122 intel_encoder_possible_clones(encoder);
17125 intel_init_pch_refclk(dev_priv);
17127 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
17130 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
17132 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
17134 drm_framebuffer_cleanup(fb);
17135 intel_frontbuffer_put(intel_fb->frontbuffer);
17140 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
17141 struct drm_file *file,
17142 unsigned int *handle)
17144 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
17145 struct drm_i915_private *i915 = to_i915(obj->base.dev);
17147 if (obj->userptr.mm) {
17148 drm_dbg(&i915->drm,
17149 "attempting to use a userptr for a framebuffer, denied\n");
17153 return drm_gem_handle_create(file, &obj->base, handle);
17156 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
17157 struct drm_file *file,
17158 unsigned flags, unsigned color,
17159 struct drm_clip_rect *clips,
17160 unsigned num_clips)
17162 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
17164 i915_gem_object_flush_if_display(obj);
17165 intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
17170 static const struct drm_framebuffer_funcs intel_fb_funcs = {
17171 .destroy = intel_user_framebuffer_destroy,
17172 .create_handle = intel_user_framebuffer_create_handle,
17173 .dirty = intel_user_framebuffer_dirty,
17176 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
17177 struct drm_i915_gem_object *obj,
17178 struct drm_mode_fb_cmd2 *mode_cmd)
17180 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
17181 struct drm_framebuffer *fb = &intel_fb->base;
17183 unsigned int tiling, stride;
17187 intel_fb->frontbuffer = intel_frontbuffer_get(obj);
17188 if (!intel_fb->frontbuffer)
17191 i915_gem_object_lock(obj, NULL);
17192 tiling = i915_gem_object_get_tiling(obj);
17193 stride = i915_gem_object_get_stride(obj);
17194 i915_gem_object_unlock(obj);
17196 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
17198 * If there's a fence, enforce that
17199 * the fb modifier and tiling mode match.
17201 if (tiling != I915_TILING_NONE &&
17202 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
17203 drm_dbg_kms(&dev_priv->drm,
17204 "tiling_mode doesn't match fb modifier\n");
17208 if (tiling == I915_TILING_X) {
17209 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
17210 } else if (tiling == I915_TILING_Y) {
17211 drm_dbg_kms(&dev_priv->drm,
17212 "No Y tiling for legacy addfb\n");
17217 if (!drm_any_plane_has_format(&dev_priv->drm,
17218 mode_cmd->pixel_format,
17219 mode_cmd->modifier[0])) {
17220 struct drm_format_name_buf format_name;
17222 drm_dbg_kms(&dev_priv->drm,
17223 "unsupported pixel format %s / modifier 0x%llx\n",
17224 drm_get_format_name(mode_cmd->pixel_format,
17226 mode_cmd->modifier[0]);
17231 * gen2/3 display engine uses the fence if present,
17232 * so the tiling mode must match the fb modifier exactly.
17234 if (INTEL_GEN(dev_priv) < 4 &&
17235 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
17236 drm_dbg_kms(&dev_priv->drm,
17237 "tiling_mode must match fb modifier exactly on gen2/3\n");
17241 max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
17242 mode_cmd->modifier[0]);
17243 if (mode_cmd->pitches[0] > max_stride) {
17244 drm_dbg_kms(&dev_priv->drm,
17245 "%s pitch (%u) must be at most %d\n",
17246 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
17247 "tiled" : "linear",
17248 mode_cmd->pitches[0], max_stride);
17253 * If there's a fence, enforce that
17254 * the fb pitch and fence stride match.
17256 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
17257 drm_dbg_kms(&dev_priv->drm,
17258 "pitch (%d) must match tiling stride (%d)\n",
17259 mode_cmd->pitches[0], stride);
17263 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
17264 if (mode_cmd->offsets[0] != 0) {
17265 drm_dbg_kms(&dev_priv->drm,
17266 "plane 0 offset (0x%08x) must be 0\n",
17267 mode_cmd->offsets[0]);
17271 drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
17273 for (i = 0; i < fb->format->num_planes; i++) {
17274 u32 stride_alignment;
17276 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
17277 drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n",
17282 stride_alignment = intel_fb_stride_alignment(fb, i);
17283 if (fb->pitches[i] & (stride_alignment - 1)) {
17284 drm_dbg_kms(&dev_priv->drm,
17285 "plane %d pitch (%d) must be at least %u byte aligned\n",
17286 i, fb->pitches[i], stride_alignment);
17290 if (is_gen12_ccs_plane(fb, i)) {
17291 int ccs_aux_stride = gen12_ccs_aux_stride(fb, i);
17293 if (fb->pitches[i] != ccs_aux_stride) {
17294 drm_dbg_kms(&dev_priv->drm,
17295 "ccs aux plane %d pitch (%d) must be %d\n",
17297 fb->pitches[i], ccs_aux_stride);
17302 fb->obj[i] = &obj->base;
17305 ret = intel_fill_fb_info(dev_priv, fb);
17309 ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
17311 drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret);
17318 intel_frontbuffer_put(intel_fb->frontbuffer);
17322 static struct drm_framebuffer *
17323 intel_user_framebuffer_create(struct drm_device *dev,
17324 struct drm_file *filp,
17325 const struct drm_mode_fb_cmd2 *user_mode_cmd)
17327 struct drm_framebuffer *fb;
17328 struct drm_i915_gem_object *obj;
17329 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
17331 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
17333 return ERR_PTR(-ENOENT);
17335 fb = intel_framebuffer_create(obj, &mode_cmd);
17336 i915_gem_object_put(obj);
17341 static enum drm_mode_status
17342 intel_mode_valid(struct drm_device *dev,
17343 const struct drm_display_mode *mode)
17345 struct drm_i915_private *dev_priv = to_i915(dev);
17346 int hdisplay_max, htotal_max;
17347 int vdisplay_max, vtotal_max;
17350 * Can't reject DBLSCAN here because Xorg ddxen can add piles
17351 * of DBLSCAN modes to the output's mode list when they detect
17352 * the scaling mode property on the connector. And they don't
17353 * ask the kernel to validate those modes in any way until
17354 * modeset time at which point the client gets a protocol error.
17355 * So in order to not upset those clients we silently ignore the
17356 * DBLSCAN flag on such connectors. For other connectors we will
17357 * reject modes with the DBLSCAN flag in encoder->compute_config().
17358 * And we always reject DBLSCAN modes in connector->mode_valid()
17359 * as we never want such modes on the connector's mode list.
17362 if (mode->vscan > 1)
17363 return MODE_NO_VSCAN;
17365 if (mode->flags & DRM_MODE_FLAG_HSKEW)
17366 return MODE_H_ILLEGAL;
17368 if (mode->flags & (DRM_MODE_FLAG_CSYNC |
17369 DRM_MODE_FLAG_NCSYNC |
17370 DRM_MODE_FLAG_PCSYNC))
17373 if (mode->flags & (DRM_MODE_FLAG_BCAST |
17374 DRM_MODE_FLAG_PIXMUX |
17375 DRM_MODE_FLAG_CLKDIV2))
17378 /* Transcoder timing limits */
17379 if (INTEL_GEN(dev_priv) >= 11) {
17380 hdisplay_max = 16384;
17381 vdisplay_max = 8192;
17382 htotal_max = 16384;
17384 } else if (INTEL_GEN(dev_priv) >= 9 ||
17385 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
17386 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
17387 vdisplay_max = 4096;
17390 } else if (INTEL_GEN(dev_priv) >= 3) {
17391 hdisplay_max = 4096;
17392 vdisplay_max = 4096;
17396 hdisplay_max = 2048;
17397 vdisplay_max = 2048;
17402 if (mode->hdisplay > hdisplay_max ||
17403 mode->hsync_start > htotal_max ||
17404 mode->hsync_end > htotal_max ||
17405 mode->htotal > htotal_max)
17406 return MODE_H_ILLEGAL;
17408 if (mode->vdisplay > vdisplay_max ||
17409 mode->vsync_start > vtotal_max ||
17410 mode->vsync_end > vtotal_max ||
17411 mode->vtotal > vtotal_max)
17412 return MODE_V_ILLEGAL;
17414 if (INTEL_GEN(dev_priv) >= 5) {
17415 if (mode->hdisplay < 64 ||
17416 mode->htotal - mode->hdisplay < 32)
17417 return MODE_H_ILLEGAL;
17419 if (mode->vtotal - mode->vdisplay < 5)
17420 return MODE_V_ILLEGAL;
17422 if (mode->htotal - mode->hdisplay < 32)
17423 return MODE_H_ILLEGAL;
17425 if (mode->vtotal - mode->vdisplay < 3)
17426 return MODE_V_ILLEGAL;
17432 enum drm_mode_status
17433 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
17434 const struct drm_display_mode *mode)
17436 int plane_width_max, plane_height_max;
17439 * intel_mode_valid() should be
17440 * sufficient on older platforms.
17442 if (INTEL_GEN(dev_priv) < 9)
17446 * Most people will probably want a fullscreen
17447 * plane so let's not advertize modes that are
17448 * too big for that.
17450 if (INTEL_GEN(dev_priv) >= 11) {
17451 plane_width_max = 5120;
17452 plane_height_max = 4320;
17454 plane_width_max = 5120;
17455 plane_height_max = 4096;
17458 if (mode->hdisplay > plane_width_max)
17459 return MODE_H_ILLEGAL;
17461 if (mode->vdisplay > plane_height_max)
17462 return MODE_V_ILLEGAL;
17467 static const struct drm_mode_config_funcs intel_mode_funcs = {
17468 .fb_create = intel_user_framebuffer_create,
17469 .get_format_info = intel_get_format_info,
17470 .output_poll_changed = intel_fbdev_output_poll_changed,
17471 .mode_valid = intel_mode_valid,
17472 .atomic_check = intel_atomic_check,
17473 .atomic_commit = intel_atomic_commit,
17474 .atomic_state_alloc = intel_atomic_state_alloc,
17475 .atomic_state_clear = intel_atomic_state_clear,
17476 .atomic_state_free = intel_atomic_state_free,
17480 * intel_init_display_hooks - initialize the display modesetting hooks
17481 * @dev_priv: device private
17483 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
17485 intel_init_cdclk_hooks(dev_priv);
17487 if (INTEL_GEN(dev_priv) >= 9) {
17488 dev_priv->display.get_pipe_config = hsw_get_pipe_config;
17489 dev_priv->display.get_initial_plane_config =
17490 skl_get_initial_plane_config;
17491 dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock;
17492 dev_priv->display.crtc_enable = hsw_crtc_enable;
17493 dev_priv->display.crtc_disable = hsw_crtc_disable;
17494 } else if (HAS_DDI(dev_priv)) {
17495 dev_priv->display.get_pipe_config = hsw_get_pipe_config;
17496 dev_priv->display.get_initial_plane_config =
17497 i9xx_get_initial_plane_config;
17498 dev_priv->display.crtc_compute_clock =
17499 hsw_crtc_compute_clock;
17500 dev_priv->display.crtc_enable = hsw_crtc_enable;
17501 dev_priv->display.crtc_disable = hsw_crtc_disable;
17502 } else if (HAS_PCH_SPLIT(dev_priv)) {
17503 dev_priv->display.get_pipe_config = ilk_get_pipe_config;
17504 dev_priv->display.get_initial_plane_config =
17505 i9xx_get_initial_plane_config;
17506 dev_priv->display.crtc_compute_clock =
17507 ilk_crtc_compute_clock;
17508 dev_priv->display.crtc_enable = ilk_crtc_enable;
17509 dev_priv->display.crtc_disable = ilk_crtc_disable;
17510 } else if (IS_CHERRYVIEW(dev_priv)) {
17511 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17512 dev_priv->display.get_initial_plane_config =
17513 i9xx_get_initial_plane_config;
17514 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
17515 dev_priv->display.crtc_enable = valleyview_crtc_enable;
17516 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17517 } else if (IS_VALLEYVIEW(dev_priv)) {
17518 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17519 dev_priv->display.get_initial_plane_config =
17520 i9xx_get_initial_plane_config;
17521 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
17522 dev_priv->display.crtc_enable = valleyview_crtc_enable;
17523 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17524 } else if (IS_G4X(dev_priv)) {
17525 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17526 dev_priv->display.get_initial_plane_config =
17527 i9xx_get_initial_plane_config;
17528 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
17529 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17530 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17531 } else if (IS_PINEVIEW(dev_priv)) {
17532 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17533 dev_priv->display.get_initial_plane_config =
17534 i9xx_get_initial_plane_config;
17535 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
17536 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17537 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17538 } else if (!IS_GEN(dev_priv, 2)) {
17539 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17540 dev_priv->display.get_initial_plane_config =
17541 i9xx_get_initial_plane_config;
17542 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
17543 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17544 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17546 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17547 dev_priv->display.get_initial_plane_config =
17548 i9xx_get_initial_plane_config;
17549 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
17550 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17551 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17554 if (IS_GEN(dev_priv, 5)) {
17555 dev_priv->display.fdi_link_train = ilk_fdi_link_train;
17556 } else if (IS_GEN(dev_priv, 6)) {
17557 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
17558 } else if (IS_IVYBRIDGE(dev_priv)) {
17559 /* FIXME: detect B0+ stepping and use auto training */
17560 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
17563 if (INTEL_GEN(dev_priv) >= 9)
17564 dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables;
17566 dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables;
17570 void intel_modeset_init_hw(struct drm_i915_private *i915)
17572 struct intel_cdclk_state *cdclk_state =
17573 to_intel_cdclk_state(i915->cdclk.obj.state);
17574 struct intel_dbuf_state *dbuf_state =
17575 to_intel_dbuf_state(i915->dbuf.obj.state);
17577 intel_update_cdclk(i915);
17578 intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
17579 cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;
17581 dbuf_state->enabled_slices = i915->dbuf.enabled_slices;
17584 static int sanitize_watermarks_add_affected(struct drm_atomic_state *state)
17586 struct drm_plane *plane;
17587 struct intel_crtc *crtc;
17589 for_each_intel_crtc(state->dev, crtc) {
17590 struct intel_crtc_state *crtc_state;
17592 crtc_state = intel_atomic_get_crtc_state(state, crtc);
17593 if (IS_ERR(crtc_state))
17594 return PTR_ERR(crtc_state);
17596 if (crtc_state->hw.active) {
17598 * Preserve the inherited flag to avoid
17599 * taking the full modeset path.
17601 crtc_state->inherited = true;
17605 drm_for_each_plane(plane, state->dev) {
17606 struct drm_plane_state *plane_state;
17608 plane_state = drm_atomic_get_plane_state(state, plane);
17609 if (IS_ERR(plane_state))
17610 return PTR_ERR(plane_state);
17617 * Calculate what we think the watermarks should be for the state we've read
17618 * out of the hardware and then immediately program those watermarks so that
17619 * we ensure the hardware settings match our internal state.
17621 * We can calculate what we think WM's should be by creating a duplicate of the
17622 * current state (which was constructed during hardware readout) and running it
17623 * through the atomic check code to calculate new watermark values in the
17626 static void sanitize_watermarks(struct drm_i915_private *dev_priv)
17628 struct drm_atomic_state *state;
17629 struct intel_atomic_state *intel_state;
17630 struct intel_crtc *crtc;
17631 struct intel_crtc_state *crtc_state;
17632 struct drm_modeset_acquire_ctx ctx;
17636 /* Only supported on platforms that use atomic watermark design */
17637 if (!dev_priv->display.optimize_watermarks)
17640 state = drm_atomic_state_alloc(&dev_priv->drm);
17641 if (drm_WARN_ON(&dev_priv->drm, !state))
17644 intel_state = to_intel_atomic_state(state);
17646 drm_modeset_acquire_init(&ctx, 0);
17649 state->acquire_ctx = &ctx;
17652 * Hardware readout is the only time we don't want to calculate
17653 * intermediate watermarks (since we don't trust the current
17656 if (!HAS_GMCH(dev_priv))
17657 intel_state->skip_intermediate_wm = true;
17659 ret = sanitize_watermarks_add_affected(state);
17663 ret = intel_atomic_check(&dev_priv->drm, state);
17667 /* Write calculated watermark values back */
17668 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
17669 crtc_state->wm.need_postvbl_update = true;
17670 dev_priv->display.optimize_watermarks(intel_state, crtc);
17672 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
17676 if (ret == -EDEADLK) {
17677 drm_atomic_state_clear(state);
17678 drm_modeset_backoff(&ctx);
17683 * If we fail here, it means that the hardware appears to be
17684 * programmed in a way that shouldn't be possible, given our
17685 * understanding of watermark requirements. This might mean a
17686 * mistake in the hardware readout code or a mistake in the
17687 * watermark calculations for a given platform. Raise a WARN
17688 * so that this is noticeable.
17690 * If this actually happens, we'll have to just leave the
17691 * BIOS-programmed watermarks untouched and hope for the best.
17693 drm_WARN(&dev_priv->drm, ret,
17694 "Could not determine valid watermarks for inherited state\n");
17696 drm_atomic_state_put(state);
17698 drm_modeset_drop_locks(&ctx);
17699 drm_modeset_acquire_fini(&ctx);
17702 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
17704 if (IS_GEN(dev_priv, 5)) {
17706 intel_de_read(dev_priv, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
17708 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
17709 } else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) {
17710 dev_priv->fdi_pll_freq = 270000;
17715 drm_dbg(&dev_priv->drm, "FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
17718 static int intel_initial_commit(struct drm_device *dev)
17720 struct drm_atomic_state *state = NULL;
17721 struct drm_modeset_acquire_ctx ctx;
17722 struct intel_crtc *crtc;
17725 state = drm_atomic_state_alloc(dev);
17729 drm_modeset_acquire_init(&ctx, 0);
17732 state->acquire_ctx = &ctx;
17734 for_each_intel_crtc(dev, crtc) {
17735 struct intel_crtc_state *crtc_state =
17736 intel_atomic_get_crtc_state(state, crtc);
17738 if (IS_ERR(crtc_state)) {
17739 ret = PTR_ERR(crtc_state);
17743 if (crtc_state->hw.active) {
17745 * We've not yet detected sink capabilities
17746 * (audio,infoframes,etc.) and thus we don't want to
17747 * force a full state recomputation yet. We want that to
17748 * happen only for the first real commit from userspace.
17749 * So preserve the inherited flag for the time being.
17751 crtc_state->inherited = true;
17753 ret = drm_atomic_add_affected_planes(state, &crtc->base);
17758 * FIXME hack to force a LUT update to avoid the
17759 * plane update forcing the pipe gamma on without
17760 * having a proper LUT loaded. Remove once we
17761 * have readout for pipe gamma enable.
17763 crtc_state->uapi.color_mgmt_changed = true;
17766 * FIXME hack to force full modeset when DSC is being
17769 * As long as we do not have full state readout and
17770 * config comparison of crtc_state->dsc, we have no way
17771 * to ensure reliable fastset. Remove once we have
17774 if (crtc_state->dsc.compression_enable) {
17775 ret = drm_atomic_add_affected_connectors(state,
17779 crtc_state->uapi.mode_changed = true;
17780 drm_dbg_kms(dev, "Force full modeset for DSC\n");
17785 ret = drm_atomic_commit(state);
17788 if (ret == -EDEADLK) {
17789 drm_atomic_state_clear(state);
17790 drm_modeset_backoff(&ctx);
17794 drm_atomic_state_put(state);
17796 drm_modeset_drop_locks(&ctx);
17797 drm_modeset_acquire_fini(&ctx);
17802 static void intel_mode_config_init(struct drm_i915_private *i915)
17804 struct drm_mode_config *mode_config = &i915->drm.mode_config;
17806 drm_mode_config_init(&i915->drm);
17807 INIT_LIST_HEAD(&i915->global_obj_list);
17809 mode_config->min_width = 0;
17810 mode_config->min_height = 0;
17812 mode_config->preferred_depth = 24;
17813 mode_config->prefer_shadow = 1;
17815 mode_config->allow_fb_modifiers = true;
17817 mode_config->funcs = &intel_mode_funcs;
17820 * Maximum framebuffer dimensions, chosen to match
17821 * the maximum render engine surface size on gen4+.
17823 if (INTEL_GEN(i915) >= 7) {
17824 mode_config->max_width = 16384;
17825 mode_config->max_height = 16384;
17826 } else if (INTEL_GEN(i915) >= 4) {
17827 mode_config->max_width = 8192;
17828 mode_config->max_height = 8192;
17829 } else if (IS_GEN(i915, 3)) {
17830 mode_config->max_width = 4096;
17831 mode_config->max_height = 4096;
17833 mode_config->max_width = 2048;
17834 mode_config->max_height = 2048;
17837 if (IS_I845G(i915) || IS_I865G(i915)) {
17838 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512;
17839 mode_config->cursor_height = 1023;
17840 } else if (IS_I830(i915) || IS_I85X(i915) ||
17841 IS_I915G(i915) || IS_I915GM(i915)) {
17842 mode_config->cursor_width = 64;
17843 mode_config->cursor_height = 64;
17845 mode_config->cursor_width = 256;
17846 mode_config->cursor_height = 256;
17850 static void intel_mode_config_cleanup(struct drm_i915_private *i915)
17852 intel_atomic_global_obj_cleanup(i915);
17853 drm_mode_config_cleanup(&i915->drm);
17856 static void plane_config_fini(struct intel_initial_plane_config *plane_config)
17858 if (plane_config->fb) {
17859 struct drm_framebuffer *fb = &plane_config->fb->base;
17861 /* We may only have the stub and not a full framebuffer */
17862 if (drm_framebuffer_read_refcount(fb))
17863 drm_framebuffer_put(fb);
17868 if (plane_config->vma)
17869 i915_vma_put(plane_config->vma);
17872 /* part #1: call before irq install */
17873 int intel_modeset_init_noirq(struct drm_i915_private *i915)
17877 if (i915_inject_probe_failure(i915))
17880 if (HAS_DISPLAY(i915)) {
17881 ret = drm_vblank_init(&i915->drm,
17882 INTEL_NUM_PIPES(i915));
17887 intel_bios_init(i915);
17889 ret = intel_vga_register(i915);
17893 /* FIXME: completely on the wrong abstraction layer */
17894 intel_power_domains_init_hw(i915, false);
17896 intel_csr_ucode_init(i915);
17898 i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
17899 i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
17900 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
17902 intel_mode_config_init(i915);
17904 ret = intel_cdclk_init(i915);
17906 goto cleanup_vga_client_pw_domain_csr;
17908 ret = intel_dbuf_init(i915);
17910 goto cleanup_vga_client_pw_domain_csr;
17912 ret = intel_bw_init(i915);
17914 goto cleanup_vga_client_pw_domain_csr;
17916 init_llist_head(&i915->atomic_helper.free_list);
17917 INIT_WORK(&i915->atomic_helper.free_work,
17918 intel_atomic_helper_free_state_worker);
17920 intel_init_quirks(i915);
17922 intel_fbc_init(i915);
17926 cleanup_vga_client_pw_domain_csr:
17927 intel_csr_ucode_fini(i915);
17928 intel_power_domains_driver_remove(i915);
17929 intel_vga_unregister(i915);
17931 intel_bios_driver_remove(i915);
17936 /* part #2: call after irq install, but before gem init */
17937 int intel_modeset_init_nogem(struct drm_i915_private *i915)
17939 struct drm_device *dev = &i915->drm;
17941 struct intel_crtc *crtc;
17944 intel_init_pm(i915);
17946 intel_panel_sanitize_ssc(i915);
17948 intel_gmbus_setup(i915);
17950 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n",
17951 INTEL_NUM_PIPES(i915),
17952 INTEL_NUM_PIPES(i915) > 1 ? "s" : "");
17954 if (HAS_DISPLAY(i915)) {
17955 for_each_pipe(i915, pipe) {
17956 ret = intel_crtc_init(i915, pipe);
17958 intel_mode_config_cleanup(i915);
17964 intel_plane_possible_crtcs_init(i915);
17965 intel_shared_dpll_init(dev);
17966 intel_update_fdi_pll_freq(i915);
17968 intel_update_czclk(i915);
17969 intel_modeset_init_hw(i915);
17971 intel_hdcp_component_init(i915);
17973 if (i915->max_cdclk_freq == 0)
17974 intel_update_max_cdclk(i915);
17977 * If the platform has HTI, we need to find out whether it has reserved
17978 * any display resources before we create our display outputs.
17980 if (INTEL_INFO(i915)->display.has_hti)
17981 i915->hti_state = intel_de_read(i915, HDPORT_STATE);
17983 /* Just disable it once at startup */
17984 intel_vga_disable(i915);
17985 intel_setup_outputs(i915);
17987 drm_modeset_lock_all(dev);
17988 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
17989 drm_modeset_unlock_all(dev);
17991 for_each_intel_crtc(dev, crtc) {
17992 struct intel_initial_plane_config plane_config = {};
17998 * Note that reserving the BIOS fb up front prevents us
17999 * from stuffing other stolen allocations like the ring
18000 * on top. This prevents some ugliness at boot time, and
18001 * can even allow for smooth boot transitions if the BIOS
18002 * fb is large enough for the active pipe configuration.
18004 i915->display.get_initial_plane_config(crtc, &plane_config);
18007 * If the fb is shared between multiple heads, we'll
18008 * just get the first one.
18010 intel_find_initial_plane_obj(crtc, &plane_config);
18012 plane_config_fini(&plane_config);
18016 * Make sure hardware watermarks really match the state we read out.
18017 * Note that we need to do this after reconstructing the BIOS fb's
18018 * since the watermark calculation done here will use pstate->fb.
18020 if (!HAS_GMCH(i915))
18021 sanitize_watermarks(i915);
18024 * Force all active planes to recompute their states. So that on
18025 * mode_setcrtc after probe, all the intel_plane_state variables
18026 * are already calculated and there is no assert_plane warnings
18029 ret = intel_initial_commit(dev);
18031 drm_dbg_kms(&i915->drm, "Initial commit in probe failed.\n");
18036 /* part #3: call after gem init */
18037 int intel_modeset_init(struct drm_i915_private *i915)
18041 intel_overlay_setup(i915);
18043 if (!HAS_DISPLAY(i915))
18046 ret = intel_fbdev_init(&i915->drm);
18050 /* Only enable hotplug handling once the fbdev is fully set up. */
18051 intel_hpd_init(i915);
18053 intel_init_ipc(i915);
18055 intel_psr_set_force_mode_changed(i915->psr.dp);
18060 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
18062 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18063 /* 640x480@60Hz, ~25175 kHz */
18064 struct dpll clock = {
18074 drm_WARN_ON(&dev_priv->drm,
18075 i9xx_calc_dpll_params(48000, &clock) != 25154);
18077 drm_dbg_kms(&dev_priv->drm,
18078 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
18079 pipe_name(pipe), clock.vco, clock.dot);
18081 fp = i9xx_dpll_compute_fp(&clock);
18082 dpll = DPLL_DVO_2X_MODE |
18083 DPLL_VGA_MODE_DIS |
18084 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
18085 PLL_P2_DIVIDE_BY_4 |
18086 PLL_REF_INPUT_DREFCLK |
18089 intel_de_write(dev_priv, FP0(pipe), fp);
18090 intel_de_write(dev_priv, FP1(pipe), fp);
18092 intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
18093 intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
18094 intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
18095 intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
18096 intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
18097 intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
18098 intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
18101 * Apparently we need to have VGA mode enabled prior to changing
18102 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
18103 * dividers, even though the register value does change.
18105 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
18106 intel_de_write(dev_priv, DPLL(pipe), dpll);
18108 /* Wait for the clocks to stabilize. */
18109 intel_de_posting_read(dev_priv, DPLL(pipe));
18112 /* The pixel multiplier can only be updated once the
18113 * DPLL is enabled and the clocks are stable.
18115 * So write it again.
18117 intel_de_write(dev_priv, DPLL(pipe), dpll);
18119 /* We do this three times for luck */
18120 for (i = 0; i < 3 ; i++) {
18121 intel_de_write(dev_priv, DPLL(pipe), dpll);
18122 intel_de_posting_read(dev_priv, DPLL(pipe));
18123 udelay(150); /* wait for warmup */
18126 intel_de_write(dev_priv, PIPECONF(pipe),
18127 PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
18128 intel_de_posting_read(dev_priv, PIPECONF(pipe));
18130 intel_wait_for_pipe_scanline_moving(crtc);
18133 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
18135 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18137 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",
18140 drm_WARN_ON(&dev_priv->drm,
18141 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) &
18142 DISPLAY_PLANE_ENABLE);
18143 drm_WARN_ON(&dev_priv->drm,
18144 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) &
18145 DISPLAY_PLANE_ENABLE);
18146 drm_WARN_ON(&dev_priv->drm,
18147 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) &
18148 DISPLAY_PLANE_ENABLE);
18149 drm_WARN_ON(&dev_priv->drm,
18150 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE);
18151 drm_WARN_ON(&dev_priv->drm,
18152 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE);
18154 intel_de_write(dev_priv, PIPECONF(pipe), 0);
18155 intel_de_posting_read(dev_priv, PIPECONF(pipe));
18157 intel_wait_for_pipe_scanline_stopped(crtc);
18159 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
18160 intel_de_posting_read(dev_priv, DPLL(pipe));
18164 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
18166 struct intel_crtc *crtc;
18168 if (INTEL_GEN(dev_priv) >= 4)
18171 for_each_intel_crtc(&dev_priv->drm, crtc) {
18172 struct intel_plane *plane =
18173 to_intel_plane(crtc->base.primary);
18174 struct intel_crtc *plane_crtc;
18177 if (!plane->get_hw_state(plane, &pipe))
18180 if (pipe == crtc->pipe)
18183 drm_dbg_kms(&dev_priv->drm,
18184 "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
18185 plane->base.base.id, plane->base.name);
18187 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18188 intel_plane_disable_noatomic(plane_crtc, plane);
18192 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
18194 struct drm_device *dev = crtc->base.dev;
18195 struct intel_encoder *encoder;
18197 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
18203 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
18205 struct drm_device *dev = encoder->base.dev;
18206 struct intel_connector *connector;
18208 for_each_connector_on_encoder(dev, &encoder->base, connector)
18214 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
18215 enum pipe pch_transcoder)
18217 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
18218 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
18221 static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc_state)
18223 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
18224 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
18225 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
18227 if (INTEL_GEN(dev_priv) >= 9 ||
18228 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
18229 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
18232 if (transcoder_is_dsi(cpu_transcoder))
18235 val = intel_de_read(dev_priv, reg);
18236 val &= ~HSW_FRAME_START_DELAY_MASK;
18237 val |= HSW_FRAME_START_DELAY(0);
18238 intel_de_write(dev_priv, reg, val);
18240 i915_reg_t reg = PIPECONF(cpu_transcoder);
18243 val = intel_de_read(dev_priv, reg);
18244 val &= ~PIPECONF_FRAME_START_DELAY_MASK;
18245 val |= PIPECONF_FRAME_START_DELAY(0);
18246 intel_de_write(dev_priv, reg, val);
18249 if (!crtc_state->has_pch_encoder)
18252 if (HAS_PCH_IBX(dev_priv)) {
18253 i915_reg_t reg = PCH_TRANSCONF(crtc->pipe);
18256 val = intel_de_read(dev_priv, reg);
18257 val &= ~TRANS_FRAME_START_DELAY_MASK;
18258 val |= TRANS_FRAME_START_DELAY(0);
18259 intel_de_write(dev_priv, reg, val);
18261 enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc);
18262 i915_reg_t reg = TRANS_CHICKEN2(pch_transcoder);
18265 val = intel_de_read(dev_priv, reg);
18266 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
18267 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
18268 intel_de_write(dev_priv, reg, val);
18272 static void intel_sanitize_crtc(struct intel_crtc *crtc,
18273 struct drm_modeset_acquire_ctx *ctx)
18275 struct drm_device *dev = crtc->base.dev;
18276 struct drm_i915_private *dev_priv = to_i915(dev);
18277 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
18279 if (crtc_state->hw.active) {
18280 struct intel_plane *plane;
18282 /* Clear any frame start delays used for debugging left by the BIOS */
18283 intel_sanitize_frame_start_delay(crtc_state);
18285 /* Disable everything but the primary plane */
18286 for_each_intel_plane_on_crtc(dev, crtc, plane) {
18287 const struct intel_plane_state *plane_state =
18288 to_intel_plane_state(plane->base.state);
18290 if (plane_state->uapi.visible &&
18291 plane->base.type != DRM_PLANE_TYPE_PRIMARY)
18292 intel_plane_disable_noatomic(crtc, plane);
18296 * Disable any background color set by the BIOS, but enable the
18297 * gamma and CSC to match how we program our planes.
18299 if (INTEL_GEN(dev_priv) >= 9)
18300 intel_de_write(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe),
18301 SKL_BOTTOM_COLOR_GAMMA_ENABLE | SKL_BOTTOM_COLOR_CSC_ENABLE);
18304 /* Adjust the state of the output pipe according to whether we
18305 * have active connectors/encoders. */
18306 if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc))
18307 intel_crtc_disable_noatomic(crtc, ctx);
18309 if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
18311 * We start out with underrun reporting disabled to avoid races.
18312 * For correct bookkeeping mark this on active crtcs.
18314 * Also on gmch platforms we dont have any hardware bits to
18315 * disable the underrun reporting. Which means we need to start
18316 * out with underrun reporting disabled also on inactive pipes,
18317 * since otherwise we'll complain about the garbage we read when
18318 * e.g. coming up after runtime pm.
18320 * No protection against concurrent access is required - at
18321 * worst a fifo underrun happens which also sets this to false.
18323 crtc->cpu_fifo_underrun_disabled = true;
18325 * We track the PCH trancoder underrun reporting state
18326 * within the crtc. With crtc for pipe A housing the underrun
18327 * reporting state for PCH transcoder A, crtc for pipe B housing
18328 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
18329 * and marking underrun reporting as disabled for the non-existing
18330 * PCH transcoders B and C would prevent enabling the south
18331 * error interrupt (see cpt_can_enable_serr_int()).
18333 if (has_pch_trancoder(dev_priv, crtc->pipe))
18334 crtc->pch_fifo_underrun_disabled = true;
18338 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
18340 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
18343 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
18344 * the hardware when a high res displays plugged in. DPLL P
18345 * divider is zero, and the pipe timings are bonkers. We'll
18346 * try to disable everything in that case.
18348 * FIXME would be nice to be able to sanitize this state
18349 * without several WARNs, but for now let's take the easy
18352 return IS_GEN(dev_priv, 6) &&
18353 crtc_state->hw.active &&
18354 crtc_state->shared_dpll &&
18355 crtc_state->port_clock == 0;
18358 static void intel_sanitize_encoder(struct intel_encoder *encoder)
18360 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
18361 struct intel_connector *connector;
18362 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18363 struct intel_crtc_state *crtc_state = crtc ?
18364 to_intel_crtc_state(crtc->base.state) : NULL;
18366 /* We need to check both for a crtc link (meaning that the
18367 * encoder is active and trying to read from a pipe) and the
18368 * pipe itself being active. */
18369 bool has_active_crtc = crtc_state &&
18370 crtc_state->hw.active;
18372 if (crtc_state && has_bogus_dpll_config(crtc_state)) {
18373 drm_dbg_kms(&dev_priv->drm,
18374 "BIOS has misprogrammed the hardware. Disabling pipe %c\n",
18375 pipe_name(crtc->pipe));
18376 has_active_crtc = false;
18379 connector = intel_encoder_find_connector(encoder);
18380 if (connector && !has_active_crtc) {
18381 drm_dbg_kms(&dev_priv->drm,
18382 "[ENCODER:%d:%s] has active connectors but no active pipe!\n",
18383 encoder->base.base.id,
18384 encoder->base.name);
18386 /* Connector is active, but has no active pipe. This is
18387 * fallout from our resume register restoring. Disable
18388 * the encoder manually again. */
18390 struct drm_encoder *best_encoder;
18392 drm_dbg_kms(&dev_priv->drm,
18393 "[ENCODER:%d:%s] manually disabled\n",
18394 encoder->base.base.id,
18395 encoder->base.name);
18397 /* avoid oopsing in case the hooks consult best_encoder */
18398 best_encoder = connector->base.state->best_encoder;
18399 connector->base.state->best_encoder = &encoder->base;
18401 /* FIXME NULL atomic state passed! */
18402 if (encoder->disable)
18403 encoder->disable(NULL, encoder, crtc_state,
18404 connector->base.state);
18405 if (encoder->post_disable)
18406 encoder->post_disable(NULL, encoder, crtc_state,
18407 connector->base.state);
18409 connector->base.state->best_encoder = best_encoder;
18411 encoder->base.crtc = NULL;
18413 /* Inconsistent output/port/pipe state happens presumably due to
18414 * a bug in one of the get_hw_state functions. Or someplace else
18415 * in our code, like the register restore mess on resume. Clamp
18416 * things to off as a safer default. */
18418 connector->base.dpms = DRM_MODE_DPMS_OFF;
18419 connector->base.encoder = NULL;
18422 /* notify opregion of the sanitized encoder state */
18423 intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
18425 if (INTEL_GEN(dev_priv) >= 11)
18426 icl_sanitize_encoder_pll_mapping(encoder);
18429 /* FIXME read out full plane state for all planes */
18430 static void readout_plane_state(struct drm_i915_private *dev_priv)
18432 struct intel_plane *plane;
18433 struct intel_crtc *crtc;
18435 for_each_intel_plane(&dev_priv->drm, plane) {
18436 struct intel_plane_state *plane_state =
18437 to_intel_plane_state(plane->base.state);
18438 struct intel_crtc_state *crtc_state;
18439 enum pipe pipe = PIPE_A;
18442 visible = plane->get_hw_state(plane, &pipe);
18444 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18445 crtc_state = to_intel_crtc_state(crtc->base.state);
18447 intel_set_plane_visible(crtc_state, plane_state, visible);
18449 drm_dbg_kms(&dev_priv->drm,
18450 "[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
18451 plane->base.base.id, plane->base.name,
18452 enableddisabled(visible), pipe_name(pipe));
18455 for_each_intel_crtc(&dev_priv->drm, crtc) {
18456 struct intel_crtc_state *crtc_state =
18457 to_intel_crtc_state(crtc->base.state);
18459 fixup_active_planes(crtc_state);
18463 static void intel_modeset_readout_hw_state(struct drm_device *dev)
18465 struct drm_i915_private *dev_priv = to_i915(dev);
18466 struct intel_cdclk_state *cdclk_state =
18467 to_intel_cdclk_state(dev_priv->cdclk.obj.state);
18468 struct intel_dbuf_state *dbuf_state =
18469 to_intel_dbuf_state(dev_priv->dbuf.obj.state);
18471 struct intel_crtc *crtc;
18472 struct intel_encoder *encoder;
18473 struct intel_connector *connector;
18474 struct drm_connector_list_iter conn_iter;
18475 u8 active_pipes = 0;
18477 for_each_intel_crtc(dev, crtc) {
18478 struct intel_crtc_state *crtc_state =
18479 to_intel_crtc_state(crtc->base.state);
18481 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
18482 intel_crtc_free_hw_state(crtc_state);
18483 intel_crtc_state_reset(crtc_state, crtc);
18485 crtc_state->hw.active = crtc_state->hw.enable =
18486 dev_priv->display.get_pipe_config(crtc, crtc_state);
18488 crtc->base.enabled = crtc_state->hw.enable;
18489 crtc->active = crtc_state->hw.active;
18491 if (crtc_state->hw.active)
18492 active_pipes |= BIT(crtc->pipe);
18494 drm_dbg_kms(&dev_priv->drm,
18495 "[CRTC:%d:%s] hw state readout: %s\n",
18496 crtc->base.base.id, crtc->base.name,
18497 enableddisabled(crtc_state->hw.active));
18500 dev_priv->active_pipes = cdclk_state->active_pipes =
18501 dbuf_state->active_pipes = active_pipes;
18503 readout_plane_state(dev_priv);
18505 intel_dpll_readout_hw_state(dev_priv);
18507 for_each_intel_encoder(dev, encoder) {
18510 if (encoder->get_hw_state(encoder, &pipe)) {
18511 struct intel_crtc_state *crtc_state;
18513 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18514 crtc_state = to_intel_crtc_state(crtc->base.state);
18516 encoder->base.crtc = &crtc->base;
18517 encoder->get_config(encoder, crtc_state);
18519 encoder->base.crtc = NULL;
18522 drm_dbg_kms(&dev_priv->drm,
18523 "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
18524 encoder->base.base.id, encoder->base.name,
18525 enableddisabled(encoder->base.crtc),
18529 drm_connector_list_iter_begin(dev, &conn_iter);
18530 for_each_intel_connector_iter(connector, &conn_iter) {
18531 if (connector->get_hw_state(connector)) {
18532 struct intel_crtc_state *crtc_state;
18533 struct intel_crtc *crtc;
18535 connector->base.dpms = DRM_MODE_DPMS_ON;
18537 encoder = intel_attached_encoder(connector);
18538 connector->base.encoder = &encoder->base;
18540 crtc = to_intel_crtc(encoder->base.crtc);
18541 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
18543 if (crtc_state && crtc_state->hw.active) {
18545 * This has to be done during hardware readout
18546 * because anything calling .crtc_disable may
18547 * rely on the connector_mask being accurate.
18549 crtc_state->uapi.connector_mask |=
18550 drm_connector_mask(&connector->base);
18551 crtc_state->uapi.encoder_mask |=
18552 drm_encoder_mask(&encoder->base);
18555 connector->base.dpms = DRM_MODE_DPMS_OFF;
18556 connector->base.encoder = NULL;
18558 drm_dbg_kms(&dev_priv->drm,
18559 "[CONNECTOR:%d:%s] hw state readout: %s\n",
18560 connector->base.base.id, connector->base.name,
18561 enableddisabled(connector->base.encoder));
18563 drm_connector_list_iter_end(&conn_iter);
18565 for_each_intel_crtc(dev, crtc) {
18566 struct intel_bw_state *bw_state =
18567 to_intel_bw_state(dev_priv->bw_obj.state);
18568 struct intel_crtc_state *crtc_state =
18569 to_intel_crtc_state(crtc->base.state);
18570 struct intel_plane *plane;
18573 if (crtc_state->hw.active) {
18574 struct drm_display_mode *mode = &crtc_state->hw.mode;
18576 intel_mode_from_pipe_config(&crtc_state->hw.adjusted_mode,
18579 *mode = crtc_state->hw.adjusted_mode;
18580 mode->hdisplay = crtc_state->pipe_src_w;
18581 mode->vdisplay = crtc_state->pipe_src_h;
18584 * The initial mode needs to be set in order to keep
18585 * the atomic core happy. It wants a valid mode if the
18586 * crtc's enabled, so we do the above call.
18588 * But we don't set all the derived state fully, hence
18589 * set a flag to indicate that a full recalculation is
18590 * needed on the next commit.
18592 crtc_state->inherited = true;
18594 intel_crtc_compute_pixel_rate(crtc_state);
18596 intel_crtc_update_active_timings(crtc_state);
18598 intel_crtc_copy_hw_to_uapi_state(crtc_state);
18601 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
18602 const struct intel_plane_state *plane_state =
18603 to_intel_plane_state(plane->base.state);
18606 * FIXME don't have the fb yet, so can't
18607 * use intel_plane_data_rate() :(
18609 if (plane_state->uapi.visible)
18610 crtc_state->data_rate[plane->id] =
18611 4 * crtc_state->pixel_rate;
18613 * FIXME don't have the fb yet, so can't
18614 * use plane->min_cdclk() :(
18616 if (plane_state->uapi.visible && plane->min_cdclk) {
18617 if (crtc_state->double_wide ||
18618 INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
18619 crtc_state->min_cdclk[plane->id] =
18620 DIV_ROUND_UP(crtc_state->pixel_rate, 2);
18622 crtc_state->min_cdclk[plane->id] =
18623 crtc_state->pixel_rate;
18625 drm_dbg_kms(&dev_priv->drm,
18626 "[PLANE:%d:%s] min_cdclk %d kHz\n",
18627 plane->base.base.id, plane->base.name,
18628 crtc_state->min_cdclk[plane->id]);
18631 if (crtc_state->hw.active) {
18632 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
18633 if (drm_WARN_ON(dev, min_cdclk < 0))
18637 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
18638 cdclk_state->min_voltage_level[crtc->pipe] =
18639 crtc_state->min_voltage_level;
18641 intel_bw_crtc_update(bw_state, crtc_state);
18643 intel_pipe_config_sanity_check(dev_priv, crtc_state);
18648 get_encoder_power_domains(struct drm_i915_private *dev_priv)
18650 struct intel_encoder *encoder;
18652 for_each_intel_encoder(&dev_priv->drm, encoder) {
18653 struct intel_crtc_state *crtc_state;
18655 if (!encoder->get_power_domains)
18659 * MST-primary and inactive encoders don't have a crtc state
18660 * and neither of these require any power domain references.
18662 if (!encoder->base.crtc)
18665 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
18666 encoder->get_power_domains(encoder, crtc_state);
18670 static void intel_early_display_was(struct drm_i915_private *dev_priv)
18673 * Display WA #1185 WaDisableDARBFClkGating:cnl,glk,icl,ehl,tgl
18674 * Also known as Wa_14010480278.
18676 if (IS_GEN_RANGE(dev_priv, 10, 12) || IS_GEMINILAKE(dev_priv))
18677 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0,
18678 intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS);
18680 if (IS_HASWELL(dev_priv)) {
18682 * WaRsPkgCStateDisplayPMReq:hsw
18683 * System hang if this isn't done before disabling all planes!
18685 intel_de_write(dev_priv, CHICKEN_PAR1_1,
18686 intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
18690 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
18691 enum port port, i915_reg_t hdmi_reg)
18693 u32 val = intel_de_read(dev_priv, hdmi_reg);
18695 if (val & SDVO_ENABLE ||
18696 (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
18699 drm_dbg_kms(&dev_priv->drm,
18700 "Sanitizing transcoder select for HDMI %c\n",
18703 val &= ~SDVO_PIPE_SEL_MASK;
18704 val |= SDVO_PIPE_SEL(PIPE_A);
18706 intel_de_write(dev_priv, hdmi_reg, val);
18709 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
18710 enum port port, i915_reg_t dp_reg)
18712 u32 val = intel_de_read(dev_priv, dp_reg);
18714 if (val & DP_PORT_EN ||
18715 (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
18718 drm_dbg_kms(&dev_priv->drm,
18719 "Sanitizing transcoder select for DP %c\n",
18722 val &= ~DP_PIPE_SEL_MASK;
18723 val |= DP_PIPE_SEL(PIPE_A);
18725 intel_de_write(dev_priv, dp_reg, val);
18728 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
18731 * The BIOS may select transcoder B on some of the PCH
18732 * ports even it doesn't enable the port. This would trip
18733 * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
18734 * Sanitize the transcoder select bits to prevent that. We
18735 * assume that the BIOS never actually enabled the port,
18736 * because if it did we'd actually have to toggle the port
18737 * on and back off to make the transcoder A select stick
18738 * (see. intel_dp_link_down(), intel_disable_hdmi(),
18739 * intel_disable_sdvo()).
18741 ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
18742 ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
18743 ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
18745 /* PCH SDVOB multiplex with HDMIB */
18746 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
18747 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
18748 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
18751 /* Scan out the current hw modeset state,
18752 * and sanitizes it to the current state
18755 intel_modeset_setup_hw_state(struct drm_device *dev,
18756 struct drm_modeset_acquire_ctx *ctx)
18758 struct drm_i915_private *dev_priv = to_i915(dev);
18759 struct intel_encoder *encoder;
18760 struct intel_crtc *crtc;
18761 intel_wakeref_t wakeref;
18763 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
18765 intel_early_display_was(dev_priv);
18766 intel_modeset_readout_hw_state(dev);
18768 /* HW state is read out, now we need to sanitize this mess. */
18770 /* Sanitize the TypeC port mode upfront, encoders depend on this */
18771 for_each_intel_encoder(dev, encoder) {
18772 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
18774 /* We need to sanitize only the MST primary port. */
18775 if (encoder->type != INTEL_OUTPUT_DP_MST &&
18776 intel_phy_is_tc(dev_priv, phy))
18777 intel_tc_port_sanitize(enc_to_dig_port(encoder));
18780 get_encoder_power_domains(dev_priv);
18782 if (HAS_PCH_IBX(dev_priv))
18783 ibx_sanitize_pch_ports(dev_priv);
18786 * intel_sanitize_plane_mapping() may need to do vblank
18787 * waits, so we need vblank interrupts restored beforehand.
18789 for_each_intel_crtc(&dev_priv->drm, crtc) {
18790 struct intel_crtc_state *crtc_state =
18791 to_intel_crtc_state(crtc->base.state);
18793 drm_crtc_vblank_reset(&crtc->base);
18795 if (crtc_state->hw.active)
18796 intel_crtc_vblank_on(crtc_state);
18799 intel_sanitize_plane_mapping(dev_priv);
18801 for_each_intel_encoder(dev, encoder)
18802 intel_sanitize_encoder(encoder);
18804 for_each_intel_crtc(&dev_priv->drm, crtc) {
18805 struct intel_crtc_state *crtc_state =
18806 to_intel_crtc_state(crtc->base.state);
18808 intel_sanitize_crtc(crtc, ctx);
18809 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
18812 intel_modeset_update_connector_atomic_state(dev);
18814 intel_dpll_sanitize_state(dev_priv);
18816 if (IS_G4X(dev_priv)) {
18817 g4x_wm_get_hw_state(dev_priv);
18818 g4x_wm_sanitize(dev_priv);
18819 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
18820 vlv_wm_get_hw_state(dev_priv);
18821 vlv_wm_sanitize(dev_priv);
18822 } else if (INTEL_GEN(dev_priv) >= 9) {
18823 skl_wm_get_hw_state(dev_priv);
18824 } else if (HAS_PCH_SPLIT(dev_priv)) {
18825 ilk_wm_get_hw_state(dev_priv);
18828 for_each_intel_crtc(dev, crtc) {
18829 struct intel_crtc_state *crtc_state =
18830 to_intel_crtc_state(crtc->base.state);
18833 put_domains = modeset_get_crtc_power_domains(crtc_state);
18834 if (drm_WARN_ON(dev, put_domains))
18835 modeset_put_power_domains(dev_priv, put_domains);
18838 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
18841 void intel_display_resume(struct drm_device *dev)
18843 struct drm_i915_private *dev_priv = to_i915(dev);
18844 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
18845 struct drm_modeset_acquire_ctx ctx;
18848 dev_priv->modeset_restore_state = NULL;
18850 state->acquire_ctx = &ctx;
18852 drm_modeset_acquire_init(&ctx, 0);
18855 ret = drm_modeset_lock_all_ctx(dev, &ctx);
18856 if (ret != -EDEADLK)
18859 drm_modeset_backoff(&ctx);
18863 ret = __intel_display_resume(dev, state, &ctx);
18865 intel_enable_ipc(dev_priv);
18866 drm_modeset_drop_locks(&ctx);
18867 drm_modeset_acquire_fini(&ctx);
18870 drm_err(&dev_priv->drm,
18871 "Restoring old state failed with %i\n", ret);
18873 drm_atomic_state_put(state);
18876 static void intel_hpd_poll_fini(struct drm_i915_private *i915)
18878 struct intel_connector *connector;
18879 struct drm_connector_list_iter conn_iter;
18881 /* Kill all the work that may have been queued by hpd. */
18882 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
18883 for_each_intel_connector_iter(connector, &conn_iter) {
18884 if (connector->modeset_retry_work.func)
18885 cancel_work_sync(&connector->modeset_retry_work);
18886 if (connector->hdcp.shim) {
18887 cancel_delayed_work_sync(&connector->hdcp.check_work);
18888 cancel_work_sync(&connector->hdcp.prop_work);
18891 drm_connector_list_iter_end(&conn_iter);
18894 /* part #1: call before irq uninstall */
18895 void intel_modeset_driver_remove(struct drm_i915_private *i915)
18897 flush_workqueue(i915->flip_wq);
18898 flush_workqueue(i915->modeset_wq);
18900 flush_work(&i915->atomic_helper.free_work);
18901 drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list));
18904 /* part #2: call after irq uninstall */
18905 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915)
18908 * Due to the hpd irq storm handling the hotplug work can re-arm the
18909 * poll handlers. Hence disable polling after hpd handling is shut down.
18911 intel_hpd_poll_fini(i915);
18914 * MST topology needs to be suspended so we don't have any calls to
18915 * fbdev after it's finalized. MST will be destroyed later as part of
18916 * drm_mode_config_cleanup()
18918 intel_dp_mst_suspend(i915);
18920 /* poll work can call into fbdev, hence clean that up afterwards */
18921 intel_fbdev_fini(i915);
18923 intel_unregister_dsm_handler();
18925 intel_fbc_global_disable(i915);
18927 /* flush any delayed tasks or pending work */
18928 flush_scheduled_work();
18930 intel_hdcp_component_fini(i915);
18932 intel_mode_config_cleanup(i915);
18934 intel_overlay_cleanup(i915);
18936 intel_gmbus_teardown(i915);
18938 destroy_workqueue(i915->flip_wq);
18939 destroy_workqueue(i915->modeset_wq);
18941 intel_fbc_cleanup_cfb(i915);
18944 /* part #3: call after gem init */
18945 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915)
18947 intel_csr_ucode_fini(i915);
18949 intel_power_domains_driver_remove(i915);
18951 intel_vga_unregister(i915);
18953 intel_bios_driver_remove(i915);
18956 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
18958 struct intel_display_error_state {
18960 u32 power_well_driver;
18962 struct intel_cursor_error_state {
18967 } cursor[I915_MAX_PIPES];
18969 struct intel_pipe_error_state {
18970 bool power_domain_on;
18973 } pipe[I915_MAX_PIPES];
18975 struct intel_plane_error_state {
18983 } plane[I915_MAX_PIPES];
18985 struct intel_transcoder_error_state {
18987 bool power_domain_on;
18988 enum transcoder cpu_transcoder;
19001 struct intel_display_error_state *
19002 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
19004 struct intel_display_error_state *error;
19005 int transcoders[] = {
19014 BUILD_BUG_ON(ARRAY_SIZE(transcoders) != ARRAY_SIZE(error->transcoder));
19016 if (!HAS_DISPLAY(dev_priv))
19019 error = kzalloc(sizeof(*error), GFP_ATOMIC);
19023 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
19024 error->power_well_driver = intel_de_read(dev_priv,
19025 HSW_PWR_WELL_CTL2);
19027 for_each_pipe(dev_priv, i) {
19028 error->pipe[i].power_domain_on =
19029 __intel_display_power_is_enabled(dev_priv,
19030 POWER_DOMAIN_PIPE(i));
19031 if (!error->pipe[i].power_domain_on)
19034 error->cursor[i].control = intel_de_read(dev_priv, CURCNTR(i));
19035 error->cursor[i].position = intel_de_read(dev_priv, CURPOS(i));
19036 error->cursor[i].base = intel_de_read(dev_priv, CURBASE(i));
19038 error->plane[i].control = intel_de_read(dev_priv, DSPCNTR(i));
19039 error->plane[i].stride = intel_de_read(dev_priv, DSPSTRIDE(i));
19040 if (INTEL_GEN(dev_priv) <= 3) {
19041 error->plane[i].size = intel_de_read(dev_priv,
19043 error->plane[i].pos = intel_de_read(dev_priv,
19046 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
19047 error->plane[i].addr = intel_de_read(dev_priv,
19049 if (INTEL_GEN(dev_priv) >= 4) {
19050 error->plane[i].surface = intel_de_read(dev_priv,
19052 error->plane[i].tile_offset = intel_de_read(dev_priv,
19056 error->pipe[i].source = intel_de_read(dev_priv, PIPESRC(i));
19058 if (HAS_GMCH(dev_priv))
19059 error->pipe[i].stat = intel_de_read(dev_priv,
19063 for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
19064 enum transcoder cpu_transcoder = transcoders[i];
19066 if (!HAS_TRANSCODER(dev_priv, cpu_transcoder))
19069 error->transcoder[i].available = true;
19070 error->transcoder[i].power_domain_on =
19071 __intel_display_power_is_enabled(dev_priv,
19072 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
19073 if (!error->transcoder[i].power_domain_on)
19076 error->transcoder[i].cpu_transcoder = cpu_transcoder;
19078 error->transcoder[i].conf = intel_de_read(dev_priv,
19079 PIPECONF(cpu_transcoder));
19080 error->transcoder[i].htotal = intel_de_read(dev_priv,
19081 HTOTAL(cpu_transcoder));
19082 error->transcoder[i].hblank = intel_de_read(dev_priv,
19083 HBLANK(cpu_transcoder));
19084 error->transcoder[i].hsync = intel_de_read(dev_priv,
19085 HSYNC(cpu_transcoder));
19086 error->transcoder[i].vtotal = intel_de_read(dev_priv,
19087 VTOTAL(cpu_transcoder));
19088 error->transcoder[i].vblank = intel_de_read(dev_priv,
19089 VBLANK(cpu_transcoder));
19090 error->transcoder[i].vsync = intel_de_read(dev_priv,
19091 VSYNC(cpu_transcoder));
19097 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
19100 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
19101 struct intel_display_error_state *error)
19103 struct drm_i915_private *dev_priv = m->i915;
19109 err_printf(m, "Num Pipes: %d\n", INTEL_NUM_PIPES(dev_priv));
19110 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
19111 err_printf(m, "PWR_WELL_CTL2: %08x\n",
19112 error->power_well_driver);
19113 for_each_pipe(dev_priv, i) {
19114 err_printf(m, "Pipe [%d]:\n", i);
19115 err_printf(m, " Power: %s\n",
19116 onoff(error->pipe[i].power_domain_on));
19117 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
19118 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
19120 err_printf(m, "Plane [%d]:\n", i);
19121 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
19122 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
19123 if (INTEL_GEN(dev_priv) <= 3) {
19124 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
19125 err_printf(m, " POS: %08x\n", error->plane[i].pos);
19127 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
19128 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
19129 if (INTEL_GEN(dev_priv) >= 4) {
19130 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
19131 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
19134 err_printf(m, "Cursor [%d]:\n", i);
19135 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
19136 err_printf(m, " POS: %08x\n", error->cursor[i].position);
19137 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
19140 for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
19141 if (!error->transcoder[i].available)
19144 err_printf(m, "CPU transcoder: %s\n",
19145 transcoder_name(error->transcoder[i].cpu_transcoder));
19146 err_printf(m, " Power: %s\n",
19147 onoff(error->transcoder[i].power_domain_on));
19148 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
19149 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
19150 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
19151 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
19152 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
19153 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
19154 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);