2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/i2c.h>
28 #include <linux/input.h>
29 #include <linux/intel-iommu.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/dma-resv.h>
33 #include <linux/slab.h>
35 #include <drm/drm_atomic.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_atomic_uapi.h>
38 #include <drm/drm_damage_helper.h>
39 #include <drm/drm_dp_helper.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_fourcc.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_probe_helper.h>
44 #include <drm/drm_rect.h>
46 #include "display/intel_crt.h"
47 #include "display/intel_ddi.h"
48 #include "display/intel_display_debugfs.h"
49 #include "display/intel_dp.h"
50 #include "display/intel_dp_mst.h"
51 #include "display/intel_dpll.h"
52 #include "display/intel_dpll_mgr.h"
53 #include "display/intel_dsi.h"
54 #include "display/intel_dvo.h"
55 #include "display/intel_gmbus.h"
56 #include "display/intel_hdmi.h"
57 #include "display/intel_lvds.h"
58 #include "display/intel_sdvo.h"
59 #include "display/intel_tv.h"
60 #include "display/intel_vdsc.h"
61 #include "display/intel_vrr.h"
63 #include "gem/i915_gem_object.h"
65 #include "gt/intel_rps.h"
68 #include "i915_trace.h"
69 #include "intel_acpi.h"
70 #include "intel_atomic.h"
71 #include "intel_atomic_plane.h"
73 #include "intel_cdclk.h"
74 #include "intel_color.h"
75 #include "intel_crtc.h"
76 #include "intel_csr.h"
77 #include "intel_display_types.h"
78 #include "intel_dp_link_training.h"
79 #include "intel_fbc.h"
80 #include "intel_fdi.h"
81 #include "intel_fbdev.h"
82 #include "intel_fifo_underrun.h"
83 #include "intel_frontbuffer.h"
84 #include "intel_hdcp.h"
85 #include "intel_hotplug.h"
86 #include "intel_overlay.h"
87 #include "intel_pipe_crc.h"
89 #include "intel_pps.h"
90 #include "intel_psr.h"
91 #include "intel_quirks.h"
92 #include "intel_sideband.h"
93 #include "intel_sprite.h"
95 #include "intel_vga.h"
96 #include "i9xx_plane.h"
98 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
99 struct intel_crtc_state *pipe_config);
100 static void ilk_pch_clock_get(struct intel_crtc *crtc,
101 struct intel_crtc_state *pipe_config);
103 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
104 struct drm_i915_gem_object *obj,
105 struct drm_mode_fb_cmd2 *mode_cmd);
106 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
107 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
108 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
109 const struct intel_link_m_n *m_n,
110 const struct intel_link_m_n *m2_n2);
111 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
112 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
113 static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state);
114 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
115 static void vlv_prepare_pll(struct intel_crtc *crtc,
116 const struct intel_crtc_state *pipe_config);
117 static void chv_prepare_pll(struct intel_crtc *crtc,
118 const struct intel_crtc_state *pipe_config);
119 static void skl_pfit_enable(const struct intel_crtc_state *crtc_state);
120 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
121 static void intel_modeset_setup_hw_state(struct drm_device *dev,
122 struct drm_modeset_acquire_ctx *ctx);
124 /* returns HPLL frequency in kHz */
125 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
127 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
129 /* Obtain SKU information */
130 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
131 CCK_FUSE_HPLL_FREQ_MASK;
133 return vco_freq[hpll_freq] * 1000;
136 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
137 const char *name, u32 reg, int ref_freq)
142 val = vlv_cck_read(dev_priv, reg);
143 divider = val & CCK_FREQUENCY_VALUES;
145 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
146 (divider << CCK_FREQUENCY_STATUS_SHIFT),
147 "%s change in progress\n", name);
149 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
152 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
153 const char *name, u32 reg)
157 vlv_cck_get(dev_priv);
159 if (dev_priv->hpll_freq == 0)
160 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
162 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
164 vlv_cck_put(dev_priv);
169 static void intel_update_czclk(struct drm_i915_private *dev_priv)
171 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
174 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
175 CCK_CZ_CLOCK_CONTROL);
177 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
178 dev_priv->czclk_freq);
181 /* WA Display #0827: Gen9:all */
183 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
186 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
187 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS);
189 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
190 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
193 /* Wa_2006604312:icl,ehl */
195 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
199 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
200 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
202 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
203 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
207 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
209 return crtc_state->master_transcoder != INVALID_TRANSCODER;
213 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
215 return crtc_state->sync_mode_slaves_mask != 0;
219 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
221 return is_trans_port_sync_master(crtc_state) ||
222 is_trans_port_sync_slave(crtc_state);
225 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
228 i915_reg_t reg = PIPEDSL(pipe);
232 if (IS_GEN(dev_priv, 2))
233 line_mask = DSL_LINEMASK_GEN2;
235 line_mask = DSL_LINEMASK_GEN3;
237 line1 = intel_de_read(dev_priv, reg) & line_mask;
239 line2 = intel_de_read(dev_priv, reg) & line_mask;
241 return line1 != line2;
244 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
246 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
247 enum pipe pipe = crtc->pipe;
249 /* Wait for the display line to settle/start moving */
250 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
251 drm_err(&dev_priv->drm,
252 "pipe %c scanline %s wait timed out\n",
253 pipe_name(pipe), onoff(state));
256 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
258 wait_for_pipe_scanline_moving(crtc, false);
261 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
263 wait_for_pipe_scanline_moving(crtc, true);
267 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
269 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
270 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
272 if (INTEL_GEN(dev_priv) >= 4) {
273 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
274 i915_reg_t reg = PIPECONF(cpu_transcoder);
276 /* Wait for the Pipe State to go off */
277 if (intel_de_wait_for_clear(dev_priv, reg,
278 I965_PIPECONF_ACTIVE, 100))
279 drm_WARN(&dev_priv->drm, 1,
280 "pipe_off wait timed out\n");
282 intel_wait_for_pipe_scanline_stopped(crtc);
286 /* Only for pre-ILK configs */
287 void assert_pll(struct drm_i915_private *dev_priv,
288 enum pipe pipe, bool state)
293 val = intel_de_read(dev_priv, DPLL(pipe));
294 cur_state = !!(val & DPLL_VCO_ENABLE);
295 I915_STATE_WARN(cur_state != state,
296 "PLL state assertion failure (expected %s, current %s)\n",
297 onoff(state), onoff(cur_state));
300 /* XXX: the dsi pll is shared between MIPI DSI ports */
301 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
306 vlv_cck_get(dev_priv);
307 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
308 vlv_cck_put(dev_priv);
310 cur_state = val & DSI_PLL_VCO_EN;
311 I915_STATE_WARN(cur_state != state,
312 "DSI PLL state assertion failure (expected %s, current %s)\n",
313 onoff(state), onoff(cur_state));
316 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
317 enum pipe pipe, bool state)
321 if (HAS_DDI(dev_priv)) {
323 * DDI does not have a specific FDI_TX register.
325 * FDI is never fed from EDP transcoder
326 * so pipe->transcoder cast is fine here.
328 enum transcoder cpu_transcoder = (enum transcoder)pipe;
329 u32 val = intel_de_read(dev_priv,
330 TRANS_DDI_FUNC_CTL(cpu_transcoder));
331 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
333 u32 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe));
334 cur_state = !!(val & FDI_TX_ENABLE);
336 I915_STATE_WARN(cur_state != state,
337 "FDI TX state assertion failure (expected %s, current %s)\n",
338 onoff(state), onoff(cur_state));
340 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
341 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
343 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
344 enum pipe pipe, bool state)
349 val = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
350 cur_state = !!(val & FDI_RX_ENABLE);
351 I915_STATE_WARN(cur_state != state,
352 "FDI RX state assertion failure (expected %s, current %s)\n",
353 onoff(state), onoff(cur_state));
355 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
356 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
358 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
363 /* ILK FDI PLL is always enabled */
364 if (IS_GEN(dev_priv, 5))
367 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
368 if (HAS_DDI(dev_priv))
371 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe));
372 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
375 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
376 enum pipe pipe, bool state)
381 val = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
382 cur_state = !!(val & FDI_RX_PLL_ENABLE);
383 I915_STATE_WARN(cur_state != state,
384 "FDI RX PLL assertion failure (expected %s, current %s)\n",
385 onoff(state), onoff(cur_state));
388 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
392 enum pipe panel_pipe = INVALID_PIPE;
395 if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv)))
398 if (HAS_PCH_SPLIT(dev_priv)) {
401 pp_reg = PP_CONTROL(0);
402 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
405 case PANEL_PORT_SELECT_LVDS:
406 intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
408 case PANEL_PORT_SELECT_DPA:
409 intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
411 case PANEL_PORT_SELECT_DPC:
412 intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
414 case PANEL_PORT_SELECT_DPD:
415 intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
418 MISSING_CASE(port_sel);
421 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
422 /* presumably write lock depends on pipe, not port select */
423 pp_reg = PP_CONTROL(pipe);
428 pp_reg = PP_CONTROL(0);
429 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
431 drm_WARN_ON(&dev_priv->drm,
432 port_sel != PANEL_PORT_SELECT_LVDS);
433 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
436 val = intel_de_read(dev_priv, pp_reg);
437 if (!(val & PANEL_POWER_ON) ||
438 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
441 I915_STATE_WARN(panel_pipe == pipe && locked,
442 "panel assertion failure, pipe %c regs locked\n",
446 void assert_pipe(struct drm_i915_private *dev_priv,
447 enum transcoder cpu_transcoder, bool state)
450 enum intel_display_power_domain power_domain;
451 intel_wakeref_t wakeref;
453 /* we keep both pipes enabled on 830 */
454 if (IS_I830(dev_priv))
457 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
458 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
460 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
461 cur_state = !!(val & PIPECONF_ENABLE);
463 intel_display_power_put(dev_priv, power_domain, wakeref);
468 I915_STATE_WARN(cur_state != state,
469 "transcoder %s assertion failure (expected %s, current %s)\n",
470 transcoder_name(cpu_transcoder),
471 onoff(state), onoff(cur_state));
474 static void assert_plane(struct intel_plane *plane, bool state)
479 cur_state = plane->get_hw_state(plane, &pipe);
481 I915_STATE_WARN(cur_state != state,
482 "%s assertion failure (expected %s, current %s)\n",
483 plane->base.name, onoff(state), onoff(cur_state));
486 #define assert_plane_enabled(p) assert_plane(p, true)
487 #define assert_plane_disabled(p) assert_plane(p, false)
489 static void assert_planes_disabled(struct intel_crtc *crtc)
491 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
492 struct intel_plane *plane;
494 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
495 assert_plane_disabled(plane);
498 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
504 val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe));
505 enabled = !!(val & TRANS_ENABLE);
506 I915_STATE_WARN(enabled,
507 "transcoder assertion failed, should be off on pipe %c but is still active\n",
511 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
512 enum pipe pipe, enum port port,
518 state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
520 I915_STATE_WARN(state && port_pipe == pipe,
521 "PCH DP %c enabled on transcoder %c, should be disabled\n",
522 port_name(port), pipe_name(pipe));
524 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
525 "IBX PCH DP %c still using transcoder B\n",
529 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
530 enum pipe pipe, enum port port,
536 state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
538 I915_STATE_WARN(state && port_pipe == pipe,
539 "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
540 port_name(port), pipe_name(pipe));
542 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
543 "IBX PCH HDMI %c still using transcoder B\n",
547 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
552 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
553 assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
554 assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
556 I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
558 "PCH VGA enabled on transcoder %c, should be disabled\n",
561 I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
563 "PCH LVDS enabled on transcoder %c, should be disabled\n",
566 /* PCH SDVOB multiplex with HDMIB */
567 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
568 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
569 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
572 static void _vlv_enable_pll(struct intel_crtc *crtc,
573 const struct intel_crtc_state *pipe_config)
575 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
576 enum pipe pipe = crtc->pipe;
578 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);
579 intel_de_posting_read(dev_priv, DPLL(pipe));
582 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
583 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe);
586 static void vlv_enable_pll(struct intel_crtc *crtc,
587 const struct intel_crtc_state *pipe_config)
589 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
590 enum pipe pipe = crtc->pipe;
592 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
594 /* PLL is protected by panel, make sure we can write it */
595 assert_panel_unlocked(dev_priv, pipe);
597 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
598 _vlv_enable_pll(crtc, pipe_config);
600 intel_de_write(dev_priv, DPLL_MD(pipe),
601 pipe_config->dpll_hw_state.dpll_md);
602 intel_de_posting_read(dev_priv, DPLL_MD(pipe));
606 static void _chv_enable_pll(struct intel_crtc *crtc,
607 const struct intel_crtc_state *pipe_config)
609 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
610 enum pipe pipe = crtc->pipe;
611 enum dpio_channel port = vlv_pipe_to_channel(pipe);
614 vlv_dpio_get(dev_priv);
616 /* Enable back the 10bit clock to display controller */
617 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
618 tmp |= DPIO_DCLKP_EN;
619 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
621 vlv_dpio_put(dev_priv);
624 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
629 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);
631 /* Check PLL is locked */
632 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
633 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe);
636 static void chv_enable_pll(struct intel_crtc *crtc,
637 const struct intel_crtc_state *pipe_config)
639 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
640 enum pipe pipe = crtc->pipe;
642 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
644 /* PLL is protected by panel, make sure we can write it */
645 assert_panel_unlocked(dev_priv, pipe);
647 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
648 _chv_enable_pll(crtc, pipe_config);
650 if (pipe != PIPE_A) {
652 * WaPixelRepeatModeFixForC0:chv
654 * DPLLCMD is AWOL. Use chicken bits to propagate
655 * the value from DPLLBMD to either pipe B or C.
657 intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
658 intel_de_write(dev_priv, DPLL_MD(PIPE_B),
659 pipe_config->dpll_hw_state.dpll_md);
660 intel_de_write(dev_priv, CBR4_VLV, 0);
661 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
664 * DPLLB VGA mode also seems to cause problems.
665 * We should always have it disabled.
667 drm_WARN_ON(&dev_priv->drm,
668 (intel_de_read(dev_priv, DPLL(PIPE_B)) &
669 DPLL_VGA_MODE_DIS) == 0);
671 intel_de_write(dev_priv, DPLL_MD(pipe),
672 pipe_config->dpll_hw_state.dpll_md);
673 intel_de_posting_read(dev_priv, DPLL_MD(pipe));
677 static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
679 if (IS_I830(dev_priv))
682 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
685 static void i9xx_enable_pll(struct intel_crtc *crtc,
686 const struct intel_crtc_state *crtc_state)
688 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
689 i915_reg_t reg = DPLL(crtc->pipe);
690 u32 dpll = crtc_state->dpll_hw_state.dpll;
693 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
695 /* PLL is protected by panel, make sure we can write it */
696 if (i9xx_has_pps(dev_priv))
697 assert_panel_unlocked(dev_priv, crtc->pipe);
700 * Apparently we need to have VGA mode enabled prior to changing
701 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
702 * dividers, even though the register value does change.
704 intel_de_write(dev_priv, reg, dpll & ~DPLL_VGA_MODE_DIS);
705 intel_de_write(dev_priv, reg, dpll);
707 /* Wait for the clocks to stabilize. */
708 intel_de_posting_read(dev_priv, reg);
711 if (INTEL_GEN(dev_priv) >= 4) {
712 intel_de_write(dev_priv, DPLL_MD(crtc->pipe),
713 crtc_state->dpll_hw_state.dpll_md);
715 /* The pixel multiplier can only be updated once the
716 * DPLL is enabled and the clocks are stable.
720 intel_de_write(dev_priv, reg, dpll);
723 /* We do this three times for luck */
724 for (i = 0; i < 3; i++) {
725 intel_de_write(dev_priv, reg, dpll);
726 intel_de_posting_read(dev_priv, reg);
727 udelay(150); /* wait for warmup */
731 static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
733 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
734 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
735 enum pipe pipe = crtc->pipe;
737 /* Don't disable pipe or pipe PLLs if needed */
738 if (IS_I830(dev_priv))
741 /* Make sure the pipe isn't still relying on us */
742 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
744 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
745 intel_de_posting_read(dev_priv, DPLL(pipe));
748 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
752 /* Make sure the pipe isn't still relying on us */
753 assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
755 val = DPLL_INTEGRATED_REF_CLK_VLV |
756 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
758 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
760 intel_de_write(dev_priv, DPLL(pipe), val);
761 intel_de_posting_read(dev_priv, DPLL(pipe));
764 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
766 enum dpio_channel port = vlv_pipe_to_channel(pipe);
769 /* Make sure the pipe isn't still relying on us */
770 assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
772 val = DPLL_SSC_REF_CLK_CHV |
773 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
775 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
777 intel_de_write(dev_priv, DPLL(pipe), val);
778 intel_de_posting_read(dev_priv, DPLL(pipe));
780 vlv_dpio_get(dev_priv);
782 /* Disable 10bit clock to display controller */
783 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
784 val &= ~DPIO_DCLKP_EN;
785 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
787 vlv_dpio_put(dev_priv);
790 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
791 struct intel_digital_port *dig_port,
792 unsigned int expected_mask)
797 switch (dig_port->base.port) {
799 port_mask = DPLL_PORTB_READY_MASK;
803 port_mask = DPLL_PORTC_READY_MASK;
808 port_mask = DPLL_PORTD_READY_MASK;
809 dpll_reg = DPIO_PHY_STATUS;
815 if (intel_de_wait_for_register(dev_priv, dpll_reg,
816 port_mask, expected_mask, 1000))
817 drm_WARN(&dev_priv->drm, 1,
818 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
819 dig_port->base.base.base.id, dig_port->base.base.name,
820 intel_de_read(dev_priv, dpll_reg) & port_mask,
824 static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
826 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
827 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
828 enum pipe pipe = crtc->pipe;
830 u32 val, pipeconf_val;
832 /* Make sure PCH DPLL is enabled */
833 assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
835 /* FDI must be feeding us bits for PCH ports */
836 assert_fdi_tx_enabled(dev_priv, pipe);
837 assert_fdi_rx_enabled(dev_priv, pipe);
839 if (HAS_PCH_CPT(dev_priv)) {
840 reg = TRANS_CHICKEN2(pipe);
841 val = intel_de_read(dev_priv, reg);
843 * Workaround: Set the timing override bit
844 * before enabling the pch transcoder.
846 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
847 /* Configure frame start delay to match the CPU */
848 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
849 val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
850 intel_de_write(dev_priv, reg, val);
853 reg = PCH_TRANSCONF(pipe);
854 val = intel_de_read(dev_priv, reg);
855 pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe));
857 if (HAS_PCH_IBX(dev_priv)) {
858 /* Configure frame start delay to match the CPU */
859 val &= ~TRANS_FRAME_START_DELAY_MASK;
860 val |= TRANS_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
863 * Make the BPC in transcoder be consistent with
864 * that in pipeconf reg. For HDMI we must use 8bpc
865 * here for both 8bpc and 12bpc.
867 val &= ~PIPECONF_BPC_MASK;
868 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
869 val |= PIPECONF_8BPC;
871 val |= pipeconf_val & PIPECONF_BPC_MASK;
874 val &= ~TRANS_INTERLACE_MASK;
875 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
876 if (HAS_PCH_IBX(dev_priv) &&
877 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
878 val |= TRANS_LEGACY_INTERLACED_ILK;
880 val |= TRANS_INTERLACED;
882 val |= TRANS_PROGRESSIVE;
885 intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
886 if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
887 drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",
891 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
892 enum transcoder cpu_transcoder)
894 u32 val, pipeconf_val;
896 /* FDI must be feeding us bits for PCH ports */
897 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
898 assert_fdi_rx_enabled(dev_priv, PIPE_A);
900 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
901 /* Workaround: set timing override bit. */
902 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
903 /* Configure frame start delay to match the CPU */
904 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
905 val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
906 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
909 pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
911 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
912 PIPECONF_INTERLACED_ILK)
913 val |= TRANS_INTERLACED;
915 val |= TRANS_PROGRESSIVE;
917 intel_de_write(dev_priv, LPT_TRANSCONF, val);
918 if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
919 TRANS_STATE_ENABLE, 100))
920 drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n");
923 static void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv,
929 /* FDI relies on the transcoder */
930 assert_fdi_tx_disabled(dev_priv, pipe);
931 assert_fdi_rx_disabled(dev_priv, pipe);
933 /* Ports must be off as well */
934 assert_pch_ports_disabled(dev_priv, pipe);
936 reg = PCH_TRANSCONF(pipe);
937 val = intel_de_read(dev_priv, reg);
938 val &= ~TRANS_ENABLE;
939 intel_de_write(dev_priv, reg, val);
940 /* wait for PCH transcoder off, transcoder state */
941 if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
942 drm_err(&dev_priv->drm, "failed to disable transcoder %c\n",
945 if (HAS_PCH_CPT(dev_priv)) {
946 /* Workaround: Clear the timing override chicken bit again. */
947 reg = TRANS_CHICKEN2(pipe);
948 val = intel_de_read(dev_priv, reg);
949 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
950 intel_de_write(dev_priv, reg, val);
954 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
958 val = intel_de_read(dev_priv, LPT_TRANSCONF);
959 val &= ~TRANS_ENABLE;
960 intel_de_write(dev_priv, LPT_TRANSCONF, val);
961 /* wait for PCH transcoder off, transcoder state */
962 if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
963 TRANS_STATE_ENABLE, 50))
964 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
966 /* Workaround: clear timing override bit. */
967 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
968 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
969 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
972 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
974 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
976 if (HAS_PCH_LPT(dev_priv))
982 void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
984 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
985 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
986 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
987 enum pipe pipe = crtc->pipe;
991 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
993 assert_planes_disabled(crtc);
996 * A pipe without a PLL won't actually be able to drive bits from
997 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1000 if (HAS_GMCH(dev_priv)) {
1001 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1002 assert_dsi_pll_enabled(dev_priv);
1004 assert_pll_enabled(dev_priv, pipe);
1006 if (new_crtc_state->has_pch_encoder) {
1007 /* if driving the PCH, we need FDI enabled */
1008 assert_fdi_rx_pll_enabled(dev_priv,
1009 intel_crtc_pch_transcoder(crtc));
1010 assert_fdi_tx_pll_enabled(dev_priv,
1011 (enum pipe) cpu_transcoder);
1013 /* FIXME: assert CPU port conditions for SNB+ */
1016 trace_intel_pipe_enable(crtc);
1018 reg = PIPECONF(cpu_transcoder);
1019 val = intel_de_read(dev_priv, reg);
1020 if (val & PIPECONF_ENABLE) {
1021 /* we keep both pipes enabled on 830 */
1022 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
1026 intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE);
1027 intel_de_posting_read(dev_priv, reg);
1030 * Until the pipe starts PIPEDSL reads will return a stale value,
1031 * which causes an apparent vblank timestamp jump when PIPEDSL
1032 * resets to its proper value. That also messes up the frame count
1033 * when it's derived from the timestamps. So let's wait for the
1034 * pipe to start properly before we call drm_crtc_vblank_on()
1036 if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
1037 intel_wait_for_pipe_scanline_moving(crtc);
1040 void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1042 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1043 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1044 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1045 enum pipe pipe = crtc->pipe;
1049 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));
1052 * Make sure planes won't keep trying to pump pixels to us,
1053 * or we might hang the display.
1055 assert_planes_disabled(crtc);
1057 trace_intel_pipe_disable(crtc);
1059 reg = PIPECONF(cpu_transcoder);
1060 val = intel_de_read(dev_priv, reg);
1061 if ((val & PIPECONF_ENABLE) == 0)
1065 * Double wide has implications for planes
1066 * so best keep it disabled when not needed.
1068 if (old_crtc_state->double_wide)
1069 val &= ~PIPECONF_DOUBLE_WIDE;
1071 /* Don't disable pipe or pipe PLLs if needed */
1072 if (!IS_I830(dev_priv))
1073 val &= ~PIPECONF_ENABLE;
1075 intel_de_write(dev_priv, reg, val);
1076 if ((val & PIPECONF_ENABLE) == 0)
1077 intel_wait_for_pipe_off(old_crtc_state);
1080 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1082 return IS_GEN(dev_priv, 2) ? 2048 : 4096;
1085 static bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
1087 if (!is_ccs_modifier(fb->modifier))
1090 return plane >= fb->format->num_planes / 2;
1093 static bool is_gen12_ccs_modifier(u64 modifier)
1095 return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
1096 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
1097 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
1100 static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
1102 return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
1105 static bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane)
1107 return fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC &&
1111 static bool is_aux_plane(const struct drm_framebuffer *fb, int plane)
1113 if (is_ccs_modifier(fb->modifier))
1114 return is_ccs_plane(fb, plane);
1119 static int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
1121 drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
1122 (main_plane && main_plane >= fb->format->num_planes / 2));
1124 return fb->format->num_planes / 2 + main_plane;
1127 static int ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
1129 drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
1130 ccs_plane < fb->format->num_planes / 2);
1132 if (is_gen12_ccs_cc_plane(fb, ccs_plane))
1135 return ccs_plane - fb->format->num_planes / 2;
1138 int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
1140 struct drm_i915_private *i915 = to_i915(fb->dev);
1142 if (is_ccs_modifier(fb->modifier))
1143 return main_to_ccs_plane(fb, main_plane);
1144 else if (INTEL_GEN(i915) < 11 &&
1145 intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
1152 intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
1155 return info->is_yuv &&
1156 info->num_planes == (is_ccs_modifier(modifier) ? 4 : 2);
1159 static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb,
1162 return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
1167 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
1169 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1170 unsigned int cpp = fb->format->cpp[color_plane];
1172 switch (fb->modifier) {
1173 case DRM_FORMAT_MOD_LINEAR:
1174 return intel_tile_size(dev_priv);
1175 case I915_FORMAT_MOD_X_TILED:
1176 if (IS_GEN(dev_priv, 2))
1180 case I915_FORMAT_MOD_Y_TILED_CCS:
1181 if (is_ccs_plane(fb, color_plane))
1184 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
1185 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
1186 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
1187 if (is_ccs_plane(fb, color_plane))
1190 case I915_FORMAT_MOD_Y_TILED:
1191 if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
1195 case I915_FORMAT_MOD_Yf_TILED_CCS:
1196 if (is_ccs_plane(fb, color_plane))
1199 case I915_FORMAT_MOD_Yf_TILED:
1215 MISSING_CASE(fb->modifier);
1221 intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
1223 if (is_gen12_ccs_plane(fb, color_plane))
1226 return intel_tile_size(to_i915(fb->dev)) /
1227 intel_tile_width_bytes(fb, color_plane);
1230 /* Return the tile dimensions in pixel units */
1231 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
1232 unsigned int *tile_width,
1233 unsigned int *tile_height)
1235 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
1236 unsigned int cpp = fb->format->cpp[color_plane];
1238 *tile_width = tile_width_bytes / cpp;
1239 *tile_height = intel_tile_height(fb, color_plane);
1242 static unsigned int intel_tile_row_size(const struct drm_framebuffer *fb,
1245 unsigned int tile_width, tile_height;
1247 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
1249 return fb->pitches[color_plane] * tile_height;
1253 intel_fb_align_height(const struct drm_framebuffer *fb,
1254 int color_plane, unsigned int height)
1256 unsigned int tile_height = intel_tile_height(fb, color_plane);
1258 return ALIGN(height, tile_height);
1261 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
1263 unsigned int size = 0;
1266 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
1267 size += rot_info->plane[i].width * rot_info->plane[i].height;
1272 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
1274 unsigned int size = 0;
1277 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++)
1278 size += rem_info->plane[i].width * rem_info->plane[i].height;
1284 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
1285 const struct drm_framebuffer *fb,
1286 unsigned int rotation)
1288 view->type = I915_GGTT_VIEW_NORMAL;
1289 if (drm_rotation_90_or_270(rotation)) {
1290 view->type = I915_GGTT_VIEW_ROTATED;
1291 view->rotated = to_intel_framebuffer(fb)->rot_info;
1295 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
1297 if (IS_I830(dev_priv))
1299 else if (IS_I85X(dev_priv))
1301 else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1307 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
1309 if (INTEL_GEN(dev_priv) >= 9)
1311 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
1312 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1314 else if (INTEL_GEN(dev_priv) >= 4)
1320 static bool has_async_flips(struct drm_i915_private *i915)
1322 return INTEL_GEN(i915) >= 5;
1325 unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
1328 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1330 /* AUX_DIST needs only 4K alignment */
1331 if ((INTEL_GEN(dev_priv) < 12 && is_aux_plane(fb, color_plane)) ||
1332 is_ccs_plane(fb, color_plane))
1335 switch (fb->modifier) {
1336 case DRM_FORMAT_MOD_LINEAR:
1337 return intel_linear_alignment(dev_priv);
1338 case I915_FORMAT_MOD_X_TILED:
1339 if (has_async_flips(dev_priv))
1342 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
1343 if (is_semiplanar_uv_plane(fb, color_plane))
1344 return intel_tile_row_size(fb, color_plane);
1346 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
1347 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
1349 case I915_FORMAT_MOD_Y_TILED_CCS:
1350 case I915_FORMAT_MOD_Yf_TILED_CCS:
1351 case I915_FORMAT_MOD_Y_TILED:
1352 if (INTEL_GEN(dev_priv) >= 12 &&
1353 is_semiplanar_uv_plane(fb, color_plane))
1354 return intel_tile_row_size(fb, color_plane);
1356 case I915_FORMAT_MOD_Yf_TILED:
1357 return 1 * 1024 * 1024;
1359 MISSING_CASE(fb->modifier);
1364 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
1366 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1367 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1369 return INTEL_GEN(dev_priv) < 4 ||
1371 plane_state->view.type == I915_GGTT_VIEW_NORMAL);
1375 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1376 const struct i915_ggtt_view *view,
1378 unsigned long *out_flags)
1380 struct drm_device *dev = fb->dev;
1381 struct drm_i915_private *dev_priv = to_i915(dev);
1382 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1383 intel_wakeref_t wakeref;
1384 struct i915_vma *vma;
1385 unsigned int pinctl;
1388 if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj)))
1389 return ERR_PTR(-EINVAL);
1391 alignment = intel_surf_alignment(fb, 0);
1392 if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment)))
1393 return ERR_PTR(-EINVAL);
1395 /* Note that the w/a also requires 64 PTE of padding following the
1396 * bo. We currently fill all unused PTE with the shadow page and so
1397 * we should always have valid PTE following the scanout preventing
1400 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
1401 alignment = 256 * 1024;
1404 * Global gtt pte registers are special registers which actually forward
1405 * writes to a chunk of system memory. Which means that there is no risk
1406 * that the register values disappear as soon as we call
1407 * intel_runtime_pm_put(), so it is correct to wrap only the
1408 * pin/unpin/fence and not more.
1410 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
1412 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
1415 * Valleyview is definitely limited to scanning out the first
1416 * 512MiB. Lets presume this behaviour was inherited from the
1417 * g4x display engine and that all earlier gen are similarly
1418 * limited. Testing suggests that it is a little more
1419 * complicated than this. For example, Cherryview appears quite
1420 * happy to scanout from anywhere within its global aperture.
1423 if (HAS_GMCH(dev_priv))
1424 pinctl |= PIN_MAPPABLE;
1426 vma = i915_gem_object_pin_to_display_plane(obj,
1427 alignment, view, pinctl);
1431 if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
1435 * Install a fence for tiled scan-out. Pre-i965 always needs a
1436 * fence, whereas 965+ only requires a fence if using
1437 * framebuffer compression. For simplicity, we always, when
1438 * possible, install a fence as the cost is not that onerous.
1440 * If we fail to fence the tiled scanout, then either the
1441 * modeset will reject the change (which is highly unlikely as
1442 * the affected systems, all but one, do not have unmappable
1443 * space) or we will not be able to enable full powersaving
1444 * techniques (also likely not to apply due to various limits
1445 * FBC and the like impose on the size of the buffer, which
1446 * presumably we violated anyway with this unmappable buffer).
1447 * Anyway, it is presumably better to stumble onwards with
1448 * something and try to run the system in a "less than optimal"
1449 * mode that matches the user configuration.
1451 ret = i915_vma_pin_fence(vma);
1452 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
1453 i915_vma_unpin(vma);
1458 if (ret == 0 && vma->fence)
1459 *out_flags |= PLANE_HAS_FENCE;
1464 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
1465 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
1469 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
1471 if (flags & PLANE_HAS_FENCE)
1472 i915_vma_unpin_fence(vma);
1473 i915_vma_unpin(vma);
1477 static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane,
1478 unsigned int rotation)
1480 if (drm_rotation_90_or_270(rotation))
1481 return to_intel_framebuffer(fb)->rotated[color_plane].pitch;
1483 return fb->pitches[color_plane];
1487 * Convert the x/y offsets into a linear offset.
1488 * Only valid with 0/180 degree rotation, which is fine since linear
1489 * offset is only used with linear buffers on pre-hsw and tiled buffers
1490 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
1492 u32 intel_fb_xy_to_linear(int x, int y,
1493 const struct intel_plane_state *state,
1496 const struct drm_framebuffer *fb = state->hw.fb;
1497 unsigned int cpp = fb->format->cpp[color_plane];
1498 unsigned int pitch = state->color_plane[color_plane].stride;
1500 return y * pitch + x * cpp;
1504 * Add the x/y offsets derived from fb->offsets[] to the user
1505 * specified plane src x/y offsets. The resulting x/y offsets
1506 * specify the start of scanout from the beginning of the gtt mapping.
1508 void intel_add_fb_offsets(int *x, int *y,
1509 const struct intel_plane_state *state,
1513 *x += state->color_plane[color_plane].x;
1514 *y += state->color_plane[color_plane].y;
1517 static u32 intel_adjust_tile_offset(int *x, int *y,
1518 unsigned int tile_width,
1519 unsigned int tile_height,
1520 unsigned int tile_size,
1521 unsigned int pitch_tiles,
1525 unsigned int pitch_pixels = pitch_tiles * tile_width;
1528 WARN_ON(old_offset & (tile_size - 1));
1529 WARN_ON(new_offset & (tile_size - 1));
1530 WARN_ON(new_offset > old_offset);
1532 tiles = (old_offset - new_offset) / tile_size;
1534 *y += tiles / pitch_tiles * tile_height;
1535 *x += tiles % pitch_tiles * tile_width;
1537 /* minimize x in case it got needlessly big */
1538 *y += *x / pitch_pixels * tile_height;
1544 static bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
1546 return fb->modifier == DRM_FORMAT_MOD_LINEAR ||
1547 is_gen12_ccs_plane(fb, color_plane);
1550 static u32 intel_adjust_aligned_offset(int *x, int *y,
1551 const struct drm_framebuffer *fb,
1553 unsigned int rotation,
1555 u32 old_offset, u32 new_offset)
1557 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1558 unsigned int cpp = fb->format->cpp[color_plane];
1560 drm_WARN_ON(&dev_priv->drm, new_offset > old_offset);
1562 if (!is_surface_linear(fb, color_plane)) {
1563 unsigned int tile_size, tile_width, tile_height;
1564 unsigned int pitch_tiles;
1566 tile_size = intel_tile_size(dev_priv);
1567 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
1569 if (drm_rotation_90_or_270(rotation)) {
1570 pitch_tiles = pitch / tile_height;
1571 swap(tile_width, tile_height);
1573 pitch_tiles = pitch / (tile_width * cpp);
1576 intel_adjust_tile_offset(x, y, tile_width, tile_height,
1577 tile_size, pitch_tiles,
1578 old_offset, new_offset);
1580 old_offset += *y * pitch + *x * cpp;
1582 *y = (old_offset - new_offset) / pitch;
1583 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
1590 * Adjust the tile offset by moving the difference into
1593 u32 intel_plane_adjust_aligned_offset(int *x, int *y,
1594 const struct intel_plane_state *state,
1596 u32 old_offset, u32 new_offset)
1598 return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane,
1600 state->color_plane[color_plane].stride,
1601 old_offset, new_offset);
1605 * Computes the aligned offset to the base tile and adjusts
1606 * x, y. bytes per pixel is assumed to be a power-of-two.
1608 * In the 90/270 rotated case, x and y are assumed
1609 * to be already rotated to match the rotated GTT view, and
1610 * pitch is the tile_height aligned framebuffer height.
1612 * This function is used when computing the derived information
1613 * under intel_framebuffer, so using any of that information
1614 * here is not allowed. Anything under drm_framebuffer can be
1615 * used. This is why the user has to pass in the pitch since it
1616 * is specified in the rotated orientation.
1618 static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
1620 const struct drm_framebuffer *fb,
1623 unsigned int rotation,
1626 unsigned int cpp = fb->format->cpp[color_plane];
1627 u32 offset, offset_aligned;
1629 if (!is_surface_linear(fb, color_plane)) {
1630 unsigned int tile_size, tile_width, tile_height;
1631 unsigned int tile_rows, tiles, pitch_tiles;
1633 tile_size = intel_tile_size(dev_priv);
1634 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
1636 if (drm_rotation_90_or_270(rotation)) {
1637 pitch_tiles = pitch / tile_height;
1638 swap(tile_width, tile_height);
1640 pitch_tiles = pitch / (tile_width * cpp);
1643 tile_rows = *y / tile_height;
1646 tiles = *x / tile_width;
1649 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
1651 offset_aligned = offset;
1653 offset_aligned = rounddown(offset_aligned, alignment);
1655 intel_adjust_tile_offset(x, y, tile_width, tile_height,
1656 tile_size, pitch_tiles,
1657 offset, offset_aligned);
1659 offset = *y * pitch + *x * cpp;
1660 offset_aligned = offset;
1662 offset_aligned = rounddown(offset_aligned, alignment);
1663 *y = (offset % alignment) / pitch;
1664 *x = ((offset % alignment) - *y * pitch) / cpp;
1670 return offset_aligned;
1673 u32 intel_plane_compute_aligned_offset(int *x, int *y,
1674 const struct intel_plane_state *state,
1677 struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane);
1678 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
1679 const struct drm_framebuffer *fb = state->hw.fb;
1680 unsigned int rotation = state->hw.rotation;
1681 int pitch = state->color_plane[color_plane].stride;
1684 if (intel_plane->id == PLANE_CURSOR)
1685 alignment = intel_cursor_alignment(dev_priv);
1687 alignment = intel_surf_alignment(fb, color_plane);
1689 return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane,
1690 pitch, rotation, alignment);
1693 /* Convert the fb->offset[] into x/y offsets */
1694 static int intel_fb_offset_to_xy(int *x, int *y,
1695 const struct drm_framebuffer *fb,
1698 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1699 unsigned int height;
1702 if (INTEL_GEN(dev_priv) >= 12 &&
1703 is_semiplanar_uv_plane(fb, color_plane))
1704 alignment = intel_tile_row_size(fb, color_plane);
1705 else if (fb->modifier != DRM_FORMAT_MOD_LINEAR)
1706 alignment = intel_tile_size(dev_priv);
1710 if (alignment != 0 && fb->offsets[color_plane] % alignment) {
1711 drm_dbg_kms(&dev_priv->drm,
1712 "Misaligned offset 0x%08x for color plane %d\n",
1713 fb->offsets[color_plane], color_plane);
1717 height = drm_framebuffer_plane_height(fb->height, fb, color_plane);
1718 height = ALIGN(height, intel_tile_height(fb, color_plane));
1720 /* Catch potential overflows early */
1721 if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]),
1722 fb->offsets[color_plane])) {
1723 drm_dbg_kms(&dev_priv->drm,
1724 "Bad offset 0x%08x or pitch %d for color plane %d\n",
1725 fb->offsets[color_plane], fb->pitches[color_plane],
1733 intel_adjust_aligned_offset(x, y,
1734 fb, color_plane, DRM_MODE_ROTATE_0,
1735 fb->pitches[color_plane],
1736 fb->offsets[color_plane], 0);
1741 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
1743 switch (fb_modifier) {
1744 case I915_FORMAT_MOD_X_TILED:
1745 return I915_TILING_X;
1746 case I915_FORMAT_MOD_Y_TILED:
1747 case I915_FORMAT_MOD_Y_TILED_CCS:
1748 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
1749 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
1750 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
1751 return I915_TILING_Y;
1753 return I915_TILING_NONE;
1758 * From the Sky Lake PRM:
1759 * "The Color Control Surface (CCS) contains the compression status of
1760 * the cache-line pairs. The compression state of the cache-line pair
1761 * is specified by 2 bits in the CCS. Each CCS cache-line represents
1762 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
1763 * cache-line-pairs. CCS is always Y tiled."
1765 * Since cache line pairs refers to horizontally adjacent cache lines,
1766 * each cache line in the CCS corresponds to an area of 32x16 cache
1767 * lines on the main surface. Since each pixel is 4 bytes, this gives
1768 * us a ratio of one byte in the CCS for each 8x16 pixels in the
1771 static const struct drm_format_info skl_ccs_formats[] = {
1772 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
1773 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
1774 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
1775 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
1776 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
1777 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
1778 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
1779 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
1783 * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
1784 * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
1785 * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
1786 * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
1789 static const struct drm_format_info gen12_ccs_formats[] = {
1790 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
1791 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1792 .hsub = 1, .vsub = 1, },
1793 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
1794 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1795 .hsub = 1, .vsub = 1, },
1796 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
1797 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1798 .hsub = 1, .vsub = 1, .has_alpha = true },
1799 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
1800 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1801 .hsub = 1, .vsub = 1, .has_alpha = true },
1802 { .format = DRM_FORMAT_YUYV, .num_planes = 2,
1803 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1804 .hsub = 2, .vsub = 1, .is_yuv = true },
1805 { .format = DRM_FORMAT_YVYU, .num_planes = 2,
1806 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1807 .hsub = 2, .vsub = 1, .is_yuv = true },
1808 { .format = DRM_FORMAT_UYVY, .num_planes = 2,
1809 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1810 .hsub = 2, .vsub = 1, .is_yuv = true },
1811 { .format = DRM_FORMAT_VYUY, .num_planes = 2,
1812 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1813 .hsub = 2, .vsub = 1, .is_yuv = true },
1814 { .format = DRM_FORMAT_NV12, .num_planes = 4,
1815 .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
1816 .hsub = 2, .vsub = 2, .is_yuv = true },
1817 { .format = DRM_FORMAT_P010, .num_planes = 4,
1818 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
1819 .hsub = 2, .vsub = 2, .is_yuv = true },
1820 { .format = DRM_FORMAT_P012, .num_planes = 4,
1821 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
1822 .hsub = 2, .vsub = 2, .is_yuv = true },
1823 { .format = DRM_FORMAT_P016, .num_planes = 4,
1824 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
1825 .hsub = 2, .vsub = 2, .is_yuv = true },
1829 * Same as gen12_ccs_formats[] above, but with additional surface used
1830 * to pass Clear Color information in plane 2 with 64 bits of data.
1832 static const struct drm_format_info gen12_ccs_cc_formats[] = {
1833 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
1834 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
1835 .hsub = 1, .vsub = 1, },
1836 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
1837 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
1838 .hsub = 1, .vsub = 1, },
1839 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
1840 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
1841 .hsub = 1, .vsub = 1, .has_alpha = true },
1842 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
1843 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
1844 .hsub = 1, .vsub = 1, .has_alpha = true },
1847 static const struct drm_format_info *
1848 lookup_format_info(const struct drm_format_info formats[],
1849 int num_formats, u32 format)
1853 for (i = 0; i < num_formats; i++) {
1854 if (formats[i].format == format)
1861 static const struct drm_format_info *
1862 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
1864 switch (cmd->modifier[0]) {
1865 case I915_FORMAT_MOD_Y_TILED_CCS:
1866 case I915_FORMAT_MOD_Yf_TILED_CCS:
1867 return lookup_format_info(skl_ccs_formats,
1868 ARRAY_SIZE(skl_ccs_formats),
1870 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
1871 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
1872 return lookup_format_info(gen12_ccs_formats,
1873 ARRAY_SIZE(gen12_ccs_formats),
1875 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
1876 return lookup_format_info(gen12_ccs_cc_formats,
1877 ARRAY_SIZE(gen12_ccs_cc_formats),
1884 bool is_ccs_modifier(u64 modifier)
1886 return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
1887 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
1888 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
1889 modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
1890 modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
1893 static int gen12_ccs_aux_stride(struct drm_framebuffer *fb, int ccs_plane)
1895 return DIV_ROUND_UP(fb->pitches[ccs_to_main_plane(fb, ccs_plane)],
1899 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
1900 u32 pixel_format, u64 modifier)
1902 struct intel_crtc *crtc;
1903 struct intel_plane *plane;
1906 * We assume the primary plane for pipe A has
1907 * the highest stride limits of them all,
1908 * if in case pipe A is disabled, use the first pipe from pipe_mask.
1910 crtc = intel_get_first_crtc(dev_priv);
1914 plane = to_intel_plane(crtc->base.primary);
1916 return plane->max_stride(plane, pixel_format, modifier,
1921 u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
1922 u32 pixel_format, u64 modifier)
1925 * Arbitrary limit for gen4+ chosen to match the
1926 * render engine max stride.
1928 * The new CCS hash mode makes remapping impossible
1930 if (!is_ccs_modifier(modifier)) {
1931 if (INTEL_GEN(dev_priv) >= 7)
1933 else if (INTEL_GEN(dev_priv) >= 4)
1937 return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
1941 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
1943 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1946 if (is_surface_linear(fb, color_plane)) {
1947 u32 max_stride = intel_plane_fb_max_stride(dev_priv,
1952 * To make remapping with linear generally feasible
1953 * we need the stride to be page aligned.
1955 if (fb->pitches[color_plane] > max_stride &&
1956 !is_ccs_modifier(fb->modifier))
1957 return intel_tile_size(dev_priv);
1962 tile_width = intel_tile_width_bytes(fb, color_plane);
1963 if (is_ccs_modifier(fb->modifier)) {
1965 * Display WA #0531: skl,bxt,kbl,glk
1967 * Render decompression and plane width > 3840
1968 * combined with horizontal panning requires the
1969 * plane stride to be a multiple of 4. We'll just
1970 * require the entire fb to accommodate that to avoid
1971 * potential runtime errors at plane configuration time.
1973 if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb->width > 3840)
1976 * The main surface pitch must be padded to a multiple of four
1979 else if (INTEL_GEN(dev_priv) >= 12)
1985 bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
1987 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1988 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1989 const struct drm_framebuffer *fb = plane_state->hw.fb;
1992 /* We don't want to deal with remapping with cursors */
1993 if (plane->id == PLANE_CURSOR)
1997 * The display engine limits already match/exceed the
1998 * render engine limits, so not much point in remapping.
1999 * Would also need to deal with the fence POT alignment
2000 * and gen2 2KiB GTT tile size.
2002 if (INTEL_GEN(dev_priv) < 4)
2006 * The new CCS hash mode isn't compatible with remapping as
2007 * the virtual address of the pages affects the compressed data.
2009 if (is_ccs_modifier(fb->modifier))
2012 /* Linear needs a page aligned stride for remapping */
2013 if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
2014 unsigned int alignment = intel_tile_size(dev_priv) - 1;
2016 for (i = 0; i < fb->format->num_planes; i++) {
2017 if (fb->pitches[i] & alignment)
2025 static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
2027 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2028 const struct drm_framebuffer *fb = plane_state->hw.fb;
2029 unsigned int rotation = plane_state->hw.rotation;
2030 u32 stride, max_stride;
2033 * No remapping for invisible planes since we don't have
2034 * an actual source viewport to remap.
2036 if (!plane_state->uapi.visible)
2039 if (!intel_plane_can_remap(plane_state))
2043 * FIXME: aux plane limits on gen9+ are
2044 * unclear in Bspec, for now no checking.
2046 stride = intel_fb_pitch(fb, 0, rotation);
2047 max_stride = plane->max_stride(plane, fb->format->format,
2048 fb->modifier, rotation);
2050 return stride > max_stride;
2054 intel_fb_plane_get_subsampling(int *hsub, int *vsub,
2055 const struct drm_framebuffer *fb,
2060 if (color_plane == 0) {
2068 * TODO: Deduct the subsampling from the char block for all CCS
2069 * formats and planes.
2071 if (!is_gen12_ccs_plane(fb, color_plane)) {
2072 *hsub = fb->format->hsub;
2073 *vsub = fb->format->vsub;
2078 main_plane = ccs_to_main_plane(fb, color_plane);
2079 *hsub = drm_format_info_block_width(fb->format, color_plane) /
2080 drm_format_info_block_width(fb->format, main_plane);
2083 * The min stride check in the core framebuffer_check() function
2084 * assumes that format->hsub applies to every plane except for the
2085 * first plane. That's incorrect for the CCS AUX plane of the first
2086 * plane, but for the above check to pass we must define the block
2087 * width with that subsampling applied to it. Adjust the width here
2088 * accordingly, so we can calculate the actual subsampling factor.
2090 if (main_plane == 0)
2091 *hsub *= fb->format->hsub;
2096 intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int ccs_plane, int x, int y)
2098 struct drm_i915_private *i915 = to_i915(fb->dev);
2099 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2102 int tile_width, tile_height;
2106 if (!is_ccs_plane(fb, ccs_plane) || is_gen12_ccs_cc_plane(fb, ccs_plane))
2109 intel_tile_dims(fb, ccs_plane, &tile_width, &tile_height);
2110 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
2113 tile_height *= vsub;
2115 ccs_x = (x * hsub) % tile_width;
2116 ccs_y = (y * vsub) % tile_height;
2118 main_plane = ccs_to_main_plane(fb, ccs_plane);
2119 main_x = intel_fb->normal[main_plane].x % tile_width;
2120 main_y = intel_fb->normal[main_plane].y % tile_height;
2123 * CCS doesn't have its own x/y offset register, so the intra CCS tile
2124 * x/y offsets must match between CCS and the main surface.
2126 if (main_x != ccs_x || main_y != ccs_y) {
2127 drm_dbg_kms(&i915->drm,
2128 "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2131 intel_fb->normal[main_plane].x,
2132 intel_fb->normal[main_plane].y,
2141 intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int color_plane)
2143 int main_plane = is_ccs_plane(fb, color_plane) ?
2144 ccs_to_main_plane(fb, color_plane) : 0;
2145 int main_hsub, main_vsub;
2148 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, main_plane);
2149 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
2150 *w = fb->width / main_hsub / hsub;
2151 *h = fb->height / main_vsub / vsub;
2155 * Setup the rotated view for an FB plane and return the size the GTT mapping
2156 * requires for this view.
2159 setup_fb_rotation(int plane, const struct intel_remapped_plane_info *plane_info,
2160 u32 gtt_offset_rotated, int x, int y,
2161 unsigned int width, unsigned int height,
2162 unsigned int tile_size,
2163 unsigned int tile_width, unsigned int tile_height,
2164 struct drm_framebuffer *fb)
2166 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2167 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2168 unsigned int pitch_tiles;
2171 /* Y or Yf modifiers required for 90/270 rotation */
2172 if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
2173 fb->modifier != I915_FORMAT_MOD_Yf_TILED)
2176 if (drm_WARN_ON(fb->dev, plane >= ARRAY_SIZE(rot_info->plane)))
2179 rot_info->plane[plane] = *plane_info;
2181 intel_fb->rotated[plane].pitch = plane_info->height * tile_height;
2183 /* rotate the x/y offsets to match the GTT view */
2184 drm_rect_init(&r, x, y, width, height);
2186 plane_info->width * tile_width,
2187 plane_info->height * tile_height,
2188 DRM_MODE_ROTATE_270);
2192 /* rotate the tile dimensions to match the GTT view */
2193 pitch_tiles = intel_fb->rotated[plane].pitch / tile_height;
2194 swap(tile_width, tile_height);
2197 * We only keep the x/y offsets, so push all of the
2198 * gtt offset into the x/y offsets.
2200 intel_adjust_tile_offset(&x, &y,
2201 tile_width, tile_height,
2202 tile_size, pitch_tiles,
2203 gtt_offset_rotated * tile_size, 0);
2206 * First pixel of the framebuffer from
2207 * the start of the rotated gtt mapping.
2209 intel_fb->rotated[plane].x = x;
2210 intel_fb->rotated[plane].y = y;
2212 return plane_info->width * plane_info->height;
2216 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2217 struct drm_framebuffer *fb)
2219 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2220 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2221 u32 gtt_offset_rotated = 0;
2222 unsigned int max_size = 0;
2223 int i, num_planes = fb->format->num_planes;
2224 unsigned int tile_size = intel_tile_size(dev_priv);
2226 for (i = 0; i < num_planes; i++) {
2227 unsigned int width, height;
2228 unsigned int cpp, size;
2234 * Plane 2 of Render Compression with Clear Color fb modifier
2235 * is consumed by the driver and not passed to DE. Skip the
2236 * arithmetic related to alignment and offset calculation.
2238 if (is_gen12_ccs_cc_plane(fb, i)) {
2239 if (IS_ALIGNED(fb->offsets[i], PAGE_SIZE))
2245 cpp = fb->format->cpp[i];
2246 intel_fb_plane_dims(&width, &height, fb, i);
2248 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2250 drm_dbg_kms(&dev_priv->drm,
2251 "bad fb plane %d offset: 0x%x\n",
2256 ret = intel_fb_check_ccs_xy(fb, i, x, y);
2261 * The fence (if used) is aligned to the start of the object
2262 * so having the framebuffer wrap around across the edge of the
2263 * fenced region doesn't really work. We have no API to configure
2264 * the fence start offset within the object (nor could we probably
2265 * on gen2/3). So it's just easier if we just require that the
2266 * fb layout agrees with the fence layout. We already check that the
2267 * fb stride matches the fence stride elsewhere.
2269 if (i == 0 && i915_gem_object_is_tiled(obj) &&
2270 (x + width) * cpp > fb->pitches[i]) {
2271 drm_dbg_kms(&dev_priv->drm,
2272 "bad fb plane %d offset: 0x%x\n",
2278 * First pixel of the framebuffer from
2279 * the start of the normal gtt mapping.
2281 intel_fb->normal[i].x = x;
2282 intel_fb->normal[i].y = y;
2284 offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i,
2288 offset /= tile_size;
2290 if (!is_surface_linear(fb, i)) {
2291 struct intel_remapped_plane_info plane_info;
2292 unsigned int tile_width, tile_height;
2294 intel_tile_dims(fb, i, &tile_width, &tile_height);
2296 plane_info.offset = offset;
2297 plane_info.stride = DIV_ROUND_UP(fb->pitches[i],
2299 plane_info.width = DIV_ROUND_UP(x + width, tile_width);
2300 plane_info.height = DIV_ROUND_UP(y + height,
2303 /* how many tiles does this plane need */
2304 size = plane_info.stride * plane_info.height;
2306 * If the plane isn't horizontally tile aligned,
2307 * we need one more tile.
2312 gtt_offset_rotated +=
2313 setup_fb_rotation(i, &plane_info,
2315 x, y, width, height,
2317 tile_width, tile_height,
2320 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2321 x * cpp, tile_size);
2324 /* how many tiles in total needed in the bo */
2325 max_size = max(max_size, offset + size);
2328 if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
2329 drm_dbg_kms(&dev_priv->drm,
2330 "fb too big for bo (need %llu bytes, have %zu bytes)\n",
2331 mul_u32_u32(max_size, tile_size), obj->base.size);
2339 intel_plane_remap_gtt(struct intel_plane_state *plane_state)
2341 struct drm_i915_private *dev_priv =
2342 to_i915(plane_state->uapi.plane->dev);
2343 struct drm_framebuffer *fb = plane_state->hw.fb;
2344 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2345 struct intel_rotation_info *info = &plane_state->view.rotated;
2346 unsigned int rotation = plane_state->hw.rotation;
2347 int i, num_planes = fb->format->num_planes;
2348 unsigned int tile_size = intel_tile_size(dev_priv);
2349 unsigned int src_x, src_y;
2350 unsigned int src_w, src_h;
2353 memset(&plane_state->view, 0, sizeof(plane_state->view));
2354 plane_state->view.type = drm_rotation_90_or_270(rotation) ?
2355 I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED;
2357 src_x = plane_state->uapi.src.x1 >> 16;
2358 src_y = plane_state->uapi.src.y1 >> 16;
2359 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
2360 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
2362 drm_WARN_ON(&dev_priv->drm, is_ccs_modifier(fb->modifier));
2364 /* Make src coordinates relative to the viewport */
2365 drm_rect_translate(&plane_state->uapi.src,
2366 -(src_x << 16), -(src_y << 16));
2368 /* Rotate src coordinates to match rotated GTT view */
2369 if (drm_rotation_90_or_270(rotation))
2370 drm_rect_rotate(&plane_state->uapi.src,
2371 src_w << 16, src_h << 16,
2372 DRM_MODE_ROTATE_270);
2374 for (i = 0; i < num_planes; i++) {
2375 unsigned int hsub = i ? fb->format->hsub : 1;
2376 unsigned int vsub = i ? fb->format->vsub : 1;
2377 unsigned int cpp = fb->format->cpp[i];
2378 unsigned int tile_width, tile_height;
2379 unsigned int width, height;
2380 unsigned int pitch_tiles;
2384 intel_tile_dims(fb, i, &tile_width, &tile_height);
2388 width = src_w / hsub;
2389 height = src_h / vsub;
2392 * First pixel of the src viewport from the
2393 * start of the normal gtt mapping.
2395 x += intel_fb->normal[i].x;
2396 y += intel_fb->normal[i].y;
2398 offset = intel_compute_aligned_offset(dev_priv, &x, &y,
2399 fb, i, fb->pitches[i],
2400 DRM_MODE_ROTATE_0, tile_size);
2401 offset /= tile_size;
2403 drm_WARN_ON(&dev_priv->drm, i >= ARRAY_SIZE(info->plane));
2404 info->plane[i].offset = offset;
2405 info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],
2407 info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2408 info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2410 if (drm_rotation_90_or_270(rotation)) {
2413 /* rotate the x/y offsets to match the GTT view */
2414 drm_rect_init(&r, x, y, width, height);
2416 info->plane[i].width * tile_width,
2417 info->plane[i].height * tile_height,
2418 DRM_MODE_ROTATE_270);
2422 pitch_tiles = info->plane[i].height;
2423 plane_state->color_plane[i].stride = pitch_tiles * tile_height;
2425 /* rotate the tile dimensions to match the GTT view */
2426 swap(tile_width, tile_height);
2428 pitch_tiles = info->plane[i].width;
2429 plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp;
2433 * We only keep the x/y offsets, so push all of the
2434 * gtt offset into the x/y offsets.
2436 intel_adjust_tile_offset(&x, &y,
2437 tile_width, tile_height,
2438 tile_size, pitch_tiles,
2439 gtt_offset * tile_size, 0);
2441 gtt_offset += info->plane[i].width * info->plane[i].height;
2443 plane_state->color_plane[i].offset = 0;
2444 plane_state->color_plane[i].x = x;
2445 plane_state->color_plane[i].y = y;
2450 intel_plane_compute_gtt(struct intel_plane_state *plane_state)
2452 const struct intel_framebuffer *fb =
2453 to_intel_framebuffer(plane_state->hw.fb);
2454 unsigned int rotation = plane_state->hw.rotation;
2460 num_planes = fb->base.format->num_planes;
2462 if (intel_plane_needs_remap(plane_state)) {
2463 intel_plane_remap_gtt(plane_state);
2466 * Sometimes even remapping can't overcome
2467 * the stride limitations :( Can happen with
2468 * big plane sizes and suitably misaligned
2471 return intel_plane_check_stride(plane_state);
2474 intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation);
2476 for (i = 0; i < num_planes; i++) {
2477 plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation);
2478 plane_state->color_plane[i].offset = 0;
2480 if (drm_rotation_90_or_270(rotation)) {
2481 plane_state->color_plane[i].x = fb->rotated[i].x;
2482 plane_state->color_plane[i].y = fb->rotated[i].y;
2484 plane_state->color_plane[i].x = fb->normal[i].x;
2485 plane_state->color_plane[i].y = fb->normal[i].y;
2489 /* Rotate src coordinates to match rotated GTT view */
2490 if (drm_rotation_90_or_270(rotation))
2491 drm_rect_rotate(&plane_state->uapi.src,
2492 fb->base.width << 16, fb->base.height << 16,
2493 DRM_MODE_ROTATE_270);
2495 return intel_plane_check_stride(plane_state);
2498 static int i9xx_format_to_fourcc(int format)
2501 case DISPPLANE_8BPP:
2502 return DRM_FORMAT_C8;
2503 case DISPPLANE_BGRA555:
2504 return DRM_FORMAT_ARGB1555;
2505 case DISPPLANE_BGRX555:
2506 return DRM_FORMAT_XRGB1555;
2507 case DISPPLANE_BGRX565:
2508 return DRM_FORMAT_RGB565;
2510 case DISPPLANE_BGRX888:
2511 return DRM_FORMAT_XRGB8888;
2512 case DISPPLANE_RGBX888:
2513 return DRM_FORMAT_XBGR8888;
2514 case DISPPLANE_BGRA888:
2515 return DRM_FORMAT_ARGB8888;
2516 case DISPPLANE_RGBA888:
2517 return DRM_FORMAT_ABGR8888;
2518 case DISPPLANE_BGRX101010:
2519 return DRM_FORMAT_XRGB2101010;
2520 case DISPPLANE_RGBX101010:
2521 return DRM_FORMAT_XBGR2101010;
2522 case DISPPLANE_BGRA101010:
2523 return DRM_FORMAT_ARGB2101010;
2524 case DISPPLANE_RGBA101010:
2525 return DRM_FORMAT_ABGR2101010;
2526 case DISPPLANE_RGBX161616:
2527 return DRM_FORMAT_XBGR16161616F;
2531 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2534 case PLANE_CTL_FORMAT_RGB_565:
2535 return DRM_FORMAT_RGB565;
2536 case PLANE_CTL_FORMAT_NV12:
2537 return DRM_FORMAT_NV12;
2538 case PLANE_CTL_FORMAT_XYUV:
2539 return DRM_FORMAT_XYUV8888;
2540 case PLANE_CTL_FORMAT_P010:
2541 return DRM_FORMAT_P010;
2542 case PLANE_CTL_FORMAT_P012:
2543 return DRM_FORMAT_P012;
2544 case PLANE_CTL_FORMAT_P016:
2545 return DRM_FORMAT_P016;
2546 case PLANE_CTL_FORMAT_Y210:
2547 return DRM_FORMAT_Y210;
2548 case PLANE_CTL_FORMAT_Y212:
2549 return DRM_FORMAT_Y212;
2550 case PLANE_CTL_FORMAT_Y216:
2551 return DRM_FORMAT_Y216;
2552 case PLANE_CTL_FORMAT_Y410:
2553 return DRM_FORMAT_XVYU2101010;
2554 case PLANE_CTL_FORMAT_Y412:
2555 return DRM_FORMAT_XVYU12_16161616;
2556 case PLANE_CTL_FORMAT_Y416:
2557 return DRM_FORMAT_XVYU16161616;
2559 case PLANE_CTL_FORMAT_XRGB_8888:
2562 return DRM_FORMAT_ABGR8888;
2564 return DRM_FORMAT_XBGR8888;
2567 return DRM_FORMAT_ARGB8888;
2569 return DRM_FORMAT_XRGB8888;
2571 case PLANE_CTL_FORMAT_XRGB_2101010:
2574 return DRM_FORMAT_ABGR2101010;
2576 return DRM_FORMAT_XBGR2101010;
2579 return DRM_FORMAT_ARGB2101010;
2581 return DRM_FORMAT_XRGB2101010;
2583 case PLANE_CTL_FORMAT_XRGB_16161616F:
2586 return DRM_FORMAT_ABGR16161616F;
2588 return DRM_FORMAT_XBGR16161616F;
2591 return DRM_FORMAT_ARGB16161616F;
2593 return DRM_FORMAT_XRGB16161616F;
2598 static struct i915_vma *
2599 initial_plane_vma(struct drm_i915_private *i915,
2600 struct intel_initial_plane_config *plane_config)
2602 struct drm_i915_gem_object *obj;
2603 struct i915_vma *vma;
2606 if (plane_config->size == 0)
2609 base = round_down(plane_config->base,
2610 I915_GTT_MIN_ALIGNMENT);
2611 size = round_up(plane_config->base + plane_config->size,
2612 I915_GTT_MIN_ALIGNMENT);
2616 * If the FB is too big, just don't use it since fbdev is not very
2617 * important and we should probably use that space with FBC or other
2620 if (size * 2 > i915->stolen_usable_size)
2623 obj = i915_gem_object_create_stolen_for_preallocated(i915, base, size);
2628 * Mark it WT ahead of time to avoid changing the
2629 * cache_level during fbdev initialization. The
2630 * unbind there would get stuck waiting for rcu.
2632 i915_gem_object_set_cache_coherency(obj, HAS_WT(i915) ?
2633 I915_CACHE_WT : I915_CACHE_NONE);
2635 switch (plane_config->tiling) {
2636 case I915_TILING_NONE:
2640 obj->tiling_and_stride =
2641 plane_config->fb->base.pitches[0] |
2642 plane_config->tiling;
2645 MISSING_CASE(plane_config->tiling);
2649 vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
2653 if (i915_ggtt_pin(vma, NULL, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base))
2656 if (i915_gem_object_is_tiled(obj) &&
2657 !i915_vma_is_map_and_fenceable(vma))
2663 i915_gem_object_put(obj);
2668 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2669 struct intel_initial_plane_config *plane_config)
2671 struct drm_device *dev = crtc->base.dev;
2672 struct drm_i915_private *dev_priv = to_i915(dev);
2673 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2674 struct drm_framebuffer *fb = &plane_config->fb->base;
2675 struct i915_vma *vma;
2677 switch (fb->modifier) {
2678 case DRM_FORMAT_MOD_LINEAR:
2679 case I915_FORMAT_MOD_X_TILED:
2680 case I915_FORMAT_MOD_Y_TILED:
2683 drm_dbg(&dev_priv->drm,
2684 "Unsupported modifier for initial FB: 0x%llx\n",
2689 vma = initial_plane_vma(dev_priv, plane_config);
2693 mode_cmd.pixel_format = fb->format->format;
2694 mode_cmd.width = fb->width;
2695 mode_cmd.height = fb->height;
2696 mode_cmd.pitches[0] = fb->pitches[0];
2697 mode_cmd.modifier[0] = fb->modifier;
2698 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2700 if (intel_framebuffer_init(to_intel_framebuffer(fb),
2701 vma->obj, &mode_cmd)) {
2702 drm_dbg_kms(&dev_priv->drm, "intel fb init failed\n");
2706 plane_config->vma = vma;
2715 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2716 struct intel_plane_state *plane_state,
2719 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2721 plane_state->uapi.visible = visible;
2724 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
2726 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
2729 static void fixup_plane_bitmasks(struct intel_crtc_state *crtc_state)
2731 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2732 struct drm_plane *plane;
2735 * Active_planes aliases if multiple "primary" or cursor planes
2736 * have been used on the same (or wrong) pipe. plane_mask uses
2737 * unique ids, hence we can use that to reconstruct active_planes.
2739 crtc_state->enabled_planes = 0;
2740 crtc_state->active_planes = 0;
2742 drm_for_each_plane_mask(plane, &dev_priv->drm,
2743 crtc_state->uapi.plane_mask) {
2744 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);
2745 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
2749 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
2750 struct intel_plane *plane)
2752 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2753 struct intel_crtc_state *crtc_state =
2754 to_intel_crtc_state(crtc->base.state);
2755 struct intel_plane_state *plane_state =
2756 to_intel_plane_state(plane->base.state);
2758 drm_dbg_kms(&dev_priv->drm,
2759 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
2760 plane->base.base.id, plane->base.name,
2761 crtc->base.base.id, crtc->base.name);
2763 intel_set_plane_visible(crtc_state, plane_state, false);
2764 fixup_plane_bitmasks(crtc_state);
2765 crtc_state->data_rate[plane->id] = 0;
2766 crtc_state->min_cdclk[plane->id] = 0;
2768 if (plane->id == PLANE_PRIMARY)
2769 hsw_disable_ips(crtc_state);
2772 * Vblank time updates from the shadow to live plane control register
2773 * are blocked if the memory self-refresh mode is active at that
2774 * moment. So to make sure the plane gets truly disabled, disable
2775 * first the self-refresh mode. The self-refresh enable bit in turn
2776 * will be checked/applied by the HW only at the next frame start
2777 * event which is after the vblank start event, so we need to have a
2778 * wait-for-vblank between disabling the plane and the pipe.
2780 if (HAS_GMCH(dev_priv) &&
2781 intel_set_memory_cxsr(dev_priv, false))
2782 intel_wait_for_vblank(dev_priv, crtc->pipe);
2785 * Gen2 reports pipe underruns whenever all planes are disabled.
2786 * So disable underrun reporting before all the planes get disabled.
2788 if (IS_GEN(dev_priv, 2) && !crtc_state->active_planes)
2789 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
2791 intel_disable_plane(plane, crtc_state);
2795 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2796 struct intel_initial_plane_config *plane_config)
2798 struct drm_device *dev = intel_crtc->base.dev;
2799 struct drm_i915_private *dev_priv = to_i915(dev);
2801 struct drm_plane *primary = intel_crtc->base.primary;
2802 struct drm_plane_state *plane_state = primary->state;
2803 struct intel_plane *intel_plane = to_intel_plane(primary);
2804 struct intel_plane_state *intel_state =
2805 to_intel_plane_state(plane_state);
2806 struct intel_crtc_state *crtc_state =
2807 to_intel_crtc_state(intel_crtc->base.state);
2808 struct drm_framebuffer *fb;
2809 struct i915_vma *vma;
2811 if (!plane_config->fb)
2814 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2815 fb = &plane_config->fb->base;
2816 vma = plane_config->vma;
2821 * Failed to alloc the obj, check to see if we should share
2822 * an fb with another CRTC instead
2824 for_each_crtc(dev, c) {
2825 struct intel_plane_state *state;
2827 if (c == &intel_crtc->base)
2830 if (!to_intel_crtc_state(c->state)->uapi.active)
2833 state = to_intel_plane_state(c->primary->state);
2837 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2845 * We've failed to reconstruct the BIOS FB. Current display state
2846 * indicates that the primary plane is visible, but has a NULL FB,
2847 * which will lead to problems later if we don't fix it up. The
2848 * simplest solution is to just disable the primary plane now and
2849 * pretend the BIOS never had it enabled.
2851 intel_plane_disable_noatomic(intel_crtc, intel_plane);
2852 if (crtc_state->bigjoiner) {
2853 struct intel_crtc *slave =
2854 crtc_state->bigjoiner_linked_crtc;
2855 intel_plane_disable_noatomic(slave, to_intel_plane(slave->base.primary));
2861 intel_state->hw.rotation = plane_config->rotation;
2862 intel_fill_fb_ggtt_view(&intel_state->view, fb,
2863 intel_state->hw.rotation);
2864 intel_state->color_plane[0].stride =
2865 intel_fb_pitch(fb, 0, intel_state->hw.rotation);
2867 __i915_vma_pin(vma);
2868 intel_state->vma = i915_vma_get(vma);
2869 if (intel_plane_uses_fence(intel_state) && i915_vma_pin_fence(vma) == 0)
2871 intel_state->flags |= PLANE_HAS_FENCE;
2873 plane_state->src_x = 0;
2874 plane_state->src_y = 0;
2875 plane_state->src_w = fb->width << 16;
2876 plane_state->src_h = fb->height << 16;
2878 plane_state->crtc_x = 0;
2879 plane_state->crtc_y = 0;
2880 plane_state->crtc_w = fb->width;
2881 plane_state->crtc_h = fb->height;
2883 intel_state->uapi.src = drm_plane_state_src(plane_state);
2884 intel_state->uapi.dst = drm_plane_state_dest(plane_state);
2886 if (plane_config->tiling)
2887 dev_priv->preserve_bios_swizzle = true;
2889 plane_state->fb = fb;
2890 drm_framebuffer_get(fb);
2892 plane_state->crtc = &intel_crtc->base;
2893 intel_plane_copy_uapi_to_hw_state(intel_state, intel_state,
2896 intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
2898 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2899 &to_intel_frontbuffer(fb)->bits);
2904 skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
2905 int main_x, int main_y, u32 main_offset,
2908 const struct drm_framebuffer *fb = plane_state->hw.fb;
2909 int aux_x = plane_state->color_plane[ccs_plane].x;
2910 int aux_y = plane_state->color_plane[ccs_plane].y;
2911 u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
2912 u32 alignment = intel_surf_alignment(fb, ccs_plane);
2916 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
2917 while (aux_offset >= main_offset && aux_y <= main_y) {
2920 if (aux_x == main_x && aux_y == main_y)
2923 if (aux_offset == 0)
2928 aux_offset = intel_plane_adjust_aligned_offset(&x, &y,
2934 aux_x = x * hsub + aux_x % hsub;
2935 aux_y = y * vsub + aux_y % vsub;
2938 if (aux_x != main_x || aux_y != main_y)
2941 plane_state->color_plane[ccs_plane].offset = aux_offset;
2942 plane_state->color_plane[ccs_plane].x = aux_x;
2943 plane_state->color_plane[ccs_plane].y = aux_y;
2949 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
2953 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
2954 plane_state->color_plane[0].offset, 0);
2959 static int intel_plane_min_width(struct intel_plane *plane,
2960 const struct drm_framebuffer *fb,
2962 unsigned int rotation)
2964 if (plane->min_width)
2965 return plane->min_width(fb, color_plane, rotation);
2970 static int intel_plane_max_width(struct intel_plane *plane,
2971 const struct drm_framebuffer *fb,
2973 unsigned int rotation)
2975 if (plane->max_width)
2976 return plane->max_width(fb, color_plane, rotation);
2981 static int intel_plane_max_height(struct intel_plane *plane,
2982 const struct drm_framebuffer *fb,
2984 unsigned int rotation)
2986 if (plane->max_height)
2987 return plane->max_height(fb, color_plane, rotation);
2992 int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state,
2993 int *x, int *y, u32 *offset)
2995 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2996 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2997 const struct drm_framebuffer *fb = plane_state->hw.fb;
2998 const int aux_plane = intel_main_to_aux_plane(fb, 0);
2999 const u32 aux_offset = plane_state->color_plane[aux_plane].offset;
3000 const u32 alignment = intel_surf_alignment(fb, 0);
3001 const int w = drm_rect_width(&plane_state->uapi.src) >> 16;
3003 intel_add_fb_offsets(x, y, plane_state, 0);
3004 *offset = intel_plane_compute_aligned_offset(x, y, plane_state, 0);
3005 if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment)))
3009 * AUX surface offset is specified as the distance from the
3010 * main surface offset, and it must be non-negative. Make
3011 * sure that is what we will get.
3013 if (aux_plane && *offset > aux_offset)
3014 *offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0,
3016 aux_offset & ~(alignment - 1));
3019 * When using an X-tiled surface, the plane blows up
3020 * if the x offset + width exceed the stride.
3022 * TODO: linear and Y-tiled seem fine, Yf untested,
3024 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3025 int cpp = fb->format->cpp[0];
3027 while ((*x + w) * cpp > plane_state->color_plane[0].stride) {
3029 drm_dbg_kms(&dev_priv->drm,
3030 "Unable to find suitable display surface offset due to X-tiling\n");
3034 *offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0,
3036 *offset - alignment);
3043 static int skl_check_main_surface(struct intel_plane_state *plane_state)
3045 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
3046 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3047 const struct drm_framebuffer *fb = plane_state->hw.fb;
3048 const unsigned int rotation = plane_state->hw.rotation;
3049 int x = plane_state->uapi.src.x1 >> 16;
3050 int y = plane_state->uapi.src.y1 >> 16;
3051 const int w = drm_rect_width(&plane_state->uapi.src) >> 16;
3052 const int h = drm_rect_height(&plane_state->uapi.src) >> 16;
3053 const int min_width = intel_plane_min_width(plane, fb, 0, rotation);
3054 const int max_width = intel_plane_max_width(plane, fb, 0, rotation);
3055 const int max_height = intel_plane_max_height(plane, fb, 0, rotation);
3056 const int aux_plane = intel_main_to_aux_plane(fb, 0);
3057 const u32 alignment = intel_surf_alignment(fb, 0);
3061 if (w > max_width || w < min_width || h > max_height) {
3062 drm_dbg_kms(&dev_priv->drm,
3063 "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n",
3064 w, h, min_width, max_width, max_height);
3068 ret = skl_calc_main_surface_offset(plane_state, &x, &y, &offset);
3073 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3074 * they match with the main surface x/y offsets.
3076 if (is_ccs_modifier(fb->modifier)) {
3077 while (!skl_check_main_ccs_coordinates(plane_state, x, y,
3078 offset, aux_plane)) {
3082 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3083 offset, offset - alignment);
3086 if (x != plane_state->color_plane[aux_plane].x ||
3087 y != plane_state->color_plane[aux_plane].y) {
3088 drm_dbg_kms(&dev_priv->drm,
3089 "Unable to find suitable display surface offset due to CCS\n");
3094 drm_WARN_ON(&dev_priv->drm, x > 8191 || y > 8191);
3096 plane_state->color_plane[0].offset = offset;
3097 plane_state->color_plane[0].x = x;
3098 plane_state->color_plane[0].y = y;
3101 * Put the final coordinates back so that the src
3102 * coordinate checks will see the right values.
3104 drm_rect_translate_to(&plane_state->uapi.src,
3110 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3112 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
3113 struct drm_i915_private *i915 = to_i915(plane->base.dev);
3114 const struct drm_framebuffer *fb = plane_state->hw.fb;
3115 unsigned int rotation = plane_state->hw.rotation;
3117 int max_width = intel_plane_max_width(plane, fb, uv_plane, rotation);
3118 int max_height = intel_plane_max_height(plane, fb, uv_plane, rotation);
3119 int x = plane_state->uapi.src.x1 >> 17;
3120 int y = plane_state->uapi.src.y1 >> 17;
3121 int w = drm_rect_width(&plane_state->uapi.src) >> 17;
3122 int h = drm_rect_height(&plane_state->uapi.src) >> 17;
3125 /* FIXME not quite sure how/if these apply to the chroma plane */
3126 if (w > max_width || h > max_height) {
3127 drm_dbg_kms(&i915->drm,
3128 "CbCr source size %dx%d too big (limit %dx%d)\n",
3129 w, h, max_width, max_height);
3133 intel_add_fb_offsets(&x, &y, plane_state, uv_plane);
3134 offset = intel_plane_compute_aligned_offset(&x, &y,
3135 plane_state, uv_plane);
3137 if (is_ccs_modifier(fb->modifier)) {
3138 int ccs_plane = main_to_ccs_plane(fb, uv_plane);
3139 u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
3140 u32 alignment = intel_surf_alignment(fb, uv_plane);
3142 if (offset > aux_offset)
3143 offset = intel_plane_adjust_aligned_offset(&x, &y,
3147 aux_offset & ~(alignment - 1));
3149 while (!skl_check_main_ccs_coordinates(plane_state, x, y,
3150 offset, ccs_plane)) {
3154 offset = intel_plane_adjust_aligned_offset(&x, &y,
3157 offset, offset - alignment);
3160 if (x != plane_state->color_plane[ccs_plane].x ||
3161 y != plane_state->color_plane[ccs_plane].y) {
3162 drm_dbg_kms(&i915->drm,
3163 "Unable to find suitable display surface offset due to CCS\n");
3168 drm_WARN_ON(&i915->drm, x > 8191 || y > 8191);
3170 plane_state->color_plane[uv_plane].offset = offset;
3171 plane_state->color_plane[uv_plane].x = x;
3172 plane_state->color_plane[uv_plane].y = y;
3177 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3179 const struct drm_framebuffer *fb = plane_state->hw.fb;
3180 int src_x = plane_state->uapi.src.x1 >> 16;
3181 int src_y = plane_state->uapi.src.y1 >> 16;
3185 for (ccs_plane = 0; ccs_plane < fb->format->num_planes; ccs_plane++) {
3186 int main_hsub, main_vsub;
3190 if (!is_ccs_plane(fb, ccs_plane) ||
3191 is_gen12_ccs_cc_plane(fb, ccs_plane))
3194 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb,
3195 ccs_to_main_plane(fb, ccs_plane));
3196 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
3203 intel_add_fb_offsets(&x, &y, plane_state, ccs_plane);
3205 offset = intel_plane_compute_aligned_offset(&x, &y,
3209 plane_state->color_plane[ccs_plane].offset = offset;
3210 plane_state->color_plane[ccs_plane].x = (x * hsub +
3213 plane_state->color_plane[ccs_plane].y = (y * vsub +
3221 int skl_check_plane_surface(struct intel_plane_state *plane_state)
3223 const struct drm_framebuffer *fb = plane_state->hw.fb;
3226 ret = intel_plane_compute_gtt(plane_state);
3230 if (!plane_state->uapi.visible)
3234 * Handle the AUX surface first since the main surface setup depends on
3237 if (is_ccs_modifier(fb->modifier)) {
3238 ret = skl_check_ccs_aux_surface(plane_state);
3243 if (intel_format_info_is_yuv_semiplanar(fb->format,
3245 ret = skl_check_nv12_aux_surface(plane_state);
3250 for (i = fb->format->num_planes; i < ARRAY_SIZE(plane_state->color_plane); i++) {
3251 plane_state->color_plane[i].offset = 0;
3252 plane_state->color_plane[i].x = 0;
3253 plane_state->color_plane[i].y = 0;
3256 ret = skl_check_main_surface(plane_state);
3263 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3265 struct drm_device *dev = intel_crtc->base.dev;
3266 struct drm_i915_private *dev_priv = to_i915(dev);
3267 unsigned long irqflags;
3269 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3271 intel_de_write_fw(dev_priv, SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3272 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3273 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3275 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3279 * This function detaches (aka. unbinds) unused scalers in hardware
3281 static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
3283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
3284 const struct intel_crtc_scaler_state *scaler_state =
3285 &crtc_state->scaler_state;
3288 /* loop through and disable scalers that aren't in use */
3289 for (i = 0; i < intel_crtc->num_scalers; i++) {
3290 if (!scaler_state->scalers[i].in_use)
3291 skl_detach_scaler(intel_crtc, i);
3295 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
3296 int color_plane, unsigned int rotation)
3299 * The stride is either expressed as a multiple of 64 bytes chunks for
3300 * linear buffers or in number of tiles for tiled buffers.
3302 if (is_surface_linear(fb, color_plane))
3304 else if (drm_rotation_90_or_270(rotation))
3305 return intel_tile_height(fb, color_plane);
3307 return intel_tile_width_bytes(fb, color_plane);
3310 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
3313 const struct drm_framebuffer *fb = plane_state->hw.fb;
3314 unsigned int rotation = plane_state->hw.rotation;
3315 u32 stride = plane_state->color_plane[color_plane].stride;
3317 if (color_plane >= fb->format->num_planes)
3320 return stride / skl_plane_stride_mult(fb, color_plane, rotation);
3323 static u32 skl_plane_ctl_format(u32 pixel_format)
3325 switch (pixel_format) {
3327 return PLANE_CTL_FORMAT_INDEXED;
3328 case DRM_FORMAT_RGB565:
3329 return PLANE_CTL_FORMAT_RGB_565;
3330 case DRM_FORMAT_XBGR8888:
3331 case DRM_FORMAT_ABGR8888:
3332 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3333 case DRM_FORMAT_XRGB8888:
3334 case DRM_FORMAT_ARGB8888:
3335 return PLANE_CTL_FORMAT_XRGB_8888;
3336 case DRM_FORMAT_XBGR2101010:
3337 case DRM_FORMAT_ABGR2101010:
3338 return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX;
3339 case DRM_FORMAT_XRGB2101010:
3340 case DRM_FORMAT_ARGB2101010:
3341 return PLANE_CTL_FORMAT_XRGB_2101010;
3342 case DRM_FORMAT_XBGR16161616F:
3343 case DRM_FORMAT_ABGR16161616F:
3344 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
3345 case DRM_FORMAT_XRGB16161616F:
3346 case DRM_FORMAT_ARGB16161616F:
3347 return PLANE_CTL_FORMAT_XRGB_16161616F;
3348 case DRM_FORMAT_XYUV8888:
3349 return PLANE_CTL_FORMAT_XYUV;
3350 case DRM_FORMAT_YUYV:
3351 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3352 case DRM_FORMAT_YVYU:
3353 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3354 case DRM_FORMAT_UYVY:
3355 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3356 case DRM_FORMAT_VYUY:
3357 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3358 case DRM_FORMAT_NV12:
3359 return PLANE_CTL_FORMAT_NV12;
3360 case DRM_FORMAT_P010:
3361 return PLANE_CTL_FORMAT_P010;
3362 case DRM_FORMAT_P012:
3363 return PLANE_CTL_FORMAT_P012;
3364 case DRM_FORMAT_P016:
3365 return PLANE_CTL_FORMAT_P016;
3366 case DRM_FORMAT_Y210:
3367 return PLANE_CTL_FORMAT_Y210;
3368 case DRM_FORMAT_Y212:
3369 return PLANE_CTL_FORMAT_Y212;
3370 case DRM_FORMAT_Y216:
3371 return PLANE_CTL_FORMAT_Y216;
3372 case DRM_FORMAT_XVYU2101010:
3373 return PLANE_CTL_FORMAT_Y410;
3374 case DRM_FORMAT_XVYU12_16161616:
3375 return PLANE_CTL_FORMAT_Y412;
3376 case DRM_FORMAT_XVYU16161616:
3377 return PLANE_CTL_FORMAT_Y416;
3379 MISSING_CASE(pixel_format);
3385 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
3387 if (!plane_state->hw.fb->format->has_alpha)
3388 return PLANE_CTL_ALPHA_DISABLE;
3390 switch (plane_state->hw.pixel_blend_mode) {
3391 case DRM_MODE_BLEND_PIXEL_NONE:
3392 return PLANE_CTL_ALPHA_DISABLE;
3393 case DRM_MODE_BLEND_PREMULTI:
3394 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3395 case DRM_MODE_BLEND_COVERAGE:
3396 return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
3398 MISSING_CASE(plane_state->hw.pixel_blend_mode);
3399 return PLANE_CTL_ALPHA_DISABLE;
3403 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
3405 if (!plane_state->hw.fb->format->has_alpha)
3406 return PLANE_COLOR_ALPHA_DISABLE;
3408 switch (plane_state->hw.pixel_blend_mode) {
3409 case DRM_MODE_BLEND_PIXEL_NONE:
3410 return PLANE_COLOR_ALPHA_DISABLE;
3411 case DRM_MODE_BLEND_PREMULTI:
3412 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
3413 case DRM_MODE_BLEND_COVERAGE:
3414 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
3416 MISSING_CASE(plane_state->hw.pixel_blend_mode);
3417 return PLANE_COLOR_ALPHA_DISABLE;
3421 static u32 skl_plane_ctl_tiling(u64 fb_modifier)
3423 switch (fb_modifier) {
3424 case DRM_FORMAT_MOD_LINEAR:
3426 case I915_FORMAT_MOD_X_TILED:
3427 return PLANE_CTL_TILED_X;
3428 case I915_FORMAT_MOD_Y_TILED:
3429 return PLANE_CTL_TILED_Y;
3430 case I915_FORMAT_MOD_Y_TILED_CCS:
3431 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
3432 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
3433 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
3434 return PLANE_CTL_TILED_Y |
3435 PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
3436 PLANE_CTL_CLEAR_COLOR_DISABLE;
3437 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
3438 return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
3439 case I915_FORMAT_MOD_Yf_TILED:
3440 return PLANE_CTL_TILED_YF;
3441 case I915_FORMAT_MOD_Yf_TILED_CCS:
3442 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
3444 MISSING_CASE(fb_modifier);
3450 static u32 skl_plane_ctl_rotate(unsigned int rotate)
3453 case DRM_MODE_ROTATE_0:
3456 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3457 * while i915 HW rotation is clockwise, thats why this swapping.
3459 case DRM_MODE_ROTATE_90:
3460 return PLANE_CTL_ROTATE_270;
3461 case DRM_MODE_ROTATE_180:
3462 return PLANE_CTL_ROTATE_180;
3463 case DRM_MODE_ROTATE_270:
3464 return PLANE_CTL_ROTATE_90;
3466 MISSING_CASE(rotate);
3472 static u32 cnl_plane_ctl_flip(unsigned int reflect)
3477 case DRM_MODE_REFLECT_X:
3478 return PLANE_CTL_FLIP_HORIZONTAL;
3479 case DRM_MODE_REFLECT_Y:
3481 MISSING_CASE(reflect);
3487 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
3489 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3492 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
3495 if (crtc_state->gamma_enable)
3496 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
3498 if (crtc_state->csc_enable)
3499 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
3504 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3505 const struct intel_plane_state *plane_state)
3507 struct drm_i915_private *dev_priv =
3508 to_i915(plane_state->uapi.plane->dev);
3509 const struct drm_framebuffer *fb = plane_state->hw.fb;
3510 unsigned int rotation = plane_state->hw.rotation;
3511 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3514 plane_ctl = PLANE_CTL_ENABLE;
3516 if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
3517 plane_ctl |= skl_plane_ctl_alpha(plane_state);
3518 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3520 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
3521 plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
3523 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
3524 plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
3527 plane_ctl |= skl_plane_ctl_format(fb->format->format);
3528 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3529 plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
3531 if (INTEL_GEN(dev_priv) >= 10)
3532 plane_ctl |= cnl_plane_ctl_flip(rotation &
3533 DRM_MODE_REFLECT_MASK);
3535 if (key->flags & I915_SET_COLORKEY_DESTINATION)
3536 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3537 else if (key->flags & I915_SET_COLORKEY_SOURCE)
3538 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3543 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
3545 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3546 u32 plane_color_ctl = 0;
3548 if (INTEL_GEN(dev_priv) >= 11)
3549 return plane_color_ctl;
3551 if (crtc_state->gamma_enable)
3552 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
3554 if (crtc_state->csc_enable)
3555 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
3557 return plane_color_ctl;
3560 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
3561 const struct intel_plane_state *plane_state)
3563 struct drm_i915_private *dev_priv =
3564 to_i915(plane_state->uapi.plane->dev);
3565 const struct drm_framebuffer *fb = plane_state->hw.fb;
3566 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
3567 u32 plane_color_ctl = 0;
3569 plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
3570 plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
3572 if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
3573 switch (plane_state->hw.color_encoding) {
3574 case DRM_COLOR_YCBCR_BT709:
3575 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
3577 case DRM_COLOR_YCBCR_BT2020:
3579 PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020;
3583 PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601;
3585 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
3586 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
3587 } else if (fb->format->is_yuv) {
3588 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
3589 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
3590 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
3593 return plane_color_ctl;
3597 __intel_display_resume(struct drm_device *dev,
3598 struct drm_atomic_state *state,
3599 struct drm_modeset_acquire_ctx *ctx)
3601 struct drm_crtc_state *crtc_state;
3602 struct drm_crtc *crtc;
3605 intel_modeset_setup_hw_state(dev, ctx);
3606 intel_vga_redisable(to_i915(dev));
3612 * We've duplicated the state, pointers to the old state are invalid.
3614 * Don't attempt to use the old state until we commit the duplicated state.
3616 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3618 * Force recalculation even if we restore
3619 * current state. With fast modeset this may not result
3620 * in a modeset when the state is compatible.
3622 crtc_state->mode_changed = true;
3625 /* ignore any reset values/BIOS leftovers in the WM registers */
3626 if (!HAS_GMCH(to_i915(dev)))
3627 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3629 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3631 drm_WARN_ON(dev, ret == -EDEADLK);
3635 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3637 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
3638 intel_has_gpu_reset(&dev_priv->gt));
3641 void intel_display_prepare_reset(struct drm_i915_private *dev_priv)
3643 struct drm_device *dev = &dev_priv->drm;
3644 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3645 struct drm_atomic_state *state;
3648 if (!HAS_DISPLAY(dev_priv))
3651 /* reset doesn't touch the display */
3652 if (!dev_priv->params.force_reset_modeset_test &&
3653 !gpu_reset_clobbers_display(dev_priv))
3656 /* We have a modeset vs reset deadlock, defensively unbreak it. */
3657 set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
3658 smp_mb__after_atomic();
3659 wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET);
3661 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
3662 drm_dbg_kms(&dev_priv->drm,
3663 "Modeset potentially stuck, unbreaking through wedging\n");
3664 intel_gt_set_wedged(&dev_priv->gt);
3668 * Need mode_config.mutex so that we don't
3669 * trample ongoing ->detect() and whatnot.
3671 mutex_lock(&dev->mode_config.mutex);
3672 drm_modeset_acquire_init(ctx, 0);
3674 ret = drm_modeset_lock_all_ctx(dev, ctx);
3675 if (ret != -EDEADLK)
3678 drm_modeset_backoff(ctx);
3681 * Disabling the crtcs gracefully seems nicer. Also the
3682 * g33 docs say we should at least disable all the planes.
3684 state = drm_atomic_helper_duplicate_state(dev, ctx);
3685 if (IS_ERR(state)) {
3686 ret = PTR_ERR(state);
3687 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n",
3692 ret = drm_atomic_helper_disable_all(dev, ctx);
3694 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
3696 drm_atomic_state_put(state);
3700 dev_priv->modeset_restore_state = state;
3701 state->acquire_ctx = ctx;
3704 void intel_display_finish_reset(struct drm_i915_private *dev_priv)
3706 struct drm_device *dev = &dev_priv->drm;
3707 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3708 struct drm_atomic_state *state;
3711 if (!HAS_DISPLAY(dev_priv))
3714 /* reset doesn't touch the display */
3715 if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
3718 state = fetch_and_zero(&dev_priv->modeset_restore_state);
3722 /* reset doesn't touch the display */
3723 if (!gpu_reset_clobbers_display(dev_priv)) {
3724 /* for testing only restore the display */
3725 ret = __intel_display_resume(dev, state, ctx);
3727 drm_err(&dev_priv->drm,
3728 "Restoring old state failed with %i\n", ret);
3731 * The display has been reset as well,
3732 * so need a full re-initialization.
3734 intel_pps_unlock_regs_wa(dev_priv);
3735 intel_modeset_init_hw(dev_priv);
3736 intel_init_clock_gating(dev_priv);
3737 intel_hpd_init(dev_priv);
3739 ret = __intel_display_resume(dev, state, ctx);
3741 drm_err(&dev_priv->drm,
3742 "Restoring old state failed with %i\n", ret);
3744 intel_hpd_poll_disable(dev_priv);
3747 drm_atomic_state_put(state);
3749 drm_modeset_drop_locks(ctx);
3750 drm_modeset_acquire_fini(ctx);
3751 mutex_unlock(&dev->mode_config.mutex);
3753 clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
3756 static void icl_set_pipe_chicken(struct intel_crtc *crtc)
3758 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3759 enum pipe pipe = crtc->pipe;
3762 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe));
3765 * Display WA #1153: icl
3766 * enable hardware to bypass the alpha math
3767 * and rounding for per-pixel values 00 and 0xff
3769 tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
3771 * Display WA # 1605353570: icl
3772 * Set the pixel rounding bit to 1 for allowing
3773 * passthrough of Frame buffer pixels unmodified
3776 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
3777 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
3780 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
3782 struct drm_crtc *crtc;
3785 drm_for_each_crtc(crtc, &dev_priv->drm) {
3786 struct drm_crtc_commit *commit;
3787 spin_lock(&crtc->commit_lock);
3788 commit = list_first_entry_or_null(&crtc->commit_list,
3789 struct drm_crtc_commit, commit_entry);
3790 cleanup_done = commit ?
3791 try_wait_for_completion(&commit->cleanup_done) : true;
3792 spin_unlock(&crtc->commit_lock);
3797 drm_crtc_wait_one_vblank(crtc);
3805 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3809 intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_GATE);
3811 mutex_lock(&dev_priv->sb_lock);
3813 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3814 temp |= SBI_SSCCTL_DISABLE;
3815 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3817 mutex_unlock(&dev_priv->sb_lock);
3820 /* Program iCLKIP clock to the desired frequency */
3821 static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
3823 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3824 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3825 int clock = crtc_state->hw.adjusted_mode.crtc_clock;
3826 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3829 lpt_disable_iclkip(dev_priv);
3831 /* The iCLK virtual clock root frequency is in MHz,
3832 * but the adjusted_mode->crtc_clock in in KHz. To get the
3833 * divisors, it is necessary to divide one by another, so we
3834 * convert the virtual clock precision to KHz here for higher
3837 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3838 u32 iclk_virtual_root_freq = 172800 * 1000;
3839 u32 iclk_pi_range = 64;
3840 u32 desired_divisor;
3842 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3844 divsel = (desired_divisor / iclk_pi_range) - 2;
3845 phaseinc = desired_divisor % iclk_pi_range;
3848 * Near 20MHz is a corner case which is
3849 * out of range for the 7-bit divisor
3855 /* This should not happen with any sane values */
3856 drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3857 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3858 drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(phasedir) &
3859 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3861 drm_dbg_kms(&dev_priv->drm,
3862 "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3863 clock, auxdiv, divsel, phasedir, phaseinc);
3865 mutex_lock(&dev_priv->sb_lock);
3867 /* Program SSCDIVINTPHASE6 */
3868 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3869 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3870 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3871 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3872 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3873 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3874 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3875 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3877 /* Program SSCAUXDIV */
3878 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3879 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3880 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3881 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3883 /* Enable modulator and associated divider */
3884 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3885 temp &= ~SBI_SSCCTL_DISABLE;
3886 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3888 mutex_unlock(&dev_priv->sb_lock);
3890 /* Wait for initialization time */
3893 intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3896 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3898 u32 divsel, phaseinc, auxdiv;
3899 u32 iclk_virtual_root_freq = 172800 * 1000;
3900 u32 iclk_pi_range = 64;
3901 u32 desired_divisor;
3904 if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3907 mutex_lock(&dev_priv->sb_lock);
3909 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3910 if (temp & SBI_SSCCTL_DISABLE) {
3911 mutex_unlock(&dev_priv->sb_lock);
3915 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3916 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
3917 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
3918 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
3919 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
3921 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3922 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
3923 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
3925 mutex_unlock(&dev_priv->sb_lock);
3927 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
3929 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3930 desired_divisor << auxdiv);
3933 static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
3934 enum pipe pch_transcoder)
3936 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3937 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3938 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3940 intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
3941 intel_de_read(dev_priv, HTOTAL(cpu_transcoder)));
3942 intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
3943 intel_de_read(dev_priv, HBLANK(cpu_transcoder)));
3944 intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
3945 intel_de_read(dev_priv, HSYNC(cpu_transcoder)));
3947 intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
3948 intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
3949 intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
3950 intel_de_read(dev_priv, VBLANK(cpu_transcoder)));
3951 intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
3952 intel_de_read(dev_priv, VSYNC(cpu_transcoder)));
3953 intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3954 intel_de_read(dev_priv, VSYNCSHIFT(cpu_transcoder)));
3957 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
3961 temp = intel_de_read(dev_priv, SOUTH_CHICKEN1);
3962 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
3965 drm_WARN_ON(&dev_priv->drm,
3966 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) &
3968 drm_WARN_ON(&dev_priv->drm,
3969 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) &
3972 temp &= ~FDI_BC_BIFURCATION_SELECT;
3974 temp |= FDI_BC_BIFURCATION_SELECT;
3976 drm_dbg_kms(&dev_priv->drm, "%sabling fdi C rx\n",
3977 enable ? "en" : "dis");
3978 intel_de_write(dev_priv, SOUTH_CHICKEN1, temp);
3979 intel_de_posting_read(dev_priv, SOUTH_CHICKEN1);
3982 static void ivb_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
3984 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3985 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3987 switch (crtc->pipe) {
3991 if (crtc_state->fdi_lanes > 2)
3992 cpt_set_fdi_bc_bifurcation(dev_priv, false);
3994 cpt_set_fdi_bc_bifurcation(dev_priv, true);
3998 cpt_set_fdi_bc_bifurcation(dev_priv, true);
4007 * Finds the encoder associated with the given CRTC. This can only be
4008 * used when we know that the CRTC isn't feeding multiple encoders!
4010 struct intel_encoder *
4011 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
4012 const struct intel_crtc_state *crtc_state)
4014 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4015 const struct drm_connector_state *connector_state;
4016 const struct drm_connector *connector;
4017 struct intel_encoder *encoder = NULL;
4018 int num_encoders = 0;
4021 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4022 if (connector_state->crtc != &crtc->base)
4025 encoder = to_intel_encoder(connector_state->best_encoder);
4029 drm_WARN(encoder->base.dev, num_encoders != 1,
4030 "%d encoders for pipe %c\n",
4031 num_encoders, pipe_name(crtc->pipe));
4037 * Enable PCH resources required for PCH ports:
4039 * - FDI training & RX/TX
4040 * - update transcoder timings
4041 * - DP transcoding bits
4044 static void ilk_pch_enable(const struct intel_atomic_state *state,
4045 const struct intel_crtc_state *crtc_state)
4047 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4048 struct drm_device *dev = crtc->base.dev;
4049 struct drm_i915_private *dev_priv = to_i915(dev);
4050 enum pipe pipe = crtc->pipe;
4053 assert_pch_transcoder_disabled(dev_priv, pipe);
4055 if (IS_IVYBRIDGE(dev_priv))
4056 ivb_update_fdi_bc_bifurcation(crtc_state);
4058 /* Write the TU size bits before fdi link training, so that error
4059 * detection works. */
4060 intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
4061 intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4063 /* For PCH output, training FDI link */
4064 dev_priv->display.fdi_link_train(crtc, crtc_state);
4066 /* We need to program the right clock selection before writing the pixel
4067 * mutliplier into the DPLL. */
4068 if (HAS_PCH_CPT(dev_priv)) {
4071 temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
4072 temp |= TRANS_DPLL_ENABLE(pipe);
4073 sel = TRANS_DPLLB_SEL(pipe);
4074 if (crtc_state->shared_dpll ==
4075 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4079 intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
4082 /* XXX: pch pll's can be enabled any time before we enable the PCH
4083 * transcoder, and we actually should do this to not upset any PCH
4084 * transcoder that already use the clock when we share it.
4086 * Note that enable_shared_dpll tries to do the right thing, but
4087 * get_shared_dpll unconditionally resets the pll - we need that to have
4088 * the right LVDS enable sequence. */
4089 intel_enable_shared_dpll(crtc_state);
4091 /* set transcoder timing, panel must allow it */
4092 assert_panel_unlocked(dev_priv, pipe);
4093 ilk_pch_transcoder_set_timings(crtc_state, pipe);
4095 intel_fdi_normal_train(crtc);
4097 /* For PCH DP, enable TRANS_DP_CTL */
4098 if (HAS_PCH_CPT(dev_priv) &&
4099 intel_crtc_has_dp_encoder(crtc_state)) {
4100 const struct drm_display_mode *adjusted_mode =
4101 &crtc_state->hw.adjusted_mode;
4102 u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4103 i915_reg_t reg = TRANS_DP_CTL(pipe);
4106 temp = intel_de_read(dev_priv, reg);
4107 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4108 TRANS_DP_SYNC_MASK |
4110 temp |= TRANS_DP_OUTPUT_ENABLE;
4111 temp |= bpc << 9; /* same format but at 11:9 */
4113 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4114 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4115 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4116 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4118 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
4119 drm_WARN_ON(dev, port < PORT_B || port > PORT_D);
4120 temp |= TRANS_DP_PORT_SEL(port);
4122 intel_de_write(dev_priv, reg, temp);
4125 ilk_enable_pch_transcoder(crtc_state);
4128 void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4130 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4131 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4132 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4134 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
4136 lpt_program_iclkip(crtc_state);
4138 /* Set transcoder timing. */
4139 ilk_pch_transcoder_set_timings(crtc_state, PIPE_A);
4141 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4144 static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
4147 i915_reg_t dslreg = PIPEDSL(pipe);
4150 temp = intel_de_read(dev_priv, dslreg);
4152 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) {
4153 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5))
4154 drm_err(&dev_priv->drm,
4155 "mode set failed: pipe %c stuck\n",
4161 * The hardware phase 0.0 refers to the center of the pixel.
4162 * We want to start from the top/left edge which is phase
4163 * -0.5. That matches how the hardware calculates the scaling
4164 * factors (from top-left of the first pixel to bottom-right
4165 * of the last pixel, as opposed to the pixel centers).
4167 * For 4:2:0 subsampled chroma planes we obviously have to
4168 * adjust that so that the chroma sample position lands in
4171 * Note that for packed YCbCr 4:2:2 formats there is no way to
4172 * control chroma siting. The hardware simply replicates the
4173 * chroma samples for both of the luma samples, and thus we don't
4174 * actually get the expected MPEG2 chroma siting convention :(
4175 * The same behaviour is observed on pre-SKL platforms as well.
4177 * Theory behind the formula (note that we ignore sub-pixel
4178 * source coordinates):
4179 * s = source sample position
4180 * d = destination sample position
4185 * | | 1.5 (initial phase)
4193 * | -0.375 (initial phase)
4200 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
4202 int phase = -0x8000;
4206 phase += (sub - 1) * 0x8000 / sub;
4208 phase += scale / (2 * sub);
4211 * Hardware initial phase limited to [-0.5:1.5].
4212 * Since the max hardware scale factor is 3.0, we
4213 * should never actually excdeed 1.0 here.
4215 WARN_ON(phase < -0x8000 || phase > 0x18000);
4218 phase = 0x10000 + phase;
4220 trip = PS_PHASE_TRIP;
4222 return ((phase >> 2) & PS_PHASE_MASK) | trip;
4225 #define SKL_MIN_SRC_W 8
4226 #define SKL_MAX_SRC_W 4096
4227 #define SKL_MIN_SRC_H 8
4228 #define SKL_MAX_SRC_H 4096
4229 #define SKL_MIN_DST_W 8
4230 #define SKL_MAX_DST_W 4096
4231 #define SKL_MIN_DST_H 8
4232 #define SKL_MAX_DST_H 4096
4233 #define ICL_MAX_SRC_W 5120
4234 #define ICL_MAX_SRC_H 4096
4235 #define ICL_MAX_DST_W 5120
4236 #define ICL_MAX_DST_H 4096
4237 #define SKL_MIN_YUV_420_SRC_W 16
4238 #define SKL_MIN_YUV_420_SRC_H 16
4241 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4242 unsigned int scaler_user, int *scaler_id,
4243 int src_w, int src_h, int dst_w, int dst_h,
4244 const struct drm_format_info *format,
4245 u64 modifier, bool need_scaler)
4247 struct intel_crtc_scaler_state *scaler_state =
4248 &crtc_state->scaler_state;
4249 struct intel_crtc *intel_crtc =
4250 to_intel_crtc(crtc_state->uapi.crtc);
4251 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4252 const struct drm_display_mode *adjusted_mode =
4253 &crtc_state->hw.adjusted_mode;
4256 * Src coordinates are already rotated by 270 degrees for
4257 * the 90/270 degree plane rotation cases (to match the
4258 * GTT mapping), hence no need to account for rotation here.
4260 if (src_w != dst_w || src_h != dst_h)
4264 * Scaling/fitting not supported in IF-ID mode in GEN9+
4265 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
4266 * Once NV12 is enabled, handle it here while allocating scaler
4269 if (INTEL_GEN(dev_priv) >= 9 && crtc_state->hw.enable &&
4270 need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4271 drm_dbg_kms(&dev_priv->drm,
4272 "Pipe/Plane scaling not supported with IF-ID mode\n");
4277 * if plane is being disabled or scaler is no more required or force detach
4278 * - free scaler binded to this plane/crtc
4279 * - in order to do this, update crtc->scaler_usage
4281 * Here scaler state in crtc_state is set free so that
4282 * scaler can be assigned to other user. Actual register
4283 * update to free the scaler is done in plane/panel-fit programming.
4284 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4286 if (force_detach || !need_scaler) {
4287 if (*scaler_id >= 0) {
4288 scaler_state->scaler_users &= ~(1 << scaler_user);
4289 scaler_state->scalers[*scaler_id].in_use = 0;
4291 drm_dbg_kms(&dev_priv->drm,
4292 "scaler_user index %u.%u: "
4293 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4294 intel_crtc->pipe, scaler_user, *scaler_id,
4295 scaler_state->scaler_users);
4301 if (format && intel_format_info_is_yuv_semiplanar(format, modifier) &&
4302 (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
4303 drm_dbg_kms(&dev_priv->drm,
4304 "Planar YUV: src dimensions not met\n");
4309 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4310 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4311 (INTEL_GEN(dev_priv) >= 11 &&
4312 (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
4313 dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
4314 (INTEL_GEN(dev_priv) < 11 &&
4315 (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4316 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
4317 drm_dbg_kms(&dev_priv->drm,
4318 "scaler_user index %u.%u: src %ux%u dst %ux%u "
4319 "size is out of scaler range\n",
4320 intel_crtc->pipe, scaler_user, src_w, src_h,
4325 /* mark this plane as a scaler user in crtc_state */
4326 scaler_state->scaler_users |= (1 << scaler_user);
4327 drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: "
4328 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4329 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4330 scaler_state->scaler_users);
4335 static int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
4337 const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
4340 if (crtc_state->pch_pfit.enabled) {
4341 width = drm_rect_width(&crtc_state->pch_pfit.dst);
4342 height = drm_rect_height(&crtc_state->pch_pfit.dst);
4344 width = pipe_mode->crtc_hdisplay;
4345 height = pipe_mode->crtc_vdisplay;
4347 return skl_update_scaler(crtc_state, !crtc_state->hw.active,
4349 &crtc_state->scaler_state.scaler_id,
4350 crtc_state->pipe_src_w, crtc_state->pipe_src_h,
4351 width, height, NULL, 0,
4352 crtc_state->pch_pfit.enabled);
4356 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4357 * @crtc_state: crtc's scaler state
4358 * @plane_state: atomic plane state to update
4361 * 0 - scaler_usage updated successfully
4362 * error - requested scaling cannot be supported or other error condition
4364 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4365 struct intel_plane_state *plane_state)
4367 struct intel_plane *intel_plane =
4368 to_intel_plane(plane_state->uapi.plane);
4369 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
4370 struct drm_framebuffer *fb = plane_state->hw.fb;
4372 bool force_detach = !fb || !plane_state->uapi.visible;
4373 bool need_scaler = false;
4375 /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
4376 if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
4377 fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
4380 ret = skl_update_scaler(crtc_state, force_detach,
4381 drm_plane_index(&intel_plane->base),
4382 &plane_state->scaler_id,
4383 drm_rect_width(&plane_state->uapi.src) >> 16,
4384 drm_rect_height(&plane_state->uapi.src) >> 16,
4385 drm_rect_width(&plane_state->uapi.dst),
4386 drm_rect_height(&plane_state->uapi.dst),
4387 fb ? fb->format : NULL,
4388 fb ? fb->modifier : 0,
4391 if (ret || plane_state->scaler_id < 0)
4394 /* check colorkey */
4395 if (plane_state->ckey.flags) {
4396 drm_dbg_kms(&dev_priv->drm,
4397 "[PLANE:%d:%s] scaling with color key not allowed",
4398 intel_plane->base.base.id,
4399 intel_plane->base.name);
4403 /* Check src format */
4404 switch (fb->format->format) {
4405 case DRM_FORMAT_RGB565:
4406 case DRM_FORMAT_XBGR8888:
4407 case DRM_FORMAT_XRGB8888:
4408 case DRM_FORMAT_ABGR8888:
4409 case DRM_FORMAT_ARGB8888:
4410 case DRM_FORMAT_XRGB2101010:
4411 case DRM_FORMAT_XBGR2101010:
4412 case DRM_FORMAT_ARGB2101010:
4413 case DRM_FORMAT_ABGR2101010:
4414 case DRM_FORMAT_YUYV:
4415 case DRM_FORMAT_YVYU:
4416 case DRM_FORMAT_UYVY:
4417 case DRM_FORMAT_VYUY:
4418 case DRM_FORMAT_NV12:
4419 case DRM_FORMAT_XYUV8888:
4420 case DRM_FORMAT_P010:
4421 case DRM_FORMAT_P012:
4422 case DRM_FORMAT_P016:
4423 case DRM_FORMAT_Y210:
4424 case DRM_FORMAT_Y212:
4425 case DRM_FORMAT_Y216:
4426 case DRM_FORMAT_XVYU2101010:
4427 case DRM_FORMAT_XVYU12_16161616:
4428 case DRM_FORMAT_XVYU16161616:
4430 case DRM_FORMAT_XBGR16161616F:
4431 case DRM_FORMAT_ABGR16161616F:
4432 case DRM_FORMAT_XRGB16161616F:
4433 case DRM_FORMAT_ARGB16161616F:
4434 if (INTEL_GEN(dev_priv) >= 11)
4438 drm_dbg_kms(&dev_priv->drm,
4439 "[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4440 intel_plane->base.base.id, intel_plane->base.name,
4441 fb->base.id, fb->format->format);
4448 void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state)
4450 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
4453 for (i = 0; i < crtc->num_scalers; i++)
4454 skl_detach_scaler(crtc, i);
4457 static int cnl_coef_tap(int i)
4462 static u16 cnl_nearest_filter_coef(int t)
4464 return t == 3 ? 0x0800 : 0x3000;
4468 * Theory behind setting nearest-neighbor integer scaling:
4470 * 17 phase of 7 taps requires 119 coefficients in 60 dwords per set.
4471 * The letter represents the filter tap (D is the center tap) and the number
4472 * represents the coefficient set for a phase (0-16).
4474 * +------------+------------------------+------------------------+
4475 * |Index value | Data value coeffient 1 | Data value coeffient 2 |
4476 * +------------+------------------------+------------------------+
4478 * +------------+------------------------+------------------------+
4480 * +------------+------------------------+------------------------+
4482 * +------------+------------------------+------------------------+
4484 * +------------+------------------------+------------------------+
4486 * +------------+------------------------+------------------------+
4487 * | ... | ... | ... |
4488 * +------------+------------------------+------------------------+
4489 * | 38h | B16 | A16 |
4490 * +------------+------------------------+------------------------+
4491 * | 39h | D16 | C16 |
4492 * +------------+------------------------+------------------------+
4493 * | 3Ah | F16 | C16 |
4494 * +------------+------------------------+------------------------+
4495 * | 3Bh | Reserved | G16 |
4496 * +------------+------------------------+------------------------+
4498 * To enable nearest-neighbor scaling: program scaler coefficents with
4499 * the center tap (Dxx) values set to 1 and all other values set to 0 as per
4500 * SCALER_COEFFICIENT_FORMAT
4504 static void cnl_program_nearest_filter_coefs(struct drm_i915_private *dev_priv,
4505 enum pipe pipe, int id, int set)
4509 intel_de_write_fw(dev_priv, CNL_PS_COEF_INDEX_SET(pipe, id, set),
4510 PS_COEE_INDEX_AUTO_INC);
4512 for (i = 0; i < 17 * 7; i += 2) {
4516 t = cnl_coef_tap(i);
4517 tmp = cnl_nearest_filter_coef(t);
4519 t = cnl_coef_tap(i + 1);
4520 tmp |= cnl_nearest_filter_coef(t) << 16;
4522 intel_de_write_fw(dev_priv, CNL_PS_COEF_DATA_SET(pipe, id, set),
4526 intel_de_write_fw(dev_priv, CNL_PS_COEF_INDEX_SET(pipe, id, set), 0);
4529 u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set)
4531 if (filter == DRM_SCALING_FILTER_NEAREST_NEIGHBOR) {
4532 return (PS_FILTER_PROGRAMMED |
4533 PS_Y_VERT_FILTER_SELECT(set) |
4534 PS_Y_HORZ_FILTER_SELECT(set) |
4535 PS_UV_VERT_FILTER_SELECT(set) |
4536 PS_UV_HORZ_FILTER_SELECT(set));
4539 return PS_FILTER_MEDIUM;
4542 void skl_scaler_setup_filter(struct drm_i915_private *dev_priv, enum pipe pipe,
4543 int id, int set, enum drm_scaling_filter filter)
4546 case DRM_SCALING_FILTER_DEFAULT:
4548 case DRM_SCALING_FILTER_NEAREST_NEIGHBOR:
4549 cnl_program_nearest_filter_coefs(dev_priv, pipe, id, set);
4552 MISSING_CASE(filter);
4556 static void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
4558 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4559 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4560 const struct intel_crtc_scaler_state *scaler_state =
4561 &crtc_state->scaler_state;
4562 struct drm_rect src = {
4563 .x2 = crtc_state->pipe_src_w << 16,
4564 .y2 = crtc_state->pipe_src_h << 16,
4566 const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
4567 u16 uv_rgb_hphase, uv_rgb_vphase;
4568 enum pipe pipe = crtc->pipe;
4569 int width = drm_rect_width(dst);
4570 int height = drm_rect_height(dst);
4574 unsigned long irqflags;
4578 if (!crtc_state->pch_pfit.enabled)
4581 if (drm_WARN_ON(&dev_priv->drm,
4582 crtc_state->scaler_state.scaler_id < 0))
4585 hscale = drm_rect_calc_hscale(&src, dst, 0, INT_MAX);
4586 vscale = drm_rect_calc_vscale(&src, dst, 0, INT_MAX);
4588 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
4589 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
4591 id = scaler_state->scaler_id;
4593 ps_ctrl = skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0);
4594 ps_ctrl |= PS_SCALER_EN | scaler_state->scalers[id].mode;
4596 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4598 skl_scaler_setup_filter(dev_priv, pipe, id, 0,
4599 crtc_state->hw.scaling_filter);
4601 intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), ps_ctrl);
4603 intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
4604 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
4605 intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
4606 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
4607 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
4609 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
4610 width << 16 | height);
4612 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4615 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
4617 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4618 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4619 const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
4620 enum pipe pipe = crtc->pipe;
4621 int width = drm_rect_width(dst);
4622 int height = drm_rect_height(dst);
4626 if (!crtc_state->pch_pfit.enabled)
4629 /* Force use of hard-coded filter coefficients
4630 * as some pre-programmed values are broken,
4633 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4634 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
4635 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
4637 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
4639 intel_de_write(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
4640 intel_de_write(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
4643 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
4645 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4646 struct drm_device *dev = crtc->base.dev;
4647 struct drm_i915_private *dev_priv = to_i915(dev);
4649 if (!crtc_state->ips_enabled)
4653 * We can only enable IPS after we enable a plane and wait for a vblank
4654 * This function is called from post_plane_update, which is run after
4657 drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
4659 if (IS_BROADWELL(dev_priv)) {
4660 drm_WARN_ON(dev, sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
4661 IPS_ENABLE | IPS_PCODE_CONTROL));
4662 /* Quoting Art Runyan: "its not safe to expect any particular
4663 * value in IPS_CTL bit 31 after enabling IPS through the
4664 * mailbox." Moreover, the mailbox may return a bogus state,
4665 * so we need to just enable it and continue on.
4668 intel_de_write(dev_priv, IPS_CTL, IPS_ENABLE);
4669 /* The bit only becomes 1 in the next vblank, so this wait here
4670 * is essentially intel_wait_for_vblank. If we don't have this
4671 * and don't wait for vblanks until the end of crtc_enable, then
4672 * the HW state readout code will complain that the expected
4673 * IPS_CTL value is not the one we read. */
4674 if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50))
4675 drm_err(&dev_priv->drm,
4676 "Timed out waiting for IPS enable\n");
4680 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
4682 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4683 struct drm_device *dev = crtc->base.dev;
4684 struct drm_i915_private *dev_priv = to_i915(dev);
4686 if (!crtc_state->ips_enabled)
4689 if (IS_BROADWELL(dev_priv)) {
4691 sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4693 * Wait for PCODE to finish disabling IPS. The BSpec specified
4694 * 42ms timeout value leads to occasional timeouts so use 100ms
4697 if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100))
4698 drm_err(&dev_priv->drm,
4699 "Timed out waiting for IPS disable\n");
4701 intel_de_write(dev_priv, IPS_CTL, 0);
4702 intel_de_posting_read(dev_priv, IPS_CTL);
4705 /* We need to wait for a vblank before we can disable the plane. */
4706 intel_wait_for_vblank(dev_priv, crtc->pipe);
4709 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4711 if (intel_crtc->overlay)
4712 (void) intel_overlay_switch_off(intel_crtc->overlay);
4714 /* Let userspace switch the overlay on again. In most cases userspace
4715 * has to recompute where to put it anyway.
4719 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
4720 const struct intel_crtc_state *new_crtc_state)
4722 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
4723 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4725 if (!old_crtc_state->ips_enabled)
4728 if (intel_crtc_needs_modeset(new_crtc_state))
4732 * Workaround : Do not read or write the pipe palette/gamma data while
4733 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4735 * Disable IPS before we program the LUT.
4737 if (IS_HASWELL(dev_priv) &&
4738 (new_crtc_state->uapi.color_mgmt_changed ||
4739 new_crtc_state->update_pipe) &&
4740 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
4743 return !new_crtc_state->ips_enabled;
4746 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
4747 const struct intel_crtc_state *new_crtc_state)
4749 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
4750 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4752 if (!new_crtc_state->ips_enabled)
4755 if (intel_crtc_needs_modeset(new_crtc_state))
4759 * Workaround : Do not read or write the pipe palette/gamma data while
4760 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4762 * Re-enable IPS after the LUT has been programmed.
4764 if (IS_HASWELL(dev_priv) &&
4765 (new_crtc_state->uapi.color_mgmt_changed ||
4766 new_crtc_state->update_pipe) &&
4767 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
4771 * We can't read out IPS on broadwell, assume the worst and
4772 * forcibly enable IPS on the first fastset.
4774 if (new_crtc_state->update_pipe && old_crtc_state->inherited)
4777 return !old_crtc_state->ips_enabled;
4780 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
4782 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4784 if (!crtc_state->nv12_planes)
4787 /* WA Display #0827: Gen9:all */
4788 if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
4794 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
4796 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4798 /* Wa_2006604312:icl,ehl */
4799 if (crtc_state->scaler_state.scaler_users > 0 && IS_GEN(dev_priv, 11))
4805 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
4806 const struct intel_crtc_state *new_crtc_state)
4808 return (!old_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)) &&
4809 new_crtc_state->active_planes;
4812 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
4813 const struct intel_crtc_state *new_crtc_state)
4815 return old_crtc_state->active_planes &&
4816 (!new_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state));
4819 static void intel_post_plane_update(struct intel_atomic_state *state,
4820 struct intel_crtc *crtc)
4822 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4823 const struct intel_crtc_state *old_crtc_state =
4824 intel_atomic_get_old_crtc_state(state, crtc);
4825 const struct intel_crtc_state *new_crtc_state =
4826 intel_atomic_get_new_crtc_state(state, crtc);
4827 enum pipe pipe = crtc->pipe;
4829 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
4831 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
4832 intel_update_watermarks(crtc);
4834 if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
4835 hsw_enable_ips(new_crtc_state);
4837 intel_fbc_post_update(state, crtc);
4839 if (needs_nv12_wa(old_crtc_state) &&
4840 !needs_nv12_wa(new_crtc_state))
4841 skl_wa_827(dev_priv, pipe, false);
4843 if (needs_scalerclk_wa(old_crtc_state) &&
4844 !needs_scalerclk_wa(new_crtc_state))
4845 icl_wa_scalerclkgating(dev_priv, pipe, false);
4848 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state,
4849 struct intel_crtc *crtc)
4851 const struct intel_crtc_state *crtc_state =
4852 intel_atomic_get_new_crtc_state(state, crtc);
4853 u8 update_planes = crtc_state->update_planes;
4854 const struct intel_plane_state *plane_state;
4855 struct intel_plane *plane;
4858 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4859 if (plane->enable_flip_done &&
4860 plane->pipe == crtc->pipe &&
4861 update_planes & BIT(plane->id))
4862 plane->enable_flip_done(plane);
4866 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state,
4867 struct intel_crtc *crtc)
4869 const struct intel_crtc_state *crtc_state =
4870 intel_atomic_get_new_crtc_state(state, crtc);
4871 u8 update_planes = crtc_state->update_planes;
4872 const struct intel_plane_state *plane_state;
4873 struct intel_plane *plane;
4876 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4877 if (plane->disable_flip_done &&
4878 plane->pipe == crtc->pipe &&
4879 update_planes & BIT(plane->id))
4880 plane->disable_flip_done(plane);
4884 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
4885 struct intel_crtc *crtc)
4887 struct drm_i915_private *i915 = to_i915(state->base.dev);
4888 const struct intel_crtc_state *old_crtc_state =
4889 intel_atomic_get_old_crtc_state(state, crtc);
4890 const struct intel_crtc_state *new_crtc_state =
4891 intel_atomic_get_new_crtc_state(state, crtc);
4892 u8 update_planes = new_crtc_state->update_planes;
4893 const struct intel_plane_state *old_plane_state;
4894 struct intel_plane *plane;
4895 bool need_vbl_wait = false;
4898 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
4899 if (plane->need_async_flip_disable_wa &&
4900 plane->pipe == crtc->pipe &&
4901 update_planes & BIT(plane->id)) {
4903 * Apart from the async flip bit we want to
4904 * preserve the old state for the plane.
4906 plane->async_flip(plane, old_crtc_state,
4907 old_plane_state, false);
4908 need_vbl_wait = true;
4913 intel_wait_for_vblank(i915, crtc->pipe);
4916 static void intel_pre_plane_update(struct intel_atomic_state *state,
4917 struct intel_crtc *crtc)
4919 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4920 const struct intel_crtc_state *old_crtc_state =
4921 intel_atomic_get_old_crtc_state(state, crtc);
4922 const struct intel_crtc_state *new_crtc_state =
4923 intel_atomic_get_new_crtc_state(state, crtc);
4924 enum pipe pipe = crtc->pipe;
4926 if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
4927 hsw_disable_ips(old_crtc_state);
4929 if (intel_fbc_pre_update(state, crtc))
4930 intel_wait_for_vblank(dev_priv, pipe);
4932 /* Display WA 827 */
4933 if (!needs_nv12_wa(old_crtc_state) &&
4934 needs_nv12_wa(new_crtc_state))
4935 skl_wa_827(dev_priv, pipe, true);
4937 /* Wa_2006604312:icl,ehl */
4938 if (!needs_scalerclk_wa(old_crtc_state) &&
4939 needs_scalerclk_wa(new_crtc_state))
4940 icl_wa_scalerclkgating(dev_priv, pipe, true);
4943 * Vblank time updates from the shadow to live plane control register
4944 * are blocked if the memory self-refresh mode is active at that
4945 * moment. So to make sure the plane gets truly disabled, disable
4946 * first the self-refresh mode. The self-refresh enable bit in turn
4947 * will be checked/applied by the HW only at the next frame start
4948 * event which is after the vblank start event, so we need to have a
4949 * wait-for-vblank between disabling the plane and the pipe.
4951 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
4952 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
4953 intel_wait_for_vblank(dev_priv, pipe);
4956 * IVB workaround: must disable low power watermarks for at least
4957 * one frame before enabling scaling. LP watermarks can be re-enabled
4958 * when scaling is disabled.
4960 * WaCxSRDisabledForSpriteScaling:ivb
4962 if (old_crtc_state->hw.active &&
4963 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
4964 intel_wait_for_vblank(dev_priv, pipe);
4967 * If we're doing a modeset we don't need to do any
4968 * pre-vblank watermark programming here.
4970 if (!intel_crtc_needs_modeset(new_crtc_state)) {
4972 * For platforms that support atomic watermarks, program the
4973 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
4974 * will be the intermediate values that are safe for both pre- and
4975 * post- vblank; when vblank happens, the 'active' values will be set
4976 * to the final 'target' values and we'll do this again to get the
4977 * optimal watermarks. For gen9+ platforms, the values we program here
4978 * will be the final target values which will get automatically latched
4979 * at vblank time; no further programming will be necessary.
4981 * If a platform hasn't been transitioned to atomic watermarks yet,
4982 * we'll continue to update watermarks the old way, if flags tell
4985 if (dev_priv->display.initial_watermarks)
4986 dev_priv->display.initial_watermarks(state, crtc);
4987 else if (new_crtc_state->update_wm_pre)
4988 intel_update_watermarks(crtc);
4992 * Gen2 reports pipe underruns whenever all planes are disabled.
4993 * So disable underrun reporting before all the planes get disabled.
4995 * We do this after .initial_watermarks() so that we have a
4996 * chance of catching underruns with the intermediate watermarks
4997 * vs. the old plane configuration.
4999 if (IS_GEN(dev_priv, 2) && planes_disabling(old_crtc_state, new_crtc_state))
5000 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5003 * WA for platforms where async address update enable bit
5004 * is double buffered and only latched at start of vblank.
5006 if (old_crtc_state->uapi.async_flip && !new_crtc_state->uapi.async_flip)
5007 intel_crtc_async_flip_disable_wa(state, crtc);
5010 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
5011 struct intel_crtc *crtc)
5013 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5014 const struct intel_crtc_state *new_crtc_state =
5015 intel_atomic_get_new_crtc_state(state, crtc);
5016 unsigned int update_mask = new_crtc_state->update_planes;
5017 const struct intel_plane_state *old_plane_state;
5018 struct intel_plane *plane;
5019 unsigned fb_bits = 0;
5022 intel_crtc_dpms_overlay_disable(crtc);
5024 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
5025 if (crtc->pipe != plane->pipe ||
5026 !(update_mask & BIT(plane->id)))
5029 intel_disable_plane(plane, new_crtc_state);
5031 if (old_plane_state->uapi.visible)
5032 fb_bits |= plane->frontbuffer_bit;
5035 intel_frontbuffer_flip(dev_priv, fb_bits);
5039 * intel_connector_primary_encoder - get the primary encoder for a connector
5040 * @connector: connector for which to return the encoder
5042 * Returns the primary encoder for a connector. There is a 1:1 mapping from
5043 * all connectors to their encoder, except for DP-MST connectors which have
5044 * both a virtual and a primary encoder. These DP-MST primary encoders can be
5045 * pointed to by as many DP-MST connectors as there are pipes.
5047 static struct intel_encoder *
5048 intel_connector_primary_encoder(struct intel_connector *connector)
5050 struct intel_encoder *encoder;
5052 if (connector->mst_port)
5053 return &dp_to_dig_port(connector->mst_port)->base;
5055 encoder = intel_attached_encoder(connector);
5056 drm_WARN_ON(connector->base.dev, !encoder);
5061 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
5063 struct drm_connector_state *new_conn_state;
5064 struct drm_connector *connector;
5067 for_each_new_connector_in_state(&state->base, connector, new_conn_state,
5069 struct intel_connector *intel_connector;
5070 struct intel_encoder *encoder;
5071 struct intel_crtc *crtc;
5073 if (!intel_connector_needs_modeset(state, connector))
5076 intel_connector = to_intel_connector(connector);
5077 encoder = intel_connector_primary_encoder(intel_connector);
5078 if (!encoder->update_prepare)
5081 crtc = new_conn_state->crtc ?
5082 to_intel_crtc(new_conn_state->crtc) : NULL;
5083 encoder->update_prepare(state, encoder, crtc);
5087 static void intel_encoders_update_complete(struct intel_atomic_state *state)
5089 struct drm_connector_state *new_conn_state;
5090 struct drm_connector *connector;
5093 for_each_new_connector_in_state(&state->base, connector, new_conn_state,
5095 struct intel_connector *intel_connector;
5096 struct intel_encoder *encoder;
5097 struct intel_crtc *crtc;
5099 if (!intel_connector_needs_modeset(state, connector))
5102 intel_connector = to_intel_connector(connector);
5103 encoder = intel_connector_primary_encoder(intel_connector);
5104 if (!encoder->update_complete)
5107 crtc = new_conn_state->crtc ?
5108 to_intel_crtc(new_conn_state->crtc) : NULL;
5109 encoder->update_complete(state, encoder, crtc);
5113 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
5114 struct intel_crtc *crtc)
5116 const struct intel_crtc_state *crtc_state =
5117 intel_atomic_get_new_crtc_state(state, crtc);
5118 const struct drm_connector_state *conn_state;
5119 struct drm_connector *conn;
5122 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
5123 struct intel_encoder *encoder =
5124 to_intel_encoder(conn_state->best_encoder);
5126 if (conn_state->crtc != &crtc->base)
5129 if (encoder->pre_pll_enable)
5130 encoder->pre_pll_enable(state, encoder,
5131 crtc_state, conn_state);
5135 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
5136 struct intel_crtc *crtc)
5138 const struct intel_crtc_state *crtc_state =
5139 intel_atomic_get_new_crtc_state(state, crtc);
5140 const struct drm_connector_state *conn_state;
5141 struct drm_connector *conn;
5144 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
5145 struct intel_encoder *encoder =
5146 to_intel_encoder(conn_state->best_encoder);
5148 if (conn_state->crtc != &crtc->base)
5151 if (encoder->pre_enable)
5152 encoder->pre_enable(state, encoder,
5153 crtc_state, conn_state);
5157 static void intel_encoders_enable(struct intel_atomic_state *state,
5158 struct intel_crtc *crtc)
5160 const struct intel_crtc_state *crtc_state =
5161 intel_atomic_get_new_crtc_state(state, crtc);
5162 const struct drm_connector_state *conn_state;
5163 struct drm_connector *conn;
5166 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
5167 struct intel_encoder *encoder =
5168 to_intel_encoder(conn_state->best_encoder);
5170 if (conn_state->crtc != &crtc->base)
5173 if (encoder->enable)
5174 encoder->enable(state, encoder,
5175 crtc_state, conn_state);
5176 intel_opregion_notify_encoder(encoder, true);
5180 static void intel_encoders_disable(struct intel_atomic_state *state,
5181 struct intel_crtc *crtc)
5183 const struct intel_crtc_state *old_crtc_state =
5184 intel_atomic_get_old_crtc_state(state, crtc);
5185 const struct drm_connector_state *old_conn_state;
5186 struct drm_connector *conn;
5189 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
5190 struct intel_encoder *encoder =
5191 to_intel_encoder(old_conn_state->best_encoder);
5193 if (old_conn_state->crtc != &crtc->base)
5196 intel_opregion_notify_encoder(encoder, false);
5197 if (encoder->disable)
5198 encoder->disable(state, encoder,
5199 old_crtc_state, old_conn_state);
5203 static void intel_encoders_post_disable(struct intel_atomic_state *state,
5204 struct intel_crtc *crtc)
5206 const struct intel_crtc_state *old_crtc_state =
5207 intel_atomic_get_old_crtc_state(state, crtc);
5208 const struct drm_connector_state *old_conn_state;
5209 struct drm_connector *conn;
5212 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
5213 struct intel_encoder *encoder =
5214 to_intel_encoder(old_conn_state->best_encoder);
5216 if (old_conn_state->crtc != &crtc->base)
5219 if (encoder->post_disable)
5220 encoder->post_disable(state, encoder,
5221 old_crtc_state, old_conn_state);
5225 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
5226 struct intel_crtc *crtc)
5228 const struct intel_crtc_state *old_crtc_state =
5229 intel_atomic_get_old_crtc_state(state, crtc);
5230 const struct drm_connector_state *old_conn_state;
5231 struct drm_connector *conn;
5234 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
5235 struct intel_encoder *encoder =
5236 to_intel_encoder(old_conn_state->best_encoder);
5238 if (old_conn_state->crtc != &crtc->base)
5241 if (encoder->post_pll_disable)
5242 encoder->post_pll_disable(state, encoder,
5243 old_crtc_state, old_conn_state);
5247 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
5248 struct intel_crtc *crtc)
5250 const struct intel_crtc_state *crtc_state =
5251 intel_atomic_get_new_crtc_state(state, crtc);
5252 const struct drm_connector_state *conn_state;
5253 struct drm_connector *conn;
5256 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
5257 struct intel_encoder *encoder =
5258 to_intel_encoder(conn_state->best_encoder);
5260 if (conn_state->crtc != &crtc->base)
5263 if (encoder->update_pipe)
5264 encoder->update_pipe(state, encoder,
5265 crtc_state, conn_state);
5269 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
5271 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5272 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
5274 plane->disable_plane(plane, crtc_state);
5277 static void ilk_crtc_enable(struct intel_atomic_state *state,
5278 struct intel_crtc *crtc)
5280 const struct intel_crtc_state *new_crtc_state =
5281 intel_atomic_get_new_crtc_state(state, crtc);
5282 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5283 enum pipe pipe = crtc->pipe;
5285 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
5289 * Sometimes spurious CPU pipe underruns happen during FDI
5290 * training, at least with VGA+HDMI cloning. Suppress them.
5292 * On ILK we get an occasional spurious CPU pipe underruns
5293 * between eDP port A enable and vdd enable. Also PCH port
5294 * enable seems to result in the occasional CPU pipe underrun.
5296 * Spurious PCH underruns also occur during PCH enabling.
5298 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5299 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5301 if (new_crtc_state->has_pch_encoder)
5302 intel_prepare_shared_dpll(new_crtc_state);
5304 if (intel_crtc_has_dp_encoder(new_crtc_state))
5305 intel_dp_set_m_n(new_crtc_state, M1_N1);
5307 intel_set_transcoder_timings(new_crtc_state);
5308 intel_set_pipe_src_size(new_crtc_state);
5310 if (new_crtc_state->has_pch_encoder)
5311 intel_cpu_transcoder_set_m_n(new_crtc_state,
5312 &new_crtc_state->fdi_m_n, NULL);
5314 ilk_set_pipeconf(new_crtc_state);
5316 crtc->active = true;
5318 intel_encoders_pre_enable(state, crtc);
5320 if (new_crtc_state->has_pch_encoder) {
5321 /* Note: FDI PLL enabling _must_ be done before we enable the
5322 * cpu pipes, hence this is separate from all the other fdi/pch
5324 ilk_fdi_pll_enable(new_crtc_state);
5326 assert_fdi_tx_disabled(dev_priv, pipe);
5327 assert_fdi_rx_disabled(dev_priv, pipe);
5330 ilk_pfit_enable(new_crtc_state);
5333 * On ILK+ LUT must be loaded before the pipe is running but with
5336 intel_color_load_luts(new_crtc_state);
5337 intel_color_commit(new_crtc_state);
5338 /* update DSPCNTR to configure gamma for pipe bottom color */
5339 intel_disable_primary_plane(new_crtc_state);
5341 if (dev_priv->display.initial_watermarks)
5342 dev_priv->display.initial_watermarks(state, crtc);
5343 intel_enable_pipe(new_crtc_state);
5345 if (new_crtc_state->has_pch_encoder)
5346 ilk_pch_enable(state, new_crtc_state);
5348 intel_crtc_vblank_on(new_crtc_state);
5350 intel_encoders_enable(state, crtc);
5352 if (HAS_PCH_CPT(dev_priv))
5353 cpt_verify_modeset(dev_priv, pipe);
5356 * Must wait for vblank to avoid spurious PCH FIFO underruns.
5357 * And a second vblank wait is needed at least on ILK with
5358 * some interlaced HDMI modes. Let's do the double wait always
5359 * in case there are more corner cases we don't know about.
5361 if (new_crtc_state->has_pch_encoder) {
5362 intel_wait_for_vblank(dev_priv, pipe);
5363 intel_wait_for_vblank(dev_priv, pipe);
5365 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5366 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5369 /* IPS only exists on ULT machines and is tied to pipe A. */
5370 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5372 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5375 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
5376 enum pipe pipe, bool apply)
5378 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe));
5379 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
5386 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
5389 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
5391 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5392 enum pipe pipe = crtc->pipe;
5395 val = MBUS_DBOX_A_CREDIT(2);
5397 if (INTEL_GEN(dev_priv) >= 12) {
5398 val |= MBUS_DBOX_BW_CREDIT(2);
5399 val |= MBUS_DBOX_B_CREDIT(12);
5401 val |= MBUS_DBOX_BW_CREDIT(1);
5402 val |= MBUS_DBOX_B_CREDIT(8);
5405 intel_de_write(dev_priv, PIPE_MBUS_DBOX_CTL(pipe), val);
5408 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
5410 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5411 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5413 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),
5414 HSW_LINETIME(crtc_state->linetime) |
5415 HSW_IPS_LINETIME(crtc_state->ips_linetime));
5418 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
5420 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5421 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5422 i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
5425 val = intel_de_read(dev_priv, reg);
5426 val &= ~HSW_FRAME_START_DELAY_MASK;
5427 val |= HSW_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
5428 intel_de_write(dev_priv, reg, val);
5431 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
5432 const struct intel_crtc_state *crtc_state)
5434 struct intel_crtc *master = to_intel_crtc(crtc_state->uapi.crtc);
5435 struct intel_crtc_state *master_crtc_state;
5436 struct drm_connector_state *conn_state;
5437 struct drm_connector *conn;
5438 struct intel_encoder *encoder = NULL;
5441 if (crtc_state->bigjoiner_slave)
5442 master = crtc_state->bigjoiner_linked_crtc;
5444 master_crtc_state = intel_atomic_get_new_crtc_state(state, master);
5446 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
5447 if (conn_state->crtc != &master->base)
5450 encoder = to_intel_encoder(conn_state->best_encoder);
5454 if (!crtc_state->bigjoiner_slave) {
5455 /* need to enable VDSC, which we skipped in pre-enable */
5456 intel_dsc_enable(encoder, crtc_state);
5459 * Enable sequence steps 1-7 on bigjoiner master
5461 intel_encoders_pre_pll_enable(state, master);
5462 intel_enable_shared_dpll(master_crtc_state);
5463 intel_encoders_pre_enable(state, master);
5465 /* and DSC on slave */
5466 intel_dsc_enable(NULL, crtc_state);
5470 static void hsw_crtc_enable(struct intel_atomic_state *state,
5471 struct intel_crtc *crtc)
5473 const struct intel_crtc_state *new_crtc_state =
5474 intel_atomic_get_new_crtc_state(state, crtc);
5475 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5476 enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
5477 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
5478 bool psl_clkgate_wa;
5480 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
5483 if (!new_crtc_state->bigjoiner) {
5484 intel_encoders_pre_pll_enable(state, crtc);
5486 if (new_crtc_state->shared_dpll)
5487 intel_enable_shared_dpll(new_crtc_state);
5489 intel_encoders_pre_enable(state, crtc);
5491 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
5494 intel_set_pipe_src_size(new_crtc_state);
5495 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
5496 bdw_set_pipemisc(new_crtc_state);
5498 if (!new_crtc_state->bigjoiner_slave && !transcoder_is_dsi(cpu_transcoder)) {
5499 intel_set_transcoder_timings(new_crtc_state);
5501 if (cpu_transcoder != TRANSCODER_EDP)
5502 intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
5503 new_crtc_state->pixel_multiplier - 1);
5505 if (new_crtc_state->has_pch_encoder)
5506 intel_cpu_transcoder_set_m_n(new_crtc_state,
5507 &new_crtc_state->fdi_m_n, NULL);
5509 hsw_set_frame_start_delay(new_crtc_state);
5512 if (!transcoder_is_dsi(cpu_transcoder))
5513 hsw_set_pipeconf(new_crtc_state);
5515 crtc->active = true;
5517 /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
5518 psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
5519 new_crtc_state->pch_pfit.enabled;
5521 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
5523 if (INTEL_GEN(dev_priv) >= 9)
5524 skl_pfit_enable(new_crtc_state);
5526 ilk_pfit_enable(new_crtc_state);
5529 * On ILK+ LUT must be loaded before the pipe is running but with
5532 intel_color_load_luts(new_crtc_state);
5533 intel_color_commit(new_crtc_state);
5534 /* update DSPCNTR to configure gamma/csc for pipe bottom color */
5535 if (INTEL_GEN(dev_priv) < 9)
5536 intel_disable_primary_plane(new_crtc_state);
5538 hsw_set_linetime_wm(new_crtc_state);
5540 if (INTEL_GEN(dev_priv) >= 11)
5541 icl_set_pipe_chicken(crtc);
5543 if (dev_priv->display.initial_watermarks)
5544 dev_priv->display.initial_watermarks(state, crtc);
5546 if (INTEL_GEN(dev_priv) >= 11)
5547 icl_pipe_mbus_enable(crtc);
5549 if (new_crtc_state->bigjoiner_slave) {
5550 trace_intel_pipe_enable(crtc);
5551 intel_crtc_vblank_on(new_crtc_state);
5554 intel_encoders_enable(state, crtc);
5556 if (psl_clkgate_wa) {
5557 intel_wait_for_vblank(dev_priv, pipe);
5558 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
5561 /* If we change the relative order between pipe/planes enabling, we need
5562 * to change the workaround. */
5563 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
5564 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5565 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5566 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5570 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
5572 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
5573 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5574 enum pipe pipe = crtc->pipe;
5576 /* To avoid upsetting the power well on haswell only disable the pfit if
5577 * it's in use. The hw state code will make sure we get this right. */
5578 if (!old_crtc_state->pch_pfit.enabled)
5581 intel_de_write(dev_priv, PF_CTL(pipe), 0);
5582 intel_de_write(dev_priv, PF_WIN_POS(pipe), 0);
5583 intel_de_write(dev_priv, PF_WIN_SZ(pipe), 0);
5586 static void ilk_crtc_disable(struct intel_atomic_state *state,
5587 struct intel_crtc *crtc)
5589 const struct intel_crtc_state *old_crtc_state =
5590 intel_atomic_get_old_crtc_state(state, crtc);
5591 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5592 enum pipe pipe = crtc->pipe;
5595 * Sometimes spurious CPU pipe underruns happen when the
5596 * pipe is already disabled, but FDI RX/TX is still enabled.
5597 * Happens at least with VGA+HDMI cloning. Suppress them.
5599 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5600 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5602 intel_encoders_disable(state, crtc);
5604 intel_crtc_vblank_off(old_crtc_state);
5606 intel_disable_pipe(old_crtc_state);
5608 ilk_pfit_disable(old_crtc_state);
5610 if (old_crtc_state->has_pch_encoder)
5611 ilk_fdi_disable(crtc);
5613 intel_encoders_post_disable(state, crtc);
5615 if (old_crtc_state->has_pch_encoder) {
5616 ilk_disable_pch_transcoder(dev_priv, pipe);
5618 if (HAS_PCH_CPT(dev_priv)) {
5622 /* disable TRANS_DP_CTL */
5623 reg = TRANS_DP_CTL(pipe);
5624 temp = intel_de_read(dev_priv, reg);
5625 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5626 TRANS_DP_PORT_SEL_MASK);
5627 temp |= TRANS_DP_PORT_SEL_NONE;
5628 intel_de_write(dev_priv, reg, temp);
5630 /* disable DPLL_SEL */
5631 temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
5632 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5633 intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
5636 ilk_fdi_pll_disable(crtc);
5639 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5640 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5643 static void hsw_crtc_disable(struct intel_atomic_state *state,
5644 struct intel_crtc *crtc)
5647 * FIXME collapse everything to one hook.
5648 * Need care with mst->ddi interactions.
5650 intel_encoders_disable(state, crtc);
5651 intel_encoders_post_disable(state, crtc);
5654 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
5656 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5657 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5659 if (!crtc_state->gmch_pfit.control)
5663 * The panel fitter should only be adjusted whilst the pipe is disabled,
5664 * according to register description and PRM.
5666 drm_WARN_ON(&dev_priv->drm,
5667 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
5668 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
5670 intel_de_write(dev_priv, PFIT_PGM_RATIOS,
5671 crtc_state->gmch_pfit.pgm_ratios);
5672 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
5674 /* Border color in case we don't scale up to the full screen. Black by
5675 * default, change to something else for debugging. */
5676 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
5679 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
5681 if (phy == PHY_NONE)
5683 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
5684 return phy <= PHY_D;
5685 else if (IS_JSL_EHL(dev_priv))
5686 return phy <= PHY_C;
5687 else if (INTEL_GEN(dev_priv) >= 11)
5688 return phy <= PHY_B;
5693 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
5695 if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
5697 else if (INTEL_GEN(dev_priv) >= 12)
5698 return phy >= PHY_D && phy <= PHY_I;
5699 else if (INTEL_GEN(dev_priv) >= 11 && !IS_JSL_EHL(dev_priv))
5700 return phy >= PHY_C && phy <= PHY_F;
5705 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
5707 if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
5708 return PHY_C + port - PORT_TC1;
5709 else if (IS_JSL_EHL(i915) && port == PORT_D)
5712 return PHY_A + port - PORT_A;
5715 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
5717 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
5718 return TC_PORT_NONE;
5720 if (INTEL_GEN(dev_priv) >= 12)
5721 return TC_PORT_1 + port - PORT_TC1;
5723 return TC_PORT_1 + port - PORT_C;
5726 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5730 return POWER_DOMAIN_PORT_DDI_A_LANES;
5732 return POWER_DOMAIN_PORT_DDI_B_LANES;
5734 return POWER_DOMAIN_PORT_DDI_C_LANES;
5736 return POWER_DOMAIN_PORT_DDI_D_LANES;
5738 return POWER_DOMAIN_PORT_DDI_E_LANES;
5740 return POWER_DOMAIN_PORT_DDI_F_LANES;
5742 return POWER_DOMAIN_PORT_DDI_G_LANES;
5744 return POWER_DOMAIN_PORT_DDI_H_LANES;
5746 return POWER_DOMAIN_PORT_DDI_I_LANES;
5749 return POWER_DOMAIN_PORT_OTHER;
5753 enum intel_display_power_domain
5754 intel_aux_power_domain(struct intel_digital_port *dig_port)
5756 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
5757 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
5759 if (intel_phy_is_tc(dev_priv, phy) &&
5760 dig_port->tc_mode == TC_PORT_TBT_ALT) {
5761 switch (dig_port->aux_ch) {
5763 return POWER_DOMAIN_AUX_C_TBT;
5765 return POWER_DOMAIN_AUX_D_TBT;
5767 return POWER_DOMAIN_AUX_E_TBT;
5769 return POWER_DOMAIN_AUX_F_TBT;
5771 return POWER_DOMAIN_AUX_G_TBT;
5773 return POWER_DOMAIN_AUX_H_TBT;
5775 return POWER_DOMAIN_AUX_I_TBT;
5777 MISSING_CASE(dig_port->aux_ch);
5778 return POWER_DOMAIN_AUX_C_TBT;
5782 return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
5786 * Converts aux_ch to power_domain without caring about TBT ports for that use
5787 * intel_aux_power_domain()
5789 enum intel_display_power_domain
5790 intel_legacy_aux_to_power_domain(enum aux_ch aux_ch)
5794 return POWER_DOMAIN_AUX_A;
5796 return POWER_DOMAIN_AUX_B;
5798 return POWER_DOMAIN_AUX_C;
5800 return POWER_DOMAIN_AUX_D;
5802 return POWER_DOMAIN_AUX_E;
5804 return POWER_DOMAIN_AUX_F;
5806 return POWER_DOMAIN_AUX_G;
5808 return POWER_DOMAIN_AUX_H;
5810 return POWER_DOMAIN_AUX_I;
5812 MISSING_CASE(aux_ch);
5813 return POWER_DOMAIN_AUX_A;
5817 static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
5819 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5820 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5821 struct drm_encoder *encoder;
5822 enum pipe pipe = crtc->pipe;
5824 enum transcoder transcoder = crtc_state->cpu_transcoder;
5826 if (!crtc_state->hw.active)
5829 mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
5830 mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
5831 if (crtc_state->pch_pfit.enabled ||
5832 crtc_state->pch_pfit.force_thru)
5833 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5835 drm_for_each_encoder_mask(encoder, &dev_priv->drm,
5836 crtc_state->uapi.encoder_mask) {
5837 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5839 mask |= BIT_ULL(intel_encoder->power_domain);
5842 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5843 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
5845 if (crtc_state->shared_dpll)
5846 mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
5848 if (crtc_state->dsc.compression_enable)
5849 mask |= BIT_ULL(intel_dsc_power_domain(crtc_state));
5855 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
5857 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5858 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5859 enum intel_display_power_domain domain;
5860 u64 domains, new_domains, old_domains;
5862 domains = get_crtc_power_domains(crtc_state);
5864 new_domains = domains & ~crtc->enabled_power_domains.mask;
5865 old_domains = crtc->enabled_power_domains.mask & ~domains;
5867 for_each_power_domain(domain, new_domains)
5868 intel_display_power_get_in_set(dev_priv,
5869 &crtc->enabled_power_domains,
5875 static void modeset_put_crtc_power_domains(struct intel_crtc *crtc,
5878 intel_display_power_put_mask_in_set(to_i915(crtc->base.dev),
5879 &crtc->enabled_power_domains,
5883 static void valleyview_crtc_enable(struct intel_atomic_state *state,
5884 struct intel_crtc *crtc)
5886 const struct intel_crtc_state *new_crtc_state =
5887 intel_atomic_get_new_crtc_state(state, crtc);
5888 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5889 enum pipe pipe = crtc->pipe;
5891 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
5894 if (intel_crtc_has_dp_encoder(new_crtc_state))
5895 intel_dp_set_m_n(new_crtc_state, M1_N1);
5897 intel_set_transcoder_timings(new_crtc_state);
5898 intel_set_pipe_src_size(new_crtc_state);
5900 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5901 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5902 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
5905 i9xx_set_pipeconf(new_crtc_state);
5907 crtc->active = true;
5909 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5911 intel_encoders_pre_pll_enable(state, crtc);
5913 if (IS_CHERRYVIEW(dev_priv)) {
5914 chv_prepare_pll(crtc, new_crtc_state);
5915 chv_enable_pll(crtc, new_crtc_state);
5917 vlv_prepare_pll(crtc, new_crtc_state);
5918 vlv_enable_pll(crtc, new_crtc_state);
5921 intel_encoders_pre_enable(state, crtc);
5923 i9xx_pfit_enable(new_crtc_state);
5925 intel_color_load_luts(new_crtc_state);
5926 intel_color_commit(new_crtc_state);
5927 /* update DSPCNTR to configure gamma for pipe bottom color */
5928 intel_disable_primary_plane(new_crtc_state);
5930 dev_priv->display.initial_watermarks(state, crtc);
5931 intel_enable_pipe(new_crtc_state);
5933 intel_crtc_vblank_on(new_crtc_state);
5935 intel_encoders_enable(state, crtc);
5938 static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
5940 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5941 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5943 intel_de_write(dev_priv, FP0(crtc->pipe),
5944 crtc_state->dpll_hw_state.fp0);
5945 intel_de_write(dev_priv, FP1(crtc->pipe),
5946 crtc_state->dpll_hw_state.fp1);
5949 static void i9xx_crtc_enable(struct intel_atomic_state *state,
5950 struct intel_crtc *crtc)
5952 const struct intel_crtc_state *new_crtc_state =
5953 intel_atomic_get_new_crtc_state(state, crtc);
5954 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5955 enum pipe pipe = crtc->pipe;
5957 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
5960 i9xx_set_pll_dividers(new_crtc_state);
5962 if (intel_crtc_has_dp_encoder(new_crtc_state))
5963 intel_dp_set_m_n(new_crtc_state, M1_N1);
5965 intel_set_transcoder_timings(new_crtc_state);
5966 intel_set_pipe_src_size(new_crtc_state);
5968 i9xx_set_pipeconf(new_crtc_state);
5970 crtc->active = true;
5972 if (!IS_GEN(dev_priv, 2))
5973 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5975 intel_encoders_pre_enable(state, crtc);
5977 i9xx_enable_pll(crtc, new_crtc_state);
5979 i9xx_pfit_enable(new_crtc_state);
5981 intel_color_load_luts(new_crtc_state);
5982 intel_color_commit(new_crtc_state);
5983 /* update DSPCNTR to configure gamma for pipe bottom color */
5984 intel_disable_primary_plane(new_crtc_state);
5986 if (dev_priv->display.initial_watermarks)
5987 dev_priv->display.initial_watermarks(state, crtc);
5989 intel_update_watermarks(crtc);
5990 intel_enable_pipe(new_crtc_state);
5992 intel_crtc_vblank_on(new_crtc_state);
5994 intel_encoders_enable(state, crtc);
5996 /* prevents spurious underruns */
5997 if (IS_GEN(dev_priv, 2))
5998 intel_wait_for_vblank(dev_priv, pipe);
6001 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
6003 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
6004 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6006 if (!old_crtc_state->gmch_pfit.control)
6009 assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
6011 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
6012 intel_de_read(dev_priv, PFIT_CONTROL));
6013 intel_de_write(dev_priv, PFIT_CONTROL, 0);
6016 static void i9xx_crtc_disable(struct intel_atomic_state *state,
6017 struct intel_crtc *crtc)
6019 struct intel_crtc_state *old_crtc_state =
6020 intel_atomic_get_old_crtc_state(state, crtc);
6021 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6022 enum pipe pipe = crtc->pipe;
6025 * On gen2 planes are double buffered but the pipe isn't, so we must
6026 * wait for planes to fully turn off before disabling the pipe.
6028 if (IS_GEN(dev_priv, 2))
6029 intel_wait_for_vblank(dev_priv, pipe);
6031 intel_encoders_disable(state, crtc);
6033 intel_crtc_vblank_off(old_crtc_state);
6035 intel_disable_pipe(old_crtc_state);
6037 i9xx_pfit_disable(old_crtc_state);
6039 intel_encoders_post_disable(state, crtc);
6041 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
6042 if (IS_CHERRYVIEW(dev_priv))
6043 chv_disable_pll(dev_priv, pipe);
6044 else if (IS_VALLEYVIEW(dev_priv))
6045 vlv_disable_pll(dev_priv, pipe);
6047 i9xx_disable_pll(old_crtc_state);
6050 intel_encoders_post_pll_disable(state, crtc);
6052 if (!IS_GEN(dev_priv, 2))
6053 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6055 if (!dev_priv->display.initial_watermarks)
6056 intel_update_watermarks(crtc);
6058 /* clock the pipe down to 640x480@60 to potentially save power */
6059 if (IS_I830(dev_priv))
6060 i830_enable_pipe(dev_priv, pipe);
6063 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
6064 struct drm_modeset_acquire_ctx *ctx)
6066 struct intel_encoder *encoder;
6067 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6068 struct intel_bw_state *bw_state =
6069 to_intel_bw_state(dev_priv->bw_obj.state);
6070 struct intel_cdclk_state *cdclk_state =
6071 to_intel_cdclk_state(dev_priv->cdclk.obj.state);
6072 struct intel_dbuf_state *dbuf_state =
6073 to_intel_dbuf_state(dev_priv->dbuf.obj.state);
6074 struct intel_crtc_state *crtc_state =
6075 to_intel_crtc_state(crtc->base.state);
6076 struct intel_plane *plane;
6077 struct drm_atomic_state *state;
6078 struct intel_crtc_state *temp_crtc_state;
6079 enum pipe pipe = crtc->pipe;
6082 if (!crtc_state->hw.active)
6085 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
6086 const struct intel_plane_state *plane_state =
6087 to_intel_plane_state(plane->base.state);
6089 if (plane_state->uapi.visible)
6090 intel_plane_disable_noatomic(crtc, plane);
6093 state = drm_atomic_state_alloc(&dev_priv->drm);
6095 drm_dbg_kms(&dev_priv->drm,
6096 "failed to disable [CRTC:%d:%s], out of memory",
6097 crtc->base.base.id, crtc->base.name);
6101 state->acquire_ctx = ctx;
6103 /* Everything's already locked, -EDEADLK can't happen. */
6104 temp_crtc_state = intel_atomic_get_crtc_state(state, crtc);
6105 ret = drm_atomic_add_affected_connectors(state, &crtc->base);
6107 drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret);
6109 dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc);
6111 drm_atomic_state_put(state);
6113 drm_dbg_kms(&dev_priv->drm,
6114 "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6115 crtc->base.base.id, crtc->base.name);
6117 crtc->active = false;
6118 crtc->base.enabled = false;
6120 drm_WARN_ON(&dev_priv->drm,
6121 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0);
6122 crtc_state->uapi.active = false;
6123 crtc_state->uapi.connector_mask = 0;
6124 crtc_state->uapi.encoder_mask = 0;
6125 intel_crtc_free_hw_state(crtc_state);
6126 memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));
6128 for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder)
6129 encoder->base.crtc = NULL;
6131 intel_fbc_disable(crtc);
6132 intel_update_watermarks(crtc);
6133 intel_disable_shared_dpll(crtc_state);
6135 intel_display_power_put_all_in_set(dev_priv, &crtc->enabled_power_domains);
6137 dev_priv->active_pipes &= ~BIT(pipe);
6138 cdclk_state->min_cdclk[pipe] = 0;
6139 cdclk_state->min_voltage_level[pipe] = 0;
6140 cdclk_state->active_pipes &= ~BIT(pipe);
6142 dbuf_state->active_pipes &= ~BIT(pipe);
6144 bw_state->data_rate[pipe] = 0;
6145 bw_state->num_active_planes[pipe] = 0;
6149 * turn all crtc's off, but do not adjust state
6150 * This has to be paired with a call to intel_modeset_setup_hw_state.
6152 int intel_display_suspend(struct drm_device *dev)
6154 struct drm_i915_private *dev_priv = to_i915(dev);
6155 struct drm_atomic_state *state;
6158 state = drm_atomic_helper_suspend(dev);
6159 ret = PTR_ERR_OR_ZERO(state);
6161 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
6164 dev_priv->modeset_restore_state = state;
6168 void intel_encoder_destroy(struct drm_encoder *encoder)
6170 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6172 drm_encoder_cleanup(encoder);
6173 kfree(intel_encoder);
6176 /* Cross check the actual hw state with our own modeset state tracking (and it's
6177 * internal consistency). */
6178 static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
6179 struct drm_connector_state *conn_state)
6181 struct intel_connector *connector = to_intel_connector(conn_state->connector);
6182 struct drm_i915_private *i915 = to_i915(connector->base.dev);
6184 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
6185 connector->base.base.id, connector->base.name);
6187 if (connector->get_hw_state(connector)) {
6188 struct intel_encoder *encoder = intel_attached_encoder(connector);
6190 I915_STATE_WARN(!crtc_state,
6191 "connector enabled without attached crtc\n");
6196 I915_STATE_WARN(!crtc_state->hw.active,
6197 "connector is active, but attached crtc isn't\n");
6199 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6202 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6203 "atomic encoder doesn't match attached encoder\n");
6205 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6206 "attached encoder crtc differs from connector crtc\n");
6208 I915_STATE_WARN(crtc_state && crtc_state->hw.active,
6209 "attached crtc is active, but connector isn't\n");
6210 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
6211 "best encoder set without crtc!\n");
6215 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
6217 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6218 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6220 /* IPS only exists on ULT machines and is tied to pipe A. */
6221 if (!hsw_crtc_supports_ips(crtc))
6224 if (!dev_priv->params.enable_ips)
6227 if (crtc_state->pipe_bpp > 24)
6231 * We compare against max which means we must take
6232 * the increased cdclk requirement into account when
6233 * calculating the new cdclk.
6235 * Should measure whether using a lower cdclk w/o IPS
6237 if (IS_BROADWELL(dev_priv) &&
6238 crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
6244 static int hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
6246 struct drm_i915_private *dev_priv =
6247 to_i915(crtc_state->uapi.crtc->dev);
6248 struct intel_atomic_state *state =
6249 to_intel_atomic_state(crtc_state->uapi.state);
6251 crtc_state->ips_enabled = false;
6253 if (!hsw_crtc_state_ips_capable(crtc_state))
6257 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
6258 * enabled and disabled dynamically based on package C states,
6259 * user space can't make reliable use of the CRCs, so let's just
6260 * completely disable it.
6262 if (crtc_state->crc_enabled)
6265 /* IPS should be fine as long as at least one plane is enabled. */
6266 if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
6269 if (IS_BROADWELL(dev_priv)) {
6270 const struct intel_cdclk_state *cdclk_state;
6272 cdclk_state = intel_atomic_get_cdclk_state(state);
6273 if (IS_ERR(cdclk_state))
6274 return PTR_ERR(cdclk_state);
6276 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
6277 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
6281 crtc_state->ips_enabled = true;
6286 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6288 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6290 /* GDG double wide on either pipe, otherwise pipe A only */
6291 return INTEL_GEN(dev_priv) < 4 &&
6292 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6295 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
6297 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
6298 unsigned int pipe_w, pipe_h, pfit_w, pfit_h;
6301 * We only use IF-ID interlacing. If we ever use
6302 * PF-ID we'll need to adjust the pixel_rate here.
6305 if (!crtc_state->pch_pfit.enabled)
6308 pipe_w = crtc_state->pipe_src_w;
6309 pipe_h = crtc_state->pipe_src_h;
6311 pfit_w = drm_rect_width(&crtc_state->pch_pfit.dst);
6312 pfit_h = drm_rect_height(&crtc_state->pch_pfit.dst);
6314 if (pipe_w < pfit_w)
6316 if (pipe_h < pfit_h)
6319 if (drm_WARN_ON(crtc_state->uapi.crtc->dev,
6320 !pfit_w || !pfit_h))
6323 return div_u64(mul_u32_u32(pixel_rate, pipe_w * pipe_h),
6327 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode,
6328 const struct drm_display_mode *timings)
6330 mode->hdisplay = timings->crtc_hdisplay;
6331 mode->htotal = timings->crtc_htotal;
6332 mode->hsync_start = timings->crtc_hsync_start;
6333 mode->hsync_end = timings->crtc_hsync_end;
6335 mode->vdisplay = timings->crtc_vdisplay;
6336 mode->vtotal = timings->crtc_vtotal;
6337 mode->vsync_start = timings->crtc_vsync_start;
6338 mode->vsync_end = timings->crtc_vsync_end;
6340 mode->flags = timings->flags;
6341 mode->type = DRM_MODE_TYPE_DRIVER;
6343 mode->clock = timings->crtc_clock;
6345 drm_mode_set_name(mode);
6348 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6350 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
6352 if (HAS_GMCH(dev_priv))
6353 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6354 crtc_state->pixel_rate =
6355 crtc_state->hw.pipe_mode.crtc_clock;
6357 crtc_state->pixel_rate =
6358 ilk_pipe_pixel_rate(crtc_state);
6361 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state)
6363 struct drm_display_mode *mode = &crtc_state->hw.mode;
6364 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
6365 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
6367 drm_mode_copy(pipe_mode, adjusted_mode);
6369 if (crtc_state->bigjoiner) {
6371 * transcoder is programmed to the full mode,
6372 * but pipe timings are half of the transcoder mode
6374 pipe_mode->crtc_hdisplay /= 2;
6375 pipe_mode->crtc_hblank_start /= 2;
6376 pipe_mode->crtc_hblank_end /= 2;
6377 pipe_mode->crtc_hsync_start /= 2;
6378 pipe_mode->crtc_hsync_end /= 2;
6379 pipe_mode->crtc_htotal /= 2;
6380 pipe_mode->crtc_clock /= 2;
6383 intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
6384 intel_mode_from_crtc_timings(adjusted_mode, adjusted_mode);
6386 intel_crtc_compute_pixel_rate(crtc_state);
6388 drm_mode_copy(mode, adjusted_mode);
6389 mode->hdisplay = crtc_state->pipe_src_w << crtc_state->bigjoiner;
6390 mode->vdisplay = crtc_state->pipe_src_h;
6393 static void intel_encoder_get_config(struct intel_encoder *encoder,
6394 struct intel_crtc_state *crtc_state)
6396 encoder->get_config(encoder, crtc_state);
6398 intel_crtc_readout_derived_state(crtc_state);
6401 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6402 struct intel_crtc_state *pipe_config)
6404 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6405 struct drm_display_mode *pipe_mode = &pipe_config->hw.pipe_mode;
6406 int clock_limit = dev_priv->max_dotclk_freq;
6408 drm_mode_copy(pipe_mode, &pipe_config->hw.adjusted_mode);
6410 /* Adjust pipe_mode for bigjoiner, with half the horizontal mode */
6411 if (pipe_config->bigjoiner) {
6412 pipe_mode->crtc_clock /= 2;
6413 pipe_mode->crtc_hdisplay /= 2;
6414 pipe_mode->crtc_hblank_start /= 2;
6415 pipe_mode->crtc_hblank_end /= 2;
6416 pipe_mode->crtc_hsync_start /= 2;
6417 pipe_mode->crtc_hsync_end /= 2;
6418 pipe_mode->crtc_htotal /= 2;
6419 pipe_config->pipe_src_w /= 2;
6422 intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
6424 if (INTEL_GEN(dev_priv) < 4) {
6425 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6428 * Enable double wide mode when the dot clock
6429 * is > 90% of the (display) core speed.
6431 if (intel_crtc_supports_double_wide(crtc) &&
6432 pipe_mode->crtc_clock > clock_limit) {
6433 clock_limit = dev_priv->max_dotclk_freq;
6434 pipe_config->double_wide = true;
6438 if (pipe_mode->crtc_clock > clock_limit) {
6439 drm_dbg_kms(&dev_priv->drm,
6440 "requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6441 pipe_mode->crtc_clock, clock_limit,
6442 yesno(pipe_config->double_wide));
6447 * Pipe horizontal size must be even in:
6449 * - LVDS dual channel mode
6450 * - Double wide pipe
6452 if (pipe_config->pipe_src_w & 1) {
6453 if (pipe_config->double_wide) {
6454 drm_dbg_kms(&dev_priv->drm,
6455 "Odd pipe source width not supported with double wide pipe\n");
6459 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6460 intel_is_dual_link_lvds(dev_priv)) {
6461 drm_dbg_kms(&dev_priv->drm,
6462 "Odd pipe source width not supported with dual link LVDS\n");
6467 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6468 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6470 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6471 pipe_mode->crtc_hsync_start == pipe_mode->crtc_hdisplay)
6474 intel_crtc_compute_pixel_rate(pipe_config);
6476 if (pipe_config->has_pch_encoder)
6477 return ilk_fdi_compute_config(crtc, pipe_config);
6483 intel_reduce_m_n_ratio(u32 *num, u32 *den)
6485 while (*num > DATA_LINK_M_N_MASK ||
6486 *den > DATA_LINK_M_N_MASK) {
6492 static void compute_m_n(unsigned int m, unsigned int n,
6493 u32 *ret_m, u32 *ret_n,
6497 * Several DP dongles in particular seem to be fussy about
6498 * too large link M/N values. Give N value as 0x8000 that
6499 * should be acceptable by specific devices. 0x8000 is the
6500 * specified fixed N value for asynchronous clock mode,
6501 * which the devices expect also in synchronous clock mode.
6504 *ret_n = DP_LINK_CONSTANT_N_VALUE;
6506 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6508 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
6509 intel_reduce_m_n_ratio(ret_m, ret_n);
6513 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
6514 int pixel_clock, int link_clock,
6515 struct intel_link_m_n *m_n,
6516 bool constant_n, bool fec_enable)
6518 u32 data_clock = bits_per_pixel * pixel_clock;
6521 data_clock = intel_dp_mode_to_fec_clock(data_clock);
6524 compute_m_n(data_clock,
6525 link_clock * nlanes * 8,
6526 &m_n->gmch_m, &m_n->gmch_n,
6529 compute_m_n(pixel_clock, link_clock,
6530 &m_n->link_m, &m_n->link_n,
6534 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
6537 * There may be no VBT; and if the BIOS enabled SSC we can
6538 * just keep using it to avoid unnecessary flicker. Whereas if the
6539 * BIOS isn't using it, don't assume it will work even if the VBT
6540 * indicates as much.
6542 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
6543 bool bios_lvds_use_ssc = intel_de_read(dev_priv,
6547 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
6548 drm_dbg_kms(&dev_priv->drm,
6549 "SSC %s by BIOS, overriding VBT which says %s\n",
6550 enableddisabled(bios_lvds_use_ssc),
6551 enableddisabled(dev_priv->vbt.lvds_use_ssc));
6552 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
6557 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6563 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6564 * and set it to a reasonable value instead.
6566 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6567 reg_val &= 0xffffff00;
6568 reg_val |= 0x00000030;
6569 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6571 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6572 reg_val &= 0x00ffffff;
6573 reg_val |= 0x8c000000;
6574 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6576 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6577 reg_val &= 0xffffff00;
6578 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6580 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6581 reg_val &= 0x00ffffff;
6582 reg_val |= 0xb0000000;
6583 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6586 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
6587 const struct intel_link_m_n *m_n)
6589 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6590 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6591 enum pipe pipe = crtc->pipe;
6593 intel_de_write(dev_priv, PCH_TRANS_DATA_M1(pipe),
6594 TU_SIZE(m_n->tu) | m_n->gmch_m);
6595 intel_de_write(dev_priv, PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6596 intel_de_write(dev_priv, PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6597 intel_de_write(dev_priv, PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6600 static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
6601 enum transcoder transcoder)
6603 if (IS_HASWELL(dev_priv))
6604 return transcoder == TRANSCODER_EDP;
6607 * Strictly speaking some registers are available before
6608 * gen7, but we only support DRRS on gen7+
6610 return IS_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv);
6613 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
6614 const struct intel_link_m_n *m_n,
6615 const struct intel_link_m_n *m2_n2)
6617 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6618 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6619 enum pipe pipe = crtc->pipe;
6620 enum transcoder transcoder = crtc_state->cpu_transcoder;
6622 if (INTEL_GEN(dev_priv) >= 5) {
6623 intel_de_write(dev_priv, PIPE_DATA_M1(transcoder),
6624 TU_SIZE(m_n->tu) | m_n->gmch_m);
6625 intel_de_write(dev_priv, PIPE_DATA_N1(transcoder),
6627 intel_de_write(dev_priv, PIPE_LINK_M1(transcoder),
6629 intel_de_write(dev_priv, PIPE_LINK_N1(transcoder),
6632 * M2_N2 registers are set only if DRRS is supported
6633 * (to make sure the registers are not unnecessarily accessed).
6635 if (m2_n2 && crtc_state->has_drrs &&
6636 transcoder_has_m2_n2(dev_priv, transcoder)) {
6637 intel_de_write(dev_priv, PIPE_DATA_M2(transcoder),
6638 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6639 intel_de_write(dev_priv, PIPE_DATA_N2(transcoder),
6641 intel_de_write(dev_priv, PIPE_LINK_M2(transcoder),
6643 intel_de_write(dev_priv, PIPE_LINK_N2(transcoder),
6647 intel_de_write(dev_priv, PIPE_DATA_M_G4X(pipe),
6648 TU_SIZE(m_n->tu) | m_n->gmch_m);
6649 intel_de_write(dev_priv, PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6650 intel_de_write(dev_priv, PIPE_LINK_M_G4X(pipe), m_n->link_m);
6651 intel_de_write(dev_priv, PIPE_LINK_N_G4X(pipe), m_n->link_n);
6655 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
6657 const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6658 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
6661 dp_m_n = &crtc_state->dp_m_n;
6662 dp_m2_n2 = &crtc_state->dp_m2_n2;
6663 } else if (m_n == M2_N2) {
6666 * M2_N2 registers are not supported. Hence m2_n2 divider value
6667 * needs to be programmed into M1_N1.
6669 dp_m_n = &crtc_state->dp_m2_n2;
6671 drm_err(&i915->drm, "Unsupported divider value\n");
6675 if (crtc_state->has_pch_encoder)
6676 intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);
6678 intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
6681 static void vlv_prepare_pll(struct intel_crtc *crtc,
6682 const struct intel_crtc_state *pipe_config)
6684 struct drm_device *dev = crtc->base.dev;
6685 struct drm_i915_private *dev_priv = to_i915(dev);
6686 enum pipe pipe = crtc->pipe;
6688 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6689 u32 coreclk, reg_val;
6692 intel_de_write(dev_priv, DPLL(pipe),
6693 pipe_config->dpll_hw_state.dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6695 /* No need to actually set up the DPLL with DSI */
6696 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6699 vlv_dpio_get(dev_priv);
6701 bestn = pipe_config->dpll.n;
6702 bestm1 = pipe_config->dpll.m1;
6703 bestm2 = pipe_config->dpll.m2;
6704 bestp1 = pipe_config->dpll.p1;
6705 bestp2 = pipe_config->dpll.p2;
6707 /* See eDP HDMI DPIO driver vbios notes doc */
6709 /* PLL B needs special handling */
6711 vlv_pllb_recal_opamp(dev_priv, pipe);
6713 /* Set up Tx target for periodic Rcomp update */
6714 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6716 /* Disable target IRef on PLL */
6717 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6718 reg_val &= 0x00ffffff;
6719 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6721 /* Disable fast lock */
6722 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6724 /* Set idtafcrecal before PLL is enabled */
6725 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6726 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6727 mdiv |= ((bestn << DPIO_N_SHIFT));
6728 mdiv |= (1 << DPIO_K_SHIFT);
6731 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6732 * but we don't support that).
6733 * Note: don't use the DAC post divider as it seems unstable.
6735 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6736 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6738 mdiv |= DPIO_ENABLE_CALIBRATION;
6739 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6741 /* Set HBR and RBR LPF coefficients */
6742 if (pipe_config->port_clock == 162000 ||
6743 intel_crtc_has_type(pipe_config, INTEL_OUTPUT_ANALOG) ||
6744 intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
6745 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6748 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6751 if (intel_crtc_has_dp_encoder(pipe_config)) {
6752 /* Use SSC source */
6754 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6757 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6759 } else { /* HDMI or VGA */
6760 /* Use bend source */
6762 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6765 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6769 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6770 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6771 if (intel_crtc_has_dp_encoder(pipe_config))
6772 coreclk |= 0x01000000;
6773 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6775 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6777 vlv_dpio_put(dev_priv);
6780 static void chv_prepare_pll(struct intel_crtc *crtc,
6781 const struct intel_crtc_state *pipe_config)
6783 struct drm_device *dev = crtc->base.dev;
6784 struct drm_i915_private *dev_priv = to_i915(dev);
6785 enum pipe pipe = crtc->pipe;
6786 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6787 u32 loopfilter, tribuf_calcntr;
6788 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6792 /* Enable Refclk and SSC */
6793 intel_de_write(dev_priv, DPLL(pipe),
6794 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6796 /* No need to actually set up the DPLL with DSI */
6797 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6800 bestn = pipe_config->dpll.n;
6801 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6802 bestm1 = pipe_config->dpll.m1;
6803 bestm2 = pipe_config->dpll.m2 >> 22;
6804 bestp1 = pipe_config->dpll.p1;
6805 bestp2 = pipe_config->dpll.p2;
6806 vco = pipe_config->dpll.vco;
6810 vlv_dpio_get(dev_priv);
6812 /* p1 and p2 divider */
6813 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6814 5 << DPIO_CHV_S1_DIV_SHIFT |
6815 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6816 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6817 1 << DPIO_CHV_K_DIV_SHIFT);
6819 /* Feedback post-divider - m2 */
6820 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6822 /* Feedback refclk divider - n and m1 */
6823 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6824 DPIO_CHV_M1_DIV_BY_2 |
6825 1 << DPIO_CHV_N_DIV_SHIFT);
6827 /* M2 fraction division */
6828 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6830 /* M2 fraction division enable */
6831 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6832 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6833 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6835 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6836 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6838 /* Program digital lock detect threshold */
6839 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6840 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6841 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6842 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6844 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6845 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6848 if (vco == 5400000) {
6849 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6850 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6851 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6852 tribuf_calcntr = 0x9;
6853 } else if (vco <= 6200000) {
6854 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6855 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6856 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6857 tribuf_calcntr = 0x9;
6858 } else if (vco <= 6480000) {
6859 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6860 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6861 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6862 tribuf_calcntr = 0x8;
6864 /* Not supported. Apply the same limits as in the max case */
6865 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6866 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6867 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6870 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6872 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6873 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6874 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6875 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6878 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6879 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6882 vlv_dpio_put(dev_priv);
6886 * vlv_force_pll_on - forcibly enable just the PLL
6887 * @dev_priv: i915 private structure
6888 * @pipe: pipe PLL to enable
6889 * @dpll: PLL configuration
6891 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6892 * in cases where we need the PLL enabled even when @pipe is not going to
6895 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6896 const struct dpll *dpll)
6898 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6899 struct intel_crtc_state *pipe_config;
6901 pipe_config = intel_crtc_state_alloc(crtc);
6905 pipe_config->cpu_transcoder = (enum transcoder)pipe;
6906 pipe_config->pixel_multiplier = 1;
6907 pipe_config->dpll = *dpll;
6909 if (IS_CHERRYVIEW(dev_priv)) {
6910 chv_compute_dpll(crtc, pipe_config);
6911 chv_prepare_pll(crtc, pipe_config);
6912 chv_enable_pll(crtc, pipe_config);
6914 vlv_compute_dpll(crtc, pipe_config);
6915 vlv_prepare_pll(crtc, pipe_config);
6916 vlv_enable_pll(crtc, pipe_config);
6925 * vlv_force_pll_off - forcibly disable just the PLL
6926 * @dev_priv: i915 private structure
6927 * @pipe: pipe PLL to disable
6929 * Disable the PLL for @pipe. To be used in cases where we need
6930 * the PLL enabled even when @pipe is not going to be enabled.
6932 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6934 if (IS_CHERRYVIEW(dev_priv))
6935 chv_disable_pll(dev_priv, pipe);
6937 vlv_disable_pll(dev_priv, pipe);
6942 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
6944 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6945 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6946 enum pipe pipe = crtc->pipe;
6947 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
6948 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
6949 u32 crtc_vtotal, crtc_vblank_end;
6952 /* We need to be careful not to changed the adjusted mode, for otherwise
6953 * the hw state checker will get angry at the mismatch. */
6954 crtc_vtotal = adjusted_mode->crtc_vtotal;
6955 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6957 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6958 /* the chip adds 2 halflines automatically */
6960 crtc_vblank_end -= 1;
6962 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
6963 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6965 vsyncshift = adjusted_mode->crtc_hsync_start -
6966 adjusted_mode->crtc_htotal / 2;
6968 vsyncshift += adjusted_mode->crtc_htotal;
6971 if (INTEL_GEN(dev_priv) > 3)
6972 intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder),
6975 intel_de_write(dev_priv, HTOTAL(cpu_transcoder),
6976 (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16));
6977 intel_de_write(dev_priv, HBLANK(cpu_transcoder),
6978 (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
6979 intel_de_write(dev_priv, HSYNC(cpu_transcoder),
6980 (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
6982 intel_de_write(dev_priv, VTOTAL(cpu_transcoder),
6983 (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16));
6984 intel_de_write(dev_priv, VBLANK(cpu_transcoder),
6985 (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16));
6986 intel_de_write(dev_priv, VSYNC(cpu_transcoder),
6987 (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
6989 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6990 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6991 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6993 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
6994 (pipe == PIPE_B || pipe == PIPE_C))
6995 intel_de_write(dev_priv, VTOTAL(pipe),
6996 intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
7000 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
7002 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7003 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7004 enum pipe pipe = crtc->pipe;
7006 /* pipesrc controls the size that is scaled from, which should
7007 * always be the user's requested size.
7009 intel_de_write(dev_priv, PIPESRC(pipe),
7010 ((crtc_state->pipe_src_w - 1) << 16) | (crtc_state->pipe_src_h - 1));
7013 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
7015 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
7016 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
7018 if (IS_GEN(dev_priv, 2))
7021 if (INTEL_GEN(dev_priv) >= 9 ||
7022 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
7023 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW;
7025 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
7028 static void intel_get_transcoder_timings(struct intel_crtc *crtc,
7029 struct intel_crtc_state *pipe_config)
7031 struct drm_device *dev = crtc->base.dev;
7032 struct drm_i915_private *dev_priv = to_i915(dev);
7033 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7036 tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder));
7037 pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7038 pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7040 if (!transcoder_is_dsi(cpu_transcoder)) {
7041 tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder));
7042 pipe_config->hw.adjusted_mode.crtc_hblank_start =
7044 pipe_config->hw.adjusted_mode.crtc_hblank_end =
7045 ((tmp >> 16) & 0xffff) + 1;
7047 tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder));
7048 pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7049 pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7051 tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder));
7052 pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7053 pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7055 if (!transcoder_is_dsi(cpu_transcoder)) {
7056 tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder));
7057 pipe_config->hw.adjusted_mode.crtc_vblank_start =
7059 pipe_config->hw.adjusted_mode.crtc_vblank_end =
7060 ((tmp >> 16) & 0xffff) + 1;
7062 tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder));
7063 pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7064 pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7066 if (intel_pipe_is_interlaced(pipe_config)) {
7067 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7068 pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
7069 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
7073 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7074 struct intel_crtc_state *pipe_config)
7076 struct drm_device *dev = crtc->base.dev;
7077 struct drm_i915_private *dev_priv = to_i915(dev);
7080 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
7081 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7082 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7085 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
7087 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7088 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7093 /* we keep both pipes enabled on 830 */
7094 if (IS_I830(dev_priv))
7095 pipeconf |= intel_de_read(dev_priv, PIPECONF(crtc->pipe)) & PIPECONF_ENABLE;
7097 if (crtc_state->double_wide)
7098 pipeconf |= PIPECONF_DOUBLE_WIDE;
7100 /* only g4x and later have fancy bpc/dither controls */
7101 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7102 IS_CHERRYVIEW(dev_priv)) {
7103 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7104 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
7105 pipeconf |= PIPECONF_DITHER_EN |
7106 PIPECONF_DITHER_TYPE_SP;
7108 switch (crtc_state->pipe_bpp) {
7110 pipeconf |= PIPECONF_6BPC;
7113 pipeconf |= PIPECONF_8BPC;
7116 pipeconf |= PIPECONF_10BPC;
7119 /* Case prevented by intel_choose_pipe_bpp_dither. */
7124 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7125 if (INTEL_GEN(dev_priv) < 4 ||
7126 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
7127 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7129 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7131 pipeconf |= PIPECONF_PROGRESSIVE;
7134 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7135 crtc_state->limited_color_range)
7136 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7138 pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
7140 pipeconf |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
7142 intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf);
7143 intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe));
7146 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
7148 if (IS_I830(dev_priv))
7151 return INTEL_GEN(dev_priv) >= 4 ||
7152 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
7155 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
7157 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7158 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7161 if (!i9xx_has_pfit(dev_priv))
7164 tmp = intel_de_read(dev_priv, PFIT_CONTROL);
7165 if (!(tmp & PFIT_ENABLE))
7168 /* Check whether the pfit is attached to our pipe. */
7169 if (INTEL_GEN(dev_priv) < 4) {
7170 if (crtc->pipe != PIPE_B)
7173 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7177 crtc_state->gmch_pfit.control = tmp;
7178 crtc_state->gmch_pfit.pgm_ratios =
7179 intel_de_read(dev_priv, PFIT_PGM_RATIOS);
7182 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7183 struct intel_crtc_state *pipe_config)
7185 struct drm_device *dev = crtc->base.dev;
7186 struct drm_i915_private *dev_priv = to_i915(dev);
7187 enum pipe pipe = crtc->pipe;
7190 int refclk = 100000;
7192 /* In case of DSI, DPLL will not be used */
7193 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7196 vlv_dpio_get(dev_priv);
7197 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7198 vlv_dpio_put(dev_priv);
7200 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7201 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7202 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7203 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7204 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7206 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7210 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7211 struct intel_initial_plane_config *plane_config)
7213 struct drm_device *dev = crtc->base.dev;
7214 struct drm_i915_private *dev_priv = to_i915(dev);
7215 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
7216 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
7218 u32 val, base, offset;
7219 int fourcc, pixel_format;
7220 unsigned int aligned_height;
7221 struct drm_framebuffer *fb;
7222 struct intel_framebuffer *intel_fb;
7224 if (!plane->get_hw_state(plane, &pipe))
7227 drm_WARN_ON(dev, pipe != crtc->pipe);
7229 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7231 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
7235 fb = &intel_fb->base;
7239 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
7241 if (INTEL_GEN(dev_priv) >= 4) {
7242 if (val & DISPPLANE_TILED) {
7243 plane_config->tiling = I915_TILING_X;
7244 fb->modifier = I915_FORMAT_MOD_X_TILED;
7247 if (val & DISPPLANE_ROTATE_180)
7248 plane_config->rotation = DRM_MODE_ROTATE_180;
7251 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
7252 val & DISPPLANE_MIRROR)
7253 plane_config->rotation |= DRM_MODE_REFLECT_X;
7255 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7256 fourcc = i9xx_format_to_fourcc(pixel_format);
7257 fb->format = drm_format_info(fourcc);
7259 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7260 offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));
7261 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
7262 } else if (INTEL_GEN(dev_priv) >= 4) {
7263 if (plane_config->tiling)
7264 offset = intel_de_read(dev_priv,
7265 DSPTILEOFF(i9xx_plane));
7267 offset = intel_de_read(dev_priv,
7268 DSPLINOFF(i9xx_plane));
7269 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
7271 base = intel_de_read(dev_priv, DSPADDR(i9xx_plane));
7273 plane_config->base = base;
7275 val = intel_de_read(dev_priv, PIPESRC(pipe));
7276 fb->width = ((val >> 16) & 0xfff) + 1;
7277 fb->height = ((val >> 0) & 0xfff) + 1;
7279 val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane));
7280 fb->pitches[0] = val & 0xffffffc0;
7282 aligned_height = intel_fb_align_height(fb, 0, fb->height);
7284 plane_config->size = fb->pitches[0] * aligned_height;
7286 drm_dbg_kms(&dev_priv->drm,
7287 "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7288 crtc->base.name, plane->base.name, fb->width, fb->height,
7289 fb->format->cpp[0] * 8, base, fb->pitches[0],
7290 plane_config->size);
7292 plane_config->fb = intel_fb;
7295 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7296 struct intel_crtc_state *pipe_config)
7298 struct drm_device *dev = crtc->base.dev;
7299 struct drm_i915_private *dev_priv = to_i915(dev);
7300 enum pipe pipe = crtc->pipe;
7301 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7303 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7304 int refclk = 100000;
7306 /* In case of DSI, DPLL will not be used */
7307 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7310 vlv_dpio_get(dev_priv);
7311 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7312 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7313 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7314 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7315 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7316 vlv_dpio_put(dev_priv);
7318 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7319 clock.m2 = (pll_dw0 & 0xff) << 22;
7320 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7321 clock.m2 |= pll_dw2 & 0x3fffff;
7322 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7323 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7324 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7326 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7329 static enum intel_output_format
7330 bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
7332 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7335 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
7337 if (tmp & PIPEMISC_YUV420_ENABLE) {
7338 /* We support 4:2:0 in full blend mode only */
7339 drm_WARN_ON(&dev_priv->drm,
7340 (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0);
7342 return INTEL_OUTPUT_FORMAT_YCBCR420;
7343 } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
7344 return INTEL_OUTPUT_FORMAT_YCBCR444;
7346 return INTEL_OUTPUT_FORMAT_RGB;
7350 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
7352 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7353 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
7354 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7355 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
7358 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
7360 if (tmp & DISPPLANE_GAMMA_ENABLE)
7361 crtc_state->gamma_enable = true;
7363 if (!HAS_GMCH(dev_priv) &&
7364 tmp & DISPPLANE_PIPE_CSC_ENABLE)
7365 crtc_state->csc_enable = true;
7368 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7369 struct intel_crtc_state *pipe_config)
7371 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7372 enum intel_display_power_domain power_domain;
7373 intel_wakeref_t wakeref;
7377 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7378 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
7382 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
7383 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7384 pipe_config->shared_dpll = NULL;
7388 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
7389 if (!(tmp & PIPECONF_ENABLE))
7392 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7393 IS_CHERRYVIEW(dev_priv)) {
7394 switch (tmp & PIPECONF_BPC_MASK) {
7396 pipe_config->pipe_bpp = 18;
7399 pipe_config->pipe_bpp = 24;
7401 case PIPECONF_10BPC:
7402 pipe_config->pipe_bpp = 30;
7409 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7410 (tmp & PIPECONF_COLOR_RANGE_SELECT))
7411 pipe_config->limited_color_range = true;
7413 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
7414 PIPECONF_GAMMA_MODE_SHIFT;
7416 if (IS_CHERRYVIEW(dev_priv))
7417 pipe_config->cgm_mode = intel_de_read(dev_priv,
7418 CGM_PIPE_MODE(crtc->pipe));
7420 i9xx_get_pipe_color_config(pipe_config);
7421 intel_color_get_config(pipe_config);
7423 if (INTEL_GEN(dev_priv) < 4)
7424 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7426 intel_get_transcoder_timings(crtc, pipe_config);
7427 intel_get_pipe_src_size(crtc, pipe_config);
7429 i9xx_get_pfit_config(pipe_config);
7431 if (INTEL_GEN(dev_priv) >= 4) {
7432 /* No way to read it out on pipes B and C */
7433 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7434 tmp = dev_priv->chv_dpll_md[crtc->pipe];
7436 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
7437 pipe_config->pixel_multiplier =
7438 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7439 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7440 pipe_config->dpll_hw_state.dpll_md = tmp;
7441 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7442 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7443 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe));
7444 pipe_config->pixel_multiplier =
7445 ((tmp & SDVO_MULTIPLIER_MASK)
7446 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7448 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7449 * port and will be fixed up in the encoder->get_config
7451 pipe_config->pixel_multiplier = 1;
7453 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv,
7455 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7456 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv,
7458 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv,
7461 /* Mask out read-only status bits. */
7462 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7463 DPLL_PORTC_READY_MASK |
7464 DPLL_PORTB_READY_MASK);
7467 if (IS_CHERRYVIEW(dev_priv))
7468 chv_crtc_clock_get(crtc, pipe_config);
7469 else if (IS_VALLEYVIEW(dev_priv))
7470 vlv_crtc_clock_get(crtc, pipe_config);
7472 i9xx_crtc_clock_get(crtc, pipe_config);
7475 * Normally the dotclock is filled in by the encoder .get_config()
7476 * but in case the pipe is enabled w/o any ports we need a sane
7479 pipe_config->hw.adjusted_mode.crtc_clock =
7480 pipe_config->port_clock / pipe_config->pixel_multiplier;
7485 intel_display_power_put(dev_priv, power_domain, wakeref);
7490 static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
7492 struct intel_encoder *encoder;
7495 bool has_lvds = false;
7496 bool has_cpu_edp = false;
7497 bool has_panel = false;
7498 bool has_ck505 = false;
7499 bool can_ssc = false;
7500 bool using_ssc_source = false;
7502 /* We need to take the global config into account */
7503 for_each_intel_encoder(&dev_priv->drm, encoder) {
7504 switch (encoder->type) {
7505 case INTEL_OUTPUT_LVDS:
7509 case INTEL_OUTPUT_EDP:
7511 if (encoder->port == PORT_A)
7519 if (HAS_PCH_IBX(dev_priv)) {
7520 has_ck505 = dev_priv->vbt.display_clock_mode;
7521 can_ssc = has_ck505;
7527 /* Check if any DPLLs are using the SSC source */
7528 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
7529 u32 temp = intel_de_read(dev_priv, PCH_DPLL(i));
7531 if (!(temp & DPLL_VCO_ENABLE))
7534 if ((temp & PLL_REF_INPUT_MASK) ==
7535 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7536 using_ssc_source = true;
7541 drm_dbg_kms(&dev_priv->drm,
7542 "has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7543 has_panel, has_lvds, has_ck505, using_ssc_source);
7545 /* Ironlake: try to setup display ref clock before DPLL
7546 * enabling. This is only under driver's control after
7547 * PCH B stepping, previous chipset stepping should be
7548 * ignoring this setting.
7550 val = intel_de_read(dev_priv, PCH_DREF_CONTROL);
7552 /* As we must carefully and slowly disable/enable each source in turn,
7553 * compute the final state we want first and check if we need to
7554 * make any changes at all.
7557 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7559 final |= DREF_NONSPREAD_CK505_ENABLE;
7561 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7563 final &= ~DREF_SSC_SOURCE_MASK;
7564 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7565 final &= ~DREF_SSC1_ENABLE;
7568 final |= DREF_SSC_SOURCE_ENABLE;
7570 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7571 final |= DREF_SSC1_ENABLE;
7574 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7575 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7577 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7579 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7580 } else if (using_ssc_source) {
7581 final |= DREF_SSC_SOURCE_ENABLE;
7582 final |= DREF_SSC1_ENABLE;
7588 /* Always enable nonspread source */
7589 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7592 val |= DREF_NONSPREAD_CK505_ENABLE;
7594 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7597 val &= ~DREF_SSC_SOURCE_MASK;
7598 val |= DREF_SSC_SOURCE_ENABLE;
7600 /* SSC must be turned on before enabling the CPU output */
7601 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7602 drm_dbg_kms(&dev_priv->drm, "Using SSC on panel\n");
7603 val |= DREF_SSC1_ENABLE;
7605 val &= ~DREF_SSC1_ENABLE;
7607 /* Get SSC going before enabling the outputs */
7608 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
7609 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
7612 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7614 /* Enable CPU source on CPU attached eDP */
7616 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7617 drm_dbg_kms(&dev_priv->drm,
7618 "Using SSC on eDP\n");
7619 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7621 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7623 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7625 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
7626 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
7629 drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n");
7631 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7633 /* Turn off CPU output */
7634 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7636 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
7637 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
7640 if (!using_ssc_source) {
7641 drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n");
7643 /* Turn off the SSC source */
7644 val &= ~DREF_SSC_SOURCE_MASK;
7645 val |= DREF_SSC_SOURCE_DISABLE;
7648 val &= ~DREF_SSC1_ENABLE;
7650 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
7651 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
7656 BUG_ON(val != final);
7659 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7663 tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
7664 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7665 intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
7667 if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) &
7668 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7669 drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n");
7671 tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
7672 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7673 intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
7675 if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) &
7676 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7677 drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n");
7680 /* WaMPhyProgramming:hsw */
7681 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7685 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7686 tmp &= ~(0xFF << 24);
7687 tmp |= (0x12 << 24);
7688 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7690 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7692 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7694 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7696 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7698 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7699 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7700 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7702 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7703 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7704 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7706 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7709 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7711 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7714 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7716 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7719 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7721 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7724 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7726 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7727 tmp &= ~(0xFF << 16);
7728 tmp |= (0x1C << 16);
7729 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7731 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7732 tmp &= ~(0xFF << 16);
7733 tmp |= (0x1C << 16);
7734 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7736 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7738 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7740 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7742 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7744 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7745 tmp &= ~(0xF << 28);
7747 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7749 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7750 tmp &= ~(0xF << 28);
7752 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7755 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7756 * Programming" based on the parameters passed:
7757 * - Sequence to enable CLKOUT_DP
7758 * - Sequence to enable CLKOUT_DP without spread
7759 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7761 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7762 bool with_spread, bool with_fdi)
7766 if (drm_WARN(&dev_priv->drm, with_fdi && !with_spread,
7767 "FDI requires downspread\n"))
7769 if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) &&
7770 with_fdi, "LP PCH doesn't have FDI\n"))
7773 mutex_lock(&dev_priv->sb_lock);
7775 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7776 tmp &= ~SBI_SSCCTL_DISABLE;
7777 tmp |= SBI_SSCCTL_PATHALT;
7778 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7783 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7784 tmp &= ~SBI_SSCCTL_PATHALT;
7785 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7788 lpt_reset_fdi_mphy(dev_priv);
7789 lpt_program_fdi_mphy(dev_priv);
7793 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7794 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7795 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7796 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7798 mutex_unlock(&dev_priv->sb_lock);
7801 /* Sequence to disable CLKOUT_DP */
7802 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
7806 mutex_lock(&dev_priv->sb_lock);
7808 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7809 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7810 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7811 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7813 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7814 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7815 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7816 tmp |= SBI_SSCCTL_PATHALT;
7817 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7820 tmp |= SBI_SSCCTL_DISABLE;
7821 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7824 mutex_unlock(&dev_priv->sb_lock);
7827 #define BEND_IDX(steps) ((50 + (steps)) / 5)
7829 static const u16 sscdivintphase[] = {
7830 [BEND_IDX( 50)] = 0x3B23,
7831 [BEND_IDX( 45)] = 0x3B23,
7832 [BEND_IDX( 40)] = 0x3C23,
7833 [BEND_IDX( 35)] = 0x3C23,
7834 [BEND_IDX( 30)] = 0x3D23,
7835 [BEND_IDX( 25)] = 0x3D23,
7836 [BEND_IDX( 20)] = 0x3E23,
7837 [BEND_IDX( 15)] = 0x3E23,
7838 [BEND_IDX( 10)] = 0x3F23,
7839 [BEND_IDX( 5)] = 0x3F23,
7840 [BEND_IDX( 0)] = 0x0025,
7841 [BEND_IDX( -5)] = 0x0025,
7842 [BEND_IDX(-10)] = 0x0125,
7843 [BEND_IDX(-15)] = 0x0125,
7844 [BEND_IDX(-20)] = 0x0225,
7845 [BEND_IDX(-25)] = 0x0225,
7846 [BEND_IDX(-30)] = 0x0325,
7847 [BEND_IDX(-35)] = 0x0325,
7848 [BEND_IDX(-40)] = 0x0425,
7849 [BEND_IDX(-45)] = 0x0425,
7850 [BEND_IDX(-50)] = 0x0525,
7855 * steps -50 to 50 inclusive, in steps of 5
7856 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
7857 * change in clock period = -(steps / 10) * 5.787 ps
7859 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
7862 int idx = BEND_IDX(steps);
7864 if (drm_WARN_ON(&dev_priv->drm, steps % 5 != 0))
7867 if (drm_WARN_ON(&dev_priv->drm, idx >= ARRAY_SIZE(sscdivintphase)))
7870 mutex_lock(&dev_priv->sb_lock);
7872 if (steps % 10 != 0)
7876 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
7878 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
7880 tmp |= sscdivintphase[idx];
7881 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
7883 mutex_unlock(&dev_priv->sb_lock);
7888 static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
7890 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
7891 u32 ctl = intel_de_read(dev_priv, SPLL_CTL);
7893 if ((ctl & SPLL_PLL_ENABLE) == 0)
7896 if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC &&
7897 (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
7900 if (IS_BROADWELL(dev_priv) &&
7901 (ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW)
7907 static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
7908 enum intel_dpll_id id)
7910 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
7911 u32 ctl = intel_de_read(dev_priv, WRPLL_CTL(id));
7913 if ((ctl & WRPLL_PLL_ENABLE) == 0)
7916 if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
7919 if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
7920 (ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW &&
7921 (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
7927 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
7929 struct intel_encoder *encoder;
7930 bool has_fdi = false;
7932 for_each_intel_encoder(&dev_priv->drm, encoder) {
7933 switch (encoder->type) {
7934 case INTEL_OUTPUT_ANALOG:
7943 * The BIOS may have decided to use the PCH SSC
7944 * reference so we must not disable it until the
7945 * relevant PLLs have stopped relying on it. We'll
7946 * just leave the PCH SSC reference enabled in case
7947 * any active PLL is using it. It will get disabled
7948 * after runtime suspend if we don't have FDI.
7950 * TODO: Move the whole reference clock handling
7951 * to the modeset sequence proper so that we can
7952 * actually enable/disable/reconfigure these things
7953 * safely. To do that we need to introduce a real
7954 * clock hierarchy. That would also allow us to do
7955 * clock bending finally.
7957 dev_priv->pch_ssc_use = 0;
7959 if (spll_uses_pch_ssc(dev_priv)) {
7960 drm_dbg_kms(&dev_priv->drm, "SPLL using PCH SSC\n");
7961 dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
7964 if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
7965 drm_dbg_kms(&dev_priv->drm, "WRPLL1 using PCH SSC\n");
7966 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
7969 if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
7970 drm_dbg_kms(&dev_priv->drm, "WRPLL2 using PCH SSC\n");
7971 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
7974 if (dev_priv->pch_ssc_use)
7978 lpt_bend_clkout_dp(dev_priv, 0);
7979 lpt_enable_clkout_dp(dev_priv, true, true);
7981 lpt_disable_clkout_dp(dev_priv);
7986 * Initialize reference clocks when the driver loads
7988 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
7990 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
7991 ilk_init_pch_refclk(dev_priv);
7992 else if (HAS_PCH_LPT(dev_priv))
7993 lpt_init_pch_refclk(dev_priv);
7996 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
7998 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7999 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8000 enum pipe pipe = crtc->pipe;
8005 switch (crtc_state->pipe_bpp) {
8007 val |= PIPECONF_6BPC;
8010 val |= PIPECONF_8BPC;
8013 val |= PIPECONF_10BPC;
8016 val |= PIPECONF_12BPC;
8019 /* Case prevented by intel_choose_pipe_bpp_dither. */
8023 if (crtc_state->dither)
8024 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8026 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8027 val |= PIPECONF_INTERLACED_ILK;
8029 val |= PIPECONF_PROGRESSIVE;
8032 * This would end up with an odd purple hue over
8033 * the entire display. Make sure we don't do it.
8035 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
8036 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
8038 if (crtc_state->limited_color_range &&
8039 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
8040 val |= PIPECONF_COLOR_RANGE_SELECT;
8042 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
8043 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
8045 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
8047 val |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
8049 intel_de_write(dev_priv, PIPECONF(pipe), val);
8050 intel_de_posting_read(dev_priv, PIPECONF(pipe));
8053 static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state)
8055 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8056 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8057 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8060 if (IS_HASWELL(dev_priv) && crtc_state->dither)
8061 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8063 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8064 val |= PIPECONF_INTERLACED_ILK;
8066 val |= PIPECONF_PROGRESSIVE;
8068 if (IS_HASWELL(dev_priv) &&
8069 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
8070 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
8072 intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val);
8073 intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder));
8076 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
8078 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8079 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8082 switch (crtc_state->pipe_bpp) {
8084 val |= PIPEMISC_DITHER_6_BPC;
8087 val |= PIPEMISC_DITHER_8_BPC;
8090 val |= PIPEMISC_DITHER_10_BPC;
8093 val |= PIPEMISC_DITHER_12_BPC;
8096 MISSING_CASE(crtc_state->pipe_bpp);
8100 if (crtc_state->dither)
8101 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8103 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
8104 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
8105 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
8107 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
8108 val |= PIPEMISC_YUV420_ENABLE |
8109 PIPEMISC_YUV420_MODE_FULL_BLEND;
8111 if (INTEL_GEN(dev_priv) >= 11 &&
8112 (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
8113 BIT(PLANE_CURSOR))) == 0)
8114 val |= PIPEMISC_HDR_MODE_PRECISION;
8116 if (INTEL_GEN(dev_priv) >= 12)
8117 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC;
8119 intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val);
8122 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
8124 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8127 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
8129 switch (tmp & PIPEMISC_DITHER_BPC_MASK) {
8130 case PIPEMISC_DITHER_6_BPC:
8132 case PIPEMISC_DITHER_8_BPC:
8134 case PIPEMISC_DITHER_10_BPC:
8136 case PIPEMISC_DITHER_12_BPC:
8144 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
8147 * Account for spread spectrum to avoid
8148 * oversubscribing the link. Max center spread
8149 * is 2.5%; use 5% for safety's sake.
8151 u32 bps = target_clock * bpp * 21 / 20;
8152 return DIV_ROUND_UP(bps, link_bw * 8);
8155 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8156 struct intel_link_m_n *m_n)
8158 struct drm_device *dev = crtc->base.dev;
8159 struct drm_i915_private *dev_priv = to_i915(dev);
8160 enum pipe pipe = crtc->pipe;
8162 m_n->link_m = intel_de_read(dev_priv, PCH_TRANS_LINK_M1(pipe));
8163 m_n->link_n = intel_de_read(dev_priv, PCH_TRANS_LINK_N1(pipe));
8164 m_n->gmch_m = intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
8166 m_n->gmch_n = intel_de_read(dev_priv, PCH_TRANS_DATA_N1(pipe));
8167 m_n->tu = ((intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
8168 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8171 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8172 enum transcoder transcoder,
8173 struct intel_link_m_n *m_n,
8174 struct intel_link_m_n *m2_n2)
8176 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8177 enum pipe pipe = crtc->pipe;
8179 if (INTEL_GEN(dev_priv) >= 5) {
8180 m_n->link_m = intel_de_read(dev_priv,
8181 PIPE_LINK_M1(transcoder));
8182 m_n->link_n = intel_de_read(dev_priv,
8183 PIPE_LINK_N1(transcoder));
8184 m_n->gmch_m = intel_de_read(dev_priv,
8185 PIPE_DATA_M1(transcoder))
8187 m_n->gmch_n = intel_de_read(dev_priv,
8188 PIPE_DATA_N1(transcoder));
8189 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M1(transcoder))
8190 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8192 if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
8193 m2_n2->link_m = intel_de_read(dev_priv,
8194 PIPE_LINK_M2(transcoder));
8195 m2_n2->link_n = intel_de_read(dev_priv,
8196 PIPE_LINK_N2(transcoder));
8197 m2_n2->gmch_m = intel_de_read(dev_priv,
8198 PIPE_DATA_M2(transcoder))
8200 m2_n2->gmch_n = intel_de_read(dev_priv,
8201 PIPE_DATA_N2(transcoder));
8202 m2_n2->tu = ((intel_de_read(dev_priv, PIPE_DATA_M2(transcoder))
8203 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8206 m_n->link_m = intel_de_read(dev_priv, PIPE_LINK_M_G4X(pipe));
8207 m_n->link_n = intel_de_read(dev_priv, PIPE_LINK_N_G4X(pipe));
8208 m_n->gmch_m = intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
8210 m_n->gmch_n = intel_de_read(dev_priv, PIPE_DATA_N_G4X(pipe));
8211 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
8212 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8216 void intel_dp_get_m_n(struct intel_crtc *crtc,
8217 struct intel_crtc_state *pipe_config)
8219 if (pipe_config->has_pch_encoder)
8220 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8222 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8223 &pipe_config->dp_m_n,
8224 &pipe_config->dp_m2_n2);
8227 static void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
8228 struct intel_crtc_state *pipe_config)
8230 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8231 &pipe_config->fdi_m_n, NULL);
8234 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state,
8237 drm_rect_init(&crtc_state->pch_pfit.dst,
8238 pos >> 16, pos & 0xffff,
8239 size >> 16, size & 0xffff);
8242 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state)
8244 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8245 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8246 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
8250 /* find scaler attached to this pipe */
8251 for (i = 0; i < crtc->num_scalers; i++) {
8254 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
8255 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)
8259 crtc_state->pch_pfit.enabled = true;
8261 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i));
8262 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
8264 ilk_get_pfit_pos_size(crtc_state, pos, size);
8266 scaler_state->scalers[i].in_use = true;
8270 scaler_state->scaler_id = id;
8272 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8274 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8278 skl_get_initial_plane_config(struct intel_crtc *crtc,
8279 struct intel_initial_plane_config *plane_config)
8281 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
8282 struct drm_device *dev = crtc->base.dev;
8283 struct drm_i915_private *dev_priv = to_i915(dev);
8284 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8285 enum plane_id plane_id = plane->id;
8287 u32 val, base, offset, stride_mult, tiling, alpha;
8288 int fourcc, pixel_format;
8289 unsigned int aligned_height;
8290 struct drm_framebuffer *fb;
8291 struct intel_framebuffer *intel_fb;
8293 if (!plane->get_hw_state(plane, &pipe))
8296 drm_WARN_ON(dev, pipe != crtc->pipe);
8298 if (crtc_state->bigjoiner) {
8299 drm_dbg_kms(&dev_priv->drm,
8300 "Unsupported bigjoiner configuration for initial FB\n");
8304 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8306 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
8310 fb = &intel_fb->base;
8314 val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id));
8316 if (INTEL_GEN(dev_priv) >= 11)
8317 pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
8319 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8321 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
8322 alpha = intel_de_read(dev_priv,
8323 PLANE_COLOR_CTL(pipe, plane_id));
8324 alpha &= PLANE_COLOR_ALPHA_MASK;
8326 alpha = val & PLANE_CTL_ALPHA_MASK;
8329 fourcc = skl_format_to_fourcc(pixel_format,
8330 val & PLANE_CTL_ORDER_RGBX, alpha);
8331 fb->format = drm_format_info(fourcc);
8333 tiling = val & PLANE_CTL_TILED_MASK;
8335 case PLANE_CTL_TILED_LINEAR:
8336 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8338 case PLANE_CTL_TILED_X:
8339 plane_config->tiling = I915_TILING_X;
8340 fb->modifier = I915_FORMAT_MOD_X_TILED;
8342 case PLANE_CTL_TILED_Y:
8343 plane_config->tiling = I915_TILING_Y;
8344 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
8345 fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
8346 I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
8347 I915_FORMAT_MOD_Y_TILED_CCS;
8348 else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
8349 fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
8351 fb->modifier = I915_FORMAT_MOD_Y_TILED;
8353 case PLANE_CTL_TILED_YF:
8354 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
8355 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
8357 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8360 MISSING_CASE(tiling);
8365 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
8366 * while i915 HW rotation is clockwise, thats why this swapping.
8368 switch (val & PLANE_CTL_ROTATE_MASK) {
8369 case PLANE_CTL_ROTATE_0:
8370 plane_config->rotation = DRM_MODE_ROTATE_0;
8372 case PLANE_CTL_ROTATE_90:
8373 plane_config->rotation = DRM_MODE_ROTATE_270;
8375 case PLANE_CTL_ROTATE_180:
8376 plane_config->rotation = DRM_MODE_ROTATE_180;
8378 case PLANE_CTL_ROTATE_270:
8379 plane_config->rotation = DRM_MODE_ROTATE_90;
8383 if (INTEL_GEN(dev_priv) >= 10 &&
8384 val & PLANE_CTL_FLIP_HORIZONTAL)
8385 plane_config->rotation |= DRM_MODE_REFLECT_X;
8387 /* 90/270 degree rotation would require extra work */
8388 if (drm_rotation_90_or_270(plane_config->rotation))
8391 base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xfffff000;
8392 plane_config->base = base;
8394 offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id));
8396 val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id));
8397 fb->height = ((val >> 16) & 0xffff) + 1;
8398 fb->width = ((val >> 0) & 0xffff) + 1;
8400 val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
8401 stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
8402 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8404 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8406 plane_config->size = fb->pitches[0] * aligned_height;
8408 drm_dbg_kms(&dev_priv->drm,
8409 "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8410 crtc->base.name, plane->base.name, fb->width, fb->height,
8411 fb->format->cpp[0] * 8, base, fb->pitches[0],
8412 plane_config->size);
8414 plane_config->fb = intel_fb;
8421 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
8423 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8424 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8427 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
8428 if ((ctl & PF_ENABLE) == 0)
8431 crtc_state->pch_pfit.enabled = true;
8433 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
8434 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
8436 ilk_get_pfit_pos_size(crtc_state, pos, size);
8439 * We currently do not free assignements of panel fitters on
8440 * ivb/hsw (since we don't use the higher upscaling modes which
8441 * differentiates them) so just WARN about this case for now.
8443 drm_WARN_ON(&dev_priv->drm, IS_GEN(dev_priv, 7) &&
8444 (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe));
8447 static bool ilk_get_pipe_config(struct intel_crtc *crtc,
8448 struct intel_crtc_state *pipe_config)
8450 struct drm_device *dev = crtc->base.dev;
8451 struct drm_i915_private *dev_priv = to_i915(dev);
8452 enum intel_display_power_domain power_domain;
8453 intel_wakeref_t wakeref;
8457 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8458 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
8462 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8463 pipe_config->shared_dpll = NULL;
8466 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
8467 if (!(tmp & PIPECONF_ENABLE))
8470 switch (tmp & PIPECONF_BPC_MASK) {
8472 pipe_config->pipe_bpp = 18;
8475 pipe_config->pipe_bpp = 24;
8477 case PIPECONF_10BPC:
8478 pipe_config->pipe_bpp = 30;
8480 case PIPECONF_12BPC:
8481 pipe_config->pipe_bpp = 36;
8487 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8488 pipe_config->limited_color_range = true;
8490 switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
8491 case PIPECONF_OUTPUT_COLORSPACE_YUV601:
8492 case PIPECONF_OUTPUT_COLORSPACE_YUV709:
8493 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
8496 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
8500 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
8501 PIPECONF_GAMMA_MODE_SHIFT;
8503 pipe_config->csc_mode = intel_de_read(dev_priv,
8504 PIPE_CSC_MODE(crtc->pipe));
8506 i9xx_get_pipe_color_config(pipe_config);
8507 intel_color_get_config(pipe_config);
8509 if (intel_de_read(dev_priv, PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8510 struct intel_shared_dpll *pll;
8511 enum intel_dpll_id pll_id;
8514 pipe_config->has_pch_encoder = true;
8516 tmp = intel_de_read(dev_priv, FDI_RX_CTL(crtc->pipe));
8517 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8518 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8520 ilk_get_fdi_m_n_config(crtc, pipe_config);
8522 if (HAS_PCH_IBX(dev_priv)) {
8524 * The pipe->pch transcoder and pch transcoder->pll
8527 pll_id = (enum intel_dpll_id) crtc->pipe;
8529 tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
8530 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8531 pll_id = DPLL_ID_PCH_PLL_B;
8533 pll_id= DPLL_ID_PCH_PLL_A;
8536 pipe_config->shared_dpll =
8537 intel_get_shared_dpll_by_id(dev_priv, pll_id);
8538 pll = pipe_config->shared_dpll;
8540 pll_active = intel_dpll_get_hw_state(dev_priv, pll,
8541 &pipe_config->dpll_hw_state);
8542 drm_WARN_ON(dev, !pll_active);
8544 tmp = pipe_config->dpll_hw_state.dpll;
8545 pipe_config->pixel_multiplier =
8546 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8547 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8549 ilk_pch_clock_get(crtc, pipe_config);
8551 pipe_config->pixel_multiplier = 1;
8554 intel_get_transcoder_timings(crtc, pipe_config);
8555 intel_get_pipe_src_size(crtc, pipe_config);
8557 ilk_get_pfit_config(pipe_config);
8562 intel_display_power_put(dev_priv, power_domain, wakeref);
8567 static void dg1_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
8568 struct intel_crtc_state *pipe_config)
8570 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
8571 enum phy phy = intel_port_to_phy(dev_priv, port);
8572 struct icl_port_dpll *port_dpll;
8573 struct intel_shared_dpll *pll;
8574 enum intel_dpll_id id;
8578 clk_sel = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy)) & DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
8579 id = DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_DPLL_MAP(clk_sel, phy);
8581 if (WARN_ON(id > DPLL_ID_DG1_DPLL3))
8584 pll = intel_get_shared_dpll_by_id(dev_priv, id);
8585 port_dpll = &pipe_config->icl_port_dplls[port_dpll_id];
8587 port_dpll->pll = pll;
8588 pll_active = intel_dpll_get_hw_state(dev_priv, pll,
8589 &port_dpll->hw_state);
8590 drm_WARN_ON(&dev_priv->drm, !pll_active);
8592 icl_set_active_port_dpll(pipe_config, port_dpll_id);
8595 static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
8596 struct intel_crtc_state *pipe_config)
8598 enum phy phy = intel_port_to_phy(dev_priv, port);
8599 enum icl_port_dpll_id port_dpll_id;
8600 struct icl_port_dpll *port_dpll;
8601 struct intel_shared_dpll *pll;
8602 enum intel_dpll_id id;
8606 if (intel_phy_is_combo(dev_priv, phy)) {
8609 if (IS_ROCKETLAKE(dev_priv)) {
8610 mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
8611 shift = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
8613 mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
8614 shift = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
8617 temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & mask;
8619 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
8620 } else if (intel_phy_is_tc(dev_priv, phy)) {
8621 u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
8623 if (clk_sel == DDI_CLK_SEL_MG) {
8624 id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
8626 port_dpll_id = ICL_PORT_DPLL_MG_PHY;
8628 drm_WARN_ON(&dev_priv->drm,
8629 clk_sel < DDI_CLK_SEL_TBT_162);
8630 id = DPLL_ID_ICL_TBTPLL;
8631 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
8634 drm_WARN(&dev_priv->drm, 1, "Invalid port %x\n", port);
8638 pll = intel_get_shared_dpll_by_id(dev_priv, id);
8639 port_dpll = &pipe_config->icl_port_dplls[port_dpll_id];
8641 port_dpll->pll = pll;
8642 pll_active = intel_dpll_get_hw_state(dev_priv, pll,
8643 &port_dpll->hw_state);
8644 drm_WARN_ON(&dev_priv->drm, !pll_active);
8646 icl_set_active_port_dpll(pipe_config, port_dpll_id);
8649 static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
8650 struct intel_crtc_state *pipe_config)
8652 struct intel_shared_dpll *pll;
8653 enum intel_dpll_id id;
8657 temp = intel_de_read(dev_priv, DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
8658 id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
8660 if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL2))
8663 pll = intel_get_shared_dpll_by_id(dev_priv, id);
8665 pipe_config->shared_dpll = pll;
8666 pll_active = intel_dpll_get_hw_state(dev_priv, pll,
8667 &pipe_config->dpll_hw_state);
8668 drm_WARN_ON(&dev_priv->drm, !pll_active);
8671 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
8673 struct intel_crtc_state *pipe_config)
8675 struct intel_shared_dpll *pll;
8676 enum intel_dpll_id id;
8681 id = DPLL_ID_SKL_DPLL0;
8684 id = DPLL_ID_SKL_DPLL1;
8687 id = DPLL_ID_SKL_DPLL2;
8690 drm_err(&dev_priv->drm, "Incorrect port type\n");
8694 pll = intel_get_shared_dpll_by_id(dev_priv, id);
8696 pipe_config->shared_dpll = pll;
8697 pll_active = intel_dpll_get_hw_state(dev_priv, pll,
8698 &pipe_config->dpll_hw_state);
8699 drm_WARN_ON(&dev_priv->drm, !pll_active);
8702 static void skl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
8703 struct intel_crtc_state *pipe_config)
8705 struct intel_shared_dpll *pll;
8706 enum intel_dpll_id id;
8710 temp = intel_de_read(dev_priv, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8711 id = temp >> (port * 3 + 1);
8713 if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL3))
8716 pll = intel_get_shared_dpll_by_id(dev_priv, id);
8718 pipe_config->shared_dpll = pll;
8719 pll_active = intel_dpll_get_hw_state(dev_priv, pll,
8720 &pipe_config->dpll_hw_state);
8721 drm_WARN_ON(&dev_priv->drm, !pll_active);
8724 static void hsw_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
8725 struct intel_crtc_state *pipe_config)
8727 struct intel_shared_dpll *pll;
8728 enum intel_dpll_id id;
8729 u32 ddi_pll_sel = intel_de_read(dev_priv, PORT_CLK_SEL(port));
8732 switch (ddi_pll_sel) {
8733 case PORT_CLK_SEL_WRPLL1:
8734 id = DPLL_ID_WRPLL1;
8736 case PORT_CLK_SEL_WRPLL2:
8737 id = DPLL_ID_WRPLL2;
8739 case PORT_CLK_SEL_SPLL:
8742 case PORT_CLK_SEL_LCPLL_810:
8743 id = DPLL_ID_LCPLL_810;
8745 case PORT_CLK_SEL_LCPLL_1350:
8746 id = DPLL_ID_LCPLL_1350;
8748 case PORT_CLK_SEL_LCPLL_2700:
8749 id = DPLL_ID_LCPLL_2700;
8752 MISSING_CASE(ddi_pll_sel);
8754 case PORT_CLK_SEL_NONE:
8758 pll = intel_get_shared_dpll_by_id(dev_priv, id);
8760 pipe_config->shared_dpll = pll;
8761 pll_active = intel_dpll_get_hw_state(dev_priv, pll,
8762 &pipe_config->dpll_hw_state);
8763 drm_WARN_ON(&dev_priv->drm, !pll_active);
8766 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
8767 struct intel_crtc_state *pipe_config,
8768 struct intel_display_power_domain_set *power_domain_set)
8770 struct drm_device *dev = crtc->base.dev;
8771 struct drm_i915_private *dev_priv = to_i915(dev);
8772 unsigned long panel_transcoder_mask = BIT(TRANSCODER_EDP);
8773 unsigned long enabled_panel_transcoders = 0;
8774 enum transcoder panel_transcoder;
8777 if (INTEL_GEN(dev_priv) >= 11)
8778 panel_transcoder_mask |=
8779 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
8782 * The pipe->transcoder mapping is fixed with the exception of the eDP
8783 * and DSI transcoders handled below.
8785 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8788 * XXX: Do intel_display_power_get_if_enabled before reading this (for
8789 * consistency and less surprising code; it's in always on power).
8791 for_each_cpu_transcoder_masked(dev_priv, panel_transcoder,
8792 panel_transcoder_mask) {
8793 bool force_thru = false;
8794 enum pipe trans_pipe;
8796 tmp = intel_de_read(dev_priv,
8797 TRANS_DDI_FUNC_CTL(panel_transcoder));
8798 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
8802 * Log all enabled ones, only use the first one.
8804 * FIXME: This won't work for two separate DSI displays.
8806 enabled_panel_transcoders |= BIT(panel_transcoder);
8807 if (enabled_panel_transcoders != BIT(panel_transcoder))
8810 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8813 "unknown pipe linked to transcoder %s\n",
8814 transcoder_name(panel_transcoder));
8816 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8819 case TRANS_DDI_EDP_INPUT_A_ON:
8820 trans_pipe = PIPE_A;
8822 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8823 trans_pipe = PIPE_B;
8825 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8826 trans_pipe = PIPE_C;
8828 case TRANS_DDI_EDP_INPUT_D_ONOFF:
8829 trans_pipe = PIPE_D;
8833 if (trans_pipe == crtc->pipe) {
8834 pipe_config->cpu_transcoder = panel_transcoder;
8835 pipe_config->pch_pfit.force_thru = force_thru;
8840 * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1
8842 drm_WARN_ON(dev, (enabled_panel_transcoders & BIT(TRANSCODER_EDP)) &&
8843 enabled_panel_transcoders != BIT(TRANSCODER_EDP));
8845 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
8846 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8849 tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder));
8851 return tmp & PIPECONF_ENABLE;
8854 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
8855 struct intel_crtc_state *pipe_config,
8856 struct intel_display_power_domain_set *power_domain_set)
8858 struct drm_device *dev = crtc->base.dev;
8859 struct drm_i915_private *dev_priv = to_i915(dev);
8860 enum transcoder cpu_transcoder;
8864 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
8866 cpu_transcoder = TRANSCODER_DSI_A;
8868 cpu_transcoder = TRANSCODER_DSI_C;
8870 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
8871 POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
8875 * The PLL needs to be enabled with a valid divider
8876 * configuration, otherwise accessing DSI registers will hang
8877 * the machine. See BSpec North Display Engine
8878 * registers/MIPI[BXT]. We can break out here early, since we
8879 * need the same DSI PLL to be enabled for both DSI ports.
8881 if (!bxt_dsi_pll_is_enabled(dev_priv))
8884 /* XXX: this works for video mode only */
8885 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
8886 if (!(tmp & DPI_ENABLE))
8889 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
8890 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
8893 pipe_config->cpu_transcoder = cpu_transcoder;
8897 return transcoder_is_dsi(pipe_config->cpu_transcoder);
8900 static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
8901 struct intel_crtc_state *pipe_config)
8903 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8904 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8908 if (transcoder_is_dsi(cpu_transcoder)) {
8909 port = (cpu_transcoder == TRANSCODER_DSI_A) ?
8912 tmp = intel_de_read(dev_priv,
8913 TRANS_DDI_FUNC_CTL(cpu_transcoder));
8914 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
8916 if (INTEL_GEN(dev_priv) >= 12)
8917 port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
8919 port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
8922 if (IS_DG1(dev_priv))
8923 dg1_get_ddi_pll(dev_priv, port, pipe_config);
8924 else if (INTEL_GEN(dev_priv) >= 11)
8925 icl_get_ddi_pll(dev_priv, port, pipe_config);
8926 else if (IS_CANNONLAKE(dev_priv))
8927 cnl_get_ddi_pll(dev_priv, port, pipe_config);
8928 else if (IS_GEN9_LP(dev_priv))
8929 bxt_get_ddi_pll(dev_priv, port, pipe_config);
8930 else if (IS_GEN9_BC(dev_priv))
8931 skl_get_ddi_pll(dev_priv, port, pipe_config);
8933 hsw_get_ddi_pll(dev_priv, port, pipe_config);
8936 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8937 * DDI E. So just check whether this pipe is wired to DDI E and whether
8938 * the PCH transcoder is on.
8940 if (INTEL_GEN(dev_priv) < 9 &&
8941 (port == PORT_E) && intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) {
8942 pipe_config->has_pch_encoder = true;
8944 tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
8945 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8946 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8948 ilk_get_fdi_m_n_config(crtc, pipe_config);
8952 static bool hsw_get_pipe_config(struct intel_crtc *crtc,
8953 struct intel_crtc_state *pipe_config)
8955 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8956 struct intel_display_power_domain_set power_domain_set = { };
8960 if (!intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set,
8961 POWER_DOMAIN_PIPE(crtc->pipe)))
8964 pipe_config->shared_dpll = NULL;
8966 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_set);
8968 if (IS_GEN9_LP(dev_priv) &&
8969 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_set)) {
8970 drm_WARN_ON(&dev_priv->drm, active);
8974 intel_dsc_get_config(pipe_config);
8977 /* bigjoiner slave doesn't enable transcoder */
8978 if (!pipe_config->bigjoiner_slave)
8982 pipe_config->pixel_multiplier = 1;
8984 /* we cannot read out most state, so don't bother.. */
8985 pipe_config->quirks |= PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE;
8986 } else if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
8987 INTEL_GEN(dev_priv) >= 11) {
8988 hsw_get_ddi_port_state(crtc, pipe_config);
8989 intel_get_transcoder_timings(crtc, pipe_config);
8992 if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder))
8993 intel_vrr_get_config(crtc, pipe_config);
8995 intel_get_pipe_src_size(crtc, pipe_config);
8997 if (IS_HASWELL(dev_priv)) {
8998 u32 tmp = intel_de_read(dev_priv,
8999 PIPECONF(pipe_config->cpu_transcoder));
9001 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
9002 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
9004 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
9006 pipe_config->output_format =
9007 bdw_get_pipemisc_output_format(crtc);
9010 pipe_config->gamma_mode = intel_de_read(dev_priv,
9011 GAMMA_MODE(crtc->pipe));
9013 pipe_config->csc_mode = intel_de_read(dev_priv,
9014 PIPE_CSC_MODE(crtc->pipe));
9016 if (INTEL_GEN(dev_priv) >= 9) {
9017 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe));
9019 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
9020 pipe_config->gamma_enable = true;
9022 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
9023 pipe_config->csc_enable = true;
9025 i9xx_get_pipe_color_config(pipe_config);
9028 intel_color_get_config(pipe_config);
9030 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));
9031 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
9032 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
9033 pipe_config->ips_linetime =
9034 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
9036 if (intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set,
9037 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {
9038 if (INTEL_GEN(dev_priv) >= 9)
9039 skl_get_pfit_config(pipe_config);
9041 ilk_get_pfit_config(pipe_config);
9044 if (hsw_crtc_supports_ips(crtc)) {
9045 if (IS_HASWELL(dev_priv))
9046 pipe_config->ips_enabled = intel_de_read(dev_priv,
9047 IPS_CTL) & IPS_ENABLE;
9050 * We cannot readout IPS state on broadwell, set to
9051 * true so we can set it to a defined state on first
9054 pipe_config->ips_enabled = true;
9058 if (pipe_config->bigjoiner_slave) {
9059 /* Cannot be read out as a slave, set to 0. */
9060 pipe_config->pixel_multiplier = 0;
9061 } else if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9062 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9063 pipe_config->pixel_multiplier =
9064 intel_de_read(dev_priv,
9065 PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9067 pipe_config->pixel_multiplier = 1;
9071 intel_display_power_put_all_in_set(dev_priv, &power_domain_set);
9076 static bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
9078 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9079 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
9081 if (!i915->display.get_pipe_config(crtc, crtc_state))
9084 crtc_state->hw.active = true;
9086 intel_crtc_readout_derived_state(crtc_state);
9091 /* VESA 640x480x72Hz mode to set on the pipe */
9092 static const struct drm_display_mode load_detect_mode = {
9093 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9094 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9097 struct drm_framebuffer *
9098 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9099 struct drm_mode_fb_cmd2 *mode_cmd)
9101 struct intel_framebuffer *intel_fb;
9104 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9106 return ERR_PTR(-ENOMEM);
9108 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9112 return &intel_fb->base;
9116 return ERR_PTR(ret);
9119 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
9120 struct drm_crtc *crtc)
9122 struct drm_plane *plane;
9123 struct drm_plane_state *plane_state;
9126 ret = drm_atomic_add_affected_planes(state, crtc);
9130 for_each_new_plane_in_state(state, plane, plane_state, i) {
9131 if (plane_state->crtc != crtc)
9134 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
9138 drm_atomic_set_fb_for_plane(plane_state, NULL);
9144 int intel_get_load_detect_pipe(struct drm_connector *connector,
9145 struct intel_load_detect_pipe *old,
9146 struct drm_modeset_acquire_ctx *ctx)
9148 struct intel_crtc *intel_crtc;
9149 struct intel_encoder *intel_encoder =
9150 intel_attached_encoder(to_intel_connector(connector));
9151 struct drm_crtc *possible_crtc;
9152 struct drm_encoder *encoder = &intel_encoder->base;
9153 struct drm_crtc *crtc = NULL;
9154 struct drm_device *dev = encoder->dev;
9155 struct drm_i915_private *dev_priv = to_i915(dev);
9156 struct drm_mode_config *config = &dev->mode_config;
9157 struct drm_atomic_state *state = NULL, *restore_state = NULL;
9158 struct drm_connector_state *connector_state;
9159 struct intel_crtc_state *crtc_state;
9162 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9163 connector->base.id, connector->name,
9164 encoder->base.id, encoder->name);
9166 old->restore_state = NULL;
9168 drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex));
9171 * Algorithm gets a little messy:
9173 * - if the connector already has an assigned crtc, use it (but make
9174 * sure it's on first)
9176 * - try to find the first unused crtc that can drive this connector,
9177 * and use that if we find one
9180 /* See if we already have a CRTC for this connector */
9181 if (connector->state->crtc) {
9182 crtc = connector->state->crtc;
9184 ret = drm_modeset_lock(&crtc->mutex, ctx);
9188 /* Make sure the crtc and connector are running */
9192 /* Find an unused one (if possible) */
9193 for_each_crtc(dev, possible_crtc) {
9195 if (!(encoder->possible_crtcs & (1 << i)))
9198 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9202 if (possible_crtc->state->enable) {
9203 drm_modeset_unlock(&possible_crtc->mutex);
9207 crtc = possible_crtc;
9212 * If we didn't find an unused CRTC, don't use any.
9215 drm_dbg_kms(&dev_priv->drm,
9216 "no pipe available for load-detect\n");
9222 intel_crtc = to_intel_crtc(crtc);
9224 state = drm_atomic_state_alloc(dev);
9225 restore_state = drm_atomic_state_alloc(dev);
9226 if (!state || !restore_state) {
9231 state->acquire_ctx = ctx;
9232 restore_state->acquire_ctx = ctx;
9234 connector_state = drm_atomic_get_connector_state(state, connector);
9235 if (IS_ERR(connector_state)) {
9236 ret = PTR_ERR(connector_state);
9240 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9244 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9245 if (IS_ERR(crtc_state)) {
9246 ret = PTR_ERR(crtc_state);
9250 crtc_state->uapi.active = true;
9252 ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi,
9257 ret = intel_modeset_disable_planes(state, crtc);
9261 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
9263 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
9265 ret = drm_atomic_add_affected_planes(restore_state, crtc);
9267 drm_dbg_kms(&dev_priv->drm,
9268 "Failed to create a copy of old state to restore: %i\n",
9273 ret = drm_atomic_commit(state);
9275 drm_dbg_kms(&dev_priv->drm,
9276 "failed to set mode on load-detect pipe\n");
9280 old->restore_state = restore_state;
9281 drm_atomic_state_put(state);
9283 /* let the connector get through one full cycle before testing */
9284 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
9289 drm_atomic_state_put(state);
9292 if (restore_state) {
9293 drm_atomic_state_put(restore_state);
9294 restore_state = NULL;
9297 if (ret == -EDEADLK)
9303 void intel_release_load_detect_pipe(struct drm_connector *connector,
9304 struct intel_load_detect_pipe *old,
9305 struct drm_modeset_acquire_ctx *ctx)
9307 struct intel_encoder *intel_encoder =
9308 intel_attached_encoder(to_intel_connector(connector));
9309 struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev);
9310 struct drm_encoder *encoder = &intel_encoder->base;
9311 struct drm_atomic_state *state = old->restore_state;
9314 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9315 connector->base.id, connector->name,
9316 encoder->base.id, encoder->name);
9321 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
9323 drm_dbg_kms(&i915->drm,
9324 "Couldn't release load detect pipe: %i\n", ret);
9325 drm_atomic_state_put(state);
9328 static int i9xx_pll_refclk(struct drm_device *dev,
9329 const struct intel_crtc_state *pipe_config)
9331 struct drm_i915_private *dev_priv = to_i915(dev);
9332 u32 dpll = pipe_config->dpll_hw_state.dpll;
9334 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9335 return dev_priv->vbt.lvds_ssc_freq;
9336 else if (HAS_PCH_SPLIT(dev_priv))
9338 else if (!IS_GEN(dev_priv, 2))
9344 /* Returns the clock of the currently programmed mode of the given pipe. */
9345 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9346 struct intel_crtc_state *pipe_config)
9348 struct drm_device *dev = crtc->base.dev;
9349 struct drm_i915_private *dev_priv = to_i915(dev);
9350 enum pipe pipe = crtc->pipe;
9351 u32 dpll = pipe_config->dpll_hw_state.dpll;
9355 int refclk = i9xx_pll_refclk(dev, pipe_config);
9357 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9358 fp = pipe_config->dpll_hw_state.fp0;
9360 fp = pipe_config->dpll_hw_state.fp1;
9362 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9363 if (IS_PINEVIEW(dev_priv)) {
9364 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9365 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9367 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9368 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9371 if (!IS_GEN(dev_priv, 2)) {
9372 if (IS_PINEVIEW(dev_priv))
9373 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9374 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9376 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9377 DPLL_FPA01_P1_POST_DIV_SHIFT);
9379 switch (dpll & DPLL_MODE_MASK) {
9380 case DPLLB_MODE_DAC_SERIAL:
9381 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9384 case DPLLB_MODE_LVDS:
9385 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9389 drm_dbg_kms(&dev_priv->drm,
9390 "Unknown DPLL mode %08x in programmed "
9391 "mode\n", (int)(dpll & DPLL_MODE_MASK));
9395 if (IS_PINEVIEW(dev_priv))
9396 port_clock = pnv_calc_dpll_params(refclk, &clock);
9398 port_clock = i9xx_calc_dpll_params(refclk, &clock);
9400 u32 lvds = IS_I830(dev_priv) ? 0 : intel_de_read(dev_priv,
9402 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9405 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9406 DPLL_FPA01_P1_POST_DIV_SHIFT);
9408 if (lvds & LVDS_CLKB_POWER_UP)
9413 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9416 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9417 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9419 if (dpll & PLL_P2_DIVIDE_BY_4)
9425 port_clock = i9xx_calc_dpll_params(refclk, &clock);
9429 * This value includes pixel_multiplier. We will use
9430 * port_clock to compute adjusted_mode.crtc_clock in the
9431 * encoder's get_config() function.
9433 pipe_config->port_clock = port_clock;
9436 int intel_dotclock_calculate(int link_freq,
9437 const struct intel_link_m_n *m_n)
9440 * The calculation for the data clock is:
9441 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9442 * But we want to avoid losing precison if possible, so:
9443 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9445 * and the link clock is simpler:
9446 * link_clock = (m * link_clock) / n
9452 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
9455 static void ilk_pch_clock_get(struct intel_crtc *crtc,
9456 struct intel_crtc_state *pipe_config)
9458 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9460 /* read out port_clock from the DPLL */
9461 i9xx_crtc_clock_get(crtc, pipe_config);
9464 * In case there is an active pipe without active ports,
9465 * we may need some idea for the dotclock anyway.
9466 * Calculate one based on the FDI configuration.
9468 pipe_config->hw.adjusted_mode.crtc_clock =
9469 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
9470 &pipe_config->fdi_m_n);
9473 /* Returns the currently programmed mode of the given encoder. */
9474 struct drm_display_mode *
9475 intel_encoder_current_mode(struct intel_encoder *encoder)
9477 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
9478 struct intel_crtc_state *crtc_state;
9479 struct drm_display_mode *mode;
9480 struct intel_crtc *crtc;
9483 if (!encoder->get_hw_state(encoder, &pipe))
9486 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
9488 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9492 crtc_state = intel_crtc_state_alloc(crtc);
9498 if (!intel_crtc_get_pipe_config(crtc_state)) {
9504 intel_encoder_get_config(encoder, crtc_state);
9506 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode);
9514 * intel_wm_need_update - Check whether watermarks need updating
9515 * @cur: current plane state
9516 * @new: new plane state
9518 * Check current plane state versus the new one to determine whether
9519 * watermarks need to be recalculated.
9521 * Returns true or false.
9523 static bool intel_wm_need_update(const struct intel_plane_state *cur,
9524 struct intel_plane_state *new)
9526 /* Update watermarks on tiling or size changes. */
9527 if (new->uapi.visible != cur->uapi.visible)
9530 if (!cur->hw.fb || !new->hw.fb)
9533 if (cur->hw.fb->modifier != new->hw.fb->modifier ||
9534 cur->hw.rotation != new->hw.rotation ||
9535 drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
9536 drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
9537 drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
9538 drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
9544 static bool needs_scaling(const struct intel_plane_state *state)
9546 int src_w = drm_rect_width(&state->uapi.src) >> 16;
9547 int src_h = drm_rect_height(&state->uapi.src) >> 16;
9548 int dst_w = drm_rect_width(&state->uapi.dst);
9549 int dst_h = drm_rect_height(&state->uapi.dst);
9551 return (src_w != dst_w || src_h != dst_h);
9554 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
9555 struct intel_crtc_state *crtc_state,
9556 const struct intel_plane_state *old_plane_state,
9557 struct intel_plane_state *plane_state)
9559 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9560 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
9561 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9562 bool mode_changed = intel_crtc_needs_modeset(crtc_state);
9563 bool was_crtc_enabled = old_crtc_state->hw.active;
9564 bool is_crtc_enabled = crtc_state->hw.active;
9565 bool turn_off, turn_on, visible, was_visible;
9568 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
9569 ret = skl_update_scaler_plane(crtc_state, plane_state);
9574 was_visible = old_plane_state->uapi.visible;
9575 visible = plane_state->uapi.visible;
9577 if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible))
9578 was_visible = false;
9581 * Visibility is calculated as if the crtc was on, but
9582 * after scaler setup everything depends on it being off
9583 * when the crtc isn't active.
9585 * FIXME this is wrong for watermarks. Watermarks should also
9586 * be computed as if the pipe would be active. Perhaps move
9587 * per-plane wm computation to the .check_plane() hook, and
9588 * only combine the results from all planes in the current place?
9590 if (!is_crtc_enabled) {
9591 intel_plane_set_invisible(crtc_state, plane_state);
9595 if (!was_visible && !visible)
9598 turn_off = was_visible && (!visible || mode_changed);
9599 turn_on = visible && (!was_visible || mode_changed);
9601 drm_dbg_atomic(&dev_priv->drm,
9602 "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
9603 crtc->base.base.id, crtc->base.name,
9604 plane->base.base.id, plane->base.name,
9605 was_visible, visible,
9606 turn_off, turn_on, mode_changed);
9609 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
9610 crtc_state->update_wm_pre = true;
9612 /* must disable cxsr around plane enable/disable */
9613 if (plane->id != PLANE_CURSOR)
9614 crtc_state->disable_cxsr = true;
9615 } else if (turn_off) {
9616 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
9617 crtc_state->update_wm_post = true;
9619 /* must disable cxsr around plane enable/disable */
9620 if (plane->id != PLANE_CURSOR)
9621 crtc_state->disable_cxsr = true;
9622 } else if (intel_wm_need_update(old_plane_state, plane_state)) {
9623 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
9624 /* FIXME bollocks */
9625 crtc_state->update_wm_pre = true;
9626 crtc_state->update_wm_post = true;
9630 if (visible || was_visible)
9631 crtc_state->fb_bits |= plane->frontbuffer_bit;
9634 * ILK/SNB DVSACNTR/Sprite Enable
9635 * IVB SPR_CTL/Sprite Enable
9636 * "When in Self Refresh Big FIFO mode, a write to enable the
9637 * plane will be internally buffered and delayed while Big FIFO
9640 * Which means that enabling the sprite can take an extra frame
9641 * when we start in big FIFO mode (LP1+). Thus we need to drop
9642 * down to LP0 and wait for vblank in order to make sure the
9643 * sprite gets enabled on the next vblank after the register write.
9644 * Doing otherwise would risk enabling the sprite one frame after
9645 * we've already signalled flip completion. We can resume LP1+
9646 * once the sprite has been enabled.
9649 * WaCxSRDisabledForSpriteScaling:ivb
9650 * IVB SPR_SCALE/Scaling Enable
9651 * "Low Power watermarks must be disabled for at least one
9652 * frame before enabling sprite scaling, and kept disabled
9653 * until sprite scaling is disabled."
9655 * ILK/SNB DVSASCALE/Scaling Enable
9656 * "When in Self Refresh Big FIFO mode, scaling enable will be
9657 * masked off while Big FIFO mode is exiting."
9659 * Despite the w/a only being listed for IVB we assume that
9660 * the ILK/SNB note has similar ramifications, hence we apply
9661 * the w/a on all three platforms.
9663 * With experimental results seems this is needed also for primary
9664 * plane, not only sprite plane.
9666 if (plane->id != PLANE_CURSOR &&
9667 (IS_GEN_RANGE(dev_priv, 5, 6) ||
9668 IS_IVYBRIDGE(dev_priv)) &&
9669 (turn_on || (!needs_scaling(old_plane_state) &&
9670 needs_scaling(plane_state))))
9671 crtc_state->disable_lp_wm = true;
9676 static bool encoders_cloneable(const struct intel_encoder *a,
9677 const struct intel_encoder *b)
9679 /* masks could be asymmetric, so check both ways */
9680 return a == b || (a->cloneable & (1 << b->type) &&
9681 b->cloneable & (1 << a->type));
9684 static bool check_single_encoder_cloning(struct intel_atomic_state *state,
9685 struct intel_crtc *crtc,
9686 struct intel_encoder *encoder)
9688 struct intel_encoder *source_encoder;
9689 struct drm_connector *connector;
9690 struct drm_connector_state *connector_state;
9693 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
9694 if (connector_state->crtc != &crtc->base)
9698 to_intel_encoder(connector_state->best_encoder);
9699 if (!encoders_cloneable(encoder, source_encoder))
9706 static int icl_add_linked_planes(struct intel_atomic_state *state)
9708 struct intel_plane *plane, *linked;
9709 struct intel_plane_state *plane_state, *linked_plane_state;
9712 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
9713 linked = plane_state->planar_linked_plane;
9718 linked_plane_state = intel_atomic_get_plane_state(state, linked);
9719 if (IS_ERR(linked_plane_state))
9720 return PTR_ERR(linked_plane_state);
9722 drm_WARN_ON(state->base.dev,
9723 linked_plane_state->planar_linked_plane != plane);
9724 drm_WARN_ON(state->base.dev,
9725 linked_plane_state->planar_slave == plane_state->planar_slave);
9731 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
9733 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9734 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9735 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
9736 struct intel_plane *plane, *linked;
9737 struct intel_plane_state *plane_state;
9740 if (INTEL_GEN(dev_priv) < 11)
9744 * Destroy all old plane links and make the slave plane invisible
9745 * in the crtc_state->active_planes mask.
9747 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
9748 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
9751 plane_state->planar_linked_plane = NULL;
9752 if (plane_state->planar_slave && !plane_state->uapi.visible) {
9753 crtc_state->enabled_planes &= ~BIT(plane->id);
9754 crtc_state->active_planes &= ~BIT(plane->id);
9755 crtc_state->update_planes |= BIT(plane->id);
9758 plane_state->planar_slave = false;
9761 if (!crtc_state->nv12_planes)
9764 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
9765 struct intel_plane_state *linked_state = NULL;
9767 if (plane->pipe != crtc->pipe ||
9768 !(crtc_state->nv12_planes & BIT(plane->id)))
9771 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
9772 if (!icl_is_nv12_y_plane(dev_priv, linked->id))
9775 if (crtc_state->active_planes & BIT(linked->id))
9778 linked_state = intel_atomic_get_plane_state(state, linked);
9779 if (IS_ERR(linked_state))
9780 return PTR_ERR(linked_state);
9785 if (!linked_state) {
9786 drm_dbg_kms(&dev_priv->drm,
9787 "Need %d free Y planes for planar YUV\n",
9788 hweight8(crtc_state->nv12_planes));
9793 plane_state->planar_linked_plane = linked;
9795 linked_state->planar_slave = true;
9796 linked_state->planar_linked_plane = plane;
9797 crtc_state->enabled_planes |= BIT(linked->id);
9798 crtc_state->active_planes |= BIT(linked->id);
9799 crtc_state->update_planes |= BIT(linked->id);
9800 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
9801 linked->base.name, plane->base.name);
9803 /* Copy parameters to slave plane */
9804 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
9805 linked_state->color_ctl = plane_state->color_ctl;
9806 linked_state->view = plane_state->view;
9807 memcpy(linked_state->color_plane, plane_state->color_plane,
9808 sizeof(linked_state->color_plane));
9810 intel_plane_copy_hw_state(linked_state, plane_state);
9811 linked_state->uapi.src = plane_state->uapi.src;
9812 linked_state->uapi.dst = plane_state->uapi.dst;
9814 if (icl_is_hdr_plane(dev_priv, plane->id)) {
9815 if (linked->id == PLANE_SPRITE5)
9816 plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
9817 else if (linked->id == PLANE_SPRITE4)
9818 plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
9819 else if (linked->id == PLANE_SPRITE3)
9820 plane_state->cus_ctl |= PLANE_CUS_PLANE_5_RKL;
9821 else if (linked->id == PLANE_SPRITE2)
9822 plane_state->cus_ctl |= PLANE_CUS_PLANE_4_RKL;
9824 MISSING_CASE(linked->id);
9831 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
9833 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
9834 struct intel_atomic_state *state =
9835 to_intel_atomic_state(new_crtc_state->uapi.state);
9836 const struct intel_crtc_state *old_crtc_state =
9837 intel_atomic_get_old_crtc_state(state, crtc);
9839 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
9842 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
9844 const struct drm_display_mode *pipe_mode =
9845 &crtc_state->hw.pipe_mode;
9848 if (!crtc_state->hw.enable)
9851 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
9852 pipe_mode->crtc_clock);
9854 return min(linetime_wm, 0x1ff);
9857 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
9858 const struct intel_cdclk_state *cdclk_state)
9860 const struct drm_display_mode *pipe_mode =
9861 &crtc_state->hw.pipe_mode;
9864 if (!crtc_state->hw.enable)
9867 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
9868 cdclk_state->logical.cdclk);
9870 return min(linetime_wm, 0x1ff);
9873 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
9875 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9876 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9877 const struct drm_display_mode *pipe_mode =
9878 &crtc_state->hw.pipe_mode;
9881 if (!crtc_state->hw.enable)
9884 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8,
9885 crtc_state->pixel_rate);
9887 /* Display WA #1135: BXT:ALL GLK:ALL */
9888 if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled)
9891 return min(linetime_wm, 0x1ff);
9894 static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
9895 struct intel_crtc *crtc)
9897 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9898 struct intel_crtc_state *crtc_state =
9899 intel_atomic_get_new_crtc_state(state, crtc);
9900 const struct intel_cdclk_state *cdclk_state;
9902 if (INTEL_GEN(dev_priv) >= 9)
9903 crtc_state->linetime = skl_linetime_wm(crtc_state);
9905 crtc_state->linetime = hsw_linetime_wm(crtc_state);
9907 if (!hsw_crtc_supports_ips(crtc))
9910 cdclk_state = intel_atomic_get_cdclk_state(state);
9911 if (IS_ERR(cdclk_state))
9912 return PTR_ERR(cdclk_state);
9914 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
9920 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
9921 struct intel_crtc *crtc)
9923 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9924 struct intel_crtc_state *crtc_state =
9925 intel_atomic_get_new_crtc_state(state, crtc);
9926 bool mode_changed = intel_crtc_needs_modeset(crtc_state);
9929 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
9930 mode_changed && !crtc_state->hw.active)
9931 crtc_state->update_wm_post = true;
9933 if (mode_changed && crtc_state->hw.enable &&
9934 dev_priv->display.crtc_compute_clock &&
9935 !crtc_state->bigjoiner_slave &&
9936 !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
9937 ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
9943 * May need to update pipe gamma enable bits
9944 * when C8 planes are getting enabled/disabled.
9946 if (c8_planes_changed(crtc_state))
9947 crtc_state->uapi.color_mgmt_changed = true;
9949 if (mode_changed || crtc_state->update_pipe ||
9950 crtc_state->uapi.color_mgmt_changed) {
9951 ret = intel_color_check(crtc_state);
9956 if (dev_priv->display.compute_pipe_wm) {
9957 ret = dev_priv->display.compute_pipe_wm(crtc_state);
9959 drm_dbg_kms(&dev_priv->drm,
9960 "Target pipe watermarks are invalid\n");
9965 if (dev_priv->display.compute_intermediate_wm) {
9966 if (drm_WARN_ON(&dev_priv->drm,
9967 !dev_priv->display.compute_pipe_wm))
9971 * Calculate 'intermediate' watermarks that satisfy both the
9972 * old state and the new state. We can program these
9975 ret = dev_priv->display.compute_intermediate_wm(crtc_state);
9977 drm_dbg_kms(&dev_priv->drm,
9978 "No valid intermediate pipe watermarks are possible\n");
9983 if (INTEL_GEN(dev_priv) >= 9) {
9984 if (mode_changed || crtc_state->update_pipe) {
9985 ret = skl_update_scaler_crtc(crtc_state);
9990 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state);
9995 if (HAS_IPS(dev_priv)) {
9996 ret = hsw_compute_ips_config(crtc_state);
10001 if (INTEL_GEN(dev_priv) >= 9 ||
10002 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
10003 ret = hsw_compute_linetime_wm(state, crtc);
10009 if (!mode_changed) {
10010 ret = intel_psr2_sel_fetch_update(state, crtc);
10018 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10020 struct intel_connector *connector;
10021 struct drm_connector_list_iter conn_iter;
10023 drm_connector_list_iter_begin(dev, &conn_iter);
10024 for_each_intel_connector_iter(connector, &conn_iter) {
10025 if (connector->base.state->crtc)
10026 drm_connector_put(&connector->base);
10028 if (connector->base.encoder) {
10029 connector->base.state->best_encoder =
10030 connector->base.encoder;
10031 connector->base.state->crtc =
10032 connector->base.encoder->crtc;
10034 drm_connector_get(&connector->base);
10036 connector->base.state->best_encoder = NULL;
10037 connector->base.state->crtc = NULL;
10040 drm_connector_list_iter_end(&conn_iter);
10044 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
10045 struct intel_crtc_state *pipe_config)
10047 struct drm_connector *connector = conn_state->connector;
10048 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
10049 const struct drm_display_info *info = &connector->display_info;
10052 switch (conn_state->max_bpc) {
10066 MISSING_CASE(conn_state->max_bpc);
10070 if (bpp < pipe_config->pipe_bpp) {
10071 drm_dbg_kms(&i915->drm,
10072 "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
10073 "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
10074 connector->base.id, connector->name,
10075 bpp, 3 * info->bpc,
10076 3 * conn_state->max_requested_bpc,
10077 pipe_config->pipe_bpp);
10079 pipe_config->pipe_bpp = bpp;
10086 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10087 struct intel_crtc_state *pipe_config)
10089 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10090 struct drm_atomic_state *state = pipe_config->uapi.state;
10091 struct drm_connector *connector;
10092 struct drm_connector_state *connector_state;
10095 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
10096 IS_CHERRYVIEW(dev_priv)))
10098 else if (INTEL_GEN(dev_priv) >= 5)
10103 pipe_config->pipe_bpp = bpp;
10105 /* Clamp display bpp to connector max bpp */
10106 for_each_new_connector_in_state(state, connector, connector_state, i) {
10109 if (connector_state->crtc != &crtc->base)
10112 ret = compute_sink_pipe_bpp(connector_state, pipe_config);
10120 static void intel_dump_crtc_timings(struct drm_i915_private *i915,
10121 const struct drm_display_mode *mode)
10123 drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, "
10124 "type: 0x%x flags: 0x%x\n",
10126 mode->crtc_hdisplay, mode->crtc_hsync_start,
10127 mode->crtc_hsync_end, mode->crtc_htotal,
10128 mode->crtc_vdisplay, mode->crtc_vsync_start,
10129 mode->crtc_vsync_end, mode->crtc_vtotal,
10130 mode->type, mode->flags);
10134 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
10135 const char *id, unsigned int lane_count,
10136 const struct intel_link_m_n *m_n)
10138 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
10140 drm_dbg_kms(&i915->drm,
10141 "%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10143 m_n->gmch_m, m_n->gmch_n,
10144 m_n->link_m, m_n->link_n, m_n->tu);
10148 intel_dump_infoframe(struct drm_i915_private *dev_priv,
10149 const union hdmi_infoframe *frame)
10151 if (!drm_debug_enabled(DRM_UT_KMS))
10154 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
10158 intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
10159 const struct drm_dp_vsc_sdp *vsc)
10161 if (!drm_debug_enabled(DRM_UT_KMS))
10164 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
10167 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
10169 static const char * const output_type_str[] = {
10170 OUTPUT_TYPE(UNUSED),
10171 OUTPUT_TYPE(ANALOG),
10175 OUTPUT_TYPE(TVOUT),
10181 OUTPUT_TYPE(DP_MST),
10186 static void snprintf_output_types(char *buf, size_t len,
10187 unsigned int output_types)
10194 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
10197 if ((output_types & BIT(i)) == 0)
10200 r = snprintf(str, len, "%s%s",
10201 str != buf ? "," : "", output_type_str[i]);
10207 output_types &= ~BIT(i);
10210 WARN_ON_ONCE(output_types != 0);
10213 static const char * const output_format_str[] = {
10214 [INTEL_OUTPUT_FORMAT_INVALID] = "Invalid",
10215 [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
10216 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
10217 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
10220 static const char *output_formats(enum intel_output_format format)
10222 if (format >= ARRAY_SIZE(output_format_str))
10223 format = INTEL_OUTPUT_FORMAT_INVALID;
10224 return output_format_str[format];
10227 static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
10229 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
10230 struct drm_i915_private *i915 = to_i915(plane->base.dev);
10231 const struct drm_framebuffer *fb = plane_state->hw.fb;
10232 struct drm_format_name_buf format_name;
10235 drm_dbg_kms(&i915->drm,
10236 "[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
10237 plane->base.base.id, plane->base.name,
10238 yesno(plane_state->uapi.visible));
10242 drm_dbg_kms(&i915->drm,
10243 "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s modifier = 0x%llx, visible: %s\n",
10244 plane->base.base.id, plane->base.name,
10245 fb->base.id, fb->width, fb->height,
10246 drm_get_format_name(fb->format->format, &format_name),
10247 fb->modifier, yesno(plane_state->uapi.visible));
10248 drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n",
10249 plane_state->hw.rotation, plane_state->scaler_id);
10250 if (plane_state->uapi.visible)
10251 drm_dbg_kms(&i915->drm,
10252 "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
10253 DRM_RECT_FP_ARG(&plane_state->uapi.src),
10254 DRM_RECT_ARG(&plane_state->uapi.dst));
10257 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
10258 struct intel_atomic_state *state,
10259 const char *context)
10261 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
10262 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10263 const struct intel_plane_state *plane_state;
10264 struct intel_plane *plane;
10268 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n",
10269 crtc->base.base.id, crtc->base.name,
10270 yesno(pipe_config->hw.enable), context);
10272 if (!pipe_config->hw.enable)
10275 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
10276 drm_dbg_kms(&dev_priv->drm,
10277 "active: %s, output_types: %s (0x%x), output format: %s\n",
10278 yesno(pipe_config->hw.active),
10279 buf, pipe_config->output_types,
10280 output_formats(pipe_config->output_format));
10282 drm_dbg_kms(&dev_priv->drm,
10283 "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
10284 transcoder_name(pipe_config->cpu_transcoder),
10285 pipe_config->pipe_bpp, pipe_config->dither);
10287 drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n",
10288 transcoder_name(pipe_config->mst_master_transcoder));
10290 drm_dbg_kms(&dev_priv->drm,
10291 "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n",
10292 transcoder_name(pipe_config->master_transcoder),
10293 pipe_config->sync_mode_slaves_mask);
10295 drm_dbg_kms(&dev_priv->drm, "bigjoiner: %s\n",
10296 pipe_config->bigjoiner_slave ? "slave" :
10297 pipe_config->bigjoiner ? "master" : "no");
10299 if (pipe_config->has_pch_encoder)
10300 intel_dump_m_n_config(pipe_config, "fdi",
10301 pipe_config->fdi_lanes,
10302 &pipe_config->fdi_m_n);
10304 if (intel_crtc_has_dp_encoder(pipe_config)) {
10305 intel_dump_m_n_config(pipe_config, "dp m_n",
10306 pipe_config->lane_count, &pipe_config->dp_m_n);
10307 if (pipe_config->has_drrs)
10308 intel_dump_m_n_config(pipe_config, "dp m2_n2",
10309 pipe_config->lane_count,
10310 &pipe_config->dp_m2_n2);
10313 drm_dbg_kms(&dev_priv->drm,
10314 "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
10315 pipe_config->has_audio, pipe_config->has_infoframe,
10316 pipe_config->infoframes.enable);
10318 if (pipe_config->infoframes.enable &
10319 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
10320 drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n",
10321 pipe_config->infoframes.gcp);
10322 if (pipe_config->infoframes.enable &
10323 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
10324 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
10325 if (pipe_config->infoframes.enable &
10326 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
10327 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
10328 if (pipe_config->infoframes.enable &
10329 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
10330 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
10331 if (pipe_config->infoframes.enable &
10332 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
10333 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
10334 if (pipe_config->infoframes.enable &
10335 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
10336 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
10337 if (pipe_config->infoframes.enable &
10338 intel_hdmi_infoframe_enable(DP_SDP_VSC))
10339 intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
10341 drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
10342 yesno(pipe_config->vrr.enable),
10343 pipe_config->vrr.vmin, pipe_config->vrr.vmax,
10344 pipe_config->vrr.pipeline_full, pipe_config->vrr.flipline,
10345 intel_vrr_vmin_vblank_start(pipe_config),
10346 intel_vrr_vmax_vblank_start(pipe_config));
10348 drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
10349 drm_mode_debug_printmodeline(&pipe_config->hw.mode);
10350 drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n");
10351 drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
10352 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode);
10353 drm_dbg_kms(&dev_priv->drm, "pipe mode:\n");
10354 drm_mode_debug_printmodeline(&pipe_config->hw.pipe_mode);
10355 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode);
10356 drm_dbg_kms(&dev_priv->drm,
10357 "port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
10358 pipe_config->port_clock,
10359 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
10360 pipe_config->pixel_rate);
10362 drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n",
10363 pipe_config->linetime, pipe_config->ips_linetime);
10365 if (INTEL_GEN(dev_priv) >= 9)
10366 drm_dbg_kms(&dev_priv->drm,
10367 "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
10369 pipe_config->scaler_state.scaler_users,
10370 pipe_config->scaler_state.scaler_id);
10372 if (HAS_GMCH(dev_priv))
10373 drm_dbg_kms(&dev_priv->drm,
10374 "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10375 pipe_config->gmch_pfit.control,
10376 pipe_config->gmch_pfit.pgm_ratios,
10377 pipe_config->gmch_pfit.lvds_border_bits);
10379 drm_dbg_kms(&dev_priv->drm,
10380 "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
10381 DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
10382 enableddisabled(pipe_config->pch_pfit.enabled),
10383 yesno(pipe_config->pch_pfit.force_thru));
10385 drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i\n",
10386 pipe_config->ips_enabled, pipe_config->double_wide);
10388 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
10390 if (IS_CHERRYVIEW(dev_priv))
10391 drm_dbg_kms(&dev_priv->drm,
10392 "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
10393 pipe_config->cgm_mode, pipe_config->gamma_mode,
10394 pipe_config->gamma_enable, pipe_config->csc_enable);
10396 drm_dbg_kms(&dev_priv->drm,
10397 "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
10398 pipe_config->csc_mode, pipe_config->gamma_mode,
10399 pipe_config->gamma_enable, pipe_config->csc_enable);
10401 drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n",
10402 pipe_config->hw.degamma_lut ?
10403 drm_color_lut_size(pipe_config->hw.degamma_lut) : 0,
10404 pipe_config->hw.gamma_lut ?
10405 drm_color_lut_size(pipe_config->hw.gamma_lut) : 0);
10411 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
10412 if (plane->pipe == crtc->pipe)
10413 intel_dump_plane_state(plane_state);
10417 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
10419 struct drm_device *dev = state->base.dev;
10420 struct drm_connector *connector;
10421 struct drm_connector_list_iter conn_iter;
10422 unsigned int used_ports = 0;
10423 unsigned int used_mst_ports = 0;
10427 * We're going to peek into connector->state,
10428 * hence connection_mutex must be held.
10430 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
10433 * Walk the connector list instead of the encoder
10434 * list to detect the problem on ddi platforms
10435 * where there's just one encoder per digital port.
10437 drm_connector_list_iter_begin(dev, &conn_iter);
10438 drm_for_each_connector_iter(connector, &conn_iter) {
10439 struct drm_connector_state *connector_state;
10440 struct intel_encoder *encoder;
10443 drm_atomic_get_new_connector_state(&state->base,
10445 if (!connector_state)
10446 connector_state = connector->state;
10448 if (!connector_state->best_encoder)
10451 encoder = to_intel_encoder(connector_state->best_encoder);
10453 drm_WARN_ON(dev, !connector_state->crtc);
10455 switch (encoder->type) {
10456 case INTEL_OUTPUT_DDI:
10457 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev))))
10460 case INTEL_OUTPUT_DP:
10461 case INTEL_OUTPUT_HDMI:
10462 case INTEL_OUTPUT_EDP:
10463 /* the same port mustn't appear more than once */
10464 if (used_ports & BIT(encoder->port))
10467 used_ports |= BIT(encoder->port);
10469 case INTEL_OUTPUT_DP_MST:
10471 1 << encoder->port;
10477 drm_connector_list_iter_end(&conn_iter);
10479 /* can't mix MST and SST/HDMI on the same port */
10480 if (used_ports & used_mst_ports)
10487 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
10488 struct intel_crtc_state *crtc_state)
10490 const struct intel_crtc_state *from_crtc_state = crtc_state;
10492 if (crtc_state->bigjoiner_slave) {
10493 from_crtc_state = intel_atomic_get_new_crtc_state(state,
10494 crtc_state->bigjoiner_linked_crtc);
10496 /* No need to copy state if the master state is unchanged */
10497 if (!from_crtc_state)
10501 intel_crtc_copy_color_blobs(crtc_state, from_crtc_state);
10505 intel_crtc_copy_uapi_to_hw_state(struct intel_atomic_state *state,
10506 struct intel_crtc_state *crtc_state)
10508 crtc_state->hw.enable = crtc_state->uapi.enable;
10509 crtc_state->hw.active = crtc_state->uapi.active;
10510 crtc_state->hw.mode = crtc_state->uapi.mode;
10511 crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
10512 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
10514 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc_state);
10517 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
10519 if (crtc_state->bigjoiner_slave)
10522 crtc_state->uapi.enable = crtc_state->hw.enable;
10523 crtc_state->uapi.active = crtc_state->hw.active;
10524 drm_WARN_ON(crtc_state->uapi.crtc->dev,
10525 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
10527 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
10528 crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter;
10530 /* copy color blobs to uapi */
10531 drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
10532 crtc_state->hw.degamma_lut);
10533 drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
10534 crtc_state->hw.gamma_lut);
10535 drm_property_replace_blob(&crtc_state->uapi.ctm,
10536 crtc_state->hw.ctm);
10540 copy_bigjoiner_crtc_state(struct intel_crtc_state *crtc_state,
10541 const struct intel_crtc_state *from_crtc_state)
10543 struct intel_crtc_state *saved_state;
10544 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10546 saved_state = kmemdup(from_crtc_state, sizeof(*saved_state), GFP_KERNEL);
10550 saved_state->uapi = crtc_state->uapi;
10551 saved_state->scaler_state = crtc_state->scaler_state;
10552 saved_state->shared_dpll = crtc_state->shared_dpll;
10553 saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
10554 saved_state->crc_enabled = crtc_state->crc_enabled;
10556 intel_crtc_free_hw_state(crtc_state);
10557 memcpy(crtc_state, saved_state, sizeof(*crtc_state));
10558 kfree(saved_state);
10560 /* Re-init hw state */
10561 memset(&crtc_state->hw, 0, sizeof(saved_state->hw));
10562 crtc_state->hw.enable = from_crtc_state->hw.enable;
10563 crtc_state->hw.active = from_crtc_state->hw.active;
10564 crtc_state->hw.pipe_mode = from_crtc_state->hw.pipe_mode;
10565 crtc_state->hw.adjusted_mode = from_crtc_state->hw.adjusted_mode;
10568 crtc_state->uapi.mode_changed = from_crtc_state->uapi.mode_changed;
10569 crtc_state->uapi.connectors_changed = from_crtc_state->uapi.connectors_changed;
10570 crtc_state->uapi.active_changed = from_crtc_state->uapi.active_changed;
10571 crtc_state->nv12_planes = crtc_state->c8_planes = crtc_state->update_planes = 0;
10572 crtc_state->bigjoiner_linked_crtc = to_intel_crtc(from_crtc_state->uapi.crtc);
10573 crtc_state->bigjoiner_slave = true;
10574 crtc_state->cpu_transcoder = (enum transcoder)crtc->pipe;
10575 crtc_state->has_audio = false;
10581 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
10582 struct intel_crtc_state *crtc_state)
10584 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10585 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10586 struct intel_crtc_state *saved_state;
10588 saved_state = intel_crtc_state_alloc(crtc);
10592 /* free the old crtc_state->hw members */
10593 intel_crtc_free_hw_state(crtc_state);
10595 /* FIXME: before the switch to atomic started, a new pipe_config was
10596 * kzalloc'd. Code that depends on any field being zero should be
10597 * fixed, so that the crtc_state can be safely duplicated. For now,
10598 * only fields that are know to not cause problems are preserved. */
10600 saved_state->uapi = crtc_state->uapi;
10601 saved_state->scaler_state = crtc_state->scaler_state;
10602 saved_state->shared_dpll = crtc_state->shared_dpll;
10603 saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
10604 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
10605 sizeof(saved_state->icl_port_dplls));
10606 saved_state->crc_enabled = crtc_state->crc_enabled;
10607 if (IS_G4X(dev_priv) ||
10608 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10609 saved_state->wm = crtc_state->wm;
10611 memcpy(crtc_state, saved_state, sizeof(*crtc_state));
10612 kfree(saved_state);
10614 intel_crtc_copy_uapi_to_hw_state(state, crtc_state);
10620 intel_modeset_pipe_config(struct intel_atomic_state *state,
10621 struct intel_crtc_state *pipe_config)
10623 struct drm_crtc *crtc = pipe_config->uapi.crtc;
10624 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
10625 struct drm_connector *connector;
10626 struct drm_connector_state *connector_state;
10627 int base_bpp, ret, i;
10630 pipe_config->cpu_transcoder =
10631 (enum transcoder) to_intel_crtc(crtc)->pipe;
10634 * Sanitize sync polarity flags based on requested ones. If neither
10635 * positive or negative polarity is requested, treat this as meaning
10636 * negative polarity.
10638 if (!(pipe_config->hw.adjusted_mode.flags &
10639 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10640 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10642 if (!(pipe_config->hw.adjusted_mode.flags &
10643 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10644 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10646 ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10651 base_bpp = pipe_config->pipe_bpp;
10654 * Determine the real pipe dimensions. Note that stereo modes can
10655 * increase the actual pipe size due to the frame doubling and
10656 * insertion of additional space for blanks between the frame. This
10657 * is stored in the crtc timings. We use the requested mode to do this
10658 * computation to clearly distinguish it from the adjusted mode, which
10659 * can be changed by the connectors in the below retry loop.
10661 drm_mode_get_hv_timing(&pipe_config->hw.mode,
10662 &pipe_config->pipe_src_w,
10663 &pipe_config->pipe_src_h);
10665 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
10666 struct intel_encoder *encoder =
10667 to_intel_encoder(connector_state->best_encoder);
10669 if (connector_state->crtc != crtc)
10672 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
10673 drm_dbg_kms(&i915->drm,
10674 "rejecting invalid cloning configuration\n");
10679 * Determine output_types before calling the .compute_config()
10680 * hooks so that the hooks can use this information safely.
10682 if (encoder->compute_output_type)
10683 pipe_config->output_types |=
10684 BIT(encoder->compute_output_type(encoder, pipe_config,
10687 pipe_config->output_types |= BIT(encoder->type);
10691 /* Ensure the port clock defaults are reset when retrying. */
10692 pipe_config->port_clock = 0;
10693 pipe_config->pixel_multiplier = 1;
10695 /* Fill in default crtc timings, allow encoders to overwrite them. */
10696 drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,
10697 CRTC_STEREO_DOUBLE);
10699 /* Pass our mode to the connectors and the CRTC to give them a chance to
10700 * adjust it according to limitations or connector properties, and also
10701 * a chance to reject the mode entirely.
10703 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
10704 struct intel_encoder *encoder =
10705 to_intel_encoder(connector_state->best_encoder);
10707 if (connector_state->crtc != crtc)
10710 ret = encoder->compute_config(encoder, pipe_config,
10713 if (ret != -EDEADLK)
10714 drm_dbg_kms(&i915->drm,
10715 "Encoder config failure: %d\n",
10721 /* Set default port clock if not overwritten by the encoder. Needs to be
10722 * done afterwards in case the encoder adjusts the mode. */
10723 if (!pipe_config->port_clock)
10724 pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
10725 * pipe_config->pixel_multiplier;
10727 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10728 if (ret == -EDEADLK)
10731 drm_dbg_kms(&i915->drm, "CRTC fixup failed\n");
10735 if (ret == I915_DISPLAY_CONFIG_RETRY) {
10736 if (drm_WARN(&i915->drm, !retry,
10737 "loop in pipe configuration computation\n"))
10740 drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n");
10742 goto encoder_retry;
10745 /* Dithering seems to not pass-through bits correctly when it should, so
10746 * only enable it on 6bpc panels and when its not a compliance
10747 * test requesting 6bpc video pattern.
10749 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
10750 !pipe_config->dither_force_disable;
10751 drm_dbg_kms(&i915->drm,
10752 "hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
10753 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10759 intel_modeset_pipe_config_late(struct intel_crtc_state *crtc_state)
10761 struct intel_atomic_state *state =
10762 to_intel_atomic_state(crtc_state->uapi.state);
10763 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10764 struct drm_connector_state *conn_state;
10765 struct drm_connector *connector;
10768 for_each_new_connector_in_state(&state->base, connector,
10770 struct intel_encoder *encoder =
10771 to_intel_encoder(conn_state->best_encoder);
10774 if (conn_state->crtc != &crtc->base ||
10775 !encoder->compute_config_late)
10778 ret = encoder->compute_config_late(encoder, crtc_state,
10787 bool intel_fuzzy_clock_check(int clock1, int clock2)
10791 if (clock1 == clock2)
10794 if (!clock1 || !clock2)
10797 diff = abs(clock1 - clock2);
10799 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10806 intel_compare_m_n(unsigned int m, unsigned int n,
10807 unsigned int m2, unsigned int n2,
10810 if (m == m2 && n == n2)
10813 if (exact || !m || !n || !m2 || !n2)
10816 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
10823 } else if (n < n2) {
10833 return intel_fuzzy_clock_check(m, m2);
10837 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
10838 const struct intel_link_m_n *m2_n2,
10841 return m_n->tu == m2_n2->tu &&
10842 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
10843 m2_n2->gmch_m, m2_n2->gmch_n, exact) &&
10844 intel_compare_m_n(m_n->link_m, m_n->link_n,
10845 m2_n2->link_m, m2_n2->link_n, exact);
10849 intel_compare_infoframe(const union hdmi_infoframe *a,
10850 const union hdmi_infoframe *b)
10852 return memcmp(a, b, sizeof(*a)) == 0;
10856 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
10857 const struct drm_dp_vsc_sdp *b)
10859 return memcmp(a, b, sizeof(*a)) == 0;
10863 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
10864 bool fastset, const char *name,
10865 const union hdmi_infoframe *a,
10866 const union hdmi_infoframe *b)
10869 if (!drm_debug_enabled(DRM_UT_KMS))
10872 drm_dbg_kms(&dev_priv->drm,
10873 "fastset mismatch in %s infoframe\n", name);
10874 drm_dbg_kms(&dev_priv->drm, "expected:\n");
10875 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
10876 drm_dbg_kms(&dev_priv->drm, "found:\n");
10877 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
10879 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name);
10880 drm_err(&dev_priv->drm, "expected:\n");
10881 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
10882 drm_err(&dev_priv->drm, "found:\n");
10883 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
10888 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
10889 bool fastset, const char *name,
10890 const struct drm_dp_vsc_sdp *a,
10891 const struct drm_dp_vsc_sdp *b)
10894 if (!drm_debug_enabled(DRM_UT_KMS))
10897 drm_dbg_kms(&dev_priv->drm,
10898 "fastset mismatch in %s dp sdp\n", name);
10899 drm_dbg_kms(&dev_priv->drm, "expected:\n");
10900 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
10901 drm_dbg_kms(&dev_priv->drm, "found:\n");
10902 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
10904 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name);
10905 drm_err(&dev_priv->drm, "expected:\n");
10906 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
10907 drm_err(&dev_priv->drm, "found:\n");
10908 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
10912 static void __printf(4, 5)
10913 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
10914 const char *name, const char *format, ...)
10916 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
10917 struct va_format vaf;
10920 va_start(args, format);
10925 drm_dbg_kms(&i915->drm,
10926 "[CRTC:%d:%s] fastset mismatch in %s %pV\n",
10927 crtc->base.base.id, crtc->base.name, name, &vaf);
10929 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n",
10930 crtc->base.base.id, crtc->base.name, name, &vaf);
10935 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
10937 if (dev_priv->params.fastboot != -1)
10938 return dev_priv->params.fastboot;
10940 /* Enable fastboot by default on Skylake and newer */
10941 if (INTEL_GEN(dev_priv) >= 9)
10944 /* Enable fastboot by default on VLV and CHV */
10945 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10948 /* Disabled by default on all others */
10953 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
10954 const struct intel_crtc_state *pipe_config,
10957 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
10958 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
10961 bool fixup_inherited = fastset &&
10962 current_config->inherited && !pipe_config->inherited;
10964 if (fixup_inherited && !fastboot_enabled(dev_priv)) {
10965 drm_dbg_kms(&dev_priv->drm,
10966 "initial modeset and fastboot not set\n");
10970 #define PIPE_CONF_CHECK_X(name) do { \
10971 if (current_config->name != pipe_config->name) { \
10972 pipe_config_mismatch(fastset, crtc, __stringify(name), \
10973 "(expected 0x%08x, found 0x%08x)", \
10974 current_config->name, \
10975 pipe_config->name); \
10980 #define PIPE_CONF_CHECK_I(name) do { \
10981 if (current_config->name != pipe_config->name) { \
10982 pipe_config_mismatch(fastset, crtc, __stringify(name), \
10983 "(expected %i, found %i)", \
10984 current_config->name, \
10985 pipe_config->name); \
10990 #define PIPE_CONF_CHECK_BOOL(name) do { \
10991 if (current_config->name != pipe_config->name) { \
10992 pipe_config_mismatch(fastset, crtc, __stringify(name), \
10993 "(expected %s, found %s)", \
10994 yesno(current_config->name), \
10995 yesno(pipe_config->name)); \
11001 * Checks state where we only read out the enabling, but not the entire
11002 * state itself (like full infoframes or ELD for audio). These states
11003 * require a full modeset on bootup to fix up.
11005 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
11006 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
11007 PIPE_CONF_CHECK_BOOL(name); \
11009 pipe_config_mismatch(fastset, crtc, __stringify(name), \
11010 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
11011 yesno(current_config->name), \
11012 yesno(pipe_config->name)); \
11017 #define PIPE_CONF_CHECK_P(name) do { \
11018 if (current_config->name != pipe_config->name) { \
11019 pipe_config_mismatch(fastset, crtc, __stringify(name), \
11020 "(expected %p, found %p)", \
11021 current_config->name, \
11022 pipe_config->name); \
11027 #define PIPE_CONF_CHECK_M_N(name) do { \
11028 if (!intel_compare_link_m_n(¤t_config->name, \
11029 &pipe_config->name,\
11031 pipe_config_mismatch(fastset, crtc, __stringify(name), \
11032 "(expected tu %i gmch %i/%i link %i/%i, " \
11033 "found tu %i, gmch %i/%i link %i/%i)", \
11034 current_config->name.tu, \
11035 current_config->name.gmch_m, \
11036 current_config->name.gmch_n, \
11037 current_config->name.link_m, \
11038 current_config->name.link_n, \
11039 pipe_config->name.tu, \
11040 pipe_config->name.gmch_m, \
11041 pipe_config->name.gmch_n, \
11042 pipe_config->name.link_m, \
11043 pipe_config->name.link_n); \
11048 /* This is required for BDW+ where there is only one set of registers for
11049 * switching between high and low RR.
11050 * This macro can be used whenever a comparison has to be made between one
11051 * hw state and multiple sw state variables.
11053 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
11054 if (!intel_compare_link_m_n(¤t_config->name, \
11055 &pipe_config->name, !fastset) && \
11056 !intel_compare_link_m_n(¤t_config->alt_name, \
11057 &pipe_config->name, !fastset)) { \
11058 pipe_config_mismatch(fastset, crtc, __stringify(name), \
11059 "(expected tu %i gmch %i/%i link %i/%i, " \
11060 "or tu %i gmch %i/%i link %i/%i, " \
11061 "found tu %i, gmch %i/%i link %i/%i)", \
11062 current_config->name.tu, \
11063 current_config->name.gmch_m, \
11064 current_config->name.gmch_n, \
11065 current_config->name.link_m, \
11066 current_config->name.link_n, \
11067 current_config->alt_name.tu, \
11068 current_config->alt_name.gmch_m, \
11069 current_config->alt_name.gmch_n, \
11070 current_config->alt_name.link_m, \
11071 current_config->alt_name.link_n, \
11072 pipe_config->name.tu, \
11073 pipe_config->name.gmch_m, \
11074 pipe_config->name.gmch_n, \
11075 pipe_config->name.link_m, \
11076 pipe_config->name.link_n); \
11081 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
11082 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11083 pipe_config_mismatch(fastset, crtc, __stringify(name), \
11084 "(%x) (expected %i, found %i)", \
11086 current_config->name & (mask), \
11087 pipe_config->name & (mask)); \
11092 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
11093 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11094 pipe_config_mismatch(fastset, crtc, __stringify(name), \
11095 "(expected %i, found %i)", \
11096 current_config->name, \
11097 pipe_config->name); \
11102 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
11103 if (!intel_compare_infoframe(¤t_config->infoframes.name, \
11104 &pipe_config->infoframes.name)) { \
11105 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
11106 ¤t_config->infoframes.name, \
11107 &pipe_config->infoframes.name); \
11112 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
11113 if (!current_config->has_psr && !pipe_config->has_psr && \
11114 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \
11115 &pipe_config->infoframes.name)) { \
11116 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
11117 ¤t_config->infoframes.name, \
11118 &pipe_config->infoframes.name); \
11123 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
11124 if (current_config->name1 != pipe_config->name1) { \
11125 pipe_config_mismatch(fastset, crtc, __stringify(name1), \
11126 "(expected %i, found %i, won't compare lut values)", \
11127 current_config->name1, \
11128 pipe_config->name1); \
11131 if (!intel_color_lut_equal(current_config->name2, \
11132 pipe_config->name2, pipe_config->name1, \
11133 bit_precision)) { \
11134 pipe_config_mismatch(fastset, crtc, __stringify(name2), \
11135 "hw_state doesn't match sw_state"); \
11141 #define PIPE_CONF_QUIRK(quirk) \
11142 ((current_config->quirks | pipe_config->quirks) & (quirk))
11144 PIPE_CONF_CHECK_I(cpu_transcoder);
11146 PIPE_CONF_CHECK_BOOL(has_pch_encoder);
11147 PIPE_CONF_CHECK_I(fdi_lanes);
11148 PIPE_CONF_CHECK_M_N(fdi_m_n);
11150 PIPE_CONF_CHECK_I(lane_count);
11151 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11153 if (INTEL_GEN(dev_priv) < 8) {
11154 PIPE_CONF_CHECK_M_N(dp_m_n);
11156 if (current_config->has_drrs)
11157 PIPE_CONF_CHECK_M_N(dp_m2_n2);
11159 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11161 PIPE_CONF_CHECK_X(output_types);
11163 /* FIXME do the readout properly and get rid of this quirk */
11164 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
11165 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
11166 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal);
11167 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_start);
11168 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_end);
11169 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_start);
11170 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_end);
11172 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vdisplay);
11173 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vtotal);
11174 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_start);
11175 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_end);
11176 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_start);
11177 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_end);
11179 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
11180 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
11181 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
11182 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
11183 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
11184 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
11186 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
11187 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
11188 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
11189 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
11190 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
11191 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
11193 PIPE_CONF_CHECK_I(pixel_multiplier);
11195 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
11196 DRM_MODE_FLAG_INTERLACE);
11198 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11199 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
11200 DRM_MODE_FLAG_PHSYNC);
11201 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
11202 DRM_MODE_FLAG_NHSYNC);
11203 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
11204 DRM_MODE_FLAG_PVSYNC);
11205 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
11206 DRM_MODE_FLAG_NVSYNC);
11210 PIPE_CONF_CHECK_I(output_format);
11211 PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
11212 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11213 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11214 PIPE_CONF_CHECK_BOOL(limited_color_range);
11216 PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
11217 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
11218 PIPE_CONF_CHECK_BOOL(has_infoframe);
11219 /* FIXME do the readout properly and get rid of this quirk */
11220 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE))
11221 PIPE_CONF_CHECK_BOOL(fec_enable);
11223 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
11225 PIPE_CONF_CHECK_X(gmch_pfit.control);
11226 /* pfit ratios are autocomputed by the hw on gen4+ */
11227 if (INTEL_GEN(dev_priv) < 4)
11228 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11229 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11232 * Changing the EDP transcoder input mux
11233 * (A_ONOFF vs. A_ON) requires a full modeset.
11235 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
11238 PIPE_CONF_CHECK_I(pipe_src_w);
11239 PIPE_CONF_CHECK_I(pipe_src_h);
11241 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
11242 if (current_config->pch_pfit.enabled) {
11243 PIPE_CONF_CHECK_I(pch_pfit.dst.x1);
11244 PIPE_CONF_CHECK_I(pch_pfit.dst.y1);
11245 PIPE_CONF_CHECK_I(pch_pfit.dst.x2);
11246 PIPE_CONF_CHECK_I(pch_pfit.dst.y2);
11249 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11250 /* FIXME do the readout properly and get rid of this quirk */
11251 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE))
11252 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11254 PIPE_CONF_CHECK_X(gamma_mode);
11255 if (IS_CHERRYVIEW(dev_priv))
11256 PIPE_CONF_CHECK_X(cgm_mode);
11258 PIPE_CONF_CHECK_X(csc_mode);
11259 PIPE_CONF_CHECK_BOOL(gamma_enable);
11260 PIPE_CONF_CHECK_BOOL(csc_enable);
11262 PIPE_CONF_CHECK_I(linetime);
11263 PIPE_CONF_CHECK_I(ips_linetime);
11265 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
11267 PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
11270 PIPE_CONF_CHECK_BOOL(double_wide);
11272 PIPE_CONF_CHECK_P(shared_dpll);
11274 /* FIXME do the readout properly and get rid of this quirk */
11275 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
11276 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11277 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11278 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11279 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11280 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11281 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11282 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11283 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11284 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11285 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
11286 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
11287 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
11288 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
11289 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
11290 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
11291 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
11292 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
11293 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
11294 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
11295 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
11296 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
11297 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
11298 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
11299 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
11300 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
11301 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
11302 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
11303 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
11304 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
11305 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
11306 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
11308 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11309 PIPE_CONF_CHECK_X(dsi_pll.div);
11311 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11312 PIPE_CONF_CHECK_I(pipe_bpp);
11314 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock);
11315 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
11316 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11318 PIPE_CONF_CHECK_I(min_voltage_level);
11321 PIPE_CONF_CHECK_X(infoframes.enable);
11322 PIPE_CONF_CHECK_X(infoframes.gcp);
11323 PIPE_CONF_CHECK_INFOFRAME(avi);
11324 PIPE_CONF_CHECK_INFOFRAME(spd);
11325 PIPE_CONF_CHECK_INFOFRAME(hdmi);
11326 PIPE_CONF_CHECK_INFOFRAME(drm);
11327 PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
11329 PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
11330 PIPE_CONF_CHECK_I(master_transcoder);
11331 PIPE_CONF_CHECK_BOOL(bigjoiner);
11332 PIPE_CONF_CHECK_BOOL(bigjoiner_slave);
11333 PIPE_CONF_CHECK_P(bigjoiner_linked_crtc);
11335 PIPE_CONF_CHECK_I(dsc.compression_enable);
11336 PIPE_CONF_CHECK_I(dsc.dsc_split);
11337 PIPE_CONF_CHECK_I(dsc.compressed_bpp);
11339 PIPE_CONF_CHECK_I(mst_master_transcoder);
11341 PIPE_CONF_CHECK_BOOL(vrr.enable);
11342 PIPE_CONF_CHECK_I(vrr.vmin);
11343 PIPE_CONF_CHECK_I(vrr.vmax);
11344 PIPE_CONF_CHECK_I(vrr.flipline);
11345 PIPE_CONF_CHECK_I(vrr.pipeline_full);
11347 #undef PIPE_CONF_CHECK_X
11348 #undef PIPE_CONF_CHECK_I
11349 #undef PIPE_CONF_CHECK_BOOL
11350 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
11351 #undef PIPE_CONF_CHECK_P
11352 #undef PIPE_CONF_CHECK_FLAGS
11353 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11354 #undef PIPE_CONF_CHECK_COLOR_LUT
11355 #undef PIPE_CONF_QUIRK
11360 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11361 const struct intel_crtc_state *pipe_config)
11363 if (pipe_config->has_pch_encoder) {
11364 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11365 &pipe_config->fdi_m_n);
11366 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
11369 * FDI already provided one idea for the dotclock.
11370 * Yell if the encoder disagrees.
11372 drm_WARN(&dev_priv->drm,
11373 !intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11374 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11375 fdi_dotclock, dotclock);
11379 static void verify_wm_state(struct intel_crtc *crtc,
11380 struct intel_crtc_state *new_crtc_state)
11382 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11383 struct skl_hw_state {
11384 struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
11385 struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
11386 struct skl_pipe_wm wm;
11388 struct skl_pipe_wm *sw_wm;
11389 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11390 u8 hw_enabled_slices;
11391 const enum pipe pipe = crtc->pipe;
11392 int plane, level, max_level = ilk_wm_max_level(dev_priv);
11394 if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active)
11397 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
11401 skl_pipe_wm_get_hw_state(crtc, &hw->wm);
11402 sw_wm = &new_crtc_state->wm.skl.optimal;
11404 skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
11406 hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
11408 if (INTEL_GEN(dev_priv) >= 11 &&
11409 hw_enabled_slices != dev_priv->dbuf.enabled_slices)
11410 drm_err(&dev_priv->drm,
11411 "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n",
11412 dev_priv->dbuf.enabled_slices,
11413 hw_enabled_slices);
11416 for_each_universal_plane(dev_priv, pipe, plane) {
11417 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11419 hw_plane_wm = &hw->wm.planes[plane];
11420 sw_plane_wm = &sw_wm->planes[plane];
11423 for (level = 0; level <= max_level; level++) {
11424 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11425 &sw_plane_wm->wm[level]) ||
11426 (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
11427 &sw_plane_wm->sagv_wm0)))
11430 drm_err(&dev_priv->drm,
11431 "mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11432 pipe_name(pipe), plane + 1, level,
11433 sw_plane_wm->wm[level].plane_en,
11434 sw_plane_wm->wm[level].plane_res_b,
11435 sw_plane_wm->wm[level].plane_res_l,
11436 hw_plane_wm->wm[level].plane_en,
11437 hw_plane_wm->wm[level].plane_res_b,
11438 hw_plane_wm->wm[level].plane_res_l);
11441 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11442 &sw_plane_wm->trans_wm)) {
11443 drm_err(&dev_priv->drm,
11444 "mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11445 pipe_name(pipe), plane + 1,
11446 sw_plane_wm->trans_wm.plane_en,
11447 sw_plane_wm->trans_wm.plane_res_b,
11448 sw_plane_wm->trans_wm.plane_res_l,
11449 hw_plane_wm->trans_wm.plane_en,
11450 hw_plane_wm->trans_wm.plane_res_b,
11451 hw_plane_wm->trans_wm.plane_res_l);
11455 hw_ddb_entry = &hw->ddb_y[plane];
11456 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane];
11458 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11459 drm_err(&dev_priv->drm,
11460 "mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11461 pipe_name(pipe), plane + 1,
11462 sw_ddb_entry->start, sw_ddb_entry->end,
11463 hw_ddb_entry->start, hw_ddb_entry->end);
11469 * If the cursor plane isn't active, we may not have updated it's ddb
11470 * allocation. In that case since the ddb allocation will be updated
11471 * once the plane becomes visible, we can skip this check
11474 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11476 hw_plane_wm = &hw->wm.planes[PLANE_CURSOR];
11477 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11480 for (level = 0; level <= max_level; level++) {
11481 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11482 &sw_plane_wm->wm[level]) ||
11483 (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
11484 &sw_plane_wm->sagv_wm0)))
11487 drm_err(&dev_priv->drm,
11488 "mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11489 pipe_name(pipe), level,
11490 sw_plane_wm->wm[level].plane_en,
11491 sw_plane_wm->wm[level].plane_res_b,
11492 sw_plane_wm->wm[level].plane_res_l,
11493 hw_plane_wm->wm[level].plane_en,
11494 hw_plane_wm->wm[level].plane_res_b,
11495 hw_plane_wm->wm[level].plane_res_l);
11498 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11499 &sw_plane_wm->trans_wm)) {
11500 drm_err(&dev_priv->drm,
11501 "mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11503 sw_plane_wm->trans_wm.plane_en,
11504 sw_plane_wm->trans_wm.plane_res_b,
11505 sw_plane_wm->trans_wm.plane_res_l,
11506 hw_plane_wm->trans_wm.plane_en,
11507 hw_plane_wm->trans_wm.plane_res_b,
11508 hw_plane_wm->trans_wm.plane_res_l);
11512 hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR];
11513 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
11515 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11516 drm_err(&dev_priv->drm,
11517 "mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11519 sw_ddb_entry->start, sw_ddb_entry->end,
11520 hw_ddb_entry->start, hw_ddb_entry->end);
11528 verify_connector_state(struct intel_atomic_state *state,
11529 struct intel_crtc *crtc)
11531 struct drm_connector *connector;
11532 struct drm_connector_state *new_conn_state;
11535 for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) {
11536 struct drm_encoder *encoder = connector->encoder;
11537 struct intel_crtc_state *crtc_state = NULL;
11539 if (new_conn_state->crtc != &crtc->base)
11543 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
11545 intel_connector_verify_state(crtc_state, new_conn_state);
11547 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
11548 "connector's atomic encoder doesn't match legacy encoder\n");
11553 verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state)
11555 struct intel_encoder *encoder;
11556 struct drm_connector *connector;
11557 struct drm_connector_state *old_conn_state, *new_conn_state;
11560 for_each_intel_encoder(&dev_priv->drm, encoder) {
11561 bool enabled = false, found = false;
11564 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n",
11565 encoder->base.base.id,
11566 encoder->base.name);
11568 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,
11569 new_conn_state, i) {
11570 if (old_conn_state->best_encoder == &encoder->base)
11573 if (new_conn_state->best_encoder != &encoder->base)
11575 found = enabled = true;
11577 I915_STATE_WARN(new_conn_state->crtc !=
11578 encoder->base.crtc,
11579 "connector's crtc doesn't match encoder crtc\n");
11585 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11586 "encoder's enabled state mismatch "
11587 "(expected %i, found %i)\n",
11588 !!encoder->base.crtc, enabled);
11590 if (!encoder->base.crtc) {
11593 active = encoder->get_hw_state(encoder, &pipe);
11594 I915_STATE_WARN(active,
11595 "encoder detached but still enabled on pipe %c.\n",
11602 verify_crtc_state(struct intel_crtc *crtc,
11603 struct intel_crtc_state *old_crtc_state,
11604 struct intel_crtc_state *new_crtc_state)
11606 struct drm_device *dev = crtc->base.dev;
11607 struct drm_i915_private *dev_priv = to_i915(dev);
11608 struct intel_encoder *encoder;
11609 struct intel_crtc_state *pipe_config = old_crtc_state;
11610 struct drm_atomic_state *state = old_crtc_state->uapi.state;
11611 struct intel_crtc *master = crtc;
11613 __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
11614 intel_crtc_free_hw_state(old_crtc_state);
11615 intel_crtc_state_reset(old_crtc_state, crtc);
11616 old_crtc_state->uapi.state = state;
11618 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id,
11621 pipe_config->hw.enable = new_crtc_state->hw.enable;
11623 intel_crtc_get_pipe_config(pipe_config);
11625 /* we keep both pipes enabled on 830 */
11626 if (IS_I830(dev_priv) && pipe_config->hw.active)
11627 pipe_config->hw.active = new_crtc_state->hw.active;
11629 I915_STATE_WARN(new_crtc_state->hw.active != pipe_config->hw.active,
11630 "crtc active state doesn't match with hw state "
11631 "(expected %i, found %i)\n",
11632 new_crtc_state->hw.active, pipe_config->hw.active);
11634 I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,
11635 "transitional active state does not match atomic hw state "
11636 "(expected %i, found %i)\n",
11637 new_crtc_state->hw.active, crtc->active);
11639 if (new_crtc_state->bigjoiner_slave)
11640 master = new_crtc_state->bigjoiner_linked_crtc;
11642 for_each_encoder_on_crtc(dev, &master->base, encoder) {
11646 active = encoder->get_hw_state(encoder, &pipe);
11647 I915_STATE_WARN(active != new_crtc_state->hw.active,
11648 "[ENCODER:%i] active %i with crtc active %i\n",
11649 encoder->base.base.id, active,
11650 new_crtc_state->hw.active);
11652 I915_STATE_WARN(active && master->pipe != pipe,
11653 "Encoder connected to wrong pipe %c\n",
11657 intel_encoder_get_config(encoder, pipe_config);
11660 if (!new_crtc_state->hw.active)
11663 intel_pipe_config_sanity_check(dev_priv, pipe_config);
11665 if (!intel_pipe_config_compare(new_crtc_state,
11666 pipe_config, false)) {
11667 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11668 intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
11669 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
11674 intel_verify_planes(struct intel_atomic_state *state)
11676 struct intel_plane *plane;
11677 const struct intel_plane_state *plane_state;
11680 for_each_new_intel_plane_in_state(state, plane,
11682 assert_plane(plane, plane_state->planar_slave ||
11683 plane_state->uapi.visible);
11687 verify_single_dpll_state(struct drm_i915_private *dev_priv,
11688 struct intel_shared_dpll *pll,
11689 struct intel_crtc *crtc,
11690 struct intel_crtc_state *new_crtc_state)
11692 struct intel_dpll_hw_state dpll_hw_state;
11693 unsigned int crtc_mask;
11696 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11698 drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name);
11700 active = intel_dpll_get_hw_state(dev_priv, pll, &dpll_hw_state);
11702 if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
11703 I915_STATE_WARN(!pll->on && pll->active_mask,
11704 "pll in active use but not on in sw tracking\n");
11705 I915_STATE_WARN(pll->on && !pll->active_mask,
11706 "pll is on but not used by any active crtc\n");
11707 I915_STATE_WARN(pll->on != active,
11708 "pll on state mismatch (expected %i, found %i)\n",
11713 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
11714 "more active pll users than references: %x vs %x\n",
11715 pll->active_mask, pll->state.crtc_mask);
11720 crtc_mask = drm_crtc_mask(&crtc->base);
11722 if (new_crtc_state->hw.active)
11723 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
11724 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
11725 pipe_name(crtc->pipe), pll->active_mask);
11727 I915_STATE_WARN(pll->active_mask & crtc_mask,
11728 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
11729 pipe_name(crtc->pipe), pll->active_mask);
11731 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
11732 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
11733 crtc_mask, pll->state.crtc_mask);
11735 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
11737 sizeof(dpll_hw_state)),
11738 "pll hw state mismatch\n");
11742 verify_shared_dpll_state(struct intel_crtc *crtc,
11743 struct intel_crtc_state *old_crtc_state,
11744 struct intel_crtc_state *new_crtc_state)
11746 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11748 if (new_crtc_state->shared_dpll)
11749 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state);
11751 if (old_crtc_state->shared_dpll &&
11752 old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
11753 unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
11754 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
11756 I915_STATE_WARN(pll->active_mask & crtc_mask,
11757 "pll active mismatch (didn't expect pipe %c in active mask)\n",
11758 pipe_name(crtc->pipe));
11759 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
11760 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
11761 pipe_name(crtc->pipe));
11766 intel_modeset_verify_crtc(struct intel_crtc *crtc,
11767 struct intel_atomic_state *state,
11768 struct intel_crtc_state *old_crtc_state,
11769 struct intel_crtc_state *new_crtc_state)
11771 if (!intel_crtc_needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
11774 verify_wm_state(crtc, new_crtc_state);
11775 verify_connector_state(state, crtc);
11776 verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
11777 verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
11781 verify_disabled_dpll_state(struct drm_i915_private *dev_priv)
11785 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++)
11786 verify_single_dpll_state(dev_priv,
11787 &dev_priv->dpll.shared_dplls[i],
11792 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
11793 struct intel_atomic_state *state)
11795 verify_encoder_state(dev_priv, state);
11796 verify_connector_state(state, NULL);
11797 verify_disabled_dpll_state(dev_priv);
11801 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
11803 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
11804 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11805 struct drm_display_mode adjusted_mode =
11806 crtc_state->hw.adjusted_mode;
11808 if (crtc_state->vrr.enable) {
11809 adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax;
11810 adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax;
11811 adjusted_mode.crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
11812 crtc->vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
11815 drm_calc_timestamping_constants(&crtc->base, &adjusted_mode);
11817 crtc->mode_flags = crtc_state->mode_flags;
11820 * The scanline counter increments at the leading edge of hsync.
11822 * On most platforms it starts counting from vtotal-1 on the
11823 * first active line. That means the scanline counter value is
11824 * always one less than what we would expect. Ie. just after
11825 * start of vblank, which also occurs at start of hsync (on the
11826 * last active line), the scanline counter will read vblank_start-1.
11828 * On gen2 the scanline counter starts counting from 1 instead
11829 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11830 * to keep the value positive), instead of adding one.
11832 * On HSW+ the behaviour of the scanline counter depends on the output
11833 * type. For DP ports it behaves like most other platforms, but on HDMI
11834 * there's an extra 1 line difference. So we need to add two instead of
11835 * one to the value.
11837 * On VLV/CHV DSI the scanline counter would appear to increment
11838 * approx. 1/3 of a scanline before start of vblank. Unfortunately
11839 * that means we can't tell whether we're in vblank or not while
11840 * we're on that particular line. We must still set scanline_offset
11841 * to 1 so that the vblank timestamps come out correct when we query
11842 * the scanline counter from within the vblank interrupt handler.
11843 * However if queried just before the start of vblank we'll get an
11844 * answer that's slightly in the future.
11846 if (IS_GEN(dev_priv, 2)) {
11849 vtotal = adjusted_mode.crtc_vtotal;
11850 if (adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
11853 crtc->scanline_offset = vtotal - 1;
11854 } else if (HAS_DDI(dev_priv) &&
11855 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
11856 crtc->scanline_offset = 2;
11858 crtc->scanline_offset = 1;
11862 static void intel_modeset_clear_plls(struct intel_atomic_state *state)
11864 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
11865 struct intel_crtc_state *new_crtc_state;
11866 struct intel_crtc *crtc;
11869 if (!dev_priv->display.crtc_compute_clock)
11872 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
11873 if (!intel_crtc_needs_modeset(new_crtc_state))
11876 intel_release_shared_dplls(state, crtc);
11881 * This implements the workaround described in the "notes" section of the mode
11882 * set sequence documentation. When going from no pipes or single pipe to
11883 * multiple pipes, and planes are enabled after the pipe, we need to wait at
11884 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
11886 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
11888 struct intel_crtc_state *crtc_state;
11889 struct intel_crtc *crtc;
11890 struct intel_crtc_state *first_crtc_state = NULL;
11891 struct intel_crtc_state *other_crtc_state = NULL;
11892 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
11895 /* look at all crtc's that are going to be enabled in during modeset */
11896 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
11897 if (!crtc_state->hw.active ||
11898 !intel_crtc_needs_modeset(crtc_state))
11901 if (first_crtc_state) {
11902 other_crtc_state = crtc_state;
11905 first_crtc_state = crtc_state;
11906 first_pipe = crtc->pipe;
11910 /* No workaround needed? */
11911 if (!first_crtc_state)
11914 /* w/a possibly needed, check how many crtc's are already enabled. */
11915 for_each_intel_crtc(state->base.dev, crtc) {
11916 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
11917 if (IS_ERR(crtc_state))
11918 return PTR_ERR(crtc_state);
11920 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
11922 if (!crtc_state->hw.active ||
11923 intel_crtc_needs_modeset(crtc_state))
11926 /* 2 or more enabled crtcs means no need for w/a */
11927 if (enabled_pipe != INVALID_PIPE)
11930 enabled_pipe = crtc->pipe;
11933 if (enabled_pipe != INVALID_PIPE)
11934 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
11935 else if (other_crtc_state)
11936 other_crtc_state->hsw_workaround_pipe = first_pipe;
11941 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
11944 const struct intel_crtc_state *crtc_state;
11945 struct intel_crtc *crtc;
11948 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
11949 if (crtc_state->hw.active)
11950 active_pipes |= BIT(crtc->pipe);
11952 active_pipes &= ~BIT(crtc->pipe);
11955 return active_pipes;
11958 static int intel_modeset_checks(struct intel_atomic_state *state)
11960 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
11962 state->modeset = true;
11964 if (IS_HASWELL(dev_priv))
11965 return hsw_mode_set_planes_workaround(state);
11971 * Handle calculation of various watermark data at the end of the atomic check
11972 * phase. The code here should be run after the per-crtc and per-plane 'check'
11973 * handlers to ensure that all derived state has been updated.
11975 static int calc_watermark_data(struct intel_atomic_state *state)
11977 struct drm_device *dev = state->base.dev;
11978 struct drm_i915_private *dev_priv = to_i915(dev);
11980 /* Is there platform-specific watermark information to calculate? */
11981 if (dev_priv->display.compute_global_watermarks)
11982 return dev_priv->display.compute_global_watermarks(state);
11987 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
11988 struct intel_crtc_state *new_crtc_state)
11990 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
11993 new_crtc_state->uapi.mode_changed = false;
11994 new_crtc_state->update_pipe = true;
11997 static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state,
11998 struct intel_crtc_state *new_crtc_state)
12001 * If we're not doing the full modeset we want to
12002 * keep the current M/N values as they may be
12003 * sufficiently different to the computed values
12004 * to cause problems.
12006 * FIXME: should really copy more fuzzy state here
12008 new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n;
12009 new_crtc_state->dp_m_n = old_crtc_state->dp_m_n;
12010 new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
12011 new_crtc_state->has_drrs = old_crtc_state->has_drrs;
12014 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
12015 struct intel_crtc *crtc,
12018 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
12019 struct intel_plane *plane;
12021 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
12022 struct intel_plane_state *plane_state;
12024 if ((plane_ids_mask & BIT(plane->id)) == 0)
12027 plane_state = intel_atomic_get_plane_state(state, plane);
12028 if (IS_ERR(plane_state))
12029 return PTR_ERR(plane_state);
12035 int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
12036 struct intel_crtc *crtc)
12038 const struct intel_crtc_state *old_crtc_state =
12039 intel_atomic_get_old_crtc_state(state, crtc);
12040 const struct intel_crtc_state *new_crtc_state =
12041 intel_atomic_get_new_crtc_state(state, crtc);
12043 return intel_crtc_add_planes_to_state(state, crtc,
12044 old_crtc_state->enabled_planes |
12045 new_crtc_state->enabled_planes);
12048 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
12050 /* See {hsw,vlv,ivb}_plane_ratio() */
12051 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
12052 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
12053 IS_IVYBRIDGE(dev_priv) || (INTEL_GEN(dev_priv) >= 11);
12056 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state,
12057 struct intel_crtc *crtc,
12058 struct intel_crtc *other)
12060 const struct intel_plane_state *plane_state;
12061 struct intel_plane *plane;
12065 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12066 if (plane->pipe == crtc->pipe)
12067 plane_ids |= BIT(plane->id);
12070 return intel_crtc_add_planes_to_state(state, other, plane_ids);
12073 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state)
12075 const struct intel_crtc_state *crtc_state;
12076 struct intel_crtc *crtc;
12079 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
12082 if (!crtc_state->bigjoiner)
12085 ret = intel_crtc_add_bigjoiner_planes(state, crtc,
12086 crtc_state->bigjoiner_linked_crtc);
12094 static int intel_atomic_check_planes(struct intel_atomic_state *state)
12096 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
12097 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
12098 struct intel_plane_state *plane_state;
12099 struct intel_plane *plane;
12100 struct intel_crtc *crtc;
12103 ret = icl_add_linked_planes(state);
12107 ret = intel_bigjoiner_add_affected_planes(state);
12111 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12112 ret = intel_plane_atomic_check(state, plane);
12114 drm_dbg_atomic(&dev_priv->drm,
12115 "[PLANE:%d:%s] atomic driver check failed\n",
12116 plane->base.base.id, plane->base.name);
12121 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
12122 new_crtc_state, i) {
12123 u8 old_active_planes, new_active_planes;
12125 ret = icl_check_nv12_planes(new_crtc_state);
12130 * On some platforms the number of active planes affects
12131 * the planes' minimum cdclk calculation. Add such planes
12132 * to the state before we compute the minimum cdclk.
12134 if (!active_planes_affects_min_cdclk(dev_priv))
12137 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
12138 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
12141 * Not only the number of planes, but if the plane configuration had
12142 * changed might already mean we need to recompute min CDCLK,
12143 * because different planes might consume different amount of Dbuf bandwidth
12144 * according to formula: Bw per plane = Pixel rate * bpp * pipe/plane scale factor
12146 if (old_active_planes == new_active_planes)
12149 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
12157 static int intel_atomic_check_cdclk(struct intel_atomic_state *state,
12158 bool *need_cdclk_calc)
12160 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
12161 const struct intel_cdclk_state *old_cdclk_state;
12162 const struct intel_cdclk_state *new_cdclk_state;
12163 struct intel_plane_state *plane_state;
12164 struct intel_bw_state *new_bw_state;
12165 struct intel_plane *plane;
12171 * active_planes bitmask has been updated, and potentially
12172 * affected planes are part of the state. We can now
12173 * compute the minimum cdclk for each plane.
12175 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12176 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc);
12181 old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
12182 new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
12184 if (new_cdclk_state &&
12185 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
12186 *need_cdclk_calc = true;
12188 ret = dev_priv->display.bw_calc_min_cdclk(state);
12192 new_bw_state = intel_atomic_get_new_bw_state(state);
12194 if (!new_cdclk_state || !new_bw_state)
12197 for_each_pipe(dev_priv, pipe) {
12198 min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk);
12201 * Currently do this change only if we need to increase
12203 if (new_bw_state->min_cdclk > min_cdclk)
12204 *need_cdclk_calc = true;
12210 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
12212 struct intel_crtc_state *crtc_state;
12213 struct intel_crtc *crtc;
12216 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
12217 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
12220 ret = intel_crtc_atomic_check(state, crtc);
12222 drm_dbg_atomic(&i915->drm,
12223 "[CRTC:%d:%s] atomic driver check failed\n",
12224 crtc->base.base.id, crtc->base.name);
12232 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
12235 const struct intel_crtc_state *new_crtc_state;
12236 struct intel_crtc *crtc;
12239 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
12240 if (new_crtc_state->hw.enable &&
12241 transcoders & BIT(new_crtc_state->cpu_transcoder) &&
12242 intel_crtc_needs_modeset(new_crtc_state))
12249 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state,
12250 struct intel_crtc *crtc,
12251 struct intel_crtc_state *old_crtc_state,
12252 struct intel_crtc_state *new_crtc_state)
12254 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
12255 struct intel_crtc_state *slave_crtc_state, *master_crtc_state;
12256 struct intel_crtc *slave, *master;
12258 /* slave being enabled, is master is still claiming this crtc? */
12259 if (old_crtc_state->bigjoiner_slave) {
12261 master = old_crtc_state->bigjoiner_linked_crtc;
12262 master_crtc_state = intel_atomic_get_new_crtc_state(state, master);
12263 if (!master_crtc_state || !intel_crtc_needs_modeset(master_crtc_state))
12267 if (!new_crtc_state->bigjoiner)
12270 if (1 + crtc->pipe >= INTEL_NUM_PIPES(dev_priv)) {
12271 DRM_DEBUG_KMS("[CRTC:%d:%s] Big joiner configuration requires "
12272 "CRTC + 1 to be used, doesn't exist\n",
12273 crtc->base.base.id, crtc->base.name);
12277 slave = new_crtc_state->bigjoiner_linked_crtc =
12278 intel_get_crtc_for_pipe(dev_priv, crtc->pipe + 1);
12279 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave);
12281 if (IS_ERR(slave_crtc_state))
12282 return PTR_ERR(slave_crtc_state);
12284 /* master being enabled, slave was already configured? */
12285 if (slave_crtc_state->uapi.enable)
12288 DRM_DEBUG_KMS("[CRTC:%d:%s] Used as slave for big joiner\n",
12289 slave->base.base.id, slave->base.name);
12291 return copy_bigjoiner_crtc_state(slave_crtc_state, new_crtc_state);
12294 DRM_DEBUG_KMS("[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
12295 "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
12296 slave->base.base.id, slave->base.name,
12297 master->base.base.id, master->base.name);
12301 static void kill_bigjoiner_slave(struct intel_atomic_state *state,
12302 struct intel_crtc_state *master_crtc_state)
12304 struct intel_crtc_state *slave_crtc_state =
12305 intel_atomic_get_new_crtc_state(state, master_crtc_state->bigjoiner_linked_crtc);
12307 slave_crtc_state->bigjoiner = master_crtc_state->bigjoiner = false;
12308 slave_crtc_state->bigjoiner_slave = master_crtc_state->bigjoiner_slave = false;
12309 slave_crtc_state->bigjoiner_linked_crtc = master_crtc_state->bigjoiner_linked_crtc = NULL;
12310 intel_crtc_copy_uapi_to_hw_state(state, slave_crtc_state);
12314 * DOC: asynchronous flip implementation
12316 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
12317 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
12318 * Correspondingly, support is currently added for primary plane only.
12320 * Async flip can only change the plane surface address, so anything else
12321 * changing is rejected from the intel_atomic_check_async() function.
12322 * Once this check is cleared, flip done interrupt is enabled using
12323 * the intel_crtc_enable_flip_done() function.
12325 * As soon as the surface address register is written, flip done interrupt is
12326 * generated and the requested events are sent to the usersapce in the interrupt
12327 * handler itself. The timestamp and sequence sent during the flip done event
12328 * correspond to the last vblank and have no relation to the actual time when
12329 * the flip done event was sent.
12331 static int intel_atomic_check_async(struct intel_atomic_state *state)
12333 struct drm_i915_private *i915 = to_i915(state->base.dev);
12334 const struct intel_crtc_state *old_crtc_state, *new_crtc_state;
12335 const struct intel_plane_state *new_plane_state, *old_plane_state;
12336 struct intel_crtc *crtc;
12337 struct intel_plane *plane;
12340 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
12341 new_crtc_state, i) {
12342 if (intel_crtc_needs_modeset(new_crtc_state)) {
12343 drm_dbg_kms(&i915->drm, "Modeset Required. Async flip not supported\n");
12347 if (!new_crtc_state->hw.active) {
12348 drm_dbg_kms(&i915->drm, "CRTC inactive\n");
12351 if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
12352 drm_dbg_kms(&i915->drm,
12353 "Active planes cannot be changed during async flip\n");
12358 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
12359 new_plane_state, i) {
12361 * TODO: Async flip is only supported through the page flip IOCTL
12362 * as of now. So support currently added for primary plane only.
12363 * Support for other planes on platforms on which supports
12364 * this(vlv/chv and icl+) should be added when async flip is
12365 * enabled in the atomic IOCTL path.
12367 if (!plane->async_flip)
12371 * FIXME: This check is kept generic for all platforms.
12372 * Need to verify this for all gen9 and gen10 platforms to enable
12373 * this selectively if required.
12375 switch (new_plane_state->hw.fb->modifier) {
12376 case I915_FORMAT_MOD_X_TILED:
12377 case I915_FORMAT_MOD_Y_TILED:
12378 case I915_FORMAT_MOD_Yf_TILED:
12381 drm_dbg_kms(&i915->drm,
12382 "Linear memory/CCS does not support async flips\n");
12386 if (old_plane_state->color_plane[0].stride !=
12387 new_plane_state->color_plane[0].stride) {
12388 drm_dbg_kms(&i915->drm, "Stride cannot be changed in async flip\n");
12392 if (old_plane_state->hw.fb->modifier !=
12393 new_plane_state->hw.fb->modifier) {
12394 drm_dbg_kms(&i915->drm,
12395 "Framebuffer modifiers cannot be changed in async flip\n");
12399 if (old_plane_state->hw.fb->format !=
12400 new_plane_state->hw.fb->format) {
12401 drm_dbg_kms(&i915->drm,
12402 "Framebuffer format cannot be changed in async flip\n");
12406 if (old_plane_state->hw.rotation !=
12407 new_plane_state->hw.rotation) {
12408 drm_dbg_kms(&i915->drm, "Rotation cannot be changed in async flip\n");
12412 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) ||
12413 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) {
12414 drm_dbg_kms(&i915->drm,
12415 "Plane size/co-ordinates cannot be changed in async flip\n");
12419 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
12420 drm_dbg_kms(&i915->drm, "Alpha value cannot be changed in async flip\n");
12424 if (old_plane_state->hw.pixel_blend_mode !=
12425 new_plane_state->hw.pixel_blend_mode) {
12426 drm_dbg_kms(&i915->drm,
12427 "Pixel blend mode cannot be changed in async flip\n");
12431 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
12432 drm_dbg_kms(&i915->drm,
12433 "Color encoding cannot be changed in async flip\n");
12437 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
12438 drm_dbg_kms(&i915->drm, "Color range cannot be changed in async flip\n");
12446 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state)
12448 struct intel_crtc_state *crtc_state;
12449 struct intel_crtc *crtc;
12452 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
12453 struct intel_crtc_state *linked_crtc_state;
12454 struct intel_crtc *linked_crtc;
12457 if (!crtc_state->bigjoiner)
12460 linked_crtc = crtc_state->bigjoiner_linked_crtc;
12461 linked_crtc_state = intel_atomic_get_crtc_state(&state->base, linked_crtc);
12462 if (IS_ERR(linked_crtc_state))
12463 return PTR_ERR(linked_crtc_state);
12465 if (!intel_crtc_needs_modeset(crtc_state))
12468 linked_crtc_state->uapi.mode_changed = true;
12470 ret = drm_atomic_add_affected_connectors(&state->base,
12471 &linked_crtc->base);
12475 ret = intel_atomic_add_affected_planes(state, linked_crtc);
12480 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
12481 /* Kill old bigjoiner link, we may re-establish afterwards */
12482 if (intel_crtc_needs_modeset(crtc_state) &&
12483 crtc_state->bigjoiner && !crtc_state->bigjoiner_slave)
12484 kill_bigjoiner_slave(state, crtc_state);
12491 * intel_atomic_check - validate state object
12493 * @_state: state to validate
12495 static int intel_atomic_check(struct drm_device *dev,
12496 struct drm_atomic_state *_state)
12498 struct drm_i915_private *dev_priv = to_i915(dev);
12499 struct intel_atomic_state *state = to_intel_atomic_state(_state);
12500 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
12501 struct intel_crtc *crtc;
12503 bool any_ms = false;
12505 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
12506 new_crtc_state, i) {
12507 if (new_crtc_state->inherited != old_crtc_state->inherited)
12508 new_crtc_state->uapi.mode_changed = true;
12511 intel_vrr_check_modeset(state);
12513 ret = drm_atomic_helper_check_modeset(dev, &state->base);
12517 ret = intel_bigjoiner_add_affected_crtcs(state);
12521 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
12522 new_crtc_state, i) {
12523 if (!intel_crtc_needs_modeset(new_crtc_state)) {
12525 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, new_crtc_state);
12530 if (!new_crtc_state->uapi.enable) {
12531 if (!new_crtc_state->bigjoiner_slave) {
12532 intel_crtc_copy_uapi_to_hw_state(state, new_crtc_state);
12538 ret = intel_crtc_prepare_cleared_state(state, new_crtc_state);
12542 ret = intel_modeset_pipe_config(state, new_crtc_state);
12546 ret = intel_atomic_check_bigjoiner(state, crtc, old_crtc_state,
12552 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
12553 new_crtc_state, i) {
12554 if (!intel_crtc_needs_modeset(new_crtc_state))
12557 ret = intel_modeset_pipe_config_late(new_crtc_state);
12561 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
12565 * Check if fastset is allowed by external dependencies like other
12566 * pipes and transcoders.
12568 * Right now it only forces a fullmodeset when the MST master
12569 * transcoder did not changed but the pipe of the master transcoder
12570 * needs a fullmodeset so all slaves also needs to do a fullmodeset or
12571 * in case of port synced crtcs, if one of the synced crtcs
12572 * needs a full modeset, all other synced crtcs should be
12573 * forced a full modeset.
12575 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
12576 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state))
12579 if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
12580 enum transcoder master = new_crtc_state->mst_master_transcoder;
12582 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
12583 new_crtc_state->uapi.mode_changed = true;
12584 new_crtc_state->update_pipe = false;
12588 if (is_trans_port_sync_mode(new_crtc_state)) {
12589 u8 trans = new_crtc_state->sync_mode_slaves_mask;
12591 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
12592 trans |= BIT(new_crtc_state->master_transcoder);
12594 if (intel_cpu_transcoders_need_modeset(state, trans)) {
12595 new_crtc_state->uapi.mode_changed = true;
12596 new_crtc_state->update_pipe = false;
12600 if (new_crtc_state->bigjoiner) {
12601 struct intel_crtc_state *linked_crtc_state =
12602 intel_atomic_get_new_crtc_state(state, new_crtc_state->bigjoiner_linked_crtc);
12604 if (intel_crtc_needs_modeset(linked_crtc_state)) {
12605 new_crtc_state->uapi.mode_changed = true;
12606 new_crtc_state->update_pipe = false;
12611 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
12612 new_crtc_state, i) {
12613 if (intel_crtc_needs_modeset(new_crtc_state)) {
12618 if (!new_crtc_state->update_pipe)
12621 intel_crtc_copy_fastset(old_crtc_state, new_crtc_state);
12624 if (any_ms && !check_digital_port_conflicts(state)) {
12625 drm_dbg_kms(&dev_priv->drm,
12626 "rejecting conflicting digital port configuration\n");
12631 ret = drm_dp_mst_atomic_check(&state->base);
12635 ret = intel_atomic_check_planes(state);
12639 intel_fbc_choose_crtc(dev_priv, state);
12640 ret = calc_watermark_data(state);
12644 ret = intel_bw_atomic_check(state);
12648 ret = intel_atomic_check_cdclk(state, &any_ms);
12653 ret = intel_modeset_checks(state);
12657 ret = intel_modeset_calc_cdclk(state);
12661 intel_modeset_clear_plls(state);
12664 ret = intel_atomic_check_crtcs(state);
12668 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
12669 new_crtc_state, i) {
12670 if (new_crtc_state->uapi.async_flip) {
12671 ret = intel_atomic_check_async(state);
12676 if (!intel_crtc_needs_modeset(new_crtc_state) &&
12677 !new_crtc_state->update_pipe)
12680 intel_dump_pipe_config(new_crtc_state, state,
12681 intel_crtc_needs_modeset(new_crtc_state) ?
12682 "[modeset]" : "[fastset]");
12688 if (ret == -EDEADLK)
12692 * FIXME would probably be nice to know which crtc specifically
12693 * caused the failure, in cases where we can pinpoint it.
12695 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
12697 intel_dump_pipe_config(new_crtc_state, state, "[failed]");
12702 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
12704 struct intel_crtc_state *crtc_state;
12705 struct intel_crtc *crtc;
12708 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
12712 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
12713 bool mode_changed = intel_crtc_needs_modeset(crtc_state);
12715 if (mode_changed || crtc_state->update_pipe ||
12716 crtc_state->uapi.color_mgmt_changed) {
12717 intel_dsb_prepare(crtc_state);
12724 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
12725 struct intel_crtc_state *crtc_state)
12727 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12729 if (!IS_GEN(dev_priv, 2) || crtc_state->active_planes)
12730 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
12732 if (crtc_state->has_pch_encoder) {
12733 enum pipe pch_transcoder =
12734 intel_crtc_pch_transcoder(crtc);
12736 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
12740 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
12741 const struct intel_crtc_state *new_crtc_state)
12743 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
12744 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12747 * Update pipe size and adjust fitter if needed: the reason for this is
12748 * that in compute_mode_changes we check the native mode (not the pfit
12749 * mode) to see if we can flip rather than do a full mode set. In the
12750 * fastboot case, we'll flip, but if we don't update the pipesrc and
12751 * pfit state, we'll end up with a big fb scanned out into the wrong
12754 intel_set_pipe_src_size(new_crtc_state);
12756 /* on skylake this is done by detaching scalers */
12757 if (INTEL_GEN(dev_priv) >= 9) {
12758 skl_detach_scalers(new_crtc_state);
12760 if (new_crtc_state->pch_pfit.enabled)
12761 skl_pfit_enable(new_crtc_state);
12762 } else if (HAS_PCH_SPLIT(dev_priv)) {
12763 if (new_crtc_state->pch_pfit.enabled)
12764 ilk_pfit_enable(new_crtc_state);
12765 else if (old_crtc_state->pch_pfit.enabled)
12766 ilk_pfit_disable(old_crtc_state);
12770 * The register is supposedly single buffered so perhaps
12771 * not 100% correct to do this here. But SKL+ calculate
12772 * this based on the adjust pixel rate so pfit changes do
12773 * affect it and so it must be updated for fastsets.
12774 * HSW/BDW only really need this here for fastboot, after
12775 * that the value should not change without a full modeset.
12777 if (INTEL_GEN(dev_priv) >= 9 ||
12778 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
12779 hsw_set_linetime_wm(new_crtc_state);
12781 if (INTEL_GEN(dev_priv) >= 11)
12782 icl_set_pipe_chicken(crtc);
12785 static void commit_pipe_config(struct intel_atomic_state *state,
12786 struct intel_crtc *crtc)
12788 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
12789 const struct intel_crtc_state *old_crtc_state =
12790 intel_atomic_get_old_crtc_state(state, crtc);
12791 const struct intel_crtc_state *new_crtc_state =
12792 intel_atomic_get_new_crtc_state(state, crtc);
12793 bool modeset = intel_crtc_needs_modeset(new_crtc_state);
12796 * During modesets pipe configuration was programmed as the
12797 * CRTC was enabled.
12800 if (new_crtc_state->uapi.color_mgmt_changed ||
12801 new_crtc_state->update_pipe)
12802 intel_color_commit(new_crtc_state);
12804 if (INTEL_GEN(dev_priv) >= 9)
12805 skl_detach_scalers(new_crtc_state);
12807 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
12808 bdw_set_pipemisc(new_crtc_state);
12810 if (new_crtc_state->update_pipe)
12811 intel_pipe_fastset(old_crtc_state, new_crtc_state);
12813 intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
12816 if (dev_priv->display.atomic_update_watermarks)
12817 dev_priv->display.atomic_update_watermarks(state, crtc);
12820 static void intel_enable_crtc(struct intel_atomic_state *state,
12821 struct intel_crtc *crtc)
12823 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
12824 const struct intel_crtc_state *new_crtc_state =
12825 intel_atomic_get_new_crtc_state(state, crtc);
12827 if (!intel_crtc_needs_modeset(new_crtc_state))
12830 intel_crtc_update_active_timings(new_crtc_state);
12832 dev_priv->display.crtc_enable(state, crtc);
12834 if (new_crtc_state->bigjoiner_slave)
12837 /* vblanks work again, re-enable pipe CRC. */
12838 intel_crtc_enable_pipe_crc(crtc);
12841 static void intel_update_crtc(struct intel_atomic_state *state,
12842 struct intel_crtc *crtc)
12844 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
12845 const struct intel_crtc_state *old_crtc_state =
12846 intel_atomic_get_old_crtc_state(state, crtc);
12847 struct intel_crtc_state *new_crtc_state =
12848 intel_atomic_get_new_crtc_state(state, crtc);
12849 bool modeset = intel_crtc_needs_modeset(new_crtc_state);
12852 if (new_crtc_state->preload_luts &&
12853 (new_crtc_state->uapi.color_mgmt_changed ||
12854 new_crtc_state->update_pipe))
12855 intel_color_load_luts(new_crtc_state);
12857 intel_pre_plane_update(state, crtc);
12859 if (new_crtc_state->update_pipe)
12860 intel_encoders_update_pipe(state, crtc);
12863 if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
12864 intel_fbc_disable(crtc);
12866 intel_fbc_enable(state, crtc);
12868 /* Perform vblank evasion around commit operation */
12869 intel_pipe_update_start(new_crtc_state);
12871 commit_pipe_config(state, crtc);
12873 if (INTEL_GEN(dev_priv) >= 9)
12874 skl_update_planes_on_crtc(state, crtc);
12876 i9xx_update_planes_on_crtc(state, crtc);
12878 intel_pipe_update_end(new_crtc_state);
12881 * We usually enable FIFO underrun interrupts as part of the
12882 * CRTC enable sequence during modesets. But when we inherit a
12883 * valid pipe configuration from the BIOS we need to take care
12884 * of enabling them on the CRTC's first fastset.
12886 if (new_crtc_state->update_pipe && !modeset &&
12887 old_crtc_state->inherited)
12888 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
12891 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
12892 struct intel_crtc_state *old_crtc_state,
12893 struct intel_crtc_state *new_crtc_state,
12894 struct intel_crtc *crtc)
12896 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
12898 drm_WARN_ON(&dev_priv->drm, old_crtc_state->bigjoiner_slave);
12900 intel_crtc_disable_planes(state, crtc);
12903 * We still need special handling for disabling bigjoiner master
12904 * and slaves since for slave we do not have encoder or plls
12905 * so we dont need to disable those.
12907 if (old_crtc_state->bigjoiner) {
12908 intel_crtc_disable_planes(state,
12909 old_crtc_state->bigjoiner_linked_crtc);
12910 old_crtc_state->bigjoiner_linked_crtc->active = false;
12914 * We need to disable pipe CRC before disabling the pipe,
12915 * or we race against vblank off.
12917 intel_crtc_disable_pipe_crc(crtc);
12919 dev_priv->display.crtc_disable(state, crtc);
12920 crtc->active = false;
12921 intel_fbc_disable(crtc);
12922 intel_disable_shared_dpll(old_crtc_state);
12924 /* FIXME unify this for all platforms */
12925 if (!new_crtc_state->hw.active &&
12926 !HAS_GMCH(dev_priv) &&
12927 dev_priv->display.initial_watermarks)
12928 dev_priv->display.initial_watermarks(state, crtc);
12931 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
12933 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
12934 struct intel_crtc *crtc;
12938 /* Only disable port sync and MST slaves */
12939 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
12940 new_crtc_state, i) {
12941 if (!intel_crtc_needs_modeset(new_crtc_state) || old_crtc_state->bigjoiner)
12944 if (!old_crtc_state->hw.active)
12947 /* In case of Transcoder port Sync master slave CRTCs can be
12948 * assigned in any order and we need to make sure that
12949 * slave CRTCs are disabled first and then master CRTC since
12950 * Slave vblanks are masked till Master Vblanks.
12952 if (!is_trans_port_sync_slave(old_crtc_state) &&
12953 !intel_dp_mst_is_slave_trans(old_crtc_state))
12956 intel_pre_plane_update(state, crtc);
12957 intel_old_crtc_state_disables(state, old_crtc_state,
12958 new_crtc_state, crtc);
12959 handled |= BIT(crtc->pipe);
12962 /* Disable everything else left on */
12963 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
12964 new_crtc_state, i) {
12965 if (!intel_crtc_needs_modeset(new_crtc_state) ||
12966 (handled & BIT(crtc->pipe)) ||
12967 old_crtc_state->bigjoiner_slave)
12970 intel_pre_plane_update(state, crtc);
12971 if (old_crtc_state->bigjoiner) {
12972 struct intel_crtc *slave =
12973 old_crtc_state->bigjoiner_linked_crtc;
12975 intel_pre_plane_update(state, slave);
12978 if (old_crtc_state->hw.active)
12979 intel_old_crtc_state_disables(state, old_crtc_state,
12980 new_crtc_state, crtc);
12984 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
12986 struct intel_crtc_state *new_crtc_state;
12987 struct intel_crtc *crtc;
12990 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
12991 if (!new_crtc_state->hw.active)
12994 intel_enable_crtc(state, crtc);
12995 intel_update_crtc(state, crtc);
12999 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
13001 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
13002 struct intel_crtc *crtc;
13003 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
13004 struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
13005 u8 update_pipes = 0, modeset_pipes = 0;
13008 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13009 enum pipe pipe = crtc->pipe;
13011 if (!new_crtc_state->hw.active)
13014 /* ignore allocations for crtc's that have been turned off. */
13015 if (!intel_crtc_needs_modeset(new_crtc_state)) {
13016 entries[pipe] = old_crtc_state->wm.skl.ddb;
13017 update_pipes |= BIT(pipe);
13019 modeset_pipes |= BIT(pipe);
13024 * Whenever the number of active pipes changes, we need to make sure we
13025 * update the pipes in the right order so that their ddb allocations
13026 * never overlap with each other between CRTC updates. Otherwise we'll
13027 * cause pipe underruns and other bad stuff.
13029 * So first lets enable all pipes that do not need a fullmodeset as
13030 * those don't have any external dependency.
13032 while (update_pipes) {
13033 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
13034 new_crtc_state, i) {
13035 enum pipe pipe = crtc->pipe;
13037 if ((update_pipes & BIT(pipe)) == 0)
13040 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
13041 entries, I915_MAX_PIPES, pipe))
13044 entries[pipe] = new_crtc_state->wm.skl.ddb;
13045 update_pipes &= ~BIT(pipe);
13047 intel_update_crtc(state, crtc);
13050 * If this is an already active pipe, it's DDB changed,
13051 * and this isn't the last pipe that needs updating
13052 * then we need to wait for a vblank to pass for the
13053 * new ddb allocation to take effect.
13055 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
13056 &old_crtc_state->wm.skl.ddb) &&
13057 (update_pipes | modeset_pipes))
13058 intel_wait_for_vblank(dev_priv, pipe);
13062 update_pipes = modeset_pipes;
13065 * Enable all pipes that needs a modeset and do not depends on other
13068 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
13069 enum pipe pipe = crtc->pipe;
13071 if ((modeset_pipes & BIT(pipe)) == 0)
13074 if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
13075 is_trans_port_sync_master(new_crtc_state) ||
13076 (new_crtc_state->bigjoiner && !new_crtc_state->bigjoiner_slave))
13079 modeset_pipes &= ~BIT(pipe);
13081 intel_enable_crtc(state, crtc);
13085 * Then we enable all remaining pipes that depend on other
13086 * pipes: MST slaves and port sync masters, big joiner master
13088 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
13089 enum pipe pipe = crtc->pipe;
13091 if ((modeset_pipes & BIT(pipe)) == 0)
13094 modeset_pipes &= ~BIT(pipe);
13096 intel_enable_crtc(state, crtc);
13100 * Finally we do the plane updates/etc. for all pipes that got enabled.
13102 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
13103 enum pipe pipe = crtc->pipe;
13105 if ((update_pipes & BIT(pipe)) == 0)
13108 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
13109 entries, I915_MAX_PIPES, pipe));
13111 entries[pipe] = new_crtc_state->wm.skl.ddb;
13112 update_pipes &= ~BIT(pipe);
13114 intel_update_crtc(state, crtc);
13117 drm_WARN_ON(&dev_priv->drm, modeset_pipes);
13118 drm_WARN_ON(&dev_priv->drm, update_pipes);
13121 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
13123 struct intel_atomic_state *state, *next;
13124 struct llist_node *freed;
13126 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
13127 llist_for_each_entry_safe(state, next, freed, freed)
13128 drm_atomic_state_put(&state->base);
13131 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
13133 struct drm_i915_private *dev_priv =
13134 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
13136 intel_atomic_helper_free_state(dev_priv);
13139 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
13141 struct wait_queue_entry wait_fence, wait_reset;
13142 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
13144 init_wait_entry(&wait_fence, 0);
13145 init_wait_entry(&wait_reset, 0);
13147 prepare_to_wait(&intel_state->commit_ready.wait,
13148 &wait_fence, TASK_UNINTERRUPTIBLE);
13149 prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
13150 I915_RESET_MODESET),
13151 &wait_reset, TASK_UNINTERRUPTIBLE);
13154 if (i915_sw_fence_done(&intel_state->commit_ready) ||
13155 test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
13160 finish_wait(&intel_state->commit_ready.wait, &wait_fence);
13161 finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
13162 I915_RESET_MODESET),
13166 static void intel_cleanup_dsbs(struct intel_atomic_state *state)
13168 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
13169 struct intel_crtc *crtc;
13172 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
13174 intel_dsb_cleanup(old_crtc_state);
13177 static void intel_atomic_cleanup_work(struct work_struct *work)
13179 struct intel_atomic_state *state =
13180 container_of(work, struct intel_atomic_state, base.commit_work);
13181 struct drm_i915_private *i915 = to_i915(state->base.dev);
13183 intel_cleanup_dsbs(state);
13184 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
13185 drm_atomic_helper_commit_cleanup_done(&state->base);
13186 drm_atomic_state_put(&state->base);
13188 intel_atomic_helper_free_state(i915);
13191 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state)
13193 struct drm_i915_private *i915 = to_i915(state->base.dev);
13194 struct intel_plane *plane;
13195 struct intel_plane_state *plane_state;
13198 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
13199 struct drm_framebuffer *fb = plane_state->hw.fb;
13203 fb->modifier != I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
13207 * The layout of the fast clear color value expected by HW
13208 * (the DRM ABI requiring this value to be located in fb at offset 0 of plane#2):
13209 * - 4 x 4 bytes per-channel value
13210 * (in surface type specific float/int format provided by the fb user)
13211 * - 8 bytes native color value used by the display
13212 * (converted/written by GPU during a fast clear operation using the
13213 * above per-channel values)
13215 * The commit's FB prepare hook already ensured that FB obj is pinned and the
13216 * caller made sure that the object is synced wrt. the related color clear value
13219 ret = i915_gem_object_read_from_page(intel_fb_obj(fb),
13220 fb->offsets[2] + 16,
13221 &plane_state->ccval,
13222 sizeof(plane_state->ccval));
13223 /* The above could only fail if the FB obj has an unexpected backing store type. */
13224 drm_WARN_ON(&i915->drm, ret);
13228 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
13230 struct drm_device *dev = state->base.dev;
13231 struct drm_i915_private *dev_priv = to_i915(dev);
13232 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
13233 struct intel_crtc *crtc;
13234 u64 put_domains[I915_MAX_PIPES] = {};
13235 intel_wakeref_t wakeref = 0;
13238 intel_atomic_commit_fence_wait(state);
13240 drm_atomic_helper_wait_for_dependencies(&state->base);
13242 if (state->modeset)
13243 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13245 intel_atomic_prepare_plane_clear_colors(state);
13247 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
13248 new_crtc_state, i) {
13249 if (intel_crtc_needs_modeset(new_crtc_state) ||
13250 new_crtc_state->update_pipe) {
13252 put_domains[crtc->pipe] =
13253 modeset_get_crtc_power_domains(new_crtc_state);
13257 intel_commit_modeset_disables(state);
13259 /* FIXME: Eventually get rid of our crtc->config pointer */
13260 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
13261 crtc->config = new_crtc_state;
13263 if (state->modeset) {
13264 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
13266 intel_set_cdclk_pre_plane_update(state);
13268 intel_modeset_verify_disabled(dev_priv, state);
13271 intel_sagv_pre_plane_update(state);
13273 /* Complete the events for pipes that have now been disabled */
13274 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
13275 bool modeset = intel_crtc_needs_modeset(new_crtc_state);
13277 /* Complete events for now disable pipes here. */
13278 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
13279 spin_lock_irq(&dev->event_lock);
13280 drm_crtc_send_vblank_event(&crtc->base,
13281 new_crtc_state->uapi.event);
13282 spin_unlock_irq(&dev->event_lock);
13284 new_crtc_state->uapi.event = NULL;
13288 if (state->modeset)
13289 intel_encoders_update_prepare(state);
13291 intel_dbuf_pre_plane_update(state);
13293 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
13294 if (new_crtc_state->uapi.async_flip)
13295 intel_crtc_enable_flip_done(state, crtc);
13298 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13299 dev_priv->display.commit_modeset_enables(state);
13301 if (state->modeset) {
13302 intel_encoders_update_complete(state);
13304 intel_set_cdclk_post_plane_update(state);
13307 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
13308 * already, but still need the state for the delayed optimization. To
13310 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
13311 * - schedule that vblank worker _before_ calling hw_done
13312 * - at the start of commit_tail, cancel it _synchrously
13313 * - switch over to the vblank wait helper in the core after that since
13314 * we don't need out special handling any more.
13316 drm_atomic_helper_wait_for_flip_done(dev, &state->base);
13318 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
13319 if (new_crtc_state->uapi.async_flip)
13320 intel_crtc_disable_flip_done(state, crtc);
13322 if (new_crtc_state->hw.active &&
13323 !intel_crtc_needs_modeset(new_crtc_state) &&
13324 !new_crtc_state->preload_luts &&
13325 (new_crtc_state->uapi.color_mgmt_changed ||
13326 new_crtc_state->update_pipe))
13327 intel_color_load_luts(new_crtc_state);
13331 * Now that the vblank has passed, we can go ahead and program the
13332 * optimal watermarks on platforms that need two-step watermark
13335 * TODO: Move this (and other cleanup) to an async worker eventually.
13337 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
13338 new_crtc_state, i) {
13340 * Gen2 reports pipe underruns whenever all planes are disabled.
13341 * So re-enable underrun reporting after some planes get enabled.
13343 * We do this before .optimize_watermarks() so that we have a
13344 * chance of catching underruns with the intermediate watermarks
13345 * vs. the new plane configuration.
13347 if (IS_GEN(dev_priv, 2) && planes_enabling(old_crtc_state, new_crtc_state))
13348 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
13350 if (dev_priv->display.optimize_watermarks)
13351 dev_priv->display.optimize_watermarks(state, crtc);
13354 intel_dbuf_post_plane_update(state);
13356 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13357 intel_post_plane_update(state, crtc);
13359 modeset_put_crtc_power_domains(crtc, put_domains[crtc->pipe]);
13361 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
13364 * DSB cleanup is done in cleanup_work aligning with framebuffer
13365 * cleanup. So copy and reset the dsb structure to sync with
13366 * commit_done and later do dsb cleanup in cleanup_work.
13368 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb);
13371 /* Underruns don't always raise interrupts, so check manually */
13372 intel_check_cpu_fifo_underruns(dev_priv);
13373 intel_check_pch_fifo_underruns(dev_priv);
13375 if (state->modeset)
13376 intel_verify_planes(state);
13378 intel_sagv_post_plane_update(state);
13380 drm_atomic_helper_commit_hw_done(&state->base);
13382 if (state->modeset) {
13383 /* As one of the primary mmio accessors, KMS has a high
13384 * likelihood of triggering bugs in unclaimed access. After we
13385 * finish modesetting, see if an error has been flagged, and if
13386 * so enable debugging for the next modeset - and hope we catch
13389 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
13390 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
13392 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
13395 * Defer the cleanup of the old state to a separate worker to not
13396 * impede the current task (userspace for blocking modesets) that
13397 * are executed inline. For out-of-line asynchronous modesets/flips,
13398 * deferring to a new worker seems overkill, but we would place a
13399 * schedule point (cond_resched()) here anyway to keep latencies
13402 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
13403 queue_work(system_highpri_wq, &state->base.commit_work);
13406 static void intel_atomic_commit_work(struct work_struct *work)
13408 struct intel_atomic_state *state =
13409 container_of(work, struct intel_atomic_state, base.commit_work);
13411 intel_atomic_commit_tail(state);
13414 static int __i915_sw_fence_call
13415 intel_atomic_commit_ready(struct i915_sw_fence *fence,
13416 enum i915_sw_fence_notify notify)
13418 struct intel_atomic_state *state =
13419 container_of(fence, struct intel_atomic_state, commit_ready);
13422 case FENCE_COMPLETE:
13423 /* we do blocking waits in the worker, nothing to do here */
13427 struct intel_atomic_helper *helper =
13428 &to_i915(state->base.dev)->atomic_helper;
13430 if (llist_add(&state->freed, &helper->free_list))
13431 schedule_work(&helper->free_work);
13436 return NOTIFY_DONE;
13439 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
13441 struct intel_plane_state *old_plane_state, *new_plane_state;
13442 struct intel_plane *plane;
13445 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
13446 new_plane_state, i)
13447 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
13448 to_intel_frontbuffer(new_plane_state->hw.fb),
13449 plane->frontbuffer_bit);
13452 static int intel_atomic_commit(struct drm_device *dev,
13453 struct drm_atomic_state *_state,
13456 struct intel_atomic_state *state = to_intel_atomic_state(_state);
13457 struct drm_i915_private *dev_priv = to_i915(dev);
13460 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
13462 drm_atomic_state_get(&state->base);
13463 i915_sw_fence_init(&state->commit_ready,
13464 intel_atomic_commit_ready);
13467 * The intel_legacy_cursor_update() fast path takes care
13468 * of avoiding the vblank waits for simple cursor
13469 * movement and flips. For cursor on/off and size changes,
13470 * we want to perform the vblank waits so that watermark
13471 * updates happen during the correct frames. Gen9+ have
13472 * double buffered watermarks and so shouldn't need this.
13474 * Unset state->legacy_cursor_update before the call to
13475 * drm_atomic_helper_setup_commit() because otherwise
13476 * drm_atomic_helper_wait_for_flip_done() is a noop and
13477 * we get FIFO underruns because we didn't wait
13480 * FIXME doing watermarks and fb cleanup from a vblank worker
13481 * (assuming we had any) would solve these problems.
13483 if (INTEL_GEN(dev_priv) < 9 && state->base.legacy_cursor_update) {
13484 struct intel_crtc_state *new_crtc_state;
13485 struct intel_crtc *crtc;
13488 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
13489 if (new_crtc_state->wm.need_postvbl_update ||
13490 new_crtc_state->update_wm_post)
13491 state->base.legacy_cursor_update = false;
13494 ret = intel_atomic_prepare_commit(state);
13496 drm_dbg_atomic(&dev_priv->drm,
13497 "Preparing state failed with %i\n", ret);
13498 i915_sw_fence_commit(&state->commit_ready);
13499 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
13503 ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
13505 ret = drm_atomic_helper_swap_state(&state->base, true);
13507 intel_atomic_swap_global_state(state);
13510 struct intel_crtc_state *new_crtc_state;
13511 struct intel_crtc *crtc;
13514 i915_sw_fence_commit(&state->commit_ready);
13516 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
13517 intel_dsb_cleanup(new_crtc_state);
13519 drm_atomic_helper_cleanup_planes(dev, &state->base);
13520 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
13523 intel_shared_dpll_swap_state(state);
13524 intel_atomic_track_fbs(state);
13526 drm_atomic_state_get(&state->base);
13527 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
13529 i915_sw_fence_commit(&state->commit_ready);
13530 if (nonblock && state->modeset) {
13531 queue_work(dev_priv->modeset_wq, &state->base.commit_work);
13532 } else if (nonblock) {
13533 queue_work(dev_priv->flip_wq, &state->base.commit_work);
13535 if (state->modeset)
13536 flush_workqueue(dev_priv->modeset_wq);
13537 intel_atomic_commit_tail(state);
13543 struct wait_rps_boost {
13544 struct wait_queue_entry wait;
13546 struct drm_crtc *crtc;
13547 struct i915_request *request;
13550 static int do_rps_boost(struct wait_queue_entry *_wait,
13551 unsigned mode, int sync, void *key)
13553 struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
13554 struct i915_request *rq = wait->request;
13557 * If we missed the vblank, but the request is already running it
13558 * is reasonable to assume that it will complete before the next
13559 * vblank without our intervention, so leave RPS alone.
13561 if (!i915_request_started(rq))
13562 intel_rps_boost(rq);
13563 i915_request_put(rq);
13565 drm_crtc_vblank_put(wait->crtc);
13567 list_del(&wait->wait.entry);
13572 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
13573 struct dma_fence *fence)
13575 struct wait_rps_boost *wait;
13577 if (!dma_fence_is_i915(fence))
13580 if (INTEL_GEN(to_i915(crtc->dev)) < 6)
13583 if (drm_crtc_vblank_get(crtc))
13586 wait = kmalloc(sizeof(*wait), GFP_KERNEL);
13588 drm_crtc_vblank_put(crtc);
13592 wait->request = to_request(dma_fence_get(fence));
13595 wait->wait.func = do_rps_boost;
13596 wait->wait.flags = 0;
13598 add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
13601 int intel_plane_pin_fb(struct intel_plane_state *plane_state)
13603 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
13604 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
13605 struct drm_framebuffer *fb = plane_state->hw.fb;
13606 struct i915_vma *vma;
13608 if (plane->id == PLANE_CURSOR &&
13609 INTEL_INFO(dev_priv)->display.cursor_needs_physical) {
13610 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13611 const int align = intel_cursor_alignment(dev_priv);
13614 err = i915_gem_object_attach_phys(obj, align);
13619 vma = intel_pin_and_fence_fb_obj(fb,
13620 &plane_state->view,
13621 intel_plane_uses_fence(plane_state),
13622 &plane_state->flags);
13624 return PTR_ERR(vma);
13626 plane_state->vma = vma;
13631 void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
13633 struct i915_vma *vma;
13635 vma = fetch_and_zero(&old_plane_state->vma);
13637 intel_unpin_fb_vma(vma, old_plane_state->flags);
13641 * intel_prepare_plane_fb - Prepare fb for usage on plane
13642 * @_plane: drm plane to prepare for
13643 * @_new_plane_state: the plane state being prepared
13645 * Prepares a framebuffer for usage on a display plane. Generally this
13646 * involves pinning the underlying object and updating the frontbuffer tracking
13647 * bits. Some older platforms need special physical address handling for
13650 * Returns 0 on success, negative error code on failure.
13653 intel_prepare_plane_fb(struct drm_plane *_plane,
13654 struct drm_plane_state *_new_plane_state)
13656 struct i915_sched_attr attr = {
13657 .priority = I915_USER_PRIORITY(I915_PRIORITY_DISPLAY),
13659 struct intel_plane *plane = to_intel_plane(_plane);
13660 struct intel_plane_state *new_plane_state =
13661 to_intel_plane_state(_new_plane_state);
13662 struct intel_atomic_state *state =
13663 to_intel_atomic_state(new_plane_state->uapi.state);
13664 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
13665 const struct intel_plane_state *old_plane_state =
13666 intel_atomic_get_old_plane_state(state, plane);
13667 struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb);
13668 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_plane_state->hw.fb);
13672 const struct intel_crtc_state *crtc_state =
13673 intel_atomic_get_new_crtc_state(state,
13674 to_intel_crtc(old_plane_state->hw.crtc));
13676 /* Big Hammer, we also need to ensure that any pending
13677 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13678 * current scanout is retired before unpinning the old
13679 * framebuffer. Note that we rely on userspace rendering
13680 * into the buffer attached to the pipe they are waiting
13681 * on. If not, userspace generates a GPU hang with IPEHR
13682 * point to the MI_WAIT_FOR_EVENT.
13684 * This should only fail upon a hung GPU, in which case we
13685 * can safely continue.
13687 if (intel_crtc_needs_modeset(crtc_state)) {
13688 ret = i915_sw_fence_await_reservation(&state->commit_ready,
13689 old_obj->base.resv, NULL,
13697 if (new_plane_state->uapi.fence) { /* explicit fencing */
13698 i915_gem_fence_wait_priority(new_plane_state->uapi.fence,
13700 ret = i915_sw_fence_await_dma_fence(&state->commit_ready,
13701 new_plane_state->uapi.fence,
13702 i915_fence_timeout(dev_priv),
13711 ret = i915_gem_object_pin_pages(obj);
13715 ret = intel_plane_pin_fb(new_plane_state);
13717 i915_gem_object_unpin_pages(obj);
13721 i915_gem_object_wait_priority(obj, 0, &attr);
13722 i915_gem_object_flush_frontbuffer(obj, ORIGIN_DIRTYFB);
13724 if (!new_plane_state->uapi.fence) { /* implicit fencing */
13725 struct dma_fence *fence;
13727 ret = i915_sw_fence_await_reservation(&state->commit_ready,
13728 obj->base.resv, NULL,
13730 i915_fence_timeout(dev_priv),
13735 fence = dma_resv_get_excl_rcu(obj->base.resv);
13737 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
13739 dma_fence_put(fence);
13742 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
13743 new_plane_state->uapi.fence);
13747 * We declare pageflips to be interactive and so merit a small bias
13748 * towards upclocking to deliver the frame on time. By only changing
13749 * the RPS thresholds to sample more regularly and aim for higher
13750 * clocks we can hopefully deliver low power workloads (like kodi)
13751 * that are not quite steady state without resorting to forcing
13752 * maximum clocks following a vblank miss (see do_rps_boost()).
13754 if (!state->rps_interactive) {
13755 intel_rps_mark_interactive(&dev_priv->gt.rps, true);
13756 state->rps_interactive = true;
13762 intel_plane_unpin_fb(new_plane_state);
13768 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13769 * @plane: drm plane to clean up for
13770 * @_old_plane_state: the state from the previous modeset
13772 * Cleans up a framebuffer that has just been removed from a plane.
13775 intel_cleanup_plane_fb(struct drm_plane *plane,
13776 struct drm_plane_state *_old_plane_state)
13778 struct intel_plane_state *old_plane_state =
13779 to_intel_plane_state(_old_plane_state);
13780 struct intel_atomic_state *state =
13781 to_intel_atomic_state(old_plane_state->uapi.state);
13782 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13783 struct drm_i915_gem_object *obj = intel_fb_obj(old_plane_state->hw.fb);
13788 if (state->rps_interactive) {
13789 intel_rps_mark_interactive(&dev_priv->gt.rps, false);
13790 state->rps_interactive = false;
13793 /* Should only be called after a successful intel_prepare_plane_fb()! */
13794 intel_plane_unpin_fb(old_plane_state);
13798 * intel_plane_destroy - destroy a plane
13799 * @plane: plane to destroy
13801 * Common destruction function for all types of planes (primary, cursor,
13804 void intel_plane_destroy(struct drm_plane *plane)
13806 drm_plane_cleanup(plane);
13807 kfree(to_intel_plane(plane));
13810 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv)
13812 struct intel_plane *plane;
13814 for_each_intel_plane(&dev_priv->drm, plane) {
13815 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
13818 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base);
13823 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
13824 struct drm_file *file)
13826 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13827 struct drm_crtc *drmmode_crtc;
13828 struct intel_crtc *crtc;
13830 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
13834 crtc = to_intel_crtc(drmmode_crtc);
13835 pipe_from_crtc_id->pipe = crtc->pipe;
13840 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
13842 struct drm_device *dev = encoder->base.dev;
13843 struct intel_encoder *source_encoder;
13844 u32 possible_clones = 0;
13846 for_each_intel_encoder(dev, source_encoder) {
13847 if (encoders_cloneable(encoder, source_encoder))
13848 possible_clones |= drm_encoder_mask(&source_encoder->base);
13851 return possible_clones;
13854 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
13856 struct drm_device *dev = encoder->base.dev;
13857 struct intel_crtc *crtc;
13858 u32 possible_crtcs = 0;
13860 for_each_intel_crtc(dev, crtc) {
13861 if (encoder->pipe_mask & BIT(crtc->pipe))
13862 possible_crtcs |= drm_crtc_mask(&crtc->base);
13865 return possible_crtcs;
13868 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
13870 if (!IS_MOBILE(dev_priv))
13873 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)
13876 if (IS_GEN(dev_priv, 5) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
13882 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
13884 if (INTEL_GEN(dev_priv) >= 9)
13887 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
13890 if (HAS_PCH_LPT_H(dev_priv) &&
13891 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
13894 /* DDI E can't be used if DDI A requires 4 lanes */
13895 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
13898 if (!dev_priv->vbt.int_crt_support)
13904 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
13906 struct intel_encoder *encoder;
13907 bool dpd_is_edp = false;
13909 intel_pps_unlock_regs_wa(dev_priv);
13911 if (!HAS_DISPLAY(dev_priv))
13914 if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
13915 intel_ddi_init(dev_priv, PORT_A);
13916 intel_ddi_init(dev_priv, PORT_B);
13917 intel_ddi_init(dev_priv, PORT_TC1);
13918 intel_ddi_init(dev_priv, PORT_TC2);
13919 } else if (INTEL_GEN(dev_priv) >= 12) {
13920 intel_ddi_init(dev_priv, PORT_A);
13921 intel_ddi_init(dev_priv, PORT_B);
13922 intel_ddi_init(dev_priv, PORT_TC1);
13923 intel_ddi_init(dev_priv, PORT_TC2);
13924 intel_ddi_init(dev_priv, PORT_TC3);
13925 intel_ddi_init(dev_priv, PORT_TC4);
13926 intel_ddi_init(dev_priv, PORT_TC5);
13927 intel_ddi_init(dev_priv, PORT_TC6);
13928 icl_dsi_init(dev_priv);
13929 } else if (IS_JSL_EHL(dev_priv)) {
13930 intel_ddi_init(dev_priv, PORT_A);
13931 intel_ddi_init(dev_priv, PORT_B);
13932 intel_ddi_init(dev_priv, PORT_C);
13933 intel_ddi_init(dev_priv, PORT_D);
13934 icl_dsi_init(dev_priv);
13935 } else if (IS_GEN(dev_priv, 11)) {
13936 intel_ddi_init(dev_priv, PORT_A);
13937 intel_ddi_init(dev_priv, PORT_B);
13938 intel_ddi_init(dev_priv, PORT_C);
13939 intel_ddi_init(dev_priv, PORT_D);
13940 intel_ddi_init(dev_priv, PORT_E);
13942 * On some ICL SKUs port F is not present. No strap bits for
13943 * this, so rely on VBT.
13944 * Work around broken VBTs on SKUs known to have no port F.
13946 if (IS_ICL_WITH_PORT_F(dev_priv) &&
13947 intel_bios_is_port_present(dev_priv, PORT_F))
13948 intel_ddi_init(dev_priv, PORT_F);
13950 icl_dsi_init(dev_priv);
13951 } else if (IS_GEN9_LP(dev_priv)) {
13953 * FIXME: Broxton doesn't support port detection via the
13954 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13955 * detect the ports.
13957 intel_ddi_init(dev_priv, PORT_A);
13958 intel_ddi_init(dev_priv, PORT_B);
13959 intel_ddi_init(dev_priv, PORT_C);
13961 vlv_dsi_init(dev_priv);
13962 } else if (HAS_DDI(dev_priv)) {
13965 if (intel_ddi_crt_present(dev_priv))
13966 intel_crt_init(dev_priv);
13969 * Haswell uses DDI functions to detect digital outputs.
13970 * On SKL pre-D0 the strap isn't connected, so we assume
13973 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
13974 /* WaIgnoreDDIAStrap: skl */
13975 if (found || IS_GEN9_BC(dev_priv))
13976 intel_ddi_init(dev_priv, PORT_A);
13978 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
13980 found = intel_de_read(dev_priv, SFUSE_STRAP);
13982 if (found & SFUSE_STRAP_DDIB_DETECTED)
13983 intel_ddi_init(dev_priv, PORT_B);
13984 if (found & SFUSE_STRAP_DDIC_DETECTED)
13985 intel_ddi_init(dev_priv, PORT_C);
13986 if (found & SFUSE_STRAP_DDID_DETECTED)
13987 intel_ddi_init(dev_priv, PORT_D);
13988 if (found & SFUSE_STRAP_DDIF_DETECTED)
13989 intel_ddi_init(dev_priv, PORT_F);
13991 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
13993 if (IS_GEN9_BC(dev_priv) &&
13994 intel_bios_is_port_present(dev_priv, PORT_E))
13995 intel_ddi_init(dev_priv, PORT_E);
13997 } else if (HAS_PCH_SPLIT(dev_priv)) {
14001 * intel_edp_init_connector() depends on this completing first,
14002 * to prevent the registration of both eDP and LVDS and the
14003 * incorrect sharing of the PPS.
14005 intel_lvds_init(dev_priv);
14006 intel_crt_init(dev_priv);
14008 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
14010 if (ilk_has_edp_a(dev_priv))
14011 intel_dp_init(dev_priv, DP_A, PORT_A);
14013 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
14014 /* PCH SDVOB multiplex with HDMIB */
14015 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
14017 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
14018 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
14019 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
14022 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
14023 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
14025 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED)
14026 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
14028 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
14029 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
14031 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
14032 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
14033 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14034 bool has_edp, has_port;
14036 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
14037 intel_crt_init(dev_priv);
14040 * The DP_DETECTED bit is the latched state of the DDC
14041 * SDA pin at boot. However since eDP doesn't require DDC
14042 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14043 * eDP ports may have been muxed to an alternate function.
14044 * Thus we can't rely on the DP_DETECTED bit alone to detect
14045 * eDP ports. Consult the VBT as well as DP_DETECTED to
14046 * detect eDP ports.
14048 * Sadly the straps seem to be missing sometimes even for HDMI
14049 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14050 * and VBT for the presence of the port. Additionally we can't
14051 * trust the port type the VBT declares as we've seen at least
14052 * HDMI ports that the VBT claim are DP or eDP.
14054 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
14055 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14056 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
14057 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
14058 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14059 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
14061 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
14062 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14063 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
14064 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
14065 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14066 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
14068 if (IS_CHERRYVIEW(dev_priv)) {
14070 * eDP not supported on port D,
14071 * so no need to worry about it
14073 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14074 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
14075 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
14076 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
14077 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
14080 vlv_dsi_init(dev_priv);
14081 } else if (IS_PINEVIEW(dev_priv)) {
14082 intel_lvds_init(dev_priv);
14083 intel_crt_init(dev_priv);
14084 } else if (IS_GEN_RANGE(dev_priv, 3, 4)) {
14085 bool found = false;
14087 if (IS_MOBILE(dev_priv))
14088 intel_lvds_init(dev_priv);
14090 intel_crt_init(dev_priv);
14092 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
14093 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
14094 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
14095 if (!found && IS_G4X(dev_priv)) {
14096 drm_dbg_kms(&dev_priv->drm,
14097 "probing HDMI on SDVOB\n");
14098 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
14101 if (!found && IS_G4X(dev_priv))
14102 intel_dp_init(dev_priv, DP_B, PORT_B);
14105 /* Before G4X SDVOC doesn't have its own detect register */
14107 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
14108 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");
14109 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
14112 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) {
14114 if (IS_G4X(dev_priv)) {
14115 drm_dbg_kms(&dev_priv->drm,
14116 "probing HDMI on SDVOC\n");
14117 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
14119 if (IS_G4X(dev_priv))
14120 intel_dp_init(dev_priv, DP_C, PORT_C);
14123 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED))
14124 intel_dp_init(dev_priv, DP_D, PORT_D);
14126 if (SUPPORTS_TV(dev_priv))
14127 intel_tv_init(dev_priv);
14128 } else if (IS_GEN(dev_priv, 2)) {
14129 if (IS_I85X(dev_priv))
14130 intel_lvds_init(dev_priv);
14132 intel_crt_init(dev_priv);
14133 intel_dvo_init(dev_priv);
14136 intel_psr_init(dev_priv);
14138 for_each_intel_encoder(&dev_priv->drm, encoder) {
14139 encoder->base.possible_crtcs =
14140 intel_encoder_possible_crtcs(encoder);
14141 encoder->base.possible_clones =
14142 intel_encoder_possible_clones(encoder);
14145 intel_init_pch_refclk(dev_priv);
14147 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
14150 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14152 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14154 drm_framebuffer_cleanup(fb);
14155 intel_frontbuffer_put(intel_fb->frontbuffer);
14160 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14161 struct drm_file *file,
14162 unsigned int *handle)
14164 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14165 struct drm_i915_private *i915 = to_i915(obj->base.dev);
14167 if (obj->userptr.mm) {
14168 drm_dbg(&i915->drm,
14169 "attempting to use a userptr for a framebuffer, denied\n");
14173 return drm_gem_handle_create(file, &obj->base, handle);
14176 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14177 struct drm_file *file,
14178 unsigned flags, unsigned color,
14179 struct drm_clip_rect *clips,
14180 unsigned num_clips)
14182 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14184 i915_gem_object_flush_if_display(obj);
14185 intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
14190 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14191 .destroy = intel_user_framebuffer_destroy,
14192 .create_handle = intel_user_framebuffer_create_handle,
14193 .dirty = intel_user_framebuffer_dirty,
14196 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
14197 struct drm_i915_gem_object *obj,
14198 struct drm_mode_fb_cmd2 *mode_cmd)
14200 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14201 struct drm_framebuffer *fb = &intel_fb->base;
14203 unsigned int tiling, stride;
14207 intel_fb->frontbuffer = intel_frontbuffer_get(obj);
14208 if (!intel_fb->frontbuffer)
14211 i915_gem_object_lock(obj, NULL);
14212 tiling = i915_gem_object_get_tiling(obj);
14213 stride = i915_gem_object_get_stride(obj);
14214 i915_gem_object_unlock(obj);
14216 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14218 * If there's a fence, enforce that
14219 * the fb modifier and tiling mode match.
14221 if (tiling != I915_TILING_NONE &&
14222 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14223 drm_dbg_kms(&dev_priv->drm,
14224 "tiling_mode doesn't match fb modifier\n");
14228 if (tiling == I915_TILING_X) {
14229 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14230 } else if (tiling == I915_TILING_Y) {
14231 drm_dbg_kms(&dev_priv->drm,
14232 "No Y tiling for legacy addfb\n");
14237 if (!drm_any_plane_has_format(&dev_priv->drm,
14238 mode_cmd->pixel_format,
14239 mode_cmd->modifier[0])) {
14240 struct drm_format_name_buf format_name;
14242 drm_dbg_kms(&dev_priv->drm,
14243 "unsupported pixel format %s / modifier 0x%llx\n",
14244 drm_get_format_name(mode_cmd->pixel_format,
14246 mode_cmd->modifier[0]);
14251 * gen2/3 display engine uses the fence if present,
14252 * so the tiling mode must match the fb modifier exactly.
14254 if (INTEL_GEN(dev_priv) < 4 &&
14255 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14256 drm_dbg_kms(&dev_priv->drm,
14257 "tiling_mode must match fb modifier exactly on gen2/3\n");
14261 max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
14262 mode_cmd->modifier[0]);
14263 if (mode_cmd->pitches[0] > max_stride) {
14264 drm_dbg_kms(&dev_priv->drm,
14265 "%s pitch (%u) must be at most %d\n",
14266 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
14267 "tiled" : "linear",
14268 mode_cmd->pitches[0], max_stride);
14273 * If there's a fence, enforce that
14274 * the fb pitch and fence stride match.
14276 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
14277 drm_dbg_kms(&dev_priv->drm,
14278 "pitch (%d) must match tiling stride (%d)\n",
14279 mode_cmd->pitches[0], stride);
14283 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14284 if (mode_cmd->offsets[0] != 0) {
14285 drm_dbg_kms(&dev_priv->drm,
14286 "plane 0 offset (0x%08x) must be 0\n",
14287 mode_cmd->offsets[0]);
14291 drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
14293 for (i = 0; i < fb->format->num_planes; i++) {
14294 u32 stride_alignment;
14296 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
14297 drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n",
14302 stride_alignment = intel_fb_stride_alignment(fb, i);
14303 if (fb->pitches[i] & (stride_alignment - 1)) {
14304 drm_dbg_kms(&dev_priv->drm,
14305 "plane %d pitch (%d) must be at least %u byte aligned\n",
14306 i, fb->pitches[i], stride_alignment);
14310 if (is_gen12_ccs_plane(fb, i) && !is_gen12_ccs_cc_plane(fb, i)) {
14311 int ccs_aux_stride = gen12_ccs_aux_stride(fb, i);
14313 if (fb->pitches[i] != ccs_aux_stride) {
14314 drm_dbg_kms(&dev_priv->drm,
14315 "ccs aux plane %d pitch (%d) must be %d\n",
14317 fb->pitches[i], ccs_aux_stride);
14322 fb->obj[i] = &obj->base;
14325 ret = intel_fill_fb_info(dev_priv, fb);
14329 ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
14331 drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret);
14338 intel_frontbuffer_put(intel_fb->frontbuffer);
14342 static struct drm_framebuffer *
14343 intel_user_framebuffer_create(struct drm_device *dev,
14344 struct drm_file *filp,
14345 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14347 struct drm_framebuffer *fb;
14348 struct drm_i915_gem_object *obj;
14349 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14351 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14353 return ERR_PTR(-ENOENT);
14355 fb = intel_framebuffer_create(obj, &mode_cmd);
14356 i915_gem_object_put(obj);
14361 static enum drm_mode_status
14362 intel_mode_valid(struct drm_device *dev,
14363 const struct drm_display_mode *mode)
14365 struct drm_i915_private *dev_priv = to_i915(dev);
14366 int hdisplay_max, htotal_max;
14367 int vdisplay_max, vtotal_max;
14370 * Can't reject DBLSCAN here because Xorg ddxen can add piles
14371 * of DBLSCAN modes to the output's mode list when they detect
14372 * the scaling mode property on the connector. And they don't
14373 * ask the kernel to validate those modes in any way until
14374 * modeset time at which point the client gets a protocol error.
14375 * So in order to not upset those clients we silently ignore the
14376 * DBLSCAN flag on such connectors. For other connectors we will
14377 * reject modes with the DBLSCAN flag in encoder->compute_config().
14378 * And we always reject DBLSCAN modes in connector->mode_valid()
14379 * as we never want such modes on the connector's mode list.
14382 if (mode->vscan > 1)
14383 return MODE_NO_VSCAN;
14385 if (mode->flags & DRM_MODE_FLAG_HSKEW)
14386 return MODE_H_ILLEGAL;
14388 if (mode->flags & (DRM_MODE_FLAG_CSYNC |
14389 DRM_MODE_FLAG_NCSYNC |
14390 DRM_MODE_FLAG_PCSYNC))
14393 if (mode->flags & (DRM_MODE_FLAG_BCAST |
14394 DRM_MODE_FLAG_PIXMUX |
14395 DRM_MODE_FLAG_CLKDIV2))
14398 /* Transcoder timing limits */
14399 if (INTEL_GEN(dev_priv) >= 11) {
14400 hdisplay_max = 16384;
14401 vdisplay_max = 8192;
14402 htotal_max = 16384;
14404 } else if (INTEL_GEN(dev_priv) >= 9 ||
14405 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
14406 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
14407 vdisplay_max = 4096;
14410 } else if (INTEL_GEN(dev_priv) >= 3) {
14411 hdisplay_max = 4096;
14412 vdisplay_max = 4096;
14416 hdisplay_max = 2048;
14417 vdisplay_max = 2048;
14422 if (mode->hdisplay > hdisplay_max ||
14423 mode->hsync_start > htotal_max ||
14424 mode->hsync_end > htotal_max ||
14425 mode->htotal > htotal_max)
14426 return MODE_H_ILLEGAL;
14428 if (mode->vdisplay > vdisplay_max ||
14429 mode->vsync_start > vtotal_max ||
14430 mode->vsync_end > vtotal_max ||
14431 mode->vtotal > vtotal_max)
14432 return MODE_V_ILLEGAL;
14434 if (INTEL_GEN(dev_priv) >= 5) {
14435 if (mode->hdisplay < 64 ||
14436 mode->htotal - mode->hdisplay < 32)
14437 return MODE_H_ILLEGAL;
14439 if (mode->vtotal - mode->vdisplay < 5)
14440 return MODE_V_ILLEGAL;
14442 if (mode->htotal - mode->hdisplay < 32)
14443 return MODE_H_ILLEGAL;
14445 if (mode->vtotal - mode->vdisplay < 3)
14446 return MODE_V_ILLEGAL;
14452 enum drm_mode_status
14453 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
14454 const struct drm_display_mode *mode,
14457 int plane_width_max, plane_height_max;
14460 * intel_mode_valid() should be
14461 * sufficient on older platforms.
14463 if (INTEL_GEN(dev_priv) < 9)
14467 * Most people will probably want a fullscreen
14468 * plane so let's not advertize modes that are
14469 * too big for that.
14471 if (INTEL_GEN(dev_priv) >= 11) {
14472 plane_width_max = 5120 << bigjoiner;
14473 plane_height_max = 4320;
14475 plane_width_max = 5120;
14476 plane_height_max = 4096;
14479 if (mode->hdisplay > plane_width_max)
14480 return MODE_H_ILLEGAL;
14482 if (mode->vdisplay > plane_height_max)
14483 return MODE_V_ILLEGAL;
14488 static const struct drm_mode_config_funcs intel_mode_funcs = {
14489 .fb_create = intel_user_framebuffer_create,
14490 .get_format_info = intel_get_format_info,
14491 .output_poll_changed = intel_fbdev_output_poll_changed,
14492 .mode_valid = intel_mode_valid,
14493 .atomic_check = intel_atomic_check,
14494 .atomic_commit = intel_atomic_commit,
14495 .atomic_state_alloc = intel_atomic_state_alloc,
14496 .atomic_state_clear = intel_atomic_state_clear,
14497 .atomic_state_free = intel_atomic_state_free,
14501 * intel_init_display_hooks - initialize the display modesetting hooks
14502 * @dev_priv: device private
14504 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14506 intel_init_cdclk_hooks(dev_priv);
14508 intel_dpll_init_clock_hook(dev_priv);
14510 if (INTEL_GEN(dev_priv) >= 9) {
14511 dev_priv->display.get_pipe_config = hsw_get_pipe_config;
14512 dev_priv->display.crtc_enable = hsw_crtc_enable;
14513 dev_priv->display.crtc_disable = hsw_crtc_disable;
14514 } else if (HAS_DDI(dev_priv)) {
14515 dev_priv->display.get_pipe_config = hsw_get_pipe_config;
14516 dev_priv->display.crtc_enable = hsw_crtc_enable;
14517 dev_priv->display.crtc_disable = hsw_crtc_disable;
14518 } else if (HAS_PCH_SPLIT(dev_priv)) {
14519 dev_priv->display.get_pipe_config = ilk_get_pipe_config;
14520 dev_priv->display.crtc_enable = ilk_crtc_enable;
14521 dev_priv->display.crtc_disable = ilk_crtc_disable;
14522 } else if (IS_CHERRYVIEW(dev_priv) ||
14523 IS_VALLEYVIEW(dev_priv)) {
14524 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14525 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14526 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14528 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14529 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14530 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14533 intel_fdi_init_hook(dev_priv);
14535 if (INTEL_GEN(dev_priv) >= 9) {
14536 dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables;
14537 dev_priv->display.get_initial_plane_config = skl_get_initial_plane_config;
14539 dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables;
14540 dev_priv->display.get_initial_plane_config = i9xx_get_initial_plane_config;
14545 void intel_modeset_init_hw(struct drm_i915_private *i915)
14547 struct intel_cdclk_state *cdclk_state =
14548 to_intel_cdclk_state(i915->cdclk.obj.state);
14550 intel_update_cdclk(i915);
14551 intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
14552 cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;
14555 static int sanitize_watermarks_add_affected(struct drm_atomic_state *state)
14557 struct drm_plane *plane;
14558 struct intel_crtc *crtc;
14560 for_each_intel_crtc(state->dev, crtc) {
14561 struct intel_crtc_state *crtc_state;
14563 crtc_state = intel_atomic_get_crtc_state(state, crtc);
14564 if (IS_ERR(crtc_state))
14565 return PTR_ERR(crtc_state);
14567 if (crtc_state->hw.active) {
14569 * Preserve the inherited flag to avoid
14570 * taking the full modeset path.
14572 crtc_state->inherited = true;
14576 drm_for_each_plane(plane, state->dev) {
14577 struct drm_plane_state *plane_state;
14579 plane_state = drm_atomic_get_plane_state(state, plane);
14580 if (IS_ERR(plane_state))
14581 return PTR_ERR(plane_state);
14588 * Calculate what we think the watermarks should be for the state we've read
14589 * out of the hardware and then immediately program those watermarks so that
14590 * we ensure the hardware settings match our internal state.
14592 * We can calculate what we think WM's should be by creating a duplicate of the
14593 * current state (which was constructed during hardware readout) and running it
14594 * through the atomic check code to calculate new watermark values in the
14597 static void sanitize_watermarks(struct drm_i915_private *dev_priv)
14599 struct drm_atomic_state *state;
14600 struct intel_atomic_state *intel_state;
14601 struct intel_crtc *crtc;
14602 struct intel_crtc_state *crtc_state;
14603 struct drm_modeset_acquire_ctx ctx;
14607 /* Only supported on platforms that use atomic watermark design */
14608 if (!dev_priv->display.optimize_watermarks)
14611 state = drm_atomic_state_alloc(&dev_priv->drm);
14612 if (drm_WARN_ON(&dev_priv->drm, !state))
14615 intel_state = to_intel_atomic_state(state);
14617 drm_modeset_acquire_init(&ctx, 0);
14620 state->acquire_ctx = &ctx;
14623 * Hardware readout is the only time we don't want to calculate
14624 * intermediate watermarks (since we don't trust the current
14627 if (!HAS_GMCH(dev_priv))
14628 intel_state->skip_intermediate_wm = true;
14630 ret = sanitize_watermarks_add_affected(state);
14634 ret = intel_atomic_check(&dev_priv->drm, state);
14638 /* Write calculated watermark values back */
14639 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
14640 crtc_state->wm.need_postvbl_update = true;
14641 dev_priv->display.optimize_watermarks(intel_state, crtc);
14643 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
14647 if (ret == -EDEADLK) {
14648 drm_atomic_state_clear(state);
14649 drm_modeset_backoff(&ctx);
14654 * If we fail here, it means that the hardware appears to be
14655 * programmed in a way that shouldn't be possible, given our
14656 * understanding of watermark requirements. This might mean a
14657 * mistake in the hardware readout code or a mistake in the
14658 * watermark calculations for a given platform. Raise a WARN
14659 * so that this is noticeable.
14661 * If this actually happens, we'll have to just leave the
14662 * BIOS-programmed watermarks untouched and hope for the best.
14664 drm_WARN(&dev_priv->drm, ret,
14665 "Could not determine valid watermarks for inherited state\n");
14667 drm_atomic_state_put(state);
14669 drm_modeset_drop_locks(&ctx);
14670 drm_modeset_acquire_fini(&ctx);
14673 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
14675 if (IS_GEN(dev_priv, 5)) {
14677 intel_de_read(dev_priv, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
14679 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
14680 } else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) {
14681 dev_priv->fdi_pll_freq = 270000;
14686 drm_dbg(&dev_priv->drm, "FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
14689 static int intel_initial_commit(struct drm_device *dev)
14691 struct drm_atomic_state *state = NULL;
14692 struct drm_modeset_acquire_ctx ctx;
14693 struct intel_crtc *crtc;
14696 state = drm_atomic_state_alloc(dev);
14700 drm_modeset_acquire_init(&ctx, 0);
14703 state->acquire_ctx = &ctx;
14705 for_each_intel_crtc(dev, crtc) {
14706 struct intel_crtc_state *crtc_state =
14707 intel_atomic_get_crtc_state(state, crtc);
14709 if (IS_ERR(crtc_state)) {
14710 ret = PTR_ERR(crtc_state);
14714 if (crtc_state->hw.active) {
14715 struct intel_encoder *encoder;
14718 * We've not yet detected sink capabilities
14719 * (audio,infoframes,etc.) and thus we don't want to
14720 * force a full state recomputation yet. We want that to
14721 * happen only for the first real commit from userspace.
14722 * So preserve the inherited flag for the time being.
14724 crtc_state->inherited = true;
14726 ret = drm_atomic_add_affected_planes(state, &crtc->base);
14731 * FIXME hack to force a LUT update to avoid the
14732 * plane update forcing the pipe gamma on without
14733 * having a proper LUT loaded. Remove once we
14734 * have readout for pipe gamma enable.
14736 crtc_state->uapi.color_mgmt_changed = true;
14738 for_each_intel_encoder_mask(dev, encoder,
14739 crtc_state->uapi.encoder_mask) {
14740 if (encoder->initial_fastset_check &&
14741 !encoder->initial_fastset_check(encoder, crtc_state)) {
14742 ret = drm_atomic_add_affected_connectors(state,
14751 ret = drm_atomic_commit(state);
14754 if (ret == -EDEADLK) {
14755 drm_atomic_state_clear(state);
14756 drm_modeset_backoff(&ctx);
14760 drm_atomic_state_put(state);
14762 drm_modeset_drop_locks(&ctx);
14763 drm_modeset_acquire_fini(&ctx);
14768 static void intel_mode_config_init(struct drm_i915_private *i915)
14770 struct drm_mode_config *mode_config = &i915->drm.mode_config;
14772 drm_mode_config_init(&i915->drm);
14773 INIT_LIST_HEAD(&i915->global_obj_list);
14775 mode_config->min_width = 0;
14776 mode_config->min_height = 0;
14778 mode_config->preferred_depth = 24;
14779 mode_config->prefer_shadow = 1;
14781 mode_config->allow_fb_modifiers = true;
14783 mode_config->funcs = &intel_mode_funcs;
14785 mode_config->async_page_flip = has_async_flips(i915);
14788 * Maximum framebuffer dimensions, chosen to match
14789 * the maximum render engine surface size on gen4+.
14791 if (INTEL_GEN(i915) >= 7) {
14792 mode_config->max_width = 16384;
14793 mode_config->max_height = 16384;
14794 } else if (INTEL_GEN(i915) >= 4) {
14795 mode_config->max_width = 8192;
14796 mode_config->max_height = 8192;
14797 } else if (IS_GEN(i915, 3)) {
14798 mode_config->max_width = 4096;
14799 mode_config->max_height = 4096;
14801 mode_config->max_width = 2048;
14802 mode_config->max_height = 2048;
14805 if (IS_I845G(i915) || IS_I865G(i915)) {
14806 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512;
14807 mode_config->cursor_height = 1023;
14808 } else if (IS_I830(i915) || IS_I85X(i915) ||
14809 IS_I915G(i915) || IS_I915GM(i915)) {
14810 mode_config->cursor_width = 64;
14811 mode_config->cursor_height = 64;
14813 mode_config->cursor_width = 256;
14814 mode_config->cursor_height = 256;
14818 static void intel_mode_config_cleanup(struct drm_i915_private *i915)
14820 intel_atomic_global_obj_cleanup(i915);
14821 drm_mode_config_cleanup(&i915->drm);
14824 static void plane_config_fini(struct intel_initial_plane_config *plane_config)
14826 if (plane_config->fb) {
14827 struct drm_framebuffer *fb = &plane_config->fb->base;
14829 /* We may only have the stub and not a full framebuffer */
14830 if (drm_framebuffer_read_refcount(fb))
14831 drm_framebuffer_put(fb);
14836 if (plane_config->vma)
14837 i915_vma_put(plane_config->vma);
14840 /* part #1: call before irq install */
14841 int intel_modeset_init_noirq(struct drm_i915_private *i915)
14845 if (i915_inject_probe_failure(i915))
14848 if (HAS_DISPLAY(i915)) {
14849 ret = drm_vblank_init(&i915->drm,
14850 INTEL_NUM_PIPES(i915));
14855 intel_bios_init(i915);
14857 ret = intel_vga_register(i915);
14861 /* FIXME: completely on the wrong abstraction layer */
14862 intel_power_domains_init_hw(i915, false);
14864 intel_csr_ucode_init(i915);
14866 i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
14867 i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
14868 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
14870 i915->framestart_delay = 1; /* 1-4 */
14872 intel_mode_config_init(i915);
14874 ret = intel_cdclk_init(i915);
14876 goto cleanup_vga_client_pw_domain_csr;
14878 ret = intel_dbuf_init(i915);
14880 goto cleanup_vga_client_pw_domain_csr;
14882 ret = intel_bw_init(i915);
14884 goto cleanup_vga_client_pw_domain_csr;
14886 init_llist_head(&i915->atomic_helper.free_list);
14887 INIT_WORK(&i915->atomic_helper.free_work,
14888 intel_atomic_helper_free_state_worker);
14890 intel_init_quirks(i915);
14892 intel_fbc_init(i915);
14896 cleanup_vga_client_pw_domain_csr:
14897 intel_csr_ucode_fini(i915);
14898 intel_power_domains_driver_remove(i915);
14899 intel_vga_unregister(i915);
14901 intel_bios_driver_remove(i915);
14906 /* part #2: call after irq install, but before gem init */
14907 int intel_modeset_init_nogem(struct drm_i915_private *i915)
14909 struct drm_device *dev = &i915->drm;
14911 struct intel_crtc *crtc;
14914 intel_init_pm(i915);
14916 intel_panel_sanitize_ssc(i915);
14918 intel_pps_setup(i915);
14920 intel_gmbus_setup(i915);
14922 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n",
14923 INTEL_NUM_PIPES(i915),
14924 INTEL_NUM_PIPES(i915) > 1 ? "s" : "");
14926 if (HAS_DISPLAY(i915)) {
14927 for_each_pipe(i915, pipe) {
14928 ret = intel_crtc_init(i915, pipe);
14930 intel_mode_config_cleanup(i915);
14936 intel_plane_possible_crtcs_init(i915);
14937 intel_shared_dpll_init(dev);
14938 intel_update_fdi_pll_freq(i915);
14940 intel_update_czclk(i915);
14941 intel_modeset_init_hw(i915);
14943 intel_hdcp_component_init(i915);
14945 if (i915->max_cdclk_freq == 0)
14946 intel_update_max_cdclk(i915);
14949 * If the platform has HTI, we need to find out whether it has reserved
14950 * any display resources before we create our display outputs.
14952 if (INTEL_INFO(i915)->display.has_hti)
14953 i915->hti_state = intel_de_read(i915, HDPORT_STATE);
14955 /* Just disable it once at startup */
14956 intel_vga_disable(i915);
14957 intel_setup_outputs(i915);
14959 drm_modeset_lock_all(dev);
14960 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
14961 drm_modeset_unlock_all(dev);
14963 for_each_intel_crtc(dev, crtc) {
14964 struct intel_initial_plane_config plane_config = {};
14966 if (!to_intel_crtc_state(crtc->base.state)->uapi.active)
14970 * Note that reserving the BIOS fb up front prevents us
14971 * from stuffing other stolen allocations like the ring
14972 * on top. This prevents some ugliness at boot time, and
14973 * can even allow for smooth boot transitions if the BIOS
14974 * fb is large enough for the active pipe configuration.
14976 i915->display.get_initial_plane_config(crtc, &plane_config);
14979 * If the fb is shared between multiple heads, we'll
14980 * just get the first one.
14982 intel_find_initial_plane_obj(crtc, &plane_config);
14984 plane_config_fini(&plane_config);
14988 * Make sure hardware watermarks really match the state we read out.
14989 * Note that we need to do this after reconstructing the BIOS fb's
14990 * since the watermark calculation done here will use pstate->fb.
14992 if (!HAS_GMCH(i915))
14993 sanitize_watermarks(i915);
14998 /* part #3: call after gem init */
14999 int intel_modeset_init(struct drm_i915_private *i915)
15003 if (!HAS_DISPLAY(i915))
15007 * Force all active planes to recompute their states. So that on
15008 * mode_setcrtc after probe, all the intel_plane_state variables
15009 * are already calculated and there is no assert_plane warnings
15012 ret = intel_initial_commit(&i915->drm);
15014 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret);
15016 intel_overlay_setup(i915);
15018 ret = intel_fbdev_init(&i915->drm);
15022 /* Only enable hotplug handling once the fbdev is fully set up. */
15023 intel_hpd_init(i915);
15024 intel_hpd_poll_disable(i915);
15026 intel_init_ipc(i915);
15031 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
15033 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15034 /* 640x480@60Hz, ~25175 kHz */
15035 struct dpll clock = {
15045 drm_WARN_ON(&dev_priv->drm,
15046 i9xx_calc_dpll_params(48000, &clock) != 25154);
15048 drm_dbg_kms(&dev_priv->drm,
15049 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
15050 pipe_name(pipe), clock.vco, clock.dot);
15052 fp = i9xx_dpll_compute_fp(&clock);
15053 dpll = DPLL_DVO_2X_MODE |
15054 DPLL_VGA_MODE_DIS |
15055 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
15056 PLL_P2_DIVIDE_BY_4 |
15057 PLL_REF_INPUT_DREFCLK |
15060 intel_de_write(dev_priv, FP0(pipe), fp);
15061 intel_de_write(dev_priv, FP1(pipe), fp);
15063 intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
15064 intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
15065 intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
15066 intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
15067 intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
15068 intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
15069 intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
15072 * Apparently we need to have VGA mode enabled prior to changing
15073 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
15074 * dividers, even though the register value does change.
15076 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
15077 intel_de_write(dev_priv, DPLL(pipe), dpll);
15079 /* Wait for the clocks to stabilize. */
15080 intel_de_posting_read(dev_priv, DPLL(pipe));
15083 /* The pixel multiplier can only be updated once the
15084 * DPLL is enabled and the clocks are stable.
15086 * So write it again.
15088 intel_de_write(dev_priv, DPLL(pipe), dpll);
15090 /* We do this three times for luck */
15091 for (i = 0; i < 3 ; i++) {
15092 intel_de_write(dev_priv, DPLL(pipe), dpll);
15093 intel_de_posting_read(dev_priv, DPLL(pipe));
15094 udelay(150); /* wait for warmup */
15097 intel_de_write(dev_priv, PIPECONF(pipe),
15098 PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
15099 intel_de_posting_read(dev_priv, PIPECONF(pipe));
15101 intel_wait_for_pipe_scanline_moving(crtc);
15104 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
15106 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15108 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",
15111 drm_WARN_ON(&dev_priv->drm,
15112 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) &
15113 DISPLAY_PLANE_ENABLE);
15114 drm_WARN_ON(&dev_priv->drm,
15115 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) &
15116 DISPLAY_PLANE_ENABLE);
15117 drm_WARN_ON(&dev_priv->drm,
15118 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) &
15119 DISPLAY_PLANE_ENABLE);
15120 drm_WARN_ON(&dev_priv->drm,
15121 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE);
15122 drm_WARN_ON(&dev_priv->drm,
15123 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE);
15125 intel_de_write(dev_priv, PIPECONF(pipe), 0);
15126 intel_de_posting_read(dev_priv, PIPECONF(pipe));
15128 intel_wait_for_pipe_scanline_stopped(crtc);
15130 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
15131 intel_de_posting_read(dev_priv, DPLL(pipe));
15135 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
15137 struct intel_crtc *crtc;
15139 if (INTEL_GEN(dev_priv) >= 4)
15142 for_each_intel_crtc(&dev_priv->drm, crtc) {
15143 struct intel_plane *plane =
15144 to_intel_plane(crtc->base.primary);
15145 struct intel_crtc *plane_crtc;
15148 if (!plane->get_hw_state(plane, &pipe))
15151 if (pipe == crtc->pipe)
15154 drm_dbg_kms(&dev_priv->drm,
15155 "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
15156 plane->base.base.id, plane->base.name);
15158 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15159 intel_plane_disable_noatomic(plane_crtc, plane);
15163 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15165 struct drm_device *dev = crtc->base.dev;
15166 struct intel_encoder *encoder;
15168 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15174 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
15176 struct drm_device *dev = encoder->base.dev;
15177 struct intel_connector *connector;
15179 for_each_connector_on_encoder(dev, &encoder->base, connector)
15185 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
15186 enum pipe pch_transcoder)
15188 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
15189 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
15192 static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc_state)
15194 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
15195 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15196 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
15198 if (INTEL_GEN(dev_priv) >= 9 ||
15199 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
15200 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
15203 if (transcoder_is_dsi(cpu_transcoder))
15206 val = intel_de_read(dev_priv, reg);
15207 val &= ~HSW_FRAME_START_DELAY_MASK;
15208 val |= HSW_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
15209 intel_de_write(dev_priv, reg, val);
15211 i915_reg_t reg = PIPECONF(cpu_transcoder);
15214 val = intel_de_read(dev_priv, reg);
15215 val &= ~PIPECONF_FRAME_START_DELAY_MASK;
15216 val |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
15217 intel_de_write(dev_priv, reg, val);
15220 if (!crtc_state->has_pch_encoder)
15223 if (HAS_PCH_IBX(dev_priv)) {
15224 i915_reg_t reg = PCH_TRANSCONF(crtc->pipe);
15227 val = intel_de_read(dev_priv, reg);
15228 val &= ~TRANS_FRAME_START_DELAY_MASK;
15229 val |= TRANS_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
15230 intel_de_write(dev_priv, reg, val);
15232 enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc);
15233 i915_reg_t reg = TRANS_CHICKEN2(pch_transcoder);
15236 val = intel_de_read(dev_priv, reg);
15237 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
15238 val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
15239 intel_de_write(dev_priv, reg, val);
15243 static void intel_sanitize_crtc(struct intel_crtc *crtc,
15244 struct drm_modeset_acquire_ctx *ctx)
15246 struct drm_device *dev = crtc->base.dev;
15247 struct drm_i915_private *dev_priv = to_i915(dev);
15248 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
15250 if (crtc_state->hw.active) {
15251 struct intel_plane *plane;
15253 /* Clear any frame start delays used for debugging left by the BIOS */
15254 intel_sanitize_frame_start_delay(crtc_state);
15256 /* Disable everything but the primary plane */
15257 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15258 const struct intel_plane_state *plane_state =
15259 to_intel_plane_state(plane->base.state);
15261 if (plane_state->uapi.visible &&
15262 plane->base.type != DRM_PLANE_TYPE_PRIMARY)
15263 intel_plane_disable_noatomic(crtc, plane);
15267 * Disable any background color set by the BIOS, but enable the
15268 * gamma and CSC to match how we program our planes.
15270 if (INTEL_GEN(dev_priv) >= 9)
15271 intel_de_write(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe),
15272 SKL_BOTTOM_COLOR_GAMMA_ENABLE | SKL_BOTTOM_COLOR_CSC_ENABLE);
15275 /* Adjust the state of the output pipe according to whether we
15276 * have active connectors/encoders. */
15277 if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) &&
15278 !crtc_state->bigjoiner_slave)
15279 intel_crtc_disable_noatomic(crtc, ctx);
15281 if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
15283 * We start out with underrun reporting disabled to avoid races.
15284 * For correct bookkeeping mark this on active crtcs.
15286 * Also on gmch platforms we dont have any hardware bits to
15287 * disable the underrun reporting. Which means we need to start
15288 * out with underrun reporting disabled also on inactive pipes,
15289 * since otherwise we'll complain about the garbage we read when
15290 * e.g. coming up after runtime pm.
15292 * No protection against concurrent access is required - at
15293 * worst a fifo underrun happens which also sets this to false.
15295 crtc->cpu_fifo_underrun_disabled = true;
15297 * We track the PCH trancoder underrun reporting state
15298 * within the crtc. With crtc for pipe A housing the underrun
15299 * reporting state for PCH transcoder A, crtc for pipe B housing
15300 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
15301 * and marking underrun reporting as disabled for the non-existing
15302 * PCH transcoders B and C would prevent enabling the south
15303 * error interrupt (see cpt_can_enable_serr_int()).
15305 if (has_pch_trancoder(dev_priv, crtc->pipe))
15306 crtc->pch_fifo_underrun_disabled = true;
15310 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
15312 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
15315 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
15316 * the hardware when a high res displays plugged in. DPLL P
15317 * divider is zero, and the pipe timings are bonkers. We'll
15318 * try to disable everything in that case.
15320 * FIXME would be nice to be able to sanitize this state
15321 * without several WARNs, but for now let's take the easy
15324 return IS_GEN(dev_priv, 6) &&
15325 crtc_state->hw.active &&
15326 crtc_state->shared_dpll &&
15327 crtc_state->port_clock == 0;
15330 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15332 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
15333 struct intel_connector *connector;
15334 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
15335 struct intel_crtc_state *crtc_state = crtc ?
15336 to_intel_crtc_state(crtc->base.state) : NULL;
15338 /* We need to check both for a crtc link (meaning that the
15339 * encoder is active and trying to read from a pipe) and the
15340 * pipe itself being active. */
15341 bool has_active_crtc = crtc_state &&
15342 crtc_state->hw.active;
15344 if (crtc_state && has_bogus_dpll_config(crtc_state)) {
15345 drm_dbg_kms(&dev_priv->drm,
15346 "BIOS has misprogrammed the hardware. Disabling pipe %c\n",
15347 pipe_name(crtc->pipe));
15348 has_active_crtc = false;
15351 connector = intel_encoder_find_connector(encoder);
15352 if (connector && !has_active_crtc) {
15353 drm_dbg_kms(&dev_priv->drm,
15354 "[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15355 encoder->base.base.id,
15356 encoder->base.name);
15358 /* Connector is active, but has no active pipe. This is
15359 * fallout from our resume register restoring. Disable
15360 * the encoder manually again. */
15362 struct drm_encoder *best_encoder;
15364 drm_dbg_kms(&dev_priv->drm,
15365 "[ENCODER:%d:%s] manually disabled\n",
15366 encoder->base.base.id,
15367 encoder->base.name);
15369 /* avoid oopsing in case the hooks consult best_encoder */
15370 best_encoder = connector->base.state->best_encoder;
15371 connector->base.state->best_encoder = &encoder->base;
15373 /* FIXME NULL atomic state passed! */
15374 if (encoder->disable)
15375 encoder->disable(NULL, encoder, crtc_state,
15376 connector->base.state);
15377 if (encoder->post_disable)
15378 encoder->post_disable(NULL, encoder, crtc_state,
15379 connector->base.state);
15381 connector->base.state->best_encoder = best_encoder;
15383 encoder->base.crtc = NULL;
15385 /* Inconsistent output/port/pipe state happens presumably due to
15386 * a bug in one of the get_hw_state functions. Or someplace else
15387 * in our code, like the register restore mess on resume. Clamp
15388 * things to off as a safer default. */
15390 connector->base.dpms = DRM_MODE_DPMS_OFF;
15391 connector->base.encoder = NULL;
15394 /* notify opregion of the sanitized encoder state */
15395 intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
15397 if (INTEL_GEN(dev_priv) >= 11)
15398 icl_sanitize_encoder_pll_mapping(encoder);
15401 /* FIXME read out full plane state for all planes */
15402 static void readout_plane_state(struct drm_i915_private *dev_priv)
15404 struct intel_plane *plane;
15405 struct intel_crtc *crtc;
15407 for_each_intel_plane(&dev_priv->drm, plane) {
15408 struct intel_plane_state *plane_state =
15409 to_intel_plane_state(plane->base.state);
15410 struct intel_crtc_state *crtc_state;
15411 enum pipe pipe = PIPE_A;
15414 visible = plane->get_hw_state(plane, &pipe);
15416 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15417 crtc_state = to_intel_crtc_state(crtc->base.state);
15419 intel_set_plane_visible(crtc_state, plane_state, visible);
15421 drm_dbg_kms(&dev_priv->drm,
15422 "[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
15423 plane->base.base.id, plane->base.name,
15424 enableddisabled(visible), pipe_name(pipe));
15427 for_each_intel_crtc(&dev_priv->drm, crtc) {
15428 struct intel_crtc_state *crtc_state =
15429 to_intel_crtc_state(crtc->base.state);
15431 fixup_plane_bitmasks(crtc_state);
15435 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15437 struct drm_i915_private *dev_priv = to_i915(dev);
15438 struct intel_cdclk_state *cdclk_state =
15439 to_intel_cdclk_state(dev_priv->cdclk.obj.state);
15440 struct intel_dbuf_state *dbuf_state =
15441 to_intel_dbuf_state(dev_priv->dbuf.obj.state);
15443 struct intel_crtc *crtc;
15444 struct intel_encoder *encoder;
15445 struct intel_connector *connector;
15446 struct drm_connector_list_iter conn_iter;
15447 u8 active_pipes = 0;
15449 for_each_intel_crtc(dev, crtc) {
15450 struct intel_crtc_state *crtc_state =
15451 to_intel_crtc_state(crtc->base.state);
15453 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
15454 intel_crtc_free_hw_state(crtc_state);
15455 intel_crtc_state_reset(crtc_state, crtc);
15457 intel_crtc_get_pipe_config(crtc_state);
15459 crtc_state->hw.enable = crtc_state->hw.active;
15461 crtc->base.enabled = crtc_state->hw.enable;
15462 crtc->active = crtc_state->hw.active;
15464 if (crtc_state->hw.active)
15465 active_pipes |= BIT(crtc->pipe);
15467 drm_dbg_kms(&dev_priv->drm,
15468 "[CRTC:%d:%s] hw state readout: %s\n",
15469 crtc->base.base.id, crtc->base.name,
15470 enableddisabled(crtc_state->hw.active));
15473 dev_priv->active_pipes = cdclk_state->active_pipes =
15474 dbuf_state->active_pipes = active_pipes;
15476 readout_plane_state(dev_priv);
15478 intel_dpll_readout_hw_state(dev_priv);
15480 for_each_intel_encoder(dev, encoder) {
15483 if (encoder->get_hw_state(encoder, &pipe)) {
15484 struct intel_crtc_state *crtc_state;
15486 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15487 crtc_state = to_intel_crtc_state(crtc->base.state);
15489 encoder->base.crtc = &crtc->base;
15490 intel_encoder_get_config(encoder, crtc_state);
15491 if (encoder->sync_state)
15492 encoder->sync_state(encoder, crtc_state);
15494 /* read out to slave crtc as well for bigjoiner */
15495 if (crtc_state->bigjoiner) {
15496 /* encoder should read be linked to bigjoiner master */
15497 WARN_ON(crtc_state->bigjoiner_slave);
15499 crtc = crtc_state->bigjoiner_linked_crtc;
15500 crtc_state = to_intel_crtc_state(crtc->base.state);
15501 intel_encoder_get_config(encoder, crtc_state);
15504 encoder->base.crtc = NULL;
15507 drm_dbg_kms(&dev_priv->drm,
15508 "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15509 encoder->base.base.id, encoder->base.name,
15510 enableddisabled(encoder->base.crtc),
15514 drm_connector_list_iter_begin(dev, &conn_iter);
15515 for_each_intel_connector_iter(connector, &conn_iter) {
15516 if (connector->get_hw_state(connector)) {
15517 struct intel_crtc_state *crtc_state;
15518 struct intel_crtc *crtc;
15520 connector->base.dpms = DRM_MODE_DPMS_ON;
15522 encoder = intel_attached_encoder(connector);
15523 connector->base.encoder = &encoder->base;
15525 crtc = to_intel_crtc(encoder->base.crtc);
15526 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
15528 if (crtc_state && crtc_state->hw.active) {
15530 * This has to be done during hardware readout
15531 * because anything calling .crtc_disable may
15532 * rely on the connector_mask being accurate.
15534 crtc_state->uapi.connector_mask |=
15535 drm_connector_mask(&connector->base);
15536 crtc_state->uapi.encoder_mask |=
15537 drm_encoder_mask(&encoder->base);
15540 connector->base.dpms = DRM_MODE_DPMS_OFF;
15541 connector->base.encoder = NULL;
15543 drm_dbg_kms(&dev_priv->drm,
15544 "[CONNECTOR:%d:%s] hw state readout: %s\n",
15545 connector->base.base.id, connector->base.name,
15546 enableddisabled(connector->base.encoder));
15548 drm_connector_list_iter_end(&conn_iter);
15550 for_each_intel_crtc(dev, crtc) {
15551 struct intel_bw_state *bw_state =
15552 to_intel_bw_state(dev_priv->bw_obj.state);
15553 struct intel_crtc_state *crtc_state =
15554 to_intel_crtc_state(crtc->base.state);
15555 struct intel_plane *plane;
15558 if (crtc_state->bigjoiner_slave)
15561 if (crtc_state->hw.active) {
15563 * The initial mode needs to be set in order to keep
15564 * the atomic core happy. It wants a valid mode if the
15565 * crtc's enabled, so we do the above call.
15567 * But we don't set all the derived state fully, hence
15568 * set a flag to indicate that a full recalculation is
15569 * needed on the next commit.
15571 crtc_state->inherited = true;
15573 intel_crtc_update_active_timings(crtc_state);
15575 intel_crtc_copy_hw_to_uapi_state(crtc_state);
15578 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
15579 const struct intel_plane_state *plane_state =
15580 to_intel_plane_state(plane->base.state);
15583 * FIXME don't have the fb yet, so can't
15584 * use intel_plane_data_rate() :(
15586 if (plane_state->uapi.visible)
15587 crtc_state->data_rate[plane->id] =
15588 4 * crtc_state->pixel_rate;
15590 * FIXME don't have the fb yet, so can't
15591 * use plane->min_cdclk() :(
15593 if (plane_state->uapi.visible && plane->min_cdclk) {
15594 if (crtc_state->double_wide ||
15595 INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
15596 crtc_state->min_cdclk[plane->id] =
15597 DIV_ROUND_UP(crtc_state->pixel_rate, 2);
15599 crtc_state->min_cdclk[plane->id] =
15600 crtc_state->pixel_rate;
15602 drm_dbg_kms(&dev_priv->drm,
15603 "[PLANE:%d:%s] min_cdclk %d kHz\n",
15604 plane->base.base.id, plane->base.name,
15605 crtc_state->min_cdclk[plane->id]);
15608 if (crtc_state->hw.active) {
15609 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
15610 if (drm_WARN_ON(dev, min_cdclk < 0))
15614 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
15615 cdclk_state->min_voltage_level[crtc->pipe] =
15616 crtc_state->min_voltage_level;
15618 intel_bw_crtc_update(bw_state, crtc_state);
15620 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15622 /* discard our incomplete slave state, copy it from master */
15623 if (crtc_state->bigjoiner && crtc_state->hw.active) {
15624 struct intel_crtc *slave = crtc_state->bigjoiner_linked_crtc;
15625 struct intel_crtc_state *slave_crtc_state =
15626 to_intel_crtc_state(slave->base.state);
15628 copy_bigjoiner_crtc_state(slave_crtc_state, crtc_state);
15629 slave->base.mode = crtc->base.mode;
15631 cdclk_state->min_cdclk[slave->pipe] = min_cdclk;
15632 cdclk_state->min_voltage_level[slave->pipe] =
15633 crtc_state->min_voltage_level;
15635 for_each_intel_plane_on_crtc(&dev_priv->drm, slave, plane) {
15636 const struct intel_plane_state *plane_state =
15637 to_intel_plane_state(plane->base.state);
15640 * FIXME don't have the fb yet, so can't
15641 * use intel_plane_data_rate() :(
15643 if (plane_state->uapi.visible)
15644 crtc_state->data_rate[plane->id] =
15645 4 * crtc_state->pixel_rate;
15647 crtc_state->data_rate[plane->id] = 0;
15650 intel_bw_crtc_update(bw_state, slave_crtc_state);
15651 drm_calc_timestamping_constants(&slave->base,
15652 &slave_crtc_state->hw.adjusted_mode);
15658 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15660 struct intel_encoder *encoder;
15662 for_each_intel_encoder(&dev_priv->drm, encoder) {
15663 struct intel_crtc_state *crtc_state;
15665 if (!encoder->get_power_domains)
15669 * MST-primary and inactive encoders don't have a crtc state
15670 * and neither of these require any power domain references.
15672 if (!encoder->base.crtc)
15675 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
15676 encoder->get_power_domains(encoder, crtc_state);
15680 static void intel_early_display_was(struct drm_i915_private *dev_priv)
15683 * Display WA #1185 WaDisableDARBFClkGating:cnl,glk,icl,ehl,tgl
15684 * Also known as Wa_14010480278.
15686 if (IS_GEN_RANGE(dev_priv, 10, 12) || IS_GEMINILAKE(dev_priv))
15687 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0,
15688 intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS);
15690 if (IS_HASWELL(dev_priv)) {
15692 * WaRsPkgCStateDisplayPMReq:hsw
15693 * System hang if this isn't done before disabling all planes!
15695 intel_de_write(dev_priv, CHICKEN_PAR1_1,
15696 intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
15699 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) {
15700 /* Display WA #1142:kbl,cfl,cml */
15701 intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
15702 KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22);
15703 intel_de_rmw(dev_priv, CHICKEN_MISC_2,
15704 KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14,
15705 KBL_ARB_FILL_SPARE_14);
15709 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
15710 enum port port, i915_reg_t hdmi_reg)
15712 u32 val = intel_de_read(dev_priv, hdmi_reg);
15714 if (val & SDVO_ENABLE ||
15715 (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
15718 drm_dbg_kms(&dev_priv->drm,
15719 "Sanitizing transcoder select for HDMI %c\n",
15722 val &= ~SDVO_PIPE_SEL_MASK;
15723 val |= SDVO_PIPE_SEL(PIPE_A);
15725 intel_de_write(dev_priv, hdmi_reg, val);
15728 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
15729 enum port port, i915_reg_t dp_reg)
15731 u32 val = intel_de_read(dev_priv, dp_reg);
15733 if (val & DP_PORT_EN ||
15734 (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
15737 drm_dbg_kms(&dev_priv->drm,
15738 "Sanitizing transcoder select for DP %c\n",
15741 val &= ~DP_PIPE_SEL_MASK;
15742 val |= DP_PIPE_SEL(PIPE_A);
15744 intel_de_write(dev_priv, dp_reg, val);
15747 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
15750 * The BIOS may select transcoder B on some of the PCH
15751 * ports even it doesn't enable the port. This would trip
15752 * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
15753 * Sanitize the transcoder select bits to prevent that. We
15754 * assume that the BIOS never actually enabled the port,
15755 * because if it did we'd actually have to toggle the port
15756 * on and back off to make the transcoder A select stick
15757 * (see. intel_dp_link_down(), intel_disable_hdmi(),
15758 * intel_disable_sdvo()).
15760 ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
15761 ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
15762 ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
15764 /* PCH SDVOB multiplex with HDMIB */
15765 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
15766 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
15767 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
15770 /* Scan out the current hw modeset state,
15771 * and sanitizes it to the current state
15774 intel_modeset_setup_hw_state(struct drm_device *dev,
15775 struct drm_modeset_acquire_ctx *ctx)
15777 struct drm_i915_private *dev_priv = to_i915(dev);
15778 struct intel_encoder *encoder;
15779 struct intel_crtc *crtc;
15780 intel_wakeref_t wakeref;
15782 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
15784 intel_early_display_was(dev_priv);
15785 intel_modeset_readout_hw_state(dev);
15787 /* HW state is read out, now we need to sanitize this mess. */
15789 /* Sanitize the TypeC port mode upfront, encoders depend on this */
15790 for_each_intel_encoder(dev, encoder) {
15791 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
15793 /* We need to sanitize only the MST primary port. */
15794 if (encoder->type != INTEL_OUTPUT_DP_MST &&
15795 intel_phy_is_tc(dev_priv, phy))
15796 intel_tc_port_sanitize(enc_to_dig_port(encoder));
15799 get_encoder_power_domains(dev_priv);
15801 if (HAS_PCH_IBX(dev_priv))
15802 ibx_sanitize_pch_ports(dev_priv);
15805 * intel_sanitize_plane_mapping() may need to do vblank
15806 * waits, so we need vblank interrupts restored beforehand.
15808 for_each_intel_crtc(&dev_priv->drm, crtc) {
15809 struct intel_crtc_state *crtc_state =
15810 to_intel_crtc_state(crtc->base.state);
15812 drm_crtc_vblank_reset(&crtc->base);
15814 if (crtc_state->hw.active)
15815 intel_crtc_vblank_on(crtc_state);
15818 intel_sanitize_plane_mapping(dev_priv);
15820 for_each_intel_encoder(dev, encoder)
15821 intel_sanitize_encoder(encoder);
15823 for_each_intel_crtc(&dev_priv->drm, crtc) {
15824 struct intel_crtc_state *crtc_state =
15825 to_intel_crtc_state(crtc->base.state);
15827 intel_sanitize_crtc(crtc, ctx);
15828 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
15831 intel_modeset_update_connector_atomic_state(dev);
15833 intel_dpll_sanitize_state(dev_priv);
15835 if (IS_G4X(dev_priv)) {
15836 g4x_wm_get_hw_state(dev_priv);
15837 g4x_wm_sanitize(dev_priv);
15838 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15839 vlv_wm_get_hw_state(dev_priv);
15840 vlv_wm_sanitize(dev_priv);
15841 } else if (INTEL_GEN(dev_priv) >= 9) {
15842 skl_wm_get_hw_state(dev_priv);
15843 } else if (HAS_PCH_SPLIT(dev_priv)) {
15844 ilk_wm_get_hw_state(dev_priv);
15847 for_each_intel_crtc(dev, crtc) {
15848 struct intel_crtc_state *crtc_state =
15849 to_intel_crtc_state(crtc->base.state);
15852 put_domains = modeset_get_crtc_power_domains(crtc_state);
15853 if (drm_WARN_ON(dev, put_domains))
15854 modeset_put_crtc_power_domains(crtc, put_domains);
15857 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
15860 void intel_display_resume(struct drm_device *dev)
15862 struct drm_i915_private *dev_priv = to_i915(dev);
15863 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15864 struct drm_modeset_acquire_ctx ctx;
15867 dev_priv->modeset_restore_state = NULL;
15869 state->acquire_ctx = &ctx;
15871 drm_modeset_acquire_init(&ctx, 0);
15874 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15875 if (ret != -EDEADLK)
15878 drm_modeset_backoff(&ctx);
15882 ret = __intel_display_resume(dev, state, &ctx);
15884 intel_enable_ipc(dev_priv);
15885 drm_modeset_drop_locks(&ctx);
15886 drm_modeset_acquire_fini(&ctx);
15889 drm_err(&dev_priv->drm,
15890 "Restoring old state failed with %i\n", ret);
15892 drm_atomic_state_put(state);
15895 static void intel_hpd_poll_fini(struct drm_i915_private *i915)
15897 struct intel_connector *connector;
15898 struct drm_connector_list_iter conn_iter;
15900 /* Kill all the work that may have been queued by hpd. */
15901 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
15902 for_each_intel_connector_iter(connector, &conn_iter) {
15903 if (connector->modeset_retry_work.func)
15904 cancel_work_sync(&connector->modeset_retry_work);
15905 if (connector->hdcp.shim) {
15906 cancel_delayed_work_sync(&connector->hdcp.check_work);
15907 cancel_work_sync(&connector->hdcp.prop_work);
15910 drm_connector_list_iter_end(&conn_iter);
15913 /* part #1: call before irq uninstall */
15914 void intel_modeset_driver_remove(struct drm_i915_private *i915)
15916 flush_workqueue(i915->flip_wq);
15917 flush_workqueue(i915->modeset_wq);
15919 flush_work(&i915->atomic_helper.free_work);
15920 drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list));
15923 /* part #2: call after irq uninstall */
15924 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915)
15927 * Due to the hpd irq storm handling the hotplug work can re-arm the
15928 * poll handlers. Hence disable polling after hpd handling is shut down.
15930 intel_hpd_poll_fini(i915);
15933 * MST topology needs to be suspended so we don't have any calls to
15934 * fbdev after it's finalized. MST will be destroyed later as part of
15935 * drm_mode_config_cleanup()
15937 intel_dp_mst_suspend(i915);
15939 /* poll work can call into fbdev, hence clean that up afterwards */
15940 intel_fbdev_fini(i915);
15942 intel_unregister_dsm_handler();
15944 intel_fbc_global_disable(i915);
15946 /* flush any delayed tasks or pending work */
15947 flush_scheduled_work();
15949 intel_hdcp_component_fini(i915);
15951 intel_mode_config_cleanup(i915);
15953 intel_overlay_cleanup(i915);
15955 intel_gmbus_teardown(i915);
15957 destroy_workqueue(i915->flip_wq);
15958 destroy_workqueue(i915->modeset_wq);
15960 intel_fbc_cleanup_cfb(i915);
15963 /* part #3: call after gem init */
15964 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915)
15966 intel_csr_ucode_fini(i915);
15968 intel_power_domains_driver_remove(i915);
15970 intel_vga_unregister(i915);
15972 intel_bios_driver_remove(i915);
15975 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15977 struct intel_display_error_state {
15979 u32 power_well_driver;
15981 struct intel_cursor_error_state {
15986 } cursor[I915_MAX_PIPES];
15988 struct intel_pipe_error_state {
15989 bool power_domain_on;
15992 } pipe[I915_MAX_PIPES];
15994 struct intel_plane_error_state {
16002 } plane[I915_MAX_PIPES];
16004 struct intel_transcoder_error_state {
16006 bool power_domain_on;
16007 enum transcoder cpu_transcoder;
16020 struct intel_display_error_state *
16021 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
16023 struct intel_display_error_state *error;
16024 int transcoders[] = {
16033 BUILD_BUG_ON(ARRAY_SIZE(transcoders) != ARRAY_SIZE(error->transcoder));
16035 if (!HAS_DISPLAY(dev_priv))
16038 error = kzalloc(sizeof(*error), GFP_ATOMIC);
16042 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16043 error->power_well_driver = intel_de_read(dev_priv,
16044 HSW_PWR_WELL_CTL2);
16046 for_each_pipe(dev_priv, i) {
16047 error->pipe[i].power_domain_on =
16048 __intel_display_power_is_enabled(dev_priv,
16049 POWER_DOMAIN_PIPE(i));
16050 if (!error->pipe[i].power_domain_on)
16053 error->cursor[i].control = intel_de_read(dev_priv, CURCNTR(i));
16054 error->cursor[i].position = intel_de_read(dev_priv, CURPOS(i));
16055 error->cursor[i].base = intel_de_read(dev_priv, CURBASE(i));
16057 error->plane[i].control = intel_de_read(dev_priv, DSPCNTR(i));
16058 error->plane[i].stride = intel_de_read(dev_priv, DSPSTRIDE(i));
16059 if (INTEL_GEN(dev_priv) <= 3) {
16060 error->plane[i].size = intel_de_read(dev_priv,
16062 error->plane[i].pos = intel_de_read(dev_priv,
16065 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16066 error->plane[i].addr = intel_de_read(dev_priv,
16068 if (INTEL_GEN(dev_priv) >= 4) {
16069 error->plane[i].surface = intel_de_read(dev_priv,
16071 error->plane[i].tile_offset = intel_de_read(dev_priv,
16075 error->pipe[i].source = intel_de_read(dev_priv, PIPESRC(i));
16077 if (HAS_GMCH(dev_priv))
16078 error->pipe[i].stat = intel_de_read(dev_priv,
16082 for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
16083 enum transcoder cpu_transcoder = transcoders[i];
16085 if (!HAS_TRANSCODER(dev_priv, cpu_transcoder))
16088 error->transcoder[i].available = true;
16089 error->transcoder[i].power_domain_on =
16090 __intel_display_power_is_enabled(dev_priv,
16091 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16092 if (!error->transcoder[i].power_domain_on)
16095 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16097 error->transcoder[i].conf = intel_de_read(dev_priv,
16098 PIPECONF(cpu_transcoder));
16099 error->transcoder[i].htotal = intel_de_read(dev_priv,
16100 HTOTAL(cpu_transcoder));
16101 error->transcoder[i].hblank = intel_de_read(dev_priv,
16102 HBLANK(cpu_transcoder));
16103 error->transcoder[i].hsync = intel_de_read(dev_priv,
16104 HSYNC(cpu_transcoder));
16105 error->transcoder[i].vtotal = intel_de_read(dev_priv,
16106 VTOTAL(cpu_transcoder));
16107 error->transcoder[i].vblank = intel_de_read(dev_priv,
16108 VBLANK(cpu_transcoder));
16109 error->transcoder[i].vsync = intel_de_read(dev_priv,
16110 VSYNC(cpu_transcoder));
16116 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16119 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16120 struct intel_display_error_state *error)
16122 struct drm_i915_private *dev_priv = m->i915;
16128 err_printf(m, "Num Pipes: %d\n", INTEL_NUM_PIPES(dev_priv));
16129 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16130 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16131 error->power_well_driver);
16132 for_each_pipe(dev_priv, i) {
16133 err_printf(m, "Pipe [%d]:\n", i);
16134 err_printf(m, " Power: %s\n",
16135 onoff(error->pipe[i].power_domain_on));
16136 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
16137 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
16139 err_printf(m, "Plane [%d]:\n", i);
16140 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16141 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
16142 if (INTEL_GEN(dev_priv) <= 3) {
16143 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16144 err_printf(m, " POS: %08x\n", error->plane[i].pos);
16146 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16147 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
16148 if (INTEL_GEN(dev_priv) >= 4) {
16149 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16150 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
16153 err_printf(m, "Cursor [%d]:\n", i);
16154 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16155 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16156 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
16159 for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
16160 if (!error->transcoder[i].available)
16163 err_printf(m, "CPU transcoder: %s\n",
16164 transcoder_name(error->transcoder[i].cpu_transcoder));
16165 err_printf(m, " Power: %s\n",
16166 onoff(error->transcoder[i].power_domain_on));
16167 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16168 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16169 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16170 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16171 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16172 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16173 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);