2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/i2c.h>
28 #include <linux/input.h>
29 #include <linux/intel-iommu.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/dma-resv.h>
33 #include <linux/slab.h>
35 #include <drm/drm_atomic.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_atomic_uapi.h>
38 #include <drm/drm_damage_helper.h>
39 #include <drm/drm_dp_helper.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_fourcc.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_probe_helper.h>
44 #include <drm/drm_rect.h>
46 #include "display/intel_crt.h"
47 #include "display/intel_ddi.h"
48 #include "display/intel_dp.h"
49 #include "display/intel_dp_mst.h"
50 #include "display/intel_dpll_mgr.h"
51 #include "display/intel_dsi.h"
52 #include "display/intel_dvo.h"
53 #include "display/intel_gmbus.h"
54 #include "display/intel_hdmi.h"
55 #include "display/intel_lvds.h"
56 #include "display/intel_sdvo.h"
57 #include "display/intel_tv.h"
58 #include "display/intel_vdsc.h"
60 #include "gt/intel_rps.h"
63 #include "i915_trace.h"
64 #include "intel_acpi.h"
65 #include "intel_atomic.h"
66 #include "intel_atomic_plane.h"
68 #include "intel_cdclk.h"
69 #include "intel_color.h"
70 #include "intel_csr.h"
71 #include "intel_display_types.h"
72 #include "intel_dp_link_training.h"
73 #include "intel_fbc.h"
74 #include "intel_fbdev.h"
75 #include "intel_fifo_underrun.h"
76 #include "intel_frontbuffer.h"
77 #include "intel_hdcp.h"
78 #include "intel_hotplug.h"
79 #include "intel_overlay.h"
80 #include "intel_pipe_crc.h"
82 #include "intel_psr.h"
83 #include "intel_quirks.h"
84 #include "intel_sideband.h"
85 #include "intel_sprite.h"
87 #include "intel_vga.h"
89 /* Primary plane formats for gen <= 3 */
90 static const u32 i8xx_primary_formats[] = {
97 /* Primary plane formats for ivb (no fp16 due to hw issue) */
98 static const u32 ivb_primary_formats[] = {
103 DRM_FORMAT_XRGB2101010,
104 DRM_FORMAT_XBGR2101010,
107 /* Primary plane formats for gen >= 4, except ivb */
108 static const u32 i965_primary_formats[] = {
113 DRM_FORMAT_XRGB2101010,
114 DRM_FORMAT_XBGR2101010,
115 DRM_FORMAT_XBGR16161616F,
118 /* Primary plane formats for vlv/chv */
119 static const u32 vlv_primary_formats[] = {
126 DRM_FORMAT_XRGB2101010,
127 DRM_FORMAT_XBGR2101010,
128 DRM_FORMAT_ARGB2101010,
129 DRM_FORMAT_ABGR2101010,
130 DRM_FORMAT_XBGR16161616F,
133 static const u64 i9xx_format_modifiers[] = {
134 I915_FORMAT_MOD_X_TILED,
135 DRM_FORMAT_MOD_LINEAR,
136 DRM_FORMAT_MOD_INVALID
140 static const u32 intel_cursor_formats[] = {
144 static const u64 cursor_format_modifiers[] = {
145 DRM_FORMAT_MOD_LINEAR,
146 DRM_FORMAT_MOD_INVALID
149 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
150 struct intel_crtc_state *pipe_config);
151 static void ilk_pch_clock_get(struct intel_crtc *crtc,
152 struct intel_crtc_state *pipe_config);
154 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
155 struct drm_i915_gem_object *obj,
156 struct drm_mode_fb_cmd2 *mode_cmd);
157 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
158 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
159 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
160 const struct intel_link_m_n *m_n,
161 const struct intel_link_m_n *m2_n2);
162 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
163 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
164 static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state);
165 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
166 static void vlv_prepare_pll(struct intel_crtc *crtc,
167 const struct intel_crtc_state *pipe_config);
168 static void chv_prepare_pll(struct intel_crtc *crtc,
169 const struct intel_crtc_state *pipe_config);
170 static void skl_pfit_enable(const struct intel_crtc_state *crtc_state);
171 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
172 static void intel_modeset_setup_hw_state(struct drm_device *dev,
173 struct drm_modeset_acquire_ctx *ctx);
174 static struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc);
179 } dot, vco, n, m, m1, m2, p, p1;
183 int p2_slow, p2_fast;
187 /* returns HPLL frequency in kHz */
188 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
190 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
192 /* Obtain SKU information */
193 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
194 CCK_FUSE_HPLL_FREQ_MASK;
196 return vco_freq[hpll_freq] * 1000;
199 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
200 const char *name, u32 reg, int ref_freq)
205 val = vlv_cck_read(dev_priv, reg);
206 divider = val & CCK_FREQUENCY_VALUES;
208 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
209 (divider << CCK_FREQUENCY_STATUS_SHIFT),
210 "%s change in progress\n", name);
212 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
215 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
216 const char *name, u32 reg)
220 vlv_cck_get(dev_priv);
222 if (dev_priv->hpll_freq == 0)
223 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
225 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
227 vlv_cck_put(dev_priv);
232 static void intel_update_czclk(struct drm_i915_private *dev_priv)
234 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
237 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
238 CCK_CZ_CLOCK_CONTROL);
240 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
241 dev_priv->czclk_freq);
244 /* units of 100MHz */
245 static u32 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
246 const struct intel_crtc_state *pipe_config)
248 if (HAS_DDI(dev_priv))
249 return pipe_config->port_clock; /* SPLL */
251 return dev_priv->fdi_pll_freq;
254 static const struct intel_limit intel_limits_i8xx_dac = {
255 .dot = { .min = 25000, .max = 350000 },
256 .vco = { .min = 908000, .max = 1512000 },
257 .n = { .min = 2, .max = 16 },
258 .m = { .min = 96, .max = 140 },
259 .m1 = { .min = 18, .max = 26 },
260 .m2 = { .min = 6, .max = 16 },
261 .p = { .min = 4, .max = 128 },
262 .p1 = { .min = 2, .max = 33 },
263 .p2 = { .dot_limit = 165000,
264 .p2_slow = 4, .p2_fast = 2 },
267 static const struct intel_limit intel_limits_i8xx_dvo = {
268 .dot = { .min = 25000, .max = 350000 },
269 .vco = { .min = 908000, .max = 1512000 },
270 .n = { .min = 2, .max = 16 },
271 .m = { .min = 96, .max = 140 },
272 .m1 = { .min = 18, .max = 26 },
273 .m2 = { .min = 6, .max = 16 },
274 .p = { .min = 4, .max = 128 },
275 .p1 = { .min = 2, .max = 33 },
276 .p2 = { .dot_limit = 165000,
277 .p2_slow = 4, .p2_fast = 4 },
280 static const struct intel_limit intel_limits_i8xx_lvds = {
281 .dot = { .min = 25000, .max = 350000 },
282 .vco = { .min = 908000, .max = 1512000 },
283 .n = { .min = 2, .max = 16 },
284 .m = { .min = 96, .max = 140 },
285 .m1 = { .min = 18, .max = 26 },
286 .m2 = { .min = 6, .max = 16 },
287 .p = { .min = 4, .max = 128 },
288 .p1 = { .min = 1, .max = 6 },
289 .p2 = { .dot_limit = 165000,
290 .p2_slow = 14, .p2_fast = 7 },
293 static const struct intel_limit intel_limits_i9xx_sdvo = {
294 .dot = { .min = 20000, .max = 400000 },
295 .vco = { .min = 1400000, .max = 2800000 },
296 .n = { .min = 1, .max = 6 },
297 .m = { .min = 70, .max = 120 },
298 .m1 = { .min = 8, .max = 18 },
299 .m2 = { .min = 3, .max = 7 },
300 .p = { .min = 5, .max = 80 },
301 .p1 = { .min = 1, .max = 8 },
302 .p2 = { .dot_limit = 200000,
303 .p2_slow = 10, .p2_fast = 5 },
306 static const struct intel_limit intel_limits_i9xx_lvds = {
307 .dot = { .min = 20000, .max = 400000 },
308 .vco = { .min = 1400000, .max = 2800000 },
309 .n = { .min = 1, .max = 6 },
310 .m = { .min = 70, .max = 120 },
311 .m1 = { .min = 8, .max = 18 },
312 .m2 = { .min = 3, .max = 7 },
313 .p = { .min = 7, .max = 98 },
314 .p1 = { .min = 1, .max = 8 },
315 .p2 = { .dot_limit = 112000,
316 .p2_slow = 14, .p2_fast = 7 },
320 static const struct intel_limit intel_limits_g4x_sdvo = {
321 .dot = { .min = 25000, .max = 270000 },
322 .vco = { .min = 1750000, .max = 3500000},
323 .n = { .min = 1, .max = 4 },
324 .m = { .min = 104, .max = 138 },
325 .m1 = { .min = 17, .max = 23 },
326 .m2 = { .min = 5, .max = 11 },
327 .p = { .min = 10, .max = 30 },
328 .p1 = { .min = 1, .max = 3},
329 .p2 = { .dot_limit = 270000,
335 static const struct intel_limit intel_limits_g4x_hdmi = {
336 .dot = { .min = 22000, .max = 400000 },
337 .vco = { .min = 1750000, .max = 3500000},
338 .n = { .min = 1, .max = 4 },
339 .m = { .min = 104, .max = 138 },
340 .m1 = { .min = 16, .max = 23 },
341 .m2 = { .min = 5, .max = 11 },
342 .p = { .min = 5, .max = 80 },
343 .p1 = { .min = 1, .max = 8},
344 .p2 = { .dot_limit = 165000,
345 .p2_slow = 10, .p2_fast = 5 },
348 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
349 .dot = { .min = 20000, .max = 115000 },
350 .vco = { .min = 1750000, .max = 3500000 },
351 .n = { .min = 1, .max = 3 },
352 .m = { .min = 104, .max = 138 },
353 .m1 = { .min = 17, .max = 23 },
354 .m2 = { .min = 5, .max = 11 },
355 .p = { .min = 28, .max = 112 },
356 .p1 = { .min = 2, .max = 8 },
357 .p2 = { .dot_limit = 0,
358 .p2_slow = 14, .p2_fast = 14
362 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
363 .dot = { .min = 80000, .max = 224000 },
364 .vco = { .min = 1750000, .max = 3500000 },
365 .n = { .min = 1, .max = 3 },
366 .m = { .min = 104, .max = 138 },
367 .m1 = { .min = 17, .max = 23 },
368 .m2 = { .min = 5, .max = 11 },
369 .p = { .min = 14, .max = 42 },
370 .p1 = { .min = 2, .max = 6 },
371 .p2 = { .dot_limit = 0,
372 .p2_slow = 7, .p2_fast = 7
376 static const struct intel_limit pnv_limits_sdvo = {
377 .dot = { .min = 20000, .max = 400000},
378 .vco = { .min = 1700000, .max = 3500000 },
379 /* Pineview's Ncounter is a ring counter */
380 .n = { .min = 3, .max = 6 },
381 .m = { .min = 2, .max = 256 },
382 /* Pineview only has one combined m divider, which we treat as m2. */
383 .m1 = { .min = 0, .max = 0 },
384 .m2 = { .min = 0, .max = 254 },
385 .p = { .min = 5, .max = 80 },
386 .p1 = { .min = 1, .max = 8 },
387 .p2 = { .dot_limit = 200000,
388 .p2_slow = 10, .p2_fast = 5 },
391 static const struct intel_limit pnv_limits_lvds = {
392 .dot = { .min = 20000, .max = 400000 },
393 .vco = { .min = 1700000, .max = 3500000 },
394 .n = { .min = 3, .max = 6 },
395 .m = { .min = 2, .max = 256 },
396 .m1 = { .min = 0, .max = 0 },
397 .m2 = { .min = 0, .max = 254 },
398 .p = { .min = 7, .max = 112 },
399 .p1 = { .min = 1, .max = 8 },
400 .p2 = { .dot_limit = 112000,
401 .p2_slow = 14, .p2_fast = 14 },
404 /* Ironlake / Sandybridge
406 * We calculate clock using (register_value + 2) for N/M1/M2, so here
407 * the range value for them is (actual_value - 2).
409 static const struct intel_limit ilk_limits_dac = {
410 .dot = { .min = 25000, .max = 350000 },
411 .vco = { .min = 1760000, .max = 3510000 },
412 .n = { .min = 1, .max = 5 },
413 .m = { .min = 79, .max = 127 },
414 .m1 = { .min = 12, .max = 22 },
415 .m2 = { .min = 5, .max = 9 },
416 .p = { .min = 5, .max = 80 },
417 .p1 = { .min = 1, .max = 8 },
418 .p2 = { .dot_limit = 225000,
419 .p2_slow = 10, .p2_fast = 5 },
422 static const struct intel_limit ilk_limits_single_lvds = {
423 .dot = { .min = 25000, .max = 350000 },
424 .vco = { .min = 1760000, .max = 3510000 },
425 .n = { .min = 1, .max = 3 },
426 .m = { .min = 79, .max = 118 },
427 .m1 = { .min = 12, .max = 22 },
428 .m2 = { .min = 5, .max = 9 },
429 .p = { .min = 28, .max = 112 },
430 .p1 = { .min = 2, .max = 8 },
431 .p2 = { .dot_limit = 225000,
432 .p2_slow = 14, .p2_fast = 14 },
435 static const struct intel_limit ilk_limits_dual_lvds = {
436 .dot = { .min = 25000, .max = 350000 },
437 .vco = { .min = 1760000, .max = 3510000 },
438 .n = { .min = 1, .max = 3 },
439 .m = { .min = 79, .max = 127 },
440 .m1 = { .min = 12, .max = 22 },
441 .m2 = { .min = 5, .max = 9 },
442 .p = { .min = 14, .max = 56 },
443 .p1 = { .min = 2, .max = 8 },
444 .p2 = { .dot_limit = 225000,
445 .p2_slow = 7, .p2_fast = 7 },
448 /* LVDS 100mhz refclk limits. */
449 static const struct intel_limit ilk_limits_single_lvds_100m = {
450 .dot = { .min = 25000, .max = 350000 },
451 .vco = { .min = 1760000, .max = 3510000 },
452 .n = { .min = 1, .max = 2 },
453 .m = { .min = 79, .max = 126 },
454 .m1 = { .min = 12, .max = 22 },
455 .m2 = { .min = 5, .max = 9 },
456 .p = { .min = 28, .max = 112 },
457 .p1 = { .min = 2, .max = 8 },
458 .p2 = { .dot_limit = 225000,
459 .p2_slow = 14, .p2_fast = 14 },
462 static const struct intel_limit ilk_limits_dual_lvds_100m = {
463 .dot = { .min = 25000, .max = 350000 },
464 .vco = { .min = 1760000, .max = 3510000 },
465 .n = { .min = 1, .max = 3 },
466 .m = { .min = 79, .max = 126 },
467 .m1 = { .min = 12, .max = 22 },
468 .m2 = { .min = 5, .max = 9 },
469 .p = { .min = 14, .max = 42 },
470 .p1 = { .min = 2, .max = 6 },
471 .p2 = { .dot_limit = 225000,
472 .p2_slow = 7, .p2_fast = 7 },
475 static const struct intel_limit intel_limits_vlv = {
477 * These are the data rate limits (measured in fast clocks)
478 * since those are the strictest limits we have. The fast
479 * clock and actual rate limits are more relaxed, so checking
480 * them would make no difference.
482 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
483 .vco = { .min = 4000000, .max = 6000000 },
484 .n = { .min = 1, .max = 7 },
485 .m1 = { .min = 2, .max = 3 },
486 .m2 = { .min = 11, .max = 156 },
487 .p1 = { .min = 2, .max = 3 },
488 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
491 static const struct intel_limit intel_limits_chv = {
493 * These are the data rate limits (measured in fast clocks)
494 * since those are the strictest limits we have. The fast
495 * clock and actual rate limits are more relaxed, so checking
496 * them would make no difference.
498 .dot = { .min = 25000 * 5, .max = 540000 * 5},
499 .vco = { .min = 4800000, .max = 6480000 },
500 .n = { .min = 1, .max = 1 },
501 .m1 = { .min = 2, .max = 2 },
502 .m2 = { .min = 24 << 22, .max = 175 << 22 },
503 .p1 = { .min = 2, .max = 4 },
504 .p2 = { .p2_slow = 1, .p2_fast = 14 },
507 static const struct intel_limit intel_limits_bxt = {
508 /* FIXME: find real dot limits */
509 .dot = { .min = 0, .max = INT_MAX },
510 .vco = { .min = 4800000, .max = 6700000 },
511 .n = { .min = 1, .max = 1 },
512 .m1 = { .min = 2, .max = 2 },
513 /* FIXME: find real m2 limits */
514 .m2 = { .min = 2 << 22, .max = 255 << 22 },
515 .p1 = { .min = 2, .max = 4 },
516 .p2 = { .p2_slow = 1, .p2_fast = 20 },
519 /* WA Display #0827: Gen9:all */
521 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
524 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
525 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS);
527 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
528 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
531 /* Wa_2006604312:icl,ehl */
533 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
537 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
538 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
540 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
541 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
545 needs_modeset(const struct intel_crtc_state *state)
547 return drm_atomic_crtc_needs_modeset(&state->uapi);
551 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
553 return crtc_state->master_transcoder != INVALID_TRANSCODER;
557 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
559 return crtc_state->sync_mode_slaves_mask != 0;
563 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
565 return is_trans_port_sync_master(crtc_state) ||
566 is_trans_port_sync_slave(crtc_state);
570 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
571 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
572 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
573 * The helpers' return value is the rate of the clock that is fed to the
574 * display engine's pipe which can be the above fast dot clock rate or a
575 * divided-down version of it.
577 /* m1 is reserved as 0 in Pineview, n is a ring counter */
578 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
580 clock->m = clock->m2 + 2;
581 clock->p = clock->p1 * clock->p2;
582 if (WARN_ON(clock->n == 0 || clock->p == 0))
584 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
585 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
590 static u32 i9xx_dpll_compute_m(struct dpll *dpll)
592 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
595 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
597 clock->m = i9xx_dpll_compute_m(clock);
598 clock->p = clock->p1 * clock->p2;
599 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
601 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
602 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
607 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
609 clock->m = clock->m1 * clock->m2;
610 clock->p = clock->p1 * clock->p2;
611 if (WARN_ON(clock->n == 0 || clock->p == 0))
613 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
614 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
616 return clock->dot / 5;
619 int chv_calc_dpll_params(int refclk, struct dpll *clock)
621 clock->m = clock->m1 * clock->m2;
622 clock->p = clock->p1 * clock->p2;
623 if (WARN_ON(clock->n == 0 || clock->p == 0))
625 clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
627 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
629 return clock->dot / 5;
633 * Returns whether the given set of divisors are valid for a given refclk with
634 * the given connectors.
636 static bool intel_pll_is_valid(struct drm_i915_private *dev_priv,
637 const struct intel_limit *limit,
638 const struct dpll *clock)
640 if (clock->n < limit->n.min || limit->n.max < clock->n)
642 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
644 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
646 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
649 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
650 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
651 if (clock->m1 <= clock->m2)
654 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
655 !IS_GEN9_LP(dev_priv)) {
656 if (clock->p < limit->p.min || limit->p.max < clock->p)
658 if (clock->m < limit->m.min || limit->m.max < clock->m)
662 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
664 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
665 * connector, etc., rather than just a single range.
667 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
674 i9xx_select_p2_div(const struct intel_limit *limit,
675 const struct intel_crtc_state *crtc_state,
678 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
680 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
682 * For LVDS just rely on its current settings for dual-channel.
683 * We haven't figured out how to reliably set up different
684 * single/dual channel state, if we even can.
686 if (intel_is_dual_link_lvds(dev_priv))
687 return limit->p2.p2_fast;
689 return limit->p2.p2_slow;
691 if (target < limit->p2.dot_limit)
692 return limit->p2.p2_slow;
694 return limit->p2.p2_fast;
699 * Returns a set of divisors for the desired target clock with the given
700 * refclk, or FALSE. The returned values represent the clock equation:
701 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
703 * Target and reference clocks are specified in kHz.
705 * If match_clock is provided, then best_clock P divider must match the P
706 * divider from @match_clock used for LVDS downclocking.
709 i9xx_find_best_dpll(const struct intel_limit *limit,
710 struct intel_crtc_state *crtc_state,
711 int target, int refclk, struct dpll *match_clock,
712 struct dpll *best_clock)
714 struct drm_device *dev = crtc_state->uapi.crtc->dev;
718 memset(best_clock, 0, sizeof(*best_clock));
720 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
722 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
724 for (clock.m2 = limit->m2.min;
725 clock.m2 <= limit->m2.max; clock.m2++) {
726 if (clock.m2 >= clock.m1)
728 for (clock.n = limit->n.min;
729 clock.n <= limit->n.max; clock.n++) {
730 for (clock.p1 = limit->p1.min;
731 clock.p1 <= limit->p1.max; clock.p1++) {
734 i9xx_calc_dpll_params(refclk, &clock);
735 if (!intel_pll_is_valid(to_i915(dev),
740 clock.p != match_clock->p)
743 this_err = abs(clock.dot - target);
744 if (this_err < err) {
753 return (err != target);
757 * Returns a set of divisors for the desired target clock with the given
758 * refclk, or FALSE. The returned values represent the clock equation:
759 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
761 * Target and reference clocks are specified in kHz.
763 * If match_clock is provided, then best_clock P divider must match the P
764 * divider from @match_clock used for LVDS downclocking.
767 pnv_find_best_dpll(const struct intel_limit *limit,
768 struct intel_crtc_state *crtc_state,
769 int target, int refclk, struct dpll *match_clock,
770 struct dpll *best_clock)
772 struct drm_device *dev = crtc_state->uapi.crtc->dev;
776 memset(best_clock, 0, sizeof(*best_clock));
778 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
780 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
782 for (clock.m2 = limit->m2.min;
783 clock.m2 <= limit->m2.max; clock.m2++) {
784 for (clock.n = limit->n.min;
785 clock.n <= limit->n.max; clock.n++) {
786 for (clock.p1 = limit->p1.min;
787 clock.p1 <= limit->p1.max; clock.p1++) {
790 pnv_calc_dpll_params(refclk, &clock);
791 if (!intel_pll_is_valid(to_i915(dev),
796 clock.p != match_clock->p)
799 this_err = abs(clock.dot - target);
800 if (this_err < err) {
809 return (err != target);
813 * Returns a set of divisors for the desired target clock with the given
814 * refclk, or FALSE. The returned values represent the clock equation:
815 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
817 * Target and reference clocks are specified in kHz.
819 * If match_clock is provided, then best_clock P divider must match the P
820 * divider from @match_clock used for LVDS downclocking.
823 g4x_find_best_dpll(const struct intel_limit *limit,
824 struct intel_crtc_state *crtc_state,
825 int target, int refclk, struct dpll *match_clock,
826 struct dpll *best_clock)
828 struct drm_device *dev = crtc_state->uapi.crtc->dev;
832 /* approximately equals target * 0.00585 */
833 int err_most = (target >> 8) + (target >> 9);
835 memset(best_clock, 0, sizeof(*best_clock));
837 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
839 max_n = limit->n.max;
840 /* based on hardware requirement, prefer smaller n to precision */
841 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
842 /* based on hardware requirement, prefere larger m1,m2 */
843 for (clock.m1 = limit->m1.max;
844 clock.m1 >= limit->m1.min; clock.m1--) {
845 for (clock.m2 = limit->m2.max;
846 clock.m2 >= limit->m2.min; clock.m2--) {
847 for (clock.p1 = limit->p1.max;
848 clock.p1 >= limit->p1.min; clock.p1--) {
851 i9xx_calc_dpll_params(refclk, &clock);
852 if (!intel_pll_is_valid(to_i915(dev),
857 this_err = abs(clock.dot - target);
858 if (this_err < err_most) {
872 * Check if the calculated PLL configuration is more optimal compared to the
873 * best configuration and error found so far. Return the calculated error.
875 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
876 const struct dpll *calculated_clock,
877 const struct dpll *best_clock,
878 unsigned int best_error_ppm,
879 unsigned int *error_ppm)
882 * For CHV ignore the error and consider only the P value.
883 * Prefer a bigger P value based on HW requirements.
885 if (IS_CHERRYVIEW(to_i915(dev))) {
888 return calculated_clock->p > best_clock->p;
891 if (drm_WARN_ON_ONCE(dev, !target_freq))
894 *error_ppm = div_u64(1000000ULL *
895 abs(target_freq - calculated_clock->dot),
898 * Prefer a better P value over a better (smaller) error if the error
899 * is small. Ensure this preference for future configurations too by
900 * setting the error to 0.
902 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
908 return *error_ppm + 10 < best_error_ppm;
912 * Returns a set of divisors for the desired target clock with the given
913 * refclk, or FALSE. The returned values represent the clock equation:
914 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
917 vlv_find_best_dpll(const struct intel_limit *limit,
918 struct intel_crtc_state *crtc_state,
919 int target, int refclk, struct dpll *match_clock,
920 struct dpll *best_clock)
922 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
923 struct drm_device *dev = crtc->base.dev;
925 unsigned int bestppm = 1000000;
926 /* min update 19.2 MHz */
927 int max_n = min(limit->n.max, refclk / 19200);
930 target *= 5; /* fast clock */
932 memset(best_clock, 0, sizeof(*best_clock));
934 /* based on hardware requirement, prefer smaller n to precision */
935 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
936 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
937 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
938 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
939 clock.p = clock.p1 * clock.p2;
940 /* based on hardware requirement, prefer bigger m1,m2 values */
941 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
944 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
947 vlv_calc_dpll_params(refclk, &clock);
949 if (!intel_pll_is_valid(to_i915(dev),
954 if (!vlv_PLL_is_optimal(dev, target,
972 * Returns a set of divisors for the desired target clock with the given
973 * refclk, or FALSE. The returned values represent the clock equation:
974 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
977 chv_find_best_dpll(const struct intel_limit *limit,
978 struct intel_crtc_state *crtc_state,
979 int target, int refclk, struct dpll *match_clock,
980 struct dpll *best_clock)
982 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
983 struct drm_device *dev = crtc->base.dev;
984 unsigned int best_error_ppm;
989 memset(best_clock, 0, sizeof(*best_clock));
990 best_error_ppm = 1000000;
993 * Based on hardware doc, the n always set to 1, and m1 always
994 * set to 2. If requires to support 200Mhz refclk, we need to
995 * revisit this because n may not 1 anymore.
997 clock.n = 1, clock.m1 = 2;
998 target *= 5; /* fast clock */
1000 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1001 for (clock.p2 = limit->p2.p2_fast;
1002 clock.p2 >= limit->p2.p2_slow;
1003 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1004 unsigned int error_ppm;
1006 clock.p = clock.p1 * clock.p2;
1008 m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
1011 if (m2 > INT_MAX/clock.m1)
1016 chv_calc_dpll_params(refclk, &clock);
1018 if (!intel_pll_is_valid(to_i915(dev), limit, &clock))
1021 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1022 best_error_ppm, &error_ppm))
1025 *best_clock = clock;
1026 best_error_ppm = error_ppm;
1034 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
1035 struct dpll *best_clock)
1037 int refclk = 100000;
1038 const struct intel_limit *limit = &intel_limits_bxt;
1040 return chv_find_best_dpll(limit, crtc_state,
1041 crtc_state->port_clock, refclk,
1045 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
1048 i915_reg_t reg = PIPEDSL(pipe);
1052 if (IS_GEN(dev_priv, 2))
1053 line_mask = DSL_LINEMASK_GEN2;
1055 line_mask = DSL_LINEMASK_GEN3;
1057 line1 = intel_de_read(dev_priv, reg) & line_mask;
1059 line2 = intel_de_read(dev_priv, reg) & line_mask;
1061 return line1 != line2;
1064 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1066 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1067 enum pipe pipe = crtc->pipe;
1069 /* Wait for the display line to settle/start moving */
1070 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1071 drm_err(&dev_priv->drm,
1072 "pipe %c scanline %s wait timed out\n",
1073 pipe_name(pipe), onoff(state));
1076 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1078 wait_for_pipe_scanline_moving(crtc, false);
1081 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1083 wait_for_pipe_scanline_moving(crtc, true);
1087 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
1089 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1090 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1092 if (INTEL_GEN(dev_priv) >= 4) {
1093 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1094 i915_reg_t reg = PIPECONF(cpu_transcoder);
1096 /* Wait for the Pipe State to go off */
1097 if (intel_de_wait_for_clear(dev_priv, reg,
1098 I965_PIPECONF_ACTIVE, 100))
1099 drm_WARN(&dev_priv->drm, 1,
1100 "pipe_off wait timed out\n");
1102 intel_wait_for_pipe_scanline_stopped(crtc);
1106 /* Only for pre-ILK configs */
1107 void assert_pll(struct drm_i915_private *dev_priv,
1108 enum pipe pipe, bool state)
1113 val = intel_de_read(dev_priv, DPLL(pipe));
1114 cur_state = !!(val & DPLL_VCO_ENABLE);
1115 I915_STATE_WARN(cur_state != state,
1116 "PLL state assertion failure (expected %s, current %s)\n",
1117 onoff(state), onoff(cur_state));
1120 /* XXX: the dsi pll is shared between MIPI DSI ports */
1121 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1126 vlv_cck_get(dev_priv);
1127 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1128 vlv_cck_put(dev_priv);
1130 cur_state = val & DSI_PLL_VCO_EN;
1131 I915_STATE_WARN(cur_state != state,
1132 "DSI PLL state assertion failure (expected %s, current %s)\n",
1133 onoff(state), onoff(cur_state));
1136 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1137 enum pipe pipe, bool state)
1141 if (HAS_DDI(dev_priv)) {
1143 * DDI does not have a specific FDI_TX register.
1145 * FDI is never fed from EDP transcoder
1146 * so pipe->transcoder cast is fine here.
1148 enum transcoder cpu_transcoder = (enum transcoder)pipe;
1149 u32 val = intel_de_read(dev_priv,
1150 TRANS_DDI_FUNC_CTL(cpu_transcoder));
1151 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1153 u32 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe));
1154 cur_state = !!(val & FDI_TX_ENABLE);
1156 I915_STATE_WARN(cur_state != state,
1157 "FDI TX state assertion failure (expected %s, current %s)\n",
1158 onoff(state), onoff(cur_state));
1160 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1161 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1163 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1164 enum pipe pipe, bool state)
1169 val = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
1170 cur_state = !!(val & FDI_RX_ENABLE);
1171 I915_STATE_WARN(cur_state != state,
1172 "FDI RX state assertion failure (expected %s, current %s)\n",
1173 onoff(state), onoff(cur_state));
1175 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1176 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1178 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1183 /* ILK FDI PLL is always enabled */
1184 if (IS_GEN(dev_priv, 5))
1187 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1188 if (HAS_DDI(dev_priv))
1191 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe));
1192 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1195 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1196 enum pipe pipe, bool state)
1201 val = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
1202 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1203 I915_STATE_WARN(cur_state != state,
1204 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1205 onoff(state), onoff(cur_state));
1208 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1212 enum pipe panel_pipe = INVALID_PIPE;
1215 if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv)))
1218 if (HAS_PCH_SPLIT(dev_priv)) {
1221 pp_reg = PP_CONTROL(0);
1222 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1225 case PANEL_PORT_SELECT_LVDS:
1226 intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1228 case PANEL_PORT_SELECT_DPA:
1229 intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1231 case PANEL_PORT_SELECT_DPC:
1232 intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1234 case PANEL_PORT_SELECT_DPD:
1235 intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1238 MISSING_CASE(port_sel);
1241 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1242 /* presumably write lock depends on pipe, not port select */
1243 pp_reg = PP_CONTROL(pipe);
1248 pp_reg = PP_CONTROL(0);
1249 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1251 drm_WARN_ON(&dev_priv->drm,
1252 port_sel != PANEL_PORT_SELECT_LVDS);
1253 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1256 val = intel_de_read(dev_priv, pp_reg);
1257 if (!(val & PANEL_POWER_ON) ||
1258 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1261 I915_STATE_WARN(panel_pipe == pipe && locked,
1262 "panel assertion failure, pipe %c regs locked\n",
1266 void assert_pipe(struct drm_i915_private *dev_priv,
1267 enum transcoder cpu_transcoder, bool state)
1270 enum intel_display_power_domain power_domain;
1271 intel_wakeref_t wakeref;
1273 /* we keep both pipes enabled on 830 */
1274 if (IS_I830(dev_priv))
1277 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1278 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1280 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
1281 cur_state = !!(val & PIPECONF_ENABLE);
1283 intel_display_power_put(dev_priv, power_domain, wakeref);
1288 I915_STATE_WARN(cur_state != state,
1289 "transcoder %s assertion failure (expected %s, current %s)\n",
1290 transcoder_name(cpu_transcoder),
1291 onoff(state), onoff(cur_state));
1294 static void assert_plane(struct intel_plane *plane, bool state)
1299 cur_state = plane->get_hw_state(plane, &pipe);
1301 I915_STATE_WARN(cur_state != state,
1302 "%s assertion failure (expected %s, current %s)\n",
1303 plane->base.name, onoff(state), onoff(cur_state));
1306 #define assert_plane_enabled(p) assert_plane(p, true)
1307 #define assert_plane_disabled(p) assert_plane(p, false)
1309 static void assert_planes_disabled(struct intel_crtc *crtc)
1311 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1312 struct intel_plane *plane;
1314 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1315 assert_plane_disabled(plane);
1318 static void assert_vblank_disabled(struct drm_crtc *crtc)
1320 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1321 drm_crtc_vblank_put(crtc);
1324 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1330 val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe));
1331 enabled = !!(val & TRANS_ENABLE);
1332 I915_STATE_WARN(enabled,
1333 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1337 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1338 enum pipe pipe, enum port port,
1341 enum pipe port_pipe;
1344 state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
1346 I915_STATE_WARN(state && port_pipe == pipe,
1347 "PCH DP %c enabled on transcoder %c, should be disabled\n",
1348 port_name(port), pipe_name(pipe));
1350 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1351 "IBX PCH DP %c still using transcoder B\n",
1355 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1356 enum pipe pipe, enum port port,
1357 i915_reg_t hdmi_reg)
1359 enum pipe port_pipe;
1362 state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
1364 I915_STATE_WARN(state && port_pipe == pipe,
1365 "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
1366 port_name(port), pipe_name(pipe));
1368 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1369 "IBX PCH HDMI %c still using transcoder B\n",
1373 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1376 enum pipe port_pipe;
1378 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
1379 assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
1380 assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
1382 I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
1384 "PCH VGA enabled on transcoder %c, should be disabled\n",
1387 I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
1389 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1392 /* PCH SDVOB multiplex with HDMIB */
1393 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
1394 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
1395 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
1398 static void _vlv_enable_pll(struct intel_crtc *crtc,
1399 const struct intel_crtc_state *pipe_config)
1401 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1402 enum pipe pipe = crtc->pipe;
1404 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1405 intel_de_posting_read(dev_priv, DPLL(pipe));
1408 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1409 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe);
1412 static void vlv_enable_pll(struct intel_crtc *crtc,
1413 const struct intel_crtc_state *pipe_config)
1415 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1416 enum pipe pipe = crtc->pipe;
1418 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
1420 /* PLL is protected by panel, make sure we can write it */
1421 assert_panel_unlocked(dev_priv, pipe);
1423 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1424 _vlv_enable_pll(crtc, pipe_config);
1426 intel_de_write(dev_priv, DPLL_MD(pipe),
1427 pipe_config->dpll_hw_state.dpll_md);
1428 intel_de_posting_read(dev_priv, DPLL_MD(pipe));
1432 static void _chv_enable_pll(struct intel_crtc *crtc,
1433 const struct intel_crtc_state *pipe_config)
1435 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1436 enum pipe pipe = crtc->pipe;
1437 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1440 vlv_dpio_get(dev_priv);
1442 /* Enable back the 10bit clock to display controller */
1443 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1444 tmp |= DPIO_DCLKP_EN;
1445 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1447 vlv_dpio_put(dev_priv);
1450 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1455 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1457 /* Check PLL is locked */
1458 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1459 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe);
1462 static void chv_enable_pll(struct intel_crtc *crtc,
1463 const struct intel_crtc_state *pipe_config)
1465 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1466 enum pipe pipe = crtc->pipe;
1468 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
1470 /* PLL is protected by panel, make sure we can write it */
1471 assert_panel_unlocked(dev_priv, pipe);
1473 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1474 _chv_enable_pll(crtc, pipe_config);
1476 if (pipe != PIPE_A) {
1478 * WaPixelRepeatModeFixForC0:chv
1480 * DPLLCMD is AWOL. Use chicken bits to propagate
1481 * the value from DPLLBMD to either pipe B or C.
1483 intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1484 intel_de_write(dev_priv, DPLL_MD(PIPE_B),
1485 pipe_config->dpll_hw_state.dpll_md);
1486 intel_de_write(dev_priv, CBR4_VLV, 0);
1487 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1490 * DPLLB VGA mode also seems to cause problems.
1491 * We should always have it disabled.
1493 drm_WARN_ON(&dev_priv->drm,
1494 (intel_de_read(dev_priv, DPLL(PIPE_B)) &
1495 DPLL_VGA_MODE_DIS) == 0);
1497 intel_de_write(dev_priv, DPLL_MD(pipe),
1498 pipe_config->dpll_hw_state.dpll_md);
1499 intel_de_posting_read(dev_priv, DPLL_MD(pipe));
1503 static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
1505 if (IS_I830(dev_priv))
1508 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
1511 static void i9xx_enable_pll(struct intel_crtc *crtc,
1512 const struct intel_crtc_state *crtc_state)
1514 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1515 i915_reg_t reg = DPLL(crtc->pipe);
1516 u32 dpll = crtc_state->dpll_hw_state.dpll;
1519 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
1521 /* PLL is protected by panel, make sure we can write it */
1522 if (i9xx_has_pps(dev_priv))
1523 assert_panel_unlocked(dev_priv, crtc->pipe);
1526 * Apparently we need to have VGA mode enabled prior to changing
1527 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1528 * dividers, even though the register value does change.
1530 intel_de_write(dev_priv, reg, dpll & ~DPLL_VGA_MODE_DIS);
1531 intel_de_write(dev_priv, reg, dpll);
1533 /* Wait for the clocks to stabilize. */
1534 intel_de_posting_read(dev_priv, reg);
1537 if (INTEL_GEN(dev_priv) >= 4) {
1538 intel_de_write(dev_priv, DPLL_MD(crtc->pipe),
1539 crtc_state->dpll_hw_state.dpll_md);
1541 /* The pixel multiplier can only be updated once the
1542 * DPLL is enabled and the clocks are stable.
1544 * So write it again.
1546 intel_de_write(dev_priv, reg, dpll);
1549 /* We do this three times for luck */
1550 for (i = 0; i < 3; i++) {
1551 intel_de_write(dev_priv, reg, dpll);
1552 intel_de_posting_read(dev_priv, reg);
1553 udelay(150); /* wait for warmup */
1557 static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
1559 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1560 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1561 enum pipe pipe = crtc->pipe;
1563 /* Don't disable pipe or pipe PLLs if needed */
1564 if (IS_I830(dev_priv))
1567 /* Make sure the pipe isn't still relying on us */
1568 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
1570 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
1571 intel_de_posting_read(dev_priv, DPLL(pipe));
1574 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1578 /* Make sure the pipe isn't still relying on us */
1579 assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
1581 val = DPLL_INTEGRATED_REF_CLK_VLV |
1582 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1584 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1586 intel_de_write(dev_priv, DPLL(pipe), val);
1587 intel_de_posting_read(dev_priv, DPLL(pipe));
1590 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1592 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1595 /* Make sure the pipe isn't still relying on us */
1596 assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
1598 val = DPLL_SSC_REF_CLK_CHV |
1599 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1601 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1603 intel_de_write(dev_priv, DPLL(pipe), val);
1604 intel_de_posting_read(dev_priv, DPLL(pipe));
1606 vlv_dpio_get(dev_priv);
1608 /* Disable 10bit clock to display controller */
1609 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1610 val &= ~DPIO_DCLKP_EN;
1611 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1613 vlv_dpio_put(dev_priv);
1616 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1617 struct intel_digital_port *dig_port,
1618 unsigned int expected_mask)
1621 i915_reg_t dpll_reg;
1623 switch (dig_port->base.port) {
1625 port_mask = DPLL_PORTB_READY_MASK;
1629 port_mask = DPLL_PORTC_READY_MASK;
1631 expected_mask <<= 4;
1634 port_mask = DPLL_PORTD_READY_MASK;
1635 dpll_reg = DPIO_PHY_STATUS;
1641 if (intel_de_wait_for_register(dev_priv, dpll_reg,
1642 port_mask, expected_mask, 1000))
1643 drm_WARN(&dev_priv->drm, 1,
1644 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
1645 dig_port->base.base.base.id, dig_port->base.base.name,
1646 intel_de_read(dev_priv, dpll_reg) & port_mask,
1650 static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
1652 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1653 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1654 enum pipe pipe = crtc->pipe;
1656 u32 val, pipeconf_val;
1658 /* Make sure PCH DPLL is enabled */
1659 assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
1661 /* FDI must be feeding us bits for PCH ports */
1662 assert_fdi_tx_enabled(dev_priv, pipe);
1663 assert_fdi_rx_enabled(dev_priv, pipe);
1665 if (HAS_PCH_CPT(dev_priv)) {
1666 reg = TRANS_CHICKEN2(pipe);
1667 val = intel_de_read(dev_priv, reg);
1669 * Workaround: Set the timing override bit
1670 * before enabling the pch transcoder.
1672 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1673 /* Configure frame start delay to match the CPU */
1674 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1675 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
1676 intel_de_write(dev_priv, reg, val);
1679 reg = PCH_TRANSCONF(pipe);
1680 val = intel_de_read(dev_priv, reg);
1681 pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe));
1683 if (HAS_PCH_IBX(dev_priv)) {
1684 /* Configure frame start delay to match the CPU */
1685 val &= ~TRANS_FRAME_START_DELAY_MASK;
1686 val |= TRANS_FRAME_START_DELAY(0);
1689 * Make the BPC in transcoder be consistent with
1690 * that in pipeconf reg. For HDMI we must use 8bpc
1691 * here for both 8bpc and 12bpc.
1693 val &= ~PIPECONF_BPC_MASK;
1694 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1695 val |= PIPECONF_8BPC;
1697 val |= pipeconf_val & PIPECONF_BPC_MASK;
1700 val &= ~TRANS_INTERLACE_MASK;
1701 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
1702 if (HAS_PCH_IBX(dev_priv) &&
1703 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
1704 val |= TRANS_LEGACY_INTERLACED_ILK;
1706 val |= TRANS_INTERLACED;
1708 val |= TRANS_PROGRESSIVE;
1711 intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
1712 if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
1713 drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",
1717 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1718 enum transcoder cpu_transcoder)
1720 u32 val, pipeconf_val;
1722 /* FDI must be feeding us bits for PCH ports */
1723 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1724 assert_fdi_rx_enabled(dev_priv, PIPE_A);
1726 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
1727 /* Workaround: set timing override bit. */
1728 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1729 /* Configure frame start delay to match the CPU */
1730 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1731 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
1732 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
1735 pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
1737 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1738 PIPECONF_INTERLACED_ILK)
1739 val |= TRANS_INTERLACED;
1741 val |= TRANS_PROGRESSIVE;
1743 intel_de_write(dev_priv, LPT_TRANSCONF, val);
1744 if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
1745 TRANS_STATE_ENABLE, 100))
1746 drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n");
1749 static void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1755 /* FDI relies on the transcoder */
1756 assert_fdi_tx_disabled(dev_priv, pipe);
1757 assert_fdi_rx_disabled(dev_priv, pipe);
1759 /* Ports must be off as well */
1760 assert_pch_ports_disabled(dev_priv, pipe);
1762 reg = PCH_TRANSCONF(pipe);
1763 val = intel_de_read(dev_priv, reg);
1764 val &= ~TRANS_ENABLE;
1765 intel_de_write(dev_priv, reg, val);
1766 /* wait for PCH transcoder off, transcoder state */
1767 if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
1768 drm_err(&dev_priv->drm, "failed to disable transcoder %c\n",
1771 if (HAS_PCH_CPT(dev_priv)) {
1772 /* Workaround: Clear the timing override chicken bit again. */
1773 reg = TRANS_CHICKEN2(pipe);
1774 val = intel_de_read(dev_priv, reg);
1775 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1776 intel_de_write(dev_priv, reg, val);
1780 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1784 val = intel_de_read(dev_priv, LPT_TRANSCONF);
1785 val &= ~TRANS_ENABLE;
1786 intel_de_write(dev_priv, LPT_TRANSCONF, val);
1787 /* wait for PCH transcoder off, transcoder state */
1788 if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
1789 TRANS_STATE_ENABLE, 50))
1790 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
1792 /* Workaround: clear timing override bit. */
1793 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
1794 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1795 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
1798 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1800 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1802 if (HAS_PCH_LPT(dev_priv))
1808 static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
1810 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1811 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1812 u32 mode_flags = crtc->mode_flags;
1815 * From Gen 11, In case of dsi cmd mode, frame counter wouldnt
1816 * have updated at the beginning of TE, if we want to use
1817 * the hw counter, then we would find it updated in only
1818 * the next TE, hence switching to sw counter.
1820 if (mode_flags & (I915_MODE_FLAG_DSI_USE_TE0 | I915_MODE_FLAG_DSI_USE_TE1))
1824 * On i965gm the hardware frame counter reads
1825 * zero when the TV encoder is enabled :(
1827 if (IS_I965GM(dev_priv) &&
1828 (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)))
1831 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1832 return 0xffffffff; /* full 32 bit counter */
1833 else if (INTEL_GEN(dev_priv) >= 3)
1834 return 0xffffff; /* only 24 bits of frame count */
1836 return 0; /* Gen2 doesn't have a hardware frame counter */
1839 void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
1841 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1843 assert_vblank_disabled(&crtc->base);
1844 drm_crtc_set_max_vblank_count(&crtc->base,
1845 intel_crtc_max_vblank_count(crtc_state));
1846 drm_crtc_vblank_on(&crtc->base);
1849 void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state)
1851 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1853 drm_crtc_vblank_off(&crtc->base);
1854 assert_vblank_disabled(&crtc->base);
1857 void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
1859 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1860 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1861 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1862 enum pipe pipe = crtc->pipe;
1866 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
1868 assert_planes_disabled(crtc);
1871 * A pipe without a PLL won't actually be able to drive bits from
1872 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1875 if (HAS_GMCH(dev_priv)) {
1876 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1877 assert_dsi_pll_enabled(dev_priv);
1879 assert_pll_enabled(dev_priv, pipe);
1881 if (new_crtc_state->has_pch_encoder) {
1882 /* if driving the PCH, we need FDI enabled */
1883 assert_fdi_rx_pll_enabled(dev_priv,
1884 intel_crtc_pch_transcoder(crtc));
1885 assert_fdi_tx_pll_enabled(dev_priv,
1886 (enum pipe) cpu_transcoder);
1888 /* FIXME: assert CPU port conditions for SNB+ */
1891 trace_intel_pipe_enable(crtc);
1893 reg = PIPECONF(cpu_transcoder);
1894 val = intel_de_read(dev_priv, reg);
1895 if (val & PIPECONF_ENABLE) {
1896 /* we keep both pipes enabled on 830 */
1897 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
1901 intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE);
1902 intel_de_posting_read(dev_priv, reg);
1905 * Until the pipe starts PIPEDSL reads will return a stale value,
1906 * which causes an apparent vblank timestamp jump when PIPEDSL
1907 * resets to its proper value. That also messes up the frame count
1908 * when it's derived from the timestamps. So let's wait for the
1909 * pipe to start properly before we call drm_crtc_vblank_on()
1911 if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
1912 intel_wait_for_pipe_scanline_moving(crtc);
1915 void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1917 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1918 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1919 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1920 enum pipe pipe = crtc->pipe;
1924 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));
1927 * Make sure planes won't keep trying to pump pixels to us,
1928 * or we might hang the display.
1930 assert_planes_disabled(crtc);
1932 trace_intel_pipe_disable(crtc);
1934 reg = PIPECONF(cpu_transcoder);
1935 val = intel_de_read(dev_priv, reg);
1936 if ((val & PIPECONF_ENABLE) == 0)
1940 * Double wide has implications for planes
1941 * so best keep it disabled when not needed.
1943 if (old_crtc_state->double_wide)
1944 val &= ~PIPECONF_DOUBLE_WIDE;
1946 /* Don't disable pipe or pipe PLLs if needed */
1947 if (!IS_I830(dev_priv))
1948 val &= ~PIPECONF_ENABLE;
1950 intel_de_write(dev_priv, reg, val);
1951 if ((val & PIPECONF_ENABLE) == 0)
1952 intel_wait_for_pipe_off(old_crtc_state);
1955 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1957 return IS_GEN(dev_priv, 2) ? 2048 : 4096;
1960 static bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
1962 if (!is_ccs_modifier(fb->modifier))
1965 return plane >= fb->format->num_planes / 2;
1968 static bool is_gen12_ccs_modifier(u64 modifier)
1970 return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
1971 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
1975 static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
1977 return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
1980 static bool is_aux_plane(const struct drm_framebuffer *fb, int plane)
1982 if (is_ccs_modifier(fb->modifier))
1983 return is_ccs_plane(fb, plane);
1988 static int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
1990 drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
1991 (main_plane && main_plane >= fb->format->num_planes / 2));
1993 return fb->format->num_planes / 2 + main_plane;
1996 static int ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
1998 drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
1999 ccs_plane < fb->format->num_planes / 2);
2001 return ccs_plane - fb->format->num_planes / 2;
2004 int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
2006 struct drm_i915_private *i915 = to_i915(fb->dev);
2008 if (is_ccs_modifier(fb->modifier))
2009 return main_to_ccs_plane(fb, main_plane);
2010 else if (INTEL_GEN(i915) < 11 &&
2011 intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
2018 intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
2021 return info->is_yuv &&
2022 info->num_planes == (is_ccs_modifier(modifier) ? 4 : 2);
2025 static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb,
2028 return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
2033 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
2035 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2036 unsigned int cpp = fb->format->cpp[color_plane];
2038 switch (fb->modifier) {
2039 case DRM_FORMAT_MOD_LINEAR:
2040 return intel_tile_size(dev_priv);
2041 case I915_FORMAT_MOD_X_TILED:
2042 if (IS_GEN(dev_priv, 2))
2046 case I915_FORMAT_MOD_Y_TILED_CCS:
2047 if (is_ccs_plane(fb, color_plane))
2050 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2051 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2052 if (is_ccs_plane(fb, color_plane))
2055 case I915_FORMAT_MOD_Y_TILED:
2056 if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
2060 case I915_FORMAT_MOD_Yf_TILED_CCS:
2061 if (is_ccs_plane(fb, color_plane))
2064 case I915_FORMAT_MOD_Yf_TILED:
2080 MISSING_CASE(fb->modifier);
2086 intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
2088 if (is_gen12_ccs_plane(fb, color_plane))
2091 return intel_tile_size(to_i915(fb->dev)) /
2092 intel_tile_width_bytes(fb, color_plane);
2095 /* Return the tile dimensions in pixel units */
2096 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
2097 unsigned int *tile_width,
2098 unsigned int *tile_height)
2100 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
2101 unsigned int cpp = fb->format->cpp[color_plane];
2103 *tile_width = tile_width_bytes / cpp;
2104 *tile_height = intel_tile_height(fb, color_plane);
2107 static unsigned int intel_tile_row_size(const struct drm_framebuffer *fb,
2110 unsigned int tile_width, tile_height;
2112 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2114 return fb->pitches[color_plane] * tile_height;
2118 intel_fb_align_height(const struct drm_framebuffer *fb,
2119 int color_plane, unsigned int height)
2121 unsigned int tile_height = intel_tile_height(fb, color_plane);
2123 return ALIGN(height, tile_height);
2126 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2128 unsigned int size = 0;
2131 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2132 size += rot_info->plane[i].width * rot_info->plane[i].height;
2137 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
2139 unsigned int size = 0;
2142 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++)
2143 size += rem_info->plane[i].width * rem_info->plane[i].height;
2149 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2150 const struct drm_framebuffer *fb,
2151 unsigned int rotation)
2153 view->type = I915_GGTT_VIEW_NORMAL;
2154 if (drm_rotation_90_or_270(rotation)) {
2155 view->type = I915_GGTT_VIEW_ROTATED;
2156 view->rotated = to_intel_framebuffer(fb)->rot_info;
2160 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2162 if (IS_I830(dev_priv))
2164 else if (IS_I85X(dev_priv))
2166 else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2172 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2174 if (INTEL_GEN(dev_priv) >= 9)
2176 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2177 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2179 else if (INTEL_GEN(dev_priv) >= 4)
2185 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2188 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2190 /* AUX_DIST needs only 4K alignment */
2191 if ((INTEL_GEN(dev_priv) < 12 && is_aux_plane(fb, color_plane)) ||
2192 is_ccs_plane(fb, color_plane))
2195 switch (fb->modifier) {
2196 case DRM_FORMAT_MOD_LINEAR:
2197 return intel_linear_alignment(dev_priv);
2198 case I915_FORMAT_MOD_X_TILED:
2199 if (INTEL_GEN(dev_priv) >= 9)
2202 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2203 if (is_semiplanar_uv_plane(fb, color_plane))
2204 return intel_tile_row_size(fb, color_plane);
2206 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2208 case I915_FORMAT_MOD_Y_TILED_CCS:
2209 case I915_FORMAT_MOD_Yf_TILED_CCS:
2210 case I915_FORMAT_MOD_Y_TILED:
2211 if (INTEL_GEN(dev_priv) >= 12 &&
2212 is_semiplanar_uv_plane(fb, color_plane))
2213 return intel_tile_row_size(fb, color_plane);
2215 case I915_FORMAT_MOD_Yf_TILED:
2216 return 1 * 1024 * 1024;
2218 MISSING_CASE(fb->modifier);
2223 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
2225 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2226 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2228 return INTEL_GEN(dev_priv) < 4 ||
2230 plane_state->view.type == I915_GGTT_VIEW_NORMAL);
2234 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2235 const struct i915_ggtt_view *view,
2237 unsigned long *out_flags)
2239 struct drm_device *dev = fb->dev;
2240 struct drm_i915_private *dev_priv = to_i915(dev);
2241 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2242 intel_wakeref_t wakeref;
2243 struct i915_vma *vma;
2244 unsigned int pinctl;
2247 if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj)))
2248 return ERR_PTR(-EINVAL);
2250 alignment = intel_surf_alignment(fb, 0);
2251 if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment)))
2252 return ERR_PTR(-EINVAL);
2254 /* Note that the w/a also requires 64 PTE of padding following the
2255 * bo. We currently fill all unused PTE with the shadow page and so
2256 * we should always have valid PTE following the scanout preventing
2259 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2260 alignment = 256 * 1024;
2263 * Global gtt pte registers are special registers which actually forward
2264 * writes to a chunk of system memory. Which means that there is no risk
2265 * that the register values disappear as soon as we call
2266 * intel_runtime_pm_put(), so it is correct to wrap only the
2267 * pin/unpin/fence and not more.
2269 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
2271 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2274 * Valleyview is definitely limited to scanning out the first
2275 * 512MiB. Lets presume this behaviour was inherited from the
2276 * g4x display engine and that all earlier gen are similarly
2277 * limited. Testing suggests that it is a little more
2278 * complicated than this. For example, Cherryview appears quite
2279 * happy to scanout from anywhere within its global aperture.
2282 if (HAS_GMCH(dev_priv))
2283 pinctl |= PIN_MAPPABLE;
2285 vma = i915_gem_object_pin_to_display_plane(obj,
2286 alignment, view, pinctl);
2290 if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
2294 * Install a fence for tiled scan-out. Pre-i965 always needs a
2295 * fence, whereas 965+ only requires a fence if using
2296 * framebuffer compression. For simplicity, we always, when
2297 * possible, install a fence as the cost is not that onerous.
2299 * If we fail to fence the tiled scanout, then either the
2300 * modeset will reject the change (which is highly unlikely as
2301 * the affected systems, all but one, do not have unmappable
2302 * space) or we will not be able to enable full powersaving
2303 * techniques (also likely not to apply due to various limits
2304 * FBC and the like impose on the size of the buffer, which
2305 * presumably we violated anyway with this unmappable buffer).
2306 * Anyway, it is presumably better to stumble onwards with
2307 * something and try to run the system in a "less than optimal"
2308 * mode that matches the user configuration.
2310 ret = i915_vma_pin_fence(vma);
2311 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
2312 i915_gem_object_unpin_from_display_plane(vma);
2317 if (ret == 0 && vma->fence)
2318 *out_flags |= PLANE_HAS_FENCE;
2323 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2324 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
2328 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
2330 i915_gem_object_lock(vma->obj, NULL);
2331 if (flags & PLANE_HAS_FENCE)
2332 i915_vma_unpin_fence(vma);
2333 i915_gem_object_unpin_from_display_plane(vma);
2334 i915_gem_object_unlock(vma->obj);
2339 static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane,
2340 unsigned int rotation)
2342 if (drm_rotation_90_or_270(rotation))
2343 return to_intel_framebuffer(fb)->rotated[color_plane].pitch;
2345 return fb->pitches[color_plane];
2349 * Convert the x/y offsets into a linear offset.
2350 * Only valid with 0/180 degree rotation, which is fine since linear
2351 * offset is only used with linear buffers on pre-hsw and tiled buffers
2352 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2354 u32 intel_fb_xy_to_linear(int x, int y,
2355 const struct intel_plane_state *state,
2358 const struct drm_framebuffer *fb = state->hw.fb;
2359 unsigned int cpp = fb->format->cpp[color_plane];
2360 unsigned int pitch = state->color_plane[color_plane].stride;
2362 return y * pitch + x * cpp;
2366 * Add the x/y offsets derived from fb->offsets[] to the user
2367 * specified plane src x/y offsets. The resulting x/y offsets
2368 * specify the start of scanout from the beginning of the gtt mapping.
2370 void intel_add_fb_offsets(int *x, int *y,
2371 const struct intel_plane_state *state,
2375 *x += state->color_plane[color_plane].x;
2376 *y += state->color_plane[color_plane].y;
2379 static u32 intel_adjust_tile_offset(int *x, int *y,
2380 unsigned int tile_width,
2381 unsigned int tile_height,
2382 unsigned int tile_size,
2383 unsigned int pitch_tiles,
2387 unsigned int pitch_pixels = pitch_tiles * tile_width;
2390 WARN_ON(old_offset & (tile_size - 1));
2391 WARN_ON(new_offset & (tile_size - 1));
2392 WARN_ON(new_offset > old_offset);
2394 tiles = (old_offset - new_offset) / tile_size;
2396 *y += tiles / pitch_tiles * tile_height;
2397 *x += tiles % pitch_tiles * tile_width;
2399 /* minimize x in case it got needlessly big */
2400 *y += *x / pitch_pixels * tile_height;
2406 static bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
2408 return fb->modifier == DRM_FORMAT_MOD_LINEAR ||
2409 is_gen12_ccs_plane(fb, color_plane);
2412 static u32 intel_adjust_aligned_offset(int *x, int *y,
2413 const struct drm_framebuffer *fb,
2415 unsigned int rotation,
2417 u32 old_offset, u32 new_offset)
2419 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2420 unsigned int cpp = fb->format->cpp[color_plane];
2422 drm_WARN_ON(&dev_priv->drm, new_offset > old_offset);
2424 if (!is_surface_linear(fb, color_plane)) {
2425 unsigned int tile_size, tile_width, tile_height;
2426 unsigned int pitch_tiles;
2428 tile_size = intel_tile_size(dev_priv);
2429 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2431 if (drm_rotation_90_or_270(rotation)) {
2432 pitch_tiles = pitch / tile_height;
2433 swap(tile_width, tile_height);
2435 pitch_tiles = pitch / (tile_width * cpp);
2438 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2439 tile_size, pitch_tiles,
2440 old_offset, new_offset);
2442 old_offset += *y * pitch + *x * cpp;
2444 *y = (old_offset - new_offset) / pitch;
2445 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2452 * Adjust the tile offset by moving the difference into
2455 static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
2456 const struct intel_plane_state *state,
2458 u32 old_offset, u32 new_offset)
2460 return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane,
2462 state->color_plane[color_plane].stride,
2463 old_offset, new_offset);
2467 * Computes the aligned offset to the base tile and adjusts
2468 * x, y. bytes per pixel is assumed to be a power-of-two.
2470 * In the 90/270 rotated case, x and y are assumed
2471 * to be already rotated to match the rotated GTT view, and
2472 * pitch is the tile_height aligned framebuffer height.
2474 * This function is used when computing the derived information
2475 * under intel_framebuffer, so using any of that information
2476 * here is not allowed. Anything under drm_framebuffer can be
2477 * used. This is why the user has to pass in the pitch since it
2478 * is specified in the rotated orientation.
2480 static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
2482 const struct drm_framebuffer *fb,
2485 unsigned int rotation,
2488 unsigned int cpp = fb->format->cpp[color_plane];
2489 u32 offset, offset_aligned;
2491 if (!is_surface_linear(fb, color_plane)) {
2492 unsigned int tile_size, tile_width, tile_height;
2493 unsigned int tile_rows, tiles, pitch_tiles;
2495 tile_size = intel_tile_size(dev_priv);
2496 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2498 if (drm_rotation_90_or_270(rotation)) {
2499 pitch_tiles = pitch / tile_height;
2500 swap(tile_width, tile_height);
2502 pitch_tiles = pitch / (tile_width * cpp);
2505 tile_rows = *y / tile_height;
2508 tiles = *x / tile_width;
2511 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2513 offset_aligned = offset;
2515 offset_aligned = rounddown(offset_aligned, alignment);
2517 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2518 tile_size, pitch_tiles,
2519 offset, offset_aligned);
2521 offset = *y * pitch + *x * cpp;
2522 offset_aligned = offset;
2524 offset_aligned = rounddown(offset_aligned, alignment);
2525 *y = (offset % alignment) / pitch;
2526 *x = ((offset % alignment) - *y * pitch) / cpp;
2532 return offset_aligned;
2535 static u32 intel_plane_compute_aligned_offset(int *x, int *y,
2536 const struct intel_plane_state *state,
2539 struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane);
2540 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2541 const struct drm_framebuffer *fb = state->hw.fb;
2542 unsigned int rotation = state->hw.rotation;
2543 int pitch = state->color_plane[color_plane].stride;
2546 if (intel_plane->id == PLANE_CURSOR)
2547 alignment = intel_cursor_alignment(dev_priv);
2549 alignment = intel_surf_alignment(fb, color_plane);
2551 return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane,
2552 pitch, rotation, alignment);
2555 /* Convert the fb->offset[] into x/y offsets */
2556 static int intel_fb_offset_to_xy(int *x, int *y,
2557 const struct drm_framebuffer *fb,
2560 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2561 unsigned int height;
2564 if (INTEL_GEN(dev_priv) >= 12 &&
2565 is_semiplanar_uv_plane(fb, color_plane))
2566 alignment = intel_tile_row_size(fb, color_plane);
2567 else if (fb->modifier != DRM_FORMAT_MOD_LINEAR)
2568 alignment = intel_tile_size(dev_priv);
2572 if (alignment != 0 && fb->offsets[color_plane] % alignment) {
2573 drm_dbg_kms(&dev_priv->drm,
2574 "Misaligned offset 0x%08x for color plane %d\n",
2575 fb->offsets[color_plane], color_plane);
2579 height = drm_framebuffer_plane_height(fb->height, fb, color_plane);
2580 height = ALIGN(height, intel_tile_height(fb, color_plane));
2582 /* Catch potential overflows early */
2583 if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]),
2584 fb->offsets[color_plane])) {
2585 drm_dbg_kms(&dev_priv->drm,
2586 "Bad offset 0x%08x or pitch %d for color plane %d\n",
2587 fb->offsets[color_plane], fb->pitches[color_plane],
2595 intel_adjust_aligned_offset(x, y,
2596 fb, color_plane, DRM_MODE_ROTATE_0,
2597 fb->pitches[color_plane],
2598 fb->offsets[color_plane], 0);
2603 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
2605 switch (fb_modifier) {
2606 case I915_FORMAT_MOD_X_TILED:
2607 return I915_TILING_X;
2608 case I915_FORMAT_MOD_Y_TILED:
2609 case I915_FORMAT_MOD_Y_TILED_CCS:
2610 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2611 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2612 return I915_TILING_Y;
2614 return I915_TILING_NONE;
2619 * From the Sky Lake PRM:
2620 * "The Color Control Surface (CCS) contains the compression status of
2621 * the cache-line pairs. The compression state of the cache-line pair
2622 * is specified by 2 bits in the CCS. Each CCS cache-line represents
2623 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2624 * cache-line-pairs. CCS is always Y tiled."
2626 * Since cache line pairs refers to horizontally adjacent cache lines,
2627 * each cache line in the CCS corresponds to an area of 32x16 cache
2628 * lines on the main surface. Since each pixel is 4 bytes, this gives
2629 * us a ratio of one byte in the CCS for each 8x16 pixels in the
2632 static const struct drm_format_info skl_ccs_formats[] = {
2633 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
2634 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2635 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
2636 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2637 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
2638 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2639 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
2640 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2644 * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
2645 * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
2646 * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
2647 * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
2650 static const struct drm_format_info gen12_ccs_formats[] = {
2651 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
2652 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2653 .hsub = 1, .vsub = 1, },
2654 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
2655 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2656 .hsub = 1, .vsub = 1, },
2657 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
2658 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2659 .hsub = 1, .vsub = 1, .has_alpha = true },
2660 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
2661 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2662 .hsub = 1, .vsub = 1, .has_alpha = true },
2663 { .format = DRM_FORMAT_YUYV, .num_planes = 2,
2664 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2665 .hsub = 2, .vsub = 1, .is_yuv = true },
2666 { .format = DRM_FORMAT_YVYU, .num_planes = 2,
2667 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2668 .hsub = 2, .vsub = 1, .is_yuv = true },
2669 { .format = DRM_FORMAT_UYVY, .num_planes = 2,
2670 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2671 .hsub = 2, .vsub = 1, .is_yuv = true },
2672 { .format = DRM_FORMAT_VYUY, .num_planes = 2,
2673 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2674 .hsub = 2, .vsub = 1, .is_yuv = true },
2675 { .format = DRM_FORMAT_NV12, .num_planes = 4,
2676 .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
2677 .hsub = 2, .vsub = 2, .is_yuv = true },
2678 { .format = DRM_FORMAT_P010, .num_planes = 4,
2679 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2680 .hsub = 2, .vsub = 2, .is_yuv = true },
2681 { .format = DRM_FORMAT_P012, .num_planes = 4,
2682 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2683 .hsub = 2, .vsub = 2, .is_yuv = true },
2684 { .format = DRM_FORMAT_P016, .num_planes = 4,
2685 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2686 .hsub = 2, .vsub = 2, .is_yuv = true },
2689 static const struct drm_format_info *
2690 lookup_format_info(const struct drm_format_info formats[],
2691 int num_formats, u32 format)
2695 for (i = 0; i < num_formats; i++) {
2696 if (formats[i].format == format)
2703 static const struct drm_format_info *
2704 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2706 switch (cmd->modifier[0]) {
2707 case I915_FORMAT_MOD_Y_TILED_CCS:
2708 case I915_FORMAT_MOD_Yf_TILED_CCS:
2709 return lookup_format_info(skl_ccs_formats,
2710 ARRAY_SIZE(skl_ccs_formats),
2712 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2713 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2714 return lookup_format_info(gen12_ccs_formats,
2715 ARRAY_SIZE(gen12_ccs_formats),
2722 bool is_ccs_modifier(u64 modifier)
2724 return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
2725 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
2726 modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2727 modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
2730 static int gen12_ccs_aux_stride(struct drm_framebuffer *fb, int ccs_plane)
2732 return DIV_ROUND_UP(fb->pitches[ccs_to_main_plane(fb, ccs_plane)],
2736 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
2737 u32 pixel_format, u64 modifier)
2739 struct intel_crtc *crtc;
2740 struct intel_plane *plane;
2743 * We assume the primary plane for pipe A has
2744 * the highest stride limits of them all,
2745 * if in case pipe A is disabled, use the first pipe from pipe_mask.
2747 crtc = intel_get_first_crtc(dev_priv);
2751 plane = to_intel_plane(crtc->base.primary);
2753 return plane->max_stride(plane, pixel_format, modifier,
2758 u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
2759 u32 pixel_format, u64 modifier)
2762 * Arbitrary limit for gen4+ chosen to match the
2763 * render engine max stride.
2765 * The new CCS hash mode makes remapping impossible
2767 if (!is_ccs_modifier(modifier)) {
2768 if (INTEL_GEN(dev_priv) >= 7)
2770 else if (INTEL_GEN(dev_priv) >= 4)
2774 return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
2778 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
2780 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2783 if (is_surface_linear(fb, color_plane)) {
2784 u32 max_stride = intel_plane_fb_max_stride(dev_priv,
2789 * To make remapping with linear generally feasible
2790 * we need the stride to be page aligned.
2792 if (fb->pitches[color_plane] > max_stride &&
2793 !is_ccs_modifier(fb->modifier))
2794 return intel_tile_size(dev_priv);
2799 tile_width = intel_tile_width_bytes(fb, color_plane);
2800 if (is_ccs_modifier(fb->modifier)) {
2802 * Display WA #0531: skl,bxt,kbl,glk
2804 * Render decompression and plane width > 3840
2805 * combined with horizontal panning requires the
2806 * plane stride to be a multiple of 4. We'll just
2807 * require the entire fb to accommodate that to avoid
2808 * potential runtime errors at plane configuration time.
2810 if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb->width > 3840)
2813 * The main surface pitch must be padded to a multiple of four
2816 else if (INTEL_GEN(dev_priv) >= 12)
2822 bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
2824 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2825 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2826 const struct drm_framebuffer *fb = plane_state->hw.fb;
2829 /* We don't want to deal with remapping with cursors */
2830 if (plane->id == PLANE_CURSOR)
2834 * The display engine limits already match/exceed the
2835 * render engine limits, so not much point in remapping.
2836 * Would also need to deal with the fence POT alignment
2837 * and gen2 2KiB GTT tile size.
2839 if (INTEL_GEN(dev_priv) < 4)
2843 * The new CCS hash mode isn't compatible with remapping as
2844 * the virtual address of the pages affects the compressed data.
2846 if (is_ccs_modifier(fb->modifier))
2849 /* Linear needs a page aligned stride for remapping */
2850 if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
2851 unsigned int alignment = intel_tile_size(dev_priv) - 1;
2853 for (i = 0; i < fb->format->num_planes; i++) {
2854 if (fb->pitches[i] & alignment)
2862 static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
2864 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2865 const struct drm_framebuffer *fb = plane_state->hw.fb;
2866 unsigned int rotation = plane_state->hw.rotation;
2867 u32 stride, max_stride;
2870 * No remapping for invisible planes since we don't have
2871 * an actual source viewport to remap.
2873 if (!plane_state->uapi.visible)
2876 if (!intel_plane_can_remap(plane_state))
2880 * FIXME: aux plane limits on gen9+ are
2881 * unclear in Bspec, for now no checking.
2883 stride = intel_fb_pitch(fb, 0, rotation);
2884 max_stride = plane->max_stride(plane, fb->format->format,
2885 fb->modifier, rotation);
2887 return stride > max_stride;
2891 intel_fb_plane_get_subsampling(int *hsub, int *vsub,
2892 const struct drm_framebuffer *fb,
2897 if (color_plane == 0) {
2905 * TODO: Deduct the subsampling from the char block for all CCS
2906 * formats and planes.
2908 if (!is_gen12_ccs_plane(fb, color_plane)) {
2909 *hsub = fb->format->hsub;
2910 *vsub = fb->format->vsub;
2915 main_plane = ccs_to_main_plane(fb, color_plane);
2916 *hsub = drm_format_info_block_width(fb->format, color_plane) /
2917 drm_format_info_block_width(fb->format, main_plane);
2920 * The min stride check in the core framebuffer_check() function
2921 * assumes that format->hsub applies to every plane except for the
2922 * first plane. That's incorrect for the CCS AUX plane of the first
2923 * plane, but for the above check to pass we must define the block
2924 * width with that subsampling applied to it. Adjust the width here
2925 * accordingly, so we can calculate the actual subsampling factor.
2927 if (main_plane == 0)
2928 *hsub *= fb->format->hsub;
2933 intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int ccs_plane, int x, int y)
2935 struct drm_i915_private *i915 = to_i915(fb->dev);
2936 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2939 int tile_width, tile_height;
2943 if (!is_ccs_plane(fb, ccs_plane))
2946 intel_tile_dims(fb, ccs_plane, &tile_width, &tile_height);
2947 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
2950 tile_height *= vsub;
2952 ccs_x = (x * hsub) % tile_width;
2953 ccs_y = (y * vsub) % tile_height;
2955 main_plane = ccs_to_main_plane(fb, ccs_plane);
2956 main_x = intel_fb->normal[main_plane].x % tile_width;
2957 main_y = intel_fb->normal[main_plane].y % tile_height;
2960 * CCS doesn't have its own x/y offset register, so the intra CCS tile
2961 * x/y offsets must match between CCS and the main surface.
2963 if (main_x != ccs_x || main_y != ccs_y) {
2964 drm_dbg_kms(&i915->drm,
2965 "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2968 intel_fb->normal[main_plane].x,
2969 intel_fb->normal[main_plane].y,
2978 intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int color_plane)
2980 int main_plane = is_ccs_plane(fb, color_plane) ?
2981 ccs_to_main_plane(fb, color_plane) : 0;
2982 int main_hsub, main_vsub;
2985 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, main_plane);
2986 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
2987 *w = fb->width / main_hsub / hsub;
2988 *h = fb->height / main_vsub / vsub;
2992 * Setup the rotated view for an FB plane and return the size the GTT mapping
2993 * requires for this view.
2996 setup_fb_rotation(int plane, const struct intel_remapped_plane_info *plane_info,
2997 u32 gtt_offset_rotated, int x, int y,
2998 unsigned int width, unsigned int height,
2999 unsigned int tile_size,
3000 unsigned int tile_width, unsigned int tile_height,
3001 struct drm_framebuffer *fb)
3003 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3004 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
3005 unsigned int pitch_tiles;
3008 /* Y or Yf modifiers required for 90/270 rotation */
3009 if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
3010 fb->modifier != I915_FORMAT_MOD_Yf_TILED)
3013 if (drm_WARN_ON(fb->dev, plane >= ARRAY_SIZE(rot_info->plane)))
3016 rot_info->plane[plane] = *plane_info;
3018 intel_fb->rotated[plane].pitch = plane_info->height * tile_height;
3020 /* rotate the x/y offsets to match the GTT view */
3021 drm_rect_init(&r, x, y, width, height);
3023 plane_info->width * tile_width,
3024 plane_info->height * tile_height,
3025 DRM_MODE_ROTATE_270);
3029 /* rotate the tile dimensions to match the GTT view */
3030 pitch_tiles = intel_fb->rotated[plane].pitch / tile_height;
3031 swap(tile_width, tile_height);
3034 * We only keep the x/y offsets, so push all of the
3035 * gtt offset into the x/y offsets.
3037 intel_adjust_tile_offset(&x, &y,
3038 tile_width, tile_height,
3039 tile_size, pitch_tiles,
3040 gtt_offset_rotated * tile_size, 0);
3043 * First pixel of the framebuffer from
3044 * the start of the rotated gtt mapping.
3046 intel_fb->rotated[plane].x = x;
3047 intel_fb->rotated[plane].y = y;
3049 return plane_info->width * plane_info->height;
3053 intel_fill_fb_info(struct drm_i915_private *dev_priv,
3054 struct drm_framebuffer *fb)
3056 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3057 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3058 u32 gtt_offset_rotated = 0;
3059 unsigned int max_size = 0;
3060 int i, num_planes = fb->format->num_planes;
3061 unsigned int tile_size = intel_tile_size(dev_priv);
3063 for (i = 0; i < num_planes; i++) {
3064 unsigned int width, height;
3065 unsigned int cpp, size;
3070 cpp = fb->format->cpp[i];
3071 intel_fb_plane_dims(&width, &height, fb, i);
3073 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
3075 drm_dbg_kms(&dev_priv->drm,
3076 "bad fb plane %d offset: 0x%x\n",
3081 ret = intel_fb_check_ccs_xy(fb, i, x, y);
3086 * The fence (if used) is aligned to the start of the object
3087 * so having the framebuffer wrap around across the edge of the
3088 * fenced region doesn't really work. We have no API to configure
3089 * the fence start offset within the object (nor could we probably
3090 * on gen2/3). So it's just easier if we just require that the
3091 * fb layout agrees with the fence layout. We already check that the
3092 * fb stride matches the fence stride elsewhere.
3094 if (i == 0 && i915_gem_object_is_tiled(obj) &&
3095 (x + width) * cpp > fb->pitches[i]) {
3096 drm_dbg_kms(&dev_priv->drm,
3097 "bad fb plane %d offset: 0x%x\n",
3103 * First pixel of the framebuffer from
3104 * the start of the normal gtt mapping.
3106 intel_fb->normal[i].x = x;
3107 intel_fb->normal[i].y = y;
3109 offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i,
3113 offset /= tile_size;
3115 if (!is_surface_linear(fb, i)) {
3116 struct intel_remapped_plane_info plane_info;
3117 unsigned int tile_width, tile_height;
3119 intel_tile_dims(fb, i, &tile_width, &tile_height);
3121 plane_info.offset = offset;
3122 plane_info.stride = DIV_ROUND_UP(fb->pitches[i],
3124 plane_info.width = DIV_ROUND_UP(x + width, tile_width);
3125 plane_info.height = DIV_ROUND_UP(y + height,
3128 /* how many tiles does this plane need */
3129 size = plane_info.stride * plane_info.height;
3131 * If the plane isn't horizontally tile aligned,
3132 * we need one more tile.
3137 gtt_offset_rotated +=
3138 setup_fb_rotation(i, &plane_info,
3140 x, y, width, height,
3142 tile_width, tile_height,
3145 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
3146 x * cpp, tile_size);
3149 /* how many tiles in total needed in the bo */
3150 max_size = max(max_size, offset + size);
3153 if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
3154 drm_dbg_kms(&dev_priv->drm,
3155 "fb too big for bo (need %llu bytes, have %zu bytes)\n",
3156 mul_u32_u32(max_size, tile_size), obj->base.size);
3164 intel_plane_remap_gtt(struct intel_plane_state *plane_state)
3166 struct drm_i915_private *dev_priv =
3167 to_i915(plane_state->uapi.plane->dev);
3168 struct drm_framebuffer *fb = plane_state->hw.fb;
3169 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3170 struct intel_rotation_info *info = &plane_state->view.rotated;
3171 unsigned int rotation = plane_state->hw.rotation;
3172 int i, num_planes = fb->format->num_planes;
3173 unsigned int tile_size = intel_tile_size(dev_priv);
3174 unsigned int src_x, src_y;
3175 unsigned int src_w, src_h;
3178 memset(&plane_state->view, 0, sizeof(plane_state->view));
3179 plane_state->view.type = drm_rotation_90_or_270(rotation) ?
3180 I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED;
3182 src_x = plane_state->uapi.src.x1 >> 16;
3183 src_y = plane_state->uapi.src.y1 >> 16;
3184 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
3185 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
3187 drm_WARN_ON(&dev_priv->drm, is_ccs_modifier(fb->modifier));
3189 /* Make src coordinates relative to the viewport */
3190 drm_rect_translate(&plane_state->uapi.src,
3191 -(src_x << 16), -(src_y << 16));
3193 /* Rotate src coordinates to match rotated GTT view */
3194 if (drm_rotation_90_or_270(rotation))
3195 drm_rect_rotate(&plane_state->uapi.src,
3196 src_w << 16, src_h << 16,
3197 DRM_MODE_ROTATE_270);
3199 for (i = 0; i < num_planes; i++) {
3200 unsigned int hsub = i ? fb->format->hsub : 1;
3201 unsigned int vsub = i ? fb->format->vsub : 1;
3202 unsigned int cpp = fb->format->cpp[i];
3203 unsigned int tile_width, tile_height;
3204 unsigned int width, height;
3205 unsigned int pitch_tiles;
3209 intel_tile_dims(fb, i, &tile_width, &tile_height);
3213 width = src_w / hsub;
3214 height = src_h / vsub;
3217 * First pixel of the src viewport from the
3218 * start of the normal gtt mapping.
3220 x += intel_fb->normal[i].x;
3221 y += intel_fb->normal[i].y;
3223 offset = intel_compute_aligned_offset(dev_priv, &x, &y,
3224 fb, i, fb->pitches[i],
3225 DRM_MODE_ROTATE_0, tile_size);
3226 offset /= tile_size;
3228 drm_WARN_ON(&dev_priv->drm, i >= ARRAY_SIZE(info->plane));
3229 info->plane[i].offset = offset;
3230 info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],
3232 info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
3233 info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
3235 if (drm_rotation_90_or_270(rotation)) {
3238 /* rotate the x/y offsets to match the GTT view */
3239 drm_rect_init(&r, x, y, width, height);
3241 info->plane[i].width * tile_width,
3242 info->plane[i].height * tile_height,
3243 DRM_MODE_ROTATE_270);
3247 pitch_tiles = info->plane[i].height;
3248 plane_state->color_plane[i].stride = pitch_tiles * tile_height;
3250 /* rotate the tile dimensions to match the GTT view */
3251 swap(tile_width, tile_height);
3253 pitch_tiles = info->plane[i].width;
3254 plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp;
3258 * We only keep the x/y offsets, so push all of the
3259 * gtt offset into the x/y offsets.
3261 intel_adjust_tile_offset(&x, &y,
3262 tile_width, tile_height,
3263 tile_size, pitch_tiles,
3264 gtt_offset * tile_size, 0);
3266 gtt_offset += info->plane[i].width * info->plane[i].height;
3268 plane_state->color_plane[i].offset = 0;
3269 plane_state->color_plane[i].x = x;
3270 plane_state->color_plane[i].y = y;
3275 intel_plane_compute_gtt(struct intel_plane_state *plane_state)
3277 const struct intel_framebuffer *fb =
3278 to_intel_framebuffer(plane_state->hw.fb);
3279 unsigned int rotation = plane_state->hw.rotation;
3285 num_planes = fb->base.format->num_planes;
3287 if (intel_plane_needs_remap(plane_state)) {
3288 intel_plane_remap_gtt(plane_state);
3291 * Sometimes even remapping can't overcome
3292 * the stride limitations :( Can happen with
3293 * big plane sizes and suitably misaligned
3296 return intel_plane_check_stride(plane_state);
3299 intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation);
3301 for (i = 0; i < num_planes; i++) {
3302 plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation);
3303 plane_state->color_plane[i].offset = 0;
3305 if (drm_rotation_90_or_270(rotation)) {
3306 plane_state->color_plane[i].x = fb->rotated[i].x;
3307 plane_state->color_plane[i].y = fb->rotated[i].y;
3309 plane_state->color_plane[i].x = fb->normal[i].x;
3310 plane_state->color_plane[i].y = fb->normal[i].y;
3314 /* Rotate src coordinates to match rotated GTT view */
3315 if (drm_rotation_90_or_270(rotation))
3316 drm_rect_rotate(&plane_state->uapi.src,
3317 fb->base.width << 16, fb->base.height << 16,
3318 DRM_MODE_ROTATE_270);
3320 return intel_plane_check_stride(plane_state);
3323 static int i9xx_format_to_fourcc(int format)
3326 case DISPPLANE_8BPP:
3327 return DRM_FORMAT_C8;
3328 case DISPPLANE_BGRA555:
3329 return DRM_FORMAT_ARGB1555;
3330 case DISPPLANE_BGRX555:
3331 return DRM_FORMAT_XRGB1555;
3332 case DISPPLANE_BGRX565:
3333 return DRM_FORMAT_RGB565;
3335 case DISPPLANE_BGRX888:
3336 return DRM_FORMAT_XRGB8888;
3337 case DISPPLANE_RGBX888:
3338 return DRM_FORMAT_XBGR8888;
3339 case DISPPLANE_BGRA888:
3340 return DRM_FORMAT_ARGB8888;
3341 case DISPPLANE_RGBA888:
3342 return DRM_FORMAT_ABGR8888;
3343 case DISPPLANE_BGRX101010:
3344 return DRM_FORMAT_XRGB2101010;
3345 case DISPPLANE_RGBX101010:
3346 return DRM_FORMAT_XBGR2101010;
3347 case DISPPLANE_BGRA101010:
3348 return DRM_FORMAT_ARGB2101010;
3349 case DISPPLANE_RGBA101010:
3350 return DRM_FORMAT_ABGR2101010;
3351 case DISPPLANE_RGBX161616:
3352 return DRM_FORMAT_XBGR16161616F;
3356 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
3359 case PLANE_CTL_FORMAT_RGB_565:
3360 return DRM_FORMAT_RGB565;
3361 case PLANE_CTL_FORMAT_NV12:
3362 return DRM_FORMAT_NV12;
3363 case PLANE_CTL_FORMAT_XYUV:
3364 return DRM_FORMAT_XYUV8888;
3365 case PLANE_CTL_FORMAT_P010:
3366 return DRM_FORMAT_P010;
3367 case PLANE_CTL_FORMAT_P012:
3368 return DRM_FORMAT_P012;
3369 case PLANE_CTL_FORMAT_P016:
3370 return DRM_FORMAT_P016;
3371 case PLANE_CTL_FORMAT_Y210:
3372 return DRM_FORMAT_Y210;
3373 case PLANE_CTL_FORMAT_Y212:
3374 return DRM_FORMAT_Y212;
3375 case PLANE_CTL_FORMAT_Y216:
3376 return DRM_FORMAT_Y216;
3377 case PLANE_CTL_FORMAT_Y410:
3378 return DRM_FORMAT_XVYU2101010;
3379 case PLANE_CTL_FORMAT_Y412:
3380 return DRM_FORMAT_XVYU12_16161616;
3381 case PLANE_CTL_FORMAT_Y416:
3382 return DRM_FORMAT_XVYU16161616;
3384 case PLANE_CTL_FORMAT_XRGB_8888:
3387 return DRM_FORMAT_ABGR8888;
3389 return DRM_FORMAT_XBGR8888;
3392 return DRM_FORMAT_ARGB8888;
3394 return DRM_FORMAT_XRGB8888;
3396 case PLANE_CTL_FORMAT_XRGB_2101010:
3399 return DRM_FORMAT_ABGR2101010;
3401 return DRM_FORMAT_XBGR2101010;
3404 return DRM_FORMAT_ARGB2101010;
3406 return DRM_FORMAT_XRGB2101010;
3408 case PLANE_CTL_FORMAT_XRGB_16161616F:
3411 return DRM_FORMAT_ABGR16161616F;
3413 return DRM_FORMAT_XBGR16161616F;
3416 return DRM_FORMAT_ARGB16161616F;
3418 return DRM_FORMAT_XRGB16161616F;
3423 static struct i915_vma *
3424 initial_plane_vma(struct drm_i915_private *i915,
3425 struct intel_initial_plane_config *plane_config)
3427 struct drm_i915_gem_object *obj;
3428 struct i915_vma *vma;
3431 if (plane_config->size == 0)
3434 base = round_down(plane_config->base,
3435 I915_GTT_MIN_ALIGNMENT);
3436 size = round_up(plane_config->base + plane_config->size,
3437 I915_GTT_MIN_ALIGNMENT);
3441 * If the FB is too big, just don't use it since fbdev is not very
3442 * important and we should probably use that space with FBC or other
3445 if (size * 2 > i915->stolen_usable_size)
3448 obj = i915_gem_object_create_stolen_for_preallocated(i915, base, size);
3453 * Mark it WT ahead of time to avoid changing the
3454 * cache_level during fbdev initialization. The
3455 * unbind there would get stuck waiting for rcu.
3457 i915_gem_object_set_cache_coherency(obj, HAS_WT(i915) ?
3458 I915_CACHE_WT : I915_CACHE_NONE);
3460 switch (plane_config->tiling) {
3461 case I915_TILING_NONE:
3465 obj->tiling_and_stride =
3466 plane_config->fb->base.pitches[0] |
3467 plane_config->tiling;
3470 MISSING_CASE(plane_config->tiling);
3474 vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
3478 if (i915_ggtt_pin(vma, NULL, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base))
3481 if (i915_gem_object_is_tiled(obj) &&
3482 !i915_vma_is_map_and_fenceable(vma))
3488 i915_gem_object_put(obj);
3493 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
3494 struct intel_initial_plane_config *plane_config)
3496 struct drm_device *dev = crtc->base.dev;
3497 struct drm_i915_private *dev_priv = to_i915(dev);
3498 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
3499 struct drm_framebuffer *fb = &plane_config->fb->base;
3500 struct i915_vma *vma;
3502 switch (fb->modifier) {
3503 case DRM_FORMAT_MOD_LINEAR:
3504 case I915_FORMAT_MOD_X_TILED:
3505 case I915_FORMAT_MOD_Y_TILED:
3508 drm_dbg(&dev_priv->drm,
3509 "Unsupported modifier for initial FB: 0x%llx\n",
3514 vma = initial_plane_vma(dev_priv, plane_config);
3518 mode_cmd.pixel_format = fb->format->format;
3519 mode_cmd.width = fb->width;
3520 mode_cmd.height = fb->height;
3521 mode_cmd.pitches[0] = fb->pitches[0];
3522 mode_cmd.modifier[0] = fb->modifier;
3523 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
3525 if (intel_framebuffer_init(to_intel_framebuffer(fb),
3526 vma->obj, &mode_cmd)) {
3527 drm_dbg_kms(&dev_priv->drm, "intel fb init failed\n");
3531 plane_config->vma = vma;
3540 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
3541 struct intel_plane_state *plane_state,
3544 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
3546 plane_state->uapi.visible = visible;
3549 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
3551 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
3554 static void fixup_active_planes(struct intel_crtc_state *crtc_state)
3556 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3557 struct drm_plane *plane;
3560 * Active_planes aliases if multiple "primary" or cursor planes
3561 * have been used on the same (or wrong) pipe. plane_mask uses
3562 * unique ids, hence we can use that to reconstruct active_planes.
3564 crtc_state->active_planes = 0;
3566 drm_for_each_plane_mask(plane, &dev_priv->drm,
3567 crtc_state->uapi.plane_mask)
3568 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
3571 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
3572 struct intel_plane *plane)
3574 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3575 struct intel_crtc_state *crtc_state =
3576 to_intel_crtc_state(crtc->base.state);
3577 struct intel_plane_state *plane_state =
3578 to_intel_plane_state(plane->base.state);
3580 drm_dbg_kms(&dev_priv->drm,
3581 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
3582 plane->base.base.id, plane->base.name,
3583 crtc->base.base.id, crtc->base.name);
3585 intel_set_plane_visible(crtc_state, plane_state, false);
3586 fixup_active_planes(crtc_state);
3587 crtc_state->data_rate[plane->id] = 0;
3588 crtc_state->min_cdclk[plane->id] = 0;
3590 if (plane->id == PLANE_PRIMARY)
3591 hsw_disable_ips(crtc_state);
3594 * Vblank time updates from the shadow to live plane control register
3595 * are blocked if the memory self-refresh mode is active at that
3596 * moment. So to make sure the plane gets truly disabled, disable
3597 * first the self-refresh mode. The self-refresh enable bit in turn
3598 * will be checked/applied by the HW only at the next frame start
3599 * event which is after the vblank start event, so we need to have a
3600 * wait-for-vblank between disabling the plane and the pipe.
3602 if (HAS_GMCH(dev_priv) &&
3603 intel_set_memory_cxsr(dev_priv, false))
3604 intel_wait_for_vblank(dev_priv, crtc->pipe);
3607 * Gen2 reports pipe underruns whenever all planes are disabled.
3608 * So disable underrun reporting before all the planes get disabled.
3610 if (IS_GEN(dev_priv, 2) && !crtc_state->active_planes)
3611 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
3613 intel_disable_plane(plane, crtc_state);
3616 static struct intel_frontbuffer *
3617 to_intel_frontbuffer(struct drm_framebuffer *fb)
3619 return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
3623 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
3624 struct intel_initial_plane_config *plane_config)
3626 struct drm_device *dev = intel_crtc->base.dev;
3627 struct drm_i915_private *dev_priv = to_i915(dev);
3629 struct drm_plane *primary = intel_crtc->base.primary;
3630 struct drm_plane_state *plane_state = primary->state;
3631 struct intel_plane *intel_plane = to_intel_plane(primary);
3632 struct intel_plane_state *intel_state =
3633 to_intel_plane_state(plane_state);
3634 struct drm_framebuffer *fb;
3635 struct i915_vma *vma;
3637 if (!plane_config->fb)
3640 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
3641 fb = &plane_config->fb->base;
3642 vma = plane_config->vma;
3647 * Failed to alloc the obj, check to see if we should share
3648 * an fb with another CRTC instead
3650 for_each_crtc(dev, c) {
3651 struct intel_plane_state *state;
3653 if (c == &intel_crtc->base)
3656 if (!to_intel_crtc(c)->active)
3659 state = to_intel_plane_state(c->primary->state);
3663 if (intel_plane_ggtt_offset(state) == plane_config->base) {
3671 * We've failed to reconstruct the BIOS FB. Current display state
3672 * indicates that the primary plane is visible, but has a NULL FB,
3673 * which will lead to problems later if we don't fix it up. The
3674 * simplest solution is to just disable the primary plane now and
3675 * pretend the BIOS never had it enabled.
3677 intel_plane_disable_noatomic(intel_crtc, intel_plane);
3682 intel_state->hw.rotation = plane_config->rotation;
3683 intel_fill_fb_ggtt_view(&intel_state->view, fb,
3684 intel_state->hw.rotation);
3685 intel_state->color_plane[0].stride =
3686 intel_fb_pitch(fb, 0, intel_state->hw.rotation);
3688 __i915_vma_pin(vma);
3689 intel_state->vma = i915_vma_get(vma);
3690 if (intel_plane_uses_fence(intel_state) && i915_vma_pin_fence(vma) == 0)
3692 intel_state->flags |= PLANE_HAS_FENCE;
3694 plane_state->src_x = 0;
3695 plane_state->src_y = 0;
3696 plane_state->src_w = fb->width << 16;
3697 plane_state->src_h = fb->height << 16;
3699 plane_state->crtc_x = 0;
3700 plane_state->crtc_y = 0;
3701 plane_state->crtc_w = fb->width;
3702 plane_state->crtc_h = fb->height;
3704 intel_state->uapi.src = drm_plane_state_src(plane_state);
3705 intel_state->uapi.dst = drm_plane_state_dest(plane_state);
3707 if (plane_config->tiling)
3708 dev_priv->preserve_bios_swizzle = true;
3710 plane_state->fb = fb;
3711 drm_framebuffer_get(fb);
3713 plane_state->crtc = &intel_crtc->base;
3714 intel_plane_copy_uapi_to_hw_state(intel_state, intel_state);
3716 intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
3718 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
3719 &to_intel_frontbuffer(fb)->bits);
3722 static int skl_max_plane_width(const struct drm_framebuffer *fb,
3724 unsigned int rotation)
3726 int cpp = fb->format->cpp[color_plane];
3728 switch (fb->modifier) {
3729 case DRM_FORMAT_MOD_LINEAR:
3730 case I915_FORMAT_MOD_X_TILED:
3732 * Validated limit is 4k, but has 5k should
3733 * work apart from the following features:
3734 * - Ytile (already limited to 4k)
3735 * - FP16 (already limited to 4k)
3736 * - render compression (already limited to 4k)
3737 * - KVMR sprite and cursor (don't care)
3738 * - horizontal panning (TODO verify this)
3739 * - pipe and plane scaling (TODO verify this)
3745 case I915_FORMAT_MOD_Y_TILED_CCS:
3746 case I915_FORMAT_MOD_Yf_TILED_CCS:
3747 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
3748 /* FIXME AUX plane? */
3749 case I915_FORMAT_MOD_Y_TILED:
3750 case I915_FORMAT_MOD_Yf_TILED:
3756 MISSING_CASE(fb->modifier);
3761 static int glk_max_plane_width(const struct drm_framebuffer *fb,
3763 unsigned int rotation)
3765 int cpp = fb->format->cpp[color_plane];
3767 switch (fb->modifier) {
3768 case DRM_FORMAT_MOD_LINEAR:
3769 case I915_FORMAT_MOD_X_TILED:
3774 case I915_FORMAT_MOD_Y_TILED_CCS:
3775 case I915_FORMAT_MOD_Yf_TILED_CCS:
3776 /* FIXME AUX plane? */
3777 case I915_FORMAT_MOD_Y_TILED:
3778 case I915_FORMAT_MOD_Yf_TILED:
3784 MISSING_CASE(fb->modifier);
3789 static int icl_min_plane_width(const struct drm_framebuffer *fb)
3791 /* Wa_14011264657, Wa_14011050563: gen11+ */
3792 switch (fb->format->format) {
3795 case DRM_FORMAT_RGB565:
3797 case DRM_FORMAT_XRGB8888:
3798 case DRM_FORMAT_XBGR8888:
3799 case DRM_FORMAT_ARGB8888:
3800 case DRM_FORMAT_ABGR8888:
3801 case DRM_FORMAT_XRGB2101010:
3802 case DRM_FORMAT_XBGR2101010:
3803 case DRM_FORMAT_ARGB2101010:
3804 case DRM_FORMAT_ABGR2101010:
3805 case DRM_FORMAT_XVYU2101010:
3806 case DRM_FORMAT_Y212:
3807 case DRM_FORMAT_Y216:
3809 case DRM_FORMAT_NV12:
3811 case DRM_FORMAT_P010:
3812 case DRM_FORMAT_P012:
3813 case DRM_FORMAT_P016:
3815 case DRM_FORMAT_XRGB16161616F:
3816 case DRM_FORMAT_XBGR16161616F:
3817 case DRM_FORMAT_ARGB16161616F:
3818 case DRM_FORMAT_ABGR16161616F:
3819 case DRM_FORMAT_XVYU12_16161616:
3820 case DRM_FORMAT_XVYU16161616:
3827 static int icl_max_plane_width(const struct drm_framebuffer *fb,
3829 unsigned int rotation)
3834 static int skl_max_plane_height(void)
3839 static int icl_max_plane_height(void)
3845 skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
3846 int main_x, int main_y, u32 main_offset,
3849 const struct drm_framebuffer *fb = plane_state->hw.fb;
3850 int aux_x = plane_state->color_plane[ccs_plane].x;
3851 int aux_y = plane_state->color_plane[ccs_plane].y;
3852 u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
3853 u32 alignment = intel_surf_alignment(fb, ccs_plane);
3857 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
3858 while (aux_offset >= main_offset && aux_y <= main_y) {
3861 if (aux_x == main_x && aux_y == main_y)
3864 if (aux_offset == 0)
3869 aux_offset = intel_plane_adjust_aligned_offset(&x, &y,
3875 aux_x = x * hsub + aux_x % hsub;
3876 aux_y = y * vsub + aux_y % vsub;
3879 if (aux_x != main_x || aux_y != main_y)
3882 plane_state->color_plane[ccs_plane].offset = aux_offset;
3883 plane_state->color_plane[ccs_plane].x = aux_x;
3884 plane_state->color_plane[ccs_plane].y = aux_y;
3890 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
3894 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3895 plane_state->color_plane[0].offset, 0);
3900 static int skl_check_main_surface(struct intel_plane_state *plane_state)
3902 struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev);
3903 const struct drm_framebuffer *fb = plane_state->hw.fb;
3904 unsigned int rotation = plane_state->hw.rotation;
3905 int x = plane_state->uapi.src.x1 >> 16;
3906 int y = plane_state->uapi.src.y1 >> 16;
3907 int w = drm_rect_width(&plane_state->uapi.src) >> 16;
3908 int h = drm_rect_height(&plane_state->uapi.src) >> 16;
3909 int max_width, min_width, max_height;
3910 u32 alignment, offset;
3911 int aux_plane = intel_main_to_aux_plane(fb, 0);
3912 u32 aux_offset = plane_state->color_plane[aux_plane].offset;
3914 if (INTEL_GEN(dev_priv) >= 11) {
3915 max_width = icl_max_plane_width(fb, 0, rotation);
3916 min_width = icl_min_plane_width(fb);
3917 } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
3918 max_width = glk_max_plane_width(fb, 0, rotation);
3921 max_width = skl_max_plane_width(fb, 0, rotation);
3925 if (INTEL_GEN(dev_priv) >= 11)
3926 max_height = icl_max_plane_height();
3928 max_height = skl_max_plane_height();
3930 if (w > max_width || w < min_width || h > max_height) {
3931 drm_dbg_kms(&dev_priv->drm,
3932 "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n",
3933 w, h, min_width, max_width, max_height);
3937 intel_add_fb_offsets(&x, &y, plane_state, 0);
3938 offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);
3939 alignment = intel_surf_alignment(fb, 0);
3940 if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment)))
3944 * AUX surface offset is specified as the distance from the
3945 * main surface offset, and it must be non-negative. Make
3946 * sure that is what we will get.
3948 if (aux_plane && offset > aux_offset)
3949 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3950 offset, aux_offset & ~(alignment - 1));
3953 * When using an X-tiled surface, the plane blows up
3954 * if the x offset + width exceed the stride.
3956 * TODO: linear and Y-tiled seem fine, Yf untested,
3958 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3959 int cpp = fb->format->cpp[0];
3961 while ((x + w) * cpp > plane_state->color_plane[0].stride) {
3963 drm_dbg_kms(&dev_priv->drm,
3964 "Unable to find suitable display surface offset due to X-tiling\n");
3968 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3969 offset, offset - alignment);
3974 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3975 * they match with the main surface x/y offsets.
3977 if (is_ccs_modifier(fb->modifier)) {
3978 while (!skl_check_main_ccs_coordinates(plane_state, x, y,
3979 offset, aux_plane)) {
3983 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3984 offset, offset - alignment);
3987 if (x != plane_state->color_plane[aux_plane].x ||
3988 y != plane_state->color_plane[aux_plane].y) {
3989 drm_dbg_kms(&dev_priv->drm,
3990 "Unable to find suitable display surface offset due to CCS\n");
3995 plane_state->color_plane[0].offset = offset;
3996 plane_state->color_plane[0].x = x;
3997 plane_state->color_plane[0].y = y;
4000 * Put the final coordinates back so that the src
4001 * coordinate checks will see the right values.
4003 drm_rect_translate_to(&plane_state->uapi.src,
4009 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
4011 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
4012 const struct drm_framebuffer *fb = plane_state->hw.fb;
4013 unsigned int rotation = plane_state->hw.rotation;
4015 int max_width = skl_max_plane_width(fb, uv_plane, rotation);
4016 int max_height = 4096;
4017 int x = plane_state->uapi.src.x1 >> 17;
4018 int y = plane_state->uapi.src.y1 >> 17;
4019 int w = drm_rect_width(&plane_state->uapi.src) >> 17;
4020 int h = drm_rect_height(&plane_state->uapi.src) >> 17;
4023 intel_add_fb_offsets(&x, &y, plane_state, uv_plane);
4024 offset = intel_plane_compute_aligned_offset(&x, &y,
4025 plane_state, uv_plane);
4027 /* FIXME not quite sure how/if these apply to the chroma plane */
4028 if (w > max_width || h > max_height) {
4029 drm_dbg_kms(&i915->drm,
4030 "CbCr source size %dx%d too big (limit %dx%d)\n",
4031 w, h, max_width, max_height);
4035 if (is_ccs_modifier(fb->modifier)) {
4036 int ccs_plane = main_to_ccs_plane(fb, uv_plane);
4037 u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
4038 u32 alignment = intel_surf_alignment(fb, uv_plane);
4040 if (offset > aux_offset)
4041 offset = intel_plane_adjust_aligned_offset(&x, &y,
4045 aux_offset & ~(alignment - 1));
4047 while (!skl_check_main_ccs_coordinates(plane_state, x, y,
4048 offset, ccs_plane)) {
4052 offset = intel_plane_adjust_aligned_offset(&x, &y,
4055 offset, offset - alignment);
4058 if (x != plane_state->color_plane[ccs_plane].x ||
4059 y != plane_state->color_plane[ccs_plane].y) {
4060 drm_dbg_kms(&i915->drm,
4061 "Unable to find suitable display surface offset due to CCS\n");
4066 plane_state->color_plane[uv_plane].offset = offset;
4067 plane_state->color_plane[uv_plane].x = x;
4068 plane_state->color_plane[uv_plane].y = y;
4073 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
4075 const struct drm_framebuffer *fb = plane_state->hw.fb;
4076 int src_x = plane_state->uapi.src.x1 >> 16;
4077 int src_y = plane_state->uapi.src.y1 >> 16;
4081 for (ccs_plane = 0; ccs_plane < fb->format->num_planes; ccs_plane++) {
4082 int main_hsub, main_vsub;
4086 if (!is_ccs_plane(fb, ccs_plane))
4089 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb,
4090 ccs_to_main_plane(fb, ccs_plane));
4091 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
4098 intel_add_fb_offsets(&x, &y, plane_state, ccs_plane);
4100 offset = intel_plane_compute_aligned_offset(&x, &y,
4104 plane_state->color_plane[ccs_plane].offset = offset;
4105 plane_state->color_plane[ccs_plane].x = (x * hsub +
4108 plane_state->color_plane[ccs_plane].y = (y * vsub +
4116 int skl_check_plane_surface(struct intel_plane_state *plane_state)
4118 const struct drm_framebuffer *fb = plane_state->hw.fb;
4121 ret = intel_plane_compute_gtt(plane_state);
4125 if (!plane_state->uapi.visible)
4129 * Handle the AUX surface first since the main surface setup depends on
4132 if (is_ccs_modifier(fb->modifier)) {
4133 ret = skl_check_ccs_aux_surface(plane_state);
4138 if (intel_format_info_is_yuv_semiplanar(fb->format,
4140 ret = skl_check_nv12_aux_surface(plane_state);
4145 for (i = fb->format->num_planes; i < ARRAY_SIZE(plane_state->color_plane); i++) {
4146 plane_state->color_plane[i].offset = 0;
4147 plane_state->color_plane[i].x = 0;
4148 plane_state->color_plane[i].y = 0;
4151 ret = skl_check_main_surface(plane_state);
4158 static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state,
4159 const struct intel_plane_state *plane_state,
4160 unsigned int *num, unsigned int *den)
4162 const struct drm_framebuffer *fb = plane_state->hw.fb;
4163 unsigned int cpp = fb->format->cpp[0];
4166 * g4x bspec says 64bpp pixel rate can't exceed 80%
4167 * of cdclk when the sprite plane is enabled on the
4168 * same pipe. ilk/snb bspec says 64bpp pixel rate is
4169 * never allowed to exceed 80% of cdclk. Let's just go
4170 * with the ilk/snb limit always.
4181 static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
4182 const struct intel_plane_state *plane_state)
4184 unsigned int pixel_rate;
4185 unsigned int num, den;
4188 * Note that crtc_state->pixel_rate accounts for both
4189 * horizontal and vertical panel fitter downscaling factors.
4190 * Pre-HSW bspec tells us to only consider the horizontal
4191 * downscaling factor here. We ignore that and just consider
4192 * both for simplicity.
4194 pixel_rate = crtc_state->pixel_rate;
4196 i9xx_plane_ratio(crtc_state, plane_state, &num, &den);
4198 /* two pixels per clock with double wide pipe */
4199 if (crtc_state->double_wide)
4202 return DIV_ROUND_UP(pixel_rate * num, den);
4206 i9xx_plane_max_stride(struct intel_plane *plane,
4207 u32 pixel_format, u64 modifier,
4208 unsigned int rotation)
4210 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4212 if (!HAS_GMCH(dev_priv)) {
4214 } else if (INTEL_GEN(dev_priv) >= 4) {
4215 if (modifier == I915_FORMAT_MOD_X_TILED)
4219 } else if (INTEL_GEN(dev_priv) >= 3) {
4220 if (modifier == I915_FORMAT_MOD_X_TILED)
4225 if (plane->i9xx_plane == PLANE_C)
4232 static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
4234 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4235 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4238 if (crtc_state->gamma_enable)
4239 dspcntr |= DISPPLANE_GAMMA_ENABLE;
4241 if (crtc_state->csc_enable)
4242 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
4244 if (INTEL_GEN(dev_priv) < 5)
4245 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
4250 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
4251 const struct intel_plane_state *plane_state)
4253 struct drm_i915_private *dev_priv =
4254 to_i915(plane_state->uapi.plane->dev);
4255 const struct drm_framebuffer *fb = plane_state->hw.fb;
4256 unsigned int rotation = plane_state->hw.rotation;
4259 dspcntr = DISPLAY_PLANE_ENABLE;
4261 if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
4262 IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
4263 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
4265 switch (fb->format->format) {
4267 dspcntr |= DISPPLANE_8BPP;
4269 case DRM_FORMAT_XRGB1555:
4270 dspcntr |= DISPPLANE_BGRX555;
4272 case DRM_FORMAT_ARGB1555:
4273 dspcntr |= DISPPLANE_BGRA555;
4275 case DRM_FORMAT_RGB565:
4276 dspcntr |= DISPPLANE_BGRX565;
4278 case DRM_FORMAT_XRGB8888:
4279 dspcntr |= DISPPLANE_BGRX888;
4281 case DRM_FORMAT_XBGR8888:
4282 dspcntr |= DISPPLANE_RGBX888;
4284 case DRM_FORMAT_ARGB8888:
4285 dspcntr |= DISPPLANE_BGRA888;
4287 case DRM_FORMAT_ABGR8888:
4288 dspcntr |= DISPPLANE_RGBA888;
4290 case DRM_FORMAT_XRGB2101010:
4291 dspcntr |= DISPPLANE_BGRX101010;
4293 case DRM_FORMAT_XBGR2101010:
4294 dspcntr |= DISPPLANE_RGBX101010;
4296 case DRM_FORMAT_ARGB2101010:
4297 dspcntr |= DISPPLANE_BGRA101010;
4299 case DRM_FORMAT_ABGR2101010:
4300 dspcntr |= DISPPLANE_RGBA101010;
4302 case DRM_FORMAT_XBGR16161616F:
4303 dspcntr |= DISPPLANE_RGBX161616;
4306 MISSING_CASE(fb->format->format);
4310 if (INTEL_GEN(dev_priv) >= 4 &&
4311 fb->modifier == I915_FORMAT_MOD_X_TILED)
4312 dspcntr |= DISPPLANE_TILED;
4314 if (rotation & DRM_MODE_ROTATE_180)
4315 dspcntr |= DISPPLANE_ROTATE_180;
4317 if (rotation & DRM_MODE_REFLECT_X)
4318 dspcntr |= DISPPLANE_MIRROR;
4323 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
4325 struct drm_i915_private *dev_priv =
4326 to_i915(plane_state->uapi.plane->dev);
4327 const struct drm_framebuffer *fb = plane_state->hw.fb;
4328 int src_x, src_y, src_w;
4332 ret = intel_plane_compute_gtt(plane_state);
4336 if (!plane_state->uapi.visible)
4339 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
4340 src_x = plane_state->uapi.src.x1 >> 16;
4341 src_y = plane_state->uapi.src.y1 >> 16;
4343 /* Undocumented hardware limit on i965/g4x/vlv/chv */
4344 if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048)
4347 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
4349 if (INTEL_GEN(dev_priv) >= 4)
4350 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
4356 * Put the final coordinates back so that the src
4357 * coordinate checks will see the right values.
4359 drm_rect_translate_to(&plane_state->uapi.src,
4360 src_x << 16, src_y << 16);
4362 /* HSW/BDW do this automagically in hardware */
4363 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
4364 unsigned int rotation = plane_state->hw.rotation;
4365 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
4366 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
4368 if (rotation & DRM_MODE_ROTATE_180) {
4371 } else if (rotation & DRM_MODE_REFLECT_X) {
4376 plane_state->color_plane[0].offset = offset;
4377 plane_state->color_plane[0].x = src_x;
4378 plane_state->color_plane[0].y = src_y;
4383 static bool i9xx_plane_has_windowing(struct intel_plane *plane)
4385 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4386 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4388 if (IS_CHERRYVIEW(dev_priv))
4389 return i9xx_plane == PLANE_B;
4390 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
4392 else if (IS_GEN(dev_priv, 4))
4393 return i9xx_plane == PLANE_C;
4395 return i9xx_plane == PLANE_B ||
4396 i9xx_plane == PLANE_C;
4400 i9xx_plane_check(struct intel_crtc_state *crtc_state,
4401 struct intel_plane_state *plane_state)
4403 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
4406 ret = chv_plane_check_rotation(plane_state);
4410 ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
4412 DRM_PLANE_HELPER_NO_SCALING,
4413 DRM_PLANE_HELPER_NO_SCALING,
4414 i9xx_plane_has_windowing(plane),
4419 ret = i9xx_check_plane_surface(plane_state);
4423 if (!plane_state->uapi.visible)
4426 ret = intel_plane_check_src_coordinates(plane_state);
4430 plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
4435 static void i9xx_update_plane(struct intel_plane *plane,
4436 const struct intel_crtc_state *crtc_state,
4437 const struct intel_plane_state *plane_state)
4439 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4440 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4442 int x = plane_state->color_plane[0].x;
4443 int y = plane_state->color_plane[0].y;
4444 int crtc_x = plane_state->uapi.dst.x1;
4445 int crtc_y = plane_state->uapi.dst.y1;
4446 int crtc_w = drm_rect_width(&plane_state->uapi.dst);
4447 int crtc_h = drm_rect_height(&plane_state->uapi.dst);
4448 unsigned long irqflags;
4452 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
4454 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
4456 if (INTEL_GEN(dev_priv) >= 4)
4457 dspaddr_offset = plane_state->color_plane[0].offset;
4459 dspaddr_offset = linear_offset;
4461 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4463 intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane),
4464 plane_state->color_plane[0].stride);
4466 if (INTEL_GEN(dev_priv) < 4) {
4468 * PLANE_A doesn't actually have a full window
4469 * generator but let's assume we still need to
4470 * program whatever is there.
4472 intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),
4473 (crtc_y << 16) | crtc_x);
4474 intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
4475 ((crtc_h - 1) << 16) | (crtc_w - 1));
4476 } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
4477 intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane),
4478 (crtc_y << 16) | crtc_x);
4479 intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane),
4480 ((crtc_h - 1) << 16) | (crtc_w - 1));
4481 intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0);
4484 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
4485 intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane),
4487 } else if (INTEL_GEN(dev_priv) >= 4) {
4488 intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane),
4490 intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane),
4495 * The control register self-arms if the plane was previously
4496 * disabled. Try to make the plane enable atomic by writing
4497 * the control register just before the surface register.
4499 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
4500 if (INTEL_GEN(dev_priv) >= 4)
4501 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
4502 intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
4504 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
4505 intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
4507 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4510 static void i9xx_disable_plane(struct intel_plane *plane,
4511 const struct intel_crtc_state *crtc_state)
4513 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4514 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4515 unsigned long irqflags;
4519 * DSPCNTR pipe gamma enable on g4x+ and pipe csc
4520 * enable on ilk+ affect the pipe bottom color as
4521 * well, so we must configure them even if the plane
4524 * On pre-g4x there is no way to gamma correct the
4525 * pipe bottom color but we'll keep on doing this
4526 * anyway so that the crtc state readout works correctly.
4528 dspcntr = i9xx_plane_ctl_crtc(crtc_state);
4530 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4532 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
4533 if (INTEL_GEN(dev_priv) >= 4)
4534 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0);
4536 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0);
4538 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4541 static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
4544 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4545 enum intel_display_power_domain power_domain;
4546 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4547 intel_wakeref_t wakeref;
4552 * Not 100% correct for planes that can move between pipes,
4553 * but that's only the case for gen2-4 which don't have any
4554 * display power wells.
4556 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
4557 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
4561 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
4563 ret = val & DISPLAY_PLANE_ENABLE;
4565 if (INTEL_GEN(dev_priv) >= 5)
4566 *pipe = plane->pipe;
4568 *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
4569 DISPPLANE_SEL_PIPE_SHIFT;
4571 intel_display_power_put(dev_priv, power_domain, wakeref);
4576 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
4578 struct drm_device *dev = intel_crtc->base.dev;
4579 struct drm_i915_private *dev_priv = to_i915(dev);
4580 unsigned long irqflags;
4582 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4584 intel_de_write_fw(dev_priv, SKL_PS_CTRL(intel_crtc->pipe, id), 0);
4585 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
4586 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
4588 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4592 * This function detaches (aka. unbinds) unused scalers in hardware
4594 static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
4596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
4597 const struct intel_crtc_scaler_state *scaler_state =
4598 &crtc_state->scaler_state;
4601 /* loop through and disable scalers that aren't in use */
4602 for (i = 0; i < intel_crtc->num_scalers; i++) {
4603 if (!scaler_state->scalers[i].in_use)
4604 skl_detach_scaler(intel_crtc, i);
4608 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
4609 int color_plane, unsigned int rotation)
4612 * The stride is either expressed as a multiple of 64 bytes chunks for
4613 * linear buffers or in number of tiles for tiled buffers.
4615 if (is_surface_linear(fb, color_plane))
4617 else if (drm_rotation_90_or_270(rotation))
4618 return intel_tile_height(fb, color_plane);
4620 return intel_tile_width_bytes(fb, color_plane);
4623 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
4626 const struct drm_framebuffer *fb = plane_state->hw.fb;
4627 unsigned int rotation = plane_state->hw.rotation;
4628 u32 stride = plane_state->color_plane[color_plane].stride;
4630 if (color_plane >= fb->format->num_planes)
4633 return stride / skl_plane_stride_mult(fb, color_plane, rotation);
4636 static u32 skl_plane_ctl_format(u32 pixel_format)
4638 switch (pixel_format) {
4640 return PLANE_CTL_FORMAT_INDEXED;
4641 case DRM_FORMAT_RGB565:
4642 return PLANE_CTL_FORMAT_RGB_565;
4643 case DRM_FORMAT_XBGR8888:
4644 case DRM_FORMAT_ABGR8888:
4645 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
4646 case DRM_FORMAT_XRGB8888:
4647 case DRM_FORMAT_ARGB8888:
4648 return PLANE_CTL_FORMAT_XRGB_8888;
4649 case DRM_FORMAT_XBGR2101010:
4650 case DRM_FORMAT_ABGR2101010:
4651 return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX;
4652 case DRM_FORMAT_XRGB2101010:
4653 case DRM_FORMAT_ARGB2101010:
4654 return PLANE_CTL_FORMAT_XRGB_2101010;
4655 case DRM_FORMAT_XBGR16161616F:
4656 case DRM_FORMAT_ABGR16161616F:
4657 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
4658 case DRM_FORMAT_XRGB16161616F:
4659 case DRM_FORMAT_ARGB16161616F:
4660 return PLANE_CTL_FORMAT_XRGB_16161616F;
4661 case DRM_FORMAT_XYUV8888:
4662 return PLANE_CTL_FORMAT_XYUV;
4663 case DRM_FORMAT_YUYV:
4664 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
4665 case DRM_FORMAT_YVYU:
4666 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
4667 case DRM_FORMAT_UYVY:
4668 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
4669 case DRM_FORMAT_VYUY:
4670 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
4671 case DRM_FORMAT_NV12:
4672 return PLANE_CTL_FORMAT_NV12;
4673 case DRM_FORMAT_P010:
4674 return PLANE_CTL_FORMAT_P010;
4675 case DRM_FORMAT_P012:
4676 return PLANE_CTL_FORMAT_P012;
4677 case DRM_FORMAT_P016:
4678 return PLANE_CTL_FORMAT_P016;
4679 case DRM_FORMAT_Y210:
4680 return PLANE_CTL_FORMAT_Y210;
4681 case DRM_FORMAT_Y212:
4682 return PLANE_CTL_FORMAT_Y212;
4683 case DRM_FORMAT_Y216:
4684 return PLANE_CTL_FORMAT_Y216;
4685 case DRM_FORMAT_XVYU2101010:
4686 return PLANE_CTL_FORMAT_Y410;
4687 case DRM_FORMAT_XVYU12_16161616:
4688 return PLANE_CTL_FORMAT_Y412;
4689 case DRM_FORMAT_XVYU16161616:
4690 return PLANE_CTL_FORMAT_Y416;
4692 MISSING_CASE(pixel_format);
4698 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
4700 if (!plane_state->hw.fb->format->has_alpha)
4701 return PLANE_CTL_ALPHA_DISABLE;
4703 switch (plane_state->hw.pixel_blend_mode) {
4704 case DRM_MODE_BLEND_PIXEL_NONE:
4705 return PLANE_CTL_ALPHA_DISABLE;
4706 case DRM_MODE_BLEND_PREMULTI:
4707 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
4708 case DRM_MODE_BLEND_COVERAGE:
4709 return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
4711 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4712 return PLANE_CTL_ALPHA_DISABLE;
4716 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
4718 if (!plane_state->hw.fb->format->has_alpha)
4719 return PLANE_COLOR_ALPHA_DISABLE;
4721 switch (plane_state->hw.pixel_blend_mode) {
4722 case DRM_MODE_BLEND_PIXEL_NONE:
4723 return PLANE_COLOR_ALPHA_DISABLE;
4724 case DRM_MODE_BLEND_PREMULTI:
4725 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
4726 case DRM_MODE_BLEND_COVERAGE:
4727 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
4729 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4730 return PLANE_COLOR_ALPHA_DISABLE;
4734 static u32 skl_plane_ctl_tiling(u64 fb_modifier)
4736 switch (fb_modifier) {
4737 case DRM_FORMAT_MOD_LINEAR:
4739 case I915_FORMAT_MOD_X_TILED:
4740 return PLANE_CTL_TILED_X;
4741 case I915_FORMAT_MOD_Y_TILED:
4742 return PLANE_CTL_TILED_Y;
4743 case I915_FORMAT_MOD_Y_TILED_CCS:
4744 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4745 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
4746 return PLANE_CTL_TILED_Y |
4747 PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
4748 PLANE_CTL_CLEAR_COLOR_DISABLE;
4749 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
4750 return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
4751 case I915_FORMAT_MOD_Yf_TILED:
4752 return PLANE_CTL_TILED_YF;
4753 case I915_FORMAT_MOD_Yf_TILED_CCS:
4754 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4756 MISSING_CASE(fb_modifier);
4762 static u32 skl_plane_ctl_rotate(unsigned int rotate)
4765 case DRM_MODE_ROTATE_0:
4768 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
4769 * while i915 HW rotation is clockwise, thats why this swapping.
4771 case DRM_MODE_ROTATE_90:
4772 return PLANE_CTL_ROTATE_270;
4773 case DRM_MODE_ROTATE_180:
4774 return PLANE_CTL_ROTATE_180;
4775 case DRM_MODE_ROTATE_270:
4776 return PLANE_CTL_ROTATE_90;
4778 MISSING_CASE(rotate);
4784 static u32 cnl_plane_ctl_flip(unsigned int reflect)
4789 case DRM_MODE_REFLECT_X:
4790 return PLANE_CTL_FLIP_HORIZONTAL;
4791 case DRM_MODE_REFLECT_Y:
4793 MISSING_CASE(reflect);
4799 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
4801 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4804 if (crtc_state->uapi.async_flip)
4805 plane_ctl |= PLANE_CTL_ASYNC_FLIP;
4807 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4810 if (crtc_state->gamma_enable)
4811 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
4813 if (crtc_state->csc_enable)
4814 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
4819 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
4820 const struct intel_plane_state *plane_state)
4822 struct drm_i915_private *dev_priv =
4823 to_i915(plane_state->uapi.plane->dev);
4824 const struct drm_framebuffer *fb = plane_state->hw.fb;
4825 unsigned int rotation = plane_state->hw.rotation;
4826 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
4829 plane_ctl = PLANE_CTL_ENABLE;
4831 if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
4832 plane_ctl |= skl_plane_ctl_alpha(plane_state);
4833 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
4835 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
4836 plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
4838 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4839 plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
4842 plane_ctl |= skl_plane_ctl_format(fb->format->format);
4843 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
4844 plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
4846 if (INTEL_GEN(dev_priv) >= 10)
4847 plane_ctl |= cnl_plane_ctl_flip(rotation &
4848 DRM_MODE_REFLECT_MASK);
4850 if (key->flags & I915_SET_COLORKEY_DESTINATION)
4851 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
4852 else if (key->flags & I915_SET_COLORKEY_SOURCE)
4853 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
4858 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
4860 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4861 u32 plane_color_ctl = 0;
4863 if (INTEL_GEN(dev_priv) >= 11)
4864 return plane_color_ctl;
4866 if (crtc_state->gamma_enable)
4867 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
4869 if (crtc_state->csc_enable)
4870 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
4872 return plane_color_ctl;
4875 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
4876 const struct intel_plane_state *plane_state)
4878 struct drm_i915_private *dev_priv =
4879 to_i915(plane_state->uapi.plane->dev);
4880 const struct drm_framebuffer *fb = plane_state->hw.fb;
4881 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
4882 u32 plane_color_ctl = 0;
4884 plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
4885 plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
4887 if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
4888 switch (plane_state->hw.color_encoding) {
4889 case DRM_COLOR_YCBCR_BT709:
4890 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
4892 case DRM_COLOR_YCBCR_BT2020:
4894 PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020;
4898 PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601;
4900 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4901 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
4902 } else if (fb->format->is_yuv) {
4903 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
4906 return plane_color_ctl;
4910 __intel_display_resume(struct drm_device *dev,
4911 struct drm_atomic_state *state,
4912 struct drm_modeset_acquire_ctx *ctx)
4914 struct drm_crtc_state *crtc_state;
4915 struct drm_crtc *crtc;
4918 intel_modeset_setup_hw_state(dev, ctx);
4919 intel_vga_redisable(to_i915(dev));
4925 * We've duplicated the state, pointers to the old state are invalid.
4927 * Don't attempt to use the old state until we commit the duplicated state.
4929 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
4931 * Force recalculation even if we restore
4932 * current state. With fast modeset this may not result
4933 * in a modeset when the state is compatible.
4935 crtc_state->mode_changed = true;
4938 /* ignore any reset values/BIOS leftovers in the WM registers */
4939 if (!HAS_GMCH(to_i915(dev)))
4940 to_intel_atomic_state(state)->skip_intermediate_wm = true;
4942 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
4944 drm_WARN_ON(dev, ret == -EDEADLK);
4948 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
4950 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
4951 intel_has_gpu_reset(&dev_priv->gt));
4954 void intel_prepare_reset(struct drm_i915_private *dev_priv)
4956 struct drm_device *dev = &dev_priv->drm;
4957 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4958 struct drm_atomic_state *state;
4961 /* reset doesn't touch the display */
4962 if (!dev_priv->params.force_reset_modeset_test &&
4963 !gpu_reset_clobbers_display(dev_priv))
4966 /* We have a modeset vs reset deadlock, defensively unbreak it. */
4967 set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4968 smp_mb__after_atomic();
4969 wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET);
4971 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
4972 drm_dbg_kms(&dev_priv->drm,
4973 "Modeset potentially stuck, unbreaking through wedging\n");
4974 intel_gt_set_wedged(&dev_priv->gt);
4978 * Need mode_config.mutex so that we don't
4979 * trample ongoing ->detect() and whatnot.
4981 mutex_lock(&dev->mode_config.mutex);
4982 drm_modeset_acquire_init(ctx, 0);
4984 ret = drm_modeset_lock_all_ctx(dev, ctx);
4985 if (ret != -EDEADLK)
4988 drm_modeset_backoff(ctx);
4991 * Disabling the crtcs gracefully seems nicer. Also the
4992 * g33 docs say we should at least disable all the planes.
4994 state = drm_atomic_helper_duplicate_state(dev, ctx);
4995 if (IS_ERR(state)) {
4996 ret = PTR_ERR(state);
4997 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n",
5002 ret = drm_atomic_helper_disable_all(dev, ctx);
5004 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
5006 drm_atomic_state_put(state);
5010 dev_priv->modeset_restore_state = state;
5011 state->acquire_ctx = ctx;
5014 void intel_finish_reset(struct drm_i915_private *dev_priv)
5016 struct drm_device *dev = &dev_priv->drm;
5017 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
5018 struct drm_atomic_state *state;
5021 /* reset doesn't touch the display */
5022 if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
5025 state = fetch_and_zero(&dev_priv->modeset_restore_state);
5029 /* reset doesn't touch the display */
5030 if (!gpu_reset_clobbers_display(dev_priv)) {
5031 /* for testing only restore the display */
5032 ret = __intel_display_resume(dev, state, ctx);
5034 drm_err(&dev_priv->drm,
5035 "Restoring old state failed with %i\n", ret);
5038 * The display has been reset as well,
5039 * so need a full re-initialization.
5041 intel_pps_unlock_regs_wa(dev_priv);
5042 intel_modeset_init_hw(dev_priv);
5043 intel_init_clock_gating(dev_priv);
5044 intel_hpd_init(dev_priv);
5046 ret = __intel_display_resume(dev, state, ctx);
5048 drm_err(&dev_priv->drm,
5049 "Restoring old state failed with %i\n", ret);
5051 intel_hpd_poll_disable(dev_priv);
5054 drm_atomic_state_put(state);
5056 drm_modeset_drop_locks(ctx);
5057 drm_modeset_acquire_fini(ctx);
5058 mutex_unlock(&dev->mode_config.mutex);
5060 clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
5063 static void icl_set_pipe_chicken(struct intel_crtc *crtc)
5065 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5066 enum pipe pipe = crtc->pipe;
5069 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe));
5072 * Display WA #1153: icl
5073 * enable hardware to bypass the alpha math
5074 * and rounding for per-pixel values 00 and 0xff
5076 tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
5078 * Display WA # 1605353570: icl
5079 * Set the pixel rounding bit to 1 for allowing
5080 * passthrough of Frame buffer pixels unmodified
5083 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
5084 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
5087 static void intel_fdi_normal_train(struct intel_crtc *crtc)
5089 struct drm_device *dev = crtc->base.dev;
5090 struct drm_i915_private *dev_priv = to_i915(dev);
5091 enum pipe pipe = crtc->pipe;
5095 /* enable normal train */
5096 reg = FDI_TX_CTL(pipe);
5097 temp = intel_de_read(dev_priv, reg);
5098 if (IS_IVYBRIDGE(dev_priv)) {
5099 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
5100 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
5102 temp &= ~FDI_LINK_TRAIN_NONE;
5103 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
5105 intel_de_write(dev_priv, reg, temp);
5107 reg = FDI_RX_CTL(pipe);
5108 temp = intel_de_read(dev_priv, reg);
5109 if (HAS_PCH_CPT(dev_priv)) {
5110 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5111 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
5113 temp &= ~FDI_LINK_TRAIN_NONE;
5114 temp |= FDI_LINK_TRAIN_NONE;
5116 intel_de_write(dev_priv, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
5118 /* wait one idle pattern time */
5119 intel_de_posting_read(dev_priv, reg);
5122 /* IVB wants error correction enabled */
5123 if (IS_IVYBRIDGE(dev_priv))
5124 intel_de_write(dev_priv, reg,
5125 intel_de_read(dev_priv, reg) | FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE);
5128 /* The FDI link training functions for ILK/Ibexpeak. */
5129 static void ilk_fdi_link_train(struct intel_crtc *crtc,
5130 const struct intel_crtc_state *crtc_state)
5132 struct drm_device *dev = crtc->base.dev;
5133 struct drm_i915_private *dev_priv = to_i915(dev);
5134 enum pipe pipe = crtc->pipe;
5138 /* FDI needs bits from pipe first */
5139 assert_pipe_enabled(dev_priv, crtc_state->cpu_transcoder);
5141 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5143 reg = FDI_RX_IMR(pipe);
5144 temp = intel_de_read(dev_priv, reg);
5145 temp &= ~FDI_RX_SYMBOL_LOCK;
5146 temp &= ~FDI_RX_BIT_LOCK;
5147 intel_de_write(dev_priv, reg, temp);
5148 intel_de_read(dev_priv, reg);
5151 /* enable CPU FDI TX and PCH FDI RX */
5152 reg = FDI_TX_CTL(pipe);
5153 temp = intel_de_read(dev_priv, reg);
5154 temp &= ~FDI_DP_PORT_WIDTH_MASK;
5155 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5156 temp &= ~FDI_LINK_TRAIN_NONE;
5157 temp |= FDI_LINK_TRAIN_PATTERN_1;
5158 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
5160 reg = FDI_RX_CTL(pipe);
5161 temp = intel_de_read(dev_priv, reg);
5162 temp &= ~FDI_LINK_TRAIN_NONE;
5163 temp |= FDI_LINK_TRAIN_PATTERN_1;
5164 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
5166 intel_de_posting_read(dev_priv, reg);
5169 /* Ironlake workaround, enable clock pointer after FDI enable*/
5170 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
5171 FDI_RX_PHASE_SYNC_POINTER_OVR);
5172 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
5173 FDI_RX_PHASE_SYNC_POINTER_OVR | FDI_RX_PHASE_SYNC_POINTER_EN);
5175 reg = FDI_RX_IIR(pipe);
5176 for (tries = 0; tries < 5; tries++) {
5177 temp = intel_de_read(dev_priv, reg);
5178 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5180 if ((temp & FDI_RX_BIT_LOCK)) {
5181 drm_dbg_kms(&dev_priv->drm, "FDI train 1 done.\n");
5182 intel_de_write(dev_priv, reg, temp | FDI_RX_BIT_LOCK);
5187 drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
5190 reg = FDI_TX_CTL(pipe);
5191 temp = intel_de_read(dev_priv, reg);
5192 temp &= ~FDI_LINK_TRAIN_NONE;
5193 temp |= FDI_LINK_TRAIN_PATTERN_2;
5194 intel_de_write(dev_priv, reg, temp);
5196 reg = FDI_RX_CTL(pipe);
5197 temp = intel_de_read(dev_priv, reg);
5198 temp &= ~FDI_LINK_TRAIN_NONE;
5199 temp |= FDI_LINK_TRAIN_PATTERN_2;
5200 intel_de_write(dev_priv, reg, temp);
5202 intel_de_posting_read(dev_priv, reg);
5205 reg = FDI_RX_IIR(pipe);
5206 for (tries = 0; tries < 5; tries++) {
5207 temp = intel_de_read(dev_priv, reg);
5208 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5210 if (temp & FDI_RX_SYMBOL_LOCK) {
5211 intel_de_write(dev_priv, reg,
5212 temp | FDI_RX_SYMBOL_LOCK);
5213 drm_dbg_kms(&dev_priv->drm, "FDI train 2 done.\n");
5218 drm_err(&dev_priv->drm, "FDI train 2 fail!\n");
5220 drm_dbg_kms(&dev_priv->drm, "FDI train done\n");
5224 static const int snb_b_fdi_train_param[] = {
5225 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
5226 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
5227 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
5228 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
5231 /* The FDI link training functions for SNB/Cougarpoint. */
5232 static void gen6_fdi_link_train(struct intel_crtc *crtc,
5233 const struct intel_crtc_state *crtc_state)
5235 struct drm_device *dev = crtc->base.dev;
5236 struct drm_i915_private *dev_priv = to_i915(dev);
5237 enum pipe pipe = crtc->pipe;
5241 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5243 reg = FDI_RX_IMR(pipe);
5244 temp = intel_de_read(dev_priv, reg);
5245 temp &= ~FDI_RX_SYMBOL_LOCK;
5246 temp &= ~FDI_RX_BIT_LOCK;
5247 intel_de_write(dev_priv, reg, temp);
5249 intel_de_posting_read(dev_priv, reg);
5252 /* enable CPU FDI TX and PCH FDI RX */
5253 reg = FDI_TX_CTL(pipe);
5254 temp = intel_de_read(dev_priv, reg);
5255 temp &= ~FDI_DP_PORT_WIDTH_MASK;
5256 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5257 temp &= ~FDI_LINK_TRAIN_NONE;
5258 temp |= FDI_LINK_TRAIN_PATTERN_1;
5259 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5261 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5262 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
5264 intel_de_write(dev_priv, FDI_RX_MISC(pipe),
5265 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
5267 reg = FDI_RX_CTL(pipe);
5268 temp = intel_de_read(dev_priv, reg);
5269 if (HAS_PCH_CPT(dev_priv)) {
5270 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5271 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5273 temp &= ~FDI_LINK_TRAIN_NONE;
5274 temp |= FDI_LINK_TRAIN_PATTERN_1;
5276 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
5278 intel_de_posting_read(dev_priv, reg);
5281 for (i = 0; i < 4; i++) {
5282 reg = FDI_TX_CTL(pipe);
5283 temp = intel_de_read(dev_priv, reg);
5284 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5285 temp |= snb_b_fdi_train_param[i];
5286 intel_de_write(dev_priv, reg, temp);
5288 intel_de_posting_read(dev_priv, reg);
5291 for (retry = 0; retry < 5; retry++) {
5292 reg = FDI_RX_IIR(pipe);
5293 temp = intel_de_read(dev_priv, reg);
5294 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5295 if (temp & FDI_RX_BIT_LOCK) {
5296 intel_de_write(dev_priv, reg,
5297 temp | FDI_RX_BIT_LOCK);
5298 drm_dbg_kms(&dev_priv->drm,
5299 "FDI train 1 done.\n");
5308 drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
5311 reg = FDI_TX_CTL(pipe);
5312 temp = intel_de_read(dev_priv, reg);
5313 temp &= ~FDI_LINK_TRAIN_NONE;
5314 temp |= FDI_LINK_TRAIN_PATTERN_2;
5315 if (IS_GEN(dev_priv, 6)) {
5316 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5318 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5320 intel_de_write(dev_priv, reg, temp);
5322 reg = FDI_RX_CTL(pipe);
5323 temp = intel_de_read(dev_priv, reg);
5324 if (HAS_PCH_CPT(dev_priv)) {
5325 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5326 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
5328 temp &= ~FDI_LINK_TRAIN_NONE;
5329 temp |= FDI_LINK_TRAIN_PATTERN_2;
5331 intel_de_write(dev_priv, reg, temp);
5333 intel_de_posting_read(dev_priv, reg);
5336 for (i = 0; i < 4; i++) {
5337 reg = FDI_TX_CTL(pipe);
5338 temp = intel_de_read(dev_priv, reg);
5339 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5340 temp |= snb_b_fdi_train_param[i];
5341 intel_de_write(dev_priv, reg, temp);
5343 intel_de_posting_read(dev_priv, reg);
5346 for (retry = 0; retry < 5; retry++) {
5347 reg = FDI_RX_IIR(pipe);
5348 temp = intel_de_read(dev_priv, reg);
5349 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5350 if (temp & FDI_RX_SYMBOL_LOCK) {
5351 intel_de_write(dev_priv, reg,
5352 temp | FDI_RX_SYMBOL_LOCK);
5353 drm_dbg_kms(&dev_priv->drm,
5354 "FDI train 2 done.\n");
5363 drm_err(&dev_priv->drm, "FDI train 2 fail!\n");
5365 drm_dbg_kms(&dev_priv->drm, "FDI train done.\n");
5368 /* Manual link training for Ivy Bridge A0 parts */
5369 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
5370 const struct intel_crtc_state *crtc_state)
5372 struct drm_device *dev = crtc->base.dev;
5373 struct drm_i915_private *dev_priv = to_i915(dev);
5374 enum pipe pipe = crtc->pipe;
5378 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5380 reg = FDI_RX_IMR(pipe);
5381 temp = intel_de_read(dev_priv, reg);
5382 temp &= ~FDI_RX_SYMBOL_LOCK;
5383 temp &= ~FDI_RX_BIT_LOCK;
5384 intel_de_write(dev_priv, reg, temp);
5386 intel_de_posting_read(dev_priv, reg);
5389 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR before link train 0x%x\n",
5390 intel_de_read(dev_priv, FDI_RX_IIR(pipe)));
5392 /* Try each vswing and preemphasis setting twice before moving on */
5393 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
5394 /* disable first in case we need to retry */
5395 reg = FDI_TX_CTL(pipe);
5396 temp = intel_de_read(dev_priv, reg);
5397 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
5398 temp &= ~FDI_TX_ENABLE;
5399 intel_de_write(dev_priv, reg, temp);
5401 reg = FDI_RX_CTL(pipe);
5402 temp = intel_de_read(dev_priv, reg);
5403 temp &= ~FDI_LINK_TRAIN_AUTO;
5404 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5405 temp &= ~FDI_RX_ENABLE;
5406 intel_de_write(dev_priv, reg, temp);
5408 /* enable CPU FDI TX and PCH FDI RX */
5409 reg = FDI_TX_CTL(pipe);
5410 temp = intel_de_read(dev_priv, reg);
5411 temp &= ~FDI_DP_PORT_WIDTH_MASK;
5412 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5413 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
5414 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5415 temp |= snb_b_fdi_train_param[j/2];
5416 temp |= FDI_COMPOSITE_SYNC;
5417 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
5419 intel_de_write(dev_priv, FDI_RX_MISC(pipe),
5420 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
5422 reg = FDI_RX_CTL(pipe);
5423 temp = intel_de_read(dev_priv, reg);
5424 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5425 temp |= FDI_COMPOSITE_SYNC;
5426 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
5428 intel_de_posting_read(dev_priv, reg);
5429 udelay(1); /* should be 0.5us */
5431 for (i = 0; i < 4; i++) {
5432 reg = FDI_RX_IIR(pipe);
5433 temp = intel_de_read(dev_priv, reg);
5434 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5436 if (temp & FDI_RX_BIT_LOCK ||
5437 (intel_de_read(dev_priv, reg) & FDI_RX_BIT_LOCK)) {
5438 intel_de_write(dev_priv, reg,
5439 temp | FDI_RX_BIT_LOCK);
5440 drm_dbg_kms(&dev_priv->drm,
5441 "FDI train 1 done, level %i.\n",
5445 udelay(1); /* should be 0.5us */
5448 drm_dbg_kms(&dev_priv->drm,
5449 "FDI train 1 fail on vswing %d\n", j / 2);
5454 reg = FDI_TX_CTL(pipe);
5455 temp = intel_de_read(dev_priv, reg);
5456 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
5457 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
5458 intel_de_write(dev_priv, reg, temp);
5460 reg = FDI_RX_CTL(pipe);
5461 temp = intel_de_read(dev_priv, reg);
5462 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5463 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
5464 intel_de_write(dev_priv, reg, temp);
5466 intel_de_posting_read(dev_priv, reg);
5467 udelay(2); /* should be 1.5us */
5469 for (i = 0; i < 4; i++) {
5470 reg = FDI_RX_IIR(pipe);
5471 temp = intel_de_read(dev_priv, reg);
5472 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5474 if (temp & FDI_RX_SYMBOL_LOCK ||
5475 (intel_de_read(dev_priv, reg) & FDI_RX_SYMBOL_LOCK)) {
5476 intel_de_write(dev_priv, reg,
5477 temp | FDI_RX_SYMBOL_LOCK);
5478 drm_dbg_kms(&dev_priv->drm,
5479 "FDI train 2 done, level %i.\n",
5483 udelay(2); /* should be 1.5us */
5486 drm_dbg_kms(&dev_priv->drm,
5487 "FDI train 2 fail on vswing %d\n", j / 2);
5491 drm_dbg_kms(&dev_priv->drm, "FDI train done.\n");
5494 static void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
5496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
5497 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
5498 enum pipe pipe = intel_crtc->pipe;
5502 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5503 reg = FDI_RX_CTL(pipe);
5504 temp = intel_de_read(dev_priv, reg);
5505 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
5506 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5507 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5508 intel_de_write(dev_priv, reg, temp | FDI_RX_PLL_ENABLE);
5510 intel_de_posting_read(dev_priv, reg);
5513 /* Switch from Rawclk to PCDclk */
5514 temp = intel_de_read(dev_priv, reg);
5515 intel_de_write(dev_priv, reg, temp | FDI_PCDCLK);
5517 intel_de_posting_read(dev_priv, reg);
5520 /* Enable CPU FDI TX PLL, always on for Ironlake */
5521 reg = FDI_TX_CTL(pipe);
5522 temp = intel_de_read(dev_priv, reg);
5523 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5524 intel_de_write(dev_priv, reg, temp | FDI_TX_PLL_ENABLE);
5526 intel_de_posting_read(dev_priv, reg);
5531 static void ilk_fdi_pll_disable(struct intel_crtc *intel_crtc)
5533 struct drm_device *dev = intel_crtc->base.dev;
5534 struct drm_i915_private *dev_priv = to_i915(dev);
5535 enum pipe pipe = intel_crtc->pipe;
5539 /* Switch from PCDclk to Rawclk */
5540 reg = FDI_RX_CTL(pipe);
5541 temp = intel_de_read(dev_priv, reg);
5542 intel_de_write(dev_priv, reg, temp & ~FDI_PCDCLK);
5544 /* Disable CPU FDI TX PLL */
5545 reg = FDI_TX_CTL(pipe);
5546 temp = intel_de_read(dev_priv, reg);
5547 intel_de_write(dev_priv, reg, temp & ~FDI_TX_PLL_ENABLE);
5549 intel_de_posting_read(dev_priv, reg);
5552 reg = FDI_RX_CTL(pipe);
5553 temp = intel_de_read(dev_priv, reg);
5554 intel_de_write(dev_priv, reg, temp & ~FDI_RX_PLL_ENABLE);
5556 /* Wait for the clocks to turn off. */
5557 intel_de_posting_read(dev_priv, reg);
5561 static void ilk_fdi_disable(struct intel_crtc *crtc)
5563 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5564 enum pipe pipe = crtc->pipe;
5568 /* disable CPU FDI tx and PCH FDI rx */
5569 reg = FDI_TX_CTL(pipe);
5570 temp = intel_de_read(dev_priv, reg);
5571 intel_de_write(dev_priv, reg, temp & ~FDI_TX_ENABLE);
5572 intel_de_posting_read(dev_priv, reg);
5574 reg = FDI_RX_CTL(pipe);
5575 temp = intel_de_read(dev_priv, reg);
5576 temp &= ~(0x7 << 16);
5577 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5578 intel_de_write(dev_priv, reg, temp & ~FDI_RX_ENABLE);
5580 intel_de_posting_read(dev_priv, reg);
5583 /* Ironlake workaround, disable clock pointer after downing FDI */
5584 if (HAS_PCH_IBX(dev_priv))
5585 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
5586 FDI_RX_PHASE_SYNC_POINTER_OVR);
5588 /* still set train pattern 1 */
5589 reg = FDI_TX_CTL(pipe);
5590 temp = intel_de_read(dev_priv, reg);
5591 temp &= ~FDI_LINK_TRAIN_NONE;
5592 temp |= FDI_LINK_TRAIN_PATTERN_1;
5593 intel_de_write(dev_priv, reg, temp);
5595 reg = FDI_RX_CTL(pipe);
5596 temp = intel_de_read(dev_priv, reg);
5597 if (HAS_PCH_CPT(dev_priv)) {
5598 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5599 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5601 temp &= ~FDI_LINK_TRAIN_NONE;
5602 temp |= FDI_LINK_TRAIN_PATTERN_1;
5604 /* BPC in FDI rx is consistent with that in PIPECONF */
5605 temp &= ~(0x07 << 16);
5606 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5607 intel_de_write(dev_priv, reg, temp);
5609 intel_de_posting_read(dev_priv, reg);
5613 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
5615 struct drm_crtc *crtc;
5618 drm_for_each_crtc(crtc, &dev_priv->drm) {
5619 struct drm_crtc_commit *commit;
5620 spin_lock(&crtc->commit_lock);
5621 commit = list_first_entry_or_null(&crtc->commit_list,
5622 struct drm_crtc_commit, commit_entry);
5623 cleanup_done = commit ?
5624 try_wait_for_completion(&commit->cleanup_done) : true;
5625 spin_unlock(&crtc->commit_lock);
5630 drm_crtc_wait_one_vblank(crtc);
5638 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
5642 intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_GATE);
5644 mutex_lock(&dev_priv->sb_lock);
5646 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5647 temp |= SBI_SSCCTL_DISABLE;
5648 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5650 mutex_unlock(&dev_priv->sb_lock);
5653 /* Program iCLKIP clock to the desired frequency */
5654 static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
5656 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5657 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5658 int clock = crtc_state->hw.adjusted_mode.crtc_clock;
5659 u32 divsel, phaseinc, auxdiv, phasedir = 0;
5662 lpt_disable_iclkip(dev_priv);
5664 /* The iCLK virtual clock root frequency is in MHz,
5665 * but the adjusted_mode->crtc_clock in in KHz. To get the
5666 * divisors, it is necessary to divide one by another, so we
5667 * convert the virtual clock precision to KHz here for higher
5670 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
5671 u32 iclk_virtual_root_freq = 172800 * 1000;
5672 u32 iclk_pi_range = 64;
5673 u32 desired_divisor;
5675 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5677 divsel = (desired_divisor / iclk_pi_range) - 2;
5678 phaseinc = desired_divisor % iclk_pi_range;
5681 * Near 20MHz is a corner case which is
5682 * out of range for the 7-bit divisor
5688 /* This should not happen with any sane values */
5689 drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
5690 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
5691 drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(phasedir) &
5692 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
5694 drm_dbg_kms(&dev_priv->drm,
5695 "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
5696 clock, auxdiv, divsel, phasedir, phaseinc);
5698 mutex_lock(&dev_priv->sb_lock);
5700 /* Program SSCDIVINTPHASE6 */
5701 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5702 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
5703 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
5704 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
5705 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
5706 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
5707 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
5708 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
5710 /* Program SSCAUXDIV */
5711 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5712 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
5713 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
5714 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
5716 /* Enable modulator and associated divider */
5717 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5718 temp &= ~SBI_SSCCTL_DISABLE;
5719 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5721 mutex_unlock(&dev_priv->sb_lock);
5723 /* Wait for initialization time */
5726 intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_UNGATE);
5729 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
5731 u32 divsel, phaseinc, auxdiv;
5732 u32 iclk_virtual_root_freq = 172800 * 1000;
5733 u32 iclk_pi_range = 64;
5734 u32 desired_divisor;
5737 if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
5740 mutex_lock(&dev_priv->sb_lock);
5742 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5743 if (temp & SBI_SSCCTL_DISABLE) {
5744 mutex_unlock(&dev_priv->sb_lock);
5748 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5749 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
5750 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
5751 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
5752 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
5754 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5755 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
5756 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
5758 mutex_unlock(&dev_priv->sb_lock);
5760 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
5762 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5763 desired_divisor << auxdiv);
5766 static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
5767 enum pipe pch_transcoder)
5769 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5770 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5771 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5773 intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
5774 intel_de_read(dev_priv, HTOTAL(cpu_transcoder)));
5775 intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
5776 intel_de_read(dev_priv, HBLANK(cpu_transcoder)));
5777 intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
5778 intel_de_read(dev_priv, HSYNC(cpu_transcoder)));
5780 intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
5781 intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
5782 intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
5783 intel_de_read(dev_priv, VBLANK(cpu_transcoder)));
5784 intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
5785 intel_de_read(dev_priv, VSYNC(cpu_transcoder)));
5786 intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
5787 intel_de_read(dev_priv, VSYNCSHIFT(cpu_transcoder)));
5790 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
5794 temp = intel_de_read(dev_priv, SOUTH_CHICKEN1);
5795 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
5798 drm_WARN_ON(&dev_priv->drm,
5799 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) &
5801 drm_WARN_ON(&dev_priv->drm,
5802 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) &
5805 temp &= ~FDI_BC_BIFURCATION_SELECT;
5807 temp |= FDI_BC_BIFURCATION_SELECT;
5809 drm_dbg_kms(&dev_priv->drm, "%sabling fdi C rx\n",
5810 enable ? "en" : "dis");
5811 intel_de_write(dev_priv, SOUTH_CHICKEN1, temp);
5812 intel_de_posting_read(dev_priv, SOUTH_CHICKEN1);
5815 static void ivb_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
5817 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5818 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5820 switch (crtc->pipe) {
5824 if (crtc_state->fdi_lanes > 2)
5825 cpt_set_fdi_bc_bifurcation(dev_priv, false);
5827 cpt_set_fdi_bc_bifurcation(dev_priv, true);
5831 cpt_set_fdi_bc_bifurcation(dev_priv, true);
5840 * Finds the encoder associated with the given CRTC. This can only be
5841 * used when we know that the CRTC isn't feeding multiple encoders!
5843 static struct intel_encoder *
5844 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
5845 const struct intel_crtc_state *crtc_state)
5847 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5848 const struct drm_connector_state *connector_state;
5849 const struct drm_connector *connector;
5850 struct intel_encoder *encoder = NULL;
5851 int num_encoders = 0;
5854 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
5855 if (connector_state->crtc != &crtc->base)
5858 encoder = to_intel_encoder(connector_state->best_encoder);
5862 drm_WARN(encoder->base.dev, num_encoders != 1,
5863 "%d encoders for pipe %c\n",
5864 num_encoders, pipe_name(crtc->pipe));
5870 * Enable PCH resources required for PCH ports:
5872 * - FDI training & RX/TX
5873 * - update transcoder timings
5874 * - DP transcoding bits
5877 static void ilk_pch_enable(const struct intel_atomic_state *state,
5878 const struct intel_crtc_state *crtc_state)
5880 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5881 struct drm_device *dev = crtc->base.dev;
5882 struct drm_i915_private *dev_priv = to_i915(dev);
5883 enum pipe pipe = crtc->pipe;
5886 assert_pch_transcoder_disabled(dev_priv, pipe);
5888 if (IS_IVYBRIDGE(dev_priv))
5889 ivb_update_fdi_bc_bifurcation(crtc_state);
5891 /* Write the TU size bits before fdi link training, so that error
5892 * detection works. */
5893 intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
5894 intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
5896 /* For PCH output, training FDI link */
5897 dev_priv->display.fdi_link_train(crtc, crtc_state);
5899 /* We need to program the right clock selection before writing the pixel
5900 * mutliplier into the DPLL. */
5901 if (HAS_PCH_CPT(dev_priv)) {
5904 temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
5905 temp |= TRANS_DPLL_ENABLE(pipe);
5906 sel = TRANS_DPLLB_SEL(pipe);
5907 if (crtc_state->shared_dpll ==
5908 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
5912 intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
5915 /* XXX: pch pll's can be enabled any time before we enable the PCH
5916 * transcoder, and we actually should do this to not upset any PCH
5917 * transcoder that already use the clock when we share it.
5919 * Note that enable_shared_dpll tries to do the right thing, but
5920 * get_shared_dpll unconditionally resets the pll - we need that to have
5921 * the right LVDS enable sequence. */
5922 intel_enable_shared_dpll(crtc_state);
5924 /* set transcoder timing, panel must allow it */
5925 assert_panel_unlocked(dev_priv, pipe);
5926 ilk_pch_transcoder_set_timings(crtc_state, pipe);
5928 intel_fdi_normal_train(crtc);
5930 /* For PCH DP, enable TRANS_DP_CTL */
5931 if (HAS_PCH_CPT(dev_priv) &&
5932 intel_crtc_has_dp_encoder(crtc_state)) {
5933 const struct drm_display_mode *adjusted_mode =
5934 &crtc_state->hw.adjusted_mode;
5935 u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5936 i915_reg_t reg = TRANS_DP_CTL(pipe);
5939 temp = intel_de_read(dev_priv, reg);
5940 temp &= ~(TRANS_DP_PORT_SEL_MASK |
5941 TRANS_DP_SYNC_MASK |
5943 temp |= TRANS_DP_OUTPUT_ENABLE;
5944 temp |= bpc << 9; /* same format but at 11:9 */
5946 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
5947 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
5948 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
5949 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
5951 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
5952 drm_WARN_ON(dev, port < PORT_B || port > PORT_D);
5953 temp |= TRANS_DP_PORT_SEL(port);
5955 intel_de_write(dev_priv, reg, temp);
5958 ilk_enable_pch_transcoder(crtc_state);
5961 void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
5963 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5964 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5965 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5967 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
5969 lpt_program_iclkip(crtc_state);
5971 /* Set transcoder timing. */
5972 ilk_pch_transcoder_set_timings(crtc_state, PIPE_A);
5974 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
5977 static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
5980 i915_reg_t dslreg = PIPEDSL(pipe);
5983 temp = intel_de_read(dev_priv, dslreg);
5985 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) {
5986 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5))
5987 drm_err(&dev_priv->drm,
5988 "mode set failed: pipe %c stuck\n",
5994 * The hardware phase 0.0 refers to the center of the pixel.
5995 * We want to start from the top/left edge which is phase
5996 * -0.5. That matches how the hardware calculates the scaling
5997 * factors (from top-left of the first pixel to bottom-right
5998 * of the last pixel, as opposed to the pixel centers).
6000 * For 4:2:0 subsampled chroma planes we obviously have to
6001 * adjust that so that the chroma sample position lands in
6004 * Note that for packed YCbCr 4:2:2 formats there is no way to
6005 * control chroma siting. The hardware simply replicates the
6006 * chroma samples for both of the luma samples, and thus we don't
6007 * actually get the expected MPEG2 chroma siting convention :(
6008 * The same behaviour is observed on pre-SKL platforms as well.
6010 * Theory behind the formula (note that we ignore sub-pixel
6011 * source coordinates):
6012 * s = source sample position
6013 * d = destination sample position
6018 * | | 1.5 (initial phase)
6026 * | -0.375 (initial phase)
6033 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
6035 int phase = -0x8000;
6039 phase += (sub - 1) * 0x8000 / sub;
6041 phase += scale / (2 * sub);
6044 * Hardware initial phase limited to [-0.5:1.5].
6045 * Since the max hardware scale factor is 3.0, we
6046 * should never actually excdeed 1.0 here.
6048 WARN_ON(phase < -0x8000 || phase > 0x18000);
6051 phase = 0x10000 + phase;
6053 trip = PS_PHASE_TRIP;
6055 return ((phase >> 2) & PS_PHASE_MASK) | trip;
6058 #define SKL_MIN_SRC_W 8
6059 #define SKL_MAX_SRC_W 4096
6060 #define SKL_MIN_SRC_H 8
6061 #define SKL_MAX_SRC_H 4096
6062 #define SKL_MIN_DST_W 8
6063 #define SKL_MAX_DST_W 4096
6064 #define SKL_MIN_DST_H 8
6065 #define SKL_MAX_DST_H 4096
6066 #define ICL_MAX_SRC_W 5120
6067 #define ICL_MAX_SRC_H 4096
6068 #define ICL_MAX_DST_W 5120
6069 #define ICL_MAX_DST_H 4096
6070 #define SKL_MIN_YUV_420_SRC_W 16
6071 #define SKL_MIN_YUV_420_SRC_H 16
6074 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
6075 unsigned int scaler_user, int *scaler_id,
6076 int src_w, int src_h, int dst_w, int dst_h,
6077 const struct drm_format_info *format,
6078 u64 modifier, bool need_scaler)
6080 struct intel_crtc_scaler_state *scaler_state =
6081 &crtc_state->scaler_state;
6082 struct intel_crtc *intel_crtc =
6083 to_intel_crtc(crtc_state->uapi.crtc);
6084 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6085 const struct drm_display_mode *adjusted_mode =
6086 &crtc_state->hw.adjusted_mode;
6089 * Src coordinates are already rotated by 270 degrees for
6090 * the 90/270 degree plane rotation cases (to match the
6091 * GTT mapping), hence no need to account for rotation here.
6093 if (src_w != dst_w || src_h != dst_h)
6097 * Scaling/fitting not supported in IF-ID mode in GEN9+
6098 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
6099 * Once NV12 is enabled, handle it here while allocating scaler
6102 if (INTEL_GEN(dev_priv) >= 9 && crtc_state->hw.enable &&
6103 need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6104 drm_dbg_kms(&dev_priv->drm,
6105 "Pipe/Plane scaling not supported with IF-ID mode\n");
6110 * if plane is being disabled or scaler is no more required or force detach
6111 * - free scaler binded to this plane/crtc
6112 * - in order to do this, update crtc->scaler_usage
6114 * Here scaler state in crtc_state is set free so that
6115 * scaler can be assigned to other user. Actual register
6116 * update to free the scaler is done in plane/panel-fit programming.
6117 * For this purpose crtc/plane_state->scaler_id isn't reset here.
6119 if (force_detach || !need_scaler) {
6120 if (*scaler_id >= 0) {
6121 scaler_state->scaler_users &= ~(1 << scaler_user);
6122 scaler_state->scalers[*scaler_id].in_use = 0;
6124 drm_dbg_kms(&dev_priv->drm,
6125 "scaler_user index %u.%u: "
6126 "Staged freeing scaler id %d scaler_users = 0x%x\n",
6127 intel_crtc->pipe, scaler_user, *scaler_id,
6128 scaler_state->scaler_users);
6134 if (format && intel_format_info_is_yuv_semiplanar(format, modifier) &&
6135 (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
6136 drm_dbg_kms(&dev_priv->drm,
6137 "Planar YUV: src dimensions not met\n");
6142 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
6143 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
6144 (INTEL_GEN(dev_priv) >= 11 &&
6145 (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
6146 dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
6147 (INTEL_GEN(dev_priv) < 11 &&
6148 (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
6149 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
6150 drm_dbg_kms(&dev_priv->drm,
6151 "scaler_user index %u.%u: src %ux%u dst %ux%u "
6152 "size is out of scaler range\n",
6153 intel_crtc->pipe, scaler_user, src_w, src_h,
6158 /* mark this plane as a scaler user in crtc_state */
6159 scaler_state->scaler_users |= (1 << scaler_user);
6160 drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: "
6161 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
6162 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
6163 scaler_state->scaler_users);
6168 static int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
6170 const struct drm_display_mode *adjusted_mode =
6171 &crtc_state->hw.adjusted_mode;
6174 if (crtc_state->pch_pfit.enabled) {
6175 width = drm_rect_width(&crtc_state->pch_pfit.dst);
6176 height = drm_rect_height(&crtc_state->pch_pfit.dst);
6178 width = adjusted_mode->crtc_hdisplay;
6179 height = adjusted_mode->crtc_vdisplay;
6182 return skl_update_scaler(crtc_state, !crtc_state->hw.active,
6184 &crtc_state->scaler_state.scaler_id,
6185 crtc_state->pipe_src_w, crtc_state->pipe_src_h,
6186 width, height, NULL, 0,
6187 crtc_state->pch_pfit.enabled);
6191 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
6192 * @crtc_state: crtc's scaler state
6193 * @plane_state: atomic plane state to update
6196 * 0 - scaler_usage updated successfully
6197 * error - requested scaling cannot be supported or other error condition
6199 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
6200 struct intel_plane_state *plane_state)
6202 struct intel_plane *intel_plane =
6203 to_intel_plane(plane_state->uapi.plane);
6204 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
6205 struct drm_framebuffer *fb = plane_state->hw.fb;
6207 bool force_detach = !fb || !plane_state->uapi.visible;
6208 bool need_scaler = false;
6210 /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
6211 if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
6212 fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
6215 ret = skl_update_scaler(crtc_state, force_detach,
6216 drm_plane_index(&intel_plane->base),
6217 &plane_state->scaler_id,
6218 drm_rect_width(&plane_state->uapi.src) >> 16,
6219 drm_rect_height(&plane_state->uapi.src) >> 16,
6220 drm_rect_width(&plane_state->uapi.dst),
6221 drm_rect_height(&plane_state->uapi.dst),
6222 fb ? fb->format : NULL,
6223 fb ? fb->modifier : 0,
6226 if (ret || plane_state->scaler_id < 0)
6229 /* check colorkey */
6230 if (plane_state->ckey.flags) {
6231 drm_dbg_kms(&dev_priv->drm,
6232 "[PLANE:%d:%s] scaling with color key not allowed",
6233 intel_plane->base.base.id,
6234 intel_plane->base.name);
6238 /* Check src format */
6239 switch (fb->format->format) {
6240 case DRM_FORMAT_RGB565:
6241 case DRM_FORMAT_XBGR8888:
6242 case DRM_FORMAT_XRGB8888:
6243 case DRM_FORMAT_ABGR8888:
6244 case DRM_FORMAT_ARGB8888:
6245 case DRM_FORMAT_XRGB2101010:
6246 case DRM_FORMAT_XBGR2101010:
6247 case DRM_FORMAT_ARGB2101010:
6248 case DRM_FORMAT_ABGR2101010:
6249 case DRM_FORMAT_YUYV:
6250 case DRM_FORMAT_YVYU:
6251 case DRM_FORMAT_UYVY:
6252 case DRM_FORMAT_VYUY:
6253 case DRM_FORMAT_NV12:
6254 case DRM_FORMAT_XYUV8888:
6255 case DRM_FORMAT_P010:
6256 case DRM_FORMAT_P012:
6257 case DRM_FORMAT_P016:
6258 case DRM_FORMAT_Y210:
6259 case DRM_FORMAT_Y212:
6260 case DRM_FORMAT_Y216:
6261 case DRM_FORMAT_XVYU2101010:
6262 case DRM_FORMAT_XVYU12_16161616:
6263 case DRM_FORMAT_XVYU16161616:
6265 case DRM_FORMAT_XBGR16161616F:
6266 case DRM_FORMAT_ABGR16161616F:
6267 case DRM_FORMAT_XRGB16161616F:
6268 case DRM_FORMAT_ARGB16161616F:
6269 if (INTEL_GEN(dev_priv) >= 11)
6273 drm_dbg_kms(&dev_priv->drm,
6274 "[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
6275 intel_plane->base.base.id, intel_plane->base.name,
6276 fb->base.id, fb->format->format);
6283 void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state)
6285 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
6288 for (i = 0; i < crtc->num_scalers; i++)
6289 skl_detach_scaler(crtc, i);
6292 static int cnl_coef_tap(int i)
6297 static u16 cnl_nearest_filter_coef(int t)
6299 return t == 3 ? 0x0800 : 0x3000;
6303 * Theory behind setting nearest-neighbor integer scaling:
6305 * 17 phase of 7 taps requires 119 coefficients in 60 dwords per set.
6306 * The letter represents the filter tap (D is the center tap) and the number
6307 * represents the coefficient set for a phase (0-16).
6309 * +------------+------------------------+------------------------+
6310 * |Index value | Data value coeffient 1 | Data value coeffient 2 |
6311 * +------------+------------------------+------------------------+
6313 * +------------+------------------------+------------------------+
6315 * +------------+------------------------+------------------------+
6317 * +------------+------------------------+------------------------+
6319 * +------------+------------------------+------------------------+
6321 * +------------+------------------------+------------------------+
6322 * | ... | ... | ... |
6323 * +------------+------------------------+------------------------+
6324 * | 38h | B16 | A16 |
6325 * +------------+------------------------+------------------------+
6326 * | 39h | D16 | C16 |
6327 * +------------+------------------------+------------------------+
6328 * | 3Ah | F16 | C16 |
6329 * +------------+------------------------+------------------------+
6330 * | 3Bh | Reserved | G16 |
6331 * +------------+------------------------+------------------------+
6333 * To enable nearest-neighbor scaling: program scaler coefficents with
6334 * the center tap (Dxx) values set to 1 and all other values set to 0 as per
6335 * SCALER_COEFFICIENT_FORMAT
6339 static void cnl_program_nearest_filter_coefs(struct drm_i915_private *dev_priv,
6340 enum pipe pipe, int id, int set)
6344 intel_de_write_fw(dev_priv, CNL_PS_COEF_INDEX_SET(pipe, id, set),
6345 PS_COEE_INDEX_AUTO_INC);
6347 for (i = 0; i < 17 * 7; i += 2) {
6351 t = cnl_coef_tap(i);
6352 tmp = cnl_nearest_filter_coef(t);
6354 t = cnl_coef_tap(i + 1);
6355 tmp |= cnl_nearest_filter_coef(t) << 16;
6357 intel_de_write_fw(dev_priv, CNL_PS_COEF_DATA_SET(pipe, id, set),
6361 intel_de_write_fw(dev_priv, CNL_PS_COEF_INDEX_SET(pipe, id, set), 0);
6364 inline u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set)
6366 if (filter == DRM_SCALING_FILTER_NEAREST_NEIGHBOR) {
6367 return (PS_FILTER_PROGRAMMED |
6368 PS_Y_VERT_FILTER_SELECT(set) |
6369 PS_Y_HORZ_FILTER_SELECT(set) |
6370 PS_UV_VERT_FILTER_SELECT(set) |
6371 PS_UV_HORZ_FILTER_SELECT(set));
6374 return PS_FILTER_MEDIUM;
6377 void skl_scaler_setup_filter(struct drm_i915_private *dev_priv, enum pipe pipe,
6378 int id, int set, enum drm_scaling_filter filter)
6381 case DRM_SCALING_FILTER_DEFAULT:
6383 case DRM_SCALING_FILTER_NEAREST_NEIGHBOR:
6384 cnl_program_nearest_filter_coefs(dev_priv, pipe, id, set);
6387 MISSING_CASE(filter);
6391 static void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
6393 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6394 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6395 const struct intel_crtc_scaler_state *scaler_state =
6396 &crtc_state->scaler_state;
6397 struct drm_rect src = {
6398 .x2 = crtc_state->pipe_src_w << 16,
6399 .y2 = crtc_state->pipe_src_h << 16,
6401 const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
6402 u16 uv_rgb_hphase, uv_rgb_vphase;
6403 enum pipe pipe = crtc->pipe;
6404 int width = drm_rect_width(dst);
6405 int height = drm_rect_height(dst);
6409 unsigned long irqflags;
6413 if (!crtc_state->pch_pfit.enabled)
6416 if (drm_WARN_ON(&dev_priv->drm,
6417 crtc_state->scaler_state.scaler_id < 0))
6420 hscale = drm_rect_calc_hscale(&src, dst, 0, INT_MAX);
6421 vscale = drm_rect_calc_vscale(&src, dst, 0, INT_MAX);
6423 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
6424 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
6426 id = scaler_state->scaler_id;
6428 ps_ctrl = skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0);
6429 ps_ctrl |= PS_SCALER_EN | scaler_state->scalers[id].mode;
6431 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
6433 skl_scaler_setup_filter(dev_priv, pipe, id, 0,
6434 crtc_state->hw.scaling_filter);
6436 intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), ps_ctrl);
6438 intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
6439 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
6440 intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
6441 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
6442 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
6444 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
6445 width << 16 | height);
6447 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
6450 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
6452 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6453 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6454 const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
6455 enum pipe pipe = crtc->pipe;
6456 int width = drm_rect_width(dst);
6457 int height = drm_rect_height(dst);
6461 if (!crtc_state->pch_pfit.enabled)
6464 /* Force use of hard-coded filter coefficients
6465 * as some pre-programmed values are broken,
6468 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
6469 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
6470 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
6472 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
6474 intel_de_write(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
6475 intel_de_write(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
6478 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
6480 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6481 struct drm_device *dev = crtc->base.dev;
6482 struct drm_i915_private *dev_priv = to_i915(dev);
6484 if (!crtc_state->ips_enabled)
6488 * We can only enable IPS after we enable a plane and wait for a vblank
6489 * This function is called from post_plane_update, which is run after
6492 drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
6494 if (IS_BROADWELL(dev_priv)) {
6495 drm_WARN_ON(dev, sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
6496 IPS_ENABLE | IPS_PCODE_CONTROL));
6497 /* Quoting Art Runyan: "its not safe to expect any particular
6498 * value in IPS_CTL bit 31 after enabling IPS through the
6499 * mailbox." Moreover, the mailbox may return a bogus state,
6500 * so we need to just enable it and continue on.
6503 intel_de_write(dev_priv, IPS_CTL, IPS_ENABLE);
6504 /* The bit only becomes 1 in the next vblank, so this wait here
6505 * is essentially intel_wait_for_vblank. If we don't have this
6506 * and don't wait for vblanks until the end of crtc_enable, then
6507 * the HW state readout code will complain that the expected
6508 * IPS_CTL value is not the one we read. */
6509 if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50))
6510 drm_err(&dev_priv->drm,
6511 "Timed out waiting for IPS enable\n");
6515 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
6517 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6518 struct drm_device *dev = crtc->base.dev;
6519 struct drm_i915_private *dev_priv = to_i915(dev);
6521 if (!crtc_state->ips_enabled)
6524 if (IS_BROADWELL(dev_priv)) {
6526 sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
6528 * Wait for PCODE to finish disabling IPS. The BSpec specified
6529 * 42ms timeout value leads to occasional timeouts so use 100ms
6532 if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100))
6533 drm_err(&dev_priv->drm,
6534 "Timed out waiting for IPS disable\n");
6536 intel_de_write(dev_priv, IPS_CTL, 0);
6537 intel_de_posting_read(dev_priv, IPS_CTL);
6540 /* We need to wait for a vblank before we can disable the plane. */
6541 intel_wait_for_vblank(dev_priv, crtc->pipe);
6544 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
6546 if (intel_crtc->overlay)
6547 (void) intel_overlay_switch_off(intel_crtc->overlay);
6549 /* Let userspace switch the overlay on again. In most cases userspace
6550 * has to recompute where to put it anyway.
6554 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
6555 const struct intel_crtc_state *new_crtc_state)
6557 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6558 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6560 if (!old_crtc_state->ips_enabled)
6563 if (needs_modeset(new_crtc_state))
6567 * Workaround : Do not read or write the pipe palette/gamma data while
6568 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6570 * Disable IPS before we program the LUT.
6572 if (IS_HASWELL(dev_priv) &&
6573 (new_crtc_state->uapi.color_mgmt_changed ||
6574 new_crtc_state->update_pipe) &&
6575 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
6578 return !new_crtc_state->ips_enabled;
6581 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
6582 const struct intel_crtc_state *new_crtc_state)
6584 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6585 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6587 if (!new_crtc_state->ips_enabled)
6590 if (needs_modeset(new_crtc_state))
6594 * Workaround : Do not read or write the pipe palette/gamma data while
6595 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6597 * Re-enable IPS after the LUT has been programmed.
6599 if (IS_HASWELL(dev_priv) &&
6600 (new_crtc_state->uapi.color_mgmt_changed ||
6601 new_crtc_state->update_pipe) &&
6602 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
6606 * We can't read out IPS on broadwell, assume the worst and
6607 * forcibly enable IPS on the first fastset.
6609 if (new_crtc_state->update_pipe && old_crtc_state->inherited)
6612 return !old_crtc_state->ips_enabled;
6615 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
6617 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
6619 if (!crtc_state->nv12_planes)
6622 /* WA Display #0827: Gen9:all */
6623 if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
6629 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
6631 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
6633 /* Wa_2006604312:icl,ehl */
6634 if (crtc_state->scaler_state.scaler_users > 0 && IS_GEN(dev_priv, 11))
6640 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
6641 const struct intel_crtc_state *new_crtc_state)
6643 return (!old_crtc_state->active_planes || needs_modeset(new_crtc_state)) &&
6644 new_crtc_state->active_planes;
6647 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
6648 const struct intel_crtc_state *new_crtc_state)
6650 return old_crtc_state->active_planes &&
6651 (!new_crtc_state->active_planes || needs_modeset(new_crtc_state));
6654 static void intel_post_plane_update(struct intel_atomic_state *state,
6655 struct intel_crtc *crtc)
6657 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6658 const struct intel_crtc_state *old_crtc_state =
6659 intel_atomic_get_old_crtc_state(state, crtc);
6660 const struct intel_crtc_state *new_crtc_state =
6661 intel_atomic_get_new_crtc_state(state, crtc);
6662 enum pipe pipe = crtc->pipe;
6664 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
6666 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
6667 intel_update_watermarks(crtc);
6669 if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
6670 hsw_enable_ips(new_crtc_state);
6672 intel_fbc_post_update(state, crtc);
6674 if (needs_nv12_wa(old_crtc_state) &&
6675 !needs_nv12_wa(new_crtc_state))
6676 skl_wa_827(dev_priv, pipe, false);
6678 if (needs_scalerclk_wa(old_crtc_state) &&
6679 !needs_scalerclk_wa(new_crtc_state))
6680 icl_wa_scalerclkgating(dev_priv, pipe, false);
6683 static void skl_disable_async_flip_wa(struct intel_atomic_state *state,
6684 struct intel_crtc *crtc,
6685 const struct intel_crtc_state *new_crtc_state)
6687 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6688 struct intel_plane *plane;
6689 struct intel_plane_state *new_plane_state;
6692 for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
6693 u32 update_mask = new_crtc_state->update_planes;
6694 u32 plane_ctl, surf_addr;
6695 enum plane_id plane_id;
6696 unsigned long irqflags;
6699 if (crtc->pipe != plane->pipe ||
6700 !(update_mask & BIT(plane->id)))
6703 plane_id = plane->id;
6706 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
6707 plane_ctl = intel_de_read_fw(dev_priv, PLANE_CTL(pipe, plane_id));
6708 surf_addr = intel_de_read_fw(dev_priv, PLANE_SURF(pipe, plane_id));
6710 plane_ctl &= ~PLANE_CTL_ASYNC_FLIP;
6712 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
6713 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), surf_addr);
6714 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
6717 intel_wait_for_vblank(dev_priv, crtc->pipe);
6720 static void intel_pre_plane_update(struct intel_atomic_state *state,
6721 struct intel_crtc *crtc)
6723 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6724 const struct intel_crtc_state *old_crtc_state =
6725 intel_atomic_get_old_crtc_state(state, crtc);
6726 const struct intel_crtc_state *new_crtc_state =
6727 intel_atomic_get_new_crtc_state(state, crtc);
6728 enum pipe pipe = crtc->pipe;
6730 if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
6731 hsw_disable_ips(old_crtc_state);
6733 if (intel_fbc_pre_update(state, crtc))
6734 intel_wait_for_vblank(dev_priv, pipe);
6736 /* Display WA 827 */
6737 if (!needs_nv12_wa(old_crtc_state) &&
6738 needs_nv12_wa(new_crtc_state))
6739 skl_wa_827(dev_priv, pipe, true);
6741 /* Wa_2006604312:icl,ehl */
6742 if (!needs_scalerclk_wa(old_crtc_state) &&
6743 needs_scalerclk_wa(new_crtc_state))
6744 icl_wa_scalerclkgating(dev_priv, pipe, true);
6747 * Vblank time updates from the shadow to live plane control register
6748 * are blocked if the memory self-refresh mode is active at that
6749 * moment. So to make sure the plane gets truly disabled, disable
6750 * first the self-refresh mode. The self-refresh enable bit in turn
6751 * will be checked/applied by the HW only at the next frame start
6752 * event which is after the vblank start event, so we need to have a
6753 * wait-for-vblank between disabling the plane and the pipe.
6755 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
6756 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
6757 intel_wait_for_vblank(dev_priv, pipe);
6760 * IVB workaround: must disable low power watermarks for at least
6761 * one frame before enabling scaling. LP watermarks can be re-enabled
6762 * when scaling is disabled.
6764 * WaCxSRDisabledForSpriteScaling:ivb
6766 if (old_crtc_state->hw.active &&
6767 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
6768 intel_wait_for_vblank(dev_priv, pipe);
6771 * If we're doing a modeset we don't need to do any
6772 * pre-vblank watermark programming here.
6774 if (!needs_modeset(new_crtc_state)) {
6776 * For platforms that support atomic watermarks, program the
6777 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
6778 * will be the intermediate values that are safe for both pre- and
6779 * post- vblank; when vblank happens, the 'active' values will be set
6780 * to the final 'target' values and we'll do this again to get the
6781 * optimal watermarks. For gen9+ platforms, the values we program here
6782 * will be the final target values which will get automatically latched
6783 * at vblank time; no further programming will be necessary.
6785 * If a platform hasn't been transitioned to atomic watermarks yet,
6786 * we'll continue to update watermarks the old way, if flags tell
6789 if (dev_priv->display.initial_watermarks)
6790 dev_priv->display.initial_watermarks(state, crtc);
6791 else if (new_crtc_state->update_wm_pre)
6792 intel_update_watermarks(crtc);
6796 * Gen2 reports pipe underruns whenever all planes are disabled.
6797 * So disable underrun reporting before all the planes get disabled.
6799 * We do this after .initial_watermarks() so that we have a
6800 * chance of catching underruns with the intermediate watermarks
6801 * vs. the old plane configuration.
6803 if (IS_GEN(dev_priv, 2) && planes_disabling(old_crtc_state, new_crtc_state))
6804 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6807 * WA for platforms where async address update enable bit
6808 * is double buffered and only latched at start of vblank.
6810 if (old_crtc_state->uapi.async_flip &&
6811 !new_crtc_state->uapi.async_flip &&
6812 IS_GEN_RANGE(dev_priv, 9, 10))
6813 skl_disable_async_flip_wa(state, crtc, new_crtc_state);
6816 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
6817 struct intel_crtc *crtc)
6819 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6820 const struct intel_crtc_state *new_crtc_state =
6821 intel_atomic_get_new_crtc_state(state, crtc);
6822 unsigned int update_mask = new_crtc_state->update_planes;
6823 const struct intel_plane_state *old_plane_state;
6824 struct intel_plane *plane;
6825 unsigned fb_bits = 0;
6828 intel_crtc_dpms_overlay_disable(crtc);
6830 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
6831 if (crtc->pipe != plane->pipe ||
6832 !(update_mask & BIT(plane->id)))
6835 intel_disable_plane(plane, new_crtc_state);
6837 if (old_plane_state->uapi.visible)
6838 fb_bits |= plane->frontbuffer_bit;
6841 intel_frontbuffer_flip(dev_priv, fb_bits);
6845 * intel_connector_primary_encoder - get the primary encoder for a connector
6846 * @connector: connector for which to return the encoder
6848 * Returns the primary encoder for a connector. There is a 1:1 mapping from
6849 * all connectors to their encoder, except for DP-MST connectors which have
6850 * both a virtual and a primary encoder. These DP-MST primary encoders can be
6851 * pointed to by as many DP-MST connectors as there are pipes.
6853 static struct intel_encoder *
6854 intel_connector_primary_encoder(struct intel_connector *connector)
6856 struct intel_encoder *encoder;
6858 if (connector->mst_port)
6859 return &dp_to_dig_port(connector->mst_port)->base;
6861 encoder = intel_attached_encoder(connector);
6862 drm_WARN_ON(connector->base.dev, !encoder);
6867 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
6869 struct drm_connector_state *new_conn_state;
6870 struct drm_connector *connector;
6873 for_each_new_connector_in_state(&state->base, connector, new_conn_state,
6875 struct intel_connector *intel_connector;
6876 struct intel_encoder *encoder;
6877 struct intel_crtc *crtc;
6879 if (!intel_connector_needs_modeset(state, connector))
6882 intel_connector = to_intel_connector(connector);
6883 encoder = intel_connector_primary_encoder(intel_connector);
6884 if (!encoder->update_prepare)
6887 crtc = new_conn_state->crtc ?
6888 to_intel_crtc(new_conn_state->crtc) : NULL;
6889 encoder->update_prepare(state, encoder, crtc);
6893 static void intel_encoders_update_complete(struct intel_atomic_state *state)
6895 struct drm_connector_state *new_conn_state;
6896 struct drm_connector *connector;
6899 for_each_new_connector_in_state(&state->base, connector, new_conn_state,
6901 struct intel_connector *intel_connector;
6902 struct intel_encoder *encoder;
6903 struct intel_crtc *crtc;
6905 if (!intel_connector_needs_modeset(state, connector))
6908 intel_connector = to_intel_connector(connector);
6909 encoder = intel_connector_primary_encoder(intel_connector);
6910 if (!encoder->update_complete)
6913 crtc = new_conn_state->crtc ?
6914 to_intel_crtc(new_conn_state->crtc) : NULL;
6915 encoder->update_complete(state, encoder, crtc);
6919 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
6920 struct intel_crtc *crtc)
6922 const struct intel_crtc_state *crtc_state =
6923 intel_atomic_get_new_crtc_state(state, crtc);
6924 const struct drm_connector_state *conn_state;
6925 struct drm_connector *conn;
6928 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6929 struct intel_encoder *encoder =
6930 to_intel_encoder(conn_state->best_encoder);
6932 if (conn_state->crtc != &crtc->base)
6935 if (encoder->pre_pll_enable)
6936 encoder->pre_pll_enable(state, encoder,
6937 crtc_state, conn_state);
6941 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
6942 struct intel_crtc *crtc)
6944 const struct intel_crtc_state *crtc_state =
6945 intel_atomic_get_new_crtc_state(state, crtc);
6946 const struct drm_connector_state *conn_state;
6947 struct drm_connector *conn;
6950 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6951 struct intel_encoder *encoder =
6952 to_intel_encoder(conn_state->best_encoder);
6954 if (conn_state->crtc != &crtc->base)
6957 if (encoder->pre_enable)
6958 encoder->pre_enable(state, encoder,
6959 crtc_state, conn_state);
6963 static void intel_encoders_enable(struct intel_atomic_state *state,
6964 struct intel_crtc *crtc)
6966 const struct intel_crtc_state *crtc_state =
6967 intel_atomic_get_new_crtc_state(state, crtc);
6968 const struct drm_connector_state *conn_state;
6969 struct drm_connector *conn;
6972 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6973 struct intel_encoder *encoder =
6974 to_intel_encoder(conn_state->best_encoder);
6976 if (conn_state->crtc != &crtc->base)
6979 if (encoder->enable)
6980 encoder->enable(state, encoder,
6981 crtc_state, conn_state);
6982 intel_opregion_notify_encoder(encoder, true);
6986 static void intel_encoders_disable(struct intel_atomic_state *state,
6987 struct intel_crtc *crtc)
6989 const struct intel_crtc_state *old_crtc_state =
6990 intel_atomic_get_old_crtc_state(state, crtc);
6991 const struct drm_connector_state *old_conn_state;
6992 struct drm_connector *conn;
6995 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6996 struct intel_encoder *encoder =
6997 to_intel_encoder(old_conn_state->best_encoder);
6999 if (old_conn_state->crtc != &crtc->base)
7002 intel_opregion_notify_encoder(encoder, false);
7003 if (encoder->disable)
7004 encoder->disable(state, encoder,
7005 old_crtc_state, old_conn_state);
7009 static void intel_encoders_post_disable(struct intel_atomic_state *state,
7010 struct intel_crtc *crtc)
7012 const struct intel_crtc_state *old_crtc_state =
7013 intel_atomic_get_old_crtc_state(state, crtc);
7014 const struct drm_connector_state *old_conn_state;
7015 struct drm_connector *conn;
7018 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
7019 struct intel_encoder *encoder =
7020 to_intel_encoder(old_conn_state->best_encoder);
7022 if (old_conn_state->crtc != &crtc->base)
7025 if (encoder->post_disable)
7026 encoder->post_disable(state, encoder,
7027 old_crtc_state, old_conn_state);
7031 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
7032 struct intel_crtc *crtc)
7034 const struct intel_crtc_state *old_crtc_state =
7035 intel_atomic_get_old_crtc_state(state, crtc);
7036 const struct drm_connector_state *old_conn_state;
7037 struct drm_connector *conn;
7040 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
7041 struct intel_encoder *encoder =
7042 to_intel_encoder(old_conn_state->best_encoder);
7044 if (old_conn_state->crtc != &crtc->base)
7047 if (encoder->post_pll_disable)
7048 encoder->post_pll_disable(state, encoder,
7049 old_crtc_state, old_conn_state);
7053 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
7054 struct intel_crtc *crtc)
7056 const struct intel_crtc_state *crtc_state =
7057 intel_atomic_get_new_crtc_state(state, crtc);
7058 const struct drm_connector_state *conn_state;
7059 struct drm_connector *conn;
7062 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
7063 struct intel_encoder *encoder =
7064 to_intel_encoder(conn_state->best_encoder);
7066 if (conn_state->crtc != &crtc->base)
7069 if (encoder->update_pipe)
7070 encoder->update_pipe(state, encoder,
7071 crtc_state, conn_state);
7075 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
7077 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7078 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
7080 plane->disable_plane(plane, crtc_state);
7083 static void ilk_crtc_enable(struct intel_atomic_state *state,
7084 struct intel_crtc *crtc)
7086 const struct intel_crtc_state *new_crtc_state =
7087 intel_atomic_get_new_crtc_state(state, crtc);
7088 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7089 enum pipe pipe = crtc->pipe;
7091 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7095 * Sometimes spurious CPU pipe underruns happen during FDI
7096 * training, at least with VGA+HDMI cloning. Suppress them.
7098 * On ILK we get an occasional spurious CPU pipe underruns
7099 * between eDP port A enable and vdd enable. Also PCH port
7100 * enable seems to result in the occasional CPU pipe underrun.
7102 * Spurious PCH underruns also occur during PCH enabling.
7104 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7105 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
7107 if (new_crtc_state->has_pch_encoder)
7108 intel_prepare_shared_dpll(new_crtc_state);
7110 if (intel_crtc_has_dp_encoder(new_crtc_state))
7111 intel_dp_set_m_n(new_crtc_state, M1_N1);
7113 intel_set_transcoder_timings(new_crtc_state);
7114 intel_set_pipe_src_size(new_crtc_state);
7116 if (new_crtc_state->has_pch_encoder)
7117 intel_cpu_transcoder_set_m_n(new_crtc_state,
7118 &new_crtc_state->fdi_m_n, NULL);
7120 ilk_set_pipeconf(new_crtc_state);
7122 crtc->active = true;
7124 intel_encoders_pre_enable(state, crtc);
7126 if (new_crtc_state->has_pch_encoder) {
7127 /* Note: FDI PLL enabling _must_ be done before we enable the
7128 * cpu pipes, hence this is separate from all the other fdi/pch
7130 ilk_fdi_pll_enable(new_crtc_state);
7132 assert_fdi_tx_disabled(dev_priv, pipe);
7133 assert_fdi_rx_disabled(dev_priv, pipe);
7136 ilk_pfit_enable(new_crtc_state);
7139 * On ILK+ LUT must be loaded before the pipe is running but with
7142 intel_color_load_luts(new_crtc_state);
7143 intel_color_commit(new_crtc_state);
7144 /* update DSPCNTR to configure gamma for pipe bottom color */
7145 intel_disable_primary_plane(new_crtc_state);
7147 if (dev_priv->display.initial_watermarks)
7148 dev_priv->display.initial_watermarks(state, crtc);
7149 intel_enable_pipe(new_crtc_state);
7151 if (new_crtc_state->has_pch_encoder)
7152 ilk_pch_enable(state, new_crtc_state);
7154 intel_crtc_vblank_on(new_crtc_state);
7156 intel_encoders_enable(state, crtc);
7158 if (HAS_PCH_CPT(dev_priv))
7159 cpt_verify_modeset(dev_priv, pipe);
7162 * Must wait for vblank to avoid spurious PCH FIFO underruns.
7163 * And a second vblank wait is needed at least on ILK with
7164 * some interlaced HDMI modes. Let's do the double wait always
7165 * in case there are more corner cases we don't know about.
7167 if (new_crtc_state->has_pch_encoder) {
7168 intel_wait_for_vblank(dev_priv, pipe);
7169 intel_wait_for_vblank(dev_priv, pipe);
7171 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7172 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
7175 /* IPS only exists on ULT machines and is tied to pipe A. */
7176 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
7178 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
7181 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
7182 enum pipe pipe, bool apply)
7184 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe));
7185 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
7192 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
7195 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
7197 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7198 enum pipe pipe = crtc->pipe;
7201 val = MBUS_DBOX_A_CREDIT(2);
7203 if (INTEL_GEN(dev_priv) >= 12) {
7204 val |= MBUS_DBOX_BW_CREDIT(2);
7205 val |= MBUS_DBOX_B_CREDIT(12);
7207 val |= MBUS_DBOX_BW_CREDIT(1);
7208 val |= MBUS_DBOX_B_CREDIT(8);
7211 intel_de_write(dev_priv, PIPE_MBUS_DBOX_CTL(pipe), val);
7214 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
7216 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7217 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7219 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),
7220 HSW_LINETIME(crtc_state->linetime) |
7221 HSW_IPS_LINETIME(crtc_state->ips_linetime));
7224 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
7226 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7227 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7228 i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
7231 val = intel_de_read(dev_priv, reg);
7232 val &= ~HSW_FRAME_START_DELAY_MASK;
7233 val |= HSW_FRAME_START_DELAY(0);
7234 intel_de_write(dev_priv, reg, val);
7237 static void hsw_crtc_enable(struct intel_atomic_state *state,
7238 struct intel_crtc *crtc)
7240 const struct intel_crtc_state *new_crtc_state =
7241 intel_atomic_get_new_crtc_state(state, crtc);
7242 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7243 enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
7244 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
7245 bool psl_clkgate_wa;
7247 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7250 intel_encoders_pre_pll_enable(state, crtc);
7252 if (new_crtc_state->shared_dpll)
7253 intel_enable_shared_dpll(new_crtc_state);
7255 intel_encoders_pre_enable(state, crtc);
7257 if (!transcoder_is_dsi(cpu_transcoder))
7258 intel_set_transcoder_timings(new_crtc_state);
7260 intel_set_pipe_src_size(new_crtc_state);
7262 if (cpu_transcoder != TRANSCODER_EDP &&
7263 !transcoder_is_dsi(cpu_transcoder))
7264 intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
7265 new_crtc_state->pixel_multiplier - 1);
7267 if (new_crtc_state->has_pch_encoder)
7268 intel_cpu_transcoder_set_m_n(new_crtc_state,
7269 &new_crtc_state->fdi_m_n, NULL);
7271 if (!transcoder_is_dsi(cpu_transcoder)) {
7272 hsw_set_frame_start_delay(new_crtc_state);
7273 hsw_set_pipeconf(new_crtc_state);
7276 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
7277 bdw_set_pipemisc(new_crtc_state);
7279 crtc->active = true;
7281 /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
7282 psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
7283 new_crtc_state->pch_pfit.enabled;
7285 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
7287 if (INTEL_GEN(dev_priv) >= 9)
7288 skl_pfit_enable(new_crtc_state);
7290 ilk_pfit_enable(new_crtc_state);
7293 * On ILK+ LUT must be loaded before the pipe is running but with
7296 intel_color_load_luts(new_crtc_state);
7297 intel_color_commit(new_crtc_state);
7298 /* update DSPCNTR to configure gamma/csc for pipe bottom color */
7299 if (INTEL_GEN(dev_priv) < 9)
7300 intel_disable_primary_plane(new_crtc_state);
7302 hsw_set_linetime_wm(new_crtc_state);
7304 if (INTEL_GEN(dev_priv) >= 11)
7305 icl_set_pipe_chicken(crtc);
7307 if (dev_priv->display.initial_watermarks)
7308 dev_priv->display.initial_watermarks(state, crtc);
7310 if (INTEL_GEN(dev_priv) >= 11)
7311 icl_pipe_mbus_enable(crtc);
7313 intel_encoders_enable(state, crtc);
7315 if (psl_clkgate_wa) {
7316 intel_wait_for_vblank(dev_priv, pipe);
7317 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
7320 /* If we change the relative order between pipe/planes enabling, we need
7321 * to change the workaround. */
7322 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
7323 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
7324 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
7325 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
7329 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
7331 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
7332 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7333 enum pipe pipe = crtc->pipe;
7335 /* To avoid upsetting the power well on haswell only disable the pfit if
7336 * it's in use. The hw state code will make sure we get this right. */
7337 if (!old_crtc_state->pch_pfit.enabled)
7340 intel_de_write(dev_priv, PF_CTL(pipe), 0);
7341 intel_de_write(dev_priv, PF_WIN_POS(pipe), 0);
7342 intel_de_write(dev_priv, PF_WIN_SZ(pipe), 0);
7345 static void ilk_crtc_disable(struct intel_atomic_state *state,
7346 struct intel_crtc *crtc)
7348 const struct intel_crtc_state *old_crtc_state =
7349 intel_atomic_get_old_crtc_state(state, crtc);
7350 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7351 enum pipe pipe = crtc->pipe;
7354 * Sometimes spurious CPU pipe underruns happen when the
7355 * pipe is already disabled, but FDI RX/TX is still enabled.
7356 * Happens at least with VGA+HDMI cloning. Suppress them.
7358 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7359 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
7361 intel_encoders_disable(state, crtc);
7363 intel_crtc_vblank_off(old_crtc_state);
7365 intel_disable_pipe(old_crtc_state);
7367 ilk_pfit_disable(old_crtc_state);
7369 if (old_crtc_state->has_pch_encoder)
7370 ilk_fdi_disable(crtc);
7372 intel_encoders_post_disable(state, crtc);
7374 if (old_crtc_state->has_pch_encoder) {
7375 ilk_disable_pch_transcoder(dev_priv, pipe);
7377 if (HAS_PCH_CPT(dev_priv)) {
7381 /* disable TRANS_DP_CTL */
7382 reg = TRANS_DP_CTL(pipe);
7383 temp = intel_de_read(dev_priv, reg);
7384 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
7385 TRANS_DP_PORT_SEL_MASK);
7386 temp |= TRANS_DP_PORT_SEL_NONE;
7387 intel_de_write(dev_priv, reg, temp);
7389 /* disable DPLL_SEL */
7390 temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
7391 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
7392 intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
7395 ilk_fdi_pll_disable(crtc);
7398 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7399 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
7402 static void hsw_crtc_disable(struct intel_atomic_state *state,
7403 struct intel_crtc *crtc)
7406 * FIXME collapse everything to one hook.
7407 * Need care with mst->ddi interactions.
7409 intel_encoders_disable(state, crtc);
7410 intel_encoders_post_disable(state, crtc);
7413 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
7415 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7416 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7418 if (!crtc_state->gmch_pfit.control)
7422 * The panel fitter should only be adjusted whilst the pipe is disabled,
7423 * according to register description and PRM.
7425 drm_WARN_ON(&dev_priv->drm,
7426 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
7427 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
7429 intel_de_write(dev_priv, PFIT_PGM_RATIOS,
7430 crtc_state->gmch_pfit.pgm_ratios);
7431 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
7433 /* Border color in case we don't scale up to the full screen. Black by
7434 * default, change to something else for debugging. */
7435 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
7438 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
7440 if (phy == PHY_NONE)
7442 else if (IS_ROCKETLAKE(dev_priv))
7443 return phy <= PHY_D;
7444 else if (IS_JSL_EHL(dev_priv))
7445 return phy <= PHY_C;
7446 else if (INTEL_GEN(dev_priv) >= 11)
7447 return phy <= PHY_B;
7452 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
7454 if (IS_ROCKETLAKE(dev_priv))
7456 else if (INTEL_GEN(dev_priv) >= 12)
7457 return phy >= PHY_D && phy <= PHY_I;
7458 else if (INTEL_GEN(dev_priv) >= 11 && !IS_JSL_EHL(dev_priv))
7459 return phy >= PHY_C && phy <= PHY_F;
7464 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
7466 if (IS_ROCKETLAKE(i915) && port >= PORT_D)
7467 return (enum phy)port - 1;
7468 else if (IS_JSL_EHL(i915) && port == PORT_D)
7471 return (enum phy)port;
7474 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
7476 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
7477 return TC_PORT_NONE;
7479 if (INTEL_GEN(dev_priv) >= 12)
7480 return port - PORT_D;
7482 return port - PORT_C;
7485 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
7489 return POWER_DOMAIN_PORT_DDI_A_LANES;
7491 return POWER_DOMAIN_PORT_DDI_B_LANES;
7493 return POWER_DOMAIN_PORT_DDI_C_LANES;
7495 return POWER_DOMAIN_PORT_DDI_D_LANES;
7497 return POWER_DOMAIN_PORT_DDI_E_LANES;
7499 return POWER_DOMAIN_PORT_DDI_F_LANES;
7501 return POWER_DOMAIN_PORT_DDI_G_LANES;
7503 return POWER_DOMAIN_PORT_DDI_H_LANES;
7505 return POWER_DOMAIN_PORT_DDI_I_LANES;
7508 return POWER_DOMAIN_PORT_OTHER;
7512 enum intel_display_power_domain
7513 intel_aux_power_domain(struct intel_digital_port *dig_port)
7515 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
7516 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
7518 if (intel_phy_is_tc(dev_priv, phy) &&
7519 dig_port->tc_mode == TC_PORT_TBT_ALT) {
7520 switch (dig_port->aux_ch) {
7522 return POWER_DOMAIN_AUX_C_TBT;
7524 return POWER_DOMAIN_AUX_D_TBT;
7526 return POWER_DOMAIN_AUX_E_TBT;
7528 return POWER_DOMAIN_AUX_F_TBT;
7530 return POWER_DOMAIN_AUX_G_TBT;
7532 return POWER_DOMAIN_AUX_H_TBT;
7534 return POWER_DOMAIN_AUX_I_TBT;
7536 MISSING_CASE(dig_port->aux_ch);
7537 return POWER_DOMAIN_AUX_C_TBT;
7541 return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
7545 * Converts aux_ch to power_domain without caring about TBT ports for that use
7546 * intel_aux_power_domain()
7548 enum intel_display_power_domain
7549 intel_legacy_aux_to_power_domain(enum aux_ch aux_ch)
7553 return POWER_DOMAIN_AUX_A;
7555 return POWER_DOMAIN_AUX_B;
7557 return POWER_DOMAIN_AUX_C;
7559 return POWER_DOMAIN_AUX_D;
7561 return POWER_DOMAIN_AUX_E;
7563 return POWER_DOMAIN_AUX_F;
7565 return POWER_DOMAIN_AUX_G;
7567 return POWER_DOMAIN_AUX_H;
7569 return POWER_DOMAIN_AUX_I;
7571 MISSING_CASE(aux_ch);
7572 return POWER_DOMAIN_AUX_A;
7576 static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
7578 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7579 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7580 struct drm_encoder *encoder;
7581 enum pipe pipe = crtc->pipe;
7583 enum transcoder transcoder = crtc_state->cpu_transcoder;
7585 if (!crtc_state->hw.active)
7588 mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
7589 mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
7590 if (crtc_state->pch_pfit.enabled ||
7591 crtc_state->pch_pfit.force_thru)
7592 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
7594 drm_for_each_encoder_mask(encoder, &dev_priv->drm,
7595 crtc_state->uapi.encoder_mask) {
7596 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
7598 mask |= BIT_ULL(intel_encoder->power_domain);
7601 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
7602 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
7604 if (crtc_state->shared_dpll)
7605 mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
7611 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
7613 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7614 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7615 enum intel_display_power_domain domain;
7616 u64 domains, new_domains, old_domains;
7618 old_domains = crtc->enabled_power_domains;
7619 crtc->enabled_power_domains = new_domains =
7620 get_crtc_power_domains(crtc_state);
7622 domains = new_domains & ~old_domains;
7624 for_each_power_domain(domain, domains)
7625 intel_display_power_get(dev_priv, domain);
7627 return old_domains & ~new_domains;
7630 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
7633 enum intel_display_power_domain domain;
7635 for_each_power_domain(domain, domains)
7636 intel_display_power_put_unchecked(dev_priv, domain);
7639 static void valleyview_crtc_enable(struct intel_atomic_state *state,
7640 struct intel_crtc *crtc)
7642 const struct intel_crtc_state *new_crtc_state =
7643 intel_atomic_get_new_crtc_state(state, crtc);
7644 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7645 enum pipe pipe = crtc->pipe;
7647 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7650 if (intel_crtc_has_dp_encoder(new_crtc_state))
7651 intel_dp_set_m_n(new_crtc_state, M1_N1);
7653 intel_set_transcoder_timings(new_crtc_state);
7654 intel_set_pipe_src_size(new_crtc_state);
7656 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
7657 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
7658 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
7661 i9xx_set_pipeconf(new_crtc_state);
7663 crtc->active = true;
7665 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7667 intel_encoders_pre_pll_enable(state, crtc);
7669 if (IS_CHERRYVIEW(dev_priv)) {
7670 chv_prepare_pll(crtc, new_crtc_state);
7671 chv_enable_pll(crtc, new_crtc_state);
7673 vlv_prepare_pll(crtc, new_crtc_state);
7674 vlv_enable_pll(crtc, new_crtc_state);
7677 intel_encoders_pre_enable(state, crtc);
7679 i9xx_pfit_enable(new_crtc_state);
7681 intel_color_load_luts(new_crtc_state);
7682 intel_color_commit(new_crtc_state);
7683 /* update DSPCNTR to configure gamma for pipe bottom color */
7684 intel_disable_primary_plane(new_crtc_state);
7686 dev_priv->display.initial_watermarks(state, crtc);
7687 intel_enable_pipe(new_crtc_state);
7689 intel_crtc_vblank_on(new_crtc_state);
7691 intel_encoders_enable(state, crtc);
7694 static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
7696 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7697 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7699 intel_de_write(dev_priv, FP0(crtc->pipe),
7700 crtc_state->dpll_hw_state.fp0);
7701 intel_de_write(dev_priv, FP1(crtc->pipe),
7702 crtc_state->dpll_hw_state.fp1);
7705 static void i9xx_crtc_enable(struct intel_atomic_state *state,
7706 struct intel_crtc *crtc)
7708 const struct intel_crtc_state *new_crtc_state =
7709 intel_atomic_get_new_crtc_state(state, crtc);
7710 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7711 enum pipe pipe = crtc->pipe;
7713 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7716 i9xx_set_pll_dividers(new_crtc_state);
7718 if (intel_crtc_has_dp_encoder(new_crtc_state))
7719 intel_dp_set_m_n(new_crtc_state, M1_N1);
7721 intel_set_transcoder_timings(new_crtc_state);
7722 intel_set_pipe_src_size(new_crtc_state);
7724 i9xx_set_pipeconf(new_crtc_state);
7726 crtc->active = true;
7728 if (!IS_GEN(dev_priv, 2))
7729 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7731 intel_encoders_pre_enable(state, crtc);
7733 i9xx_enable_pll(crtc, new_crtc_state);
7735 i9xx_pfit_enable(new_crtc_state);
7737 intel_color_load_luts(new_crtc_state);
7738 intel_color_commit(new_crtc_state);
7739 /* update DSPCNTR to configure gamma for pipe bottom color */
7740 intel_disable_primary_plane(new_crtc_state);
7742 if (dev_priv->display.initial_watermarks)
7743 dev_priv->display.initial_watermarks(state, crtc);
7745 intel_update_watermarks(crtc);
7746 intel_enable_pipe(new_crtc_state);
7748 intel_crtc_vblank_on(new_crtc_state);
7750 intel_encoders_enable(state, crtc);
7752 /* prevents spurious underruns */
7753 if (IS_GEN(dev_priv, 2))
7754 intel_wait_for_vblank(dev_priv, pipe);
7757 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
7759 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
7760 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7762 if (!old_crtc_state->gmch_pfit.control)
7765 assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
7767 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
7768 intel_de_read(dev_priv, PFIT_CONTROL));
7769 intel_de_write(dev_priv, PFIT_CONTROL, 0);
7772 static void i9xx_crtc_disable(struct intel_atomic_state *state,
7773 struct intel_crtc *crtc)
7775 struct intel_crtc_state *old_crtc_state =
7776 intel_atomic_get_old_crtc_state(state, crtc);
7777 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7778 enum pipe pipe = crtc->pipe;
7781 * On gen2 planes are double buffered but the pipe isn't, so we must
7782 * wait for planes to fully turn off before disabling the pipe.
7784 if (IS_GEN(dev_priv, 2))
7785 intel_wait_for_vblank(dev_priv, pipe);
7787 intel_encoders_disable(state, crtc);
7789 intel_crtc_vblank_off(old_crtc_state);
7791 intel_disable_pipe(old_crtc_state);
7793 i9xx_pfit_disable(old_crtc_state);
7795 intel_encoders_post_disable(state, crtc);
7797 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
7798 if (IS_CHERRYVIEW(dev_priv))
7799 chv_disable_pll(dev_priv, pipe);
7800 else if (IS_VALLEYVIEW(dev_priv))
7801 vlv_disable_pll(dev_priv, pipe);
7803 i9xx_disable_pll(old_crtc_state);
7806 intel_encoders_post_pll_disable(state, crtc);
7808 if (!IS_GEN(dev_priv, 2))
7809 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7811 if (!dev_priv->display.initial_watermarks)
7812 intel_update_watermarks(crtc);
7814 /* clock the pipe down to 640x480@60 to potentially save power */
7815 if (IS_I830(dev_priv))
7816 i830_enable_pipe(dev_priv, pipe);
7819 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
7820 struct drm_modeset_acquire_ctx *ctx)
7822 struct intel_encoder *encoder;
7823 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7824 struct intel_bw_state *bw_state =
7825 to_intel_bw_state(dev_priv->bw_obj.state);
7826 struct intel_cdclk_state *cdclk_state =
7827 to_intel_cdclk_state(dev_priv->cdclk.obj.state);
7828 struct intel_dbuf_state *dbuf_state =
7829 to_intel_dbuf_state(dev_priv->dbuf.obj.state);
7830 struct intel_crtc_state *crtc_state =
7831 to_intel_crtc_state(crtc->base.state);
7832 enum intel_display_power_domain domain;
7833 struct intel_plane *plane;
7834 struct drm_atomic_state *state;
7835 struct intel_crtc_state *temp_crtc_state;
7836 enum pipe pipe = crtc->pipe;
7840 if (!crtc_state->hw.active)
7843 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
7844 const struct intel_plane_state *plane_state =
7845 to_intel_plane_state(plane->base.state);
7847 if (plane_state->uapi.visible)
7848 intel_plane_disable_noatomic(crtc, plane);
7851 state = drm_atomic_state_alloc(&dev_priv->drm);
7853 drm_dbg_kms(&dev_priv->drm,
7854 "failed to disable [CRTC:%d:%s], out of memory",
7855 crtc->base.base.id, crtc->base.name);
7859 state->acquire_ctx = ctx;
7861 /* Everything's already locked, -EDEADLK can't happen. */
7862 temp_crtc_state = intel_atomic_get_crtc_state(state, crtc);
7863 ret = drm_atomic_add_affected_connectors(state, &crtc->base);
7865 drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret);
7867 dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc);
7869 drm_atomic_state_put(state);
7871 drm_dbg_kms(&dev_priv->drm,
7872 "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
7873 crtc->base.base.id, crtc->base.name);
7875 crtc->active = false;
7876 crtc->base.enabled = false;
7878 drm_WARN_ON(&dev_priv->drm,
7879 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0);
7880 crtc_state->uapi.active = false;
7881 crtc_state->uapi.connector_mask = 0;
7882 crtc_state->uapi.encoder_mask = 0;
7883 intel_crtc_free_hw_state(crtc_state);
7884 memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));
7886 for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder)
7887 encoder->base.crtc = NULL;
7889 intel_fbc_disable(crtc);
7890 intel_update_watermarks(crtc);
7891 intel_disable_shared_dpll(crtc_state);
7893 domains = crtc->enabled_power_domains;
7894 for_each_power_domain(domain, domains)
7895 intel_display_power_put_unchecked(dev_priv, domain);
7896 crtc->enabled_power_domains = 0;
7898 dev_priv->active_pipes &= ~BIT(pipe);
7899 cdclk_state->min_cdclk[pipe] = 0;
7900 cdclk_state->min_voltage_level[pipe] = 0;
7901 cdclk_state->active_pipes &= ~BIT(pipe);
7903 dbuf_state->active_pipes &= ~BIT(pipe);
7905 bw_state->data_rate[pipe] = 0;
7906 bw_state->num_active_planes[pipe] = 0;
7910 * turn all crtc's off, but do not adjust state
7911 * This has to be paired with a call to intel_modeset_setup_hw_state.
7913 int intel_display_suspend(struct drm_device *dev)
7915 struct drm_i915_private *dev_priv = to_i915(dev);
7916 struct drm_atomic_state *state;
7919 state = drm_atomic_helper_suspend(dev);
7920 ret = PTR_ERR_OR_ZERO(state);
7922 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
7925 dev_priv->modeset_restore_state = state;
7929 void intel_encoder_destroy(struct drm_encoder *encoder)
7931 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
7933 drm_encoder_cleanup(encoder);
7934 kfree(intel_encoder);
7937 /* Cross check the actual hw state with our own modeset state tracking (and it's
7938 * internal consistency). */
7939 static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
7940 struct drm_connector_state *conn_state)
7942 struct intel_connector *connector = to_intel_connector(conn_state->connector);
7943 struct drm_i915_private *i915 = to_i915(connector->base.dev);
7945 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
7946 connector->base.base.id, connector->base.name);
7948 if (connector->get_hw_state(connector)) {
7949 struct intel_encoder *encoder = intel_attached_encoder(connector);
7951 I915_STATE_WARN(!crtc_state,
7952 "connector enabled without attached crtc\n");
7957 I915_STATE_WARN(!crtc_state->hw.active,
7958 "connector is active, but attached crtc isn't\n");
7960 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
7963 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
7964 "atomic encoder doesn't match attached encoder\n");
7966 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
7967 "attached encoder crtc differs from connector crtc\n");
7969 I915_STATE_WARN(crtc_state && crtc_state->hw.active,
7970 "attached crtc is active, but connector isn't\n");
7971 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
7972 "best encoder set without crtc!\n");
7976 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7978 if (crtc_state->hw.enable && crtc_state->has_pch_encoder)
7979 return crtc_state->fdi_lanes;
7984 static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7985 struct intel_crtc_state *pipe_config)
7987 struct drm_i915_private *dev_priv = to_i915(dev);
7988 struct drm_atomic_state *state = pipe_config->uapi.state;
7989 struct intel_crtc *other_crtc;
7990 struct intel_crtc_state *other_crtc_state;
7992 drm_dbg_kms(&dev_priv->drm,
7993 "checking fdi config on pipe %c, lanes %i\n",
7994 pipe_name(pipe), pipe_config->fdi_lanes);
7995 if (pipe_config->fdi_lanes > 4) {
7996 drm_dbg_kms(&dev_priv->drm,
7997 "invalid fdi lane config on pipe %c: %i lanes\n",
7998 pipe_name(pipe), pipe_config->fdi_lanes);
8002 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8003 if (pipe_config->fdi_lanes > 2) {
8004 drm_dbg_kms(&dev_priv->drm,
8005 "only 2 lanes on haswell, required: %i lanes\n",
8006 pipe_config->fdi_lanes);
8013 if (INTEL_NUM_PIPES(dev_priv) == 2)
8016 /* Ivybridge 3 pipe is really complicated */
8021 if (pipe_config->fdi_lanes <= 2)
8024 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
8026 intel_atomic_get_crtc_state(state, other_crtc);
8027 if (IS_ERR(other_crtc_state))
8028 return PTR_ERR(other_crtc_state);
8030 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
8031 drm_dbg_kms(&dev_priv->drm,
8032 "invalid shared fdi lane config on pipe %c: %i lanes\n",
8033 pipe_name(pipe), pipe_config->fdi_lanes);
8038 if (pipe_config->fdi_lanes > 2) {
8039 drm_dbg_kms(&dev_priv->drm,
8040 "only 2 lanes on pipe %c: required %i lanes\n",
8041 pipe_name(pipe), pipe_config->fdi_lanes);
8045 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
8047 intel_atomic_get_crtc_state(state, other_crtc);
8048 if (IS_ERR(other_crtc_state))
8049 return PTR_ERR(other_crtc_state);
8051 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
8052 drm_dbg_kms(&dev_priv->drm,
8053 "fdi link B uses too many lanes to enable link C\n");
8063 static int ilk_fdi_compute_config(struct intel_crtc *intel_crtc,
8064 struct intel_crtc_state *pipe_config)
8066 struct drm_device *dev = intel_crtc->base.dev;
8067 struct drm_i915_private *i915 = to_i915(dev);
8068 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
8069 int lane, link_bw, fdi_dotclock, ret;
8070 bool needs_recompute = false;
8073 /* FDI is a binary signal running at ~2.7GHz, encoding
8074 * each output octet as 10 bits. The actual frequency
8075 * is stored as a divider into a 100MHz clock, and the
8076 * mode pixel clock is stored in units of 1KHz.
8077 * Hence the bw of each lane in terms of the mode signal
8080 link_bw = intel_fdi_link_freq(i915, pipe_config);
8082 fdi_dotclock = adjusted_mode->crtc_clock;
8084 lane = ilk_get_lanes_required(fdi_dotclock, link_bw,
8085 pipe_config->pipe_bpp);
8087 pipe_config->fdi_lanes = lane;
8089 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
8090 link_bw, &pipe_config->fdi_m_n, false, false);
8092 ret = ilk_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
8093 if (ret == -EDEADLK)
8096 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
8097 pipe_config->pipe_bpp -= 2*3;
8098 drm_dbg_kms(&i915->drm,
8099 "fdi link bw constraint, reducing pipe bpp to %i\n",
8100 pipe_config->pipe_bpp);
8101 needs_recompute = true;
8102 pipe_config->bw_constrained = true;
8107 if (needs_recompute)
8113 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
8115 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8116 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8118 /* IPS only exists on ULT machines and is tied to pipe A. */
8119 if (!hsw_crtc_supports_ips(crtc))
8122 if (!dev_priv->params.enable_ips)
8125 if (crtc_state->pipe_bpp > 24)
8129 * We compare against max which means we must take
8130 * the increased cdclk requirement into account when
8131 * calculating the new cdclk.
8133 * Should measure whether using a lower cdclk w/o IPS
8135 if (IS_BROADWELL(dev_priv) &&
8136 crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
8142 static int hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
8144 struct drm_i915_private *dev_priv =
8145 to_i915(crtc_state->uapi.crtc->dev);
8146 struct intel_atomic_state *state =
8147 to_intel_atomic_state(crtc_state->uapi.state);
8149 crtc_state->ips_enabled = false;
8151 if (!hsw_crtc_state_ips_capable(crtc_state))
8155 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
8156 * enabled and disabled dynamically based on package C states,
8157 * user space can't make reliable use of the CRCs, so let's just
8158 * completely disable it.
8160 if (crtc_state->crc_enabled)
8163 /* IPS should be fine as long as at least one plane is enabled. */
8164 if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
8167 if (IS_BROADWELL(dev_priv)) {
8168 const struct intel_cdclk_state *cdclk_state;
8170 cdclk_state = intel_atomic_get_cdclk_state(state);
8171 if (IS_ERR(cdclk_state))
8172 return PTR_ERR(cdclk_state);
8174 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
8175 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
8179 crtc_state->ips_enabled = true;
8184 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
8186 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8188 /* GDG double wide on either pipe, otherwise pipe A only */
8189 return INTEL_GEN(dev_priv) < 4 &&
8190 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
8193 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
8195 u32 pixel_rate = crtc_state->hw.adjusted_mode.crtc_clock;
8196 unsigned int pipe_w, pipe_h, pfit_w, pfit_h;
8199 * We only use IF-ID interlacing. If we ever use
8200 * PF-ID we'll need to adjust the pixel_rate here.
8203 if (!crtc_state->pch_pfit.enabled)
8206 pipe_w = crtc_state->pipe_src_w;
8207 pipe_h = crtc_state->pipe_src_h;
8209 pfit_w = drm_rect_width(&crtc_state->pch_pfit.dst);
8210 pfit_h = drm_rect_height(&crtc_state->pch_pfit.dst);
8212 if (pipe_w < pfit_w)
8214 if (pipe_h < pfit_h)
8217 if (drm_WARN_ON(crtc_state->uapi.crtc->dev,
8218 !pfit_w || !pfit_h))
8221 return div_u64(mul_u32_u32(pixel_rate, pipe_w * pipe_h),
8225 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
8227 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
8229 if (HAS_GMCH(dev_priv))
8230 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
8231 crtc_state->pixel_rate =
8232 crtc_state->hw.adjusted_mode.crtc_clock;
8234 crtc_state->pixel_rate =
8235 ilk_pipe_pixel_rate(crtc_state);
8238 static int intel_crtc_compute_config(struct intel_crtc *crtc,
8239 struct intel_crtc_state *pipe_config)
8241 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8242 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
8243 int clock_limit = dev_priv->max_dotclk_freq;
8245 if (INTEL_GEN(dev_priv) < 4) {
8246 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
8249 * Enable double wide mode when the dot clock
8250 * is > 90% of the (display) core speed.
8252 if (intel_crtc_supports_double_wide(crtc) &&
8253 adjusted_mode->crtc_clock > clock_limit) {
8254 clock_limit = dev_priv->max_dotclk_freq;
8255 pipe_config->double_wide = true;
8259 if (adjusted_mode->crtc_clock > clock_limit) {
8260 drm_dbg_kms(&dev_priv->drm,
8261 "requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
8262 adjusted_mode->crtc_clock, clock_limit,
8263 yesno(pipe_config->double_wide));
8267 if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
8268 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
8269 pipe_config->hw.ctm) {
8271 * There is only one pipe CSC unit per pipe, and we need that
8272 * for output conversion from RGB->YCBCR. So if CTM is already
8273 * applied we can't support YCBCR420 output.
8275 drm_dbg_kms(&dev_priv->drm,
8276 "YCBCR420 and CTM together are not possible\n");
8281 * Pipe horizontal size must be even in:
8283 * - LVDS dual channel mode
8284 * - Double wide pipe
8286 if (pipe_config->pipe_src_w & 1) {
8287 if (pipe_config->double_wide) {
8288 drm_dbg_kms(&dev_priv->drm,
8289 "Odd pipe source width not supported with double wide pipe\n");
8293 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
8294 intel_is_dual_link_lvds(dev_priv)) {
8295 drm_dbg_kms(&dev_priv->drm,
8296 "Odd pipe source width not supported with dual link LVDS\n");
8301 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
8302 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
8304 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
8305 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
8308 intel_crtc_compute_pixel_rate(pipe_config);
8310 if (pipe_config->has_pch_encoder)
8311 return ilk_fdi_compute_config(crtc, pipe_config);
8317 intel_reduce_m_n_ratio(u32 *num, u32 *den)
8319 while (*num > DATA_LINK_M_N_MASK ||
8320 *den > DATA_LINK_M_N_MASK) {
8326 static void compute_m_n(unsigned int m, unsigned int n,
8327 u32 *ret_m, u32 *ret_n,
8331 * Several DP dongles in particular seem to be fussy about
8332 * too large link M/N values. Give N value as 0x8000 that
8333 * should be acceptable by specific devices. 0x8000 is the
8334 * specified fixed N value for asynchronous clock mode,
8335 * which the devices expect also in synchronous clock mode.
8340 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
8342 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
8343 intel_reduce_m_n_ratio(ret_m, ret_n);
8347 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
8348 int pixel_clock, int link_clock,
8349 struct intel_link_m_n *m_n,
8350 bool constant_n, bool fec_enable)
8352 u32 data_clock = bits_per_pixel * pixel_clock;
8355 data_clock = intel_dp_mode_to_fec_clock(data_clock);
8358 compute_m_n(data_clock,
8359 link_clock * nlanes * 8,
8360 &m_n->gmch_m, &m_n->gmch_n,
8363 compute_m_n(pixel_clock, link_clock,
8364 &m_n->link_m, &m_n->link_n,
8368 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
8371 * There may be no VBT; and if the BIOS enabled SSC we can
8372 * just keep using it to avoid unnecessary flicker. Whereas if the
8373 * BIOS isn't using it, don't assume it will work even if the VBT
8374 * indicates as much.
8376 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
8377 bool bios_lvds_use_ssc = intel_de_read(dev_priv,
8381 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
8382 drm_dbg_kms(&dev_priv->drm,
8383 "SSC %s by BIOS, overriding VBT which says %s\n",
8384 enableddisabled(bios_lvds_use_ssc),
8385 enableddisabled(dev_priv->vbt.lvds_use_ssc));
8386 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
8391 static bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
8393 if (dev_priv->params.panel_use_ssc >= 0)
8394 return dev_priv->params.panel_use_ssc != 0;
8395 return dev_priv->vbt.lvds_use_ssc
8396 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
8399 static u32 pnv_dpll_compute_fp(struct dpll *dpll)
8401 return (1 << dpll->n) << 16 | dpll->m2;
8404 static u32 i9xx_dpll_compute_fp(struct dpll *dpll)
8406 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
8409 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
8410 struct intel_crtc_state *crtc_state,
8411 struct dpll *reduced_clock)
8413 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8416 if (IS_PINEVIEW(dev_priv)) {
8417 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
8419 fp2 = pnv_dpll_compute_fp(reduced_clock);
8421 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8423 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8426 crtc_state->dpll_hw_state.fp0 = fp;
8428 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8430 crtc_state->dpll_hw_state.fp1 = fp2;
8432 crtc_state->dpll_hw_state.fp1 = fp;
8436 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
8442 * PLLB opamp always calibrates to max value of 0x3f, force enable it
8443 * and set it to a reasonable value instead.
8445 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
8446 reg_val &= 0xffffff00;
8447 reg_val |= 0x00000030;
8448 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
8450 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
8451 reg_val &= 0x00ffffff;
8452 reg_val |= 0x8c000000;
8453 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
8455 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
8456 reg_val &= 0xffffff00;
8457 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
8459 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
8460 reg_val &= 0x00ffffff;
8461 reg_val |= 0xb0000000;
8462 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
8465 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
8466 const struct intel_link_m_n *m_n)
8468 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8469 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8470 enum pipe pipe = crtc->pipe;
8472 intel_de_write(dev_priv, PCH_TRANS_DATA_M1(pipe),
8473 TU_SIZE(m_n->tu) | m_n->gmch_m);
8474 intel_de_write(dev_priv, PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
8475 intel_de_write(dev_priv, PCH_TRANS_LINK_M1(pipe), m_n->link_m);
8476 intel_de_write(dev_priv, PCH_TRANS_LINK_N1(pipe), m_n->link_n);
8479 static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
8480 enum transcoder transcoder)
8482 if (IS_HASWELL(dev_priv))
8483 return transcoder == TRANSCODER_EDP;
8486 * Strictly speaking some registers are available before
8487 * gen7, but we only support DRRS on gen7+
8489 return IS_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv);
8492 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
8493 const struct intel_link_m_n *m_n,
8494 const struct intel_link_m_n *m2_n2)
8496 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8497 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8498 enum pipe pipe = crtc->pipe;
8499 enum transcoder transcoder = crtc_state->cpu_transcoder;
8501 if (INTEL_GEN(dev_priv) >= 5) {
8502 intel_de_write(dev_priv, PIPE_DATA_M1(transcoder),
8503 TU_SIZE(m_n->tu) | m_n->gmch_m);
8504 intel_de_write(dev_priv, PIPE_DATA_N1(transcoder),
8506 intel_de_write(dev_priv, PIPE_LINK_M1(transcoder),
8508 intel_de_write(dev_priv, PIPE_LINK_N1(transcoder),
8511 * M2_N2 registers are set only if DRRS is supported
8512 * (to make sure the registers are not unnecessarily accessed).
8514 if (m2_n2 && crtc_state->has_drrs &&
8515 transcoder_has_m2_n2(dev_priv, transcoder)) {
8516 intel_de_write(dev_priv, PIPE_DATA_M2(transcoder),
8517 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
8518 intel_de_write(dev_priv, PIPE_DATA_N2(transcoder),
8520 intel_de_write(dev_priv, PIPE_LINK_M2(transcoder),
8522 intel_de_write(dev_priv, PIPE_LINK_N2(transcoder),
8526 intel_de_write(dev_priv, PIPE_DATA_M_G4X(pipe),
8527 TU_SIZE(m_n->tu) | m_n->gmch_m);
8528 intel_de_write(dev_priv, PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
8529 intel_de_write(dev_priv, PIPE_LINK_M_G4X(pipe), m_n->link_m);
8530 intel_de_write(dev_priv, PIPE_LINK_N_G4X(pipe), m_n->link_n);
8534 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
8536 const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
8537 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
8540 dp_m_n = &crtc_state->dp_m_n;
8541 dp_m2_n2 = &crtc_state->dp_m2_n2;
8542 } else if (m_n == M2_N2) {
8545 * M2_N2 registers are not supported. Hence m2_n2 divider value
8546 * needs to be programmed into M1_N1.
8548 dp_m_n = &crtc_state->dp_m2_n2;
8550 drm_err(&i915->drm, "Unsupported divider value\n");
8554 if (crtc_state->has_pch_encoder)
8555 intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);
8557 intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
8560 static void vlv_compute_dpll(struct intel_crtc *crtc,
8561 struct intel_crtc_state *pipe_config)
8563 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
8564 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
8565 if (crtc->pipe != PIPE_A)
8566 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
8568 /* DPLL not used with DSI, but still need the rest set up */
8569 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
8570 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
8571 DPLL_EXT_BUFFER_ENABLE_VLV;
8573 pipe_config->dpll_hw_state.dpll_md =
8574 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8577 static void chv_compute_dpll(struct intel_crtc *crtc,
8578 struct intel_crtc_state *pipe_config)
8580 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
8581 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
8582 if (crtc->pipe != PIPE_A)
8583 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
8585 /* DPLL not used with DSI, but still need the rest set up */
8586 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
8587 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
8589 pipe_config->dpll_hw_state.dpll_md =
8590 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8593 static void vlv_prepare_pll(struct intel_crtc *crtc,
8594 const struct intel_crtc_state *pipe_config)
8596 struct drm_device *dev = crtc->base.dev;
8597 struct drm_i915_private *dev_priv = to_i915(dev);
8598 enum pipe pipe = crtc->pipe;
8600 u32 bestn, bestm1, bestm2, bestp1, bestp2;
8601 u32 coreclk, reg_val;
8604 intel_de_write(dev_priv, DPLL(pipe),
8605 pipe_config->dpll_hw_state.dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
8607 /* No need to actually set up the DPLL with DSI */
8608 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8611 vlv_dpio_get(dev_priv);
8613 bestn = pipe_config->dpll.n;
8614 bestm1 = pipe_config->dpll.m1;
8615 bestm2 = pipe_config->dpll.m2;
8616 bestp1 = pipe_config->dpll.p1;
8617 bestp2 = pipe_config->dpll.p2;
8619 /* See eDP HDMI DPIO driver vbios notes doc */
8621 /* PLL B needs special handling */
8623 vlv_pllb_recal_opamp(dev_priv, pipe);
8625 /* Set up Tx target for periodic Rcomp update */
8626 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
8628 /* Disable target IRef on PLL */
8629 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
8630 reg_val &= 0x00ffffff;
8631 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
8633 /* Disable fast lock */
8634 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
8636 /* Set idtafcrecal before PLL is enabled */
8637 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
8638 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
8639 mdiv |= ((bestn << DPIO_N_SHIFT));
8640 mdiv |= (1 << DPIO_K_SHIFT);
8643 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
8644 * but we don't support that).
8645 * Note: don't use the DAC post divider as it seems unstable.
8647 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
8648 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
8650 mdiv |= DPIO_ENABLE_CALIBRATION;
8651 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
8653 /* Set HBR and RBR LPF coefficients */
8654 if (pipe_config->port_clock == 162000 ||
8655 intel_crtc_has_type(pipe_config, INTEL_OUTPUT_ANALOG) ||
8656 intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
8657 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
8660 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
8663 if (intel_crtc_has_dp_encoder(pipe_config)) {
8664 /* Use SSC source */
8666 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8669 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8671 } else { /* HDMI or VGA */
8672 /* Use bend source */
8674 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8677 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8681 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
8682 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
8683 if (intel_crtc_has_dp_encoder(pipe_config))
8684 coreclk |= 0x01000000;
8685 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
8687 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
8689 vlv_dpio_put(dev_priv);
8692 static void chv_prepare_pll(struct intel_crtc *crtc,
8693 const struct intel_crtc_state *pipe_config)
8695 struct drm_device *dev = crtc->base.dev;
8696 struct drm_i915_private *dev_priv = to_i915(dev);
8697 enum pipe pipe = crtc->pipe;
8698 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8699 u32 loopfilter, tribuf_calcntr;
8700 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
8704 /* Enable Refclk and SSC */
8705 intel_de_write(dev_priv, DPLL(pipe),
8706 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
8708 /* No need to actually set up the DPLL with DSI */
8709 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8712 bestn = pipe_config->dpll.n;
8713 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
8714 bestm1 = pipe_config->dpll.m1;
8715 bestm2 = pipe_config->dpll.m2 >> 22;
8716 bestp1 = pipe_config->dpll.p1;
8717 bestp2 = pipe_config->dpll.p2;
8718 vco = pipe_config->dpll.vco;
8722 vlv_dpio_get(dev_priv);
8724 /* p1 and p2 divider */
8725 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
8726 5 << DPIO_CHV_S1_DIV_SHIFT |
8727 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
8728 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
8729 1 << DPIO_CHV_K_DIV_SHIFT);
8731 /* Feedback post-divider - m2 */
8732 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
8734 /* Feedback refclk divider - n and m1 */
8735 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8736 DPIO_CHV_M1_DIV_BY_2 |
8737 1 << DPIO_CHV_N_DIV_SHIFT);
8739 /* M2 fraction division */
8740 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8742 /* M2 fraction division enable */
8743 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8744 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8745 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8747 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8748 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8750 /* Program digital lock detect threshold */
8751 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8752 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8753 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8754 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8756 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8757 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8760 if (vco == 5400000) {
8761 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8762 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8763 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8764 tribuf_calcntr = 0x9;
8765 } else if (vco <= 6200000) {
8766 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8767 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8768 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8769 tribuf_calcntr = 0x9;
8770 } else if (vco <= 6480000) {
8771 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8772 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8773 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8774 tribuf_calcntr = 0x8;
8776 /* Not supported. Apply the same limits as in the max case */
8777 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8778 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8779 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8782 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8784 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8785 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8786 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8787 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8790 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8791 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8794 vlv_dpio_put(dev_priv);
8798 * vlv_force_pll_on - forcibly enable just the PLL
8799 * @dev_priv: i915 private structure
8800 * @pipe: pipe PLL to enable
8801 * @dpll: PLL configuration
8803 * Enable the PLL for @pipe using the supplied @dpll config. To be used
8804 * in cases where we need the PLL enabled even when @pipe is not going to
8807 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
8808 const struct dpll *dpll)
8810 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
8811 struct intel_crtc_state *pipe_config;
8813 pipe_config = intel_crtc_state_alloc(crtc);
8817 pipe_config->cpu_transcoder = (enum transcoder)pipe;
8818 pipe_config->pixel_multiplier = 1;
8819 pipe_config->dpll = *dpll;
8821 if (IS_CHERRYVIEW(dev_priv)) {
8822 chv_compute_dpll(crtc, pipe_config);
8823 chv_prepare_pll(crtc, pipe_config);
8824 chv_enable_pll(crtc, pipe_config);
8826 vlv_compute_dpll(crtc, pipe_config);
8827 vlv_prepare_pll(crtc, pipe_config);
8828 vlv_enable_pll(crtc, pipe_config);
8837 * vlv_force_pll_off - forcibly disable just the PLL
8838 * @dev_priv: i915 private structure
8839 * @pipe: pipe PLL to disable
8841 * Disable the PLL for @pipe. To be used in cases where we need
8842 * the PLL enabled even when @pipe is not going to be enabled.
8844 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
8846 if (IS_CHERRYVIEW(dev_priv))
8847 chv_disable_pll(dev_priv, pipe);
8849 vlv_disable_pll(dev_priv, pipe);
8852 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8853 struct intel_crtc_state *crtc_state,
8854 struct dpll *reduced_clock)
8856 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8858 struct dpll *clock = &crtc_state->dpll;
8860 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8862 dpll = DPLL_VGA_MODE_DIS;
8864 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8865 dpll |= DPLLB_MODE_LVDS;
8867 dpll |= DPLLB_MODE_DAC_SERIAL;
8869 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8870 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8871 dpll |= (crtc_state->pixel_multiplier - 1)
8872 << SDVO_MULTIPLIER_SHIFT_HIRES;
8875 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8876 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8877 dpll |= DPLL_SDVO_HIGH_SPEED;
8879 if (intel_crtc_has_dp_encoder(crtc_state))
8880 dpll |= DPLL_SDVO_HIGH_SPEED;
8882 /* compute bitmask from p1 value */
8883 if (IS_PINEVIEW(dev_priv))
8884 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8886 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8887 if (IS_G4X(dev_priv) && reduced_clock)
8888 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8890 switch (clock->p2) {
8892 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8895 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8898 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8901 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8904 if (INTEL_GEN(dev_priv) >= 4)
8905 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8907 if (crtc_state->sdvo_tv_clock)
8908 dpll |= PLL_REF_INPUT_TVCLKINBC;
8909 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8910 intel_panel_use_ssc(dev_priv))
8911 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8913 dpll |= PLL_REF_INPUT_DREFCLK;
8915 dpll |= DPLL_VCO_ENABLE;
8916 crtc_state->dpll_hw_state.dpll = dpll;
8918 if (INTEL_GEN(dev_priv) >= 4) {
8919 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8920 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8921 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8925 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8926 struct intel_crtc_state *crtc_state,
8927 struct dpll *reduced_clock)
8929 struct drm_device *dev = crtc->base.dev;
8930 struct drm_i915_private *dev_priv = to_i915(dev);
8932 struct dpll *clock = &crtc_state->dpll;
8934 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8936 dpll = DPLL_VGA_MODE_DIS;
8938 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8939 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8942 dpll |= PLL_P1_DIVIDE_BY_TWO;
8944 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8946 dpll |= PLL_P2_DIVIDE_BY_4;
8951 * "[Almador Errata}: For the correct operation of the muxed DVO pins
8952 * (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
8953 * GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
8954 * Enable) must be set to “1” in both the DPLL A Control Register
8955 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
8957 * For simplicity We simply keep both bits always enabled in
8958 * both DPLLS. The spec says we should disable the DVO 2X clock
8959 * when not needed, but this seems to work fine in practice.
8961 if (IS_I830(dev_priv) ||
8962 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8963 dpll |= DPLL_DVO_2X_MODE;
8965 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8966 intel_panel_use_ssc(dev_priv))
8967 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8969 dpll |= PLL_REF_INPUT_DREFCLK;
8971 dpll |= DPLL_VCO_ENABLE;
8972 crtc_state->dpll_hw_state.dpll = dpll;
8975 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
8977 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8978 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8979 enum pipe pipe = crtc->pipe;
8980 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8981 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
8982 u32 crtc_vtotal, crtc_vblank_end;
8985 /* We need to be careful not to changed the adjusted mode, for otherwise
8986 * the hw state checker will get angry at the mismatch. */
8987 crtc_vtotal = adjusted_mode->crtc_vtotal;
8988 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8990 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8991 /* the chip adds 2 halflines automatically */
8993 crtc_vblank_end -= 1;
8995 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
8996 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8998 vsyncshift = adjusted_mode->crtc_hsync_start -
8999 adjusted_mode->crtc_htotal / 2;
9001 vsyncshift += adjusted_mode->crtc_htotal;
9004 if (INTEL_GEN(dev_priv) > 3)
9005 intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder),
9008 intel_de_write(dev_priv, HTOTAL(cpu_transcoder),
9009 (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16));
9010 intel_de_write(dev_priv, HBLANK(cpu_transcoder),
9011 (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
9012 intel_de_write(dev_priv, HSYNC(cpu_transcoder),
9013 (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
9015 intel_de_write(dev_priv, VTOTAL(cpu_transcoder),
9016 (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16));
9017 intel_de_write(dev_priv, VBLANK(cpu_transcoder),
9018 (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16));
9019 intel_de_write(dev_priv, VSYNC(cpu_transcoder),
9020 (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
9022 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
9023 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
9024 * documented on the DDI_FUNC_CTL register description, EDP Input Select
9026 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
9027 (pipe == PIPE_B || pipe == PIPE_C))
9028 intel_de_write(dev_priv, VTOTAL(pipe),
9029 intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
9033 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
9035 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9036 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9037 enum pipe pipe = crtc->pipe;
9039 /* pipesrc controls the size that is scaled from, which should
9040 * always be the user's requested size.
9042 intel_de_write(dev_priv, PIPESRC(pipe),
9043 ((crtc_state->pipe_src_w - 1) << 16) | (crtc_state->pipe_src_h - 1));
9046 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
9048 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
9049 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
9051 if (IS_GEN(dev_priv, 2))
9054 if (INTEL_GEN(dev_priv) >= 9 ||
9055 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
9056 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW;
9058 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
9061 static void intel_get_transcoder_timings(struct intel_crtc *crtc,
9062 struct intel_crtc_state *pipe_config)
9064 struct drm_device *dev = crtc->base.dev;
9065 struct drm_i915_private *dev_priv = to_i915(dev);
9066 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
9069 tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder));
9070 pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
9071 pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
9073 if (!transcoder_is_dsi(cpu_transcoder)) {
9074 tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder));
9075 pipe_config->hw.adjusted_mode.crtc_hblank_start =
9077 pipe_config->hw.adjusted_mode.crtc_hblank_end =
9078 ((tmp >> 16) & 0xffff) + 1;
9080 tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder));
9081 pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
9082 pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
9084 tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder));
9085 pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
9086 pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
9088 if (!transcoder_is_dsi(cpu_transcoder)) {
9089 tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder));
9090 pipe_config->hw.adjusted_mode.crtc_vblank_start =
9092 pipe_config->hw.adjusted_mode.crtc_vblank_end =
9093 ((tmp >> 16) & 0xffff) + 1;
9095 tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder));
9096 pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
9097 pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
9099 if (intel_pipe_is_interlaced(pipe_config)) {
9100 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
9101 pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
9102 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
9106 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
9107 struct intel_crtc_state *pipe_config)
9109 struct drm_device *dev = crtc->base.dev;
9110 struct drm_i915_private *dev_priv = to_i915(dev);
9113 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
9114 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
9115 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
9117 pipe_config->hw.mode.vdisplay = pipe_config->pipe_src_h;
9118 pipe_config->hw.mode.hdisplay = pipe_config->pipe_src_w;
9121 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
9122 struct intel_crtc_state *pipe_config)
9124 mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay;
9125 mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal;
9126 mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start;
9127 mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end;
9129 mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay;
9130 mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal;
9131 mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start;
9132 mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end;
9134 mode->flags = pipe_config->hw.adjusted_mode.flags;
9135 mode->type = DRM_MODE_TYPE_DRIVER;
9137 mode->clock = pipe_config->hw.adjusted_mode.crtc_clock;
9139 drm_mode_set_name(mode);
9142 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
9144 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9145 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9150 /* we keep both pipes enabled on 830 */
9151 if (IS_I830(dev_priv))
9152 pipeconf |= intel_de_read(dev_priv, PIPECONF(crtc->pipe)) & PIPECONF_ENABLE;
9154 if (crtc_state->double_wide)
9155 pipeconf |= PIPECONF_DOUBLE_WIDE;
9157 /* only g4x and later have fancy bpc/dither controls */
9158 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
9159 IS_CHERRYVIEW(dev_priv)) {
9160 /* Bspec claims that we can't use dithering for 30bpp pipes. */
9161 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
9162 pipeconf |= PIPECONF_DITHER_EN |
9163 PIPECONF_DITHER_TYPE_SP;
9165 switch (crtc_state->pipe_bpp) {
9167 pipeconf |= PIPECONF_6BPC;
9170 pipeconf |= PIPECONF_8BPC;
9173 pipeconf |= PIPECONF_10BPC;
9176 /* Case prevented by intel_choose_pipe_bpp_dither. */
9181 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
9182 if (INTEL_GEN(dev_priv) < 4 ||
9183 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
9184 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
9186 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
9188 pipeconf |= PIPECONF_PROGRESSIVE;
9191 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
9192 crtc_state->limited_color_range)
9193 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9195 pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
9197 pipeconf |= PIPECONF_FRAME_START_DELAY(0);
9199 intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf);
9200 intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe));
9203 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
9204 struct intel_crtc_state *crtc_state)
9206 struct drm_device *dev = crtc->base.dev;
9207 struct drm_i915_private *dev_priv = to_i915(dev);
9208 const struct intel_limit *limit;
9211 memset(&crtc_state->dpll_hw_state, 0,
9212 sizeof(crtc_state->dpll_hw_state));
9214 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9215 if (intel_panel_use_ssc(dev_priv)) {
9216 refclk = dev_priv->vbt.lvds_ssc_freq;
9217 drm_dbg_kms(&dev_priv->drm,
9218 "using SSC reference clock of %d kHz\n",
9222 limit = &intel_limits_i8xx_lvds;
9223 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
9224 limit = &intel_limits_i8xx_dvo;
9226 limit = &intel_limits_i8xx_dac;
9229 if (!crtc_state->clock_set &&
9230 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9231 refclk, NULL, &crtc_state->dpll)) {
9232 drm_err(&dev_priv->drm,
9233 "Couldn't find PLL settings for mode!\n");
9237 i8xx_compute_dpll(crtc, crtc_state, NULL);
9242 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
9243 struct intel_crtc_state *crtc_state)
9245 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9246 const struct intel_limit *limit;
9249 memset(&crtc_state->dpll_hw_state, 0,
9250 sizeof(crtc_state->dpll_hw_state));
9252 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9253 if (intel_panel_use_ssc(dev_priv)) {
9254 refclk = dev_priv->vbt.lvds_ssc_freq;
9255 drm_dbg_kms(&dev_priv->drm,
9256 "using SSC reference clock of %d kHz\n",
9260 if (intel_is_dual_link_lvds(dev_priv))
9261 limit = &intel_limits_g4x_dual_channel_lvds;
9263 limit = &intel_limits_g4x_single_channel_lvds;
9264 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
9265 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
9266 limit = &intel_limits_g4x_hdmi;
9267 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
9268 limit = &intel_limits_g4x_sdvo;
9270 /* The option is for other outputs */
9271 limit = &intel_limits_i9xx_sdvo;
9274 if (!crtc_state->clock_set &&
9275 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9276 refclk, NULL, &crtc_state->dpll)) {
9277 drm_err(&dev_priv->drm,
9278 "Couldn't find PLL settings for mode!\n");
9282 i9xx_compute_dpll(crtc, crtc_state, NULL);
9287 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
9288 struct intel_crtc_state *crtc_state)
9290 struct drm_device *dev = crtc->base.dev;
9291 struct drm_i915_private *dev_priv = to_i915(dev);
9292 const struct intel_limit *limit;
9295 memset(&crtc_state->dpll_hw_state, 0,
9296 sizeof(crtc_state->dpll_hw_state));
9298 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9299 if (intel_panel_use_ssc(dev_priv)) {
9300 refclk = dev_priv->vbt.lvds_ssc_freq;
9301 drm_dbg_kms(&dev_priv->drm,
9302 "using SSC reference clock of %d kHz\n",
9306 limit = &pnv_limits_lvds;
9308 limit = &pnv_limits_sdvo;
9311 if (!crtc_state->clock_set &&
9312 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9313 refclk, NULL, &crtc_state->dpll)) {
9314 drm_err(&dev_priv->drm,
9315 "Couldn't find PLL settings for mode!\n");
9319 i9xx_compute_dpll(crtc, crtc_state, NULL);
9324 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
9325 struct intel_crtc_state *crtc_state)
9327 struct drm_device *dev = crtc->base.dev;
9328 struct drm_i915_private *dev_priv = to_i915(dev);
9329 const struct intel_limit *limit;
9332 memset(&crtc_state->dpll_hw_state, 0,
9333 sizeof(crtc_state->dpll_hw_state));
9335 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9336 if (intel_panel_use_ssc(dev_priv)) {
9337 refclk = dev_priv->vbt.lvds_ssc_freq;
9338 drm_dbg_kms(&dev_priv->drm,
9339 "using SSC reference clock of %d kHz\n",
9343 limit = &intel_limits_i9xx_lvds;
9345 limit = &intel_limits_i9xx_sdvo;
9348 if (!crtc_state->clock_set &&
9349 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9350 refclk, NULL, &crtc_state->dpll)) {
9351 drm_err(&dev_priv->drm,
9352 "Couldn't find PLL settings for mode!\n");
9356 i9xx_compute_dpll(crtc, crtc_state, NULL);
9361 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
9362 struct intel_crtc_state *crtc_state)
9364 int refclk = 100000;
9365 const struct intel_limit *limit = &intel_limits_chv;
9366 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
9368 memset(&crtc_state->dpll_hw_state, 0,
9369 sizeof(crtc_state->dpll_hw_state));
9371 if (!crtc_state->clock_set &&
9372 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9373 refclk, NULL, &crtc_state->dpll)) {
9374 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n");
9378 chv_compute_dpll(crtc, crtc_state);
9383 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
9384 struct intel_crtc_state *crtc_state)
9386 int refclk = 100000;
9387 const struct intel_limit *limit = &intel_limits_vlv;
9388 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
9390 memset(&crtc_state->dpll_hw_state, 0,
9391 sizeof(crtc_state->dpll_hw_state));
9393 if (!crtc_state->clock_set &&
9394 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9395 refclk, NULL, &crtc_state->dpll)) {
9396 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n");
9400 vlv_compute_dpll(crtc, crtc_state);
9405 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
9407 if (IS_I830(dev_priv))
9410 return INTEL_GEN(dev_priv) >= 4 ||
9411 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
9414 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
9416 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9417 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9420 if (!i9xx_has_pfit(dev_priv))
9423 tmp = intel_de_read(dev_priv, PFIT_CONTROL);
9424 if (!(tmp & PFIT_ENABLE))
9427 /* Check whether the pfit is attached to our pipe. */
9428 if (INTEL_GEN(dev_priv) < 4) {
9429 if (crtc->pipe != PIPE_B)
9432 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
9436 crtc_state->gmch_pfit.control = tmp;
9437 crtc_state->gmch_pfit.pgm_ratios =
9438 intel_de_read(dev_priv, PFIT_PGM_RATIOS);
9441 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
9442 struct intel_crtc_state *pipe_config)
9444 struct drm_device *dev = crtc->base.dev;
9445 struct drm_i915_private *dev_priv = to_i915(dev);
9446 enum pipe pipe = crtc->pipe;
9449 int refclk = 100000;
9451 /* In case of DSI, DPLL will not be used */
9452 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
9455 vlv_dpio_get(dev_priv);
9456 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
9457 vlv_dpio_put(dev_priv);
9459 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
9460 clock.m2 = mdiv & DPIO_M2DIV_MASK;
9461 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
9462 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
9463 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
9465 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
9469 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
9470 struct intel_initial_plane_config *plane_config)
9472 struct drm_device *dev = crtc->base.dev;
9473 struct drm_i915_private *dev_priv = to_i915(dev);
9474 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
9475 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
9477 u32 val, base, offset;
9478 int fourcc, pixel_format;
9479 unsigned int aligned_height;
9480 struct drm_framebuffer *fb;
9481 struct intel_framebuffer *intel_fb;
9483 if (!plane->get_hw_state(plane, &pipe))
9486 drm_WARN_ON(dev, pipe != crtc->pipe);
9488 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9490 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
9494 fb = &intel_fb->base;
9498 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
9500 if (INTEL_GEN(dev_priv) >= 4) {
9501 if (val & DISPPLANE_TILED) {
9502 plane_config->tiling = I915_TILING_X;
9503 fb->modifier = I915_FORMAT_MOD_X_TILED;
9506 if (val & DISPPLANE_ROTATE_180)
9507 plane_config->rotation = DRM_MODE_ROTATE_180;
9510 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
9511 val & DISPPLANE_MIRROR)
9512 plane_config->rotation |= DRM_MODE_REFLECT_X;
9514 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9515 fourcc = i9xx_format_to_fourcc(pixel_format);
9516 fb->format = drm_format_info(fourcc);
9518 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
9519 offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));
9520 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
9521 } else if (INTEL_GEN(dev_priv) >= 4) {
9522 if (plane_config->tiling)
9523 offset = intel_de_read(dev_priv,
9524 DSPTILEOFF(i9xx_plane));
9526 offset = intel_de_read(dev_priv,
9527 DSPLINOFF(i9xx_plane));
9528 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
9530 base = intel_de_read(dev_priv, DSPADDR(i9xx_plane));
9532 plane_config->base = base;
9534 val = intel_de_read(dev_priv, PIPESRC(pipe));
9535 fb->width = ((val >> 16) & 0xfff) + 1;
9536 fb->height = ((val >> 0) & 0xfff) + 1;
9538 val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane));
9539 fb->pitches[0] = val & 0xffffffc0;
9541 aligned_height = intel_fb_align_height(fb, 0, fb->height);
9543 plane_config->size = fb->pitches[0] * aligned_height;
9545 drm_dbg_kms(&dev_priv->drm,
9546 "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9547 crtc->base.name, plane->base.name, fb->width, fb->height,
9548 fb->format->cpp[0] * 8, base, fb->pitches[0],
9549 plane_config->size);
9551 plane_config->fb = intel_fb;
9554 static void chv_crtc_clock_get(struct intel_crtc *crtc,
9555 struct intel_crtc_state *pipe_config)
9557 struct drm_device *dev = crtc->base.dev;
9558 struct drm_i915_private *dev_priv = to_i915(dev);
9559 enum pipe pipe = crtc->pipe;
9560 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9562 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
9563 int refclk = 100000;
9565 /* In case of DSI, DPLL will not be used */
9566 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
9569 vlv_dpio_get(dev_priv);
9570 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
9571 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
9572 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
9573 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
9574 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
9575 vlv_dpio_put(dev_priv);
9577 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
9578 clock.m2 = (pll_dw0 & 0xff) << 22;
9579 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
9580 clock.m2 |= pll_dw2 & 0x3fffff;
9581 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
9582 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
9583 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
9585 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
9588 static enum intel_output_format
9589 bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
9591 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9594 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
9596 if (tmp & PIPEMISC_YUV420_ENABLE) {
9597 /* We support 4:2:0 in full blend mode only */
9598 drm_WARN_ON(&dev_priv->drm,
9599 (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0);
9601 return INTEL_OUTPUT_FORMAT_YCBCR420;
9602 } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
9603 return INTEL_OUTPUT_FORMAT_YCBCR444;
9605 return INTEL_OUTPUT_FORMAT_RGB;
9609 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
9611 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9612 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
9613 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9614 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
9617 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
9619 if (tmp & DISPPLANE_GAMMA_ENABLE)
9620 crtc_state->gamma_enable = true;
9622 if (!HAS_GMCH(dev_priv) &&
9623 tmp & DISPPLANE_PIPE_CSC_ENABLE)
9624 crtc_state->csc_enable = true;
9627 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
9628 struct intel_crtc_state *pipe_config)
9630 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9631 enum intel_display_power_domain power_domain;
9632 intel_wakeref_t wakeref;
9636 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9637 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
9641 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
9642 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9643 pipe_config->shared_dpll = NULL;
9647 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
9648 if (!(tmp & PIPECONF_ENABLE))
9651 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
9652 IS_CHERRYVIEW(dev_priv)) {
9653 switch (tmp & PIPECONF_BPC_MASK) {
9655 pipe_config->pipe_bpp = 18;
9658 pipe_config->pipe_bpp = 24;
9660 case PIPECONF_10BPC:
9661 pipe_config->pipe_bpp = 30;
9668 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
9669 (tmp & PIPECONF_COLOR_RANGE_SELECT))
9670 pipe_config->limited_color_range = true;
9672 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
9673 PIPECONF_GAMMA_MODE_SHIFT;
9675 if (IS_CHERRYVIEW(dev_priv))
9676 pipe_config->cgm_mode = intel_de_read(dev_priv,
9677 CGM_PIPE_MODE(crtc->pipe));
9679 i9xx_get_pipe_color_config(pipe_config);
9680 intel_color_get_config(pipe_config);
9682 if (INTEL_GEN(dev_priv) < 4)
9683 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
9685 intel_get_transcoder_timings(crtc, pipe_config);
9686 intel_get_pipe_src_size(crtc, pipe_config);
9688 i9xx_get_pfit_config(pipe_config);
9690 if (INTEL_GEN(dev_priv) >= 4) {
9691 /* No way to read it out on pipes B and C */
9692 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
9693 tmp = dev_priv->chv_dpll_md[crtc->pipe];
9695 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
9696 pipe_config->pixel_multiplier =
9697 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
9698 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
9699 pipe_config->dpll_hw_state.dpll_md = tmp;
9700 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
9701 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
9702 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe));
9703 pipe_config->pixel_multiplier =
9704 ((tmp & SDVO_MULTIPLIER_MASK)
9705 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
9707 /* Note that on i915G/GM the pixel multiplier is in the sdvo
9708 * port and will be fixed up in the encoder->get_config
9710 pipe_config->pixel_multiplier = 1;
9712 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv,
9714 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
9715 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv,
9717 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv,
9720 /* Mask out read-only status bits. */
9721 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
9722 DPLL_PORTC_READY_MASK |
9723 DPLL_PORTB_READY_MASK);
9726 if (IS_CHERRYVIEW(dev_priv))
9727 chv_crtc_clock_get(crtc, pipe_config);
9728 else if (IS_VALLEYVIEW(dev_priv))
9729 vlv_crtc_clock_get(crtc, pipe_config);
9731 i9xx_crtc_clock_get(crtc, pipe_config);
9734 * Normally the dotclock is filled in by the encoder .get_config()
9735 * but in case the pipe is enabled w/o any ports we need a sane
9738 pipe_config->hw.adjusted_mode.crtc_clock =
9739 pipe_config->port_clock / pipe_config->pixel_multiplier;
9744 intel_display_power_put(dev_priv, power_domain, wakeref);
9749 static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
9751 struct intel_encoder *encoder;
9754 bool has_lvds = false;
9755 bool has_cpu_edp = false;
9756 bool has_panel = false;
9757 bool has_ck505 = false;
9758 bool can_ssc = false;
9759 bool using_ssc_source = false;
9761 /* We need to take the global config into account */
9762 for_each_intel_encoder(&dev_priv->drm, encoder) {
9763 switch (encoder->type) {
9764 case INTEL_OUTPUT_LVDS:
9768 case INTEL_OUTPUT_EDP:
9770 if (encoder->port == PORT_A)
9778 if (HAS_PCH_IBX(dev_priv)) {
9779 has_ck505 = dev_priv->vbt.display_clock_mode;
9780 can_ssc = has_ck505;
9786 /* Check if any DPLLs are using the SSC source */
9787 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
9788 u32 temp = intel_de_read(dev_priv, PCH_DPLL(i));
9790 if (!(temp & DPLL_VCO_ENABLE))
9793 if ((temp & PLL_REF_INPUT_MASK) ==
9794 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
9795 using_ssc_source = true;
9800 drm_dbg_kms(&dev_priv->drm,
9801 "has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
9802 has_panel, has_lvds, has_ck505, using_ssc_source);
9804 /* Ironlake: try to setup display ref clock before DPLL
9805 * enabling. This is only under driver's control after
9806 * PCH B stepping, previous chipset stepping should be
9807 * ignoring this setting.
9809 val = intel_de_read(dev_priv, PCH_DREF_CONTROL);
9811 /* As we must carefully and slowly disable/enable each source in turn,
9812 * compute the final state we want first and check if we need to
9813 * make any changes at all.
9816 final &= ~DREF_NONSPREAD_SOURCE_MASK;
9818 final |= DREF_NONSPREAD_CK505_ENABLE;
9820 final |= DREF_NONSPREAD_SOURCE_ENABLE;
9822 final &= ~DREF_SSC_SOURCE_MASK;
9823 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9824 final &= ~DREF_SSC1_ENABLE;
9827 final |= DREF_SSC_SOURCE_ENABLE;
9829 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9830 final |= DREF_SSC1_ENABLE;
9833 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9834 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9836 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9838 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9839 } else if (using_ssc_source) {
9840 final |= DREF_SSC_SOURCE_ENABLE;
9841 final |= DREF_SSC1_ENABLE;
9847 /* Always enable nonspread source */
9848 val &= ~DREF_NONSPREAD_SOURCE_MASK;
9851 val |= DREF_NONSPREAD_CK505_ENABLE;
9853 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9856 val &= ~DREF_SSC_SOURCE_MASK;
9857 val |= DREF_SSC_SOURCE_ENABLE;
9859 /* SSC must be turned on before enabling the CPU output */
9860 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9861 drm_dbg_kms(&dev_priv->drm, "Using SSC on panel\n");
9862 val |= DREF_SSC1_ENABLE;
9864 val &= ~DREF_SSC1_ENABLE;
9866 /* Get SSC going before enabling the outputs */
9867 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9868 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9871 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9873 /* Enable CPU source on CPU attached eDP */
9875 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9876 drm_dbg_kms(&dev_priv->drm,
9877 "Using SSC on eDP\n");
9878 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9880 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9882 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9884 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9885 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9888 drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n");
9890 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9892 /* Turn off CPU output */
9893 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9895 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9896 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9899 if (!using_ssc_source) {
9900 drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n");
9902 /* Turn off the SSC source */
9903 val &= ~DREF_SSC_SOURCE_MASK;
9904 val |= DREF_SSC_SOURCE_DISABLE;
9907 val &= ~DREF_SSC1_ENABLE;
9909 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9910 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9915 BUG_ON(val != final);
9918 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9922 tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
9923 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9924 intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
9926 if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) &
9927 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9928 drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n");
9930 tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
9931 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9932 intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
9934 if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) &
9935 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9936 drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n");
9939 /* WaMPhyProgramming:hsw */
9940 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9944 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9945 tmp &= ~(0xFF << 24);
9946 tmp |= (0x12 << 24);
9947 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9949 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9951 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9953 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9955 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9957 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9958 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9959 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9961 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9962 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9963 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9965 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9968 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9970 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9973 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9975 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9978 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9980 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9983 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9985 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9986 tmp &= ~(0xFF << 16);
9987 tmp |= (0x1C << 16);
9988 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9990 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9991 tmp &= ~(0xFF << 16);
9992 tmp |= (0x1C << 16);
9993 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9995 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9997 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9999 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
10001 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
10003 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
10004 tmp &= ~(0xF << 28);
10006 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
10008 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
10009 tmp &= ~(0xF << 28);
10011 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
10014 /* Implements 3 different sequences from BSpec chapter "Display iCLK
10015 * Programming" based on the parameters passed:
10016 * - Sequence to enable CLKOUT_DP
10017 * - Sequence to enable CLKOUT_DP without spread
10018 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
10020 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
10021 bool with_spread, bool with_fdi)
10025 if (drm_WARN(&dev_priv->drm, with_fdi && !with_spread,
10026 "FDI requires downspread\n"))
10027 with_spread = true;
10028 if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) &&
10029 with_fdi, "LP PCH doesn't have FDI\n"))
10032 mutex_lock(&dev_priv->sb_lock);
10034 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
10035 tmp &= ~SBI_SSCCTL_DISABLE;
10036 tmp |= SBI_SSCCTL_PATHALT;
10037 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
10042 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
10043 tmp &= ~SBI_SSCCTL_PATHALT;
10044 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
10047 lpt_reset_fdi_mphy(dev_priv);
10048 lpt_program_fdi_mphy(dev_priv);
10052 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
10053 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
10054 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
10055 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
10057 mutex_unlock(&dev_priv->sb_lock);
10060 /* Sequence to disable CLKOUT_DP */
10061 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
10065 mutex_lock(&dev_priv->sb_lock);
10067 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
10068 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
10069 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
10070 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
10072 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
10073 if (!(tmp & SBI_SSCCTL_DISABLE)) {
10074 if (!(tmp & SBI_SSCCTL_PATHALT)) {
10075 tmp |= SBI_SSCCTL_PATHALT;
10076 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
10079 tmp |= SBI_SSCCTL_DISABLE;
10080 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
10083 mutex_unlock(&dev_priv->sb_lock);
10086 #define BEND_IDX(steps) ((50 + (steps)) / 5)
10088 static const u16 sscdivintphase[] = {
10089 [BEND_IDX( 50)] = 0x3B23,
10090 [BEND_IDX( 45)] = 0x3B23,
10091 [BEND_IDX( 40)] = 0x3C23,
10092 [BEND_IDX( 35)] = 0x3C23,
10093 [BEND_IDX( 30)] = 0x3D23,
10094 [BEND_IDX( 25)] = 0x3D23,
10095 [BEND_IDX( 20)] = 0x3E23,
10096 [BEND_IDX( 15)] = 0x3E23,
10097 [BEND_IDX( 10)] = 0x3F23,
10098 [BEND_IDX( 5)] = 0x3F23,
10099 [BEND_IDX( 0)] = 0x0025,
10100 [BEND_IDX( -5)] = 0x0025,
10101 [BEND_IDX(-10)] = 0x0125,
10102 [BEND_IDX(-15)] = 0x0125,
10103 [BEND_IDX(-20)] = 0x0225,
10104 [BEND_IDX(-25)] = 0x0225,
10105 [BEND_IDX(-30)] = 0x0325,
10106 [BEND_IDX(-35)] = 0x0325,
10107 [BEND_IDX(-40)] = 0x0425,
10108 [BEND_IDX(-45)] = 0x0425,
10109 [BEND_IDX(-50)] = 0x0525,
10114 * steps -50 to 50 inclusive, in steps of 5
10115 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
10116 * change in clock period = -(steps / 10) * 5.787 ps
10118 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
10121 int idx = BEND_IDX(steps);
10123 if (drm_WARN_ON(&dev_priv->drm, steps % 5 != 0))
10126 if (drm_WARN_ON(&dev_priv->drm, idx >= ARRAY_SIZE(sscdivintphase)))
10129 mutex_lock(&dev_priv->sb_lock);
10131 if (steps % 10 != 0)
10135 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
10137 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
10139 tmp |= sscdivintphase[idx];
10140 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
10142 mutex_unlock(&dev_priv->sb_lock);
10147 static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
10149 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
10150 u32 ctl = intel_de_read(dev_priv, SPLL_CTL);
10152 if ((ctl & SPLL_PLL_ENABLE) == 0)
10155 if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC &&
10156 (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
10159 if (IS_BROADWELL(dev_priv) &&
10160 (ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW)
10166 static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
10167 enum intel_dpll_id id)
10169 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
10170 u32 ctl = intel_de_read(dev_priv, WRPLL_CTL(id));
10172 if ((ctl & WRPLL_PLL_ENABLE) == 0)
10175 if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
10178 if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
10179 (ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW &&
10180 (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
10186 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
10188 struct intel_encoder *encoder;
10189 bool has_fdi = false;
10191 for_each_intel_encoder(&dev_priv->drm, encoder) {
10192 switch (encoder->type) {
10193 case INTEL_OUTPUT_ANALOG:
10202 * The BIOS may have decided to use the PCH SSC
10203 * reference so we must not disable it until the
10204 * relevant PLLs have stopped relying on it. We'll
10205 * just leave the PCH SSC reference enabled in case
10206 * any active PLL is using it. It will get disabled
10207 * after runtime suspend if we don't have FDI.
10209 * TODO: Move the whole reference clock handling
10210 * to the modeset sequence proper so that we can
10211 * actually enable/disable/reconfigure these things
10212 * safely. To do that we need to introduce a real
10213 * clock hierarchy. That would also allow us to do
10214 * clock bending finally.
10216 dev_priv->pch_ssc_use = 0;
10218 if (spll_uses_pch_ssc(dev_priv)) {
10219 drm_dbg_kms(&dev_priv->drm, "SPLL using PCH SSC\n");
10220 dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
10223 if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
10224 drm_dbg_kms(&dev_priv->drm, "WRPLL1 using PCH SSC\n");
10225 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
10228 if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
10229 drm_dbg_kms(&dev_priv->drm, "WRPLL2 using PCH SSC\n");
10230 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
10233 if (dev_priv->pch_ssc_use)
10237 lpt_bend_clkout_dp(dev_priv, 0);
10238 lpt_enable_clkout_dp(dev_priv, true, true);
10240 lpt_disable_clkout_dp(dev_priv);
10245 * Initialize reference clocks when the driver loads
10247 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
10249 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
10250 ilk_init_pch_refclk(dev_priv);
10251 else if (HAS_PCH_LPT(dev_priv))
10252 lpt_init_pch_refclk(dev_priv);
10255 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
10257 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10258 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10259 enum pipe pipe = crtc->pipe;
10264 switch (crtc_state->pipe_bpp) {
10266 val |= PIPECONF_6BPC;
10269 val |= PIPECONF_8BPC;
10272 val |= PIPECONF_10BPC;
10275 val |= PIPECONF_12BPC;
10278 /* Case prevented by intel_choose_pipe_bpp_dither. */
10282 if (crtc_state->dither)
10283 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
10285 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
10286 val |= PIPECONF_INTERLACED_ILK;
10288 val |= PIPECONF_PROGRESSIVE;
10291 * This would end up with an odd purple hue over
10292 * the entire display. Make sure we don't do it.
10294 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
10295 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
10297 if (crtc_state->limited_color_range &&
10298 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
10299 val |= PIPECONF_COLOR_RANGE_SELECT;
10301 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
10302 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
10304 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
10306 val |= PIPECONF_FRAME_START_DELAY(0);
10308 intel_de_write(dev_priv, PIPECONF(pipe), val);
10309 intel_de_posting_read(dev_priv, PIPECONF(pipe));
10312 static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state)
10314 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10315 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10316 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
10319 if (IS_HASWELL(dev_priv) && crtc_state->dither)
10320 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
10322 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
10323 val |= PIPECONF_INTERLACED_ILK;
10325 val |= PIPECONF_PROGRESSIVE;
10327 if (IS_HASWELL(dev_priv) &&
10328 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
10329 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
10331 intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val);
10332 intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder));
10335 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
10337 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10338 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10341 switch (crtc_state->pipe_bpp) {
10343 val |= PIPEMISC_DITHER_6_BPC;
10346 val |= PIPEMISC_DITHER_8_BPC;
10349 val |= PIPEMISC_DITHER_10_BPC;
10352 val |= PIPEMISC_DITHER_12_BPC;
10355 MISSING_CASE(crtc_state->pipe_bpp);
10359 if (crtc_state->dither)
10360 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
10362 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
10363 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
10364 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
10366 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
10367 val |= PIPEMISC_YUV420_ENABLE |
10368 PIPEMISC_YUV420_MODE_FULL_BLEND;
10370 if (INTEL_GEN(dev_priv) >= 11 &&
10371 (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
10372 BIT(PLANE_CURSOR))) == 0)
10373 val |= PIPEMISC_HDR_MODE_PRECISION;
10375 if (INTEL_GEN(dev_priv) >= 12)
10376 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC;
10378 intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val);
10381 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
10383 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10386 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
10388 switch (tmp & PIPEMISC_DITHER_BPC_MASK) {
10389 case PIPEMISC_DITHER_6_BPC:
10391 case PIPEMISC_DITHER_8_BPC:
10393 case PIPEMISC_DITHER_10_BPC:
10395 case PIPEMISC_DITHER_12_BPC:
10403 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
10406 * Account for spread spectrum to avoid
10407 * oversubscribing the link. Max center spread
10408 * is 2.5%; use 5% for safety's sake.
10410 u32 bps = target_clock * bpp * 21 / 20;
10411 return DIV_ROUND_UP(bps, link_bw * 8);
10414 static bool ilk_needs_fb_cb_tune(struct dpll *dpll, int factor)
10416 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
10419 static void ilk_compute_dpll(struct intel_crtc *crtc,
10420 struct intel_crtc_state *crtc_state,
10421 struct dpll *reduced_clock)
10423 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10427 /* Enable autotuning of the PLL clock (if permissible) */
10429 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
10430 if ((intel_panel_use_ssc(dev_priv) &&
10431 dev_priv->vbt.lvds_ssc_freq == 100000) ||
10432 (HAS_PCH_IBX(dev_priv) &&
10433 intel_is_dual_link_lvds(dev_priv)))
10435 } else if (crtc_state->sdvo_tv_clock) {
10439 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
10441 if (ilk_needs_fb_cb_tune(&crtc_state->dpll, factor))
10444 if (reduced_clock) {
10445 fp2 = i9xx_dpll_compute_fp(reduced_clock);
10447 if (reduced_clock->m < factor * reduced_clock->n)
10455 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
10456 dpll |= DPLLB_MODE_LVDS;
10458 dpll |= DPLLB_MODE_DAC_SERIAL;
10460 dpll |= (crtc_state->pixel_multiplier - 1)
10461 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
10463 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
10464 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
10465 dpll |= DPLL_SDVO_HIGH_SPEED;
10467 if (intel_crtc_has_dp_encoder(crtc_state))
10468 dpll |= DPLL_SDVO_HIGH_SPEED;
10471 * The high speed IO clock is only really required for
10472 * SDVO/HDMI/DP, but we also enable it for CRT to make it
10473 * possible to share the DPLL between CRT and HDMI. Enabling
10474 * the clock needlessly does no real harm, except use up a
10475 * bit of power potentially.
10477 * We'll limit this to IVB with 3 pipes, since it has only two
10478 * DPLLs and so DPLL sharing is the only way to get three pipes
10479 * driving PCH ports at the same time. On SNB we could do this,
10480 * and potentially avoid enabling the second DPLL, but it's not
10481 * clear if it''s a win or loss power wise. No point in doing
10482 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
10484 if (INTEL_NUM_PIPES(dev_priv) == 3 &&
10485 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
10486 dpll |= DPLL_SDVO_HIGH_SPEED;
10488 /* compute bitmask from p1 value */
10489 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
10491 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
10493 switch (crtc_state->dpll.p2) {
10495 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
10498 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
10501 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
10504 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
10508 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
10509 intel_panel_use_ssc(dev_priv))
10510 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
10512 dpll |= PLL_REF_INPUT_DREFCLK;
10514 dpll |= DPLL_VCO_ENABLE;
10516 crtc_state->dpll_hw_state.dpll = dpll;
10517 crtc_state->dpll_hw_state.fp0 = fp;
10518 crtc_state->dpll_hw_state.fp1 = fp2;
10521 static int ilk_crtc_compute_clock(struct intel_crtc *crtc,
10522 struct intel_crtc_state *crtc_state)
10524 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10525 struct intel_atomic_state *state =
10526 to_intel_atomic_state(crtc_state->uapi.state);
10527 const struct intel_limit *limit;
10528 int refclk = 120000;
10530 memset(&crtc_state->dpll_hw_state, 0,
10531 sizeof(crtc_state->dpll_hw_state));
10533 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
10534 if (!crtc_state->has_pch_encoder)
10537 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
10538 if (intel_panel_use_ssc(dev_priv)) {
10539 drm_dbg_kms(&dev_priv->drm,
10540 "using SSC reference clock of %d kHz\n",
10541 dev_priv->vbt.lvds_ssc_freq);
10542 refclk = dev_priv->vbt.lvds_ssc_freq;
10545 if (intel_is_dual_link_lvds(dev_priv)) {
10546 if (refclk == 100000)
10547 limit = &ilk_limits_dual_lvds_100m;
10549 limit = &ilk_limits_dual_lvds;
10551 if (refclk == 100000)
10552 limit = &ilk_limits_single_lvds_100m;
10554 limit = &ilk_limits_single_lvds;
10557 limit = &ilk_limits_dac;
10560 if (!crtc_state->clock_set &&
10561 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
10562 refclk, NULL, &crtc_state->dpll)) {
10563 drm_err(&dev_priv->drm,
10564 "Couldn't find PLL settings for mode!\n");
10568 ilk_compute_dpll(crtc, crtc_state, NULL);
10570 if (!intel_reserve_shared_dplls(state, crtc, NULL)) {
10571 drm_dbg_kms(&dev_priv->drm,
10572 "failed to find PLL for pipe %c\n",
10573 pipe_name(crtc->pipe));
10580 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
10581 struct intel_link_m_n *m_n)
10583 struct drm_device *dev = crtc->base.dev;
10584 struct drm_i915_private *dev_priv = to_i915(dev);
10585 enum pipe pipe = crtc->pipe;
10587 m_n->link_m = intel_de_read(dev_priv, PCH_TRANS_LINK_M1(pipe));
10588 m_n->link_n = intel_de_read(dev_priv, PCH_TRANS_LINK_N1(pipe));
10589 m_n->gmch_m = intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
10591 m_n->gmch_n = intel_de_read(dev_priv, PCH_TRANS_DATA_N1(pipe));
10592 m_n->tu = ((intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
10593 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10596 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
10597 enum transcoder transcoder,
10598 struct intel_link_m_n *m_n,
10599 struct intel_link_m_n *m2_n2)
10601 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10602 enum pipe pipe = crtc->pipe;
10604 if (INTEL_GEN(dev_priv) >= 5) {
10605 m_n->link_m = intel_de_read(dev_priv,
10606 PIPE_LINK_M1(transcoder));
10607 m_n->link_n = intel_de_read(dev_priv,
10608 PIPE_LINK_N1(transcoder));
10609 m_n->gmch_m = intel_de_read(dev_priv,
10610 PIPE_DATA_M1(transcoder))
10612 m_n->gmch_n = intel_de_read(dev_priv,
10613 PIPE_DATA_N1(transcoder));
10614 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M1(transcoder))
10615 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10617 if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
10618 m2_n2->link_m = intel_de_read(dev_priv,
10619 PIPE_LINK_M2(transcoder));
10620 m2_n2->link_n = intel_de_read(dev_priv,
10621 PIPE_LINK_N2(transcoder));
10622 m2_n2->gmch_m = intel_de_read(dev_priv,
10623 PIPE_DATA_M2(transcoder))
10625 m2_n2->gmch_n = intel_de_read(dev_priv,
10626 PIPE_DATA_N2(transcoder));
10627 m2_n2->tu = ((intel_de_read(dev_priv, PIPE_DATA_M2(transcoder))
10628 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10631 m_n->link_m = intel_de_read(dev_priv, PIPE_LINK_M_G4X(pipe));
10632 m_n->link_n = intel_de_read(dev_priv, PIPE_LINK_N_G4X(pipe));
10633 m_n->gmch_m = intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
10635 m_n->gmch_n = intel_de_read(dev_priv, PIPE_DATA_N_G4X(pipe));
10636 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
10637 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10641 void intel_dp_get_m_n(struct intel_crtc *crtc,
10642 struct intel_crtc_state *pipe_config)
10644 if (pipe_config->has_pch_encoder)
10645 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
10647 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
10648 &pipe_config->dp_m_n,
10649 &pipe_config->dp_m2_n2);
10652 static void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
10653 struct intel_crtc_state *pipe_config)
10655 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
10656 &pipe_config->fdi_m_n, NULL);
10659 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state,
10662 drm_rect_init(&crtc_state->pch_pfit.dst,
10663 pos >> 16, pos & 0xffff,
10664 size >> 16, size & 0xffff);
10667 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state)
10669 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10670 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10671 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
10675 /* find scaler attached to this pipe */
10676 for (i = 0; i < crtc->num_scalers; i++) {
10677 u32 ctl, pos, size;
10679 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
10680 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)
10684 crtc_state->pch_pfit.enabled = true;
10686 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i));
10687 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
10689 ilk_get_pfit_pos_size(crtc_state, pos, size);
10691 scaler_state->scalers[i].in_use = true;
10695 scaler_state->scaler_id = id;
10697 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
10699 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
10703 skl_get_initial_plane_config(struct intel_crtc *crtc,
10704 struct intel_initial_plane_config *plane_config)
10706 struct drm_device *dev = crtc->base.dev;
10707 struct drm_i915_private *dev_priv = to_i915(dev);
10708 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
10709 enum plane_id plane_id = plane->id;
10711 u32 val, base, offset, stride_mult, tiling, alpha;
10712 int fourcc, pixel_format;
10713 unsigned int aligned_height;
10714 struct drm_framebuffer *fb;
10715 struct intel_framebuffer *intel_fb;
10717 if (!plane->get_hw_state(plane, &pipe))
10720 drm_WARN_ON(dev, pipe != crtc->pipe);
10722 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10724 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
10728 fb = &intel_fb->base;
10732 val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id));
10734 if (INTEL_GEN(dev_priv) >= 11)
10735 pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
10737 pixel_format = val & PLANE_CTL_FORMAT_MASK;
10739 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
10740 alpha = intel_de_read(dev_priv,
10741 PLANE_COLOR_CTL(pipe, plane_id));
10742 alpha &= PLANE_COLOR_ALPHA_MASK;
10744 alpha = val & PLANE_CTL_ALPHA_MASK;
10747 fourcc = skl_format_to_fourcc(pixel_format,
10748 val & PLANE_CTL_ORDER_RGBX, alpha);
10749 fb->format = drm_format_info(fourcc);
10751 tiling = val & PLANE_CTL_TILED_MASK;
10753 case PLANE_CTL_TILED_LINEAR:
10754 fb->modifier = DRM_FORMAT_MOD_LINEAR;
10756 case PLANE_CTL_TILED_X:
10757 plane_config->tiling = I915_TILING_X;
10758 fb->modifier = I915_FORMAT_MOD_X_TILED;
10760 case PLANE_CTL_TILED_Y:
10761 plane_config->tiling = I915_TILING_Y;
10762 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
10763 fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
10764 I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
10765 I915_FORMAT_MOD_Y_TILED_CCS;
10766 else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
10767 fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
10769 fb->modifier = I915_FORMAT_MOD_Y_TILED;
10771 case PLANE_CTL_TILED_YF:
10772 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
10773 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
10775 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
10778 MISSING_CASE(tiling);
10783 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
10784 * while i915 HW rotation is clockwise, thats why this swapping.
10786 switch (val & PLANE_CTL_ROTATE_MASK) {
10787 case PLANE_CTL_ROTATE_0:
10788 plane_config->rotation = DRM_MODE_ROTATE_0;
10790 case PLANE_CTL_ROTATE_90:
10791 plane_config->rotation = DRM_MODE_ROTATE_270;
10793 case PLANE_CTL_ROTATE_180:
10794 plane_config->rotation = DRM_MODE_ROTATE_180;
10796 case PLANE_CTL_ROTATE_270:
10797 plane_config->rotation = DRM_MODE_ROTATE_90;
10801 if (INTEL_GEN(dev_priv) >= 10 &&
10802 val & PLANE_CTL_FLIP_HORIZONTAL)
10803 plane_config->rotation |= DRM_MODE_REFLECT_X;
10805 /* 90/270 degree rotation would require extra work */
10806 if (drm_rotation_90_or_270(plane_config->rotation))
10809 base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xfffff000;
10810 plane_config->base = base;
10812 offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id));
10814 val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id));
10815 fb->height = ((val >> 16) & 0xffff) + 1;
10816 fb->width = ((val >> 0) & 0xffff) + 1;
10818 val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
10819 stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
10820 fb->pitches[0] = (val & 0x3ff) * stride_mult;
10822 aligned_height = intel_fb_align_height(fb, 0, fb->height);
10824 plane_config->size = fb->pitches[0] * aligned_height;
10826 drm_dbg_kms(&dev_priv->drm,
10827 "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
10828 crtc->base.name, plane->base.name, fb->width, fb->height,
10829 fb->format->cpp[0] * 8, base, fb->pitches[0],
10830 plane_config->size);
10832 plane_config->fb = intel_fb;
10839 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
10841 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10842 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10843 u32 ctl, pos, size;
10845 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
10846 if ((ctl & PF_ENABLE) == 0)
10849 crtc_state->pch_pfit.enabled = true;
10851 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
10852 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
10854 ilk_get_pfit_pos_size(crtc_state, pos, size);
10857 * We currently do not free assignements of panel fitters on
10858 * ivb/hsw (since we don't use the higher upscaling modes which
10859 * differentiates them) so just WARN about this case for now.
10861 drm_WARN_ON(&dev_priv->drm, IS_GEN(dev_priv, 7) &&
10862 (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe));
10865 static bool ilk_get_pipe_config(struct intel_crtc *crtc,
10866 struct intel_crtc_state *pipe_config)
10868 struct drm_device *dev = crtc->base.dev;
10869 struct drm_i915_private *dev_priv = to_i915(dev);
10870 enum intel_display_power_domain power_domain;
10871 intel_wakeref_t wakeref;
10875 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10876 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
10880 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10881 pipe_config->shared_dpll = NULL;
10884 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
10885 if (!(tmp & PIPECONF_ENABLE))
10888 switch (tmp & PIPECONF_BPC_MASK) {
10889 case PIPECONF_6BPC:
10890 pipe_config->pipe_bpp = 18;
10892 case PIPECONF_8BPC:
10893 pipe_config->pipe_bpp = 24;
10895 case PIPECONF_10BPC:
10896 pipe_config->pipe_bpp = 30;
10898 case PIPECONF_12BPC:
10899 pipe_config->pipe_bpp = 36;
10905 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
10906 pipe_config->limited_color_range = true;
10908 switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
10909 case PIPECONF_OUTPUT_COLORSPACE_YUV601:
10910 case PIPECONF_OUTPUT_COLORSPACE_YUV709:
10911 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
10914 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
10918 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
10919 PIPECONF_GAMMA_MODE_SHIFT;
10921 pipe_config->csc_mode = intel_de_read(dev_priv,
10922 PIPE_CSC_MODE(crtc->pipe));
10924 i9xx_get_pipe_color_config(pipe_config);
10925 intel_color_get_config(pipe_config);
10927 if (intel_de_read(dev_priv, PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
10928 struct intel_shared_dpll *pll;
10929 enum intel_dpll_id pll_id;
10931 pipe_config->has_pch_encoder = true;
10933 tmp = intel_de_read(dev_priv, FDI_RX_CTL(crtc->pipe));
10934 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10935 FDI_DP_PORT_WIDTH_SHIFT) + 1;
10937 ilk_get_fdi_m_n_config(crtc, pipe_config);
10939 if (HAS_PCH_IBX(dev_priv)) {
10941 * The pipe->pch transcoder and pch transcoder->pll
10942 * mapping is fixed.
10944 pll_id = (enum intel_dpll_id) crtc->pipe;
10946 tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
10947 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
10948 pll_id = DPLL_ID_PCH_PLL_B;
10950 pll_id= DPLL_ID_PCH_PLL_A;
10953 pipe_config->shared_dpll =
10954 intel_get_shared_dpll_by_id(dev_priv, pll_id);
10955 pll = pipe_config->shared_dpll;
10957 drm_WARN_ON(dev, !pll->info->funcs->get_hw_state(dev_priv, pll,
10958 &pipe_config->dpll_hw_state));
10960 tmp = pipe_config->dpll_hw_state.dpll;
10961 pipe_config->pixel_multiplier =
10962 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
10963 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
10965 ilk_pch_clock_get(crtc, pipe_config);
10967 pipe_config->pixel_multiplier = 1;
10970 intel_get_transcoder_timings(crtc, pipe_config);
10971 intel_get_pipe_src_size(crtc, pipe_config);
10973 ilk_get_pfit_config(pipe_config);
10978 intel_display_power_put(dev_priv, power_domain, wakeref);
10983 static int hsw_crtc_compute_clock(struct intel_crtc *crtc,
10984 struct intel_crtc_state *crtc_state)
10986 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10987 struct intel_atomic_state *state =
10988 to_intel_atomic_state(crtc_state->uapi.state);
10990 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
10991 INTEL_GEN(dev_priv) >= 11) {
10992 struct intel_encoder *encoder =
10993 intel_get_crtc_new_encoder(state, crtc_state);
10995 if (!intel_reserve_shared_dplls(state, crtc, encoder)) {
10996 drm_dbg_kms(&dev_priv->drm,
10997 "failed to find PLL for pipe %c\n",
10998 pipe_name(crtc->pipe));
11006 static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
11007 struct intel_crtc_state *pipe_config)
11009 enum intel_dpll_id id;
11012 temp = intel_de_read(dev_priv, DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
11013 id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
11015 if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL2))
11018 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
11021 static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
11022 struct intel_crtc_state *pipe_config)
11024 enum phy phy = intel_port_to_phy(dev_priv, port);
11025 enum icl_port_dpll_id port_dpll_id;
11026 enum intel_dpll_id id;
11029 if (intel_phy_is_combo(dev_priv, phy)) {
11032 if (IS_ROCKETLAKE(dev_priv)) {
11033 mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
11034 shift = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
11036 mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
11037 shift = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
11040 temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & mask;
11041 id = temp >> shift;
11042 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
11043 } else if (intel_phy_is_tc(dev_priv, phy)) {
11044 u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
11046 if (clk_sel == DDI_CLK_SEL_MG) {
11047 id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
11049 port_dpll_id = ICL_PORT_DPLL_MG_PHY;
11051 drm_WARN_ON(&dev_priv->drm,
11052 clk_sel < DDI_CLK_SEL_TBT_162);
11053 id = DPLL_ID_ICL_TBTPLL;
11054 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
11057 drm_WARN(&dev_priv->drm, 1, "Invalid port %x\n", port);
11061 pipe_config->icl_port_dplls[port_dpll_id].pll =
11062 intel_get_shared_dpll_by_id(dev_priv, id);
11064 icl_set_active_port_dpll(pipe_config, port_dpll_id);
11067 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
11069 struct intel_crtc_state *pipe_config)
11071 enum intel_dpll_id id;
11075 id = DPLL_ID_SKL_DPLL0;
11078 id = DPLL_ID_SKL_DPLL1;
11081 id = DPLL_ID_SKL_DPLL2;
11084 drm_err(&dev_priv->drm, "Incorrect port type\n");
11088 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
11091 static void skl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
11092 struct intel_crtc_state *pipe_config)
11094 enum intel_dpll_id id;
11097 temp = intel_de_read(dev_priv, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
11098 id = temp >> (port * 3 + 1);
11100 if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL3))
11103 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
11106 static void hsw_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
11107 struct intel_crtc_state *pipe_config)
11109 enum intel_dpll_id id;
11110 u32 ddi_pll_sel = intel_de_read(dev_priv, PORT_CLK_SEL(port));
11112 switch (ddi_pll_sel) {
11113 case PORT_CLK_SEL_WRPLL1:
11114 id = DPLL_ID_WRPLL1;
11116 case PORT_CLK_SEL_WRPLL2:
11117 id = DPLL_ID_WRPLL2;
11119 case PORT_CLK_SEL_SPLL:
11122 case PORT_CLK_SEL_LCPLL_810:
11123 id = DPLL_ID_LCPLL_810;
11125 case PORT_CLK_SEL_LCPLL_1350:
11126 id = DPLL_ID_LCPLL_1350;
11128 case PORT_CLK_SEL_LCPLL_2700:
11129 id = DPLL_ID_LCPLL_2700;
11132 MISSING_CASE(ddi_pll_sel);
11134 case PORT_CLK_SEL_NONE:
11138 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
11141 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
11142 struct intel_crtc_state *pipe_config,
11143 u64 *power_domain_mask,
11144 intel_wakeref_t *wakerefs)
11146 struct drm_device *dev = crtc->base.dev;
11147 struct drm_i915_private *dev_priv = to_i915(dev);
11148 enum intel_display_power_domain power_domain;
11149 unsigned long panel_transcoder_mask = BIT(TRANSCODER_EDP);
11150 unsigned long enabled_panel_transcoders = 0;
11151 enum transcoder panel_transcoder;
11152 intel_wakeref_t wf;
11155 if (INTEL_GEN(dev_priv) >= 11)
11156 panel_transcoder_mask |=
11157 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
11160 * The pipe->transcoder mapping is fixed with the exception of the eDP
11161 * and DSI transcoders handled below.
11163 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
11166 * XXX: Do intel_display_power_get_if_enabled before reading this (for
11167 * consistency and less surprising code; it's in always on power).
11169 for_each_cpu_transcoder_masked(dev_priv, panel_transcoder,
11170 panel_transcoder_mask) {
11171 bool force_thru = false;
11172 enum pipe trans_pipe;
11174 tmp = intel_de_read(dev_priv,
11175 TRANS_DDI_FUNC_CTL(panel_transcoder));
11176 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
11180 * Log all enabled ones, only use the first one.
11182 * FIXME: This won't work for two separate DSI displays.
11184 enabled_panel_transcoders |= BIT(panel_transcoder);
11185 if (enabled_panel_transcoders != BIT(panel_transcoder))
11188 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
11191 "unknown pipe linked to transcoder %s\n",
11192 transcoder_name(panel_transcoder));
11194 case TRANS_DDI_EDP_INPUT_A_ONOFF:
11197 case TRANS_DDI_EDP_INPUT_A_ON:
11198 trans_pipe = PIPE_A;
11200 case TRANS_DDI_EDP_INPUT_B_ONOFF:
11201 trans_pipe = PIPE_B;
11203 case TRANS_DDI_EDP_INPUT_C_ONOFF:
11204 trans_pipe = PIPE_C;
11206 case TRANS_DDI_EDP_INPUT_D_ONOFF:
11207 trans_pipe = PIPE_D;
11211 if (trans_pipe == crtc->pipe) {
11212 pipe_config->cpu_transcoder = panel_transcoder;
11213 pipe_config->pch_pfit.force_thru = force_thru;
11218 * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1
11220 drm_WARN_ON(dev, (enabled_panel_transcoders & BIT(TRANSCODER_EDP)) &&
11221 enabled_panel_transcoders != BIT(TRANSCODER_EDP));
11223 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
11224 drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain));
11226 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11230 wakerefs[power_domain] = wf;
11231 *power_domain_mask |= BIT_ULL(power_domain);
11233 tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder));
11235 return tmp & PIPECONF_ENABLE;
11238 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
11239 struct intel_crtc_state *pipe_config,
11240 u64 *power_domain_mask,
11241 intel_wakeref_t *wakerefs)
11243 struct drm_device *dev = crtc->base.dev;
11244 struct drm_i915_private *dev_priv = to_i915(dev);
11245 enum intel_display_power_domain power_domain;
11246 enum transcoder cpu_transcoder;
11247 intel_wakeref_t wf;
11251 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
11252 if (port == PORT_A)
11253 cpu_transcoder = TRANSCODER_DSI_A;
11255 cpu_transcoder = TRANSCODER_DSI_C;
11257 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
11258 drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain));
11260 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11264 wakerefs[power_domain] = wf;
11265 *power_domain_mask |= BIT_ULL(power_domain);
11268 * The PLL needs to be enabled with a valid divider
11269 * configuration, otherwise accessing DSI registers will hang
11270 * the machine. See BSpec North Display Engine
11271 * registers/MIPI[BXT]. We can break out here early, since we
11272 * need the same DSI PLL to be enabled for both DSI ports.
11274 if (!bxt_dsi_pll_is_enabled(dev_priv))
11277 /* XXX: this works for video mode only */
11278 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
11279 if (!(tmp & DPI_ENABLE))
11282 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
11283 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
11286 pipe_config->cpu_transcoder = cpu_transcoder;
11290 return transcoder_is_dsi(pipe_config->cpu_transcoder);
11293 static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
11294 struct intel_crtc_state *pipe_config)
11296 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11297 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
11298 struct intel_shared_dpll *pll;
11302 if (transcoder_is_dsi(cpu_transcoder)) {
11303 port = (cpu_transcoder == TRANSCODER_DSI_A) ?
11306 tmp = intel_de_read(dev_priv,
11307 TRANS_DDI_FUNC_CTL(cpu_transcoder));
11308 if (INTEL_GEN(dev_priv) >= 12)
11309 port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
11311 port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
11314 if (INTEL_GEN(dev_priv) >= 11)
11315 icl_get_ddi_pll(dev_priv, port, pipe_config);
11316 else if (IS_CANNONLAKE(dev_priv))
11317 cnl_get_ddi_pll(dev_priv, port, pipe_config);
11318 else if (IS_GEN9_BC(dev_priv))
11319 skl_get_ddi_pll(dev_priv, port, pipe_config);
11320 else if (IS_GEN9_LP(dev_priv))
11321 bxt_get_ddi_pll(dev_priv, port, pipe_config);
11323 hsw_get_ddi_pll(dev_priv, port, pipe_config);
11325 pll = pipe_config->shared_dpll;
11327 drm_WARN_ON(&dev_priv->drm,
11328 !pll->info->funcs->get_hw_state(dev_priv, pll,
11329 &pipe_config->dpll_hw_state));
11333 * Haswell has only FDI/PCH transcoder A. It is which is connected to
11334 * DDI E. So just check whether this pipe is wired to DDI E and whether
11335 * the PCH transcoder is on.
11337 if (INTEL_GEN(dev_priv) < 9 &&
11338 (port == PORT_E) && intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) {
11339 pipe_config->has_pch_encoder = true;
11341 tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
11342 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
11343 FDI_DP_PORT_WIDTH_SHIFT) + 1;
11345 ilk_get_fdi_m_n_config(crtc, pipe_config);
11349 static bool hsw_get_pipe_config(struct intel_crtc *crtc,
11350 struct intel_crtc_state *pipe_config)
11352 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11353 intel_wakeref_t wakerefs[POWER_DOMAIN_NUM], wf;
11354 enum intel_display_power_domain power_domain;
11355 u64 power_domain_mask;
11359 pipe_config->master_transcoder = INVALID_TRANSCODER;
11361 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
11362 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11366 wakerefs[power_domain] = wf;
11367 power_domain_mask = BIT_ULL(power_domain);
11369 pipe_config->shared_dpll = NULL;
11371 active = hsw_get_transcoder_state(crtc, pipe_config,
11372 &power_domain_mask, wakerefs);
11374 if (IS_GEN9_LP(dev_priv) &&
11375 bxt_get_dsi_transcoder_state(crtc, pipe_config,
11376 &power_domain_mask, wakerefs)) {
11377 drm_WARN_ON(&dev_priv->drm, active);
11384 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
11385 INTEL_GEN(dev_priv) >= 11) {
11386 hsw_get_ddi_port_state(crtc, pipe_config);
11387 intel_get_transcoder_timings(crtc, pipe_config);
11390 intel_get_pipe_src_size(crtc, pipe_config);
11392 if (IS_HASWELL(dev_priv)) {
11393 u32 tmp = intel_de_read(dev_priv,
11394 PIPECONF(pipe_config->cpu_transcoder));
11396 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
11397 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
11399 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
11401 pipe_config->output_format =
11402 bdw_get_pipemisc_output_format(crtc);
11405 pipe_config->gamma_mode = intel_de_read(dev_priv,
11406 GAMMA_MODE(crtc->pipe));
11408 pipe_config->csc_mode = intel_de_read(dev_priv,
11409 PIPE_CSC_MODE(crtc->pipe));
11411 if (INTEL_GEN(dev_priv) >= 9) {
11412 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe));
11414 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
11415 pipe_config->gamma_enable = true;
11417 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
11418 pipe_config->csc_enable = true;
11420 i9xx_get_pipe_color_config(pipe_config);
11423 intel_color_get_config(pipe_config);
11425 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));
11426 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
11427 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
11428 pipe_config->ips_linetime =
11429 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
11431 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
11432 drm_WARN_ON(&dev_priv->drm, power_domain_mask & BIT_ULL(power_domain));
11434 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11436 wakerefs[power_domain] = wf;
11437 power_domain_mask |= BIT_ULL(power_domain);
11439 if (INTEL_GEN(dev_priv) >= 9)
11440 skl_get_pfit_config(pipe_config);
11442 ilk_get_pfit_config(pipe_config);
11445 if (hsw_crtc_supports_ips(crtc)) {
11446 if (IS_HASWELL(dev_priv))
11447 pipe_config->ips_enabled = intel_de_read(dev_priv,
11448 IPS_CTL) & IPS_ENABLE;
11451 * We cannot readout IPS state on broadwell, set to
11452 * true so we can set it to a defined state on first
11455 pipe_config->ips_enabled = true;
11459 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
11460 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
11461 pipe_config->pixel_multiplier =
11462 intel_de_read(dev_priv,
11463 PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
11465 pipe_config->pixel_multiplier = 1;
11469 for_each_power_domain(power_domain, power_domain_mask)
11470 intel_display_power_put(dev_priv,
11471 power_domain, wakerefs[power_domain]);
11476 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
11478 struct drm_i915_private *dev_priv =
11479 to_i915(plane_state->uapi.plane->dev);
11480 const struct drm_framebuffer *fb = plane_state->hw.fb;
11481 const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11484 if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
11485 base = sg_dma_address(obj->mm.pages->sgl);
11487 base = intel_plane_ggtt_offset(plane_state);
11489 return base + plane_state->color_plane[0].offset;
11492 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
11494 int x = plane_state->uapi.dst.x1;
11495 int y = plane_state->uapi.dst.y1;
11499 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
11502 pos |= x << CURSOR_X_SHIFT;
11505 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
11508 pos |= y << CURSOR_Y_SHIFT;
11513 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
11515 const struct drm_mode_config *config =
11516 &plane_state->uapi.plane->dev->mode_config;
11517 int width = drm_rect_width(&plane_state->uapi.dst);
11518 int height = drm_rect_height(&plane_state->uapi.dst);
11520 return width > 0 && width <= config->cursor_width &&
11521 height > 0 && height <= config->cursor_height;
11524 static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
11526 struct drm_i915_private *dev_priv =
11527 to_i915(plane_state->uapi.plane->dev);
11528 unsigned int rotation = plane_state->hw.rotation;
11533 ret = intel_plane_compute_gtt(plane_state);
11537 if (!plane_state->uapi.visible)
11540 src_x = plane_state->uapi.src.x1 >> 16;
11541 src_y = plane_state->uapi.src.y1 >> 16;
11543 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
11544 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
11547 if (src_x != 0 || src_y != 0) {
11548 drm_dbg_kms(&dev_priv->drm,
11549 "Arbitrary cursor panning not supported\n");
11554 * Put the final coordinates back so that the src
11555 * coordinate checks will see the right values.
11557 drm_rect_translate_to(&plane_state->uapi.src,
11558 src_x << 16, src_y << 16);
11560 /* ILK+ do this automagically in hardware */
11561 if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) {
11562 const struct drm_framebuffer *fb = plane_state->hw.fb;
11563 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
11564 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
11566 offset += (src_h * src_w - 1) * fb->format->cpp[0];
11569 plane_state->color_plane[0].offset = offset;
11570 plane_state->color_plane[0].x = src_x;
11571 plane_state->color_plane[0].y = src_y;
11576 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
11577 struct intel_plane_state *plane_state)
11579 const struct drm_framebuffer *fb = plane_state->hw.fb;
11580 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
11583 if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
11584 drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n");
11588 ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
11590 DRM_PLANE_HELPER_NO_SCALING,
11591 DRM_PLANE_HELPER_NO_SCALING,
11596 /* Use the unclipped src/dst rectangles, which we program to hw */
11597 plane_state->uapi.src = drm_plane_state_src(&plane_state->uapi);
11598 plane_state->uapi.dst = drm_plane_state_dest(&plane_state->uapi);
11600 ret = intel_cursor_check_surface(plane_state);
11604 if (!plane_state->uapi.visible)
11607 ret = intel_plane_check_src_coordinates(plane_state);
11614 static unsigned int
11615 i845_cursor_max_stride(struct intel_plane *plane,
11616 u32 pixel_format, u64 modifier,
11617 unsigned int rotation)
11622 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
11626 if (crtc_state->gamma_enable)
11627 cntl |= CURSOR_GAMMA_ENABLE;
11632 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
11633 const struct intel_plane_state *plane_state)
11635 return CURSOR_ENABLE |
11636 CURSOR_FORMAT_ARGB |
11637 CURSOR_STRIDE(plane_state->color_plane[0].stride);
11640 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
11642 int width = drm_rect_width(&plane_state->uapi.dst);
11645 * 845g/865g are only limited by the width of their cursors,
11646 * the height is arbitrary up to the precision of the register.
11648 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
11651 static int i845_check_cursor(struct intel_crtc_state *crtc_state,
11652 struct intel_plane_state *plane_state)
11654 const struct drm_framebuffer *fb = plane_state->hw.fb;
11655 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
11658 ret = intel_check_cursor(crtc_state, plane_state);
11662 /* if we want to turn off the cursor ignore width and height */
11666 /* Check for which cursor types we support */
11667 if (!i845_cursor_size_ok(plane_state)) {
11668 drm_dbg_kms(&i915->drm,
11669 "Cursor dimension %dx%d not supported\n",
11670 drm_rect_width(&plane_state->uapi.dst),
11671 drm_rect_height(&plane_state->uapi.dst));
11675 drm_WARN_ON(&i915->drm, plane_state->uapi.visible &&
11676 plane_state->color_plane[0].stride != fb->pitches[0]);
11678 switch (fb->pitches[0]) {
11685 drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n",
11690 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
11695 static void i845_update_cursor(struct intel_plane *plane,
11696 const struct intel_crtc_state *crtc_state,
11697 const struct intel_plane_state *plane_state)
11699 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11700 u32 cntl = 0, base = 0, pos = 0, size = 0;
11701 unsigned long irqflags;
11703 if (plane_state && plane_state->uapi.visible) {
11704 unsigned int width = drm_rect_width(&plane_state->uapi.dst);
11705 unsigned int height = drm_rect_height(&plane_state->uapi.dst);
11707 cntl = plane_state->ctl |
11708 i845_cursor_ctl_crtc(crtc_state);
11710 size = (height << 12) | width;
11712 base = intel_cursor_base(plane_state);
11713 pos = intel_cursor_position(plane_state);
11716 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11718 /* On these chipsets we can only modify the base/size/stride
11719 * whilst the cursor is disabled.
11721 if (plane->cursor.base != base ||
11722 plane->cursor.size != size ||
11723 plane->cursor.cntl != cntl) {
11724 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0);
11725 intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base);
11726 intel_de_write_fw(dev_priv, CURSIZE, size);
11727 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
11728 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl);
11730 plane->cursor.base = base;
11731 plane->cursor.size = size;
11732 plane->cursor.cntl = cntl;
11734 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
11737 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11740 static void i845_disable_cursor(struct intel_plane *plane,
11741 const struct intel_crtc_state *crtc_state)
11743 i845_update_cursor(plane, crtc_state, NULL);
11746 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
11749 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11750 enum intel_display_power_domain power_domain;
11751 intel_wakeref_t wakeref;
11754 power_domain = POWER_DOMAIN_PIPE(PIPE_A);
11755 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11759 ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE;
11763 intel_display_power_put(dev_priv, power_domain, wakeref);
11768 static unsigned int
11769 i9xx_cursor_max_stride(struct intel_plane *plane,
11770 u32 pixel_format, u64 modifier,
11771 unsigned int rotation)
11773 return plane->base.dev->mode_config.cursor_width * 4;
11776 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
11778 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
11779 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11782 if (INTEL_GEN(dev_priv) >= 11)
11785 if (crtc_state->gamma_enable)
11786 cntl = MCURSOR_GAMMA_ENABLE;
11788 if (crtc_state->csc_enable)
11789 cntl |= MCURSOR_PIPE_CSC_ENABLE;
11791 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11792 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
11797 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
11798 const struct intel_plane_state *plane_state)
11800 struct drm_i915_private *dev_priv =
11801 to_i915(plane_state->uapi.plane->dev);
11804 if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
11805 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
11807 switch (drm_rect_width(&plane_state->uapi.dst)) {
11809 cntl |= MCURSOR_MODE_64_ARGB_AX;
11812 cntl |= MCURSOR_MODE_128_ARGB_AX;
11815 cntl |= MCURSOR_MODE_256_ARGB_AX;
11818 MISSING_CASE(drm_rect_width(&plane_state->uapi.dst));
11822 if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)
11823 cntl |= MCURSOR_ROTATE_180;
11828 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
11830 struct drm_i915_private *dev_priv =
11831 to_i915(plane_state->uapi.plane->dev);
11832 int width = drm_rect_width(&plane_state->uapi.dst);
11833 int height = drm_rect_height(&plane_state->uapi.dst);
11835 if (!intel_cursor_size_ok(plane_state))
11838 /* Cursor width is limited to a few power-of-two sizes */
11849 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
11850 * height from 8 lines up to the cursor width, when the
11851 * cursor is not rotated. Everything else requires square
11854 if (HAS_CUR_FBC(dev_priv) &&
11855 plane_state->hw.rotation & DRM_MODE_ROTATE_0) {
11856 if (height < 8 || height > width)
11859 if (height != width)
11866 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
11867 struct intel_plane_state *plane_state)
11869 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
11870 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11871 const struct drm_framebuffer *fb = plane_state->hw.fb;
11872 enum pipe pipe = plane->pipe;
11875 ret = intel_check_cursor(crtc_state, plane_state);
11879 /* if we want to turn off the cursor ignore width and height */
11883 /* Check for which cursor types we support */
11884 if (!i9xx_cursor_size_ok(plane_state)) {
11885 drm_dbg(&dev_priv->drm,
11886 "Cursor dimension %dx%d not supported\n",
11887 drm_rect_width(&plane_state->uapi.dst),
11888 drm_rect_height(&plane_state->uapi.dst));
11892 drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible &&
11893 plane_state->color_plane[0].stride != fb->pitches[0]);
11895 if (fb->pitches[0] !=
11896 drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) {
11897 drm_dbg_kms(&dev_priv->drm,
11898 "Invalid cursor stride (%u) (cursor width %d)\n",
11900 drm_rect_width(&plane_state->uapi.dst));
11905 * There's something wrong with the cursor on CHV pipe C.
11906 * If it straddles the left edge of the screen then
11907 * moving it away from the edge or disabling it often
11908 * results in a pipe underrun, and often that can lead to
11909 * dead pipe (constant underrun reported, and it scans
11910 * out just a solid color). To recover from that, the
11911 * display power well must be turned off and on again.
11912 * Refuse the put the cursor into that compromised position.
11914 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
11915 plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) {
11916 drm_dbg_kms(&dev_priv->drm,
11917 "CHV cursor C not allowed to straddle the left screen edge\n");
11921 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
11926 static void i9xx_update_cursor(struct intel_plane *plane,
11927 const struct intel_crtc_state *crtc_state,
11928 const struct intel_plane_state *plane_state)
11930 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11931 enum pipe pipe = plane->pipe;
11932 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
11933 unsigned long irqflags;
11935 if (plane_state && plane_state->uapi.visible) {
11936 unsigned width = drm_rect_width(&plane_state->uapi.dst);
11937 unsigned height = drm_rect_height(&plane_state->uapi.dst);
11939 cntl = plane_state->ctl |
11940 i9xx_cursor_ctl_crtc(crtc_state);
11942 if (width != height)
11943 fbc_ctl = CUR_FBC_CTL_EN | (height - 1);
11945 base = intel_cursor_base(plane_state);
11946 pos = intel_cursor_position(plane_state);
11949 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11952 * On some platforms writing CURCNTR first will also
11953 * cause CURPOS to be armed by the CURBASE write.
11954 * Without the CURCNTR write the CURPOS write would
11955 * arm itself. Thus we always update CURCNTR before
11958 * On other platforms CURPOS always requires the
11959 * CURBASE write to arm the update. Additonally
11960 * a write to any of the cursor register will cancel
11961 * an already armed cursor update. Thus leaving out
11962 * the CURBASE write after CURPOS could lead to a
11963 * cursor that doesn't appear to move, or even change
11964 * shape. Thus we always write CURBASE.
11966 * The other registers are armed by by the CURBASE write
11967 * except when the plane is getting enabled at which time
11968 * the CURCNTR write arms the update.
11971 if (INTEL_GEN(dev_priv) >= 9)
11972 skl_write_cursor_wm(plane, crtc_state);
11974 if (!needs_modeset(crtc_state))
11975 intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, 0);
11977 if (plane->cursor.base != base ||
11978 plane->cursor.size != fbc_ctl ||
11979 plane->cursor.cntl != cntl) {
11980 if (HAS_CUR_FBC(dev_priv))
11981 intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe),
11983 intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl);
11984 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
11985 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
11987 plane->cursor.base = base;
11988 plane->cursor.size = fbc_ctl;
11989 plane->cursor.cntl = cntl;
11991 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
11992 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
11995 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11998 static void i9xx_disable_cursor(struct intel_plane *plane,
11999 const struct intel_crtc_state *crtc_state)
12001 i9xx_update_cursor(plane, crtc_state, NULL);
12004 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
12007 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
12008 enum intel_display_power_domain power_domain;
12009 intel_wakeref_t wakeref;
12014 * Not 100% correct for planes that can move between pipes,
12015 * but that's only the case for gen2-3 which don't have any
12016 * display power wells.
12018 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
12019 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
12023 val = intel_de_read(dev_priv, CURCNTR(plane->pipe));
12025 ret = val & MCURSOR_MODE;
12027 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
12028 *pipe = plane->pipe;
12030 *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
12031 MCURSOR_PIPE_SELECT_SHIFT;
12033 intel_display_power_put(dev_priv, power_domain, wakeref);
12038 /* VESA 640x480x72Hz mode to set on the pipe */
12039 static const struct drm_display_mode load_detect_mode = {
12040 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
12041 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
12044 struct drm_framebuffer *
12045 intel_framebuffer_create(struct drm_i915_gem_object *obj,
12046 struct drm_mode_fb_cmd2 *mode_cmd)
12048 struct intel_framebuffer *intel_fb;
12051 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
12053 return ERR_PTR(-ENOMEM);
12055 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
12059 return &intel_fb->base;
12063 return ERR_PTR(ret);
12066 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
12067 struct drm_crtc *crtc)
12069 struct drm_plane *plane;
12070 struct drm_plane_state *plane_state;
12073 ret = drm_atomic_add_affected_planes(state, crtc);
12077 for_each_new_plane_in_state(state, plane, plane_state, i) {
12078 if (plane_state->crtc != crtc)
12081 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
12085 drm_atomic_set_fb_for_plane(plane_state, NULL);
12091 int intel_get_load_detect_pipe(struct drm_connector *connector,
12092 struct intel_load_detect_pipe *old,
12093 struct drm_modeset_acquire_ctx *ctx)
12095 struct intel_crtc *intel_crtc;
12096 struct intel_encoder *intel_encoder =
12097 intel_attached_encoder(to_intel_connector(connector));
12098 struct drm_crtc *possible_crtc;
12099 struct drm_encoder *encoder = &intel_encoder->base;
12100 struct drm_crtc *crtc = NULL;
12101 struct drm_device *dev = encoder->dev;
12102 struct drm_i915_private *dev_priv = to_i915(dev);
12103 struct drm_mode_config *config = &dev->mode_config;
12104 struct drm_atomic_state *state = NULL, *restore_state = NULL;
12105 struct drm_connector_state *connector_state;
12106 struct intel_crtc_state *crtc_state;
12109 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
12110 connector->base.id, connector->name,
12111 encoder->base.id, encoder->name);
12113 old->restore_state = NULL;
12115 drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex));
12118 * Algorithm gets a little messy:
12120 * - if the connector already has an assigned crtc, use it (but make
12121 * sure it's on first)
12123 * - try to find the first unused crtc that can drive this connector,
12124 * and use that if we find one
12127 /* See if we already have a CRTC for this connector */
12128 if (connector->state->crtc) {
12129 crtc = connector->state->crtc;
12131 ret = drm_modeset_lock(&crtc->mutex, ctx);
12135 /* Make sure the crtc and connector are running */
12139 /* Find an unused one (if possible) */
12140 for_each_crtc(dev, possible_crtc) {
12142 if (!(encoder->possible_crtcs & (1 << i)))
12145 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
12149 if (possible_crtc->state->enable) {
12150 drm_modeset_unlock(&possible_crtc->mutex);
12154 crtc = possible_crtc;
12159 * If we didn't find an unused CRTC, don't use any.
12162 drm_dbg_kms(&dev_priv->drm,
12163 "no pipe available for load-detect\n");
12169 intel_crtc = to_intel_crtc(crtc);
12171 state = drm_atomic_state_alloc(dev);
12172 restore_state = drm_atomic_state_alloc(dev);
12173 if (!state || !restore_state) {
12178 state->acquire_ctx = ctx;
12179 restore_state->acquire_ctx = ctx;
12181 connector_state = drm_atomic_get_connector_state(state, connector);
12182 if (IS_ERR(connector_state)) {
12183 ret = PTR_ERR(connector_state);
12187 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
12191 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
12192 if (IS_ERR(crtc_state)) {
12193 ret = PTR_ERR(crtc_state);
12197 crtc_state->uapi.active = true;
12199 ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi,
12200 &load_detect_mode);
12204 ret = intel_modeset_disable_planes(state, crtc);
12208 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
12210 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
12212 ret = drm_atomic_add_affected_planes(restore_state, crtc);
12214 drm_dbg_kms(&dev_priv->drm,
12215 "Failed to create a copy of old state to restore: %i\n",
12220 ret = drm_atomic_commit(state);
12222 drm_dbg_kms(&dev_priv->drm,
12223 "failed to set mode on load-detect pipe\n");
12227 old->restore_state = restore_state;
12228 drm_atomic_state_put(state);
12230 /* let the connector get through one full cycle before testing */
12231 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
12236 drm_atomic_state_put(state);
12239 if (restore_state) {
12240 drm_atomic_state_put(restore_state);
12241 restore_state = NULL;
12244 if (ret == -EDEADLK)
12250 void intel_release_load_detect_pipe(struct drm_connector *connector,
12251 struct intel_load_detect_pipe *old,
12252 struct drm_modeset_acquire_ctx *ctx)
12254 struct intel_encoder *intel_encoder =
12255 intel_attached_encoder(to_intel_connector(connector));
12256 struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev);
12257 struct drm_encoder *encoder = &intel_encoder->base;
12258 struct drm_atomic_state *state = old->restore_state;
12261 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
12262 connector->base.id, connector->name,
12263 encoder->base.id, encoder->name);
12268 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
12270 drm_dbg_kms(&i915->drm,
12271 "Couldn't release load detect pipe: %i\n", ret);
12272 drm_atomic_state_put(state);
12275 static int i9xx_pll_refclk(struct drm_device *dev,
12276 const struct intel_crtc_state *pipe_config)
12278 struct drm_i915_private *dev_priv = to_i915(dev);
12279 u32 dpll = pipe_config->dpll_hw_state.dpll;
12281 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
12282 return dev_priv->vbt.lvds_ssc_freq;
12283 else if (HAS_PCH_SPLIT(dev_priv))
12285 else if (!IS_GEN(dev_priv, 2))
12291 /* Returns the clock of the currently programmed mode of the given pipe. */
12292 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
12293 struct intel_crtc_state *pipe_config)
12295 struct drm_device *dev = crtc->base.dev;
12296 struct drm_i915_private *dev_priv = to_i915(dev);
12297 enum pipe pipe = crtc->pipe;
12298 u32 dpll = pipe_config->dpll_hw_state.dpll;
12302 int refclk = i9xx_pll_refclk(dev, pipe_config);
12304 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
12305 fp = pipe_config->dpll_hw_state.fp0;
12307 fp = pipe_config->dpll_hw_state.fp1;
12309 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
12310 if (IS_PINEVIEW(dev_priv)) {
12311 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
12312 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
12314 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
12315 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
12318 if (!IS_GEN(dev_priv, 2)) {
12319 if (IS_PINEVIEW(dev_priv))
12320 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
12321 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
12323 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
12324 DPLL_FPA01_P1_POST_DIV_SHIFT);
12326 switch (dpll & DPLL_MODE_MASK) {
12327 case DPLLB_MODE_DAC_SERIAL:
12328 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
12331 case DPLLB_MODE_LVDS:
12332 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
12336 drm_dbg_kms(&dev_priv->drm,
12337 "Unknown DPLL mode %08x in programmed "
12338 "mode\n", (int)(dpll & DPLL_MODE_MASK));
12342 if (IS_PINEVIEW(dev_priv))
12343 port_clock = pnv_calc_dpll_params(refclk, &clock);
12345 port_clock = i9xx_calc_dpll_params(refclk, &clock);
12347 u32 lvds = IS_I830(dev_priv) ? 0 : intel_de_read(dev_priv,
12349 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
12352 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
12353 DPLL_FPA01_P1_POST_DIV_SHIFT);
12355 if (lvds & LVDS_CLKB_POWER_UP)
12360 if (dpll & PLL_P1_DIVIDE_BY_TWO)
12363 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
12364 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
12366 if (dpll & PLL_P2_DIVIDE_BY_4)
12372 port_clock = i9xx_calc_dpll_params(refclk, &clock);
12376 * This value includes pixel_multiplier. We will use
12377 * port_clock to compute adjusted_mode.crtc_clock in the
12378 * encoder's get_config() function.
12380 pipe_config->port_clock = port_clock;
12383 int intel_dotclock_calculate(int link_freq,
12384 const struct intel_link_m_n *m_n)
12387 * The calculation for the data clock is:
12388 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
12389 * But we want to avoid losing precison if possible, so:
12390 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
12392 * and the link clock is simpler:
12393 * link_clock = (m * link_clock) / n
12399 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
12402 static void ilk_pch_clock_get(struct intel_crtc *crtc,
12403 struct intel_crtc_state *pipe_config)
12405 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12407 /* read out port_clock from the DPLL */
12408 i9xx_crtc_clock_get(crtc, pipe_config);
12411 * In case there is an active pipe without active ports,
12412 * we may need some idea for the dotclock anyway.
12413 * Calculate one based on the FDI configuration.
12415 pipe_config->hw.adjusted_mode.crtc_clock =
12416 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12417 &pipe_config->fdi_m_n);
12420 static void intel_crtc_state_reset(struct intel_crtc_state *crtc_state,
12421 struct intel_crtc *crtc)
12423 memset(crtc_state, 0, sizeof(*crtc_state));
12425 __drm_atomic_helper_crtc_state_reset(&crtc_state->uapi, &crtc->base);
12427 crtc_state->cpu_transcoder = INVALID_TRANSCODER;
12428 crtc_state->master_transcoder = INVALID_TRANSCODER;
12429 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
12430 crtc_state->output_format = INTEL_OUTPUT_FORMAT_INVALID;
12431 crtc_state->scaler_state.scaler_id = -1;
12432 crtc_state->mst_master_transcoder = INVALID_TRANSCODER;
12435 static struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc)
12437 struct intel_crtc_state *crtc_state;
12439 crtc_state = kmalloc(sizeof(*crtc_state), GFP_KERNEL);
12442 intel_crtc_state_reset(crtc_state, crtc);
12447 /* Returns the currently programmed mode of the given encoder. */
12448 struct drm_display_mode *
12449 intel_encoder_current_mode(struct intel_encoder *encoder)
12451 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
12452 struct intel_crtc_state *crtc_state;
12453 struct drm_display_mode *mode;
12454 struct intel_crtc *crtc;
12457 if (!encoder->get_hw_state(encoder, &pipe))
12460 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12462 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
12466 crtc_state = intel_crtc_state_alloc(crtc);
12472 if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
12478 encoder->get_config(encoder, crtc_state);
12480 intel_mode_from_pipe_config(mode, crtc_state);
12487 static void intel_crtc_destroy(struct drm_crtc *crtc)
12489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12491 drm_crtc_cleanup(crtc);
12496 * intel_wm_need_update - Check whether watermarks need updating
12497 * @cur: current plane state
12498 * @new: new plane state
12500 * Check current plane state versus the new one to determine whether
12501 * watermarks need to be recalculated.
12503 * Returns true or false.
12505 static bool intel_wm_need_update(const struct intel_plane_state *cur,
12506 struct intel_plane_state *new)
12508 /* Update watermarks on tiling or size changes. */
12509 if (new->uapi.visible != cur->uapi.visible)
12512 if (!cur->hw.fb || !new->hw.fb)
12515 if (cur->hw.fb->modifier != new->hw.fb->modifier ||
12516 cur->hw.rotation != new->hw.rotation ||
12517 drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
12518 drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
12519 drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
12520 drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
12526 static bool needs_scaling(const struct intel_plane_state *state)
12528 int src_w = drm_rect_width(&state->uapi.src) >> 16;
12529 int src_h = drm_rect_height(&state->uapi.src) >> 16;
12530 int dst_w = drm_rect_width(&state->uapi.dst);
12531 int dst_h = drm_rect_height(&state->uapi.dst);
12533 return (src_w != dst_w || src_h != dst_h);
12536 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
12537 struct intel_crtc_state *crtc_state,
12538 const struct intel_plane_state *old_plane_state,
12539 struct intel_plane_state *plane_state)
12541 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12542 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
12543 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12544 bool mode_changed = needs_modeset(crtc_state);
12545 bool was_crtc_enabled = old_crtc_state->hw.active;
12546 bool is_crtc_enabled = crtc_state->hw.active;
12547 bool turn_off, turn_on, visible, was_visible;
12550 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
12551 ret = skl_update_scaler_plane(crtc_state, plane_state);
12556 was_visible = old_plane_state->uapi.visible;
12557 visible = plane_state->uapi.visible;
12559 if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible))
12560 was_visible = false;
12563 * Visibility is calculated as if the crtc was on, but
12564 * after scaler setup everything depends on it being off
12565 * when the crtc isn't active.
12567 * FIXME this is wrong for watermarks. Watermarks should also
12568 * be computed as if the pipe would be active. Perhaps move
12569 * per-plane wm computation to the .check_plane() hook, and
12570 * only combine the results from all planes in the current place?
12572 if (!is_crtc_enabled) {
12573 intel_plane_set_invisible(crtc_state, plane_state);
12577 if (!was_visible && !visible)
12580 turn_off = was_visible && (!visible || mode_changed);
12581 turn_on = visible && (!was_visible || mode_changed);
12583 drm_dbg_atomic(&dev_priv->drm,
12584 "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12585 crtc->base.base.id, crtc->base.name,
12586 plane->base.base.id, plane->base.name,
12587 was_visible, visible,
12588 turn_off, turn_on, mode_changed);
12591 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
12592 crtc_state->update_wm_pre = true;
12594 /* must disable cxsr around plane enable/disable */
12595 if (plane->id != PLANE_CURSOR)
12596 crtc_state->disable_cxsr = true;
12597 } else if (turn_off) {
12598 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
12599 crtc_state->update_wm_post = true;
12601 /* must disable cxsr around plane enable/disable */
12602 if (plane->id != PLANE_CURSOR)
12603 crtc_state->disable_cxsr = true;
12604 } else if (intel_wm_need_update(old_plane_state, plane_state)) {
12605 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
12606 /* FIXME bollocks */
12607 crtc_state->update_wm_pre = true;
12608 crtc_state->update_wm_post = true;
12612 if (visible || was_visible)
12613 crtc_state->fb_bits |= plane->frontbuffer_bit;
12616 * ILK/SNB DVSACNTR/Sprite Enable
12617 * IVB SPR_CTL/Sprite Enable
12618 * "When in Self Refresh Big FIFO mode, a write to enable the
12619 * plane will be internally buffered and delayed while Big FIFO
12620 * mode is exiting."
12622 * Which means that enabling the sprite can take an extra frame
12623 * when we start in big FIFO mode (LP1+). Thus we need to drop
12624 * down to LP0 and wait for vblank in order to make sure the
12625 * sprite gets enabled on the next vblank after the register write.
12626 * Doing otherwise would risk enabling the sprite one frame after
12627 * we've already signalled flip completion. We can resume LP1+
12628 * once the sprite has been enabled.
12631 * WaCxSRDisabledForSpriteScaling:ivb
12632 * IVB SPR_SCALE/Scaling Enable
12633 * "Low Power watermarks must be disabled for at least one
12634 * frame before enabling sprite scaling, and kept disabled
12635 * until sprite scaling is disabled."
12637 * ILK/SNB DVSASCALE/Scaling Enable
12638 * "When in Self Refresh Big FIFO mode, scaling enable will be
12639 * masked off while Big FIFO mode is exiting."
12641 * Despite the w/a only being listed for IVB we assume that
12642 * the ILK/SNB note has similar ramifications, hence we apply
12643 * the w/a on all three platforms.
12645 * With experimental results seems this is needed also for primary
12646 * plane, not only sprite plane.
12648 if (plane->id != PLANE_CURSOR &&
12649 (IS_GEN_RANGE(dev_priv, 5, 6) ||
12650 IS_IVYBRIDGE(dev_priv)) &&
12651 (turn_on || (!needs_scaling(old_plane_state) &&
12652 needs_scaling(plane_state))))
12653 crtc_state->disable_lp_wm = true;
12658 static bool encoders_cloneable(const struct intel_encoder *a,
12659 const struct intel_encoder *b)
12661 /* masks could be asymmetric, so check both ways */
12662 return a == b || (a->cloneable & (1 << b->type) &&
12663 b->cloneable & (1 << a->type));
12666 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12667 struct intel_crtc *crtc,
12668 struct intel_encoder *encoder)
12670 struct intel_encoder *source_encoder;
12671 struct drm_connector *connector;
12672 struct drm_connector_state *connector_state;
12675 for_each_new_connector_in_state(state, connector, connector_state, i) {
12676 if (connector_state->crtc != &crtc->base)
12680 to_intel_encoder(connector_state->best_encoder);
12681 if (!encoders_cloneable(encoder, source_encoder))
12688 static int icl_add_linked_planes(struct intel_atomic_state *state)
12690 struct intel_plane *plane, *linked;
12691 struct intel_plane_state *plane_state, *linked_plane_state;
12694 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12695 linked = plane_state->planar_linked_plane;
12700 linked_plane_state = intel_atomic_get_plane_state(state, linked);
12701 if (IS_ERR(linked_plane_state))
12702 return PTR_ERR(linked_plane_state);
12704 drm_WARN_ON(state->base.dev,
12705 linked_plane_state->planar_linked_plane != plane);
12706 drm_WARN_ON(state->base.dev,
12707 linked_plane_state->planar_slave == plane_state->planar_slave);
12713 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
12715 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12716 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12717 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
12718 struct intel_plane *plane, *linked;
12719 struct intel_plane_state *plane_state;
12722 if (INTEL_GEN(dev_priv) < 11)
12726 * Destroy all old plane links and make the slave plane invisible
12727 * in the crtc_state->active_planes mask.
12729 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12730 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
12733 plane_state->planar_linked_plane = NULL;
12734 if (plane_state->planar_slave && !plane_state->uapi.visible) {
12735 crtc_state->active_planes &= ~BIT(plane->id);
12736 crtc_state->update_planes |= BIT(plane->id);
12739 plane_state->planar_slave = false;
12742 if (!crtc_state->nv12_planes)
12745 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12746 struct intel_plane_state *linked_state = NULL;
12748 if (plane->pipe != crtc->pipe ||
12749 !(crtc_state->nv12_planes & BIT(plane->id)))
12752 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
12753 if (!icl_is_nv12_y_plane(dev_priv, linked->id))
12756 if (crtc_state->active_planes & BIT(linked->id))
12759 linked_state = intel_atomic_get_plane_state(state, linked);
12760 if (IS_ERR(linked_state))
12761 return PTR_ERR(linked_state);
12766 if (!linked_state) {
12767 drm_dbg_kms(&dev_priv->drm,
12768 "Need %d free Y planes for planar YUV\n",
12769 hweight8(crtc_state->nv12_planes));
12774 plane_state->planar_linked_plane = linked;
12776 linked_state->planar_slave = true;
12777 linked_state->planar_linked_plane = plane;
12778 crtc_state->active_planes |= BIT(linked->id);
12779 crtc_state->update_planes |= BIT(linked->id);
12780 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
12781 linked->base.name, plane->base.name);
12783 /* Copy parameters to slave plane */
12784 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
12785 linked_state->color_ctl = plane_state->color_ctl;
12786 linked_state->view = plane_state->view;
12787 memcpy(linked_state->color_plane, plane_state->color_plane,
12788 sizeof(linked_state->color_plane));
12790 intel_plane_copy_uapi_to_hw_state(linked_state, plane_state);
12791 linked_state->uapi.src = plane_state->uapi.src;
12792 linked_state->uapi.dst = plane_state->uapi.dst;
12794 if (icl_is_hdr_plane(dev_priv, plane->id)) {
12795 if (linked->id == PLANE_SPRITE5)
12796 plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
12797 else if (linked->id == PLANE_SPRITE4)
12798 plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
12799 else if (linked->id == PLANE_SPRITE3)
12800 plane_state->cus_ctl |= PLANE_CUS_PLANE_5_RKL;
12801 else if (linked->id == PLANE_SPRITE2)
12802 plane_state->cus_ctl |= PLANE_CUS_PLANE_4_RKL;
12804 MISSING_CASE(linked->id);
12811 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
12813 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
12814 struct intel_atomic_state *state =
12815 to_intel_atomic_state(new_crtc_state->uapi.state);
12816 const struct intel_crtc_state *old_crtc_state =
12817 intel_atomic_get_old_crtc_state(state, crtc);
12819 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
12822 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
12824 const struct drm_display_mode *adjusted_mode =
12825 &crtc_state->hw.adjusted_mode;
12828 if (!crtc_state->hw.enable)
12831 linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
12832 adjusted_mode->crtc_clock);
12834 return min(linetime_wm, 0x1ff);
12837 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
12838 const struct intel_cdclk_state *cdclk_state)
12840 const struct drm_display_mode *adjusted_mode =
12841 &crtc_state->hw.adjusted_mode;
12844 if (!crtc_state->hw.enable)
12847 linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
12848 cdclk_state->logical.cdclk);
12850 return min(linetime_wm, 0x1ff);
12853 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
12855 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12856 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12857 const struct drm_display_mode *adjusted_mode =
12858 &crtc_state->hw.adjusted_mode;
12861 if (!crtc_state->hw.enable)
12864 linetime_wm = DIV_ROUND_UP(adjusted_mode->crtc_htotal * 1000 * 8,
12865 crtc_state->pixel_rate);
12867 /* Display WA #1135: BXT:ALL GLK:ALL */
12868 if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled)
12871 return min(linetime_wm, 0x1ff);
12874 static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
12875 struct intel_crtc *crtc)
12877 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12878 struct intel_crtc_state *crtc_state =
12879 intel_atomic_get_new_crtc_state(state, crtc);
12880 const struct intel_cdclk_state *cdclk_state;
12882 if (INTEL_GEN(dev_priv) >= 9)
12883 crtc_state->linetime = skl_linetime_wm(crtc_state);
12885 crtc_state->linetime = hsw_linetime_wm(crtc_state);
12887 if (!hsw_crtc_supports_ips(crtc))
12890 cdclk_state = intel_atomic_get_cdclk_state(state);
12891 if (IS_ERR(cdclk_state))
12892 return PTR_ERR(cdclk_state);
12894 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
12900 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
12901 struct intel_crtc *crtc)
12903 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12904 struct intel_crtc_state *crtc_state =
12905 intel_atomic_get_new_crtc_state(state, crtc);
12906 bool mode_changed = needs_modeset(crtc_state);
12909 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
12910 mode_changed && !crtc_state->hw.active)
12911 crtc_state->update_wm_post = true;
12913 if (mode_changed && crtc_state->hw.enable &&
12914 dev_priv->display.crtc_compute_clock &&
12915 !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
12916 ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
12922 * May need to update pipe gamma enable bits
12923 * when C8 planes are getting enabled/disabled.
12925 if (c8_planes_changed(crtc_state))
12926 crtc_state->uapi.color_mgmt_changed = true;
12928 if (mode_changed || crtc_state->update_pipe ||
12929 crtc_state->uapi.color_mgmt_changed) {
12930 ret = intel_color_check(crtc_state);
12935 if (dev_priv->display.compute_pipe_wm) {
12936 ret = dev_priv->display.compute_pipe_wm(crtc_state);
12938 drm_dbg_kms(&dev_priv->drm,
12939 "Target pipe watermarks are invalid\n");
12944 if (dev_priv->display.compute_intermediate_wm) {
12945 if (drm_WARN_ON(&dev_priv->drm,
12946 !dev_priv->display.compute_pipe_wm))
12950 * Calculate 'intermediate' watermarks that satisfy both the
12951 * old state and the new state. We can program these
12954 ret = dev_priv->display.compute_intermediate_wm(crtc_state);
12956 drm_dbg_kms(&dev_priv->drm,
12957 "No valid intermediate pipe watermarks are possible\n");
12962 if (INTEL_GEN(dev_priv) >= 9) {
12963 if (mode_changed || crtc_state->update_pipe) {
12964 ret = skl_update_scaler_crtc(crtc_state);
12969 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state);
12974 if (HAS_IPS(dev_priv)) {
12975 ret = hsw_compute_ips_config(crtc_state);
12980 if (INTEL_GEN(dev_priv) >= 9 ||
12981 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
12982 ret = hsw_compute_linetime_wm(state, crtc);
12988 if (!mode_changed) {
12989 ret = intel_psr2_sel_fetch_update(state, crtc);
12997 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12999 struct intel_connector *connector;
13000 struct drm_connector_list_iter conn_iter;
13002 drm_connector_list_iter_begin(dev, &conn_iter);
13003 for_each_intel_connector_iter(connector, &conn_iter) {
13004 if (connector->base.state->crtc)
13005 drm_connector_put(&connector->base);
13007 if (connector->base.encoder) {
13008 connector->base.state->best_encoder =
13009 connector->base.encoder;
13010 connector->base.state->crtc =
13011 connector->base.encoder->crtc;
13013 drm_connector_get(&connector->base);
13015 connector->base.state->best_encoder = NULL;
13016 connector->base.state->crtc = NULL;
13019 drm_connector_list_iter_end(&conn_iter);
13023 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
13024 struct intel_crtc_state *pipe_config)
13026 struct drm_connector *connector = conn_state->connector;
13027 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
13028 const struct drm_display_info *info = &connector->display_info;
13031 switch (conn_state->max_bpc) {
13048 if (bpp < pipe_config->pipe_bpp) {
13049 drm_dbg_kms(&i915->drm,
13050 "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
13051 "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
13052 connector->base.id, connector->name,
13053 bpp, 3 * info->bpc,
13054 3 * conn_state->max_requested_bpc,
13055 pipe_config->pipe_bpp);
13057 pipe_config->pipe_bpp = bpp;
13064 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
13065 struct intel_crtc_state *pipe_config)
13067 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13068 struct drm_atomic_state *state = pipe_config->uapi.state;
13069 struct drm_connector *connector;
13070 struct drm_connector_state *connector_state;
13073 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
13074 IS_CHERRYVIEW(dev_priv)))
13076 else if (INTEL_GEN(dev_priv) >= 5)
13081 pipe_config->pipe_bpp = bpp;
13083 /* Clamp display bpp to connector max bpp */
13084 for_each_new_connector_in_state(state, connector, connector_state, i) {
13087 if (connector_state->crtc != &crtc->base)
13090 ret = compute_sink_pipe_bpp(connector_state, pipe_config);
13098 static void intel_dump_crtc_timings(struct drm_i915_private *i915,
13099 const struct drm_display_mode *mode)
13101 drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, "
13102 "type: 0x%x flags: 0x%x\n",
13104 mode->crtc_hdisplay, mode->crtc_hsync_start,
13105 mode->crtc_hsync_end, mode->crtc_htotal,
13106 mode->crtc_vdisplay, mode->crtc_vsync_start,
13107 mode->crtc_vsync_end, mode->crtc_vtotal,
13108 mode->type, mode->flags);
13112 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
13113 const char *id, unsigned int lane_count,
13114 const struct intel_link_m_n *m_n)
13116 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
13118 drm_dbg_kms(&i915->drm,
13119 "%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
13121 m_n->gmch_m, m_n->gmch_n,
13122 m_n->link_m, m_n->link_n, m_n->tu);
13126 intel_dump_infoframe(struct drm_i915_private *dev_priv,
13127 const union hdmi_infoframe *frame)
13129 if (!drm_debug_enabled(DRM_UT_KMS))
13132 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
13136 intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
13137 const struct drm_dp_vsc_sdp *vsc)
13139 if (!drm_debug_enabled(DRM_UT_KMS))
13142 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
13145 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
13147 static const char * const output_type_str[] = {
13148 OUTPUT_TYPE(UNUSED),
13149 OUTPUT_TYPE(ANALOG),
13153 OUTPUT_TYPE(TVOUT),
13159 OUTPUT_TYPE(DP_MST),
13164 static void snprintf_output_types(char *buf, size_t len,
13165 unsigned int output_types)
13172 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
13175 if ((output_types & BIT(i)) == 0)
13178 r = snprintf(str, len, "%s%s",
13179 str != buf ? "," : "", output_type_str[i]);
13185 output_types &= ~BIT(i);
13188 WARN_ON_ONCE(output_types != 0);
13191 static const char * const output_format_str[] = {
13192 [INTEL_OUTPUT_FORMAT_INVALID] = "Invalid",
13193 [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
13194 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
13195 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
13198 static const char *output_formats(enum intel_output_format format)
13200 if (format >= ARRAY_SIZE(output_format_str))
13201 format = INTEL_OUTPUT_FORMAT_INVALID;
13202 return output_format_str[format];
13205 static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
13207 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
13208 struct drm_i915_private *i915 = to_i915(plane->base.dev);
13209 const struct drm_framebuffer *fb = plane_state->hw.fb;
13210 struct drm_format_name_buf format_name;
13213 drm_dbg_kms(&i915->drm,
13214 "[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
13215 plane->base.base.id, plane->base.name,
13216 yesno(plane_state->uapi.visible));
13220 drm_dbg_kms(&i915->drm,
13221 "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s, visible: %s\n",
13222 plane->base.base.id, plane->base.name,
13223 fb->base.id, fb->width, fb->height,
13224 drm_get_format_name(fb->format->format, &format_name),
13225 yesno(plane_state->uapi.visible));
13226 drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n",
13227 plane_state->hw.rotation, plane_state->scaler_id);
13228 if (plane_state->uapi.visible)
13229 drm_dbg_kms(&i915->drm,
13230 "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
13231 DRM_RECT_FP_ARG(&plane_state->uapi.src),
13232 DRM_RECT_ARG(&plane_state->uapi.dst));
13235 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
13236 struct intel_atomic_state *state,
13237 const char *context)
13239 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
13240 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13241 const struct intel_plane_state *plane_state;
13242 struct intel_plane *plane;
13246 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n",
13247 crtc->base.base.id, crtc->base.name,
13248 yesno(pipe_config->hw.enable), context);
13250 if (!pipe_config->hw.enable)
13253 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
13254 drm_dbg_kms(&dev_priv->drm,
13255 "active: %s, output_types: %s (0x%x), output format: %s\n",
13256 yesno(pipe_config->hw.active),
13257 buf, pipe_config->output_types,
13258 output_formats(pipe_config->output_format));
13260 drm_dbg_kms(&dev_priv->drm,
13261 "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
13262 transcoder_name(pipe_config->cpu_transcoder),
13263 pipe_config->pipe_bpp, pipe_config->dither);
13265 drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n",
13266 transcoder_name(pipe_config->mst_master_transcoder));
13268 drm_dbg_kms(&dev_priv->drm,
13269 "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n",
13270 transcoder_name(pipe_config->master_transcoder),
13271 pipe_config->sync_mode_slaves_mask);
13273 if (pipe_config->has_pch_encoder)
13274 intel_dump_m_n_config(pipe_config, "fdi",
13275 pipe_config->fdi_lanes,
13276 &pipe_config->fdi_m_n);
13278 if (intel_crtc_has_dp_encoder(pipe_config)) {
13279 intel_dump_m_n_config(pipe_config, "dp m_n",
13280 pipe_config->lane_count, &pipe_config->dp_m_n);
13281 if (pipe_config->has_drrs)
13282 intel_dump_m_n_config(pipe_config, "dp m2_n2",
13283 pipe_config->lane_count,
13284 &pipe_config->dp_m2_n2);
13287 drm_dbg_kms(&dev_priv->drm,
13288 "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
13289 pipe_config->has_audio, pipe_config->has_infoframe,
13290 pipe_config->infoframes.enable);
13292 if (pipe_config->infoframes.enable &
13293 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
13294 drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n",
13295 pipe_config->infoframes.gcp);
13296 if (pipe_config->infoframes.enable &
13297 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
13298 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
13299 if (pipe_config->infoframes.enable &
13300 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
13301 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
13302 if (pipe_config->infoframes.enable &
13303 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
13304 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
13305 if (pipe_config->infoframes.enable &
13306 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
13307 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
13308 if (pipe_config->infoframes.enable &
13309 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
13310 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
13311 if (pipe_config->infoframes.enable &
13312 intel_hdmi_infoframe_enable(DP_SDP_VSC))
13313 intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
13315 drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
13316 drm_mode_debug_printmodeline(&pipe_config->hw.mode);
13317 drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n");
13318 drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
13319 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode);
13320 drm_dbg_kms(&dev_priv->drm,
13321 "port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
13322 pipe_config->port_clock,
13323 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
13324 pipe_config->pixel_rate);
13326 drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n",
13327 pipe_config->linetime, pipe_config->ips_linetime);
13329 if (INTEL_GEN(dev_priv) >= 9)
13330 drm_dbg_kms(&dev_priv->drm,
13331 "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
13333 pipe_config->scaler_state.scaler_users,
13334 pipe_config->scaler_state.scaler_id);
13336 if (HAS_GMCH(dev_priv))
13337 drm_dbg_kms(&dev_priv->drm,
13338 "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
13339 pipe_config->gmch_pfit.control,
13340 pipe_config->gmch_pfit.pgm_ratios,
13341 pipe_config->gmch_pfit.lvds_border_bits);
13343 drm_dbg_kms(&dev_priv->drm,
13344 "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
13345 DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
13346 enableddisabled(pipe_config->pch_pfit.enabled),
13347 yesno(pipe_config->pch_pfit.force_thru));
13349 drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i\n",
13350 pipe_config->ips_enabled, pipe_config->double_wide);
13352 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
13354 if (IS_CHERRYVIEW(dev_priv))
13355 drm_dbg_kms(&dev_priv->drm,
13356 "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
13357 pipe_config->cgm_mode, pipe_config->gamma_mode,
13358 pipe_config->gamma_enable, pipe_config->csc_enable);
13360 drm_dbg_kms(&dev_priv->drm,
13361 "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
13362 pipe_config->csc_mode, pipe_config->gamma_mode,
13363 pipe_config->gamma_enable, pipe_config->csc_enable);
13365 drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n",
13366 pipe_config->hw.degamma_lut ?
13367 drm_color_lut_size(pipe_config->hw.degamma_lut) : 0,
13368 pipe_config->hw.gamma_lut ?
13369 drm_color_lut_size(pipe_config->hw.gamma_lut) : 0);
13375 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
13376 if (plane->pipe == crtc->pipe)
13377 intel_dump_plane_state(plane_state);
13381 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
13383 struct drm_device *dev = state->base.dev;
13384 struct drm_connector *connector;
13385 struct drm_connector_list_iter conn_iter;
13386 unsigned int used_ports = 0;
13387 unsigned int used_mst_ports = 0;
13391 * We're going to peek into connector->state,
13392 * hence connection_mutex must be held.
13394 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
13397 * Walk the connector list instead of the encoder
13398 * list to detect the problem on ddi platforms
13399 * where there's just one encoder per digital port.
13401 drm_connector_list_iter_begin(dev, &conn_iter);
13402 drm_for_each_connector_iter(connector, &conn_iter) {
13403 struct drm_connector_state *connector_state;
13404 struct intel_encoder *encoder;
13407 drm_atomic_get_new_connector_state(&state->base,
13409 if (!connector_state)
13410 connector_state = connector->state;
13412 if (!connector_state->best_encoder)
13415 encoder = to_intel_encoder(connector_state->best_encoder);
13417 drm_WARN_ON(dev, !connector_state->crtc);
13419 switch (encoder->type) {
13420 case INTEL_OUTPUT_DDI:
13421 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev))))
13424 case INTEL_OUTPUT_DP:
13425 case INTEL_OUTPUT_HDMI:
13426 case INTEL_OUTPUT_EDP:
13427 /* the same port mustn't appear more than once */
13428 if (used_ports & BIT(encoder->port))
13431 used_ports |= BIT(encoder->port);
13433 case INTEL_OUTPUT_DP_MST:
13435 1 << encoder->port;
13441 drm_connector_list_iter_end(&conn_iter);
13443 /* can't mix MST and SST/HDMI on the same port */
13444 if (used_ports & used_mst_ports)
13451 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_crtc_state *crtc_state)
13453 intel_crtc_copy_color_blobs(crtc_state);
13457 intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
13459 crtc_state->hw.enable = crtc_state->uapi.enable;
13460 crtc_state->hw.active = crtc_state->uapi.active;
13461 crtc_state->hw.mode = crtc_state->uapi.mode;
13462 crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
13463 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
13464 intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
13467 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
13469 crtc_state->uapi.enable = crtc_state->hw.enable;
13470 crtc_state->uapi.active = crtc_state->hw.active;
13471 drm_WARN_ON(crtc_state->uapi.crtc->dev,
13472 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
13474 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
13475 crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter;
13477 /* copy color blobs to uapi */
13478 drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
13479 crtc_state->hw.degamma_lut);
13480 drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
13481 crtc_state->hw.gamma_lut);
13482 drm_property_replace_blob(&crtc_state->uapi.ctm,
13483 crtc_state->hw.ctm);
13487 intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
13489 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
13490 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13491 struct intel_crtc_state *saved_state;
13493 saved_state = intel_crtc_state_alloc(crtc);
13497 /* free the old crtc_state->hw members */
13498 intel_crtc_free_hw_state(crtc_state);
13500 /* FIXME: before the switch to atomic started, a new pipe_config was
13501 * kzalloc'd. Code that depends on any field being zero should be
13502 * fixed, so that the crtc_state can be safely duplicated. For now,
13503 * only fields that are know to not cause problems are preserved. */
13505 saved_state->uapi = crtc_state->uapi;
13506 saved_state->scaler_state = crtc_state->scaler_state;
13507 saved_state->shared_dpll = crtc_state->shared_dpll;
13508 saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
13509 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
13510 sizeof(saved_state->icl_port_dplls));
13511 saved_state->crc_enabled = crtc_state->crc_enabled;
13512 if (IS_G4X(dev_priv) ||
13513 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13514 saved_state->wm = crtc_state->wm;
13516 memcpy(crtc_state, saved_state, sizeof(*crtc_state));
13517 kfree(saved_state);
13519 intel_crtc_copy_uapi_to_hw_state(crtc_state);
13525 intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
13527 struct drm_crtc *crtc = pipe_config->uapi.crtc;
13528 struct drm_atomic_state *state = pipe_config->uapi.state;
13529 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
13530 struct drm_connector *connector;
13531 struct drm_connector_state *connector_state;
13532 int base_bpp, ret, i;
13535 pipe_config->cpu_transcoder =
13536 (enum transcoder) to_intel_crtc(crtc)->pipe;
13539 * Sanitize sync polarity flags based on requested ones. If neither
13540 * positive or negative polarity is requested, treat this as meaning
13541 * negative polarity.
13543 if (!(pipe_config->hw.adjusted_mode.flags &
13544 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
13545 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
13547 if (!(pipe_config->hw.adjusted_mode.flags &
13548 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
13549 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
13551 ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
13556 base_bpp = pipe_config->pipe_bpp;
13559 * Determine the real pipe dimensions. Note that stereo modes can
13560 * increase the actual pipe size due to the frame doubling and
13561 * insertion of additional space for blanks between the frame. This
13562 * is stored in the crtc timings. We use the requested mode to do this
13563 * computation to clearly distinguish it from the adjusted mode, which
13564 * can be changed by the connectors in the below retry loop.
13566 drm_mode_get_hv_timing(&pipe_config->hw.mode,
13567 &pipe_config->pipe_src_w,
13568 &pipe_config->pipe_src_h);
13570 for_each_new_connector_in_state(state, connector, connector_state, i) {
13571 struct intel_encoder *encoder =
13572 to_intel_encoder(connector_state->best_encoder);
13574 if (connector_state->crtc != crtc)
13577 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
13578 drm_dbg_kms(&i915->drm,
13579 "rejecting invalid cloning configuration\n");
13584 * Determine output_types before calling the .compute_config()
13585 * hooks so that the hooks can use this information safely.
13587 if (encoder->compute_output_type)
13588 pipe_config->output_types |=
13589 BIT(encoder->compute_output_type(encoder, pipe_config,
13592 pipe_config->output_types |= BIT(encoder->type);
13596 /* Ensure the port clock defaults are reset when retrying. */
13597 pipe_config->port_clock = 0;
13598 pipe_config->pixel_multiplier = 1;
13600 /* Fill in default crtc timings, allow encoders to overwrite them. */
13601 drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,
13602 CRTC_STEREO_DOUBLE);
13604 /* Pass our mode to the connectors and the CRTC to give them a chance to
13605 * adjust it according to limitations or connector properties, and also
13606 * a chance to reject the mode entirely.
13608 for_each_new_connector_in_state(state, connector, connector_state, i) {
13609 struct intel_encoder *encoder =
13610 to_intel_encoder(connector_state->best_encoder);
13612 if (connector_state->crtc != crtc)
13615 ret = encoder->compute_config(encoder, pipe_config,
13618 if (ret != -EDEADLK)
13619 drm_dbg_kms(&i915->drm,
13620 "Encoder config failure: %d\n",
13626 /* Set default port clock if not overwritten by the encoder. Needs to be
13627 * done afterwards in case the encoder adjusts the mode. */
13628 if (!pipe_config->port_clock)
13629 pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
13630 * pipe_config->pixel_multiplier;
13632 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
13633 if (ret == -EDEADLK)
13636 drm_dbg_kms(&i915->drm, "CRTC fixup failed\n");
13640 if (ret == RETRY) {
13641 if (drm_WARN(&i915->drm, !retry,
13642 "loop in pipe configuration computation\n"))
13645 drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n");
13647 goto encoder_retry;
13650 /* Dithering seems to not pass-through bits correctly when it should, so
13651 * only enable it on 6bpc panels and when its not a compliance
13652 * test requesting 6bpc video pattern.
13654 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
13655 !pipe_config->dither_force_disable;
13656 drm_dbg_kms(&i915->drm,
13657 "hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
13658 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
13661 * Make drm_calc_timestamping_constants in
13662 * drm_atomic_helper_update_legacy_modeset_state() happy
13664 pipe_config->uapi.adjusted_mode = pipe_config->hw.adjusted_mode;
13670 intel_modeset_pipe_config_late(struct intel_crtc_state *crtc_state)
13672 struct intel_atomic_state *state =
13673 to_intel_atomic_state(crtc_state->uapi.state);
13674 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
13675 struct drm_connector_state *conn_state;
13676 struct drm_connector *connector;
13679 for_each_new_connector_in_state(&state->base, connector,
13681 struct intel_encoder *encoder =
13682 to_intel_encoder(conn_state->best_encoder);
13685 if (conn_state->crtc != &crtc->base ||
13686 !encoder->compute_config_late)
13689 ret = encoder->compute_config_late(encoder, crtc_state,
13698 bool intel_fuzzy_clock_check(int clock1, int clock2)
13702 if (clock1 == clock2)
13705 if (!clock1 || !clock2)
13708 diff = abs(clock1 - clock2);
13710 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
13717 intel_compare_m_n(unsigned int m, unsigned int n,
13718 unsigned int m2, unsigned int n2,
13721 if (m == m2 && n == n2)
13724 if (exact || !m || !n || !m2 || !n2)
13727 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
13734 } else if (n < n2) {
13744 return intel_fuzzy_clock_check(m, m2);
13748 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
13749 const struct intel_link_m_n *m2_n2,
13752 return m_n->tu == m2_n2->tu &&
13753 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
13754 m2_n2->gmch_m, m2_n2->gmch_n, exact) &&
13755 intel_compare_m_n(m_n->link_m, m_n->link_n,
13756 m2_n2->link_m, m2_n2->link_n, exact);
13760 intel_compare_infoframe(const union hdmi_infoframe *a,
13761 const union hdmi_infoframe *b)
13763 return memcmp(a, b, sizeof(*a)) == 0;
13767 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
13768 const struct drm_dp_vsc_sdp *b)
13770 return memcmp(a, b, sizeof(*a)) == 0;
13774 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
13775 bool fastset, const char *name,
13776 const union hdmi_infoframe *a,
13777 const union hdmi_infoframe *b)
13780 if (!drm_debug_enabled(DRM_UT_KMS))
13783 drm_dbg_kms(&dev_priv->drm,
13784 "fastset mismatch in %s infoframe\n", name);
13785 drm_dbg_kms(&dev_priv->drm, "expected:\n");
13786 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
13787 drm_dbg_kms(&dev_priv->drm, "found:\n");
13788 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
13790 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name);
13791 drm_err(&dev_priv->drm, "expected:\n");
13792 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
13793 drm_err(&dev_priv->drm, "found:\n");
13794 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
13799 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
13800 bool fastset, const char *name,
13801 const struct drm_dp_vsc_sdp *a,
13802 const struct drm_dp_vsc_sdp *b)
13805 if (!drm_debug_enabled(DRM_UT_KMS))
13808 drm_dbg_kms(&dev_priv->drm,
13809 "fastset mismatch in %s dp sdp\n", name);
13810 drm_dbg_kms(&dev_priv->drm, "expected:\n");
13811 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
13812 drm_dbg_kms(&dev_priv->drm, "found:\n");
13813 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
13815 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name);
13816 drm_err(&dev_priv->drm, "expected:\n");
13817 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
13818 drm_err(&dev_priv->drm, "found:\n");
13819 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
13823 static void __printf(4, 5)
13824 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
13825 const char *name, const char *format, ...)
13827 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
13828 struct va_format vaf;
13831 va_start(args, format);
13836 drm_dbg_kms(&i915->drm,
13837 "[CRTC:%d:%s] fastset mismatch in %s %pV\n",
13838 crtc->base.base.id, crtc->base.name, name, &vaf);
13840 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n",
13841 crtc->base.base.id, crtc->base.name, name, &vaf);
13846 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
13848 if (dev_priv->params.fastboot != -1)
13849 return dev_priv->params.fastboot;
13851 /* Enable fastboot by default on Skylake and newer */
13852 if (INTEL_GEN(dev_priv) >= 9)
13855 /* Enable fastboot by default on VLV and CHV */
13856 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13859 /* Disabled by default on all others */
13864 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
13865 const struct intel_crtc_state *pipe_config,
13868 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
13869 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
13872 bool fixup_inherited = fastset &&
13873 current_config->inherited && !pipe_config->inherited;
13875 if (fixup_inherited && !fastboot_enabled(dev_priv)) {
13876 drm_dbg_kms(&dev_priv->drm,
13877 "initial modeset and fastboot not set\n");
13881 #define PIPE_CONF_CHECK_X(name) do { \
13882 if (current_config->name != pipe_config->name) { \
13883 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13884 "(expected 0x%08x, found 0x%08x)", \
13885 current_config->name, \
13886 pipe_config->name); \
13891 #define PIPE_CONF_CHECK_I(name) do { \
13892 if (current_config->name != pipe_config->name) { \
13893 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13894 "(expected %i, found %i)", \
13895 current_config->name, \
13896 pipe_config->name); \
13901 #define PIPE_CONF_CHECK_BOOL(name) do { \
13902 if (current_config->name != pipe_config->name) { \
13903 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13904 "(expected %s, found %s)", \
13905 yesno(current_config->name), \
13906 yesno(pipe_config->name)); \
13912 * Checks state where we only read out the enabling, but not the entire
13913 * state itself (like full infoframes or ELD for audio). These states
13914 * require a full modeset on bootup to fix up.
13916 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
13917 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
13918 PIPE_CONF_CHECK_BOOL(name); \
13920 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13921 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
13922 yesno(current_config->name), \
13923 yesno(pipe_config->name)); \
13928 #define PIPE_CONF_CHECK_P(name) do { \
13929 if (current_config->name != pipe_config->name) { \
13930 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13931 "(expected %p, found %p)", \
13932 current_config->name, \
13933 pipe_config->name); \
13938 #define PIPE_CONF_CHECK_M_N(name) do { \
13939 if (!intel_compare_link_m_n(¤t_config->name, \
13940 &pipe_config->name,\
13942 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13943 "(expected tu %i gmch %i/%i link %i/%i, " \
13944 "found tu %i, gmch %i/%i link %i/%i)", \
13945 current_config->name.tu, \
13946 current_config->name.gmch_m, \
13947 current_config->name.gmch_n, \
13948 current_config->name.link_m, \
13949 current_config->name.link_n, \
13950 pipe_config->name.tu, \
13951 pipe_config->name.gmch_m, \
13952 pipe_config->name.gmch_n, \
13953 pipe_config->name.link_m, \
13954 pipe_config->name.link_n); \
13959 /* This is required for BDW+ where there is only one set of registers for
13960 * switching between high and low RR.
13961 * This macro can be used whenever a comparison has to be made between one
13962 * hw state and multiple sw state variables.
13964 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
13965 if (!intel_compare_link_m_n(¤t_config->name, \
13966 &pipe_config->name, !fastset) && \
13967 !intel_compare_link_m_n(¤t_config->alt_name, \
13968 &pipe_config->name, !fastset)) { \
13969 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13970 "(expected tu %i gmch %i/%i link %i/%i, " \
13971 "or tu %i gmch %i/%i link %i/%i, " \
13972 "found tu %i, gmch %i/%i link %i/%i)", \
13973 current_config->name.tu, \
13974 current_config->name.gmch_m, \
13975 current_config->name.gmch_n, \
13976 current_config->name.link_m, \
13977 current_config->name.link_n, \
13978 current_config->alt_name.tu, \
13979 current_config->alt_name.gmch_m, \
13980 current_config->alt_name.gmch_n, \
13981 current_config->alt_name.link_m, \
13982 current_config->alt_name.link_n, \
13983 pipe_config->name.tu, \
13984 pipe_config->name.gmch_m, \
13985 pipe_config->name.gmch_n, \
13986 pipe_config->name.link_m, \
13987 pipe_config->name.link_n); \
13992 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
13993 if ((current_config->name ^ pipe_config->name) & (mask)) { \
13994 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13995 "(%x) (expected %i, found %i)", \
13997 current_config->name & (mask), \
13998 pipe_config->name & (mask)); \
14003 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
14004 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
14005 pipe_config_mismatch(fastset, crtc, __stringify(name), \
14006 "(expected %i, found %i)", \
14007 current_config->name, \
14008 pipe_config->name); \
14013 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
14014 if (!intel_compare_infoframe(¤t_config->infoframes.name, \
14015 &pipe_config->infoframes.name)) { \
14016 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
14017 ¤t_config->infoframes.name, \
14018 &pipe_config->infoframes.name); \
14023 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
14024 if (!current_config->has_psr && !pipe_config->has_psr && \
14025 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \
14026 &pipe_config->infoframes.name)) { \
14027 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
14028 ¤t_config->infoframes.name, \
14029 &pipe_config->infoframes.name); \
14034 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
14035 if (current_config->name1 != pipe_config->name1) { \
14036 pipe_config_mismatch(fastset, crtc, __stringify(name1), \
14037 "(expected %i, found %i, won't compare lut values)", \
14038 current_config->name1, \
14039 pipe_config->name1); \
14042 if (!intel_color_lut_equal(current_config->name2, \
14043 pipe_config->name2, pipe_config->name1, \
14044 bit_precision)) { \
14045 pipe_config_mismatch(fastset, crtc, __stringify(name2), \
14046 "hw_state doesn't match sw_state"); \
14052 #define PIPE_CONF_QUIRK(quirk) \
14053 ((current_config->quirks | pipe_config->quirks) & (quirk))
14055 PIPE_CONF_CHECK_I(cpu_transcoder);
14057 PIPE_CONF_CHECK_BOOL(has_pch_encoder);
14058 PIPE_CONF_CHECK_I(fdi_lanes);
14059 PIPE_CONF_CHECK_M_N(fdi_m_n);
14061 PIPE_CONF_CHECK_I(lane_count);
14062 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
14064 if (INTEL_GEN(dev_priv) < 8) {
14065 PIPE_CONF_CHECK_M_N(dp_m_n);
14067 if (current_config->has_drrs)
14068 PIPE_CONF_CHECK_M_N(dp_m2_n2);
14070 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
14072 PIPE_CONF_CHECK_X(output_types);
14074 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
14075 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
14076 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
14077 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
14078 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
14079 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
14081 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
14082 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
14083 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
14084 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
14085 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
14086 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
14088 PIPE_CONF_CHECK_I(pixel_multiplier);
14089 PIPE_CONF_CHECK_I(output_format);
14090 PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
14091 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
14092 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14093 PIPE_CONF_CHECK_BOOL(limited_color_range);
14095 PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
14096 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
14097 PIPE_CONF_CHECK_BOOL(has_infoframe);
14098 PIPE_CONF_CHECK_BOOL(fec_enable);
14100 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
14102 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
14103 DRM_MODE_FLAG_INTERLACE);
14105 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
14106 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
14107 DRM_MODE_FLAG_PHSYNC);
14108 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
14109 DRM_MODE_FLAG_NHSYNC);
14110 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
14111 DRM_MODE_FLAG_PVSYNC);
14112 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
14113 DRM_MODE_FLAG_NVSYNC);
14116 PIPE_CONF_CHECK_X(gmch_pfit.control);
14117 /* pfit ratios are autocomputed by the hw on gen4+ */
14118 if (INTEL_GEN(dev_priv) < 4)
14119 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
14120 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
14123 * Changing the EDP transcoder input mux
14124 * (A_ONOFF vs. A_ON) requires a full modeset.
14126 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
14129 PIPE_CONF_CHECK_I(pipe_src_w);
14130 PIPE_CONF_CHECK_I(pipe_src_h);
14132 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
14133 if (current_config->pch_pfit.enabled) {
14134 PIPE_CONF_CHECK_I(pch_pfit.dst.x1);
14135 PIPE_CONF_CHECK_I(pch_pfit.dst.y1);
14136 PIPE_CONF_CHECK_I(pch_pfit.dst.x2);
14137 PIPE_CONF_CHECK_I(pch_pfit.dst.y2);
14140 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
14141 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
14143 PIPE_CONF_CHECK_X(gamma_mode);
14144 if (IS_CHERRYVIEW(dev_priv))
14145 PIPE_CONF_CHECK_X(cgm_mode);
14147 PIPE_CONF_CHECK_X(csc_mode);
14148 PIPE_CONF_CHECK_BOOL(gamma_enable);
14149 PIPE_CONF_CHECK_BOOL(csc_enable);
14151 PIPE_CONF_CHECK_I(linetime);
14152 PIPE_CONF_CHECK_I(ips_linetime);
14154 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
14156 PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
14159 PIPE_CONF_CHECK_BOOL(double_wide);
14161 PIPE_CONF_CHECK_P(shared_dpll);
14162 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
14163 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
14164 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
14165 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
14166 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
14167 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
14168 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
14169 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
14170 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
14171 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
14172 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
14173 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
14174 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
14175 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
14176 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
14177 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
14178 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
14179 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
14180 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
14181 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
14182 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
14183 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
14184 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
14185 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
14186 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
14187 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
14188 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
14189 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
14190 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
14191 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
14192 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
14194 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
14195 PIPE_CONF_CHECK_X(dsi_pll.div);
14197 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
14198 PIPE_CONF_CHECK_I(pipe_bpp);
14200 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
14201 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
14203 PIPE_CONF_CHECK_I(min_voltage_level);
14205 PIPE_CONF_CHECK_X(infoframes.enable);
14206 PIPE_CONF_CHECK_X(infoframes.gcp);
14207 PIPE_CONF_CHECK_INFOFRAME(avi);
14208 PIPE_CONF_CHECK_INFOFRAME(spd);
14209 PIPE_CONF_CHECK_INFOFRAME(hdmi);
14210 PIPE_CONF_CHECK_INFOFRAME(drm);
14211 PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
14213 PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
14214 PIPE_CONF_CHECK_I(master_transcoder);
14216 PIPE_CONF_CHECK_I(dsc.compression_enable);
14217 PIPE_CONF_CHECK_I(dsc.dsc_split);
14218 PIPE_CONF_CHECK_I(dsc.compressed_bpp);
14220 PIPE_CONF_CHECK_I(mst_master_transcoder);
14222 #undef PIPE_CONF_CHECK_X
14223 #undef PIPE_CONF_CHECK_I
14224 #undef PIPE_CONF_CHECK_BOOL
14225 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
14226 #undef PIPE_CONF_CHECK_P
14227 #undef PIPE_CONF_CHECK_FLAGS
14228 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
14229 #undef PIPE_CONF_CHECK_COLOR_LUT
14230 #undef PIPE_CONF_QUIRK
14235 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
14236 const struct intel_crtc_state *pipe_config)
14238 if (pipe_config->has_pch_encoder) {
14239 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
14240 &pipe_config->fdi_m_n);
14241 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
14244 * FDI already provided one idea for the dotclock.
14245 * Yell if the encoder disagrees.
14247 drm_WARN(&dev_priv->drm,
14248 !intel_fuzzy_clock_check(fdi_dotclock, dotclock),
14249 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
14250 fdi_dotclock, dotclock);
14254 static void verify_wm_state(struct intel_crtc *crtc,
14255 struct intel_crtc_state *new_crtc_state)
14257 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14258 struct skl_hw_state {
14259 struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
14260 struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
14261 struct skl_pipe_wm wm;
14263 struct skl_pipe_wm *sw_wm;
14264 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
14265 u8 hw_enabled_slices;
14266 const enum pipe pipe = crtc->pipe;
14267 int plane, level, max_level = ilk_wm_max_level(dev_priv);
14269 if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active)
14272 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
14276 skl_pipe_wm_get_hw_state(crtc, &hw->wm);
14277 sw_wm = &new_crtc_state->wm.skl.optimal;
14279 skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
14281 hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
14283 if (INTEL_GEN(dev_priv) >= 11 &&
14284 hw_enabled_slices != dev_priv->dbuf.enabled_slices)
14285 drm_err(&dev_priv->drm,
14286 "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n",
14287 dev_priv->dbuf.enabled_slices,
14288 hw_enabled_slices);
14291 for_each_universal_plane(dev_priv, pipe, plane) {
14292 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
14294 hw_plane_wm = &hw->wm.planes[plane];
14295 sw_plane_wm = &sw_wm->planes[plane];
14298 for (level = 0; level <= max_level; level++) {
14299 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
14300 &sw_plane_wm->wm[level]) ||
14301 (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
14302 &sw_plane_wm->sagv_wm0)))
14305 drm_err(&dev_priv->drm,
14306 "mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14307 pipe_name(pipe), plane + 1, level,
14308 sw_plane_wm->wm[level].plane_en,
14309 sw_plane_wm->wm[level].plane_res_b,
14310 sw_plane_wm->wm[level].plane_res_l,
14311 hw_plane_wm->wm[level].plane_en,
14312 hw_plane_wm->wm[level].plane_res_b,
14313 hw_plane_wm->wm[level].plane_res_l);
14316 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
14317 &sw_plane_wm->trans_wm)) {
14318 drm_err(&dev_priv->drm,
14319 "mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14320 pipe_name(pipe), plane + 1,
14321 sw_plane_wm->trans_wm.plane_en,
14322 sw_plane_wm->trans_wm.plane_res_b,
14323 sw_plane_wm->trans_wm.plane_res_l,
14324 hw_plane_wm->trans_wm.plane_en,
14325 hw_plane_wm->trans_wm.plane_res_b,
14326 hw_plane_wm->trans_wm.plane_res_l);
14330 hw_ddb_entry = &hw->ddb_y[plane];
14331 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane];
14333 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
14334 drm_err(&dev_priv->drm,
14335 "mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
14336 pipe_name(pipe), plane + 1,
14337 sw_ddb_entry->start, sw_ddb_entry->end,
14338 hw_ddb_entry->start, hw_ddb_entry->end);
14344 * If the cursor plane isn't active, we may not have updated it's ddb
14345 * allocation. In that case since the ddb allocation will be updated
14346 * once the plane becomes visible, we can skip this check
14349 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
14351 hw_plane_wm = &hw->wm.planes[PLANE_CURSOR];
14352 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
14355 for (level = 0; level <= max_level; level++) {
14356 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
14357 &sw_plane_wm->wm[level]) ||
14358 (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
14359 &sw_plane_wm->sagv_wm0)))
14362 drm_err(&dev_priv->drm,
14363 "mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14364 pipe_name(pipe), level,
14365 sw_plane_wm->wm[level].plane_en,
14366 sw_plane_wm->wm[level].plane_res_b,
14367 sw_plane_wm->wm[level].plane_res_l,
14368 hw_plane_wm->wm[level].plane_en,
14369 hw_plane_wm->wm[level].plane_res_b,
14370 hw_plane_wm->wm[level].plane_res_l);
14373 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
14374 &sw_plane_wm->trans_wm)) {
14375 drm_err(&dev_priv->drm,
14376 "mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14378 sw_plane_wm->trans_wm.plane_en,
14379 sw_plane_wm->trans_wm.plane_res_b,
14380 sw_plane_wm->trans_wm.plane_res_l,
14381 hw_plane_wm->trans_wm.plane_en,
14382 hw_plane_wm->trans_wm.plane_res_b,
14383 hw_plane_wm->trans_wm.plane_res_l);
14387 hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR];
14388 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
14390 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
14391 drm_err(&dev_priv->drm,
14392 "mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
14394 sw_ddb_entry->start, sw_ddb_entry->end,
14395 hw_ddb_entry->start, hw_ddb_entry->end);
14403 verify_connector_state(struct intel_atomic_state *state,
14404 struct intel_crtc *crtc)
14406 struct drm_connector *connector;
14407 struct drm_connector_state *new_conn_state;
14410 for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) {
14411 struct drm_encoder *encoder = connector->encoder;
14412 struct intel_crtc_state *crtc_state = NULL;
14414 if (new_conn_state->crtc != &crtc->base)
14418 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
14420 intel_connector_verify_state(crtc_state, new_conn_state);
14422 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
14423 "connector's atomic encoder doesn't match legacy encoder\n");
14428 verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state)
14430 struct intel_encoder *encoder;
14431 struct drm_connector *connector;
14432 struct drm_connector_state *old_conn_state, *new_conn_state;
14435 for_each_intel_encoder(&dev_priv->drm, encoder) {
14436 bool enabled = false, found = false;
14439 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n",
14440 encoder->base.base.id,
14441 encoder->base.name);
14443 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,
14444 new_conn_state, i) {
14445 if (old_conn_state->best_encoder == &encoder->base)
14448 if (new_conn_state->best_encoder != &encoder->base)
14450 found = enabled = true;
14452 I915_STATE_WARN(new_conn_state->crtc !=
14453 encoder->base.crtc,
14454 "connector's crtc doesn't match encoder crtc\n");
14460 I915_STATE_WARN(!!encoder->base.crtc != enabled,
14461 "encoder's enabled state mismatch "
14462 "(expected %i, found %i)\n",
14463 !!encoder->base.crtc, enabled);
14465 if (!encoder->base.crtc) {
14468 active = encoder->get_hw_state(encoder, &pipe);
14469 I915_STATE_WARN(active,
14470 "encoder detached but still enabled on pipe %c.\n",
14477 verify_crtc_state(struct intel_crtc *crtc,
14478 struct intel_crtc_state *old_crtc_state,
14479 struct intel_crtc_state *new_crtc_state)
14481 struct drm_device *dev = crtc->base.dev;
14482 struct drm_i915_private *dev_priv = to_i915(dev);
14483 struct intel_encoder *encoder;
14484 struct intel_crtc_state *pipe_config = old_crtc_state;
14485 struct drm_atomic_state *state = old_crtc_state->uapi.state;
14487 __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
14488 intel_crtc_free_hw_state(old_crtc_state);
14489 intel_crtc_state_reset(old_crtc_state, crtc);
14490 old_crtc_state->uapi.state = state;
14492 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id,
14495 pipe_config->hw.enable = new_crtc_state->hw.enable;
14497 pipe_config->hw.active =
14498 dev_priv->display.get_pipe_config(crtc, pipe_config);
14500 /* we keep both pipes enabled on 830 */
14501 if (IS_I830(dev_priv) && pipe_config->hw.active)
14502 pipe_config->hw.active = new_crtc_state->hw.active;
14504 I915_STATE_WARN(new_crtc_state->hw.active != pipe_config->hw.active,
14505 "crtc active state doesn't match with hw state "
14506 "(expected %i, found %i)\n",
14507 new_crtc_state->hw.active, pipe_config->hw.active);
14509 I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,
14510 "transitional active state does not match atomic hw state "
14511 "(expected %i, found %i)\n",
14512 new_crtc_state->hw.active, crtc->active);
14514 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14518 active = encoder->get_hw_state(encoder, &pipe);
14519 I915_STATE_WARN(active != new_crtc_state->hw.active,
14520 "[ENCODER:%i] active %i with crtc active %i\n",
14521 encoder->base.base.id, active,
14522 new_crtc_state->hw.active);
14524 I915_STATE_WARN(active && crtc->pipe != pipe,
14525 "Encoder connected to wrong pipe %c\n",
14529 encoder->get_config(encoder, pipe_config);
14532 intel_crtc_compute_pixel_rate(pipe_config);
14534 if (!new_crtc_state->hw.active)
14537 intel_pipe_config_sanity_check(dev_priv, pipe_config);
14539 if (!intel_pipe_config_compare(new_crtc_state,
14540 pipe_config, false)) {
14541 I915_STATE_WARN(1, "pipe state doesn't match!\n");
14542 intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
14543 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
14548 intel_verify_planes(struct intel_atomic_state *state)
14550 struct intel_plane *plane;
14551 const struct intel_plane_state *plane_state;
14554 for_each_new_intel_plane_in_state(state, plane,
14556 assert_plane(plane, plane_state->planar_slave ||
14557 plane_state->uapi.visible);
14561 verify_single_dpll_state(struct drm_i915_private *dev_priv,
14562 struct intel_shared_dpll *pll,
14563 struct intel_crtc *crtc,
14564 struct intel_crtc_state *new_crtc_state)
14566 struct intel_dpll_hw_state dpll_hw_state;
14567 unsigned int crtc_mask;
14570 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
14572 drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name);
14574 active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
14576 if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
14577 I915_STATE_WARN(!pll->on && pll->active_mask,
14578 "pll in active use but not on in sw tracking\n");
14579 I915_STATE_WARN(pll->on && !pll->active_mask,
14580 "pll is on but not used by any active crtc\n");
14581 I915_STATE_WARN(pll->on != active,
14582 "pll on state mismatch (expected %i, found %i)\n",
14587 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
14588 "more active pll users than references: %x vs %x\n",
14589 pll->active_mask, pll->state.crtc_mask);
14594 crtc_mask = drm_crtc_mask(&crtc->base);
14596 if (new_crtc_state->hw.active)
14597 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
14598 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
14599 pipe_name(crtc->pipe), pll->active_mask);
14601 I915_STATE_WARN(pll->active_mask & crtc_mask,
14602 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
14603 pipe_name(crtc->pipe), pll->active_mask);
14605 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
14606 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
14607 crtc_mask, pll->state.crtc_mask);
14609 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
14611 sizeof(dpll_hw_state)),
14612 "pll hw state mismatch\n");
14616 verify_shared_dpll_state(struct intel_crtc *crtc,
14617 struct intel_crtc_state *old_crtc_state,
14618 struct intel_crtc_state *new_crtc_state)
14620 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14622 if (new_crtc_state->shared_dpll)
14623 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state);
14625 if (old_crtc_state->shared_dpll &&
14626 old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
14627 unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
14628 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
14630 I915_STATE_WARN(pll->active_mask & crtc_mask,
14631 "pll active mismatch (didn't expect pipe %c in active mask)\n",
14632 pipe_name(crtc->pipe));
14633 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
14634 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
14635 pipe_name(crtc->pipe));
14640 intel_modeset_verify_crtc(struct intel_crtc *crtc,
14641 struct intel_atomic_state *state,
14642 struct intel_crtc_state *old_crtc_state,
14643 struct intel_crtc_state *new_crtc_state)
14645 if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
14648 verify_wm_state(crtc, new_crtc_state);
14649 verify_connector_state(state, crtc);
14650 verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
14651 verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
14655 verify_disabled_dpll_state(struct drm_i915_private *dev_priv)
14659 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++)
14660 verify_single_dpll_state(dev_priv,
14661 &dev_priv->dpll.shared_dplls[i],
14666 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
14667 struct intel_atomic_state *state)
14669 verify_encoder_state(dev_priv, state);
14670 verify_connector_state(state, NULL);
14671 verify_disabled_dpll_state(dev_priv);
14675 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
14677 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
14678 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14679 const struct drm_display_mode *adjusted_mode =
14680 &crtc_state->hw.adjusted_mode;
14682 drm_calc_timestamping_constants(&crtc->base, adjusted_mode);
14684 crtc->mode_flags = crtc_state->mode_flags;
14687 * The scanline counter increments at the leading edge of hsync.
14689 * On most platforms it starts counting from vtotal-1 on the
14690 * first active line. That means the scanline counter value is
14691 * always one less than what we would expect. Ie. just after
14692 * start of vblank, which also occurs at start of hsync (on the
14693 * last active line), the scanline counter will read vblank_start-1.
14695 * On gen2 the scanline counter starts counting from 1 instead
14696 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
14697 * to keep the value positive), instead of adding one.
14699 * On HSW+ the behaviour of the scanline counter depends on the output
14700 * type. For DP ports it behaves like most other platforms, but on HDMI
14701 * there's an extra 1 line difference. So we need to add two instead of
14702 * one to the value.
14704 * On VLV/CHV DSI the scanline counter would appear to increment
14705 * approx. 1/3 of a scanline before start of vblank. Unfortunately
14706 * that means we can't tell whether we're in vblank or not while
14707 * we're on that particular line. We must still set scanline_offset
14708 * to 1 so that the vblank timestamps come out correct when we query
14709 * the scanline counter from within the vblank interrupt handler.
14710 * However if queried just before the start of vblank we'll get an
14711 * answer that's slightly in the future.
14713 if (IS_GEN(dev_priv, 2)) {
14716 vtotal = adjusted_mode->crtc_vtotal;
14717 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
14720 crtc->scanline_offset = vtotal - 1;
14721 } else if (HAS_DDI(dev_priv) &&
14722 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
14723 crtc->scanline_offset = 2;
14725 crtc->scanline_offset = 1;
14729 static void intel_modeset_clear_plls(struct intel_atomic_state *state)
14731 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14732 struct intel_crtc_state *new_crtc_state;
14733 struct intel_crtc *crtc;
14736 if (!dev_priv->display.crtc_compute_clock)
14739 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14740 if (!needs_modeset(new_crtc_state))
14743 intel_release_shared_dplls(state, crtc);
14748 * This implements the workaround described in the "notes" section of the mode
14749 * set sequence documentation. When going from no pipes or single pipe to
14750 * multiple pipes, and planes are enabled after the pipe, we need to wait at
14751 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
14753 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
14755 struct intel_crtc_state *crtc_state;
14756 struct intel_crtc *crtc;
14757 struct intel_crtc_state *first_crtc_state = NULL;
14758 struct intel_crtc_state *other_crtc_state = NULL;
14759 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
14762 /* look at all crtc's that are going to be enabled in during modeset */
14763 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14764 if (!crtc_state->hw.active ||
14765 !needs_modeset(crtc_state))
14768 if (first_crtc_state) {
14769 other_crtc_state = crtc_state;
14772 first_crtc_state = crtc_state;
14773 first_pipe = crtc->pipe;
14777 /* No workaround needed? */
14778 if (!first_crtc_state)
14781 /* w/a possibly needed, check how many crtc's are already enabled. */
14782 for_each_intel_crtc(state->base.dev, crtc) {
14783 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
14784 if (IS_ERR(crtc_state))
14785 return PTR_ERR(crtc_state);
14787 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
14789 if (!crtc_state->hw.active ||
14790 needs_modeset(crtc_state))
14793 /* 2 or more enabled crtcs means no need for w/a */
14794 if (enabled_pipe != INVALID_PIPE)
14797 enabled_pipe = crtc->pipe;
14800 if (enabled_pipe != INVALID_PIPE)
14801 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
14802 else if (other_crtc_state)
14803 other_crtc_state->hsw_workaround_pipe = first_pipe;
14808 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
14811 const struct intel_crtc_state *crtc_state;
14812 struct intel_crtc *crtc;
14815 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14816 if (crtc_state->hw.active)
14817 active_pipes |= BIT(crtc->pipe);
14819 active_pipes &= ~BIT(crtc->pipe);
14822 return active_pipes;
14825 static int intel_modeset_checks(struct intel_atomic_state *state)
14827 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14829 state->modeset = true;
14831 if (IS_HASWELL(dev_priv))
14832 return hsw_mode_set_planes_workaround(state);
14838 * Handle calculation of various watermark data at the end of the atomic check
14839 * phase. The code here should be run after the per-crtc and per-plane 'check'
14840 * handlers to ensure that all derived state has been updated.
14842 static int calc_watermark_data(struct intel_atomic_state *state)
14844 struct drm_device *dev = state->base.dev;
14845 struct drm_i915_private *dev_priv = to_i915(dev);
14847 /* Is there platform-specific watermark information to calculate? */
14848 if (dev_priv->display.compute_global_watermarks)
14849 return dev_priv->display.compute_global_watermarks(state);
14854 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
14855 struct intel_crtc_state *new_crtc_state)
14857 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
14860 new_crtc_state->uapi.mode_changed = false;
14861 new_crtc_state->update_pipe = true;
14864 static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state,
14865 struct intel_crtc_state *new_crtc_state)
14868 * If we're not doing the full modeset we want to
14869 * keep the current M/N values as they may be
14870 * sufficiently different to the computed values
14871 * to cause problems.
14873 * FIXME: should really copy more fuzzy state here
14875 new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n;
14876 new_crtc_state->dp_m_n = old_crtc_state->dp_m_n;
14877 new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
14878 new_crtc_state->has_drrs = old_crtc_state->has_drrs;
14881 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
14882 struct intel_crtc *crtc,
14885 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14886 struct intel_plane *plane;
14888 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
14889 struct intel_plane_state *plane_state;
14891 if ((plane_ids_mask & BIT(plane->id)) == 0)
14894 plane_state = intel_atomic_get_plane_state(state, plane);
14895 if (IS_ERR(plane_state))
14896 return PTR_ERR(plane_state);
14902 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
14904 /* See {hsw,vlv,ivb}_plane_ratio() */
14905 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
14906 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
14907 IS_IVYBRIDGE(dev_priv) || (INTEL_GEN(dev_priv) >= 11);
14910 static int intel_atomic_check_planes(struct intel_atomic_state *state)
14912 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14913 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14914 struct intel_plane_state *plane_state;
14915 struct intel_plane *plane;
14916 struct intel_crtc *crtc;
14919 ret = icl_add_linked_planes(state);
14923 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
14924 ret = intel_plane_atomic_check(state, plane);
14926 drm_dbg_atomic(&dev_priv->drm,
14927 "[PLANE:%d:%s] atomic driver check failed\n",
14928 plane->base.base.id, plane->base.name);
14933 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14934 new_crtc_state, i) {
14935 u8 old_active_planes, new_active_planes;
14937 ret = icl_check_nv12_planes(new_crtc_state);
14942 * On some platforms the number of active planes affects
14943 * the planes' minimum cdclk calculation. Add such planes
14944 * to the state before we compute the minimum cdclk.
14946 if (!active_planes_affects_min_cdclk(dev_priv))
14949 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
14950 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
14953 * Not only the number of planes, but if the plane configuration had
14954 * changed might already mean we need to recompute min CDCLK,
14955 * because different planes might consume different amount of Dbuf bandwidth
14956 * according to formula: Bw per plane = Pixel rate * bpp * pipe/plane scale factor
14958 if (old_active_planes == new_active_planes)
14961 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
14969 static int intel_atomic_check_cdclk(struct intel_atomic_state *state,
14970 bool *need_cdclk_calc)
14972 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14973 const struct intel_cdclk_state *old_cdclk_state;
14974 const struct intel_cdclk_state *new_cdclk_state;
14975 struct intel_plane_state *plane_state;
14976 struct intel_bw_state *new_bw_state;
14977 struct intel_plane *plane;
14983 * active_planes bitmask has been updated, and potentially
14984 * affected planes are part of the state. We can now
14985 * compute the minimum cdclk for each plane.
14987 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
14988 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc);
14993 old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
14994 new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
14996 if (new_cdclk_state &&
14997 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
14998 *need_cdclk_calc = true;
15000 ret = dev_priv->display.bw_calc_min_cdclk(state);
15004 new_bw_state = intel_atomic_get_new_bw_state(state);
15006 if (!new_cdclk_state || !new_bw_state)
15009 for_each_pipe(dev_priv, pipe) {
15010 min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk);
15013 * Currently do this change only if we need to increase
15015 if (new_bw_state->min_cdclk > min_cdclk)
15016 *need_cdclk_calc = true;
15022 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
15024 struct intel_crtc_state *crtc_state;
15025 struct intel_crtc *crtc;
15028 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
15029 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
15032 ret = intel_crtc_atomic_check(state, crtc);
15034 drm_dbg_atomic(&i915->drm,
15035 "[CRTC:%d:%s] atomic driver check failed\n",
15036 crtc->base.base.id, crtc->base.name);
15044 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
15047 const struct intel_crtc_state *new_crtc_state;
15048 struct intel_crtc *crtc;
15051 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15052 if (new_crtc_state->hw.enable &&
15053 transcoders & BIT(new_crtc_state->cpu_transcoder) &&
15054 needs_modeset(new_crtc_state))
15062 * DOC: asynchronous flip implementation
15064 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
15065 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
15066 * Correspondingly, support is currently added for primary plane only.
15068 * Async flip can only change the plane surface address, so anything else
15069 * changing is rejected from the intel_atomic_check_async() function.
15070 * Once this check is cleared, flip done interrupt is enabled using
15071 * the skl_enable_flip_done() function.
15073 * As soon as the surface address register is written, flip done interrupt is
15074 * generated and the requested events are sent to the usersapce in the interrupt
15075 * handler itself. The timestamp and sequence sent during the flip done event
15076 * correspond to the last vblank and have no relation to the actual time when
15077 * the flip done event was sent.
15079 static int intel_atomic_check_async(struct intel_atomic_state *state)
15081 struct drm_i915_private *i915 = to_i915(state->base.dev);
15082 const struct intel_crtc_state *old_crtc_state, *new_crtc_state;
15083 const struct intel_plane_state *new_plane_state, *old_plane_state;
15084 struct intel_crtc *crtc;
15085 struct intel_plane *plane;
15088 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15089 new_crtc_state, i) {
15090 if (needs_modeset(new_crtc_state)) {
15091 drm_dbg_kms(&i915->drm, "Modeset Required. Async flip not supported\n");
15095 if (!new_crtc_state->hw.active) {
15096 drm_dbg_kms(&i915->drm, "CRTC inactive\n");
15099 if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
15100 drm_dbg_kms(&i915->drm,
15101 "Active planes cannot be changed during async flip\n");
15106 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
15107 new_plane_state, i) {
15109 * TODO: Async flip is only supported through the page flip IOCTL
15110 * as of now. So support currently added for primary plane only.
15111 * Support for other planes on platforms on which supports
15112 * this(vlv/chv and icl+) should be added when async flip is
15113 * enabled in the atomic IOCTL path.
15115 if (plane->id != PLANE_PRIMARY)
15119 * FIXME: This check is kept generic for all platforms.
15120 * Need to verify this for all gen9 and gen10 platforms to enable
15121 * this selectively if required.
15123 switch (new_plane_state->hw.fb->modifier) {
15124 case I915_FORMAT_MOD_X_TILED:
15125 case I915_FORMAT_MOD_Y_TILED:
15126 case I915_FORMAT_MOD_Yf_TILED:
15129 drm_dbg_kms(&i915->drm,
15130 "Linear memory/CCS does not support async flips\n");
15134 if (old_plane_state->color_plane[0].stride !=
15135 new_plane_state->color_plane[0].stride) {
15136 drm_dbg_kms(&i915->drm, "Stride cannot be changed in async flip\n");
15140 if (old_plane_state->hw.fb->modifier !=
15141 new_plane_state->hw.fb->modifier) {
15142 drm_dbg_kms(&i915->drm,
15143 "Framebuffer modifiers cannot be changed in async flip\n");
15147 if (old_plane_state->hw.fb->format !=
15148 new_plane_state->hw.fb->format) {
15149 drm_dbg_kms(&i915->drm,
15150 "Framebuffer format cannot be changed in async flip\n");
15154 if (old_plane_state->hw.rotation !=
15155 new_plane_state->hw.rotation) {
15156 drm_dbg_kms(&i915->drm, "Rotation cannot be changed in async flip\n");
15160 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) ||
15161 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) {
15162 drm_dbg_kms(&i915->drm,
15163 "Plane size/co-ordinates cannot be changed in async flip\n");
15167 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
15168 drm_dbg_kms(&i915->drm, "Alpha value cannot be changed in async flip\n");
15172 if (old_plane_state->hw.pixel_blend_mode !=
15173 new_plane_state->hw.pixel_blend_mode) {
15174 drm_dbg_kms(&i915->drm,
15175 "Pixel blend mode cannot be changed in async flip\n");
15179 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
15180 drm_dbg_kms(&i915->drm,
15181 "Color encoding cannot be changed in async flip\n");
15185 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
15186 drm_dbg_kms(&i915->drm, "Color range cannot be changed in async flip\n");
15195 * intel_atomic_check - validate state object
15197 * @_state: state to validate
15199 static int intel_atomic_check(struct drm_device *dev,
15200 struct drm_atomic_state *_state)
15202 struct drm_i915_private *dev_priv = to_i915(dev);
15203 struct intel_atomic_state *state = to_intel_atomic_state(_state);
15204 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
15205 struct intel_crtc *crtc;
15207 bool any_ms = false;
15209 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15210 new_crtc_state, i) {
15211 if (new_crtc_state->inherited != old_crtc_state->inherited)
15212 new_crtc_state->uapi.mode_changed = true;
15215 ret = drm_atomic_helper_check_modeset(dev, &state->base);
15219 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15220 new_crtc_state, i) {
15221 if (!needs_modeset(new_crtc_state)) {
15223 intel_crtc_copy_uapi_to_hw_state_nomodeset(new_crtc_state);
15228 ret = intel_crtc_prepare_cleared_state(new_crtc_state);
15232 if (!new_crtc_state->hw.enable)
15235 ret = intel_modeset_pipe_config(new_crtc_state);
15240 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15241 new_crtc_state, i) {
15242 if (!needs_modeset(new_crtc_state))
15245 ret = intel_modeset_pipe_config_late(new_crtc_state);
15249 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
15253 * Check if fastset is allowed by external dependencies like other
15254 * pipes and transcoders.
15256 * Right now it only forces a fullmodeset when the MST master
15257 * transcoder did not changed but the pipe of the master transcoder
15258 * needs a fullmodeset so all slaves also needs to do a fullmodeset or
15259 * in case of port synced crtcs, if one of the synced crtcs
15260 * needs a full modeset, all other synced crtcs should be
15261 * forced a full modeset.
15263 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15264 if (!new_crtc_state->hw.enable || needs_modeset(new_crtc_state))
15267 if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
15268 enum transcoder master = new_crtc_state->mst_master_transcoder;
15270 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
15271 new_crtc_state->uapi.mode_changed = true;
15272 new_crtc_state->update_pipe = false;
15276 if (is_trans_port_sync_mode(new_crtc_state)) {
15277 u8 trans = new_crtc_state->sync_mode_slaves_mask;
15279 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
15280 trans |= BIT(new_crtc_state->master_transcoder);
15282 if (intel_cpu_transcoders_need_modeset(state, trans)) {
15283 new_crtc_state->uapi.mode_changed = true;
15284 new_crtc_state->update_pipe = false;
15289 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15290 new_crtc_state, i) {
15291 if (needs_modeset(new_crtc_state)) {
15296 if (!new_crtc_state->update_pipe)
15299 intel_crtc_copy_fastset(old_crtc_state, new_crtc_state);
15302 if (any_ms && !check_digital_port_conflicts(state)) {
15303 drm_dbg_kms(&dev_priv->drm,
15304 "rejecting conflicting digital port configuration\n");
15309 ret = drm_dp_mst_atomic_check(&state->base);
15313 ret = intel_atomic_check_planes(state);
15318 * distrust_bios_wm will force a full dbuf recomputation
15319 * but the hardware state will only get updated accordingly
15320 * if state->modeset==true. Hence distrust_bios_wm==true &&
15321 * state->modeset==false is an invalid combination which
15322 * would cause the hardware and software dbuf state to get
15323 * out of sync. We must prevent that.
15325 * FIXME clean up this mess and introduce better
15326 * state tracking for dbuf.
15328 if (dev_priv->wm.distrust_bios_wm)
15331 intel_fbc_choose_crtc(dev_priv, state);
15332 ret = calc_watermark_data(state);
15336 ret = intel_bw_atomic_check(state);
15340 ret = intel_atomic_check_cdclk(state, &any_ms);
15345 ret = intel_modeset_checks(state);
15349 ret = intel_modeset_calc_cdclk(state);
15353 intel_modeset_clear_plls(state);
15356 ret = intel_atomic_check_crtcs(state);
15360 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15361 new_crtc_state, i) {
15362 if (new_crtc_state->uapi.async_flip) {
15363 ret = intel_atomic_check_async(state);
15368 if (!needs_modeset(new_crtc_state) &&
15369 !new_crtc_state->update_pipe)
15372 intel_dump_pipe_config(new_crtc_state, state,
15373 needs_modeset(new_crtc_state) ?
15374 "[modeset]" : "[fastset]");
15380 if (ret == -EDEADLK)
15384 * FIXME would probably be nice to know which crtc specifically
15385 * caused the failure, in cases where we can pinpoint it.
15387 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15389 intel_dump_pipe_config(new_crtc_state, state, "[failed]");
15394 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
15396 struct intel_crtc_state *crtc_state;
15397 struct intel_crtc *crtc;
15400 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
15404 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
15405 bool mode_changed = needs_modeset(crtc_state);
15407 if (mode_changed || crtc_state->update_pipe ||
15408 crtc_state->uapi.color_mgmt_changed) {
15409 intel_dsb_prepare(crtc_state);
15416 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
15418 struct drm_device *dev = crtc->base.dev;
15419 struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)];
15421 if (!vblank->max_vblank_count)
15422 return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
15424 return crtc->base.funcs->get_vblank_counter(&crtc->base);
15427 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
15428 struct intel_crtc_state *crtc_state)
15430 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15432 if (!IS_GEN(dev_priv, 2) || crtc_state->active_planes)
15433 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
15435 if (crtc_state->has_pch_encoder) {
15436 enum pipe pch_transcoder =
15437 intel_crtc_pch_transcoder(crtc);
15439 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
15443 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
15444 const struct intel_crtc_state *new_crtc_state)
15446 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
15447 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15450 * Update pipe size and adjust fitter if needed: the reason for this is
15451 * that in compute_mode_changes we check the native mode (not the pfit
15452 * mode) to see if we can flip rather than do a full mode set. In the
15453 * fastboot case, we'll flip, but if we don't update the pipesrc and
15454 * pfit state, we'll end up with a big fb scanned out into the wrong
15457 intel_set_pipe_src_size(new_crtc_state);
15459 /* on skylake this is done by detaching scalers */
15460 if (INTEL_GEN(dev_priv) >= 9) {
15461 skl_detach_scalers(new_crtc_state);
15463 if (new_crtc_state->pch_pfit.enabled)
15464 skl_pfit_enable(new_crtc_state);
15465 } else if (HAS_PCH_SPLIT(dev_priv)) {
15466 if (new_crtc_state->pch_pfit.enabled)
15467 ilk_pfit_enable(new_crtc_state);
15468 else if (old_crtc_state->pch_pfit.enabled)
15469 ilk_pfit_disable(old_crtc_state);
15473 * The register is supposedly single buffered so perhaps
15474 * not 100% correct to do this here. But SKL+ calculate
15475 * this based on the adjust pixel rate so pfit changes do
15476 * affect it and so it must be updated for fastsets.
15477 * HSW/BDW only really need this here for fastboot, after
15478 * that the value should not change without a full modeset.
15480 if (INTEL_GEN(dev_priv) >= 9 ||
15481 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
15482 hsw_set_linetime_wm(new_crtc_state);
15484 if (INTEL_GEN(dev_priv) >= 11)
15485 icl_set_pipe_chicken(crtc);
15488 static void commit_pipe_config(struct intel_atomic_state *state,
15489 struct intel_crtc *crtc)
15491 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15492 const struct intel_crtc_state *old_crtc_state =
15493 intel_atomic_get_old_crtc_state(state, crtc);
15494 const struct intel_crtc_state *new_crtc_state =
15495 intel_atomic_get_new_crtc_state(state, crtc);
15496 bool modeset = needs_modeset(new_crtc_state);
15499 * During modesets pipe configuration was programmed as the
15500 * CRTC was enabled.
15503 if (new_crtc_state->uapi.color_mgmt_changed ||
15504 new_crtc_state->update_pipe)
15505 intel_color_commit(new_crtc_state);
15507 if (INTEL_GEN(dev_priv) >= 9)
15508 skl_detach_scalers(new_crtc_state);
15510 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
15511 bdw_set_pipemisc(new_crtc_state);
15513 if (new_crtc_state->update_pipe)
15514 intel_pipe_fastset(old_crtc_state, new_crtc_state);
15516 intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
15519 if (dev_priv->display.atomic_update_watermarks)
15520 dev_priv->display.atomic_update_watermarks(state, crtc);
15523 static void intel_enable_crtc(struct intel_atomic_state *state,
15524 struct intel_crtc *crtc)
15526 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15527 const struct intel_crtc_state *new_crtc_state =
15528 intel_atomic_get_new_crtc_state(state, crtc);
15530 if (!needs_modeset(new_crtc_state))
15533 intel_crtc_update_active_timings(new_crtc_state);
15535 dev_priv->display.crtc_enable(state, crtc);
15537 /* vblanks work again, re-enable pipe CRC. */
15538 intel_crtc_enable_pipe_crc(crtc);
15541 static void intel_update_crtc(struct intel_atomic_state *state,
15542 struct intel_crtc *crtc)
15544 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15545 const struct intel_crtc_state *old_crtc_state =
15546 intel_atomic_get_old_crtc_state(state, crtc);
15547 struct intel_crtc_state *new_crtc_state =
15548 intel_atomic_get_new_crtc_state(state, crtc);
15549 bool modeset = needs_modeset(new_crtc_state);
15552 if (new_crtc_state->preload_luts &&
15553 (new_crtc_state->uapi.color_mgmt_changed ||
15554 new_crtc_state->update_pipe))
15555 intel_color_load_luts(new_crtc_state);
15557 intel_pre_plane_update(state, crtc);
15559 if (new_crtc_state->update_pipe)
15560 intel_encoders_update_pipe(state, crtc);
15563 if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
15564 intel_fbc_disable(crtc);
15566 intel_fbc_enable(state, crtc);
15568 /* Perform vblank evasion around commit operation */
15569 intel_pipe_update_start(new_crtc_state);
15571 commit_pipe_config(state, crtc);
15573 if (INTEL_GEN(dev_priv) >= 9)
15574 skl_update_planes_on_crtc(state, crtc);
15576 i9xx_update_planes_on_crtc(state, crtc);
15578 intel_pipe_update_end(new_crtc_state);
15581 * We usually enable FIFO underrun interrupts as part of the
15582 * CRTC enable sequence during modesets. But when we inherit a
15583 * valid pipe configuration from the BIOS we need to take care
15584 * of enabling them on the CRTC's first fastset.
15586 if (new_crtc_state->update_pipe && !modeset &&
15587 old_crtc_state->inherited)
15588 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
15592 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
15593 struct intel_crtc_state *old_crtc_state,
15594 struct intel_crtc_state *new_crtc_state,
15595 struct intel_crtc *crtc)
15597 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15599 intel_crtc_disable_planes(state, crtc);
15602 * We need to disable pipe CRC before disabling the pipe,
15603 * or we race against vblank off.
15605 intel_crtc_disable_pipe_crc(crtc);
15607 dev_priv->display.crtc_disable(state, crtc);
15608 crtc->active = false;
15609 intel_fbc_disable(crtc);
15610 intel_disable_shared_dpll(old_crtc_state);
15612 /* FIXME unify this for all platforms */
15613 if (!new_crtc_state->hw.active &&
15614 !HAS_GMCH(dev_priv) &&
15615 dev_priv->display.initial_watermarks)
15616 dev_priv->display.initial_watermarks(state, crtc);
15619 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
15621 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
15622 struct intel_crtc *crtc;
15626 /* Only disable port sync and MST slaves */
15627 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15628 new_crtc_state, i) {
15629 if (!needs_modeset(new_crtc_state))
15632 if (!old_crtc_state->hw.active)
15635 /* In case of Transcoder port Sync master slave CRTCs can be
15636 * assigned in any order and we need to make sure that
15637 * slave CRTCs are disabled first and then master CRTC since
15638 * Slave vblanks are masked till Master Vblanks.
15640 if (!is_trans_port_sync_slave(old_crtc_state) &&
15641 !intel_dp_mst_is_slave_trans(old_crtc_state))
15644 intel_pre_plane_update(state, crtc);
15645 intel_old_crtc_state_disables(state, old_crtc_state,
15646 new_crtc_state, crtc);
15647 handled |= BIT(crtc->pipe);
15650 /* Disable everything else left on */
15651 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15652 new_crtc_state, i) {
15653 if (!needs_modeset(new_crtc_state) ||
15654 (handled & BIT(crtc->pipe)))
15657 intel_pre_plane_update(state, crtc);
15658 if (old_crtc_state->hw.active)
15659 intel_old_crtc_state_disables(state, old_crtc_state,
15660 new_crtc_state, crtc);
15664 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
15666 struct intel_crtc_state *new_crtc_state;
15667 struct intel_crtc *crtc;
15670 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15671 if (!new_crtc_state->hw.active)
15674 intel_enable_crtc(state, crtc);
15675 intel_update_crtc(state, crtc);
15679 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
15681 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15682 struct intel_crtc *crtc;
15683 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
15684 struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
15685 u8 update_pipes = 0, modeset_pipes = 0;
15688 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
15689 enum pipe pipe = crtc->pipe;
15691 if (!new_crtc_state->hw.active)
15694 /* ignore allocations for crtc's that have been turned off. */
15695 if (!needs_modeset(new_crtc_state)) {
15696 entries[pipe] = old_crtc_state->wm.skl.ddb;
15697 update_pipes |= BIT(pipe);
15699 modeset_pipes |= BIT(pipe);
15704 * Whenever the number of active pipes changes, we need to make sure we
15705 * update the pipes in the right order so that their ddb allocations
15706 * never overlap with each other between CRTC updates. Otherwise we'll
15707 * cause pipe underruns and other bad stuff.
15709 * So first lets enable all pipes that do not need a fullmodeset as
15710 * those don't have any external dependency.
15712 while (update_pipes) {
15713 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15714 new_crtc_state, i) {
15715 enum pipe pipe = crtc->pipe;
15717 if ((update_pipes & BIT(pipe)) == 0)
15720 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
15721 entries, I915_MAX_PIPES, pipe))
15724 entries[pipe] = new_crtc_state->wm.skl.ddb;
15725 update_pipes &= ~BIT(pipe);
15727 intel_update_crtc(state, crtc);
15730 * If this is an already active pipe, it's DDB changed,
15731 * and this isn't the last pipe that needs updating
15732 * then we need to wait for a vblank to pass for the
15733 * new ddb allocation to take effect.
15735 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
15736 &old_crtc_state->wm.skl.ddb) &&
15737 (update_pipes | modeset_pipes))
15738 intel_wait_for_vblank(dev_priv, pipe);
15742 update_pipes = modeset_pipes;
15745 * Enable all pipes that needs a modeset and do not depends on other
15748 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15749 enum pipe pipe = crtc->pipe;
15751 if ((modeset_pipes & BIT(pipe)) == 0)
15754 if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
15755 is_trans_port_sync_master(new_crtc_state))
15758 modeset_pipes &= ~BIT(pipe);
15760 intel_enable_crtc(state, crtc);
15764 * Then we enable all remaining pipes that depend on other
15765 * pipes: MST slaves and port sync masters.
15767 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15768 enum pipe pipe = crtc->pipe;
15770 if ((modeset_pipes & BIT(pipe)) == 0)
15773 modeset_pipes &= ~BIT(pipe);
15775 intel_enable_crtc(state, crtc);
15779 * Finally we do the plane updates/etc. for all pipes that got enabled.
15781 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15782 enum pipe pipe = crtc->pipe;
15784 if ((update_pipes & BIT(pipe)) == 0)
15787 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
15788 entries, I915_MAX_PIPES, pipe));
15790 entries[pipe] = new_crtc_state->wm.skl.ddb;
15791 update_pipes &= ~BIT(pipe);
15793 intel_update_crtc(state, crtc);
15796 drm_WARN_ON(&dev_priv->drm, modeset_pipes);
15797 drm_WARN_ON(&dev_priv->drm, update_pipes);
15800 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
15802 struct intel_atomic_state *state, *next;
15803 struct llist_node *freed;
15805 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
15806 llist_for_each_entry_safe(state, next, freed, freed)
15807 drm_atomic_state_put(&state->base);
15810 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
15812 struct drm_i915_private *dev_priv =
15813 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
15815 intel_atomic_helper_free_state(dev_priv);
15818 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
15820 struct wait_queue_entry wait_fence, wait_reset;
15821 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
15823 init_wait_entry(&wait_fence, 0);
15824 init_wait_entry(&wait_reset, 0);
15826 prepare_to_wait(&intel_state->commit_ready.wait,
15827 &wait_fence, TASK_UNINTERRUPTIBLE);
15828 prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
15829 I915_RESET_MODESET),
15830 &wait_reset, TASK_UNINTERRUPTIBLE);
15833 if (i915_sw_fence_done(&intel_state->commit_ready) ||
15834 test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
15839 finish_wait(&intel_state->commit_ready.wait, &wait_fence);
15840 finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
15841 I915_RESET_MODESET),
15845 static void intel_cleanup_dsbs(struct intel_atomic_state *state)
15847 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
15848 struct intel_crtc *crtc;
15851 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15853 intel_dsb_cleanup(old_crtc_state);
15856 static void intel_atomic_cleanup_work(struct work_struct *work)
15858 struct intel_atomic_state *state =
15859 container_of(work, struct intel_atomic_state, base.commit_work);
15860 struct drm_i915_private *i915 = to_i915(state->base.dev);
15862 intel_cleanup_dsbs(state);
15863 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
15864 drm_atomic_helper_commit_cleanup_done(&state->base);
15865 drm_atomic_state_put(&state->base);
15867 intel_atomic_helper_free_state(i915);
15870 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
15872 struct drm_device *dev = state->base.dev;
15873 struct drm_i915_private *dev_priv = to_i915(dev);
15874 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
15875 struct intel_crtc *crtc;
15876 u64 put_domains[I915_MAX_PIPES] = {};
15877 intel_wakeref_t wakeref = 0;
15880 intel_atomic_commit_fence_wait(state);
15882 drm_atomic_helper_wait_for_dependencies(&state->base);
15884 if (state->modeset)
15885 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
15887 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15888 new_crtc_state, i) {
15889 if (needs_modeset(new_crtc_state) ||
15890 new_crtc_state->update_pipe) {
15892 put_domains[crtc->pipe] =
15893 modeset_get_crtc_power_domains(new_crtc_state);
15897 intel_commit_modeset_disables(state);
15899 /* FIXME: Eventually get rid of our crtc->config pointer */
15900 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
15901 crtc->config = new_crtc_state;
15903 if (state->modeset) {
15904 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
15906 intel_set_cdclk_pre_plane_update(state);
15908 intel_modeset_verify_disabled(dev_priv, state);
15911 intel_sagv_pre_plane_update(state);
15913 /* Complete the events for pipes that have now been disabled */
15914 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15915 bool modeset = needs_modeset(new_crtc_state);
15917 /* Complete events for now disable pipes here. */
15918 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
15919 spin_lock_irq(&dev->event_lock);
15920 drm_crtc_send_vblank_event(&crtc->base,
15921 new_crtc_state->uapi.event);
15922 spin_unlock_irq(&dev->event_lock);
15924 new_crtc_state->uapi.event = NULL;
15928 if (state->modeset)
15929 intel_encoders_update_prepare(state);
15931 intel_dbuf_pre_plane_update(state);
15933 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15934 if (new_crtc_state->uapi.async_flip)
15935 skl_enable_flip_done(crtc);
15938 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
15939 dev_priv->display.commit_modeset_enables(state);
15941 if (state->modeset) {
15942 intel_encoders_update_complete(state);
15944 intel_set_cdclk_post_plane_update(state);
15947 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
15948 * already, but still need the state for the delayed optimization. To
15950 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
15951 * - schedule that vblank worker _before_ calling hw_done
15952 * - at the start of commit_tail, cancel it _synchrously
15953 * - switch over to the vblank wait helper in the core after that since
15954 * we don't need out special handling any more.
15956 drm_atomic_helper_wait_for_flip_done(dev, &state->base);
15958 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15959 if (new_crtc_state->uapi.async_flip)
15960 skl_disable_flip_done(crtc);
15962 if (new_crtc_state->hw.active &&
15963 !needs_modeset(new_crtc_state) &&
15964 !new_crtc_state->preload_luts &&
15965 (new_crtc_state->uapi.color_mgmt_changed ||
15966 new_crtc_state->update_pipe))
15967 intel_color_load_luts(new_crtc_state);
15971 * Now that the vblank has passed, we can go ahead and program the
15972 * optimal watermarks on platforms that need two-step watermark
15975 * TODO: Move this (and other cleanup) to an async worker eventually.
15977 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15978 new_crtc_state, i) {
15980 * Gen2 reports pipe underruns whenever all planes are disabled.
15981 * So re-enable underrun reporting after some planes get enabled.
15983 * We do this before .optimize_watermarks() so that we have a
15984 * chance of catching underruns with the intermediate watermarks
15985 * vs. the new plane configuration.
15987 if (IS_GEN(dev_priv, 2) && planes_enabling(old_crtc_state, new_crtc_state))
15988 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
15990 if (dev_priv->display.optimize_watermarks)
15991 dev_priv->display.optimize_watermarks(state, crtc);
15994 intel_dbuf_post_plane_update(state);
15996 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
15997 intel_post_plane_update(state, crtc);
15999 if (put_domains[i])
16000 modeset_put_power_domains(dev_priv, put_domains[i]);
16002 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
16005 * DSB cleanup is done in cleanup_work aligning with framebuffer
16006 * cleanup. So copy and reset the dsb structure to sync with
16007 * commit_done and later do dsb cleanup in cleanup_work.
16009 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb);
16012 /* Underruns don't always raise interrupts, so check manually */
16013 intel_check_cpu_fifo_underruns(dev_priv);
16014 intel_check_pch_fifo_underruns(dev_priv);
16016 if (state->modeset)
16017 intel_verify_planes(state);
16019 intel_sagv_post_plane_update(state);
16021 drm_atomic_helper_commit_hw_done(&state->base);
16023 if (state->modeset) {
16024 /* As one of the primary mmio accessors, KMS has a high
16025 * likelihood of triggering bugs in unclaimed access. After we
16026 * finish modesetting, see if an error has been flagged, and if
16027 * so enable debugging for the next modeset - and hope we catch
16030 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
16031 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
16033 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
16036 * Defer the cleanup of the old state to a separate worker to not
16037 * impede the current task (userspace for blocking modesets) that
16038 * are executed inline. For out-of-line asynchronous modesets/flips,
16039 * deferring to a new worker seems overkill, but we would place a
16040 * schedule point (cond_resched()) here anyway to keep latencies
16043 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
16044 queue_work(system_highpri_wq, &state->base.commit_work);
16047 static void intel_atomic_commit_work(struct work_struct *work)
16049 struct intel_atomic_state *state =
16050 container_of(work, struct intel_atomic_state, base.commit_work);
16052 intel_atomic_commit_tail(state);
16055 static int __i915_sw_fence_call
16056 intel_atomic_commit_ready(struct i915_sw_fence *fence,
16057 enum i915_sw_fence_notify notify)
16059 struct intel_atomic_state *state =
16060 container_of(fence, struct intel_atomic_state, commit_ready);
16063 case FENCE_COMPLETE:
16064 /* we do blocking waits in the worker, nothing to do here */
16068 struct intel_atomic_helper *helper =
16069 &to_i915(state->base.dev)->atomic_helper;
16071 if (llist_add(&state->freed, &helper->free_list))
16072 schedule_work(&helper->free_work);
16077 return NOTIFY_DONE;
16080 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
16082 struct intel_plane_state *old_plane_state, *new_plane_state;
16083 struct intel_plane *plane;
16086 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
16087 new_plane_state, i)
16088 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
16089 to_intel_frontbuffer(new_plane_state->hw.fb),
16090 plane->frontbuffer_bit);
16093 static int intel_atomic_commit(struct drm_device *dev,
16094 struct drm_atomic_state *_state,
16097 struct intel_atomic_state *state = to_intel_atomic_state(_state);
16098 struct drm_i915_private *dev_priv = to_i915(dev);
16101 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
16103 drm_atomic_state_get(&state->base);
16104 i915_sw_fence_init(&state->commit_ready,
16105 intel_atomic_commit_ready);
16108 * The intel_legacy_cursor_update() fast path takes care
16109 * of avoiding the vblank waits for simple cursor
16110 * movement and flips. For cursor on/off and size changes,
16111 * we want to perform the vblank waits so that watermark
16112 * updates happen during the correct frames. Gen9+ have
16113 * double buffered watermarks and so shouldn't need this.
16115 * Unset state->legacy_cursor_update before the call to
16116 * drm_atomic_helper_setup_commit() because otherwise
16117 * drm_atomic_helper_wait_for_flip_done() is a noop and
16118 * we get FIFO underruns because we didn't wait
16121 * FIXME doing watermarks and fb cleanup from a vblank worker
16122 * (assuming we had any) would solve these problems.
16124 if (INTEL_GEN(dev_priv) < 9 && state->base.legacy_cursor_update) {
16125 struct intel_crtc_state *new_crtc_state;
16126 struct intel_crtc *crtc;
16129 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
16130 if (new_crtc_state->wm.need_postvbl_update ||
16131 new_crtc_state->update_wm_post)
16132 state->base.legacy_cursor_update = false;
16135 ret = intel_atomic_prepare_commit(state);
16137 drm_dbg_atomic(&dev_priv->drm,
16138 "Preparing state failed with %i\n", ret);
16139 i915_sw_fence_commit(&state->commit_ready);
16140 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
16144 ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
16146 ret = drm_atomic_helper_swap_state(&state->base, true);
16148 intel_atomic_swap_global_state(state);
16151 struct intel_crtc_state *new_crtc_state;
16152 struct intel_crtc *crtc;
16155 i915_sw_fence_commit(&state->commit_ready);
16157 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
16158 intel_dsb_cleanup(new_crtc_state);
16160 drm_atomic_helper_cleanup_planes(dev, &state->base);
16161 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
16164 dev_priv->wm.distrust_bios_wm = false;
16165 intel_shared_dpll_swap_state(state);
16166 intel_atomic_track_fbs(state);
16168 drm_atomic_state_get(&state->base);
16169 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
16171 i915_sw_fence_commit(&state->commit_ready);
16172 if (nonblock && state->modeset) {
16173 queue_work(dev_priv->modeset_wq, &state->base.commit_work);
16174 } else if (nonblock) {
16175 queue_work(dev_priv->flip_wq, &state->base.commit_work);
16177 if (state->modeset)
16178 flush_workqueue(dev_priv->modeset_wq);
16179 intel_atomic_commit_tail(state);
16185 struct wait_rps_boost {
16186 struct wait_queue_entry wait;
16188 struct drm_crtc *crtc;
16189 struct i915_request *request;
16192 static int do_rps_boost(struct wait_queue_entry *_wait,
16193 unsigned mode, int sync, void *key)
16195 struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
16196 struct i915_request *rq = wait->request;
16199 * If we missed the vblank, but the request is already running it
16200 * is reasonable to assume that it will complete before the next
16201 * vblank without our intervention, so leave RPS alone.
16203 if (!i915_request_started(rq))
16204 intel_rps_boost(rq);
16205 i915_request_put(rq);
16207 drm_crtc_vblank_put(wait->crtc);
16209 list_del(&wait->wait.entry);
16214 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
16215 struct dma_fence *fence)
16217 struct wait_rps_boost *wait;
16219 if (!dma_fence_is_i915(fence))
16222 if (INTEL_GEN(to_i915(crtc->dev)) < 6)
16225 if (drm_crtc_vblank_get(crtc))
16228 wait = kmalloc(sizeof(*wait), GFP_KERNEL);
16230 drm_crtc_vblank_put(crtc);
16234 wait->request = to_request(dma_fence_get(fence));
16237 wait->wait.func = do_rps_boost;
16238 wait->wait.flags = 0;
16240 add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
16243 static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
16245 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
16246 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16247 struct drm_framebuffer *fb = plane_state->hw.fb;
16248 struct i915_vma *vma;
16250 if (plane->id == PLANE_CURSOR &&
16251 INTEL_INFO(dev_priv)->display.cursor_needs_physical) {
16252 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
16253 const int align = intel_cursor_alignment(dev_priv);
16256 err = i915_gem_object_attach_phys(obj, align);
16261 vma = intel_pin_and_fence_fb_obj(fb,
16262 &plane_state->view,
16263 intel_plane_uses_fence(plane_state),
16264 &plane_state->flags);
16266 return PTR_ERR(vma);
16268 plane_state->vma = vma;
16273 static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
16275 struct i915_vma *vma;
16277 vma = fetch_and_zero(&old_plane_state->vma);
16279 intel_unpin_fb_vma(vma, old_plane_state->flags);
16282 static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
16284 struct i915_sched_attr attr = {
16285 .priority = I915_USER_PRIORITY(I915_PRIORITY_DISPLAY),
16288 i915_gem_object_wait_priority(obj, 0, &attr);
16292 * intel_prepare_plane_fb - Prepare fb for usage on plane
16293 * @_plane: drm plane to prepare for
16294 * @_new_plane_state: the plane state being prepared
16296 * Prepares a framebuffer for usage on a display plane. Generally this
16297 * involves pinning the underlying object and updating the frontbuffer tracking
16298 * bits. Some older platforms need special physical address handling for
16301 * Returns 0 on success, negative error code on failure.
16304 intel_prepare_plane_fb(struct drm_plane *_plane,
16305 struct drm_plane_state *_new_plane_state)
16307 struct intel_plane *plane = to_intel_plane(_plane);
16308 struct intel_plane_state *new_plane_state =
16309 to_intel_plane_state(_new_plane_state);
16310 struct intel_atomic_state *state =
16311 to_intel_atomic_state(new_plane_state->uapi.state);
16312 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16313 const struct intel_plane_state *old_plane_state =
16314 intel_atomic_get_old_plane_state(state, plane);
16315 struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb);
16316 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_plane_state->hw.fb);
16320 const struct intel_crtc_state *crtc_state =
16321 intel_atomic_get_new_crtc_state(state,
16322 to_intel_crtc(old_plane_state->hw.crtc));
16324 /* Big Hammer, we also need to ensure that any pending
16325 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
16326 * current scanout is retired before unpinning the old
16327 * framebuffer. Note that we rely on userspace rendering
16328 * into the buffer attached to the pipe they are waiting
16329 * on. If not, userspace generates a GPU hang with IPEHR
16330 * point to the MI_WAIT_FOR_EVENT.
16332 * This should only fail upon a hung GPU, in which case we
16333 * can safely continue.
16335 if (needs_modeset(crtc_state)) {
16336 ret = i915_sw_fence_await_reservation(&state->commit_ready,
16337 old_obj->base.resv, NULL,
16345 if (new_plane_state->uapi.fence) { /* explicit fencing */
16346 ret = i915_sw_fence_await_dma_fence(&state->commit_ready,
16347 new_plane_state->uapi.fence,
16348 i915_fence_timeout(dev_priv),
16357 ret = i915_gem_object_pin_pages(obj);
16361 ret = intel_plane_pin_fb(new_plane_state);
16363 i915_gem_object_unpin_pages(obj);
16367 fb_obj_bump_render_priority(obj);
16368 i915_gem_object_flush_frontbuffer(obj, ORIGIN_DIRTYFB);
16370 if (!new_plane_state->uapi.fence) { /* implicit fencing */
16371 struct dma_fence *fence;
16373 ret = i915_sw_fence_await_reservation(&state->commit_ready,
16374 obj->base.resv, NULL,
16376 i915_fence_timeout(dev_priv),
16381 fence = dma_resv_get_excl_rcu(obj->base.resv);
16383 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
16385 dma_fence_put(fence);
16388 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
16389 new_plane_state->uapi.fence);
16393 * We declare pageflips to be interactive and so merit a small bias
16394 * towards upclocking to deliver the frame on time. By only changing
16395 * the RPS thresholds to sample more regularly and aim for higher
16396 * clocks we can hopefully deliver low power workloads (like kodi)
16397 * that are not quite steady state without resorting to forcing
16398 * maximum clocks following a vblank miss (see do_rps_boost()).
16400 if (!state->rps_interactive) {
16401 intel_rps_mark_interactive(&dev_priv->gt.rps, true);
16402 state->rps_interactive = true;
16408 intel_plane_unpin_fb(new_plane_state);
16414 * intel_cleanup_plane_fb - Cleans up an fb after plane use
16415 * @plane: drm plane to clean up for
16416 * @_old_plane_state: the state from the previous modeset
16418 * Cleans up a framebuffer that has just been removed from a plane.
16421 intel_cleanup_plane_fb(struct drm_plane *plane,
16422 struct drm_plane_state *_old_plane_state)
16424 struct intel_plane_state *old_plane_state =
16425 to_intel_plane_state(_old_plane_state);
16426 struct intel_atomic_state *state =
16427 to_intel_atomic_state(old_plane_state->uapi.state);
16428 struct drm_i915_private *dev_priv = to_i915(plane->dev);
16429 struct drm_i915_gem_object *obj = intel_fb_obj(old_plane_state->hw.fb);
16434 if (state->rps_interactive) {
16435 intel_rps_mark_interactive(&dev_priv->gt.rps, false);
16436 state->rps_interactive = false;
16439 /* Should only be called after a successful intel_prepare_plane_fb()! */
16440 intel_plane_unpin_fb(old_plane_state);
16444 * intel_plane_destroy - destroy a plane
16445 * @plane: plane to destroy
16447 * Common destruction function for all types of planes (primary, cursor,
16450 void intel_plane_destroy(struct drm_plane *plane)
16452 drm_plane_cleanup(plane);
16453 kfree(to_intel_plane(plane));
16456 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
16457 u32 format, u64 modifier)
16459 switch (modifier) {
16460 case DRM_FORMAT_MOD_LINEAR:
16461 case I915_FORMAT_MOD_X_TILED:
16468 case DRM_FORMAT_C8:
16469 case DRM_FORMAT_RGB565:
16470 case DRM_FORMAT_XRGB1555:
16471 case DRM_FORMAT_XRGB8888:
16472 return modifier == DRM_FORMAT_MOD_LINEAR ||
16473 modifier == I915_FORMAT_MOD_X_TILED;
16479 static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
16480 u32 format, u64 modifier)
16482 switch (modifier) {
16483 case DRM_FORMAT_MOD_LINEAR:
16484 case I915_FORMAT_MOD_X_TILED:
16491 case DRM_FORMAT_C8:
16492 case DRM_FORMAT_RGB565:
16493 case DRM_FORMAT_XRGB8888:
16494 case DRM_FORMAT_XBGR8888:
16495 case DRM_FORMAT_ARGB8888:
16496 case DRM_FORMAT_ABGR8888:
16497 case DRM_FORMAT_XRGB2101010:
16498 case DRM_FORMAT_XBGR2101010:
16499 case DRM_FORMAT_ARGB2101010:
16500 case DRM_FORMAT_ABGR2101010:
16501 case DRM_FORMAT_XBGR16161616F:
16502 return modifier == DRM_FORMAT_MOD_LINEAR ||
16503 modifier == I915_FORMAT_MOD_X_TILED;
16509 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
16510 u32 format, u64 modifier)
16512 return modifier == DRM_FORMAT_MOD_LINEAR &&
16513 format == DRM_FORMAT_ARGB8888;
16516 static const struct drm_plane_funcs i965_plane_funcs = {
16517 .update_plane = drm_atomic_helper_update_plane,
16518 .disable_plane = drm_atomic_helper_disable_plane,
16519 .destroy = intel_plane_destroy,
16520 .atomic_duplicate_state = intel_plane_duplicate_state,
16521 .atomic_destroy_state = intel_plane_destroy_state,
16522 .format_mod_supported = i965_plane_format_mod_supported,
16525 static const struct drm_plane_funcs i8xx_plane_funcs = {
16526 .update_plane = drm_atomic_helper_update_plane,
16527 .disable_plane = drm_atomic_helper_disable_plane,
16528 .destroy = intel_plane_destroy,
16529 .atomic_duplicate_state = intel_plane_duplicate_state,
16530 .atomic_destroy_state = intel_plane_destroy_state,
16531 .format_mod_supported = i8xx_plane_format_mod_supported,
16535 intel_legacy_cursor_update(struct drm_plane *_plane,
16536 struct drm_crtc *_crtc,
16537 struct drm_framebuffer *fb,
16538 int crtc_x, int crtc_y,
16539 unsigned int crtc_w, unsigned int crtc_h,
16540 u32 src_x, u32 src_y,
16541 u32 src_w, u32 src_h,
16542 struct drm_modeset_acquire_ctx *ctx)
16544 struct intel_plane *plane = to_intel_plane(_plane);
16545 struct intel_crtc *crtc = to_intel_crtc(_crtc);
16546 struct intel_plane_state *old_plane_state =
16547 to_intel_plane_state(plane->base.state);
16548 struct intel_plane_state *new_plane_state;
16549 struct intel_crtc_state *crtc_state =
16550 to_intel_crtc_state(crtc->base.state);
16551 struct intel_crtc_state *new_crtc_state;
16555 * When crtc is inactive or there is a modeset pending,
16556 * wait for it to complete in the slowpath
16558 if (!crtc_state->hw.active || needs_modeset(crtc_state) ||
16559 crtc_state->update_pipe)
16563 * Don't do an async update if there is an outstanding commit modifying
16564 * the plane. This prevents our async update's changes from getting
16565 * overridden by a previous synchronous update's state.
16567 if (old_plane_state->uapi.commit &&
16568 !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done))
16572 * If any parameters change that may affect watermarks,
16573 * take the slowpath. Only changing fb or position should be
16576 if (old_plane_state->uapi.crtc != &crtc->base ||
16577 old_plane_state->uapi.src_w != src_w ||
16578 old_plane_state->uapi.src_h != src_h ||
16579 old_plane_state->uapi.crtc_w != crtc_w ||
16580 old_plane_state->uapi.crtc_h != crtc_h ||
16581 !old_plane_state->uapi.fb != !fb)
16584 new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base));
16585 if (!new_plane_state)
16588 new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base));
16589 if (!new_crtc_state) {
16594 drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb);
16596 new_plane_state->uapi.src_x = src_x;
16597 new_plane_state->uapi.src_y = src_y;
16598 new_plane_state->uapi.src_w = src_w;
16599 new_plane_state->uapi.src_h = src_h;
16600 new_plane_state->uapi.crtc_x = crtc_x;
16601 new_plane_state->uapi.crtc_y = crtc_y;
16602 new_plane_state->uapi.crtc_w = crtc_w;
16603 new_plane_state->uapi.crtc_h = crtc_h;
16605 intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state);
16607 ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
16608 old_plane_state, new_plane_state);
16612 ret = intel_plane_pin_fb(new_plane_state);
16616 intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb),
16618 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
16619 to_intel_frontbuffer(new_plane_state->hw.fb),
16620 plane->frontbuffer_bit);
16622 /* Swap plane state */
16623 plane->base.state = &new_plane_state->uapi;
16626 * We cannot swap crtc_state as it may be in use by an atomic commit or
16627 * page flip that's running simultaneously. If we swap crtc_state and
16628 * destroy the old state, we will cause a use-after-free there.
16630 * Only update active_planes, which is needed for our internal
16631 * bookkeeping. Either value will do the right thing when updating
16632 * planes atomically. If the cursor was part of the atomic update then
16633 * we would have taken the slowpath.
16635 crtc_state->active_planes = new_crtc_state->active_planes;
16637 if (new_plane_state->uapi.visible)
16638 intel_update_plane(plane, crtc_state, new_plane_state);
16640 intel_disable_plane(plane, crtc_state);
16642 intel_plane_unpin_fb(old_plane_state);
16645 if (new_crtc_state)
16646 intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
16648 intel_plane_destroy_state(&plane->base, &new_plane_state->uapi);
16650 intel_plane_destroy_state(&plane->base, &old_plane_state->uapi);
16654 return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb,
16655 crtc_x, crtc_y, crtc_w, crtc_h,
16656 src_x, src_y, src_w, src_h, ctx);
16659 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
16660 .update_plane = intel_legacy_cursor_update,
16661 .disable_plane = drm_atomic_helper_disable_plane,
16662 .destroy = intel_plane_destroy,
16663 .atomic_duplicate_state = intel_plane_duplicate_state,
16664 .atomic_destroy_state = intel_plane_destroy_state,
16665 .format_mod_supported = intel_cursor_format_mod_supported,
16668 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
16669 enum i9xx_plane_id i9xx_plane)
16671 if (!HAS_FBC(dev_priv))
16674 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
16675 return i9xx_plane == PLANE_A; /* tied to pipe A */
16676 else if (IS_IVYBRIDGE(dev_priv))
16677 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
16678 i9xx_plane == PLANE_C;
16679 else if (INTEL_GEN(dev_priv) >= 4)
16680 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
16682 return i9xx_plane == PLANE_A;
16685 static struct intel_plane *
16686 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
16688 struct intel_plane *plane;
16689 const struct drm_plane_funcs *plane_funcs;
16690 unsigned int supported_rotations;
16691 const u32 *formats;
16695 if (INTEL_GEN(dev_priv) >= 9)
16696 return skl_universal_plane_create(dev_priv, pipe,
16699 plane = intel_plane_alloc();
16703 plane->pipe = pipe;
16705 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
16706 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
16708 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4 &&
16709 INTEL_NUM_PIPES(dev_priv) == 2)
16710 plane->i9xx_plane = (enum i9xx_plane_id) !pipe;
16712 plane->i9xx_plane = (enum i9xx_plane_id) pipe;
16713 plane->id = PLANE_PRIMARY;
16714 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
16716 plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane);
16717 if (plane->has_fbc) {
16718 struct intel_fbc *fbc = &dev_priv->fbc;
16720 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
16723 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16724 formats = vlv_primary_formats;
16725 num_formats = ARRAY_SIZE(vlv_primary_formats);
16726 } else if (INTEL_GEN(dev_priv) >= 4) {
16728 * WaFP16GammaEnabling:ivb
16729 * "Workaround : When using the 64-bit format, the plane
16730 * output on each color channel has one quarter amplitude.
16731 * It can be brought up to full amplitude by using pipe
16732 * gamma correction or pipe color space conversion to
16733 * multiply the plane output by four."
16735 * There is no dedicated plane gamma for the primary plane,
16736 * and using the pipe gamma/csc could conflict with other
16737 * planes, so we choose not to expose fp16 on IVB primary
16738 * planes. HSW primary planes no longer have this problem.
16740 if (IS_IVYBRIDGE(dev_priv)) {
16741 formats = ivb_primary_formats;
16742 num_formats = ARRAY_SIZE(ivb_primary_formats);
16744 formats = i965_primary_formats;
16745 num_formats = ARRAY_SIZE(i965_primary_formats);
16748 formats = i8xx_primary_formats;
16749 num_formats = ARRAY_SIZE(i8xx_primary_formats);
16752 if (INTEL_GEN(dev_priv) >= 4)
16753 plane_funcs = &i965_plane_funcs;
16755 plane_funcs = &i8xx_plane_funcs;
16757 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16758 plane->min_cdclk = vlv_plane_min_cdclk;
16759 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
16760 plane->min_cdclk = hsw_plane_min_cdclk;
16761 else if (IS_IVYBRIDGE(dev_priv))
16762 plane->min_cdclk = ivb_plane_min_cdclk;
16764 plane->min_cdclk = i9xx_plane_min_cdclk;
16766 plane->max_stride = i9xx_plane_max_stride;
16767 plane->update_plane = i9xx_update_plane;
16768 plane->disable_plane = i9xx_disable_plane;
16769 plane->get_hw_state = i9xx_plane_get_hw_state;
16770 plane->check_plane = i9xx_plane_check;
16772 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
16773 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
16775 formats, num_formats,
16776 i9xx_format_modifiers,
16777 DRM_PLANE_TYPE_PRIMARY,
16778 "primary %c", pipe_name(pipe));
16780 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
16782 formats, num_formats,
16783 i9xx_format_modifiers,
16784 DRM_PLANE_TYPE_PRIMARY,
16786 plane_name(plane->i9xx_plane));
16790 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
16791 supported_rotations =
16792 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
16793 DRM_MODE_REFLECT_X;
16794 } else if (INTEL_GEN(dev_priv) >= 4) {
16795 supported_rotations =
16796 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
16798 supported_rotations = DRM_MODE_ROTATE_0;
16801 if (INTEL_GEN(dev_priv) >= 4)
16802 drm_plane_create_rotation_property(&plane->base,
16804 supported_rotations);
16807 drm_plane_create_zpos_immutable_property(&plane->base, zpos);
16809 drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
16814 intel_plane_free(plane);
16816 return ERR_PTR(ret);
16819 static struct intel_plane *
16820 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
16823 struct intel_plane *cursor;
16826 cursor = intel_plane_alloc();
16827 if (IS_ERR(cursor))
16830 cursor->pipe = pipe;
16831 cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
16832 cursor->id = PLANE_CURSOR;
16833 cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
16835 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
16836 cursor->max_stride = i845_cursor_max_stride;
16837 cursor->update_plane = i845_update_cursor;
16838 cursor->disable_plane = i845_disable_cursor;
16839 cursor->get_hw_state = i845_cursor_get_hw_state;
16840 cursor->check_plane = i845_check_cursor;
16842 cursor->max_stride = i9xx_cursor_max_stride;
16843 cursor->update_plane = i9xx_update_cursor;
16844 cursor->disable_plane = i9xx_disable_cursor;
16845 cursor->get_hw_state = i9xx_cursor_get_hw_state;
16846 cursor->check_plane = i9xx_check_cursor;
16849 cursor->cursor.base = ~0;
16850 cursor->cursor.cntl = ~0;
16852 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
16853 cursor->cursor.size = ~0;
16855 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
16856 0, &intel_cursor_plane_funcs,
16857 intel_cursor_formats,
16858 ARRAY_SIZE(intel_cursor_formats),
16859 cursor_format_modifiers,
16860 DRM_PLANE_TYPE_CURSOR,
16861 "cursor %c", pipe_name(pipe));
16865 if (INTEL_GEN(dev_priv) >= 4)
16866 drm_plane_create_rotation_property(&cursor->base,
16868 DRM_MODE_ROTATE_0 |
16869 DRM_MODE_ROTATE_180);
16871 zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
16872 drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
16874 if (INTEL_GEN(dev_priv) >= 12)
16875 drm_plane_enable_fb_damage_clips(&cursor->base);
16877 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
16882 intel_plane_free(cursor);
16884 return ERR_PTR(ret);
16887 #define INTEL_CRTC_FUNCS \
16888 .gamma_set = drm_atomic_helper_legacy_gamma_set, \
16889 .set_config = drm_atomic_helper_set_config, \
16890 .destroy = intel_crtc_destroy, \
16891 .page_flip = drm_atomic_helper_page_flip, \
16892 .atomic_duplicate_state = intel_crtc_duplicate_state, \
16893 .atomic_destroy_state = intel_crtc_destroy_state, \
16894 .set_crc_source = intel_crtc_set_crc_source, \
16895 .verify_crc_source = intel_crtc_verify_crc_source, \
16896 .get_crc_sources = intel_crtc_get_crc_sources
16898 static const struct drm_crtc_funcs bdw_crtc_funcs = {
16901 .get_vblank_counter = g4x_get_vblank_counter,
16902 .enable_vblank = bdw_enable_vblank,
16903 .disable_vblank = bdw_disable_vblank,
16904 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16907 static const struct drm_crtc_funcs ilk_crtc_funcs = {
16910 .get_vblank_counter = g4x_get_vblank_counter,
16911 .enable_vblank = ilk_enable_vblank,
16912 .disable_vblank = ilk_disable_vblank,
16913 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16916 static const struct drm_crtc_funcs g4x_crtc_funcs = {
16919 .get_vblank_counter = g4x_get_vblank_counter,
16920 .enable_vblank = i965_enable_vblank,
16921 .disable_vblank = i965_disable_vblank,
16922 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16925 static const struct drm_crtc_funcs i965_crtc_funcs = {
16928 .get_vblank_counter = i915_get_vblank_counter,
16929 .enable_vblank = i965_enable_vblank,
16930 .disable_vblank = i965_disable_vblank,
16931 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16934 static const struct drm_crtc_funcs i915gm_crtc_funcs = {
16937 .get_vblank_counter = i915_get_vblank_counter,
16938 .enable_vblank = i915gm_enable_vblank,
16939 .disable_vblank = i915gm_disable_vblank,
16940 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16943 static const struct drm_crtc_funcs i915_crtc_funcs = {
16946 .get_vblank_counter = i915_get_vblank_counter,
16947 .enable_vblank = i8xx_enable_vblank,
16948 .disable_vblank = i8xx_disable_vblank,
16949 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16952 static const struct drm_crtc_funcs i8xx_crtc_funcs = {
16955 /* no hw vblank counter */
16956 .enable_vblank = i8xx_enable_vblank,
16957 .disable_vblank = i8xx_disable_vblank,
16958 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16961 static struct intel_crtc *intel_crtc_alloc(void)
16963 struct intel_crtc_state *crtc_state;
16964 struct intel_crtc *crtc;
16966 crtc = kzalloc(sizeof(*crtc), GFP_KERNEL);
16968 return ERR_PTR(-ENOMEM);
16970 crtc_state = intel_crtc_state_alloc(crtc);
16973 return ERR_PTR(-ENOMEM);
16976 crtc->base.state = &crtc_state->uapi;
16977 crtc->config = crtc_state;
16982 static void intel_crtc_free(struct intel_crtc *crtc)
16984 intel_crtc_destroy_state(&crtc->base, crtc->base.state);
16988 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv)
16990 struct intel_plane *plane;
16992 for_each_intel_plane(&dev_priv->drm, plane) {
16993 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
16996 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base);
17000 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
17002 struct intel_plane *primary, *cursor;
17003 const struct drm_crtc_funcs *funcs;
17004 struct intel_crtc *crtc;
17007 crtc = intel_crtc_alloc();
17009 return PTR_ERR(crtc);
17012 crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[pipe];
17014 primary = intel_primary_plane_create(dev_priv, pipe);
17015 if (IS_ERR(primary)) {
17016 ret = PTR_ERR(primary);
17019 crtc->plane_ids_mask |= BIT(primary->id);
17021 for_each_sprite(dev_priv, pipe, sprite) {
17022 struct intel_plane *plane;
17024 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
17025 if (IS_ERR(plane)) {
17026 ret = PTR_ERR(plane);
17029 crtc->plane_ids_mask |= BIT(plane->id);
17032 cursor = intel_cursor_plane_create(dev_priv, pipe);
17033 if (IS_ERR(cursor)) {
17034 ret = PTR_ERR(cursor);
17037 crtc->plane_ids_mask |= BIT(cursor->id);
17039 if (HAS_GMCH(dev_priv)) {
17040 if (IS_CHERRYVIEW(dev_priv) ||
17041 IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv))
17042 funcs = &g4x_crtc_funcs;
17043 else if (IS_GEN(dev_priv, 4))
17044 funcs = &i965_crtc_funcs;
17045 else if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv))
17046 funcs = &i915gm_crtc_funcs;
17047 else if (IS_GEN(dev_priv, 3))
17048 funcs = &i915_crtc_funcs;
17050 funcs = &i8xx_crtc_funcs;
17052 if (INTEL_GEN(dev_priv) >= 8)
17053 funcs = &bdw_crtc_funcs;
17055 funcs = &ilk_crtc_funcs;
17058 ret = drm_crtc_init_with_planes(&dev_priv->drm, &crtc->base,
17059 &primary->base, &cursor->base,
17060 funcs, "pipe %c", pipe_name(pipe));
17064 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
17065 dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
17066 dev_priv->pipe_to_crtc_mapping[pipe] = crtc;
17068 if (INTEL_GEN(dev_priv) < 9) {
17069 enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
17071 BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
17072 dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
17073 dev_priv->plane_to_crtc_mapping[i9xx_plane] = crtc;
17076 if (INTEL_GEN(dev_priv) >= 10)
17077 drm_crtc_create_scaling_filter_property(&crtc->base,
17078 BIT(DRM_SCALING_FILTER_DEFAULT) |
17079 BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR));
17081 intel_color_init(crtc);
17083 intel_crtc_crc_init(crtc);
17085 drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) != crtc->pipe);
17090 intel_crtc_free(crtc);
17095 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
17096 struct drm_file *file)
17098 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
17099 struct drm_crtc *drmmode_crtc;
17100 struct intel_crtc *crtc;
17102 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
17106 crtc = to_intel_crtc(drmmode_crtc);
17107 pipe_from_crtc_id->pipe = crtc->pipe;
17112 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
17114 struct drm_device *dev = encoder->base.dev;
17115 struct intel_encoder *source_encoder;
17116 u32 possible_clones = 0;
17118 for_each_intel_encoder(dev, source_encoder) {
17119 if (encoders_cloneable(encoder, source_encoder))
17120 possible_clones |= drm_encoder_mask(&source_encoder->base);
17123 return possible_clones;
17126 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
17128 struct drm_device *dev = encoder->base.dev;
17129 struct intel_crtc *crtc;
17130 u32 possible_crtcs = 0;
17132 for_each_intel_crtc(dev, crtc) {
17133 if (encoder->pipe_mask & BIT(crtc->pipe))
17134 possible_crtcs |= drm_crtc_mask(&crtc->base);
17137 return possible_crtcs;
17140 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
17142 if (!IS_MOBILE(dev_priv))
17145 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)
17148 if (IS_GEN(dev_priv, 5) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
17154 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
17156 if (INTEL_GEN(dev_priv) >= 9)
17159 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
17162 if (HAS_PCH_LPT_H(dev_priv) &&
17163 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
17166 /* DDI E can't be used if DDI A requires 4 lanes */
17167 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
17170 if (!dev_priv->vbt.int_crt_support)
17176 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
17181 if (HAS_DDI(dev_priv))
17184 * This w/a is needed at least on CPT/PPT, but to be sure apply it
17185 * everywhere where registers can be write protected.
17187 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
17192 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
17193 u32 val = intel_de_read(dev_priv, PP_CONTROL(pps_idx));
17195 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
17196 intel_de_write(dev_priv, PP_CONTROL(pps_idx), val);
17200 static void intel_pps_init(struct drm_i915_private *dev_priv)
17202 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
17203 dev_priv->pps_mmio_base = PCH_PPS_BASE;
17204 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
17205 dev_priv->pps_mmio_base = VLV_PPS_BASE;
17207 dev_priv->pps_mmio_base = PPS_BASE;
17209 intel_pps_unlock_regs_wa(dev_priv);
17212 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
17214 struct intel_encoder *encoder;
17215 bool dpd_is_edp = false;
17217 intel_pps_init(dev_priv);
17219 if (!HAS_DISPLAY(dev_priv))
17222 if (IS_ROCKETLAKE(dev_priv)) {
17223 intel_ddi_init(dev_priv, PORT_A);
17224 intel_ddi_init(dev_priv, PORT_B);
17225 intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */
17226 intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */
17227 } else if (INTEL_GEN(dev_priv) >= 12) {
17228 intel_ddi_init(dev_priv, PORT_A);
17229 intel_ddi_init(dev_priv, PORT_B);
17230 intel_ddi_init(dev_priv, PORT_D);
17231 intel_ddi_init(dev_priv, PORT_E);
17232 intel_ddi_init(dev_priv, PORT_F);
17233 intel_ddi_init(dev_priv, PORT_G);
17234 intel_ddi_init(dev_priv, PORT_H);
17235 intel_ddi_init(dev_priv, PORT_I);
17236 icl_dsi_init(dev_priv);
17237 } else if (IS_JSL_EHL(dev_priv)) {
17238 intel_ddi_init(dev_priv, PORT_A);
17239 intel_ddi_init(dev_priv, PORT_B);
17240 intel_ddi_init(dev_priv, PORT_C);
17241 intel_ddi_init(dev_priv, PORT_D);
17242 icl_dsi_init(dev_priv);
17243 } else if (IS_GEN(dev_priv, 11)) {
17244 intel_ddi_init(dev_priv, PORT_A);
17245 intel_ddi_init(dev_priv, PORT_B);
17246 intel_ddi_init(dev_priv, PORT_C);
17247 intel_ddi_init(dev_priv, PORT_D);
17248 intel_ddi_init(dev_priv, PORT_E);
17250 * On some ICL SKUs port F is not present. No strap bits for
17251 * this, so rely on VBT.
17252 * Work around broken VBTs on SKUs known to have no port F.
17254 if (IS_ICL_WITH_PORT_F(dev_priv) &&
17255 intel_bios_is_port_present(dev_priv, PORT_F))
17256 intel_ddi_init(dev_priv, PORT_F);
17258 icl_dsi_init(dev_priv);
17259 } else if (IS_GEN9_LP(dev_priv)) {
17261 * FIXME: Broxton doesn't support port detection via the
17262 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
17263 * detect the ports.
17265 intel_ddi_init(dev_priv, PORT_A);
17266 intel_ddi_init(dev_priv, PORT_B);
17267 intel_ddi_init(dev_priv, PORT_C);
17269 vlv_dsi_init(dev_priv);
17270 } else if (HAS_DDI(dev_priv)) {
17273 if (intel_ddi_crt_present(dev_priv))
17274 intel_crt_init(dev_priv);
17277 * Haswell uses DDI functions to detect digital outputs.
17278 * On SKL pre-D0 the strap isn't connected, so we assume
17281 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
17282 /* WaIgnoreDDIAStrap: skl */
17283 if (found || IS_GEN9_BC(dev_priv))
17284 intel_ddi_init(dev_priv, PORT_A);
17286 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
17288 found = intel_de_read(dev_priv, SFUSE_STRAP);
17290 if (found & SFUSE_STRAP_DDIB_DETECTED)
17291 intel_ddi_init(dev_priv, PORT_B);
17292 if (found & SFUSE_STRAP_DDIC_DETECTED)
17293 intel_ddi_init(dev_priv, PORT_C);
17294 if (found & SFUSE_STRAP_DDID_DETECTED)
17295 intel_ddi_init(dev_priv, PORT_D);
17296 if (found & SFUSE_STRAP_DDIF_DETECTED)
17297 intel_ddi_init(dev_priv, PORT_F);
17299 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
17301 if (IS_GEN9_BC(dev_priv) &&
17302 intel_bios_is_port_present(dev_priv, PORT_E))
17303 intel_ddi_init(dev_priv, PORT_E);
17305 } else if (HAS_PCH_SPLIT(dev_priv)) {
17309 * intel_edp_init_connector() depends on this completing first,
17310 * to prevent the registration of both eDP and LVDS and the
17311 * incorrect sharing of the PPS.
17313 intel_lvds_init(dev_priv);
17314 intel_crt_init(dev_priv);
17316 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
17318 if (ilk_has_edp_a(dev_priv))
17319 intel_dp_init(dev_priv, DP_A, PORT_A);
17321 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
17322 /* PCH SDVOB multiplex with HDMIB */
17323 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
17325 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
17326 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
17327 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
17330 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
17331 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
17333 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED)
17334 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
17336 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
17337 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
17339 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
17340 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
17341 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
17342 bool has_edp, has_port;
17344 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
17345 intel_crt_init(dev_priv);
17348 * The DP_DETECTED bit is the latched state of the DDC
17349 * SDA pin at boot. However since eDP doesn't require DDC
17350 * (no way to plug in a DP->HDMI dongle) the DDC pins for
17351 * eDP ports may have been muxed to an alternate function.
17352 * Thus we can't rely on the DP_DETECTED bit alone to detect
17353 * eDP ports. Consult the VBT as well as DP_DETECTED to
17354 * detect eDP ports.
17356 * Sadly the straps seem to be missing sometimes even for HDMI
17357 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
17358 * and VBT for the presence of the port. Additionally we can't
17359 * trust the port type the VBT declares as we've seen at least
17360 * HDMI ports that the VBT claim are DP or eDP.
17362 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
17363 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
17364 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
17365 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
17366 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
17367 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
17369 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
17370 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
17371 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
17372 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
17373 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
17374 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
17376 if (IS_CHERRYVIEW(dev_priv)) {
17378 * eDP not supported on port D,
17379 * so no need to worry about it
17381 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
17382 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
17383 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
17384 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
17385 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
17388 vlv_dsi_init(dev_priv);
17389 } else if (IS_PINEVIEW(dev_priv)) {
17390 intel_lvds_init(dev_priv);
17391 intel_crt_init(dev_priv);
17392 } else if (IS_GEN_RANGE(dev_priv, 3, 4)) {
17393 bool found = false;
17395 if (IS_MOBILE(dev_priv))
17396 intel_lvds_init(dev_priv);
17398 intel_crt_init(dev_priv);
17400 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
17401 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
17402 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
17403 if (!found && IS_G4X(dev_priv)) {
17404 drm_dbg_kms(&dev_priv->drm,
17405 "probing HDMI on SDVOB\n");
17406 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
17409 if (!found && IS_G4X(dev_priv))
17410 intel_dp_init(dev_priv, DP_B, PORT_B);
17413 /* Before G4X SDVOC doesn't have its own detect register */
17415 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
17416 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");
17417 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
17420 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) {
17422 if (IS_G4X(dev_priv)) {
17423 drm_dbg_kms(&dev_priv->drm,
17424 "probing HDMI on SDVOC\n");
17425 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
17427 if (IS_G4X(dev_priv))
17428 intel_dp_init(dev_priv, DP_C, PORT_C);
17431 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED))
17432 intel_dp_init(dev_priv, DP_D, PORT_D);
17434 if (SUPPORTS_TV(dev_priv))
17435 intel_tv_init(dev_priv);
17436 } else if (IS_GEN(dev_priv, 2)) {
17437 if (IS_I85X(dev_priv))
17438 intel_lvds_init(dev_priv);
17440 intel_crt_init(dev_priv);
17441 intel_dvo_init(dev_priv);
17444 intel_psr_init(dev_priv);
17446 for_each_intel_encoder(&dev_priv->drm, encoder) {
17447 encoder->base.possible_crtcs =
17448 intel_encoder_possible_crtcs(encoder);
17449 encoder->base.possible_clones =
17450 intel_encoder_possible_clones(encoder);
17453 intel_init_pch_refclk(dev_priv);
17455 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
17458 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
17460 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
17462 drm_framebuffer_cleanup(fb);
17463 intel_frontbuffer_put(intel_fb->frontbuffer);
17468 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
17469 struct drm_file *file,
17470 unsigned int *handle)
17472 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
17473 struct drm_i915_private *i915 = to_i915(obj->base.dev);
17475 if (obj->userptr.mm) {
17476 drm_dbg(&i915->drm,
17477 "attempting to use a userptr for a framebuffer, denied\n");
17481 return drm_gem_handle_create(file, &obj->base, handle);
17484 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
17485 struct drm_file *file,
17486 unsigned flags, unsigned color,
17487 struct drm_clip_rect *clips,
17488 unsigned num_clips)
17490 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
17492 i915_gem_object_flush_if_display(obj);
17493 intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
17498 static const struct drm_framebuffer_funcs intel_fb_funcs = {
17499 .destroy = intel_user_framebuffer_destroy,
17500 .create_handle = intel_user_framebuffer_create_handle,
17501 .dirty = intel_user_framebuffer_dirty,
17504 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
17505 struct drm_i915_gem_object *obj,
17506 struct drm_mode_fb_cmd2 *mode_cmd)
17508 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
17509 struct drm_framebuffer *fb = &intel_fb->base;
17511 unsigned int tiling, stride;
17515 intel_fb->frontbuffer = intel_frontbuffer_get(obj);
17516 if (!intel_fb->frontbuffer)
17519 i915_gem_object_lock(obj, NULL);
17520 tiling = i915_gem_object_get_tiling(obj);
17521 stride = i915_gem_object_get_stride(obj);
17522 i915_gem_object_unlock(obj);
17524 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
17526 * If there's a fence, enforce that
17527 * the fb modifier and tiling mode match.
17529 if (tiling != I915_TILING_NONE &&
17530 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
17531 drm_dbg_kms(&dev_priv->drm,
17532 "tiling_mode doesn't match fb modifier\n");
17536 if (tiling == I915_TILING_X) {
17537 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
17538 } else if (tiling == I915_TILING_Y) {
17539 drm_dbg_kms(&dev_priv->drm,
17540 "No Y tiling for legacy addfb\n");
17545 if (!drm_any_plane_has_format(&dev_priv->drm,
17546 mode_cmd->pixel_format,
17547 mode_cmd->modifier[0])) {
17548 struct drm_format_name_buf format_name;
17550 drm_dbg_kms(&dev_priv->drm,
17551 "unsupported pixel format %s / modifier 0x%llx\n",
17552 drm_get_format_name(mode_cmd->pixel_format,
17554 mode_cmd->modifier[0]);
17559 * gen2/3 display engine uses the fence if present,
17560 * so the tiling mode must match the fb modifier exactly.
17562 if (INTEL_GEN(dev_priv) < 4 &&
17563 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
17564 drm_dbg_kms(&dev_priv->drm,
17565 "tiling_mode must match fb modifier exactly on gen2/3\n");
17569 max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
17570 mode_cmd->modifier[0]);
17571 if (mode_cmd->pitches[0] > max_stride) {
17572 drm_dbg_kms(&dev_priv->drm,
17573 "%s pitch (%u) must be at most %d\n",
17574 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
17575 "tiled" : "linear",
17576 mode_cmd->pitches[0], max_stride);
17581 * If there's a fence, enforce that
17582 * the fb pitch and fence stride match.
17584 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
17585 drm_dbg_kms(&dev_priv->drm,
17586 "pitch (%d) must match tiling stride (%d)\n",
17587 mode_cmd->pitches[0], stride);
17591 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
17592 if (mode_cmd->offsets[0] != 0) {
17593 drm_dbg_kms(&dev_priv->drm,
17594 "plane 0 offset (0x%08x) must be 0\n",
17595 mode_cmd->offsets[0]);
17599 drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
17601 for (i = 0; i < fb->format->num_planes; i++) {
17602 u32 stride_alignment;
17604 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
17605 drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n",
17610 stride_alignment = intel_fb_stride_alignment(fb, i);
17611 if (fb->pitches[i] & (stride_alignment - 1)) {
17612 drm_dbg_kms(&dev_priv->drm,
17613 "plane %d pitch (%d) must be at least %u byte aligned\n",
17614 i, fb->pitches[i], stride_alignment);
17618 if (is_gen12_ccs_plane(fb, i)) {
17619 int ccs_aux_stride = gen12_ccs_aux_stride(fb, i);
17621 if (fb->pitches[i] != ccs_aux_stride) {
17622 drm_dbg_kms(&dev_priv->drm,
17623 "ccs aux plane %d pitch (%d) must be %d\n",
17625 fb->pitches[i], ccs_aux_stride);
17630 fb->obj[i] = &obj->base;
17633 ret = intel_fill_fb_info(dev_priv, fb);
17637 ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
17639 drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret);
17646 intel_frontbuffer_put(intel_fb->frontbuffer);
17650 static struct drm_framebuffer *
17651 intel_user_framebuffer_create(struct drm_device *dev,
17652 struct drm_file *filp,
17653 const struct drm_mode_fb_cmd2 *user_mode_cmd)
17655 struct drm_framebuffer *fb;
17656 struct drm_i915_gem_object *obj;
17657 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
17659 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
17661 return ERR_PTR(-ENOENT);
17663 fb = intel_framebuffer_create(obj, &mode_cmd);
17664 i915_gem_object_put(obj);
17669 static enum drm_mode_status
17670 intel_mode_valid(struct drm_device *dev,
17671 const struct drm_display_mode *mode)
17673 struct drm_i915_private *dev_priv = to_i915(dev);
17674 int hdisplay_max, htotal_max;
17675 int vdisplay_max, vtotal_max;
17678 * Can't reject DBLSCAN here because Xorg ddxen can add piles
17679 * of DBLSCAN modes to the output's mode list when they detect
17680 * the scaling mode property on the connector. And they don't
17681 * ask the kernel to validate those modes in any way until
17682 * modeset time at which point the client gets a protocol error.
17683 * So in order to not upset those clients we silently ignore the
17684 * DBLSCAN flag on such connectors. For other connectors we will
17685 * reject modes with the DBLSCAN flag in encoder->compute_config().
17686 * And we always reject DBLSCAN modes in connector->mode_valid()
17687 * as we never want such modes on the connector's mode list.
17690 if (mode->vscan > 1)
17691 return MODE_NO_VSCAN;
17693 if (mode->flags & DRM_MODE_FLAG_HSKEW)
17694 return MODE_H_ILLEGAL;
17696 if (mode->flags & (DRM_MODE_FLAG_CSYNC |
17697 DRM_MODE_FLAG_NCSYNC |
17698 DRM_MODE_FLAG_PCSYNC))
17701 if (mode->flags & (DRM_MODE_FLAG_BCAST |
17702 DRM_MODE_FLAG_PIXMUX |
17703 DRM_MODE_FLAG_CLKDIV2))
17706 /* Transcoder timing limits */
17707 if (INTEL_GEN(dev_priv) >= 11) {
17708 hdisplay_max = 16384;
17709 vdisplay_max = 8192;
17710 htotal_max = 16384;
17712 } else if (INTEL_GEN(dev_priv) >= 9 ||
17713 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
17714 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
17715 vdisplay_max = 4096;
17718 } else if (INTEL_GEN(dev_priv) >= 3) {
17719 hdisplay_max = 4096;
17720 vdisplay_max = 4096;
17724 hdisplay_max = 2048;
17725 vdisplay_max = 2048;
17730 if (mode->hdisplay > hdisplay_max ||
17731 mode->hsync_start > htotal_max ||
17732 mode->hsync_end > htotal_max ||
17733 mode->htotal > htotal_max)
17734 return MODE_H_ILLEGAL;
17736 if (mode->vdisplay > vdisplay_max ||
17737 mode->vsync_start > vtotal_max ||
17738 mode->vsync_end > vtotal_max ||
17739 mode->vtotal > vtotal_max)
17740 return MODE_V_ILLEGAL;
17742 if (INTEL_GEN(dev_priv) >= 5) {
17743 if (mode->hdisplay < 64 ||
17744 mode->htotal - mode->hdisplay < 32)
17745 return MODE_H_ILLEGAL;
17747 if (mode->vtotal - mode->vdisplay < 5)
17748 return MODE_V_ILLEGAL;
17750 if (mode->htotal - mode->hdisplay < 32)
17751 return MODE_H_ILLEGAL;
17753 if (mode->vtotal - mode->vdisplay < 3)
17754 return MODE_V_ILLEGAL;
17760 enum drm_mode_status
17761 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
17762 const struct drm_display_mode *mode)
17764 int plane_width_max, plane_height_max;
17767 * intel_mode_valid() should be
17768 * sufficient on older platforms.
17770 if (INTEL_GEN(dev_priv) < 9)
17774 * Most people will probably want a fullscreen
17775 * plane so let's not advertize modes that are
17776 * too big for that.
17778 if (INTEL_GEN(dev_priv) >= 11) {
17779 plane_width_max = 5120;
17780 plane_height_max = 4320;
17782 plane_width_max = 5120;
17783 plane_height_max = 4096;
17786 if (mode->hdisplay > plane_width_max)
17787 return MODE_H_ILLEGAL;
17789 if (mode->vdisplay > plane_height_max)
17790 return MODE_V_ILLEGAL;
17795 static const struct drm_mode_config_funcs intel_mode_funcs = {
17796 .fb_create = intel_user_framebuffer_create,
17797 .get_format_info = intel_get_format_info,
17798 .output_poll_changed = intel_fbdev_output_poll_changed,
17799 .mode_valid = intel_mode_valid,
17800 .atomic_check = intel_atomic_check,
17801 .atomic_commit = intel_atomic_commit,
17802 .atomic_state_alloc = intel_atomic_state_alloc,
17803 .atomic_state_clear = intel_atomic_state_clear,
17804 .atomic_state_free = intel_atomic_state_free,
17808 * intel_init_display_hooks - initialize the display modesetting hooks
17809 * @dev_priv: device private
17811 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
17813 intel_init_cdclk_hooks(dev_priv);
17815 if (INTEL_GEN(dev_priv) >= 9) {
17816 dev_priv->display.get_pipe_config = hsw_get_pipe_config;
17817 dev_priv->display.get_initial_plane_config =
17818 skl_get_initial_plane_config;
17819 dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock;
17820 dev_priv->display.crtc_enable = hsw_crtc_enable;
17821 dev_priv->display.crtc_disable = hsw_crtc_disable;
17822 } else if (HAS_DDI(dev_priv)) {
17823 dev_priv->display.get_pipe_config = hsw_get_pipe_config;
17824 dev_priv->display.get_initial_plane_config =
17825 i9xx_get_initial_plane_config;
17826 dev_priv->display.crtc_compute_clock =
17827 hsw_crtc_compute_clock;
17828 dev_priv->display.crtc_enable = hsw_crtc_enable;
17829 dev_priv->display.crtc_disable = hsw_crtc_disable;
17830 } else if (HAS_PCH_SPLIT(dev_priv)) {
17831 dev_priv->display.get_pipe_config = ilk_get_pipe_config;
17832 dev_priv->display.get_initial_plane_config =
17833 i9xx_get_initial_plane_config;
17834 dev_priv->display.crtc_compute_clock =
17835 ilk_crtc_compute_clock;
17836 dev_priv->display.crtc_enable = ilk_crtc_enable;
17837 dev_priv->display.crtc_disable = ilk_crtc_disable;
17838 } else if (IS_CHERRYVIEW(dev_priv)) {
17839 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17840 dev_priv->display.get_initial_plane_config =
17841 i9xx_get_initial_plane_config;
17842 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
17843 dev_priv->display.crtc_enable = valleyview_crtc_enable;
17844 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17845 } else if (IS_VALLEYVIEW(dev_priv)) {
17846 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17847 dev_priv->display.get_initial_plane_config =
17848 i9xx_get_initial_plane_config;
17849 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
17850 dev_priv->display.crtc_enable = valleyview_crtc_enable;
17851 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17852 } else if (IS_G4X(dev_priv)) {
17853 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17854 dev_priv->display.get_initial_plane_config =
17855 i9xx_get_initial_plane_config;
17856 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
17857 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17858 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17859 } else if (IS_PINEVIEW(dev_priv)) {
17860 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17861 dev_priv->display.get_initial_plane_config =
17862 i9xx_get_initial_plane_config;
17863 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
17864 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17865 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17866 } else if (!IS_GEN(dev_priv, 2)) {
17867 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17868 dev_priv->display.get_initial_plane_config =
17869 i9xx_get_initial_plane_config;
17870 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
17871 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17872 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17874 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17875 dev_priv->display.get_initial_plane_config =
17876 i9xx_get_initial_plane_config;
17877 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
17878 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17879 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17882 if (IS_GEN(dev_priv, 5)) {
17883 dev_priv->display.fdi_link_train = ilk_fdi_link_train;
17884 } else if (IS_GEN(dev_priv, 6)) {
17885 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
17886 } else if (IS_IVYBRIDGE(dev_priv)) {
17887 /* FIXME: detect B0+ stepping and use auto training */
17888 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
17891 if (INTEL_GEN(dev_priv) >= 9)
17892 dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables;
17894 dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables;
17898 void intel_modeset_init_hw(struct drm_i915_private *i915)
17900 struct intel_cdclk_state *cdclk_state =
17901 to_intel_cdclk_state(i915->cdclk.obj.state);
17902 struct intel_dbuf_state *dbuf_state =
17903 to_intel_dbuf_state(i915->dbuf.obj.state);
17905 intel_update_cdclk(i915);
17906 intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
17907 cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;
17909 dbuf_state->enabled_slices = i915->dbuf.enabled_slices;
17912 static int sanitize_watermarks_add_affected(struct drm_atomic_state *state)
17914 struct drm_plane *plane;
17915 struct intel_crtc *crtc;
17917 for_each_intel_crtc(state->dev, crtc) {
17918 struct intel_crtc_state *crtc_state;
17920 crtc_state = intel_atomic_get_crtc_state(state, crtc);
17921 if (IS_ERR(crtc_state))
17922 return PTR_ERR(crtc_state);
17924 if (crtc_state->hw.active) {
17926 * Preserve the inherited flag to avoid
17927 * taking the full modeset path.
17929 crtc_state->inherited = true;
17933 drm_for_each_plane(plane, state->dev) {
17934 struct drm_plane_state *plane_state;
17936 plane_state = drm_atomic_get_plane_state(state, plane);
17937 if (IS_ERR(plane_state))
17938 return PTR_ERR(plane_state);
17945 * Calculate what we think the watermarks should be for the state we've read
17946 * out of the hardware and then immediately program those watermarks so that
17947 * we ensure the hardware settings match our internal state.
17949 * We can calculate what we think WM's should be by creating a duplicate of the
17950 * current state (which was constructed during hardware readout) and running it
17951 * through the atomic check code to calculate new watermark values in the
17954 static void sanitize_watermarks(struct drm_i915_private *dev_priv)
17956 struct drm_atomic_state *state;
17957 struct intel_atomic_state *intel_state;
17958 struct intel_crtc *crtc;
17959 struct intel_crtc_state *crtc_state;
17960 struct drm_modeset_acquire_ctx ctx;
17964 /* Only supported on platforms that use atomic watermark design */
17965 if (!dev_priv->display.optimize_watermarks)
17968 state = drm_atomic_state_alloc(&dev_priv->drm);
17969 if (drm_WARN_ON(&dev_priv->drm, !state))
17972 intel_state = to_intel_atomic_state(state);
17974 drm_modeset_acquire_init(&ctx, 0);
17977 state->acquire_ctx = &ctx;
17980 * Hardware readout is the only time we don't want to calculate
17981 * intermediate watermarks (since we don't trust the current
17984 if (!HAS_GMCH(dev_priv))
17985 intel_state->skip_intermediate_wm = true;
17987 ret = sanitize_watermarks_add_affected(state);
17991 ret = intel_atomic_check(&dev_priv->drm, state);
17995 /* Write calculated watermark values back */
17996 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
17997 crtc_state->wm.need_postvbl_update = true;
17998 dev_priv->display.optimize_watermarks(intel_state, crtc);
18000 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
18004 if (ret == -EDEADLK) {
18005 drm_atomic_state_clear(state);
18006 drm_modeset_backoff(&ctx);
18011 * If we fail here, it means that the hardware appears to be
18012 * programmed in a way that shouldn't be possible, given our
18013 * understanding of watermark requirements. This might mean a
18014 * mistake in the hardware readout code or a mistake in the
18015 * watermark calculations for a given platform. Raise a WARN
18016 * so that this is noticeable.
18018 * If this actually happens, we'll have to just leave the
18019 * BIOS-programmed watermarks untouched and hope for the best.
18021 drm_WARN(&dev_priv->drm, ret,
18022 "Could not determine valid watermarks for inherited state\n");
18024 drm_atomic_state_put(state);
18026 drm_modeset_drop_locks(&ctx);
18027 drm_modeset_acquire_fini(&ctx);
18030 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
18032 if (IS_GEN(dev_priv, 5)) {
18034 intel_de_read(dev_priv, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
18036 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
18037 } else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) {
18038 dev_priv->fdi_pll_freq = 270000;
18043 drm_dbg(&dev_priv->drm, "FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
18046 static int intel_initial_commit(struct drm_device *dev)
18048 struct drm_atomic_state *state = NULL;
18049 struct drm_modeset_acquire_ctx ctx;
18050 struct intel_crtc *crtc;
18053 state = drm_atomic_state_alloc(dev);
18057 drm_modeset_acquire_init(&ctx, 0);
18060 state->acquire_ctx = &ctx;
18062 for_each_intel_crtc(dev, crtc) {
18063 struct intel_crtc_state *crtc_state =
18064 intel_atomic_get_crtc_state(state, crtc);
18066 if (IS_ERR(crtc_state)) {
18067 ret = PTR_ERR(crtc_state);
18071 if (crtc_state->hw.active) {
18072 struct intel_encoder *encoder;
18075 * We've not yet detected sink capabilities
18076 * (audio,infoframes,etc.) and thus we don't want to
18077 * force a full state recomputation yet. We want that to
18078 * happen only for the first real commit from userspace.
18079 * So preserve the inherited flag for the time being.
18081 crtc_state->inherited = true;
18083 ret = drm_atomic_add_affected_planes(state, &crtc->base);
18088 * FIXME hack to force a LUT update to avoid the
18089 * plane update forcing the pipe gamma on without
18090 * having a proper LUT loaded. Remove once we
18091 * have readout for pipe gamma enable.
18093 crtc_state->uapi.color_mgmt_changed = true;
18095 for_each_intel_encoder_mask(dev, encoder,
18096 crtc_state->uapi.encoder_mask) {
18097 if (encoder->initial_fastset_check &&
18098 !encoder->initial_fastset_check(encoder, crtc_state)) {
18099 ret = drm_atomic_add_affected_connectors(state,
18108 ret = drm_atomic_commit(state);
18111 if (ret == -EDEADLK) {
18112 drm_atomic_state_clear(state);
18113 drm_modeset_backoff(&ctx);
18117 drm_atomic_state_put(state);
18119 drm_modeset_drop_locks(&ctx);
18120 drm_modeset_acquire_fini(&ctx);
18125 static void intel_mode_config_init(struct drm_i915_private *i915)
18127 struct drm_mode_config *mode_config = &i915->drm.mode_config;
18129 drm_mode_config_init(&i915->drm);
18130 INIT_LIST_HEAD(&i915->global_obj_list);
18132 mode_config->min_width = 0;
18133 mode_config->min_height = 0;
18135 mode_config->preferred_depth = 24;
18136 mode_config->prefer_shadow = 1;
18138 mode_config->allow_fb_modifiers = true;
18140 mode_config->funcs = &intel_mode_funcs;
18142 if (INTEL_GEN(i915) >= 9)
18143 mode_config->async_page_flip = true;
18146 * Maximum framebuffer dimensions, chosen to match
18147 * the maximum render engine surface size on gen4+.
18149 if (INTEL_GEN(i915) >= 7) {
18150 mode_config->max_width = 16384;
18151 mode_config->max_height = 16384;
18152 } else if (INTEL_GEN(i915) >= 4) {
18153 mode_config->max_width = 8192;
18154 mode_config->max_height = 8192;
18155 } else if (IS_GEN(i915, 3)) {
18156 mode_config->max_width = 4096;
18157 mode_config->max_height = 4096;
18159 mode_config->max_width = 2048;
18160 mode_config->max_height = 2048;
18163 if (IS_I845G(i915) || IS_I865G(i915)) {
18164 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512;
18165 mode_config->cursor_height = 1023;
18166 } else if (IS_I830(i915) || IS_I85X(i915) ||
18167 IS_I915G(i915) || IS_I915GM(i915)) {
18168 mode_config->cursor_width = 64;
18169 mode_config->cursor_height = 64;
18171 mode_config->cursor_width = 256;
18172 mode_config->cursor_height = 256;
18176 static void intel_mode_config_cleanup(struct drm_i915_private *i915)
18178 intel_atomic_global_obj_cleanup(i915);
18179 drm_mode_config_cleanup(&i915->drm);
18182 static void plane_config_fini(struct intel_initial_plane_config *plane_config)
18184 if (plane_config->fb) {
18185 struct drm_framebuffer *fb = &plane_config->fb->base;
18187 /* We may only have the stub and not a full framebuffer */
18188 if (drm_framebuffer_read_refcount(fb))
18189 drm_framebuffer_put(fb);
18194 if (plane_config->vma)
18195 i915_vma_put(plane_config->vma);
18198 /* part #1: call before irq install */
18199 int intel_modeset_init_noirq(struct drm_i915_private *i915)
18203 if (i915_inject_probe_failure(i915))
18206 if (HAS_DISPLAY(i915)) {
18207 ret = drm_vblank_init(&i915->drm,
18208 INTEL_NUM_PIPES(i915));
18213 intel_bios_init(i915);
18215 ret = intel_vga_register(i915);
18219 /* FIXME: completely on the wrong abstraction layer */
18220 intel_power_domains_init_hw(i915, false);
18222 intel_csr_ucode_init(i915);
18224 i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
18225 i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
18226 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
18228 intel_mode_config_init(i915);
18230 ret = intel_cdclk_init(i915);
18232 goto cleanup_vga_client_pw_domain_csr;
18234 ret = intel_dbuf_init(i915);
18236 goto cleanup_vga_client_pw_domain_csr;
18238 ret = intel_bw_init(i915);
18240 goto cleanup_vga_client_pw_domain_csr;
18242 init_llist_head(&i915->atomic_helper.free_list);
18243 INIT_WORK(&i915->atomic_helper.free_work,
18244 intel_atomic_helper_free_state_worker);
18246 intel_init_quirks(i915);
18248 intel_fbc_init(i915);
18252 cleanup_vga_client_pw_domain_csr:
18253 intel_csr_ucode_fini(i915);
18254 intel_power_domains_driver_remove(i915);
18255 intel_vga_unregister(i915);
18257 intel_bios_driver_remove(i915);
18262 /* part #2: call after irq install, but before gem init */
18263 int intel_modeset_init_nogem(struct drm_i915_private *i915)
18265 struct drm_device *dev = &i915->drm;
18267 struct intel_crtc *crtc;
18270 intel_init_pm(i915);
18272 intel_panel_sanitize_ssc(i915);
18274 intel_gmbus_setup(i915);
18276 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n",
18277 INTEL_NUM_PIPES(i915),
18278 INTEL_NUM_PIPES(i915) > 1 ? "s" : "");
18280 if (HAS_DISPLAY(i915)) {
18281 for_each_pipe(i915, pipe) {
18282 ret = intel_crtc_init(i915, pipe);
18284 intel_mode_config_cleanup(i915);
18290 intel_plane_possible_crtcs_init(i915);
18291 intel_shared_dpll_init(dev);
18292 intel_update_fdi_pll_freq(i915);
18294 intel_update_czclk(i915);
18295 intel_modeset_init_hw(i915);
18297 intel_hdcp_component_init(i915);
18299 if (i915->max_cdclk_freq == 0)
18300 intel_update_max_cdclk(i915);
18303 * If the platform has HTI, we need to find out whether it has reserved
18304 * any display resources before we create our display outputs.
18306 if (INTEL_INFO(i915)->display.has_hti)
18307 i915->hti_state = intel_de_read(i915, HDPORT_STATE);
18309 /* Just disable it once at startup */
18310 intel_vga_disable(i915);
18311 intel_setup_outputs(i915);
18313 drm_modeset_lock_all(dev);
18314 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
18315 drm_modeset_unlock_all(dev);
18317 for_each_intel_crtc(dev, crtc) {
18318 struct intel_initial_plane_config plane_config = {};
18324 * Note that reserving the BIOS fb up front prevents us
18325 * from stuffing other stolen allocations like the ring
18326 * on top. This prevents some ugliness at boot time, and
18327 * can even allow for smooth boot transitions if the BIOS
18328 * fb is large enough for the active pipe configuration.
18330 i915->display.get_initial_plane_config(crtc, &plane_config);
18333 * If the fb is shared between multiple heads, we'll
18334 * just get the first one.
18336 intel_find_initial_plane_obj(crtc, &plane_config);
18338 plane_config_fini(&plane_config);
18342 * Make sure hardware watermarks really match the state we read out.
18343 * Note that we need to do this after reconstructing the BIOS fb's
18344 * since the watermark calculation done here will use pstate->fb.
18346 if (!HAS_GMCH(i915))
18347 sanitize_watermarks(i915);
18350 * Force all active planes to recompute their states. So that on
18351 * mode_setcrtc after probe, all the intel_plane_state variables
18352 * are already calculated and there is no assert_plane warnings
18355 ret = intel_initial_commit(dev);
18357 drm_dbg_kms(&i915->drm, "Initial commit in probe failed.\n");
18362 /* part #3: call after gem init */
18363 int intel_modeset_init(struct drm_i915_private *i915)
18367 intel_overlay_setup(i915);
18369 if (!HAS_DISPLAY(i915))
18372 ret = intel_fbdev_init(&i915->drm);
18376 /* Only enable hotplug handling once the fbdev is fully set up. */
18377 intel_hpd_init(i915);
18378 intel_hpd_poll_disable(i915);
18380 intel_init_ipc(i915);
18382 intel_psr_set_force_mode_changed(i915->psr.dp);
18387 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
18389 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18390 /* 640x480@60Hz, ~25175 kHz */
18391 struct dpll clock = {
18401 drm_WARN_ON(&dev_priv->drm,
18402 i9xx_calc_dpll_params(48000, &clock) != 25154);
18404 drm_dbg_kms(&dev_priv->drm,
18405 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
18406 pipe_name(pipe), clock.vco, clock.dot);
18408 fp = i9xx_dpll_compute_fp(&clock);
18409 dpll = DPLL_DVO_2X_MODE |
18410 DPLL_VGA_MODE_DIS |
18411 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
18412 PLL_P2_DIVIDE_BY_4 |
18413 PLL_REF_INPUT_DREFCLK |
18416 intel_de_write(dev_priv, FP0(pipe), fp);
18417 intel_de_write(dev_priv, FP1(pipe), fp);
18419 intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
18420 intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
18421 intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
18422 intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
18423 intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
18424 intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
18425 intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
18428 * Apparently we need to have VGA mode enabled prior to changing
18429 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
18430 * dividers, even though the register value does change.
18432 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
18433 intel_de_write(dev_priv, DPLL(pipe), dpll);
18435 /* Wait for the clocks to stabilize. */
18436 intel_de_posting_read(dev_priv, DPLL(pipe));
18439 /* The pixel multiplier can only be updated once the
18440 * DPLL is enabled and the clocks are stable.
18442 * So write it again.
18444 intel_de_write(dev_priv, DPLL(pipe), dpll);
18446 /* We do this three times for luck */
18447 for (i = 0; i < 3 ; i++) {
18448 intel_de_write(dev_priv, DPLL(pipe), dpll);
18449 intel_de_posting_read(dev_priv, DPLL(pipe));
18450 udelay(150); /* wait for warmup */
18453 intel_de_write(dev_priv, PIPECONF(pipe),
18454 PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
18455 intel_de_posting_read(dev_priv, PIPECONF(pipe));
18457 intel_wait_for_pipe_scanline_moving(crtc);
18460 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
18462 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18464 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",
18467 drm_WARN_ON(&dev_priv->drm,
18468 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) &
18469 DISPLAY_PLANE_ENABLE);
18470 drm_WARN_ON(&dev_priv->drm,
18471 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) &
18472 DISPLAY_PLANE_ENABLE);
18473 drm_WARN_ON(&dev_priv->drm,
18474 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) &
18475 DISPLAY_PLANE_ENABLE);
18476 drm_WARN_ON(&dev_priv->drm,
18477 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE);
18478 drm_WARN_ON(&dev_priv->drm,
18479 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE);
18481 intel_de_write(dev_priv, PIPECONF(pipe), 0);
18482 intel_de_posting_read(dev_priv, PIPECONF(pipe));
18484 intel_wait_for_pipe_scanline_stopped(crtc);
18486 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
18487 intel_de_posting_read(dev_priv, DPLL(pipe));
18491 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
18493 struct intel_crtc *crtc;
18495 if (INTEL_GEN(dev_priv) >= 4)
18498 for_each_intel_crtc(&dev_priv->drm, crtc) {
18499 struct intel_plane *plane =
18500 to_intel_plane(crtc->base.primary);
18501 struct intel_crtc *plane_crtc;
18504 if (!plane->get_hw_state(plane, &pipe))
18507 if (pipe == crtc->pipe)
18510 drm_dbg_kms(&dev_priv->drm,
18511 "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
18512 plane->base.base.id, plane->base.name);
18514 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18515 intel_plane_disable_noatomic(plane_crtc, plane);
18519 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
18521 struct drm_device *dev = crtc->base.dev;
18522 struct intel_encoder *encoder;
18524 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
18530 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
18532 struct drm_device *dev = encoder->base.dev;
18533 struct intel_connector *connector;
18535 for_each_connector_on_encoder(dev, &encoder->base, connector)
18541 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
18542 enum pipe pch_transcoder)
18544 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
18545 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
18548 static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc_state)
18550 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
18551 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
18552 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
18554 if (INTEL_GEN(dev_priv) >= 9 ||
18555 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
18556 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
18559 if (transcoder_is_dsi(cpu_transcoder))
18562 val = intel_de_read(dev_priv, reg);
18563 val &= ~HSW_FRAME_START_DELAY_MASK;
18564 val |= HSW_FRAME_START_DELAY(0);
18565 intel_de_write(dev_priv, reg, val);
18567 i915_reg_t reg = PIPECONF(cpu_transcoder);
18570 val = intel_de_read(dev_priv, reg);
18571 val &= ~PIPECONF_FRAME_START_DELAY_MASK;
18572 val |= PIPECONF_FRAME_START_DELAY(0);
18573 intel_de_write(dev_priv, reg, val);
18576 if (!crtc_state->has_pch_encoder)
18579 if (HAS_PCH_IBX(dev_priv)) {
18580 i915_reg_t reg = PCH_TRANSCONF(crtc->pipe);
18583 val = intel_de_read(dev_priv, reg);
18584 val &= ~TRANS_FRAME_START_DELAY_MASK;
18585 val |= TRANS_FRAME_START_DELAY(0);
18586 intel_de_write(dev_priv, reg, val);
18588 enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc);
18589 i915_reg_t reg = TRANS_CHICKEN2(pch_transcoder);
18592 val = intel_de_read(dev_priv, reg);
18593 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
18594 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
18595 intel_de_write(dev_priv, reg, val);
18599 static void intel_sanitize_crtc(struct intel_crtc *crtc,
18600 struct drm_modeset_acquire_ctx *ctx)
18602 struct drm_device *dev = crtc->base.dev;
18603 struct drm_i915_private *dev_priv = to_i915(dev);
18604 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
18606 if (crtc_state->hw.active) {
18607 struct intel_plane *plane;
18609 /* Clear any frame start delays used for debugging left by the BIOS */
18610 intel_sanitize_frame_start_delay(crtc_state);
18612 /* Disable everything but the primary plane */
18613 for_each_intel_plane_on_crtc(dev, crtc, plane) {
18614 const struct intel_plane_state *plane_state =
18615 to_intel_plane_state(plane->base.state);
18617 if (plane_state->uapi.visible &&
18618 plane->base.type != DRM_PLANE_TYPE_PRIMARY)
18619 intel_plane_disable_noatomic(crtc, plane);
18623 * Disable any background color set by the BIOS, but enable the
18624 * gamma and CSC to match how we program our planes.
18626 if (INTEL_GEN(dev_priv) >= 9)
18627 intel_de_write(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe),
18628 SKL_BOTTOM_COLOR_GAMMA_ENABLE | SKL_BOTTOM_COLOR_CSC_ENABLE);
18631 /* Adjust the state of the output pipe according to whether we
18632 * have active connectors/encoders. */
18633 if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc))
18634 intel_crtc_disable_noatomic(crtc, ctx);
18636 if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
18638 * We start out with underrun reporting disabled to avoid races.
18639 * For correct bookkeeping mark this on active crtcs.
18641 * Also on gmch platforms we dont have any hardware bits to
18642 * disable the underrun reporting. Which means we need to start
18643 * out with underrun reporting disabled also on inactive pipes,
18644 * since otherwise we'll complain about the garbage we read when
18645 * e.g. coming up after runtime pm.
18647 * No protection against concurrent access is required - at
18648 * worst a fifo underrun happens which also sets this to false.
18650 crtc->cpu_fifo_underrun_disabled = true;
18652 * We track the PCH trancoder underrun reporting state
18653 * within the crtc. With crtc for pipe A housing the underrun
18654 * reporting state for PCH transcoder A, crtc for pipe B housing
18655 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
18656 * and marking underrun reporting as disabled for the non-existing
18657 * PCH transcoders B and C would prevent enabling the south
18658 * error interrupt (see cpt_can_enable_serr_int()).
18660 if (has_pch_trancoder(dev_priv, crtc->pipe))
18661 crtc->pch_fifo_underrun_disabled = true;
18665 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
18667 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
18670 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
18671 * the hardware when a high res displays plugged in. DPLL P
18672 * divider is zero, and the pipe timings are bonkers. We'll
18673 * try to disable everything in that case.
18675 * FIXME would be nice to be able to sanitize this state
18676 * without several WARNs, but for now let's take the easy
18679 return IS_GEN(dev_priv, 6) &&
18680 crtc_state->hw.active &&
18681 crtc_state->shared_dpll &&
18682 crtc_state->port_clock == 0;
18685 static void intel_sanitize_encoder(struct intel_encoder *encoder)
18687 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
18688 struct intel_connector *connector;
18689 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18690 struct intel_crtc_state *crtc_state = crtc ?
18691 to_intel_crtc_state(crtc->base.state) : NULL;
18693 /* We need to check both for a crtc link (meaning that the
18694 * encoder is active and trying to read from a pipe) and the
18695 * pipe itself being active. */
18696 bool has_active_crtc = crtc_state &&
18697 crtc_state->hw.active;
18699 if (crtc_state && has_bogus_dpll_config(crtc_state)) {
18700 drm_dbg_kms(&dev_priv->drm,
18701 "BIOS has misprogrammed the hardware. Disabling pipe %c\n",
18702 pipe_name(crtc->pipe));
18703 has_active_crtc = false;
18706 connector = intel_encoder_find_connector(encoder);
18707 if (connector && !has_active_crtc) {
18708 drm_dbg_kms(&dev_priv->drm,
18709 "[ENCODER:%d:%s] has active connectors but no active pipe!\n",
18710 encoder->base.base.id,
18711 encoder->base.name);
18713 /* Connector is active, but has no active pipe. This is
18714 * fallout from our resume register restoring. Disable
18715 * the encoder manually again. */
18717 struct drm_encoder *best_encoder;
18719 drm_dbg_kms(&dev_priv->drm,
18720 "[ENCODER:%d:%s] manually disabled\n",
18721 encoder->base.base.id,
18722 encoder->base.name);
18724 /* avoid oopsing in case the hooks consult best_encoder */
18725 best_encoder = connector->base.state->best_encoder;
18726 connector->base.state->best_encoder = &encoder->base;
18728 /* FIXME NULL atomic state passed! */
18729 if (encoder->disable)
18730 encoder->disable(NULL, encoder, crtc_state,
18731 connector->base.state);
18732 if (encoder->post_disable)
18733 encoder->post_disable(NULL, encoder, crtc_state,
18734 connector->base.state);
18736 connector->base.state->best_encoder = best_encoder;
18738 encoder->base.crtc = NULL;
18740 /* Inconsistent output/port/pipe state happens presumably due to
18741 * a bug in one of the get_hw_state functions. Or someplace else
18742 * in our code, like the register restore mess on resume. Clamp
18743 * things to off as a safer default. */
18745 connector->base.dpms = DRM_MODE_DPMS_OFF;
18746 connector->base.encoder = NULL;
18749 /* notify opregion of the sanitized encoder state */
18750 intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
18752 if (INTEL_GEN(dev_priv) >= 11)
18753 icl_sanitize_encoder_pll_mapping(encoder);
18756 /* FIXME read out full plane state for all planes */
18757 static void readout_plane_state(struct drm_i915_private *dev_priv)
18759 struct intel_plane *plane;
18760 struct intel_crtc *crtc;
18762 for_each_intel_plane(&dev_priv->drm, plane) {
18763 struct intel_plane_state *plane_state =
18764 to_intel_plane_state(plane->base.state);
18765 struct intel_crtc_state *crtc_state;
18766 enum pipe pipe = PIPE_A;
18769 visible = plane->get_hw_state(plane, &pipe);
18771 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18772 crtc_state = to_intel_crtc_state(crtc->base.state);
18774 intel_set_plane_visible(crtc_state, plane_state, visible);
18776 drm_dbg_kms(&dev_priv->drm,
18777 "[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
18778 plane->base.base.id, plane->base.name,
18779 enableddisabled(visible), pipe_name(pipe));
18782 for_each_intel_crtc(&dev_priv->drm, crtc) {
18783 struct intel_crtc_state *crtc_state =
18784 to_intel_crtc_state(crtc->base.state);
18786 fixup_active_planes(crtc_state);
18790 static void intel_modeset_readout_hw_state(struct drm_device *dev)
18792 struct drm_i915_private *dev_priv = to_i915(dev);
18793 struct intel_cdclk_state *cdclk_state =
18794 to_intel_cdclk_state(dev_priv->cdclk.obj.state);
18795 struct intel_dbuf_state *dbuf_state =
18796 to_intel_dbuf_state(dev_priv->dbuf.obj.state);
18798 struct intel_crtc *crtc;
18799 struct intel_encoder *encoder;
18800 struct intel_connector *connector;
18801 struct drm_connector_list_iter conn_iter;
18802 u8 active_pipes = 0;
18804 for_each_intel_crtc(dev, crtc) {
18805 struct intel_crtc_state *crtc_state =
18806 to_intel_crtc_state(crtc->base.state);
18808 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
18809 intel_crtc_free_hw_state(crtc_state);
18810 intel_crtc_state_reset(crtc_state, crtc);
18812 crtc_state->hw.active = crtc_state->hw.enable =
18813 dev_priv->display.get_pipe_config(crtc, crtc_state);
18815 crtc->base.enabled = crtc_state->hw.enable;
18816 crtc->active = crtc_state->hw.active;
18818 if (crtc_state->hw.active)
18819 active_pipes |= BIT(crtc->pipe);
18821 drm_dbg_kms(&dev_priv->drm,
18822 "[CRTC:%d:%s] hw state readout: %s\n",
18823 crtc->base.base.id, crtc->base.name,
18824 enableddisabled(crtc_state->hw.active));
18827 dev_priv->active_pipes = cdclk_state->active_pipes =
18828 dbuf_state->active_pipes = active_pipes;
18830 readout_plane_state(dev_priv);
18832 intel_dpll_readout_hw_state(dev_priv);
18834 for_each_intel_encoder(dev, encoder) {
18837 if (encoder->get_hw_state(encoder, &pipe)) {
18838 struct intel_crtc_state *crtc_state;
18840 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18841 crtc_state = to_intel_crtc_state(crtc->base.state);
18843 encoder->base.crtc = &crtc->base;
18844 encoder->get_config(encoder, crtc_state);
18845 if (encoder->sync_state)
18846 encoder->sync_state(encoder, crtc_state);
18848 encoder->base.crtc = NULL;
18851 drm_dbg_kms(&dev_priv->drm,
18852 "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
18853 encoder->base.base.id, encoder->base.name,
18854 enableddisabled(encoder->base.crtc),
18858 drm_connector_list_iter_begin(dev, &conn_iter);
18859 for_each_intel_connector_iter(connector, &conn_iter) {
18860 if (connector->get_hw_state(connector)) {
18861 struct intel_crtc_state *crtc_state;
18862 struct intel_crtc *crtc;
18864 connector->base.dpms = DRM_MODE_DPMS_ON;
18866 encoder = intel_attached_encoder(connector);
18867 connector->base.encoder = &encoder->base;
18869 crtc = to_intel_crtc(encoder->base.crtc);
18870 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
18872 if (crtc_state && crtc_state->hw.active) {
18874 * This has to be done during hardware readout
18875 * because anything calling .crtc_disable may
18876 * rely on the connector_mask being accurate.
18878 crtc_state->uapi.connector_mask |=
18879 drm_connector_mask(&connector->base);
18880 crtc_state->uapi.encoder_mask |=
18881 drm_encoder_mask(&encoder->base);
18884 connector->base.dpms = DRM_MODE_DPMS_OFF;
18885 connector->base.encoder = NULL;
18887 drm_dbg_kms(&dev_priv->drm,
18888 "[CONNECTOR:%d:%s] hw state readout: %s\n",
18889 connector->base.base.id, connector->base.name,
18890 enableddisabled(connector->base.encoder));
18892 drm_connector_list_iter_end(&conn_iter);
18894 for_each_intel_crtc(dev, crtc) {
18895 struct intel_bw_state *bw_state =
18896 to_intel_bw_state(dev_priv->bw_obj.state);
18897 struct intel_crtc_state *crtc_state =
18898 to_intel_crtc_state(crtc->base.state);
18899 struct intel_plane *plane;
18902 if (crtc_state->hw.active) {
18903 struct drm_display_mode *mode = &crtc_state->hw.mode;
18905 intel_mode_from_pipe_config(&crtc_state->hw.adjusted_mode,
18908 *mode = crtc_state->hw.adjusted_mode;
18909 mode->hdisplay = crtc_state->pipe_src_w;
18910 mode->vdisplay = crtc_state->pipe_src_h;
18913 * The initial mode needs to be set in order to keep
18914 * the atomic core happy. It wants a valid mode if the
18915 * crtc's enabled, so we do the above call.
18917 * But we don't set all the derived state fully, hence
18918 * set a flag to indicate that a full recalculation is
18919 * needed on the next commit.
18921 crtc_state->inherited = true;
18923 intel_crtc_compute_pixel_rate(crtc_state);
18925 intel_crtc_update_active_timings(crtc_state);
18927 intel_crtc_copy_hw_to_uapi_state(crtc_state);
18930 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
18931 const struct intel_plane_state *plane_state =
18932 to_intel_plane_state(plane->base.state);
18935 * FIXME don't have the fb yet, so can't
18936 * use intel_plane_data_rate() :(
18938 if (plane_state->uapi.visible)
18939 crtc_state->data_rate[plane->id] =
18940 4 * crtc_state->pixel_rate;
18942 * FIXME don't have the fb yet, so can't
18943 * use plane->min_cdclk() :(
18945 if (plane_state->uapi.visible && plane->min_cdclk) {
18946 if (crtc_state->double_wide ||
18947 INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
18948 crtc_state->min_cdclk[plane->id] =
18949 DIV_ROUND_UP(crtc_state->pixel_rate, 2);
18951 crtc_state->min_cdclk[plane->id] =
18952 crtc_state->pixel_rate;
18954 drm_dbg_kms(&dev_priv->drm,
18955 "[PLANE:%d:%s] min_cdclk %d kHz\n",
18956 plane->base.base.id, plane->base.name,
18957 crtc_state->min_cdclk[plane->id]);
18960 if (crtc_state->hw.active) {
18961 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
18962 if (drm_WARN_ON(dev, min_cdclk < 0))
18966 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
18967 cdclk_state->min_voltage_level[crtc->pipe] =
18968 crtc_state->min_voltage_level;
18970 intel_bw_crtc_update(bw_state, crtc_state);
18972 intel_pipe_config_sanity_check(dev_priv, crtc_state);
18977 get_encoder_power_domains(struct drm_i915_private *dev_priv)
18979 struct intel_encoder *encoder;
18981 for_each_intel_encoder(&dev_priv->drm, encoder) {
18982 struct intel_crtc_state *crtc_state;
18984 if (!encoder->get_power_domains)
18988 * MST-primary and inactive encoders don't have a crtc state
18989 * and neither of these require any power domain references.
18991 if (!encoder->base.crtc)
18994 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
18995 encoder->get_power_domains(encoder, crtc_state);
18999 static void intel_early_display_was(struct drm_i915_private *dev_priv)
19002 * Display WA #1185 WaDisableDARBFClkGating:cnl,glk,icl,ehl,tgl
19003 * Also known as Wa_14010480278.
19005 if (IS_GEN_RANGE(dev_priv, 10, 12) || IS_GEMINILAKE(dev_priv))
19006 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0,
19007 intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS);
19009 if (IS_HASWELL(dev_priv)) {
19011 * WaRsPkgCStateDisplayPMReq:hsw
19012 * System hang if this isn't done before disabling all planes!
19014 intel_de_write(dev_priv, CHICKEN_PAR1_1,
19015 intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
19018 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) {
19019 /* Display WA #1142:kbl,cfl,cml */
19020 intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
19021 KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22);
19022 intel_de_rmw(dev_priv, CHICKEN_MISC_2,
19023 KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14,
19024 KBL_ARB_FILL_SPARE_14);
19028 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
19029 enum port port, i915_reg_t hdmi_reg)
19031 u32 val = intel_de_read(dev_priv, hdmi_reg);
19033 if (val & SDVO_ENABLE ||
19034 (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
19037 drm_dbg_kms(&dev_priv->drm,
19038 "Sanitizing transcoder select for HDMI %c\n",
19041 val &= ~SDVO_PIPE_SEL_MASK;
19042 val |= SDVO_PIPE_SEL(PIPE_A);
19044 intel_de_write(dev_priv, hdmi_reg, val);
19047 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
19048 enum port port, i915_reg_t dp_reg)
19050 u32 val = intel_de_read(dev_priv, dp_reg);
19052 if (val & DP_PORT_EN ||
19053 (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
19056 drm_dbg_kms(&dev_priv->drm,
19057 "Sanitizing transcoder select for DP %c\n",
19060 val &= ~DP_PIPE_SEL_MASK;
19061 val |= DP_PIPE_SEL(PIPE_A);
19063 intel_de_write(dev_priv, dp_reg, val);
19066 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
19069 * The BIOS may select transcoder B on some of the PCH
19070 * ports even it doesn't enable the port. This would trip
19071 * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
19072 * Sanitize the transcoder select bits to prevent that. We
19073 * assume that the BIOS never actually enabled the port,
19074 * because if it did we'd actually have to toggle the port
19075 * on and back off to make the transcoder A select stick
19076 * (see. intel_dp_link_down(), intel_disable_hdmi(),
19077 * intel_disable_sdvo()).
19079 ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
19080 ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
19081 ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
19083 /* PCH SDVOB multiplex with HDMIB */
19084 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
19085 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
19086 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
19089 /* Scan out the current hw modeset state,
19090 * and sanitizes it to the current state
19093 intel_modeset_setup_hw_state(struct drm_device *dev,
19094 struct drm_modeset_acquire_ctx *ctx)
19096 struct drm_i915_private *dev_priv = to_i915(dev);
19097 struct intel_encoder *encoder;
19098 struct intel_crtc *crtc;
19099 intel_wakeref_t wakeref;
19101 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
19103 intel_early_display_was(dev_priv);
19104 intel_modeset_readout_hw_state(dev);
19106 /* HW state is read out, now we need to sanitize this mess. */
19108 /* Sanitize the TypeC port mode upfront, encoders depend on this */
19109 for_each_intel_encoder(dev, encoder) {
19110 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
19112 /* We need to sanitize only the MST primary port. */
19113 if (encoder->type != INTEL_OUTPUT_DP_MST &&
19114 intel_phy_is_tc(dev_priv, phy))
19115 intel_tc_port_sanitize(enc_to_dig_port(encoder));
19118 get_encoder_power_domains(dev_priv);
19120 if (HAS_PCH_IBX(dev_priv))
19121 ibx_sanitize_pch_ports(dev_priv);
19124 * intel_sanitize_plane_mapping() may need to do vblank
19125 * waits, so we need vblank interrupts restored beforehand.
19127 for_each_intel_crtc(&dev_priv->drm, crtc) {
19128 struct intel_crtc_state *crtc_state =
19129 to_intel_crtc_state(crtc->base.state);
19131 drm_crtc_vblank_reset(&crtc->base);
19133 if (crtc_state->hw.active)
19134 intel_crtc_vblank_on(crtc_state);
19137 intel_sanitize_plane_mapping(dev_priv);
19139 for_each_intel_encoder(dev, encoder)
19140 intel_sanitize_encoder(encoder);
19142 for_each_intel_crtc(&dev_priv->drm, crtc) {
19143 struct intel_crtc_state *crtc_state =
19144 to_intel_crtc_state(crtc->base.state);
19146 intel_sanitize_crtc(crtc, ctx);
19147 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
19150 intel_modeset_update_connector_atomic_state(dev);
19152 intel_dpll_sanitize_state(dev_priv);
19154 if (IS_G4X(dev_priv)) {
19155 g4x_wm_get_hw_state(dev_priv);
19156 g4x_wm_sanitize(dev_priv);
19157 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
19158 vlv_wm_get_hw_state(dev_priv);
19159 vlv_wm_sanitize(dev_priv);
19160 } else if (INTEL_GEN(dev_priv) >= 9) {
19161 skl_wm_get_hw_state(dev_priv);
19162 } else if (HAS_PCH_SPLIT(dev_priv)) {
19163 ilk_wm_get_hw_state(dev_priv);
19166 for_each_intel_crtc(dev, crtc) {
19167 struct intel_crtc_state *crtc_state =
19168 to_intel_crtc_state(crtc->base.state);
19171 put_domains = modeset_get_crtc_power_domains(crtc_state);
19172 if (drm_WARN_ON(dev, put_domains))
19173 modeset_put_power_domains(dev_priv, put_domains);
19176 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
19179 void intel_display_resume(struct drm_device *dev)
19181 struct drm_i915_private *dev_priv = to_i915(dev);
19182 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
19183 struct drm_modeset_acquire_ctx ctx;
19186 dev_priv->modeset_restore_state = NULL;
19188 state->acquire_ctx = &ctx;
19190 drm_modeset_acquire_init(&ctx, 0);
19193 ret = drm_modeset_lock_all_ctx(dev, &ctx);
19194 if (ret != -EDEADLK)
19197 drm_modeset_backoff(&ctx);
19201 ret = __intel_display_resume(dev, state, &ctx);
19203 intel_enable_ipc(dev_priv);
19204 drm_modeset_drop_locks(&ctx);
19205 drm_modeset_acquire_fini(&ctx);
19208 drm_err(&dev_priv->drm,
19209 "Restoring old state failed with %i\n", ret);
19211 drm_atomic_state_put(state);
19214 static void intel_hpd_poll_fini(struct drm_i915_private *i915)
19216 struct intel_connector *connector;
19217 struct drm_connector_list_iter conn_iter;
19219 /* Kill all the work that may have been queued by hpd. */
19220 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
19221 for_each_intel_connector_iter(connector, &conn_iter) {
19222 if (connector->modeset_retry_work.func)
19223 cancel_work_sync(&connector->modeset_retry_work);
19224 if (connector->hdcp.shim) {
19225 cancel_delayed_work_sync(&connector->hdcp.check_work);
19226 cancel_work_sync(&connector->hdcp.prop_work);
19229 drm_connector_list_iter_end(&conn_iter);
19232 /* part #1: call before irq uninstall */
19233 void intel_modeset_driver_remove(struct drm_i915_private *i915)
19235 flush_workqueue(i915->flip_wq);
19236 flush_workqueue(i915->modeset_wq);
19238 flush_work(&i915->atomic_helper.free_work);
19239 drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list));
19242 /* part #2: call after irq uninstall */
19243 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915)
19246 * Due to the hpd irq storm handling the hotplug work can re-arm the
19247 * poll handlers. Hence disable polling after hpd handling is shut down.
19249 intel_hpd_poll_fini(i915);
19252 * MST topology needs to be suspended so we don't have any calls to
19253 * fbdev after it's finalized. MST will be destroyed later as part of
19254 * drm_mode_config_cleanup()
19256 intel_dp_mst_suspend(i915);
19258 /* poll work can call into fbdev, hence clean that up afterwards */
19259 intel_fbdev_fini(i915);
19261 intel_unregister_dsm_handler();
19263 intel_fbc_global_disable(i915);
19265 /* flush any delayed tasks or pending work */
19266 flush_scheduled_work();
19268 intel_hdcp_component_fini(i915);
19270 intel_mode_config_cleanup(i915);
19272 intel_overlay_cleanup(i915);
19274 intel_gmbus_teardown(i915);
19276 destroy_workqueue(i915->flip_wq);
19277 destroy_workqueue(i915->modeset_wq);
19279 intel_fbc_cleanup_cfb(i915);
19282 /* part #3: call after gem init */
19283 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915)
19285 intel_csr_ucode_fini(i915);
19287 intel_power_domains_driver_remove(i915);
19289 intel_vga_unregister(i915);
19291 intel_bios_driver_remove(i915);
19294 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
19296 struct intel_display_error_state {
19298 u32 power_well_driver;
19300 struct intel_cursor_error_state {
19305 } cursor[I915_MAX_PIPES];
19307 struct intel_pipe_error_state {
19308 bool power_domain_on;
19311 } pipe[I915_MAX_PIPES];
19313 struct intel_plane_error_state {
19321 } plane[I915_MAX_PIPES];
19323 struct intel_transcoder_error_state {
19325 bool power_domain_on;
19326 enum transcoder cpu_transcoder;
19339 struct intel_display_error_state *
19340 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
19342 struct intel_display_error_state *error;
19343 int transcoders[] = {
19352 BUILD_BUG_ON(ARRAY_SIZE(transcoders) != ARRAY_SIZE(error->transcoder));
19354 if (!HAS_DISPLAY(dev_priv))
19357 error = kzalloc(sizeof(*error), GFP_ATOMIC);
19361 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
19362 error->power_well_driver = intel_de_read(dev_priv,
19363 HSW_PWR_WELL_CTL2);
19365 for_each_pipe(dev_priv, i) {
19366 error->pipe[i].power_domain_on =
19367 __intel_display_power_is_enabled(dev_priv,
19368 POWER_DOMAIN_PIPE(i));
19369 if (!error->pipe[i].power_domain_on)
19372 error->cursor[i].control = intel_de_read(dev_priv, CURCNTR(i));
19373 error->cursor[i].position = intel_de_read(dev_priv, CURPOS(i));
19374 error->cursor[i].base = intel_de_read(dev_priv, CURBASE(i));
19376 error->plane[i].control = intel_de_read(dev_priv, DSPCNTR(i));
19377 error->plane[i].stride = intel_de_read(dev_priv, DSPSTRIDE(i));
19378 if (INTEL_GEN(dev_priv) <= 3) {
19379 error->plane[i].size = intel_de_read(dev_priv,
19381 error->plane[i].pos = intel_de_read(dev_priv,
19384 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
19385 error->plane[i].addr = intel_de_read(dev_priv,
19387 if (INTEL_GEN(dev_priv) >= 4) {
19388 error->plane[i].surface = intel_de_read(dev_priv,
19390 error->plane[i].tile_offset = intel_de_read(dev_priv,
19394 error->pipe[i].source = intel_de_read(dev_priv, PIPESRC(i));
19396 if (HAS_GMCH(dev_priv))
19397 error->pipe[i].stat = intel_de_read(dev_priv,
19401 for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
19402 enum transcoder cpu_transcoder = transcoders[i];
19404 if (!HAS_TRANSCODER(dev_priv, cpu_transcoder))
19407 error->transcoder[i].available = true;
19408 error->transcoder[i].power_domain_on =
19409 __intel_display_power_is_enabled(dev_priv,
19410 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
19411 if (!error->transcoder[i].power_domain_on)
19414 error->transcoder[i].cpu_transcoder = cpu_transcoder;
19416 error->transcoder[i].conf = intel_de_read(dev_priv,
19417 PIPECONF(cpu_transcoder));
19418 error->transcoder[i].htotal = intel_de_read(dev_priv,
19419 HTOTAL(cpu_transcoder));
19420 error->transcoder[i].hblank = intel_de_read(dev_priv,
19421 HBLANK(cpu_transcoder));
19422 error->transcoder[i].hsync = intel_de_read(dev_priv,
19423 HSYNC(cpu_transcoder));
19424 error->transcoder[i].vtotal = intel_de_read(dev_priv,
19425 VTOTAL(cpu_transcoder));
19426 error->transcoder[i].vblank = intel_de_read(dev_priv,
19427 VBLANK(cpu_transcoder));
19428 error->transcoder[i].vsync = intel_de_read(dev_priv,
19429 VSYNC(cpu_transcoder));
19435 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
19438 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
19439 struct intel_display_error_state *error)
19441 struct drm_i915_private *dev_priv = m->i915;
19447 err_printf(m, "Num Pipes: %d\n", INTEL_NUM_PIPES(dev_priv));
19448 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
19449 err_printf(m, "PWR_WELL_CTL2: %08x\n",
19450 error->power_well_driver);
19451 for_each_pipe(dev_priv, i) {
19452 err_printf(m, "Pipe [%d]:\n", i);
19453 err_printf(m, " Power: %s\n",
19454 onoff(error->pipe[i].power_domain_on));
19455 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
19456 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
19458 err_printf(m, "Plane [%d]:\n", i);
19459 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
19460 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
19461 if (INTEL_GEN(dev_priv) <= 3) {
19462 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
19463 err_printf(m, " POS: %08x\n", error->plane[i].pos);
19465 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
19466 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
19467 if (INTEL_GEN(dev_priv) >= 4) {
19468 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
19469 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
19472 err_printf(m, "Cursor [%d]:\n", i);
19473 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
19474 err_printf(m, " POS: %08x\n", error->cursor[i].position);
19475 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
19478 for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
19479 if (!error->transcoder[i].available)
19482 err_printf(m, "CPU transcoder: %s\n",
19483 transcoder_name(error->transcoder[i].cpu_transcoder));
19484 err_printf(m, " Power: %s\n",
19485 onoff(error->transcoder[i].power_domain_on));
19486 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
19487 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
19488 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
19489 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
19490 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
19491 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
19492 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);